SFP HSMC User Manual
Contents
1. ter www terasic com SFP HSMC Terasic SFP Board User Manual Preliminary Version 2009 by lerasic INTRODUC TION naa an non anna 1 1 1 UN uc Na 1 1 2 T2 Na EN AN 2 1 3 1 3 ASSEMBLE THE SFP HSMC ear aa 3 1 4 1 4 GETTING 5 AR HE CU RE in ea 6 2 1 2 1 LAYOUT AND 6 2 2 8 BOARD CO enim ENT E 9 3 1 PAE SEP me 9 9 3 2 PN 15 3 3 17 5 18 4 1 AA ITO IG TION Mem 18 4 2 4 2 SYSTEM REQUIREMENTS cscccccccccsccccccaccccccccsceccccusceccccussececcuaucececcusceccceuuuceccecsuuceecceuuuceececuuuceceecuacececcuaeeeecens 18 4 3 43 SETUP THE DEMONSTRATION an an ana nana ngan ai mia son bana nanda mana mei 18 4 4 PER ATOM 20 4 5 mellis 21 APPEND 23 5 1 DI REAGON AN NE cinerea MN GA NIAS AS IA AE TEA 23 5 2 5 2 ALWAYS VISIT SFP WEBPAGE FOR NEW MAIN BOARD ssccccceeccccsccccccceccccucccccucccecseccccanececeaesceeueececeues 23 CHAPTER 1 Introduction The Small Form Factor Pluggable2. Dip Switch PLL 4 1 Input Multiplexer I Dip Switch PLL 4 1 Input Multiplexer XCVR RX4n XCVR RX4p SMA CLK1 CLK2 SMA p gt SMA n CLK2 SMA n SMA CLK p Dip Switch LVDS SFP Dip Switch XCVR SFP 935 LVDS SFP7 LVDS LVDS LVDS channel SFP6 SFP5 SFP4 channel channel channel Figure 2 1 The SFP HSMC PCB and component diagram 6 HSMC Connector XCVR SFPO XCVR SFP1 XCVR SFP2 XCVR SFP3 Figure 2 2 The SFP HSMC Back side connector view The following components are provided on the SFP HSMC board e LVDS SFP 4 7 J10 XCVR SFP Dip Switch 55 XCVR LVDS Dip Switch S4 CLK2 SMA p 14 CLK2 SMA n J15 SMA CLK1 J9 PLL 4 1 Input Multiplexer Dip Switch S3 PLL 4 1 Input Multiplexer Dip Switch S2 SMA REFCLK J11 SMA REFCLK n J8 SMA REFCLK p J4 CLOCK Dip Switch S1 XCVR TX4n J5 XOVR TX4p J1 XCVR_TX4n J6 XCVR RX4p J2 SMA J7 SMA J3 Connector J17 XCVR SFP O0 3 J16 2 2 Block Diagram Figure 2 3 shows the block diagram of the SFP HSMC board XCVRTX4p TX3p n Transceiver Based RX3p n Transceiver Based XCVR Based SFP3 XCVR TX4n SFP3 Control Siganls TX2p n Transceiver Based SMA REFCLK XCVRAX4p E RX2p n Transceiver Based XCVR Based SEP SFP2 Control
3. Power Power Output Input Output Input Power Power Output Input Output Input Power Power Input Input Output Input Power Power Inout Output Input Output Power Power Input Input Output Inout Power Rate Select Power 3 3V Power 12V Receiver Loss of Signal Indication Module Transmitter Fault Transmitter Disable Turns off transmitter laser output SDA Serial Data Signal Power 3 3V Power 12V SCL Serial Clock Signal LED indicator that the module is present Rate Select Receiver Loss of Signal Indication Power 3 3V Power 12V Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Power 3 3V Power 12V Module Transmitter Fault Differential Clock Input Transmitter Disable Turns off transmitter laser output Differential Clock Input Power 3 3V Power 12V SDA Serial Data Signal SCL Serial Clock Signal LED indicator that the module is present Rate Select Power 3 3V Power 12V Receiver Loss of Signal Indication Module Transmitter Fault Transmitter Disable Turns off transmitter laser output SDA Serial Data Signal Power 3 3V 13 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 12V SFP5 TDp SFP5 RDp SFP5 TDn SFP5 RDn 3V3 12V SFP5 MOD1 SCL SFP5 MODO PRSNTn SFP5 RATESEL SFP5 LOS 3V3 12V SFP6 T
4. SW2 to the 0 position Power on the Stratix IV GX FPGA Development Board and download the SOF file hsmc_loopback sof Press and release CPU reset button located on the host board to initiate the test Press and release PBO enabling comma detect Press and release PB1 enabling channel bonding Press and release PB2 start transmitting PRBS data LEDO LED1 and LED2 should ON and LED3 should be OFF Remove one of the SFP modules or one side of a connector so that the loopback will fail Failure is indicated on the Stratix IV GX FPGA Dev Kit when LEDS turns ON To reset the board test system press and release the CPU reset button on the host board Press and release PB1 and PB2 at the same time creates an error in the transmitter data stream where LED3 should be ON Press and release the CPU reset button on the host board and verify the results LVDS Loopback Test Demo Project directory sfp hsmb s4gx pcie Ivds loopback restored Bit Stream used hsmc loopback sof SFP HSMC Setup v nsert SFP modules with loopback connectors into SFP ports 4 7 on the SFP board v Set SWA switches on the SFP all to the 1 position Stratix IV GX FPGA Development Kit Setup v Set SWS switches 1 4 amp 6 8 in the down position v Set SW3 switch 5 in the up position v Set SWA switches 1 2 4 in the up position and switches 3 5 6 8 in the down position 20 v Setthe rotary switch SW2 to the 0 positi
5. Transceiver Input SMA Transceiver Output Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Not Connect Not Connect Not Connect 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 N C JTAG TDO TDI JTAG TDO TDI N C N C SEL O SEL 1 SEL 2 SEL 3 3V3 12V SFP3 TXFAULT SFP3 TXDISABLE SFP3 MOD2 SDA SFP3 MOD1 SCL 3V3 12V SFP3 MODO PRSNTn SFP3 RATESEL SFP3 LOS SFP2 TXFAULT 3V3 12V SFP2 TXDISABLE SFP2 MOD2 SDA SFP2 MOD1 SCL SFP2 MODO PRSNTn 3V3 12V SFP2 RATESEL SFP2 LOS SFP1 TXFAULT SFP1 TXDISABLE 3V3 12V SFP1 MOD2 SDA SFP1 MOD1 SCL SFP1 MODO PRSNTn N A Inout Inout N A N A Inout Inout Inout Inout Power Power Input Output Input Inout Power Power Input Output Input Input Power Power Output Inout Output Input Power Power Output Input Input Output Power Power Inout Output Input Not Connect JTAG data loo
6. for users to provide a basic introduction to the SFP daughter board with the procedure to control different hardware and software settings 4 2 System Requirements The following items are required for the HSMC DVI Server demonstration SFP HSMC x 1 Stratix IV GX FPGA Development Board x 1 SFP Loopback Connectors x 4 4 3 Setup the Demonstration Figure 4 3 and 4 4 shows how to setup hardware for the SFP HSMC demonstration 18 Figure 4 3 Transceiver Loopback Test Setup Figure 4 4 LVDS Loopback Test Setup Note The SFP board must be connected to Slot of the Stratix IV GX FPGA Development Board for this demonstration 19 4 4 Demo Operation This section describes the procedures of running the demonstration FPGA Configuration Demonstration Setup File Locations and Instructions Transceiver Loopback Test Demo Project directory sfp hsmb s4gx pcie xcvr loopback 6p25Gbps restored Bit Stream used hsmc loopback sof SFP HSMC Setup v nsert SFP modules with loopback connectors into SFP ports 0 3 on the SFP HSMC board v Set SW5 switches on the SFP all to the 0 position Stratix IV GX FPGA Development Kit Setup v Set SW3 switches 1 3 amp 5 8 in the down position v Set SW3 switch 4 in the up position v Set SWA switches 1 2 4 in the up position and switches 3 5 6 8 in the down position v Setthe rotary switch
7. Dp SFP6 RDp SFP6 TDn SFP6 RDn 3V3 12V SFP6 TXFAULT SFP6 TXDISABLE SFP6 MOD2 SDA SFP6 MOD1 SCL 3V3 12V SFP6 MODO PRSNTn SFP6 RATESEL SFP6 LOS SFP7 TXFAULT 3V3 12V SFP7 TDp SFP7 RDp SFP7 TDn SFP7 RDn 3V3 12V SFP7 TXDISABLE Power Output Input Output Input Power Power Output Input Output Input Power Power Output Input Output Input Power Power Input Output Inout Output Power Power Input Output Input Input Power Power Output Input Output Input Power Power Output Power 12V Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Power 3 3V Power 12V SCL Serial Clock Signal Not Connect Rate Select Receiver Loss of Signal Indication Power 3 3V Power 12V Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Power 3 3V Power 12V Module Transmitter Fault Transmitter Disable Turns off transmitter laser output SDA Serial Data Signal SCL Serial Clock Signal Power 3 3V Power 12V LED indicator that the module is present Rate Select Receiver Loss of Signal Indication Module Transmitter Fault Power 3 3V Power 12V Transmitter Non Inverted Data Input Receiver Non Inverted Data Output Transmitter Inverted Data Input Receiver Inverted Data Output Power 3 3V Power 12V Transmitter Disable Turns off transmitter laser output 14 This secti
8. M pin 4S204BGI 155 52MHz LVDS 156 25M pin 156 25MHz LVDS SMA p n ICS8545204BGI Figure 3 2 Clock Diagram Table 3 2 Settings 11 125 00 MHz Default 10 155 52 MHz 01 156 25 MHz 00 61 44 MHz Table 3 3 CLK2 Settings 11 125 00 MHz Default 10 155 52 MHz 01 156 25 MHz 00 SMA CLK p n 3 3 Power Supply This section describes the power supply on the SFI board The SFP HSMC is powered through the HSMC connector s 3 3V and 12V pins The SFP and clocking circuitry requires 3 3V switching regulator powered from the 12 input produces 4V Three linear regulators powered from 4V will produce the 3 3V The switching frequency is set to 1MHz The power distribution network is shown in the figure below Max power consumption is estimated at 1A on 12V Typical power consumption is considerably less than this Linear 3 3V XCVR Bari 12A 3 3V LVDS LVDS Based 12A gt SFPs LIME ILT 3080 Figure 3 3 Power distribution on the SFP HSMC board 17 CHAPTER 4 Demonstration This Chapter illustrates the reference designs for the SFP HSMC board 4 1 Introduction This section describes the functionality of the demonstration briefly The demonstration shows how to run the SFP HSMC loopback test for both Transceiver LVDS based channels using the SFP HSMC daughter board and the Stratix IV GX FPGA Development board The demonstration is intended
9. P5 TDn SFP5 RDn SFP5 MODI SCL SFP5 MODO PRSNTn SFP5 RATESEL SFP5 LOS 12V SFP6 TDp SFP6_RDp SFPG TDn SFP6 RDn 12 SFPG TXFAULT SFPG TXD SABLE SFP amp MOD2 SDA SFP6 MODI SCL 12 SFP6 MODO PRSNTn SFPE RATESEL SFP6 LOS TXFAULT 12Y SFPT TDp SFPT RDp SFP7 TDn RDn 121 SFP7 TXD BABLE SFPT MOD SDA SFP7 MODI SCL SFP7 MODO PRSNTn 12V SFPT RATESEL CLK p SFPT LOS n QSH 060 Figure 3 1 The pin outs on the connector 10 The table 3 1 below lists the signal direction and description WIT o IO IO D o O O lhDh A AAA O N C N C N C N C N C N C N C N C N C N C N C XCVR_TX4p XCVR_RX4p XCVR_TX4n XCVR_RX4n SFP3 TDp SFP3 RDp SFP3 TDn SFP3 RDn SFP2 TDp SFP2 RDp SFP2 TDn SFP2 RDn SFP1 TDp SFP1 RDp SFP1 TDn SFP1 RDn SFPO TDp SFPO RDp SFPO TDn SFPO RDn N C N C N C N A N A N A N A N A N A N A N A N A N A N A N A Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input N A N A N A 11 Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect Not Connect SMA Transceiver Input SMA Transceiver Output SMA
10. SFP HSMC board is a hardware platform for evaluating the interoperation of Altera FPGA specifically Stratix IV GX GX and GX with generic SFP modules optical modules that are of particular importance SGMII Ethernet Fiber channel CPRI OBSAI and SONET Furthermore the SFP HSMC board is intended for customers to implement both telecommunication and data communications applications 1 1 Features Figure 1 1 shows the photo of the SFP HSMC board The important features are listed below 8 SFP Connectors 4 Transceiver Based SFPs v 4 LVDS Bases SFPs 8 SMAs v 2 Transceiver Receive SMAs 2 Transceiver Transmit SMAs 1 LVDS Clock Input SMA pair 2 SMAs 2 Single ended Clock Outputs SMAs 1 LVDS Clock Output SMA pair 2 SMAs 1 LVPECL Clock Output SMA pair 2 SMAs e Power v 12Vto4V v 4 103 3 Ss 5 5 5 5 e Clocks v 61 44 MHz v 125 MHz 155 52 MHz v 156 25 MHz Differential SMA e High Speed Mezzanine Card Figure 1 1 The SFP HSMC Board 1 2 About the KIT This section describes the package content SFP Board x 1 e System CD ROM x 1 The CD contains technical documents of the SFP HSMC and reference designs along with the source code Figure 1 2 SFP HSMC Package 1 3 Assemble the SFP Board This section describes how to connect the SFP board to main board The SFP HSMC board connects with Altera DE3 Boa
11. Siganls TX1p n Transceiver Based RX1p n Transceiver Based XCVR Based lt SFP1 Control Siganis Single Ended 4 TXOp n Transceiver Based ICS843030 01 RXOp n Transceiver Based SFPO Control Siganls SEL 1 0 CLK1 p n RX4p n LVDS Based Single Ended SFP4 Control Siganls XCVR Based SFPO Soh SMA REFCLK CLK1 125M p n CLK1 155 52M p n CLK1 156 25M p n 4 61M p n SY89547LMGTR 61 44MHz LVDS LVDS Based SFP4 5 TX5p n LVDS Based RXSp n LVDS Based SFP5 Control Siganls 5 TX6p n LVDS Based RX6p n LVDS Based SFP6 Control Siganls 5 TX7p n LVDS Based RX7p n LVDS Based SFP7 Control Siganls 5 LVDS Based SFP5 LVDS Based SFP6 SEL 3 2 CLK2 125M p n CLK2 p n CLK2 155 52M p n CLK2 156 25M p n SMA CLK p n CLK2 p n SMAs SMA CLK p n CLK1_125M_p n CLK2 125M p n 125M p n e CLK1 155 52M p n 1 55 52M p n CLK2 155 52M p n 125MHz LVDS 155 52MHz LV CLK1 156 25M p n CLK2 156 25M p n 156 25M p n 156 25MHz LVI ICS8545204BGI Figure 2 3 The block diagram of the SFP HSMC board 3 Board Components 2 This section illustrates the detailed information of the components connector interfaces and the pin mapping tables of the SFP HSMC board 3 1 The SFP HSMC Connector This section describes pin definit
12. igned Channel Bonded 1 PRBS Data Received USER LED 2 Test Complete USER LED 93 Error USER LED 15 4 Heartbeat Pattern Board is active 22 CHAPTER Appendix 5 1 Revision History Date Change Log SEPT 4 2009 Initial Version April 20 2013 Modify some board name 5 2 Always Visit SFP HSMC Webpage for New Main board We will be continuing providing interesting examples and labs on our SFP HSMC webpage Please visit www altera com or hsmcsfp terasic com for more information 23
13. ion of the SFP HSMC interface onboard All the control and data signals of the SFPs are connected to the connector so users can fully control the SFP daughter board through the interface Power is derived from 3 3V and 12V of the connector SFP3 ATP SFP2 SFP SFPI SFPI XCYR XCYR XCVR_RX4p XCVR RX4n FP3RDp STP3 RDn SFP2 RDp STP2 RDn STPI RDp 1 TX4n _ 5 TDp SFPO_RDp TDn SFPO RDn JTAG TDO TDI JTAG TDO TDI CLK N CLK1 SEL SELI SEL SEL3 12V SFP3 TXFAULT SFP3 TXD SABLE SFP3 MOD SDA SFP3 MODI SCL 12V SFP3 MODO PRSNTn SFP3 RATESEL SFP3 105 SFP2 TXFAULT 12Y SFP2 TXD BABLE SFP MOD SDA SFP2 MODI SCL SFP2 MODO PRSNTn 12 SFP RATESEL SFP LOS SFPI TXFAULT SFPI TXD SABLE 121 SFP1 MOD SDA SFPI MODI SCL SFPI MODO PRSNTn STPI RATESEL 12V SFPI LOS SFPO TXFAULT SFPO TXD SABLE SFPO 002 SDA 12Y SFPO MODI SCL MODO PRSNTn SFPO RATESEL SFPO LOS F 12V SFP4 TDp SFP4 RDp SFP4 TDn i SFP4 RDn 1 12V SFP4 TXFAULT CLKI SFP4 TXD SABLE i CLK1 n 12V SFP4 MOD SDA SFP4 MODI SCL SFPA MODO PRSNTn 1 SFP4 RATESEL 121 SFP4 LOS y SFP5 TXFAULT SFP5 TXD BABLE SFP5 MOD SDA 12 SFP5 TDp 5 RDp SF
14. on Power on the Stratix IV GX FPGA Development Board and download the SOF file hsmc_loopback sof e Press the CPU reset button located on the host board to initiate the test e Press and release PBO enabling comma detect e Press and release PB1 enabling channel bonding e Press and release PB2 start transmitting PRBS data LEDO LED1 and LED2 should be ON and LEDS should be OFF Remove one of the SFP modules or one side of a connector so that the loopback will fail A Failure is indicated on the Stratix IV GX FPGA Dev Kit when LEDS turns ON To reset the board test system press and release the CPU reset button on the host board e Press and release PB1 and PB2 at the same time creates an error in the transmitter data stream where LED3 should be ON e Press and release the CPU reset button on the host board and verify the results 4 5 Overview This section describes the design concepts for the SFP HSMC demonstration The demonstration is operating on Stratix GX Development Board HSMC Port B interface testing the four Transceiver LVDS channels at 6 25Gbps The transceiver signals HSMB 0 3 on the Stratix IV GX FPGA Development board are looped back through the SFP HSMC daughter board The SFP HSMC board must have SFP modules inserted in SFP 0 3 locations with a loopback from SFP TX to SFP RX on each module Four transceiver channels of pseudo random data are 8B 10B encoded serialized pre emphasized and transmitted out acco
15. on describes the board s clock inputs and outputs 150 SFP7 MOD2 SDA Inout SDA Serial Data Signal 151 SFP7 MOD SCL Output SCL Serial Clock Signal 152 SFP7 MODO PRSNTn Input LED indicator that the module is present 153 3V3 Power Power 3 3V 154 12V Power Power 12V 155 SFP7 RATESEL Output Rate Select 156 CLK2 p Input Differential Clock Input 157 srr LOS Input Receiver Loss of Signal Indication 158 CLK2 n Input Differential Clock Input 159 N C N A Not Connect 160 GND Power Power Ground 3 2 Clock Circuitry LVDS clock frequencies of 61 44MHz 125MHz 155 52MHz or 156 25MHz can be selected for HSMC CLK1p CLK1n CLK1p CLk1n will be converted to a single ended clock signal and output to an SMA LVDS clock frequencies of 125MHz 155 52MHz 156 25MHz SMA be selected for CLK2p CLK2n pins CLK2p CLK2n will also be output directly to SMAs CLK IN is a single ended CMOS signal received by the daughter card from the FPGA and is cleaned up with a frequency synthesizer The cleaned up clock is output to an LVPECL SMA pair 15 SMA REFCLK LVDS to Single Ended 523034507 PLL Clean Up SMA p n SEL 1 0 CLK1 p n 125M LVDS to CLK1 155 52M Single Ended 61M In SY89547LMGTR 61 44MHz LVDS 1 5 CLK1 125M CLK2 125M pin EI Inm pm 55 52M Ph 125MHz LVDS SEL 3 2 Q4 2 125M p n LK2 156 25
16. p through JTAG data loop through Not Connect Not Connect CLK 1 Select bit O CLK 1 Select bit 1 CLK 2 Select bit 2 CLK 2 Select bit 3 Power 3 3V Power 12V Module Transmitter Fault Transmitter Disable Turns off transmitter laser output SDA Serial Data Signal SCL Serial Clock Signal Power 3 3V Power 12V LED indicator that the module is present Rate Select Receiver Loss of Signal Indication Module Transmitter Fault Power 3 3V Power 12V Transmitter Disable Turns off transmitter laser output SDA Serial Data Signal SCL Serial Clock Signal LED indicator that the module is present Power 3 3V Power 12V Rate Select Receiver Loss of Signal Indication Module Transmitter Fault Transmitter Disable Turns off transmitter laser output Power 3 3V Power 12V SDA Serial Data Signal SCL Serial Clock Signal LED indicator that the module is present 12 74 75 76 77 78 79 80 81 82 83 84 85 86 8 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 SFP1 RATESEL 3V3 12V SFP1_LOS SFPO_TXFAULT SFPO TXDISABLE SFPO MOD2 SDA 3V3 12V SFPO_MOD1_SCL SFPO MODO PRSNTn SFPO RATESEL SFPO LOS 3V3 12V SFP4_TDp SFP4 RDp SFP4 TDn 4 RDn 3V3 12V SFP4_TXFAULT CLK1 p SFP4 TXDISABLE CLK1 n 3V3 12V SFP4 MOD2 SDA SFP4 MOD1 SCL SFP4 MODO PRSNTn SFP4 RATESEL 3V3 12V SFP4_LOS SFP5_TXFAULT SFP5_TXDISABLE SFP5 MOD2 SDA 3V3 Output Power Power Input Input Output Inout
17. rd DE Ae 1 i F m 5 sper parecer rere T T o Tut 34 j i I P L F CIVI PPT i 29 Ap The SFP HSMC connects to the Stratix IV GX FPGA Development Board 12222221 1 gt LELAS 23 Et E gt iE E 4 015 154 OWSH 445 2 TLUmMP OY a Note Do not attempt to connect remove the SFP daughter board to from the main board when the power is on or else the hardware could be damaged 1 4 Getting Help Here are some places to get help if you encounter any problem Email to support terasic com Taiwan amp China 886 3 550 8800 Korea 82 2 512 7661 Japan 81 428 77 7000 lt lt lt lt CHAPTER Architecture This Chapter covers the architecture of the SFP HSMC board including its PCB and block diagram 2 1 Layout and Componets The picture of the SFP HSMC board is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the location of the connectors and key components SMA REFCLK SMA REFCLK n SMA REFCLK p Dip Switch Clock Li XCVR
18. rding to the following signals HSMB TX P N 3 0 of the Stratix IV GX device at 6 25Gbps These high speed serial data are then looped back through an external SFP HSMC back to the Stratix IV GX device Through the SFP HSMC board the data is then equalized retimed deserialized word aligned 8B 10B decoded channel bonded and then the four bonded channels are compared against a receive side PRBS generator inside the Stratix IV GX FPGA fabric The demonstration function block diagram is shown below in figure 4 5 21 Sync Pattern Generator PCS word alignment and channel bonding pattern Four SFP HSMC Daughter Card Faur i 1 MUX H 88 108 Serializers HSMB TX P N 3 0 a Encoders PRES Generator p Start TX PRBS 8 Hod 2INSH Four Four Ch 45 1 x anne Word our HSMB RX P N 3 0 Bonder Deserializers Decoders Aligners 6 52 53 Sees Comparator PRES Seed PRES Detector PRBS Generator Data Error Figure 4 5 SFP Transceiver Test Block Diagram Transceiver LVDS Loopback Definitions RESET Resets the Board Test System PBO Enable Comma Detect PB1 Enable Channel Bond PB2 Start Transmitting PRBS data PB1 amp PB2 Pressing PB1 and PB2 at the same time creates and error in the transmitter data stream USER LED 0 PLLs are locked USER LED 1 Pattern Sync Acquired Word al
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