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PCI-6110/6111 User Manual - UCSD Department of Physics

1. eee 4 27 Figure 4 23 UPDATE Input Signal Timing eee 4 28 Figure 4 24 UPDATE Output Signal Timing eee 4 28 Figure 4 25 UISOURCE Signal Timing eene 4 29 Figure 4 26 GPCTRO SOURCE Signal Timing 00 eee 4 30 PCI 6110 6111 User Manual viii ni com Contents Figure 4 27 GPCTRO GATE Signal Timing in Edge Detection Mode 4 31 Figure 4 28 GPCTRO OUT Signal Timing eene 4 31 Figure 4 29 GPCTRI SOURCE Signal Timing eee 4 32 Figure 4 30 GPCTRI GATE Signal Timing in Edge Detection Mode 4 33 Figure 4 31 GPCTRI OUT Signal Timing eerte 4 33 Figure 4 32 GPCTR Timing Summary essere enne ene 4 34 Figure B 1 68 Pin 611X Connector Pin Assignments esse B 2 Tables Table 3 1 Actual Range and Measurement Precision sese 3 3 Table 4 1 Signal Descriptions for I O Connector Pins eeesss 4 3 Table 4 2 I O Signal Summary for the 611X sese 4 6 Table 4 3 Signal Source Types cic ee eid tete tee pide teen eet 4 10 National Instruments Corporation ix PCI 6110 6111 User Manual About This Manual Conventions This manual describes the electrical and mechanical aspects of the 611X family of devices and contains information concerning their operation and programming The 611X family of devices inclu
2. 1 1 1 1 1 1 1 I I i i 2 i 1 I 1 2 1 PCI 6110 6111 User Manual Figure 4 9 Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed This signal has a 450 ns pulse width and is software enabled Figure 4 10 shows the timing for the SCANCLK signal CONVERT fi L8 SCANCLK lt gt lt gt ta 50 to 100 ns tw 450 ns Figure 4 10 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 us and a 1 2 us clock are available for generating a sequence of eight pulses in the hardware strobe mode 4 18 ni com Chapter 4 Signal Connections Figure 4 11 shows the timing for the hardware strobe mode EXTSTROBE signal V OH j j VOL lt gt ty 7 600 ns or 5 us Figure 4 11 EXTSTROBE Signal Timing
3. DGND Input Output PFI5 Update As an input this is one of the PFIs As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated PCI 6110 6111 User Manual 4 4 ni com Chapter 4 Signal Connections Table 4 1 Signal Descriptions for I O Connector Pins Continued Signal Name Reference Direction Description PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs As an output this is the WFTRIG signal In timed analog Output output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is one of the PFIs Output As an output this is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTRO_OUT DGND Output Coun
4. National Instruments Corporation Index description table 4 5 signal summary table 4 7 PFI9 GPCTRO GATE signal description table 4 5 signal summary table 4 7 PFIs programmable function inputs 4 16 to 4 17 connecting to external signal source caution C 5 overview 4 16 to 4 17 questions about C 4 to C 5 signal routing 3 12 timing input connections 4 16 to 4 17 PGIA programmable gain instrumentation amplifier analog input connections 4 8 common mode signal rejection 4 12 differential connections floating signal sources figure 4 12 ground referenced signal sources 4 10 to 4 11 physical specifications A 9 pin assignments figure 4 2 B 2 polarity selection analog input 3 3 posttriggered data acquisition 4 17 power connections 5 V power pins 4 15 self resetting fuse 4 15 power requirement specifications A 9 pretriggered data acquisition 4 17 to 4 18 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier Q questions and answers analog input and output C 2 to C 3 general information C 1 PCI 6110 6111 User Manual Index installation and configuration C 2 timing and digital I O C 3 to C 5 R register level programming 1 4 requirements for getting started 1 2 RTSI clocks 3 12 RTSI trigger lines 3 12 signal connection figure 3 13 specifications A
5. and V input signals are both within 11 V of the channel ground for gain 21 For gain lt 1 the input signals for ACHO can be within 42 V of the channel ground 4 12 ni com Chapter 4 Signal Connections Analog Output Signal Connections The analog output signals are DACOOUT DACIOUT and AOGND DACOOUT is the voltage output signal for analog output channel 0 DACIOUT is the voltage output signal for analog output channel 1 AOGND is the ground reference signal for the analog output channels Figure 4 5 shows how to make analog output connections to the 611X device DACOOUT Lol Channel 0 Load VOUT 0 AOGND Load VOUT 1 oy DAC1OUT lol Channel 1 Analog Output Channels 611X Device Figure 4 5 Analog Output Connections Digital 1 0 Signal Connections The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs National Instruments Corporation 4 13 PCI 6110 6111 User Manual Chapter 4 Signal Connections A Caution Exceeding the maximum input voltage ratings which are listed in Table 4 2 can damage the 611X device and the computer National Instruments is not liable for any damages resulting from such signal connections Figure 4 6 shows signal connec
6. manual See documentation National Instruments Web support D 1 NI DAQ driver software 1 3 to 1 4 NI Developer Zone D 1 noise avoiding 4 35 to 4 36 0 optional equipment 1 5 output characteristic specifications A 5 P PCI 6110 6111 See also hardware overview custom cabling 1 5 optional equipment 1 5 overview 1 1 to 1 2 ni com questions about C 1 to C 5 analog input and output C 2 to C 3 general information C 1 installation and configuration C 2 timing and digital I O C 3 to C 5 requirements for getting started 1 2 software programming choices 1 2 to 1 4 ComponentWorks 1 2 LabVIEW and LabWindows CVI application software 1 3 National Instruments application software 1 2 to 1 3 NI DAQ driver software 1 3 to 1 4 register level programming 1 4 VirtualBench 1 3 unpacking 1 6 PFIO TRIGI signal description table 4 4 signal summary table 4 6 PFII TRIG2 signal description table 4 4 signal summary table 4 6 PFI2 CONVERT signal description table 4 4 signal summary table 4 6 PFI3 GPCTR1 SOURCE signal description table 4 4 signal summary table 4 6 PFI4 GPCTR1_GATE signal description table 4 4 signal summary table 4 6 PFI5 UPDATE signal description table 4 4 signal summary table 4 6 PFI6 WFTRIG signal description table 4 5 signal summary table 4 6 PFI7 STARTSCAN signal description table 4 5 signal summary table 4 7 PFIS GPCTRO SOURCE signal
7. 0 28 mV 75 dB 62 dB 0 5 V 0 05 0 20 mV 75 dB 67 dB 0 5 500 mV 0 05 0 15 mV 75 dB 70 dB 0 6 200 mV 0 05 0 10 mV 75 dB 72 dB 1 0 1 Relative to reading max 2 All input ranges DC to 100 kHz 3 All input ranges DC to 60 Hz 4LSBms not including quantization National Instruments Corporation A 1 PCI 6110 6111 User Manual Appendix A Specifications PCI 6110 6111 User Manual Input coupling DC AC Max working voltage for all analog input channels T3DpUL eerte Should remain within 11 V for ranges 2 x10 V should remain within 42 V for ranges x10 V SAPU eii aem Should remain within 11 V Overvoltage protection 42 V Inputs protected api EE all channels AnpUt zd Ate gp ade all channels FIFO buffer SiZess suens ianei 8 192 samples Data transfers sisir niesi eeens DMA interrupts programmed I O DMA modes eee Scatter gather Accuracy Information See following table A 2 ni com Specifications Appendix A pepueururooo1 eAIojur uomeJqieo JeoK ouQ omnje1oduro uonedqr eo K10358 JO eu19jx9 JO D QF pue o1njeroduro uoneqt eo eu1ojur Jo 2 F UM soqnje1oduroj euorje1odo 103 PASH ae SIMINI juouromseopq sSurpeor ouueqo o 8urs QO Jo SurSeoAv pue Suuouirp oumsse sroquimu poSe1oAy uonelqi eo eurojur ue SuIMO OJ SJUSWOANSVOUT JOJ PILA are sorouInooy 9 0N AU 9p0 0 AU 86070 95 000 0 AU CC0 0 AU 6C AW C0 956800 8S0 0 L
8. In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter DAQ Timing Connections The DAQ timing signals are SCANCLK EXTSTROBE TRIGI TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 8 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 9 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures is included later in this chapter TRIG1 STARTSCAN CONVERT Scan Counter Figure 4 8 Typical Posttriggered Acquisition National Instruments Corporation 4 17 PCI 6110 6111 User Manual Chapter 4 Signal Connections TRIG1 TRIG2 Don t Care A STARTSCAN CONVERT Scan Counter
9. NC AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFIS GPCTR1 SOURCE PFl4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PFIS GPCTRO SOURCE DGND DGND 1 NC on PCI 6111 Figure 4 1 1 0 Connector Pin Assignment for the 611 X Device 4 2 ni com 1 0 Connector Signal Descriptions Chapter 4 Signal Connections Table 4 1 Signal Descriptions for I O Connector Pins Signal Name Reference Direction Description ACH lt 0 3 gt GND Analog Input Channels 0 through 3 ground These pins are the bias current return point for differential measurements ACH lt 2 3 gt GND signals are no connects on the PCI 6111 ACH lt 0 3 gt ACH lt 0 3 gt GND Input Analog Input Channels 0 through 3 These pins are routed to the terminal of the respective channel s amplifier ACH lt 2 3 gt signals are no connects on the PCI 6111 ACH lt 0 3 gt ACH lt 0 3 gt GND Input Analog Input Channels 0 through 3 These pins are routed to the terminal of the respective channel s amplifier ACH 2 3 signals are no connects on the PCI 6111 DACOOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 DACIOUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 AOGND Ana
10. SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Contents About This Manual COnVentlonDs 2 ie ten RR c
11. These connections are designed to enable the 611X device to both control and be controlled by other devices and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the CONVERT signal is shown in Figure 3 11 EE RTSI Trigger lt 0 6 gt gt CONVERT PFI lt 0 9 gt lt Sample Interval Counter TC 3 GPCTRO OUT m d Figure 3 11 CONVERT Signal Routing National Instruments Corporation 3 11 PCI 6110 6111 User Manual Chapter 3 Hardware Overview This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmahle Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of the P
12. note 3 6 below low level analog triggering mode figure 3 7 block diagrams PCI 6110 3 6 PCI 6111 3 7 high hysteresis analog triggering mode figure 3 9 inside region analog triggering mode figure 3 8 PCI 6110 6111 User Manual Index low hysteresis analog triggering mode figure 3 9 specifications A 8 AOGND signal analog output signal connections 4 13 description table 4 3 signal summary table 4 6 B bipolar input 3 3 block diagrams PCI 6110 3 1 PCI 6111 3 2 device configuration 2 2 bus interface specifications A 9 C cables See also I O connectors custom cabling 1 5 field wiring considerations 4 35 to 4 36 optional equipment 1 5 calibration 5 1 to 5 2 external calibration 5 2 loading calibration constants 5 1 to 5 2 self calibration 5 2 clocks device and RTSI 3 12 commonly asked questions See questions and answers common mode signal rejection 4 12 ComponentWorks software 1 2 configuration PCI 6110 6111 2 2 questions about C 2 connectors See I O connectors CONVERT signal input timing figure 4 24 multiplexer for controlling figure 3 11 output timing figure 4 24 signal routing 3 11 to 3 12 PCI 6110 6111 User Manual I 2 timing connections 4 23 to 4 25 counter timer applications C 4 customer education D 1 D DACOOUT signal analog output signal connections 4 13 description table 4 3 signal summary table 4 6 DACIOUT signal analog output signa
13. 2 0 4 0 4 0 6 0 6 0 4 0 100 200 300 400 500 0 100 200 300 400 500 a Dither disabled no averaging b Dither disabled average of 50 acquisitions LSBs LSBs 6 0 6 0 4 0 4 0 2 0 2 0 0 0 0 0 lf 2 0 2 0 Pd 4 0 4 0 6 0 6 0 0 100 200 300 400 500 0 100 200 300 400 500 c Dither enabled no averaging d Dither enabled average of 50 acquisitions Figure 3 3 Effects of Dither on Signal Acquisition Analog Output The 611X device supplies two channels of analog output voltage at the I O connector The range is fixed at bipolar 10 V National Instruments Corporation PCI 6110 6111 User Manual Chapter 3 Hardware Overview Analog Trigger Note The PFIO TRIGI pin is an analog input when configured as an analog trigger Therefore it is susceptible to crosstalk from adjacent pins which can result in false In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence these devices also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFIO TRIGI pin on the I O connector or a postgain signal from the output of the PGIA on any of the channels as shown in Figures 3 4 and 3 5 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the 61 LX device The range for the post PGIA trigger selection is simply the full scale range of the selected
14. 8 S SCANCLK signal description table 4 3 signal summary table 4 6 timing connections 4 18 signal connections analog input 4 8 analog output 4 13 differential measurements 4 10 to 4 12 common mode signal rejection 4 12 connection considerations 4 10 floating signal sources 4 9 4 11 to 4 12 ground referenced signal sources 4 9 4 10 to 4 11 nonreferenced signal sources 4 11 to 4 12 recommended configuration table 4 10 digital I O 4 13 to 4 14 field wiring considerations 4 35 to 4 36 T O connector 4 1 to 4 7 exceeding maximum ratings caution 4 1 I O signal summary table 4 6 to 4 7 pin assignments figure 4 2 B 2 signal descriptions table 4 3 to 4 5 PCI 6110 6111 User Manual l 6 power connections 4 15 RTSI trigger lines 3 11 to 3 13 timing connections 4 15 to 4 35 DAQ timing connections 4 17 to 4 25 AIGATE signal 4 24 to 4 26 CONVERT signal 4 23 to 4 24 EXTSTROBE signal 4 18 to 4 19 SCANCLK signal 4 18 SISOURCE signal 4 25 STARTSCAN signal 4 22 to 4 23 TRIGI signal 4 19 to 4 20 TRIG signal 4 20 to 4 21 typical posttriggered acquisition figure 4 17 typical pretriggered acquisition figure 4 18 general purpose timing signal connections 4 29 to 4 35 FREQ OUT signal 4 35 GPCTRO GATE signal 4 30 to 4 31 GPCTRO OUT signal 4 31 GPCTRO SOURCE signal 4 29 to 4 30 GPCTRO UP DOWN signal 4 31 GPCTR1_GATE signal 4 32 to 4 33 GPCTRI OUT signal 4 33 GPCTRI SOUR
15. GPCTRO SOURCE GPCTRO UP DOWN GPCTRI GATE GPCTRI OUT GPCTR1 SOURCE GPCTRI UP DOWN National Instruments Corporation Glossary first in first out memory buffer FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be read or written For example an analog input FIFO stores the results of A D conversions until the data can be read into system memory Programming the DMA controller and servicing interrupts can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored in the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device frequency output signal feet gate signal general purpose counter signal general purpose counter 0 gate signal general purpose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down signal general purpose counter gate signal general purpose counter output signal general purpose counter clock source signal general purpose counter up down signal G 5 PCI 6110 6111 User Manual Glossary INL VO lou Io kHz LED LSB MB MHz MIO PCI 6110 6111 User Manual hour hexadecimal hertz
16. Instruments documentation xii xiii related documentation xiii dynamic characteristic specifications analog input A 4 analog output A 6 E EEPROM storage of calibration constants 5 1 environment specifications A 9 environmental noise avoiding 4 35 to 4 36 equipment optional 1 5 EXTSTROBE signal description table 4 3 signal summary table 4 6 timing connections 4 18 to 4 19 National Instruments Corporation I 3 Index F field wiring considerations 4 35 to 4 36 floating signal sources description 4 9 differential connections 4 10 to 4 12 recommended configuration table 4 10 FREQ OUT signal description table 4 5 general purpose timing connections 4 35 signal summary table 4 7 frequently asked questions See questions and answers fuse self resetting 4 15 C 1 G general purpose timing signal connections 4 29 to 4 35 FREQ OUT signal 4 35 GPCTRO GATE signal 4 30 to 4 31 GPCTRO OUT signal 4 31 GPCTRO SOURCE signal 4 29 to 4 30 GPCTRO UP DOWN signal 4 31 GPCTRI GATE signal 4 31 to 4 32 GPCTRI OUT signal 4 32 GPCTRI SOURCE signal 4 32 GPCTRI UP DOWN signal 4 34 to 4 35 questions about C 3 to C 4 glitches C 2 GPCTRO GATE signal 4 30 to 4 31 GPCTRO OUT signal description table 4 5 general purpose timing connections 4 31 signal summary table 4 7 GPCTRO SOURCE signal 4 29 to 4 30 GPCTRO UP DOWN signal 4 31 GPCTR1_GATE signal 4 32 to 4 33 GPCTRI OUT signal de
17. analog output waveform generation starts 4 Initiate analog output waveform generation Timing and Digital 1 0 What types of triggering can be hardware implemented on my 611X device Hardware digital and analog triggering are both supported on the 611X device What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement National Instruments Corporation C 3 PCI 6110 6111 User Manual Appendix C Common Questions PCI 6110 6111 User Manual What is the difference in timebases between the Am9513 counter timer and the DAQ STC The DAQ STC based MIO devices have a 20 MHz timebase The Am9513 based MIO devices have a 1 MHz or 5 MHz timebase Will the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs will still run However there are many differences in the counters between the 611X and other devices the counter numbers are different timeba
18. can be used by any of the timing sections of the DAQ STC including the analog input analog output and general purpose counter timer sections For example the analog input section can be configured to acquire n scans after the analog input signal crosses a specific threshold As another example the analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold National Instruments Corporation 3 9 PCI 6110 6111 User Manual Chapter 3 Hardware Overview Digital 1 0 The 611X device contains eight lines of digital I O for general purpose use You can individually software configure each line for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines PCI 6110 6111 User Manual 3 10 ni com Chapter 3 Hardware Overview Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other devices or external circuitry The 611X device uses the RTSI bus to interconnect timing signals between devices and the Programmable Function Input PFI pins on the I O connector to connect the device to external circuitry
19. channel and the resolution is that range divided by 256 triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 1 k source impedance if you plan to enable this input via software Analog Input CHO PGIA Analog Input CH1 PGIA Analog Input CH2 PGIA Analog Input CH3 PGIA PFIO TRIG1 ADC ADC ADC Analog Trigger Circuit DAQ STC PCI 6110 6111 User Manual Figure 3 4 Analog Trigger Block Diagram for the PCI 6110 ni com Chapter 3 Hardware Overview 3 ADC Analog Input PGIA enm Analog Mux Trigger p DAQ STC ADC Circuit Analog Input PGIA CH1 PFIO TRIG1 Figure 3 5 Analog Trigger Block Diagram for the PCI 6111 Five analog triggering modes are available as shown in Figures 3 6 through 3 10 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue as shown in Figure 3 6 HighValue is unused lowValue Trigger at tj Figure 3 6 Below Low Level Analog Triggering Mode National Instruments Corporation 3 7 PCI 6110 6111 User Manual Chapter 3 Hardware Overview In above high level analog tr
20. connector on the 611X device A signal description follows the connector pinouts UN Caution Connections that exceed any of the maximum ratings of input or output signals on the 61 LX device can damage the 611X device and the computer Maximum input ratings for each signal are given in the Protection column of Table 4 2 National Instruments is not liable for any damages resulting from such signal connections National Instruments Corporation 4 1 PCI 6110 6111 User Manual Chapter 4 PCI 6110 6111 User Manual Signal Connections ACHO ACH1 ACH1GND ACH2 ACH3 1 ACHSGND NC NC NC NC NC NC DACOOUT DAC1OUT NC DIO4 DGND DIO1 DIO6 DGND 5 V DGND DGND PFIO TRIG1 PFH TRIG2 DGND 45V DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT oo AB 68 C2 wo 67 C2 N 66 C3 ak 65 C2 o 64 N c 63 mN oo 62 N 61 N o 60 n ol 59 mN A 58 N ev 57 N N 56 n 55 N o 54 c 53 A oo 52 N 51 c o 50 oa 49 A 48 A w 47 a ye 46 un 45 o 44 o 43 42 41 40 39 38 37 36 PO BR OH DM N oo 35 ACHO ACHOGND ACH1 ACH2 1 ACH2GND ACH3 1 NC NC NC NC NC NC
21. device National Instruments Corporation B 1 PCI 6110 6111 User Manual Appendix B Cable Connector Descriptions ACHO ACH1 ACH1GND ACH2 ACH3 1 ACH3GND1 NC NC NC NC NC NC DACOOUT DAC1OUT NC DIO4 DGND DIO1 DIO6 DGND 45V DGND DGND PFIO TRIG1 PFH TRIG2 DGND 45V DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT wo R 68 C2 wo 67 C2 N 66 wo 65 C2 o 64 n c 63 mN oo 62 N 61 N o 60 ye oa 59 no R 58 N wo 57 N N 56 N 55 N o 54 E c 53 ak oo 52 Er NI 51 o 50 E oa 49 A 48 w 47 ye 46 an 45 A o 44 o 43 42 41 40 39 38 37 36 PO oO A OH OM N oo 35 ACHO ACHOGND ACH1 ACH2 1 ACH2GND1 ACH3 1 NC NC NC NC NC NC NC AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFIS GPCTR1 SOURCE PFIA GPCTR1 GATE GPCTR1 OUT DGND PFI7 STARTSCAN PFI8 GPCTRO_SOURCE DGND DGND 1 NC on PCI 6111 PCI 6110 6111 User Manual Figure B 1 68 Pin 611X Connector Pin Assignments B 2 ni com Common Questions This appendix contains a list of commonly asked questions and
22. state at startup Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with the 611X device if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to analog input signal routing to the device although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect analog input signals to the device With this type of wire the signals attached to the ACH and ACH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling National Instruments Corporation 4 35 PCI 6110 6111 User Manual Chapter 4 Signal Connections PCI 6110 6111 User Manual through areas with large magnetic fields or high electromagnetic interference e Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PCI data acquisition system is the video monitor Separate the monitor from the analog signals as much as possible e Thefollowing recommendations apply for all signal connections to the 611X device e Separate the 611X devic
23. to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number analog input analog input gate signal analog input ground signal American National Standards Institute analog output analog output ground signal Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions a signal range that includes both positive and negative values for example 5 V to 5 V G 2 ni com C C CalDAC CH cm CMOS CMRR CONVERT counter timer CTR D D A DAC DACOOUT DACIOUT DAQ National Instruments Corporation Glossary Celsius calibration DAC channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels centimeter complementary metal oxide semiconductor common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB convert signal a circuit that counts external pulses or clock pulses timing counter digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog v
24. which the 611X device analog input signal has its own reference signal or signal return path The 611X channels are always configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA Each differential signal uses two inputs one for the signal and one for its reference signal Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA PCI 6110 6111 User Manual ni com Chapter 4 Signal Connections Differential Connections for Ground Referenced Signal Sources Figure 4 3 shows how to connect a ground referenced signal source to a channel on the 611X device Instrumentation ACHO Amplifier Ground Referenced Y Signal C Source I el ACHO Measured Voltage Mode 3 Noise and cm Ground z Potential TFT 1 O Connector ACHOGND ACHO Connections Shown Figure 4 3 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the 611X device ground shown as V m in Figure 4 3 Differential Connections for Nonreferenced or Floating Signal Sources Figure
25. 11 User Manual Appendix D Technical Support Resources Worldwide Support National Instruments has offices located around the world to help address your support needs You can access our branch office Web sites from the Worldwide Offices section of ni com Branch office Web sites provide up to date contact information support phone numbers e mail addresses and current events If you have searched the technical support resources on our Web site and still cannot find the answers you need contact your local office or National Instruments corporate Phone numbers for our worldwide offices are listed at the front of this manual PCI 6110 6111 User Manual D 2 ni com Glossary Prefix Meaning Value p pico 10 2 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 Symbols Numbers 2 degrees gt greater than 2 greater than or equal to less than lt less than or equal to per percent plus or minus positive of or plus negative of or minus Q ohms National Instruments Corporation G 1 PCI 6110 6111 User Manual Glossary 5 V A A AC ACH ACHOGND A D ADC Al AIGATE AIGND ANSI AO AOGND ASIC bipolar PCI 6110 6111 User Manual square root of 5 VDC source signal amperes alternating current analog input channel signal analog input channel ground signal analog to digital analog
26. 4 4 shows how to connect a floating signal source to a channel on the 611X device National Instruments Corporation 4 11 PCI 6110 6111 User Manual Chapter 4 Signal Connections Bias Resistor see text 1 0 Connector ACHO O Instrumentation Floating t Amplifier Signal 100pf wo Source r lo ACHO 4 V Measured Bias m Voltage Current 10nf 5 Return Paths o ACHOGND ACHO Connections Shown Figure 4 4 Differential Input Connections for Nonreferenced Signals Figure 4 4 shows a bias resistor connected between ACHO and the floating signal source ground If you do not use the resistor and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to the respective channel ground Common Mode Signal Rejection Considerations PCI 6110 6111 User Manual Figure 4 3 shows connections for signal sources that are already referenced to some ground point with respect to the 611X device In this case the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device The PGIA can reject common mode signals as long as V
27. 611X device PFI pins PFIO TRIG1 PFI2 CONVERT TRIG1 CONVERT Source Source DGND l O Connector 611X Device Figure 4 7 Timing 1 0 Connections Programmable Function Input Connections PCI 6110 6111 User Manual There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin Be careful not to drive a PFI signal externally when it is configured as an output 4 16 ni com Chapter 4 Signal Connections As an input you can individually configure each PFI for edge or level detection and for polarity selection as well You can use the polarity selection for any of the 13 timing signals but the edge or level detection will depend upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal
28. 8 samples DMA interrupts programmed I O Scatter gather 4 LSB typ 8 LSB max 2 LSB typ 8 LSB max S 5 0 mV max e 0 1 of output range max PCI 6110 6111 User Manual Appendix A Specifications Digital 1 0 PCI 6110 6111 User Manual Voltage Output Ranges s mer n ORE Output coupling eee Output impedance eee Current drive aue Output stability seesss PrOteCtlON sse Dynamic Characteristics Slew Tales esee aia ke Stability Offset temperature coefficient Gain temperature coefficient Internal reference External reference Onboard calibration reference Level acute cette on e Temperature coefficient Long term stability Number of channels Compatibility eese A 6 10 V DC 50 Q 5 5 mA min Any passive load Short circuit to ground OV 300 V us 1 mV m DC to 5 MHz 75 dB DC to 10 kHz 500 pV C 50 ppm C 25 ppm C 5 000 V 2 5 mV actual value stored in EEPROM sans 0 6 ppm C max 6 ppm J1 000 h 8 input output TTL CMOS ni com Timing 1 0 Appendix A Specifications Digital logic levels Level Min Max Input low voltage 0 0 V 0 8 V Input high voltage 2 0 V 5 0 V Input low current Vin 0 V S 320 pA Input high current Vin 5 V 10 pA Out
29. 9 to 4 20 TRIG2 signal input timing figure 4 21 output timing figure 4 21 timing connections 4 20 to 4 21 trigger analog above high level analog triggering mode figure 3 8 avoiding false triggering note 3 6 below low level analog triggering mode figure 3 7 block diagrams PCI 6110 3 6 PCI 6111 3 7 high hysteresis analog triggering mode figure 3 9 inside region analog triggering mode figure 3 8 low hysteresis analog triggering mode figure 3 9 specifications A 8 triggers questions about C 3 PCI 6110 6111 User Manual I 8 specifications analog trigger A 8 digital trigger A 8 U UISOURCE signal 4 28 to 4 29 unpacking PCI 6110 6111 1 6 UPDATE signal input signal timing figure 4 28 output signal timing figure 4 28 timing connections 4 27 to 4 28 V VCC signal table 4 6 VirtualBench software 1 3 voltage output specifications A 6 W waveform generation questions about C 2 waveform generation timing connections 4 26 to 4 29 UISOURCE signal 4 28 to 4 29 UPDATE signal 4 27 to 4 28 WFTRIG signal 4 25 to 4 26 Web support from National Instruments D 1 WFTRIG signal input signal timing figure 4 27 output signal timing figure 4 27 timing connections 4 26 to 4 27 wiring considerations 4 35 to 4 36 worldwide technical support D 2 ni com
30. B typ 0 75 LSB max See table analog input characteristics 11 0 bits DC to 100 kHz See table analog input characteristics 1 MQ in parallel with 100 pF 200 pA 100 pA See table analog input characteristics ns typ fin 100 kHz input range 10 V 5 MHz 4 MHz See table analog input characteristics 80 dB DC to 100 kHz ni com Analog Output Stability Recommended warm up time Offset temperature coefficient Prtegain odere PU POStgathi iei Gain temperature coefficient Onboard calibration reference Eevels ssi eV EE Temperature coefficient Long term stability Output Characteristics Number of channels Resolution eeeeeenm Max update rate 1 channel eeee 2 charinel ees FIFO buffer size eene Data transfers seeeeeeeenn DMA modes eem Transfer Characteristics Relative accuracy INL DNE udruenh s Offset error iit rhe Gain error relative to internal reference National Instruments Corporation A 5 Appendix A Specifications 5 uV C 50 uV C 20 ppm C 5 000 V 42 5 mV actual value stored in EEPROM 255 0 6 ppm C max 6 ppm 4 1 000 h 2 voltage 16 bits 1 in 65 536 4 MS s system dependent 2 5 MS s system dependent 2 04
31. CE signal 4 32 GPCTRI UP DOWN signal 4 34 to 4 35 programmable function input connections 4 16 to 4 17 waveform generation timing connections 4 26 to 4 29 UISOURCE signal 4 28 to 4 29 UPDATE signal 4 27 to 4 28 ni com WFTRIG signal 4 26 to 4 27 types of signal sources 4 9 floating 4 9 ground referenced 4 9 Index STARTSCAN signal input timing figure 4 22 output timing figure 4 23 timing connections 4 22 to 4 23 SISOURCE signal 4 25 to 4 26 software installation 2 1 system integration by National Instruments D 1 software programming choices 1 2 to 1 4 ComponentWorks 1 2 LabVIEW and LabWindows CVI application software 1 3 National Instruments application software 1 2 to 1 3 NI DAQ driver software 1 3 to 1 4 register level programming 1 4 VirtualBench 1 3 specifications analog input A 1 to A 5 amplifier characteristics A 4 dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 5 transfer characteristics A 4 analog output A 5 to A 6 dynamic characteristics A 6 output characteristics A 5 stability A 6 transfer characteristics A 5 voltage output A 6 analog trigger A 8 bus interface A 9 digital I O A 6 to A 7 digital trigger A 8 environment A 9 physical A 9 power requirements A 9 RTSI A 8 timing I O A 7 stability specifications analog input A 5 analog output A 6 National Instruments Corporation I 7 T technic
32. D converter ADC measures this output voltage when it performs A D conversions 4 8 ni com Chapter 4 Signal Connections Types of Signal Sources When making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to the 611X device analog input ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the 611X device assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the s
33. DAQ PCI 6110 6111 User Manual Multifunction 1 0 Devices for PCI Bus Computers b f NATIONAL November 2000 Edition y INSTRUMENTS Part Number 321759C 01 Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 794 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Calgary 403 274 9391 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 China 0755 3904939 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 528 94 06 Portugal 351 1 726 9011 Singapore 2265886 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support Resources appendix To comment on the documentation send e mail to techpubseni com Copyright 1998 2000 National Instruments Corporation All rights reserved Important Information Warranty The PCI 6110 and PCI 6111 devices are warranted against defects in materials and workmanship f
34. FIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFIS UPDATE pin Device and RTSI Clocks PCI 6110 6111 User Manual Many functions performed by the 611X device require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector The 611X device can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable 3 12 ni com RTSI Triggers Chapter 3 Hardware Overview The seven RTSI trigger lines on the RTSI bus provide a v
35. I 6110 6111 User Manual Chapter 4 Signal Connections Analog Input Signal Connections The analog input signals for the 611X device are ACH lt 0 3 gt and ACH 0 3 The ACH lt 0 3 gt signals are routed to the positive input of the PGIA and signals connected to ACH lt 0 3 gt are routed to the negative input of the PGIA UN Caution Exceeding the differential and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage the 611X device and the computer National Instruments is not liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in the Protection column of Table 4 2 PCI 6110 6111 User Manual With the different configurations you can use the PGIA in different ways Figure 4 2 shows a diagram of your 611X device PGIA Instrumentation Amplifier Vins O Measured Voltage Vin Vins Vin Gain Figure 4 2 611X Device PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to the 611X device Signals are routed to the positive and negative inputs of the PGIA The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the ground for the device The 611X device A
36. I3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu PFI4 GPCTR1_GATE DIO Vec 40 5 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu GPCTR1_OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIS UPDATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PCI 6110 6111 User Manual 4 6 ni com Chapter 4 Signal Connections Table 4 2 1 0 Signal Summary for the 611X Continued Signal Impedance Protection Rise Type and Input Volts Source Sink Time Signal Name Direction Output On Off mA at V mA at V ns Bias PFI7 STARTSCAN DIO Vec 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFI8 GPCTRO_SOURCE DIO Voc 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu GPCTRO_OUT DO 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu FREQ OUT DO 3 5 at Voc 0 4 5at0 4 1 5 50 kQ pu 1 Applies to gain 1 impedance refers to ACH 0 3 2Applies to gain gt 1 impedance refers to ACH lt 0 3 gt AI Analog Input DIO Digital Input Output pu pull up AO Analog Output DO Digital Output AI DIO Analog Input Digital Input Output The tolerance on the 50 kQ pull up and pull down resistors is very large Actual value may range between 17 and 100 KQ National Instruments Corporation 4 7 PC
37. SO O TOF AW LL0 0 AW 70 25600070 AU 6600 AU 9 0 AW p O 256800 258800 LS0 0 S OF AU TIO AU 6p 0 25 000 0 AU 8800 AUT AW 0 956800 8S0 0 LSO O F AU ETO AW 860 S000 0 AU STO AUT AUI CT 956800 8S0 0 LSO O CF AW gC 0 AW YZ 25600070 AU pp Q AU T S AU 256800 25800 LS0 0 SF AW TT AU Gr S000 0 AW 880 AW OT AW L S ITO ITO ITO OIF AUI c AUI 8 6 S000 0 AW 8 T AW Jc AUI Qc ISO ISO ISO OTF AW CS AU pg 95 000 0 AU py AWTS AUI SE ISO ISO ISO OSF pasezaay eopo1oaq Q po3eIaay Id BUS Aur Je I shed 06 sanoH pz areas MA Aut uopnosoq yq duro AW uonezguenQ aston PSO ZUIPEN Jo A aduey EUTUION AdVINIIV 2Ane ow Asem y ojnjosqy uoneuno0ju 3e1n33y LLLE9 OLL9 I9d ni com A 3 PCI 6110 6111 User Manual Appendix A Specifications PCI 6110 6111 User Manual Transfer Characteristics INE Stetson toe DNL ineo eere Spurious free dynamic range SFDR Effective number of bits ENOB Offset Error nette em Amplifier Characteristics Input impedance Input bias current essss Input offset current Dynamic Characteristics Interchannel skew Bandwidth 0 5 to 3 dB Input range gt 40 2 V Input range 0 2 V System noise toes Crosstalk tette A 4 0 5 LSB typ 1 LSB max 0 3 LS
38. TRIG1 Signal Any PFI pin can externally input the TRIGI signal which is available as an output on the PFIO TRIGI pin Refer to Figures 4 8 and 4 9 for the relationship of TRIGI to the DAQ sequence As an input the TRIGI signal is configured in the edge detection mode You can select any PFI pin as the source for TRIGI and configure the polarity selection for either rising or falling edge The selected edge of the TRIGI signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions The 611X supports analog triggering on the PFIO TRIGI pin See Chapter 3 Hardware Overview for more information on analog triggering As an output the TRIGI signal reflects the action that initiates a DAQ sequence This is true even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to tri state at startup National Instruments Corporation 4 19 PCI 6110 6111 User Manual Chapter 4 Signal Connections PCI 6110 6111 User Manual Figures 4 12 and 4 13 show the input and output timing requirements for the TRIGI signal i tw i A gt Rising edge polarity Falling edge polarity tw 10 ns minimum Figure 4 12 TRIG1 Input Signal Timing 1 ty i gt 1 1 i tw 25 50 ns 1 Figure 4 13 TRIG1 Output Signal Timing The device also uses the TRIGI signa
39. Trigger Compatibility esee ReSpotise ii cosi ei ssec ge edes Pulse width essen Trigger Lines eee mnis A 8 All analog input channels external trigger PFIO TRIG1 All analog input channels external trigger PFIO TRIG1 full scale internal 10 V external Positive or negative software selectable 8 bits 1 in 256 Programmable 3 dB 5 MHz internal external 10 KQ AC DC 0 5 V to Vee 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Rising or falling edge 10 ns min ni com Bus Interface Power Requirement 5 VDC 45 PCI 6110 reete PGIEOGTLI a ces tet heres Power available at I O connector Physical Dimensions not including connectors I O connector Environment Operating temperature Storage temperature Relative humidity National Instruments Corporation A 9 Appendix A Specifications Master slave 25 A 2 0A 4 65 to 45 25 VDC at 1 A 31 2 by 10 6 cm 12 3 by 4 2 in 68 pin male SCSI II type 0 to 45 C 20 to 70 C 5 to 9096 noncondensing PCI 6110 6111 User Manual Cable Connector Descriptions This appendix describes the cable connectors on your 611X device Figure B 1 shows the pin assignments for the 68 pin 611X connector This connector is available when you use the SH6868EP cable assemblies with the 611X
40. al support resources D 1 theory of operation See hardware overview timing connections 4 15 to 4 35 DAQ timing connections 4 17 to 4 26 AIGATE signal 4 25 CONVERT signal 4 23 to 4 25 EXTSTROBE signal 4 18 to 4 19 SCANCLK signal 4 18 SISOURCE signal 4 25 to 4 26 STARTSCAN signal 4 22 to 4 23 TRIGI signal 4 19 to 4 20 TRIG2 signal 4 20 to 4 21 typical posttriggered acquisition figure 4 17 typical pretriggered acquisition figure 4 18 general purpose timing signal connections 4 29 to 4 35 FREQ OUT signal 4 35 GPCTRO GATE signal 4 30 to 4 31 GPCTRO OUT signal 4 31 GPCTRO SOURCE signal 4 29 to 4 30 GPCTRO UP DOWN signal 4 31 GPCTR1_GATE signal 4 32 to 4 33 GPCTR1_OUT signal 4 32 GPCTR1_SOURCE signal 4 32 GPCTR1_UP_DOWN signal 4 33 to 4 35 programmable function input connections 4 16 to 4 17 questions about C 4 to C 5 PCI 6110 6111 User Manual Index timing I O connections figure 4 16 waveform generation timing connections 4 26 to 4 29 UISOURCE signal 4 28 to 4 29 UPDATE signal 4 27 to 4 28 WFTRIG signal 4 25 to 4 26 timing I O specifications A 7 timing signal routing 3 11 to 3 13 device and RTSI clocks 3 12 CONVERT signal routing figure 3 10 programmable function inputs 3 11 RTSI triggers 3 10 to 3 13 transfer characteristic specifications analog input A 4 analog output A 5 TRIGI signal input timing figure 4 20 output timing figure 4 20 timing connections 4 1
41. allation configuration and application problems and questions Online problem solving and diagnostic resources include frequently asked questions knowledge bases product specific troubleshooting wizards manuals drivers software updates and more Web support is available through the Technical Support section of ni com NI Developer Zone The NI Developer Zone at ni com zone is the essential resource for building measurement and automation systems At the NI Developer Zone you can easily access the latest example programs system configurators tutorials technical news as well as a community of developers ready to share their own techniques Customer Education National Instruments provides a number of alternatives to satisfy your training needs from self paced tutorials videos and interactive CDs to instructor led hands on courses at locations around the world Visit the Customer Education section of ni com for online course schedules syllabi training centers and class registration System Integration If you have time constraints limited in house technical resources or other dilemmas you may prefer to employ consulting or system integration services You can rely on the expertise available through our worldwide network of Alliance Program members To find out more about our Alliance system integration solutions visit the System Integration section of ni com National Instruments Corporation D 1 PCI 6110 61
42. allic probe that measures temperature based upon its coefficient of resistivity G 8 ni com Glossary RTSIbus real time system integration bus the National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise timing synchronization between multiple devices RTSI OSC RTSI Oscillator RTSI bus master clock S S seconds S samples SCANCLK scan clock signal SCXI Signal Conditioning eXtensions for Instrumentation the National Instruments product line for conditioning low level signals within an external chassis near sensors so only high level signals are sent to DAQ devices in the noisy computer environment SE single ended a term used to describe an analog input that is measured with respect to a common ground settling time the amount of time required for a voltage to reach its final value within specified limits signal conditioning the manipulation of signals to prepare them for digitizing SISOURCE SI counter clock signal SOURCE source signal S s samples per second used to express the rate at which a DAQ device samples an analog signal STARTSCAN start scan signal system noise a measure of the amount of noise seen by an analog circuit or an ADC when the analog inputs are grounded National Instruments Corporation G 9 PCI 6110 6111 User Manual Glossary TC tgh tgsu gw out THD thermocouple TRIG tsc tsp TTL U UI UISOURCE unipola
43. alue of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings National Instruments Corporation 3 3 PCI 6110 6111 User Manual Chapter 3 Hardware Overview Considerations for Selecting Input Ranges The range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results match the input range as closely as possible to the expected range of the input signal Input Coupling You can configure the 611X device for either AC or DC input coupling on a per channel basis Use AC coupling when your AC signal contains a large DC component If you enable AC coupling you remove the large DC offset for the input amplifier and amplify only the AC component This makes effective use of the ADC dynamic range Dither Dither adds approximately 0 5 LSBrms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of the 611X device as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dit
44. ame building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Differential Measurements The following sections discuss the use of differential DIFF measurements and considerations for measuring both floating and ground referenced signal sources National Instruments Corporation 4 9 PCI 6110 6111 User Manual Chapter 4 Signal Connections Table 4 3 summarizes the recommended DIFF signal connections and includes input examples for both types of signal sources Table 4 3 Signal Source Types DIFF Input Examples and Floating Signal Source Signal Source Not Connected to Building Ground Grounded Signal Source outputs Battery devices Input Examples Ungrounded Thermocouples Signal conditioning with isolated Plug in cards with nonisolated outputs Differential DIFF ACHO Oy T ACHO Oy ACHO N ACHO ACHOGND See text for information on bias resistors he ACHOGND T Differential Connection Considerations A differential connection is one in
45. ase notes and follow the instructions given there for your operating system and application software package If you are using NI DAQ refer to your NI DAQ release notes Find the installation section for your operating system and follow the instructions given there Hardware Installation You can install the 611X device in any available expansion slot in your computer However to achieve best noise performance leave as much room as possible between the 611X device and other devices and hardware The following are general installation instructions but consult your computer user manual or technical reference manual for specific instructions and warnings Turn off and unplug your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the 611X device into a 5 V PCI slot Gently rock the device to ease it into place It may be a tight fit but do not force the device into place 5 Ifrequired screw the mounting bracket of the 611X device to the back panel rail of the computer National Instruments Corporation 2 1 PCI 6110 6111 User Manual Chapter 2 Installation and Configuration 6 Replace the cover 7 Plugin and turn on your computer The 611X device is installed You are now ready to configure your software Refer to your software documentation for configuration instructions Device Configuration PCI 6110 6111 User Ma
46. brate when the device is installed in the environment in which it will be used Self Calibration The 611X device can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration PCI 6110 6111 User Manual The 611X device has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your device at an extreme temperature or if the onboard reference has not been measured for a yea
47. ction in Chapter 3 Hardware Overview As an output this is the TRIGI signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input Output PFI1 Trigger 2 As an input this is one of the PFIs As an output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input Output PFI2 Convert As an input this is one of the PFIs As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input Output PFI3 Counter 1 Source As an input this is one of the PFIs As an output this is the GPCTRI SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTRI GATE DGND Input Output PFIA Counter 1 Gate As an input this is one of the PFIs As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTRI OUT DGND Output Counter 1 Output This output is from the general purpose counter 1 output PFIS UPDATE
48. des e PCI 6110 e PCI 6111 Your 611X device is a high performance multifunction analog digital and timing I O device for PCI bus computers Supported functions include analog input analog output digital I O and timing I O lt gt 3 A 611X bold italic Macintosh The following conventions appear in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DBIO lt 3 0 gt This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash This refers to either the PCI 6110 or PCI 6111 device Bold text denotes parameter names Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply Macintosh refers to all Macintosh OS computers with PCI bus unless otherwise noted National Instruments Corporation Xi PCI 6110 6111 User Manual About This Manual monospace NI DAQ PC SCXI Text in this font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functi
49. dge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low National Instruments Corporation 4 25 PCI 6110 6111 User Manual Chapter 4 Signal Connections The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 20 shows the timing requirements for the SISOURCE signal tp 50 ns minimum tw 7 23 ns minimum Figure 4 20 SISOURCE Signal Timing Waveform Generation Timing Connection
50. dix D Technical Support Resources Glossary Index National Instruments Corporation Vii Contents PCI 6110 6111 User Manual Contents Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardwat e ccccccsscccceessssseeceeesssececeeeesseeeeeeeesaes 1 4 Figure3 1 PCI 6110 Block Diagram eeeeeeeeeeeeenee emen eene 3 1 Figure 3 2 PCI 6111 Block Diagram eeeeeeneeeeeenee emen enn 3 2 Figure 3 3 Effects of Dither on Signal Acquisition een 3 5 Figure 3 4 Analog Trigger Block Diagram for the PCI 6110 3 6 Figure 3 5 Analog Trigger Block Diagram for the PCI 6111 3 7 Figure 3 6 Below Low Level Analog Triggering Mode 3 7 Figure 3 7 Above High Level Analog Triggering Mode 3 8 Figure 3 8 Inside Region Analog Triggering Mode sees 3 8 Figure 3 9 High Hysteresis Analog Triggering Mode sess 3 9 Figure 3 10 Low Hysteresis Analog Triggering Mode sese 3 9 Figure 3 11 CONVERT Signal Routing eere rennen 3 11 Figure 3 12 RTSI Bus Signal Connection eere 3 13 Figure 4 1 I O Connector Pin Assignment for the 611X Device 4 2 Figure4 2 611IX Device PGIA nn
51. e has 5 V lines equipped with a self resetting 1 A fuse National Instruments Corporation C 1 PCI 6110 6111 User Manual Appendix C Common Questions Installation and Configuration How do you set the base address for the 611X device The base address of the 611X device is assigned automatically through the PCI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring my 611X device The 611X device is jumperless and switchless Which National Instruments document should I read first to get started using DAQ software Your NI DAQ or application software release notes documentation is always the best starting place Analog Input and Output PCI 6110 6111 User Manual I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the device ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the device reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Signal Connections I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When i
52. e signal lines from high current or high voltage lines These lines can induce currents in or voltages on the 611X device signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Donotrun signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments 4 36 ni com Calibration This chapter discusses the calibration procedures for your 611X device If you are using the NI DAQ device driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the 611X device these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of device calibration is required for all but the most forgiving applications If you do not calibrate your device your signals and measurements could have very large offset gain and linearity errors Three levels of calibration are ava
53. ery flexible interconnection scheme for the 611X device sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 12 zx DAQ STC TRIGI TRIG2 CONVERT 44 UPDATE WFTRIG j GPCTRO SOURCE GPCTRO GATE GPCTRO OUT I STARTSCAN I p AIGATE e SISOURCE I p UISOURCE I p GPCTR1 SOURCE p GPCTR1 GATE Switch 4 3 RTSI OSC 20 MHz Trigger I 7 7 RTSI Switch RTSI Bus Connector Clock sy Figure 3 12 RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 Signal Connections for a description of the signals shown in Figure 3 12 National Instruments Corporation 3 13 PCI 6110 6111 User Manual Signal Connections This chapter describes how to make input and output signal connections to your 611X device via the device I O connector The I O connector for the 611X device has 68 pins that you can connect to 68 pin accessories with the SH6868EP shielded cable 1 0 Connector Figure 4 1 shows the pin assignments for the 68 pin I O
54. etween V ef 2 and V 2 These devices have a bipolar input range of 20 V x10 V You can program range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on these devices increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate They have gains of 0 2 0 5 1 2 5 10 20 and 50 and are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 1 shows the overall input range and precision according to the gain used Table 3 1 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision 10 to 10 V 0 2 50 to 50 V 24 41 mV 0 5 20 to 20 V 9 77 mV 1 0 10 to 10 V 4 88 mV 2 0 5 to 45 V 2 44 mV 5 0 2to 42 V 976 56 uV 10 0 to 1V 488 28 uV 20 0 500 to 500 mV 244 14 uV 50 0 200 to 200 mV 97 66 uV Warning The 611X is not designed for input voltages greater than 42 V even if a user installed voltage divider reduces the voltage to within the input range of the DAQ device Input voltages greater than 42 V can damage the 611X any device connected to it and the host computer Overvoltage can also cause an electric shock hazard for the operator National Instruments is NOT liable for damage or injury resulting from such misuse The v
55. g input connections 4 8 description table 4 3 differential connections ground referenced signal sources figure 4 11 nonreferenced or floating signal sources figure 4 12 signal summary table 4 6 ACH lt 0 3 gt signal analog input connections 4 8 description table 4 3 differential connections ground referenced signal sources figure 4 11 nonreferenced or floating signal sources figure 4 12 signal summary table 4 6 ACH lt 0 3 gt GND signal description table 4 3 differential connections ground referenced signal sources figure 4 11 nonreferenced or floating signal sources figure 4 12 signal summary table 4 6 AIGATE signal 4 25 amplifier characteristic specifications A 4 National Instruments Corporation analog input 3 2 to 3 5 dither 3 4 input coupling 3 4 input mode 3 2 to 3 3 input polarity and range 3 3 to 3 4 questions about C 2 to C 3 selection considerations 3 4 signal connections 4 8 specifications A 1 to A 5 amplifier characteristics A 4 dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 5 transfer characteristics A 4 analog output 3 5 questions about C 2 to C 3 signal connections 4 13 specifications A 5 to A 6 dynamic characteristics A 6 output characteristics A 5 stability A 6 transfer characteristics A 5 voltage output A 6 analog trigger above high level analog triggering mode figure 3 8 avoiding false triggering
56. hapter describes your 611X device lists what you need to get started describes the optional software and optional equipment and explains how to unpack your 611X device About the 611X Devices Thank you for buying a National Instruments PCI 6110 6111 device Your 611X device is a completely Plug and Play multifunction analog digital and timing I O device for PCI bus computers The 611X device features a 12 bit ADC per channel with four or two simultaneously sampling analog inputs 16 bit DACs with voltage outputs eight lines of TTL compatible digital I O and two 24 bit counter timers for timing I O Because the 611X device has no DIP switches jumpers or potentiometers it is easily software configured and calibrated The 611X device is a completely switchless and jumperless data acquisition DAQ device for the PCI bus This feature is made possible by the National Instruments MITE bus interface chip that connects the device to the PCI I O bus The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all software configured The 611X device uses the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The DAQ STC makes
57. he polarity selection for either rising or falling edge As an output the GPCTRO SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to tri state at startup National Instruments Corporation 4 29 PCI 6110 6111 User Manual Chapter 4 Signal Connections Figure 4 26 shows the timing requirements for the GPCTRO SOURCE signal tp 50 ns minimum tw 7 10 ns minimum Figure 4 26 GPCTRO SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO SOURCE signal unless you select some external source GPCTRO GATE Signal Any PFI pin can externally input the GPCTRO GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO GATE signal reflects the actual gate signal connected to general purpose counter 0 This is t
58. her When taking DC measurements such as when checking the device calibration you should average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution Figure 3 3 illustrates the effect of dither on signal acquisition Figure 3 3a shows a small x4 LSB sine wave acquired without dither The ADC quantization is clearly visible Figure 3 3b shows what happens when 50 such acquisitions are averaged together quantization is still plainly visible In Figure 3 3c the sine wave is acquired with dither There is a considerable amount of visible noise But averaging about 50 such acquisitions as shown in Figure 3 3d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal PCI 6110 6111 User Manual 3 4 ni com Chapter 3 Hardware Overview You cannot disable dither on the 611X device This is because the ADC resolution is so fine that the ADC and the PGIA inherently produce almost 0 5 LSBrms of noise This is equivalent to having a dither circuit that is always enabled LSBs LSBs 6 0 6 0 4 0 4 0 2 0 a 2 0 0 0 0 0 2 0 H
59. ic ete te etie o coe a de e 4 8 Figure 4 3 Differential Input Connections for Ground Referenced Signals 4 11 Figure 4 4 Differential Input Connections for Nonreferenced Signals 4 12 Figure 4 5 Analog Output Connections eee eee seeeeeeseeseeeseceeeeseeseeeseseeeaes 4 13 Figure 4 6 Digital I O Connections sees 4 14 Figure 4 7 Timing I O Connections eee eerte rene 4 16 Figure 4 8 Typical Posttriggered Acquisition eeseeeeeene 4 17 Figure 4 9 Typical Pretriggered Acquisition esee 4 18 Figure 4 10 SCANCLK Signal Timing eese rene nen 4 18 Figure 4 11 EXTSTROBE Signal Timing eee 4 19 Figure 4 12 TRIGI Input Signal Timing eene 4 20 Figure 4 13 TRIG1 Output Signal Timing eene 4 20 Figure 4 14 TRIG2 Input Signal Timing eene 4 21 Figure 4 15 TRIG2 Output Signal Timing eene 4 21 Figure 4 16 STARTSCAN Input Signal Timing eee 4 22 Figure 4 17 STARTSCAN Output Signal Timing eee 4 23 Figure 4 18 CONVERT Input Signal Timing eee 4 24 Figure 4 19 CONVERT Output Signal Timing eee 4 24 Figure 4 20 SISOURCE Signal Timing esee 4 26 Figure 4 21 WHFTRIG Input Signal Timing eee 4 27 Figure 4 22 WFTRIG Output Signal Timing
60. ident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks ComponentWorks CVI DAQ STC LabVIEW Measure MITE National Instruments ni com NI DAQ NI PGIA RTSI SCXI and VirtualBench are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS
61. iggering mode the trigger is generated when the signal value is greater than highValue as shown in Figure 3 7 LowValue is unused highValue Trigger Figure 3 7 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue as shown in Figure 3 8 highValue Nc co acccoc tuis He ML NDA aai D NUES lowValue SEAE AERE eT A E A E E d m LI LLLI Figure 3 8 Inside Region Analog Triggering Mode PCI 6110 6111 User Manual 3 8 ni com Chapter 3 Hardware Overview In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than high Value with the hysteresis specified by lowValue as shown in Figure 3 9 highValue lowValue Trigger Figure 3 9 High Hysteresis Analog Triggering Mode In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue as shown in Figure 3 10 highValue lowValue Y vL LL SSP Sees wey ces AN Trigger Figure 3 10 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger
62. ignal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on 4 32 ni com Chapter 4 Signal Connections As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup Figure 4 30 shows the timing requirements for the GPCTR1 GATE signal Rising edge polarity Falling edge polarity tw 10 ns minimum Figure 4 30 GPCTR1 GATE Signal Timing in Edge Detection Mode GPCTR1 OUT Signal This signal is available only as an output on the GPCTR1 OUT pin The GPCTR1_OUT signal monitors the TC device general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 31 shows the timing requirements for the GPCTR1 OUT signal GPCTR1 SOURCE GPCTR1 OUT Pulse on TC Toggle output on TC GPCTR1 OUT Figure 4 31 GPCTR1 OUT Signal Timing National Instruments Corporation 4 33 PCI 6110 6111 User Manual Chapter 4 Signal Connections GPCTR1 UP DOWN Signal This signal can be externally input on the DIO7 pin and i
63. ilable to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants The 61 1X device is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed National Instruments Corporation 5 1 PCI 6110 6111 User Manual Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can vary with time and temperature It is better to self cali
64. integral nonlinearity For an ADC deviation of codes of the actual transfer function from a straight line input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high current output low kilohertz light emitting diode least significant bit meter megabytes of memory megahertz multifunction I O ni com MITE MSB mux mV NC NI DAQ noise NRSE OUT PCI National Instruments Corporation Glossary MXI Interface to Everything most significant bit multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel millivolts normally closed or not connected National Instruments driver software for DAQ hardware an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive nonreferenced single ended mode all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can var
65. ions UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 2 can damage the 61 LX device and the computer National Instruments is not liable for any damages resulting from such signal connections All external control over the timing of the 61 LX device is routed through the 10 programmable function inputs labeled PFIO through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The DAQ signals are explained in the DAQ Timing Connections section later in this chapter The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section later in this chapter National Instruments Corporation 4 15 PCI 6110 6111 User Manual Chapter 4 Signal Connections All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 7 which shows how to connect an external TRIGI source and an external CONVERT source to two
66. l connections 4 13 description table 4 3 signal summary table 4 6 DAQ timing connections 4 17 to 4 26 AIGATE signal 4 25 CONVERT signal 4 23 to 4 25 EXTSTROBE signal 4 18 to 4 19 SCANCLK signal 4 18 SISOURCE signal 4 25 to 4 26 STARTSCAN signal 4 22 to 4 23 TRIGI signal 4 19 to 4 20 TRIG signal 4 20 to 4 21 typical posttriggered acquisition figure 4 17 typical pretriggered acquisition figure 4 18 DAQ STC system timing controller overview 1 1 questions about C 3 to C 4 data acquisition timing connections See DAQ timing connections DC input coupling 3 4 DGND signal description table 4 3 digital I O connections 4 13 to 4 14 signal summary table 4 6 timing connections 4 15 to 4 16 differential measurements 4 9 to 4 12 common mode signal rejection 4 12 connection considerations 4 10 to 4 12 ni com DIFF input mode 3 2 to 3 3 floating signal sources 4 9 4 10 to 4 12 ground referenced signal sources 4 9 4 10 to 4 11 nonreferenced signal sources 4 11 to 4 12 recommended configuration table 4 10 digital I O operation 3 10 questions about C 3 to C 5 signal connections 4 13 to 4 14 specifications A 6 to A 7 digital trigger specifications A 8 DIO lt 0 7 gt signal description table 4 3 digital I O connections 4 13 to 4 14 signal summary table 4 6 dither enabling 3 4 to 3 5 signal acquisition effects figure 3 5 documentation conventions used in manual xi xii National
67. l to initiate pretriggered DAQ operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIGI and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFII TRIG2 pin Refer to Figure 4 9 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIGZ2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIGI signal initiates the data acquisition The scan counter indicates the minimum number of scans 4 20 ni com Chapter 4 Signal Connections before TRIG2 can be recognized After the scan counter decrements to Zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The device ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIGZ2 is received the device will acquire a fixed number of scans and the acquisition will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acq
68. log Output Ground The analog output voltages are referenced to this node DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply DIO lt 0 7 gt DGND Input or Output Digital I O signals DIO6 and 7 can control the up down signal of general purpose counters 0 and 1 respectively 45V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices National Instruments Corporation 4 3 PCI 6110 6111 User Manual Chapter 4 Signal Connections Table 4 1 Signal Descriptions for 1 0 Connector Pins Continued Signal Name Reference Direction Description PFIO TRIGI DGND Input Output PFIO Trigger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger se
69. mmable Function Input Connections eeeeeeeeee 4 16 DAQ Timing Connections eec rer eei p eee eer Perg 4 17 SCANCLK Signal ine ee the ee eee 4 18 EXTSTROBE Sign alz xt tee p 4 18 TRIGI Signal teint Mite ay een S gg e 4 19 TRIG2 Signal etat eet petente tede 4 20 STARTSCAN Signal eaae aM 4 22 CONVERT Sign l 3 iet et Re ER 4 23 AIGATE Signal eeu nioleene ddl cian nte 4 25 SISOURGE Signal aia dataset er CR e eon 4 25 Waveform Generation Timing Connections eene 4 26 WETRIG Signal ttt tere e ERIS 4 26 UPDATE Signal eee eee ies 4 27 UISQURCE Signal iio eire teo det lund d ttt Neves 4 28 General Purpose Timing Signal Connections esee 4 29 GPCFROUSOURCGE Signal etr eterne tent 4 29 GPCTRO GATE Signal stent tieu 4 30 GPGTRO QUT Signal 5 etr ert tr orci Ree 4 31 GPCTRO UP DOWN Signal esee 4 31 PCI 6110 6111 User Manual vi ni com GPCTRI SOURCE Signal GPCTR1_GATE Signal GPCTRI OUT Signal GPCTRI UP DOWN Signal FREQ OUT Signal Field Wiring Considerations esses Chapter 5 Calibration Loading Calibration Constants esses Selt Calibrationi uenerat a External Calibration eeeeeeeee Appendix A Specifications Appendix B Cable Connector Descriptions Appendix C Common Questions Appen
70. n 4 31 PCI 6110 6111 User Manual Chapter 4 Signal Connections PCI 6110 6111 User Manual GPCTR1 SOURCE Signal Any PFI pin can externally input the GPCTR1 SOURCE signal which is available as an output on the PFI3 JGPCTR1 SOURCE pin As an input the GPCTRI SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRI SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1 SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is being externally generated by another PFI This output is set to tri state at startup Figure 4 29 shows the timing requirements for the GPCTRI1 SOURCE signal tp 50 ns minimum tw 7 10 ns minimum Figure 4 29 GPCTR1 SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRI SOURCE unless you select some external source GPCTR1 GATE Signal Any PFI pin can externally input the GPCTR1 GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate s
71. n instructions specification information about your DAQ hardware and application hints e Software documentation You may have both application software and NI DAQ software documentation National Instruments application software includes ComponentWorks LabVIEW LabWindows CVI Measure and VirtualBench After you set up your hardware system use either your application software documentation or the NI DAQ documentation to help you write your application If you have a large complicated system it is worthwhile to look through the software documentation before you configure your hardware Xii ni com About This Manual e Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXIchassis manuals If you are using SCXI read these manuals for maintenance information on the chassis and installation instructions Related Documentation The following documents contain information that you might find helpful as you read this manual e DAQ STC Technical Reference Manual e National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals e PCI Local Bus Specification Revision 2 0 National Instruments Corporation xiij PCI 6110 6111 User Manual Introduction This c
72. nal signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which C 4 ni com Appendix C Common Questions function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals UN Caution If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the device the computer and the connected equipment What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the device circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Table 4 2 7 0 Signal Summary for the 611X These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 2 shows that there is a 50 kQ pull up resistor This pull up resistor will set the DIO 0 pin to a logic high when the output is in a high impedance state National Instruments Corporation C 5 PCI 6110 6111 User Manual Technical Support Resources Web Support National Instruments Web support is your first stop for help in solving inst
73. nd other accessories as follows e Cables and cable assemblies e Connector blocks shielded and unshielded 50 and 68 pin screw terminals RTSI bus cables e Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges RTDs and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections If you want to develop your own cable however the following guidelines may be useful e Forthe analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source e Route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments The following list gives recommended part numbers for connectors that mate to the I O connector on the 611X device Honda 68 position solder cup female connector par
74. nimum Figure 4 18 CONVERT Input Signal Timing I i E l tw 50 100 ns i I I Figure 4 19 CONVERT Output Signal Timing The ADC switches to hold mode within 20 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next 4 24 ni com Chapter 4 Signal Connections The sample interval counter on the 611X device normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the e
75. nual Due to the National Instruments standard architecture for data acquisition and the PCI bus specification the 611X device is completely software configurable You must perform two types of configuration on the 611X device bus related and data acquisition related configuration The 611X device is fully compatible with the industry standard PCI Local Bus Specification Revision 2 0 This allows the PCI system to automatically perform all bus related configurations and requires no user interaction Bus related configuration includes setting the device base memory address and interrupt channel Data acquisition related configuration includes such settings as analog input coupling and range and others You can modify these settings using NI DAQ or application level software such as ComponentWorks LabVIEW LabWindows CVI and VirtualBench 2 2 ni com Hardware Overview This chapter presents an overview of the hardware functions on your 611X device Figure 3 1 shows a block diagram for the PCI 6110 device l O Connector PCI Bu is Interface CHO Al CHO CHO 12 CHO Mux 4 D 12 Bit ADC Latch Data 16 CH0 CH1 p AI CH1 Y CH1 12 CH1 CH1 mx fE D amp 12 Bit ADC Latch paaa e gt CH2 ly AI CH2 y CH2 12 CH2 pata 16 cub Mux D amp 128i ADC Latch eae US D ADC bd doe m FIFO Data 32 My wierce AI CH3 lt CH3 CH3 Data 16 cs Mu
76. oltage or current analog channel 0 output signal analog channel 1 output signal data acquisition a system that uses the computer to collect receive and generate electrical signals G 3 PCI 6110 6111 User Manual Glossary DAQ STC dB DC DGND DI DIFF DIO DIP dithering DMA DNL DO E EEPROM EXTSTROBE PCI 6110 6111 User Manual Data acquisition system timing controller An application specific integrated circuit ASIC for the system timing requirements of a general A D and D A system decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct current digital ground signal digital input differential mode digital input output dual inline package the addition of Gaussian noise to an analog input signal direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their ideal value of 1 LSB digital output electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed external strobe signal G 4 ni com FIFO FREQ OUT ft G GATE GPCTR GPCTRO GATE GPCTRO OUT
77. ons operations variables filenames and extensions and code excerpts NI DAQ refers to the NI DAQ driver software for Macintosh or PC compatible computers unless otherwise noted Refers to all PC AT series computers with PCI bus unless otherwise noted SCXI stands for Signal Conditioning eXentsions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National instruments plug in DAQ devices National Instruments Documentation PCI 6110 6111 User Manual The PCI 6110 6111 User Manual is one piece of the documentation set for your DAQ system You could have any of several types of documentation depending on the hardware and software in your system Use the documentation you have as follows e Getting Started with SCXI TIf you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints e Your DAQ hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to your computer Use this documentation for hardware installation and configuratio
78. or a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of
79. possible such applications as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate Often with DAQ devices you cannot easily synchronize several measurement functions to a common trigger or timing event The 611X device has the Real Time System Integration RTSI bus to solve this problem The RTSI bus consists of our RTSI bus interface and a ribbon National Instruments Corporation 1 1 PCI 6110 6111 User Manual Chapter 1 Introduction cable to route timing and trigger signals between several functions on as many as five DAQ devices in your computer Detailed specifications of the 611X device are in Appendix A Specifications What You Need to Get Started To set up and use the 611X device you will need the following L Either the PCI 6110 or PCI 6111 device L PCI 6110 6111 User Manual L One of the following software packages and documentation ComponentWorks LabVIEW for Macintosh LabVIEW for Windows LabWindows CVI for Windows Measure NI DAQ for PC Compatibles VirtualBench C Your computer Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instruments application software NI DAQ or register level programming National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver softwa
80. processors Using ComponentWorks LabVIEW LabWindows CVI or VirtualBench software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with SCXI or accessory products except for the SCXI 1200 NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI self calibration messaging and acquiring data to extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak National Instruments Corporation 1 8 PCI 6110 6111 User Manual Chapter 1 Introduction NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hard
81. put 3e deter dee 3 5 ANALOG PIPER 3 6 Digital WO eee oa dnte eate mee endi eterne 3 10 National Instruments Corporation V PCI 6110 6111 User Manual Contents Timing Signal Routing 2 eere ire ite a me e Re tege tee genera 3 11 Programmable Function Inputs esee 3 12 Device and RTSI Clocks tet ed tene tee RH eed 3 12 RISI Triggers iinne RED pe RS skates 3 13 Chapter 4 Signal Connections W O Connector 5 d reete o tee T tab p ae eter da 4 1 T O Connector Signal Descriptions sess 4 3 Analog Input Signal Connections essere 4 8 TLypes of Signal Sources nere ORENSE E N at 4 9 Floating Signal Sources 2 255 get meten hedge 4 0 Ground Referenced Signal Sources sse 4 0 Differential Measurements niet tenet eer pe eto ens 4 0 Differential Connection Considerations eee 4 10 Differential Connections for Ground Referenced Signal Sources sess 4 11 Differential Connections for Nonreferenced or Floating Signal Sources 4 11 Common Mode Signal Rejection Considerations esse 4 12 Analog Output Signal Connections eseeeeeeeseeeeeeeenen rennen eene 4 13 Digital I O Signal Connections Jusis eiue a E Ea E EERE e rennen 4 13 Power Connections edente ER LE a b RS tesis 4 15 Taming CONMECUOMNS roere det stt E een e e e tes 4 15 Progra
82. put low voltage Io 24 mA 0 4 V Output high voltage loy 13 mA 4 35 V Power on state eeeenn Data transfers eeeeen Number of channels Resolution Counter timers eee Frequency scaler Compatibility eee Base clocks available Counter timers eee Frequency scaler Base clock accuracy Max source frequency sss Min source pulse duration Min gate pulse duration Data transfers eeeee DMA modes ee National Instruments Corporation A 7 Input High Z Programmed I O 2 up down counter timers 1 frequency scaler 24 bits 4 bits TTL CMOS 20 MHz 100 kHz 10 MHz 100 kHz 0 01 20 MHz 10 ns edge detect mode 10 ns edge detect mode DMA interrupts programmed I O Scatter gather PCI 6110 6111 User Manual Appendix A Specifications Triggers RTSI PCI 6110 6111 User Manual Analog Trigger Source PCLE 6110 eese PCT 6111 tee ToC VE t ttt tette Resolution eeeeeeenn Hysteresis 4c dct re IRR Bandwidth esseeeeeennee External input PFIO TRIG1 Impedance eeeeeees Coupling eue eee Protection a ueteri Digital
83. r UPDATE V V VDC PCI 6110 6111 User Manual terminal count the ending value of a counter gate hold time gate setup time gate pulse width output delay time total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in decibel or a percentage a temperature sensor created by joining two dissimilar metals The junction produces a small voltage as a function of the temperature trigger signal source clock period source pulse width transistor transistor logic update interval update interval counter clock signal a signal range that is always positive for example 0 to 10 V update signal volts volts direct current G 10 ni com VI WFTRIG National Instruments Corporation Glossary virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program volts input high volts input low volts in measured voltage volts output high volts output low reference voltage volts root mean square waveform generation trigger signal G 11 PCI 6110 6111 User Manual Index Numbers 5 V signal description table 4 3 power connections 4 15 self resetting fuse 4 15 C 1 A AC input coupling 3 4 ACH lt 0 3 gt signal analo
84. r or more you may wish to externally calibrate your device An external calibration refers to calibrating your device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your device by calling the NI DAQ calibration function To externally calibrate your device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For example to calibrate a 16 bit device the external reference should be at least 0 00196 10 ppm accurate 5 2 ni com Specifications Analog Input This appendix lists the specifications of your 611X device These specifications are typical at 25 C unless otherwise noted Input Characteristics Number of channels PGE6110 nisus 4 differential PCEOLlL nekmes 2 differential Resol tiOn5 ne amem eene 12 bits 1 in 4 096 Max sampling rate eee 5 MS s Min sampling rate esses 1 kS s Analog input characteristics Input Range Gain Error Offset Error SFDR CMRR System Noise 50 V 0 50 10 mV 70 dB 32 dB 0 5 20 V 0 50 10 mV 70 dB 35 dB 0 5 10 V 0 10 0 8 mV 75 dB 50 dB 0 5 5 V 0 05 0 5 mV 75 dB 56 dB 0 5 2 V 0 05
85. re ComponentWorks provides a higher level programming interface for building virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ PCI 6110 6111 User Manual 1 2 ni com Chapter 1 Introduction LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software LabWindows CVI features interactive graphics state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word
86. rue even if the gate is being externally generated by another PFI This output is set to tri state at startup PCI 6110 6111 User Manual 4 30 ni com Chapter 4 Signal Connections Figure 4 27 shows the timing requirements for the GPCTRO GATE signal Rising edge polarity Falling edge polarity tw 2 10 ns minimum Figure 4 27 GPCTRO GATE Signal Timing in Edge Detection Mode GPCTRO OUT Signal This signal is available only as an output on the GPCTRO OUT pin The GPCTRO OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 28 shows the timing of the GPCTRO OUT signal GPCTRO SOURCE GPCTRO OUT Pulse on TC GPCTRO OUT Toggle output on TC TC i 1 Figure 4 28 GPCTRO OUT Signal Timing GPCTRO UP DOWN Signal This signal can be externally input on the DIOG pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use National Instruments Corporatio
87. s The analog group defined for the 611X device is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to tri state at startup PCI 6110 6111 User Manual 4 26 ni com Chapter 4 Signal Connections Figures 4 21 and 4 22 show the input and output timing requirements for the WFTRIG signal Rising edge polarity Falling edge polarity ty 10 ns minimum Figure 4 21 WFTRIG Input Signal Timing I tw 25 50 ns Figure 4 22 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode Yo
88. s not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 32 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the 611X device OUT output signals V SOURCE H V IL GATE IH IL o Von UT V OL FS OS i tsc Pit is A i tgsu tgh I 3 tow tout Source Clock Period te 50 ns minimum Source Pulse Width tsp 23 ns minimum Gate Setup Time tosu 10 ns minimum Gate Hold Time tgh Ons minimum Gate Pulse Width t gw 10 ns minimum Output Delay Time tout 80 ns maximum PCI 6110 6111 User Manual Figure 4 32 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 32 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on the 611X device Figure 4 32 shows the GATE signal referenced to the ri
89. s te x Le Cohtrol Control Interface z Counter Bus m r O Timing vo DAQ STC interface PASS FPGA o OIN n a I C interface pa A mmm vo B Analog Output RTSI Bus Analog Bus gt Digital VO 8 Digital I O 1 Timing Control Interface Output Interface AO Control DACO DAC1 Calibration l i 4 DACs Analog Input Figure 3 2 PCI 6111 Block Diagram Input Mode PCI 6110 6111 User Manual The analog input section for the 611X device is software configurable You can select different analog input configurations through application software The following sections describe in detail each of the analog input categories The 611X device supports only differential inputs DIFF The DIFF input configuration provides up to four channels on the PCI 6110 device and up to two channels on the PCI 6111 device A channel configured in DIFF mode uses two analog channel input lines One line connects to the positive input of the device programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA For more information about DIFF input configuration 3 2 ni com Chapter 3 Hardware Overview refer to the Analog Input Signal Connections section in Chapter 4 Signal Connections which contains diagrams showing the signal paths for DIFF input Input Polarity and Input Range The 611X device has bipolar inputs only Bipolar input means that the input voltage range is b
90. scription table 4 4 PCI 6110 6111 User Manual Index general purpose timing connections 4 33 signal summary table 4 6 GPCTRI SOURCE signal 4 32 GPCTRI UP DOWN signal 4 34 to 4 35 ground referenced signal sources description 4 9 differential connections 4 11 recommended configuration table 4 10 H hardware installation procedure 2 1 to 2 2 unpacking PCI 6110 6111 1 6 hardware overview analog input 3 2 to 3 5 dither 3 4 to 3 5 input mode 3 2 to 3 3 input polarity and range 3 3 to 3 4 selection considerations 3 4 analog output 3 5 analog trigger 3 6 to 3 9 block diagrams PCI 6110 3 1 PCI 6111 3 2 digital I O 3 10 timing signal routing 3 11 to 3 12 device and RTSI clocks 3 12 CONVERT signal routing figure 3 11 programmable function inputs 3 12 RTSI triggers 3 13 input characteristic specifications A 1 to A 2 input mode See differential measurements input polarity and range 3 3 to 3 4 actual range and measurement precision table 3 3 selection considerations 3 4 PCI 6110 6111 User Manual l 4 installation hardware 2 1 to 2 2 questions about C 2 software 2 1 unpacking PCI 6110 6111 1 6 T O connectors 4 1 to 4 7 cable connectors for PCI 6110 6111 1 5 exceeding maximum ratings caution 4 1 I O signal summary table 4 6 to 4 7 pin assignments figure 4 2 B 2 signal descriptions table 4 3 to 4 5 L LabVIEW and LabWindows CVI application software 1 3
91. se selections are different and the DAQ STC counters are 24 bit counters unlike the 16 bit counters on devices without the DAQ STC If you are using the NI DAQ language interface or LabWindows CVI the answer is no the counter timer applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I m using one of the general purpose counter timers on my 611X device but I do not see the counter timer output on the I O connector What am I doing wrong If you are using the NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri stated What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect exter
92. sing edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t and t in Figure 4 32 4 34 ni com Chapter 4 Signal Connections The gate signal is not required to be held after the active edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the 611X device Figure 4 32 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ OUT Signal This signal is available only as an output on the FREQ OUT pin The frequency generator for the 611X device outputs the FREQ OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to tri
93. t number PCS E68FS e Honda backshell part number PCS E68LKPA National Instruments Corporation 1 5 PCI 6110 6111 User Manual Chapter 1 Introduction Unpacking The 611X device is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge can damage several components on the device To avoid such damage in handling the device take the following precautions e Ground yourself via a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the device from the package e Remove the device from the package and inspect the device for loose components or any other sign of damage Notify National Instruments if the device appears damaged in any way Do not install a damaged device into your computer e Never touch the exposed pins of connectors PCI 6110 6111 User Manual 1 6 ni com Installation and Configuration This chapter explains how to install and configure your 611X device Software Installation Install your software before you install the 611X device Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence If you are using LabVIEW LabWindows CVI or other National Instruments application software packages refer to the appropriate release notes After you have installed your application software refer to your NI DAQ rele
94. t switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my 611X device Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps C 2 ni com Appendix C Common Questions 1 through 4 below in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFI5 line for output as follows e If you are using NI DAQ call Select Signal deviceNumber ND PFI 5 ND OUT UPDATE ND HIGH TO LOW e If you are using LabVIEW invoke Route Signal VI with signal name set to PFI5 and signal source set to AO Update 2 Setup data acquisition timing so that the timing signal for A D conversion comes from PFIS5 as follows e If you are using NI DAQ call Select Signal deviceNumber ND IN CONVERT ND PFI 5 ND HIGH TO LOW e Ifyou are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate analog input data acquisition which will start only when the
95. ted by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low 4 28 ni com Chapter 4 Signal Connections Figure 4 25 shows the timing requirements for the UISOURCE signal tp 2 50 ns minimum ty 10 ns minimum Figure 4 25 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 KHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTRO SOURCE GPCTRO GATE GPCTRO OUT GPCTRO UP DOWN GPCTRI1 SOURCE GPCTR1_GATE GPCTR1_OUT GPCTRI UP DOWN and FREQ OUT GPCTRO SOURCE Signal Any PFI pin can externally input the GPCTRO SOURCE signal which is available as an output on the PFIS GPCTRO SOURCE pin As an input the GPCTRO SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO SOURCE and configure t
96. ter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output National Instruments Corporation 4 5 PCI 6110 6111 User Manual Chapter 4 Signal Connections Table 4 2 shows the I O signal summary for the 611X devices Table 4 2 1 0 Signal Summary for the 611X Signal Impedance Protection Rise Type and Input Volts Source Sink Time Signal Name Direction Output On Off mA at V mA at V ns Bias ACH lt 0 3 gt Al 1MQ 42 V in parallel with 100 pF 1 MQ in parallel with 10 pF ACH lt 0 3 gt AI 10 nF 42 V 200 pA ACH lt 0 3 gt GND AI DACOOUT AO 50 Q Short circuitto 5 at 10 5at 10 300 ground V us DACIOUT AO 50 Q Short circuitto 5 at 10 5at 10 300 ground V us AOGND AO DGND DO VCC DO 0 10 Short circuitto 1A ground DIO lt 0 7 gt DIO Vec 40 5 13 at Vec 0 4 24at0 4 1 1 50 kQ pu SCANCLK DO 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu EXTSTROBE DO 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu PFIO TRIGI AI 10 KQ 35 3 5 at Voc 0 4 5at0 4 1 5 9 KQ pu DIO Vec 0 5 and 10 kQ pd PFI1 TRIG2 DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PF
97. their answers relating to usage and special features of your 611X device General Information What is the 611X device The 611X device is a switchless and jumperless enhanced MIO device that uses the DAQ STC for timing What is the DAQ STC The DAQ STC is the system timing control application specific integrated circuit ASIC designed by National Instruments and is the backbone of the 611X device The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups e Analog input two 24 bit two 16 bit counters e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible What does sampling rate mean to me It means that this is the fastest you can acquire data on your device and still achieve accurate results The 61 LX device has a sampling rate of 5 MS s This sampling rate is at 5 MS s regardless if 1 or 4 channels are acquiring data What type of 5 V protection does the 611X device have The 611X devic
98. this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood acc
99. tions for three typical digital I O applications LED SP d ANN 4 043 4 DIO lt 4 7 gt He Hal JLI O L gt TTL Signal o DIO lt 0 3 gt 45V VVV O Switch Y j V e DGND l O Connector 611X Device Figure 4 6 Digital I O Connections Figure 4 6 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the switch state shown in Figure 4 6 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 4 6 PCI 6110 6111 User Manual 4 14 ni com Chapter 4 Signal Connections Power Connections Two pins on the I O connector supply 5 V from the computer power supply via a self resetting fuse The fuse will reset automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry e Power rating 4 65 to 5 25 VDC at 1 A N Caution Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the 611X device or any other device Doing so can damage the 611X device and the computer National Instruments is not liable for damages resulting from such a connection Timing Connect
100. u bas HER SEE Ee EE PO er Ete EQUES TTE xi National Instruments Documentation sees neret eene xii Related Doc mentatior ene d eec aret eese ca dvd ere R xiii Chapter 1 Introduction Aboutthe 6T LX Devices a rt nee terere REO OR CR a ER casas 1 1 What You Need to Get Started neioii a an t y RR E EE NEE nares 1 2 Software Programming Choices essere rennen eem enne 1 2 National Instruments Application Software esse 1 2 NI DAQ Driver Software ccccccccsscceesseeeeneeessneeeessaeeeseseeeseseeeseseesseeeeseeees 1 3 Register Level Programming esses nennen enne 1 4 Optional Equipment tro ene ga tet tte etia egg ea 1 5 Custom Cabling 2 te etse ecce dt i Re e ales 1 5 Unpacking ue an daret reete queer irr RR 1 6 Chapter 2 Installation and Configuration Software Installation eeeeeeeeeeeeeeeeee n nennen nennen nenne emen nnn nnn nn sse esee eene e E a 2 1 Hardware Installation ier tette testen ect ee A ert deve nhe Ue odo 2 1 Device Config ration x et e eei eee eo ee ti tert es 2 2 Chapter 3 Hardware Overview Analog Input 7er a a em etel niuseiteiit eiut eie 3 2 Input Mode s eb reete ie ee pe eee HEINE E E sees 3 2 Input Polarity and Input Range eene 3 3 Considerations for Selecting Input Ranges esses 3 4 Input Coupling anie eee ad ee ege de eiet 3 4 bird 3 4 Analog Out
101. u can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACSs This is true even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 75 ns This output is set to tri state at startup National Instruments Corporation 4 27 PCI 6110 6111 User Manual Chapter 4 Signal Connections PCI 6110 6111 User Manual Figures 4 23 and 4 24 show the input and output timing requirements for the UPDATE signal Rising edge polarity Falling edge polarity tw 2 10 ns minimum Figure 4 23 UPDATE Input Signal Timing ty 50 75 ns Figure 4 24 UPDATE Output Signal Timing The DACS are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The UI counter for the 61 LX device normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when ga
102. uisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to tri state at startup Figures 4 14 and 4 15 show the input and output timing requirements for the TRIG2 signal A M Rising edge polarity 1 i Falling edge polarity tw 10 ns minimum Figure 4 14 TRIG2 Input Signal Timing I i tw 25 50 ns i Figure 4 15 TRIG2 Output Signal Timing National Instruments Corporation 4 21 PCI 6110 6111 User Manual Chapter 4 Signal Connections PCI 6110 6111 User Manual STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 8 and 4 9 for the relationship of STARTSCAN to the DAQ sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two o
103. utput options The first is an active high pulse with a pulse width of 25 to 50 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN will be deasserted t after the last conversion in the scan is initiated This output is set to tri state at startup Figures 4 16 and 4 17 show the input and output timing requirements for the STARTSCAN signal lt Rising edge polarity Falling edge polarity tw 10 ns minimum Figure 4 16 STARTSCAN Input Signal Timing 4 22 ni com Chapter 4 Signal Connections Start Pulse CONVERT STARTSCAN a _ 4 gt 1 tw 25 50 ns i i a Start of Scan STARTSCAN tog 10 ns minimum o loft b Scan in Progress Two Conversions per Scan Figure 4 17 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the device generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion The STARTSCAN pulses should be separated by at least one scan period A counter on the 611X device internally generates the STARTSCAN signal unless you select some e
104. ware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages or National Instruments application software your application uses the NI DAQ driver software as illustrated in Figure 1 1 Conventional ComponentWorks Programming LabVIEW LabWindows CVI Environment NI DAQ Driver Software a DAQ or Personal Computer SCXI Hardware or Workstation or VirtualBench Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware Register Level Programming PCI 6110 6111 User Manual The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer using NI DAQ or application software to program your National Instruments DAQ hardware is easier than and as flexible as register level programming and can save weeks of development time 1 4 ni com Chapter 1 Introduction Optional Equipment National Instruments offers a variety of products to use with the 611X device including cables connector blocks a
105. x Amplifier 12 Bit ADC Latch gt gt Calibration gt l Mux Analog Trigger Trigger Trigger Level 2 gt e PFI Trigger Trigger Circuitry Analog Input DMA IRQ AO Control Timing Control Analog EEPROM ie Soe eS Conte Control Interface Counter Bus v es ES Timing vo DAQ STC interface Fu CREE T UNT IEEE PEN A Interface 2m Analog Output RTSI Bus Analog Digital VO 8 Digital VO Timing Control Interface Output Interface Y DMA vo Bus DAC FIFO 2 Calibration 4 DACs Data 32 Address Data LE PCI Bus National Instruments Corporation 3 1 Figure 3 1 PCI 6110 Block Diagram PCI 6110 6111 User Manual Chapter 3 Hardware Overview Figure 3 2 shows a block diagram for the PCI 6111 device CHO gt AI CHO CHO CHO 12 Gc Mu I amplifier gt lt 12 Bit ADC H Generic Mini Pct Bus Bus Interface MITE interface CH1 aF 1 AI CH1 CH1 Y CH1 12 i cur Mux amplifier D X 12 Bit ADC tae gt Calibration AT Control E eErrow x Trigger Trigger Level J 2 Analog 9 DACs Trigger TN ba Circuitry D i i vy S i i R Analog Input 2 c PFI Trigger Trigger Timing Control DMA IRQ Analog EEPROM DMA mM S Chesca SO ee a
106. xternal source This counter is started by the TRIGI signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin National Instruments Corporation 4 23 PCI 6110 6111 User Manual Chapter 4 Signal Connections PCI 6110 6111 User Manual Refer to Figures 4 8 and 4 9 for the relationship of STARTSCAN to the DAQ sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 18 and 4 19 show the input and output timing requirements for the CONVERT signal Rising edge polarity i Falling edge polarity tw 2 10 ns mi
107. y with respect to the measurement system ground output pin a counter output pin where the counter can generate various TTL pulse waveforms Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA Itis achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 MB s G 7 PCI 6110 6111 User Manual Glossary PFI PFIO TRIGI PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE PFIS UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFIS GPCTRO SOURCE PFI9 GPCTRO GATE PGIA port ppm pu RAM rms RSE RTD PCI 6110 6111 User Manual Programmable Function Input PFIO trigger 1 PFIl trigger 2 PFI2 convert PFI3 general purpose counter 1 source PFI4 general purpose counter gate PFI5 update PFI6 waveform trigger PFI7 start of scan PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate Programmable Gain Instrumentation Amplifier 1 acommunications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output parts per million pull up random access memory root mean square referenced single ended mode all measurements are made with respect to a common reference measurement system or a ground Also called a grounded measurement system resistive temperature detector a met

PCI-6110/6111 User Manual - UCSD Department of Physics

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