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ST40 core support peripherals (ST40-300)

1. 39 54 1 Instruction register SDIR 39 5 4 2 Dataregister SDDR 40 5 4 3 Bypass register SDBPR 40 5 4 4 Interrupt factor register SDINT 41 5 5 Operation PRIM 42 5 5 1 TAP control e eek EE Ru EE ae 42 5 5 2 UD reset is EE RE inira RR RD de ERES DES x deer ras 43 5 5 3 UDlinterrupt ius EER EER EE EES ER ee EE ER be g da bea 43 5 5 4 BYPASS AE RE ca EE RO EE ea ewe dee a aes E 43 5 6 Usage notes exis Me re quer RU RE DERE ROER EE ame Be ae Se 44 5 6 1 SDIR command pag pama oad LEON we ie a dug ws 44 5 6 2 SDIR commands in sleep mode 44 8011247 Rev 5 3 58 Contents ST40 core support peripherals 300 series 4 58 Interrupt controller INTC 45 6 1 INTC features 45 6 2 Blockdiagram 46 6 3 PICO ie uie sa aia a aana WA ia dd 46 6 4 Register configuration se ee 47 6 5 LEMA SOUIGES ESE duda dude rr Ede S dra cess drin 47 6 5 1 Non maskable interrupts NMI 47 6 5 2 IRL interrupts iu sek KG a ADA ad RR Ee Aad eels 48 6 5 3 On chip peripheral module interrupts 49 6 5 4 Interrupt exception handling and priority 49 6 6 I
2. 9 10 Exception 20 43 44 47 49 50 Power on reset 19 43 47 52 PP BUS ree ep CR vos kha 11 F Priority sch RR wakes 35 43 45 47 54 Priority Register 51 FUNCION cimas S 20 33 37 43 Functions eee eee eee eee 36 R Register 11 12 17 20 29 33 35 36 38 40 45 WA edit IAEA booth LAGA e Ed IE 47 49 54 lg oc 45 46 51 53 Field Type Interrupt controller 53 54 READ ONLY 13 14 30 32 33 o ETT 20 46 48 52 READ WRITE 12 13 32 33 52 53 IREM ium et dme et aee oe BANANA 49 RESERVED 13 53 INTEVT 20 43 49 50 54 J Husos v ES 18 19 23 26 29 32 38 41 47 SR ii 20 46 47 49 50 54 JTAG M c PIA 36 37 42 43 SRBL cvs li hie EE 45 52 53 Sj Mm rr 20 54 56 58 8011247 Rev 5 ky ST40 core support peripherals 300 series Index VBR issue shy See geek e redu See et 43 54 W Registers A Program Counter 54 a MA EE M E RESERVED 13 39 41 58 CT 7777777770770 77000 EII IEI Reserved bits 51 RESET IE EU EI 18 37 Reset 9 10 12 14 17 20 23 26 28 30 33 36 37 39 41 43 44 47 49 51 53 Response eese 12 Rising edge 42 52 RIE uoa dead EET 43 49 54 S SLEEP ui ads 17 20 Sleep 20 44 47 53 SPO is EE a ieee d ORE TA ee ts 20 54 scr pP ETT 20 St
3. Table 35 Interrupt control register INTC ICR Bit name Bit Size Volatile Synopsis Type 14 1 NMI interrupt mask RW Specifies whether or not all interrupts are to be masked while the NMI pin input level is low irrespective of the CPU s SR BL Operation bit MAI 0 interrupts are enabled even while NMI pin is low 1 interrupts are disabled while NMI pin is low When read Returns current value When written Updates current value Reset 0 15 1 3 NMI input level RO Reports the level of the signal input at the NMI pin This bit can be read to determine the NMI pin level It cannot be modified Operation A 0 NMI input level is low NMIL 1 NMI input level is high When read Returns current value When written Ignored Reset 0 1 6 0 13 10 4 Reserved RES Operation Reserved gt When read Returns O When written Write 0 Reset 0 a If an interrupt request is accepted while SR BL 1 the previous exception information is lost so should be saved beforehand This bit is cleared automatically when an NMI interrupt is accepted b NMI interrupts are accepted in normal operation and in sleep mode c 1 when NMI input is high O when low INTC operation Interrupt sequence The sequence of interrupt operations is as follows 1 The interrupt request sources send interrupt request signals to the interrupt controller 2 The interrupt controller selects the highest priority interrupt from the interrupt req
4. Each channel has a 32 bit timer counter TCNT that performs count down operations and a 32 bit timer constant register TCOR The channels have an auto reload function that allows cyclic count operations Counter operation When one of bits STRO to STR2 is set to 1 in the timer start register TMU TSTR the timer counter TCNT for the corresponding channel starts counting When TCNT underflows the UNF flag is set in the corresponding timer control register TCR If the UNIE bit in TCR is set to 1 at this time an interrupt request is sent to the CPU At the same time the value is copied from TCOR into TCNT and the count down continues auto reload function Example of count operation setting procedure Figure 5 shows an example of the count operation setting procedure 1 Select the count clock with bits TPSC2 to TPSCO in the timer control register TCR 2 Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR 3 Setavalue in the timer constant register TCOR 4 Set the initial value in the timer counter TCNT 5 Set the STR bit to 1 in the timer start register TMU TSTR to start the count 8011247 Rev 5 33 58 Timer unit TMU ST40 core support peripherals 300 series 34 58 Figure 5 Example of count operation setting procedure Operation selection Y Select count clock v Underflow interrupt generation setting v Time constant register
5. Ti RM0148 YI Reference manual ST40 core support peripherals ST40 300 Overview Note This manual reflects the core support peripherals CSP for the ST40 300 series devices only The ST40 CSP package contains a set of core support peripherals for use in ST40 based system on chips SoCs These peripherals are designed to provide many common functions used by embedded operating systems This manual provides details on the architecture of the core support peripherals which includes Clock power and reset control CPRC Timer unit TMU User debug interface UDI and the Interrupt controller INTC This manual also describes the peripheral bridge which acts as the interface between the peripherals and the STBus This is achieved by grouping the modules into a single port on the STBus and handling any data size data rate and endianness issues transparently For the architectural description of the peripheral bridge see Chapter 2 Peripheral bridge on page 9 October 2011 8011247 Rev 5 1 58 www st com Contents ST40 core support peripherals 300 series Contents 1 Architectural overview 7 2 Peripheralbridge 9 2 1 Address map 9 2 1 1 Virtual addressing of a CPU s own CSP peripherals 9 2 1 2 CSP physical addressing 9 2 1 3 Error con
6. Initialized by a power on reset or manual reset c 0x8000 when the NMI pin is high 0x0000 when the NMI pin is low Interrupt sources There are four types of interrupt sources e NMI e IRL e CSP modules e external interrupt controllers cascaded to the INTC Each interrupt has a priority level 15 to 0 15 is the highest and O the lowest When level 0 is set the interrupt is masked and interrupt requests are ignored Non maskable interrupts NMI The NMI has the highest interrupt priority level of 16 It is always accepted unless the BL bit in the status register SR in the CPU is set to 1 In sleep mode the interrupt is accepted regardless of the BL setting The ICR NMIB bit can also be used in normal operation to accept the NMI interrupt even if the BL bit is set to 1 Input from the NMI pin is edge detected The NMI edge select bit NMIE in the interrupt control register ICR is used to select either a rising or falling edge When ICR NMIE is modified the NMI interrupt is not detected for a maximum of 6 bus clock cycles after the modification NMI interrupt exception handling does not affect the interrupt mask level bits 13 to 10 in SR 8011247 Rev 5 47 58 Interrupt controller INTC ST40 core support peripherals 300 series 6 5 2 48 58 IRL interrupts IRL interrupts are input by level at pins IRL3 to IRLO The priority level is the level indicated by pins IRL3 to IRLO An IRL3 to IRLO value
7. 12 TMU1 TUNI1 0x420 Oto 15 0 IPRA 11 8 TMU2 TUNI2 0x440 Oto 15 0 IPRA 7 4 50 58 8011247 Rev 5 g ST40 core support peripherals 300 series Interrupt controller INTC 6 6 6 6 1 Table 33 ST40 core interrupt exception vectors and rankings continued Interrupt priority initial value Priority within IPR setting unit INTEVT code IPR bit numbers Default Interrupt source ae priority 0x460 0x480 Ox4A0 Ox4CO 0x700 0x720 0x740 0x760 0x560 Ox3E0 RESERVED WDT ITI RESERVED 0 to 15 0 IPRB 15 12 Other interrupts are device specific and are listed in the datasheet a Default priority position of external interrupts using the expander The details of interrupts in this group are an integration option b These INTEVT codes are used by CSP modules present in other ST40 series These codes should be avoided when allocating new codes for cascaded interrupt controllers to avoid potential software conflicts For further information on these interrupts refer to the following sections e TUNIO TUNI2 underflow interrupts see Chapter Timer unit TMU on page 28 e ITI interval timer interrupt see Section 3 5 Watchdog timer on page 22 e VCR CSP bridge version control interrupt see Chapter Peripheral bridge on page 9 INTC registers Interrupt priority registers
8. Canceling user break controller stopped state 6 Read STBCR2 then clear MSTP5 bit in the read data to 0 and write it back mov 1 STBCR2 R1 mov b R1 RO and H FE RO mov b RO R1 7 7 Twice dummy read STBGR2 mov b R1 RO mov b R1 RO 3 5 Watchdog timer Figure 2 WDT block diagram A Peripheral clock Interrupt reset Reset Frequency request GH divider T Wi Clock selector Clock selection Interrupt 4 Interrupt Overflow request control Clock WTCSR WTCSR2 C Bus interface 4 Y WTCSR WTCSR2 Watchdog timer control status registers WTONT Watchdog timer counter g 22 58 8011247 Rev 5 ST40 core support peripherals 300 series Clock power and reset control CPRC 3 5 1 3 5 2 Watchdog timer counter WTCNT The watchdog timer counter WTCNT is an 8 bit readable writable counter that counts up on the selected clock When WTCNT overflows a reset is generated in watchdog timer mode or an interrupt in interval timer mode WTONT is initialized to 0x00 only by a power on reset using the RESET pin To write to the WTCNT counter use a word size access with the upper byte set to Ox5A To read WTCNT use a byte size access Table 13 CPRC WTCNT CPRC WTCNT 0x08 Field Bits Size Volatile Synopsis Type 7 0 8 Yes WDT count register RW Operation Specifies initial value for watchdog counter WTCNT When re
9. and reset control CPRC ST40 core support peripherals 300 series 3 3 2 Module clock control register CPRC STBCR The module clock control register CPRC STBCR is an 8 bit read write register that specifies the power down mode status It is initialized to 0x00 by a power on reset either asserted from outside the ST40 or due to watchdog timer overflow Table 11 CPRC STBCR CPRC STBCR 0x04 Field Bits Size Volatile Synopsis Type 1 0 2 Reserved RW Operation Reserved RESERVED When read Returns 0 When written Ignored Reset 0 2 1 Module stop 2 TMU RW Bit 2 specifies the TMU module if present to stop the clock Operation supply Po 0 TMU operates MSTP2 1 TMU clock supply is stopped When read Returns current value When written Updates current value Reset 0 va m Operation Reserved RESERVED When read Returns 0 When written Ignored Reset 0 1 Register bits are specific to the implementation If an implementation omits the TMU all bits in this register are reserved 18 58 ky 8011247 Rev 5 ST40 core support peripherals 300 series Clock power and reset control CPRC 3 3 3 Module clock control register 2 CPRC STBCR2 Module clock control register 2 CPRC STBCR2 is an 8 bit read write register that specifies clock stop behavior for particular modules inside the ST40 CPU It is initialized to 0x00 by a power on
10. between ST40 variants Table 3 is an example of how the TMU TSTR register can be accessed from software running on its own ST40 and from software running on another ST40 or another STBus initiator Table 3 Addressing of ST40 CSP registers by their associated CPU and by other initiators Example Software Address es for TMU TSTR of Address es for TMU TSTR of running on CPUBASE of ST40 0 ST40 1 9 this ST40 0x0123 4604 ST40 0 0x0123 4000 OxFFD8 0004 7 0x0246 8604 discouraged 0x0246 8604 ST40 1 0x0246 8000 0x0123 4604 OxFFD8 0004 a discouraged Other device n a 0x0123 4604 0x0246 8604 The conversion of the addressing scheme in Table 7 to the physical addresses in Table 2 is handled automatically by the ST40 CPU when it accesses its own CSP peripherals If the CSP is mapped using translations in the UTLB or PMB there are two translation stages inside the ST40 CPU 1 Virtual to physical translation in the UTLB or PMB 2 Conversion of CSP P4 physical address to STbus physical address that is mapping of Table 1 base addresses to Table 2 base addresses Error conditions If an access is attempted to an unmapped area or to an un implemented peripheral an address error is recorded and an STBus error response sent to the requesting initiator 8011247 Rev 5 ky ST40 core support peripherals 300 series Peripheral bridge 2 2 2 3 Bridge registers The peripheral b
11. flag RW Indicates that WTCNT has overflowed in interval timer mode i This flag is not set in watchdog timer mode Operation um 0 no overflow initial value IOVF 1 WTCNT has overflowed in interval timer mode When read Returns current value When written Returns current value Reset 0x0 4 1 Yes Watchdog timer overflow flag RW Indicates that WTCNT has overflowed in watchdog timer mode This flag is not set in interval timer mode Operation aue 0 no overflow initial value WOVF 1 WTCNT has overflowed in watchdog timer mode When read Returns current value When written Updates current value Reset 0x0 5 1 Reset select RW Specifies the type of reset to use when WTCNT overflows in watchdog timer mode This setting is ignored in interval timer Operation mode RSTS 0 power on reset initial value 1 manual reset When read Returns the current value When written Updates the current value Reset 0x0 6 1 Timer mode select RW Specifies whether the WDT is used as a watchdog timer or interval timer paration 0 interval timer mode Initial value WT IT 1 watchdog timer mode When read Returns current value When written Reset Updates current value 0 g 8011247 Rev 5 ST40 core support peripherals 300 series Clock power and reset control CPRC Table 14 CPRC WTCSR continued CPRC WTCSR 0x0c Field Bits Size Volatile Synopsis Type 7 1 Timer enable RW Sp
12. generated each time the counter overflows This enables interrupts to be generated at fixed intervals 1 2 3 4 Clear the WT IT bit in the WTCSR register to O Select the count clock with bits CKS3 CKSO Set the initial value in the WTCNT counter Set the TME bit in the WTCSR register to 1 The count starts in interval timer mode When the counter overflows the WDT sets the IOVF flag in the WTCSR register to 1 and sends an interval timer interrupt request to INTC The counter continues counting 8011247 Rev 5 27 58 Timer unit TMU ST40 core support peripherals 300 series 4 4 1 4 2 28 58 Timer unit TMU This chapter describes the on chip 32 bit timer unit TMU module comprising three 32 bit timer channels channels 0 to 2 Features The TMU has the following features Auto reload type 32 bit down counter provided for each channel 32 bit timer constant register for auto reload use readable or writable at any time and 32 bit down counter provided for each channel Selection of five internal clocks for each channel P 4 P 16 Pdy64 PO256 Pd 1024 where Po is the peripheral module clock Timer count operations are only possible when the module clock supply to the TMU is enabled Three interrupt sources three underflow sources channels 0 1 and 2 Block diagram Figure 4 shows a block diagram of the TMU Figure 4 Block diagram of TMU RESET STBY TUNIO PCLK 4 16 64 TUN
13. level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts However the priority level can be changed to a higher one The interrupt mask bits I3 to IO in SR are not affected by IRL interrupt handling Setting the IRLM bit to 1 in the ICR register enables pins IRLO to IRL3 to be used for four independent interrupt requests On chip peripheral module interrupts CSP module interrupts are generated by the following optional modules e timer unit TMU e watchdog timer WDT e version control register VCR Other modules integrated outside the CSP could also generate interrupts These should be controlled by a second level external interrupt controller This second level interrupt controller should be cascaded into the CSP interrupt controller Not every interrupt source is assigned a different interrupt vector Sources are reflected on the interrupt event register INTEVT It is easy to identify sources using the values of INTEVT as branch offsets in the exception handler routine The priority level from O to 15 can be set for each module by writing to interrupt priority setting registers IPRA to IPRD The interrupt mask bits I3 to 10 in SR are not affected by the on chip peripheral module interrupt handling On chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in SR is set to 1 To prevent acceptance
14. of an erroneous interrupt from an interrupt source that should have been updated first read the on chip peripheral register containing the relevant flag then clear the BL bit to O This ensures that the updated state applies to subsequent processing When updating several flags it is sufficient to read only the register containing the last flag updated If flag updating is performed while the BL bit is cleared to 0 the program may jump to the interrupt service routine when the INTEVT register value is O Interrupt handling is then initiated due to the timing relationship between the flag update and interrupt request recognition in the chip Processing can be continued without any problem by executing an RTE instruction Interrupt exception handling and priority Table 33 lists the codes for INTEVT and the order of interrupt priority Each interrupt source is assigned a unique code The start address of the interrupt handler is common to each interrupt source This is why for instance the value of INTEVT is used as offset at the start of the interrupt handler and branched to identify the interrupt source The order of priority of the on chip peripheral module is set in the priority levels 0 to 15 using the interrupt priority level set in registers A B C and D IPRA to IPRD The order of priority of the on chip peripheral module is set to 0 by a reset When the priorities for multiple interrupt sources are set to the same level and such in
15. write data When writing to WTCSR perform the transfer with the upper byte set to OxA5 and the lower byte containing the write data When writing to WTCSR2 perform the transfer with the upper byte set to OXAA and the lower byte containing the write data 8011247 Rev 5 ky ST40 core support peripherals 300 series Clock power and reset control CPRC 3 6 3 6 1 3 6 2 This transfer procedure writes the lower byte data to WTCNT or WTCSR The write formats are shown in Figure 3 Figure 3 Writing to WTCNT WTCSR and WTCSR2 WTONT write Address OxFFCO 0008 Write data WTCSR write Address OXFFCO 000C Write data WTCSR2 write Address OXFFCO 001C Write data Using the WDT Using watchdog timer mode DOL dece NO ccs Set the WT IT bit in the WTCSR register to 1 Select the type of reset with the RSTS bit Set the count clock with bits CKS3 CKSO Set the initial value in the WTCNT counter Set the TME bit in the WTCSR register 1 The count starts in watchdog timer mode During operation in watchdog timer mode write 0x00 to the counter periodically so that it does not overflow When the counter overflows the WDT sets the WOVF flag in the WTCSR register to 1 and generates a reset of the type specified by the RSTS bit The counter then continues counting Using interval timer mode When the WDT is operating in interval timer mode an interval timer interrupt is
16. 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 Description TI7 TI6 TI5 TI4 TI3 TI2 TH TIO 0 0 0 0 0 0 0 EXTEST 0 0 0 0 0 1 0 ener 0 1 1 0 UDI reset negate 0 1 1 1 UDI reset assert 1 0 1 UDI interrupt ho le ho fh Ea Other than above Reserved 5 4 2 Data register SDDR The data register SDDR is a 32 bit register comprising the two 16 bit registers SDDRH and SDDRL that can be read and written to by the CPU The value in this register is not initialized by a NOT TRST or CPU reset Table 28 Data register SDDR SDDR 0x08 Field Bits Size Volatile Synopsis Type 31 0 32 RO Operation These bits store the SDDR value DR Data When read Returns current value When written Updates current value Reset 0 5 4 3 Bypass register SDBPR The bypass register SDBPR is a 1 bit register that cannot be accessed by the CPU When bypass mode is set in SDIR SDBPR is connected between the TDI pin and TDO pin of the UDI 40 58 8011247 Rev 5 ST40 core support peripherals 300 series User debug interface UDI 5 4 4 Interrupt factor register SDINT The interrupt factor register SDINT is a 16 bit register that can be read and written from the CPU When a UDI interrupt command is set in the SDIR Update IR using the UDI pin the INTREQ bit is set to 1 While SDIR has the UDI interrupt command the SDINT register is connected between UDI pins TDI and T
17. 2 Using interval timer mode 27 2 58 8011247 Rev 5 ky ST40 core support peripherals 300 series Contents 4 Timer unit TMU 28 4 1 FOIOS AAP AA AS 28 4 2 Blockdiagram 28 4 3 Register configuration 29 4 4 Register descriptions 30 4 4 1 Timer start register TMU TSTR 30 4 4 2 Timer constant registers TMU TCOR 31 4 4 3 Timer counters TMU TCNT 31 4 4 4 Timer control registers TMU TCR 32 45 Operation 33 4 5 1 Counter operation 33 4 5 2 TCNTocounttiming 35 4 6 NAI eras arica WA EER AAA EIA 35 4 7 Usage Noles SPECTET 35 4 7 1 Register WIGS spi accented s Rex E RUE Y RR SOR RE desea den 35 4 7 2 TCNT register reads 35 User debug interface UDI 36 5 1 Block diagram zii ess Robe ERR tta RE DEERE EDGE Ek OEE eR RES 36 5 2 Pin CONIQUKANON ss ss Ee ES BE chseudstodses case ag hoes eee DR 37 5 3 Register configuration 38 54 Register descriptions
18. A to D IPRA to IPRD Interrupt priority registers A to D IPRA to IPRD are 16 bit read write registers These four registers set priority levels from O to 15 for on chip peripheral module interrupts which are part of the CSP They are used for the legacy SH peripherals common to ST40 parts The IPRA to IPRC registers are initialized to Ox0000 by a reset IPRD is initialized to OxDA74 Table 34 lists the relationship between the interrupt sources and the IPRA to IPRD bits Table 34 Relationship between the interrupt sources and the IPRA to IPRD bits Register Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPRA TMUO TMU1 TMU2 Reserved IPRB WDT Reserved Reserved Reserved IPRC Reserved Reserved Reserved UDI IPRD IRLO IRL1 IRL2 IRL3 a For reserved bits the read value is undefined Only O should be written 8011247 Rev 5 51 58 Interrupt controller INTC ST40 core support peripherals 300 series 6 6 2 52 58 As listed in Table 34 four sets of on chip peripheral modules are assigned to each register 4 bit groups bits 15 to 12 bits 11 to 8 bits 7 to 4 and bits 3 to 0 are set with values from 0x0 0000 to OxF 1111 Setting 0x0 means priority level O masked OxF is priority level 15 highest priority Interrupt control register ICR The interrupt control register ICR is a 16 bit register that sets the input signal detection mode for external interrupt input pin NMI and indi
19. DO and can be read as a 32 bit register The high 16 bits are O and the low 16 bits are SDINT Only 0 can be written to the INTREQ bit from the CPU While this bit is 1 the interrupt request continues to be generated and must therefore be cleared to O by the interrupt handler This register is initialized by NOT_TRST or when in the test logic reset state Table 29 Interrupt factor register SDINT SDINT 0x14 Field Bits Size Volatile Synopsis Type 153 dis l RES Operation Reserved RES When read Undefined When written Write O Reset Undefined 0 1 RO Shows the existence of an interrupt request from the UDI interrupt command The interrupt request can be cleared by Operation writing O to this bit from the CPU When 1 is written to this bit INTREQ the existing value is retained When read Returns current value When written Updates current value Reset 0 8011247 Rev 5 41 58 User debug interface UDI ST40 core support peripherals 300 series 5 5 Operation 5 5 1 TAP control Figure 9 shows the internal states of the TAP control circuit These conform to the state transitions specified by JTAG The transition condition is the TMS value at the rising edge of TCK The TDI value is sampled at the rising edge of TCK and shifted at the falling edge The TDO value changes at the falling edge of TCK When not in the Shift DR or Shift In a transition to NOT_
20. I etc A A Prescaler To each channel h hi Ch2 re 0 C s Y Interrupt Y Interrupt Y Interrupt Counter unit control unit Counter unit control unit Counter unit control unit TONT1 i i Y Y Bus interface Internal peripheral module bus es Note Signals with 1 4 1 16 and 1 64 the Po frequency supplied to the on chip peripheral functions 8011247 Rev 5 ky ST40 core support peripherals 300 series Timer unit TMU 4 3 lt Register configuration Table 17 summarizes the TMU registers All addresses are given as offsets relative to the TMU base address TMUBASE Refer to the system address map for the value of TMUBASE Table 17 TMU registers base address P4 OxFFD8 0000 Initialization Initial Access Channel Name Abbreviation RW Power Manual value Offset size on reset reset Timer Common start TMU TSTR RW Initialized Initialized Ox00 0x04 8 register Timer constant TMU TCORO RW Initialized Initialized AERE 0x08 32 FFFF register O 0 Timer TMU TCNTO RW Initialized initialized OXFFFF loxoc 32 counter O FFFF Timer control TMU TCRO RW initialized Initialized Ox0000 0x10 16 register O Timer
21. NTC registers 51 6 6 1 Interrupt priority registers A to D IPRA to IPRD 51 6 6 2 Interrupt control register ICR 52 6 7 INTC operation 53 6 7 1 Interruptseguence 53 6 7 2 Nested interrupts 54 REVISION history 55 8011247 Rev 5 ky ST40 core support peripherals 300 series Preface Preface Comments on this manual should be made by contacting the local STMicroelectronics sales office or distributor Document identification and control Each book carries a unique identifier of the form nnnnnnn Rev x where nnnnnnn is the document number and x is the revision Whenever making comments on this document quote the complete identification nnnnnnn Rev x ST40 documentation suite The ST40 documentation suite comprises the following volumes 32 bit RISC Series ST40 Core Architecture Manual 7182230 This manual describes the architecture and instruction set of the ST40 previously known as ST40 C200 core as used by STMicroelectronics ST40 Micro Toolset User Guide 7379953 This manual describes the ST40 Micro Toolset and provides an introduction to OS21 It covers the various code and cross development tools that are provided in the toolset how to boot OS21
22. PC can be set Accesses which are not determined by the peripheral bridge to be a bad address or a bad opcode are forwarded to the appropriate peripheral If the peripheral determines the access address is not of the correct size or access type for the accessed register or if the access address does not map onto a legitimate register the result of the operation is undefined Information on the correct size access type and address for each register is given in the peripheral architectural elsewhere in this manual The peripheral subsystem does not support locked transactions Its bus interface ignores the STbus lock signal on an incoming request and does not generate a corresponding lock signal in its response All ST40 CPU cores are tolerant of this behaviour However the peripheral subsystem may be accessed using another bus initiator In this case the access 8011247 Rev 5 11 58 Peripheral bridge ST40 core support peripherals 300 series 2 3 1 12 58 method and hence the type of STbus transaction involved may require care Refer to the documentation for the bus initiator being used Peripheral bridge registers Address map Table 5 Peripheral bridge registers address map Abbreviation VCR_L P4 address OxFFFF FFFC Register description Version control register low 4 bytes VCR_H OxFFFF FFF8 Version control register high 4 bytes Register definitions PBR VCR_L T
23. STP2 bit in the STBCR to 1 halts the clock supply to the TMU Use of this function allows for further reduction of power consumption in sleep mode Whilst the clock is stopped the TMU retains its state from before the clock was stopped User break controller stop function This function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating Use of this function prevents use of the user break controller 8011247 Rev 5 ky ST40 core support peripherals 300 series Clock power and reset control CPRC Transition to user break controller stopped state Setting the MSTP5 bit of the CPRC STBCR2 to 1 stops the clock supply and causes the user break controller to enter the stopped state The following procedure sets the MSTP5 bit to 1 and enters the stopped state 1 Initialize UBC BBRA and UBC BBRB to 0 2 Initialize UBC BBCR to 0 3 Make a dummy read of UBC BBCR 4 Read CPRC STBCR2 Set the MSTP5 bit in the read data to 1 and write back 5 Make two dummy reads of CPRC STBCR2 If an exception or interrupt occurs while performing these steps make sure the values of these registers are not changed in the exception handling routine Do not read or write the following registers while the user break controller clock is stopped UBC BARA UBC BAMRA UBC BBRA UBC BARB UBC BAMRB UBC BBRB UBC BDRB UBC BDMRB UBC BRCR If these registers are read or writt
24. Section 5 4 3 UDI SDBPR Bypass register SDBPR on Undefined RW 1 page 40 Interrupt factor register see UDI SDINT Section 5 4 4 Interrupt factor register OX00000000 wo 32 SDINT on page 41 a Initialized when the NOT_TRST pin goes low or when the TAP is in the test logic reset state b The value read from UDI is fixed OxFFFF FFFD c 1 can be written to the LSB using the UDI interrupt command 5 4 5 4 1 Register descriptions Instruction register SDIR The instruction register SDIR is a 16 bit register that can only be read by the CPU In the initial state bypass mode is set The value command is set from the serial input pin TDI SDIR is initialized by the NOT TRST pin or in the TAP test logic reset state When this register is written to from the UDI writing is possible regardless of the CPU mode Operation is undefined if a reserved command is set in this register Table 26 Instruction register SDIR SDIR 0x00 Field Bits Size Volatile Synopsis Type Operation See Table 27 Bits 15 8 TI7 TIO When read Returns current value When written Writes ignored Reset OxFF 7 0 8 RO Operation Reserved RES When read Undefined When written Writes ignored Reset Undefined 8011247 Rev 5 39 58 User debug interface UDI ST40 core support peripherals 300 series Table 27 Bits 15 8 Bit 15 Bit
25. TRST 0 a transition is made to the Test Logic Reset state e e e IR state TDO is in the high impedance state e asynchronously with respect to TCK Figure 9 TAP control state transition diagram 42 58 Test Logic Reset a 0 1 O Y 6 Run Test ldle Select DR Scan 0 Capture DR 0 Shift DR 0 1 Exit1 DR pa ANENE Exit2 DR 1 EE AA Update DR 1 0 Y 0 Pause DR 0 1 1 ON FRA E Select IR Scan 0 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 0 Naa 1 m EN Exit2 IR 1 Update IR f 8011247 Rev 5 1 0 ON ST40 core support peripherals 300 series User debug interface UDI 5 5 2 5 5 3 5 5 4 UDI reset A power on reset is effected by an SDIR command A reset is effected by sending a UDI reset assert command and then sending a UDI reset negate command from the UDI pin see Figure 10 The interval required between the UDI reset assert command and the UDI reset negate command is the same as the length of time the reset pin is held low in order to effect a power on reset Figure 10 UDI reset UDI UDI reset assert reset negate UDI pin Chip internal reset CPU state Normal Reset Reset processing UDI interrupt The UDI interrupt function generates an interrupt by setting a command value in SDIR from the UDI The UDI interrupt is of general excepti
26. able 6 PBR VCR_L PBR VCR_L OxFFFF FFFC Field Bits Size Volatile Synopsis Type 0 1 Y ST40 received an error response RW Operation This bit is set by the ST40 core when an error response is P received by its initiator port implementation dependent ERR REC When read Returns current value When written Updates current value Reset 0 1 1 Y An error response has been sent RW This bit is set by the bridge hardware if an error response is Operation sent by the bridge to the STBus It indicates that an earlier ERR_SNT request to the bridge was invalid When read Returns current value When written Updates current value Reset 0 2 1 A request for an undefined control BW register has been received This bit is only set if the PBR can not find a block to send the Operation request to BAD_ADDR q i When read Returns current value When written Updates current value Reset 0 8011247 Rev 5 g ST40 core support peripherals 300 series Peripheral bridge g Table 6 PBR VCR_L continued PBR VCR_L OxFFFF FFFC Field Bits Size Volatile Synopsis Type 3 1 7 ST40 received an unsolicited RW response Operation ee in EL when an unsolicited response UNSOL i When read Returns current value When written Updates current value Reset 0 5 1 Mi eee sed a ERE opcode RW This bit is set by the bridge hardware if a r
27. ad Returns current value When written Updates current value Reset 0x00 a To write use a word size access with the upper byte set to Ox5A Watchdog timer control status register WTCSR The watchdog timer control status register WTCSR is an 8 bit readable writable register containing bits for selecting the count clock and timer mode and overflow flags WTCSR is initialized to 0x00 only by a power on reset using the RESET pin It retains its value in an internal reset due to WDT overflow To write to the WTCSR register use a word size access with the upper byte set to OxA5 To read WTCSR use a byte size access Table 14 CPRC WTCSR CPRC WTCSR 0x0c Field Bits Size Volatile Synopsis Type 2 0 3 Clock select 2 to 0 RW In conjunction with WTCSR2 CKS3 these bits select the clock used for the WTCNT count from 16 clocks obtained by dividing Operation the peripheral clock P The overflow periods can be calculated CKS2 0 using the appropriate frequency See Table 15 on page 25 When read Returns current value When written Updates current value Reset 0x0 8011247 Rev 5 23 58 Clock power and reset control CPRC ST40 core support peripherals 300 series 24 58 Table 14 CPRC WTCSR continued CPRC WTCSR OxOc Field Bits Size Volatile Synopsis Type 3 1 Yes Interval timer overflow
28. an be referenced by the CPU UDI registers on CPU side Register name UDI SDIR Description Instruction register see Section 5 4 1 Instruction register SDIR on page 39 Initial value OxFFFF CPU side Type RO P4 address OxFFF00000 Area 7 address Ox1FF00000 Access size 16 UDI SDDR SDDRH Data register H see Section 5 4 2 Data register SDDR on page 40 Undefined RW OxFFF00008 Ox1FF00008 32 16 UDI SDDRL UDI SDBPR Data register L see Section 5 4 2 Data register SDDR on page 40 Bypass register see Section 5 4 3 Bypass register SDBPR on page 40 Undefined Undefined RW OxFFF0000A Ox1FF0000A 16 UDI SDINT Interrupt factor register see Section 5 4 4 Interrupt factor register SDINT on page 41 0x00000000 RW OxFFF00014 Ox1FF00014 16 a Initialized when the NOT TRST pin goes low or when the TAP is in the test logic reset state 38 58 8011247 Rev 5 g ST40 core support peripherals 300 series User debug interface UDI Table 25 UDI registers on UDI side Register HAD ide 9 Description Initial value name Type Access size Instruction register see UDI SDIR Section 5 4 1 Instruction register Ec RW 32 SDIR on page 39 Data register see Section 5 4 2 AB DBE Data register SDDR on page 40 Ungannad ae Bypass register see
29. andard i sooo sus a RR Ua 36 Standby 18 20 31 32 44 47 51 Status register SR 47 49 50 54 Status register field BL soriana 20 47 49 50 54 A OS ER ee eo 54 Em 9 10 STBUS scrape ita ini a eta ene UREA EE aten 9 10 li C ETT 11 San MO 30 33 35 Synchronization 35 37 T TON Tiana Ren RR E DEG KNA ee 30 35 NOOR CPP 31 33 TOR uix ed ber ERA ERE 31 33 35 TMU 18 28 33 35 45 50 51 TMUBASE corcra eiiean AA 29 TODD se EE ann EE Seda a ie Ee d 14 TPSC 220 a EE OO EE be 31 33 35 Type 12 14 18 19 23 26 28 30 32 39 41 43 PTT 47 52 U UNF hoes aha Ng ede ewe bee ea LNAG 31 33 35 UNIE s see a 32 33 35 V VOR sacked ex ce ER GRO Rx EO ENS 12 Volatile 12 14 18 19 23 26 30 32 39 41 52 ky 8011247 Rev 5 57 58 ST40 core support peripherals 300 series Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice select
30. applications from ROM and how to port applications which use STMicroelectronics OS20 operating systems Information is also given on how to build the open source packages that provide the compiler tools base run time libraries and debug tools and how to set up an ST Micro Connect OS21 User Manual 7358306 This manual describes the generic use of OS21 across the supported platforms It describes all the core features of OS21 and their use and details the OS21 function definitions It also explains how OS21 differs from OS20 the API targeted at ST20 platforms OS21 for ST40 User Manual 7358673 This manual describes the use of OS21 on ST40 platforms It describes how specific ST40 facilities are exploited by the OS21 API It also describes the OS21 board support packages for ST40 platforms ky 8011247 Rev 5 5 58 Preface ST40 core support peripherals 300 series Conventions used in this guide General notation The notation in this document uses the following conventions sample code keyboard input and file names variables code variables and code comments equations and math screens windows dialog boxes and tool names instructions Hardware notation The following conventions are used for hardware notation 6 58 REGISTER NAMES and FIELD NAMES PIN NAMES and SIGNAL NAMES 8011247 Rev 5 ky ST40 core support peripherals 300 series Architectural overview 1 Architectural overview Figure 1 shows a
31. cates the input signal level at the NMI pin This register is initialized by a power on reset or manual reset Table 35 Interrupt control register INTC ICR Bit name Bit Size Volatile Synopsis Type 7 1 IRL pin mode RW Selects whether pins IRL3 to IRLO are used for level encoded Operation interrupt requests or for four independent interrupt requests p 0 IRL pins are used for level encoded interrupt requests IRLM 1 IRL pins are used for four independent interrupt requests When read Returns current value When written Updates current value Reset 0 8 1 NMI edge select RW Selects whether the falling or rising edge of the interrupt request signal to the NMI is detected Operation ih interrupt request is detected on the falling edge of NMI NMIE 1 an interrupt request is detected on the rising edge of NMI input When read Returns current value When written Updates current value Reset 0 9 1 NMI block mode RW Selects whether NMI requests are held pending or immediately detected when the SR BL bit is 19 Operation 0 NMI interrupt requests are held pending when SR BL 1 NMIB 1 NMI interrupt requests are detected when SR BL 1 When read Returns current value When written Updates current value Reset 0 8011247 Rev 5 ky ST40 core support peripherals 300 series Interrupt controller INTC 6 7 6 7 1 g
32. constant TMU TCOR1 RW Initialized Initialized psi 0x14 32 register 1 1 Timer TWUTCNT1 RW initalized initialized OFFFF lox18 ae counter 1 FFFF Timer control TMU TCR1 RW Initialized Initialized O0x0000 Ox1C 16 register 1 Timer constant TMU TCOR2 RW Initialized Initialized OTER 0x20 32 FFFF register 2 2 Timer TMU TCNT2 RW initalized initialized OXFFFF loxoa a2 counter 2 FFFF Timer control TMU TCR2 RW initialized Initialized Ox0000 0x28 16 register 2 8011247 Rev 5 29 58 Timer unit TMU ST40 core support peripherals 300 series 4 4 4 4 1 30 58 Register descriptions Timer start register TMU TSTR TMU TSTR is an 8 bit readable writable register that specifies whether the channel 0 to channel 2 timer counters TCNT are operated or stopped TMU TSTR is initialized to 0x00 by a power on reset or manual reset Table 18 TMU TSTR TMU TSTR 0x04 Field Bits Size Volatile Synopsis Type 0 1 Counter 0 start RW Specifies whether timer counter 0 TMU TCNTO is operated or Operation stopped STRO When read Returns current value 0 TMU TCNTO count operation is stopped Wh tt M 1 TMU TCNTO performs count operation Reset 0 1 1 Counter 1 start RW Specifies whether timer counter 1 TMU TCNT 1 is operated or Operation stopped STR1 When read Returns current value 0 TMU TCNT1 count operation is stopped Wh tt Bea 1 TMU TCNT1 performs
33. count operation Reset 0 2 1 Counter 2 start RW Specifies whether timer counter 2 TMU TCNT2 is operated or Operation stopped STR2 When read Returns current value When written 0 TMU TCNT2 count operation is stopped 1 TMU TCNT2 performs count operation Reset 0 7 3 5 Reserved RES Operation When read 0 When written Invalid Reset 0 8011247 Rev 5 ky ST40 core support peripherals 300 series Timer unit TMU 4 4 2 4 4 3 Timer constant registers TMU TCOR The TCOR registers are 32 bit readable writable registers There are three TCOR registers one for each channel When a TCNT counter underflows while counting down the TCOR value is set in that TCNT which continues counting down from the set value The TCOR registers are initialized to OxFFFF FFFF by a power on or manual reset They retain their contents in sleep mode Table 19 8 TMU TCOR registers TMU TCOR n where n 0 2 0x08 n OxOC Field Bits Size Volatile Synopsis Type 31 0 32 Timer constant RW Operation This value is used to reload TCNT n when it underflows When read Returns current value When written Updates current value Reset OxFFFF FFFF Timer counters TMU TCNT The TCNT registers are 32 bit readable writable registers There are three TCNT registers one for each channel Each TCNT counts down on the input clock selected by TPSC2 t
34. dates 19 Mar 2010 D Revalidation Added new paragraph at end of Section 2 3 Peripheral subsystem 19 Oct 2011 5 access errors on page 11 Deleted Module detection from chapter 2 8011247 Rev 5 55 58 Index ST40 core support peripherals 300 series Index A L Address 9 10 12 29 38 43 49 54 A OR HR Paya nG 11 Address map 29 ANDE 2 ES 35 M B Memory secre rsa ene 54 Memory block 14 Bad addr 12 Mod id 14 badi addr sisse Poe need E Rs 11 Mod vers ooo 13 Bad ODE x usse dr nce s OR Re wes 13 Mode 17 18 20 31 32 36 37 39 40 43 44 47 bad ee RE N AA DEC 51 54 Bot TD ius codi a ai cce s 14 MSTP nani 17 20 Break i c ew EXER ER eed BEE ER 54 N C NAME iscsi peas are urs 38 39 46 47 52 Channel 28 30 33 35 NM cee sea KEER EE 20 45 47 50 52 53 Clock pause function 20 Control registers CR 12 13 18 19 29 31 33 O 36 38 43 47 52 PR ares warp PARERE e neared 9 10 18 On chip peripheral 20 37 49 51 52 Opcode iussa Ree Reeve CX RA 13 a P Data edet A WA kn KA VEM 36 40 DiS UG is a ewe tes qo 36 Packet router 13 PBR VCR_H mai 9 11 E PBR VCR L coco 9 11 PBR VCR L perr flags 11 Ett SAU ON OE EE ag 12 Ao RE ume re EE da 54 Event sites exe ee ERES RE REEL 49 54 Peripheral bridge
35. ditions si ER ek e ETE Ee EUR we IA Ec as 10 2 2 Bridge registers e dass dide basis e RA aded Rn a Ed ended esas 11 2 3 Peripheral subsystem access errors 11 2 3 1 Peripheral bridge registers 12 3 Clock power and reset control CPRO 15 3 1 POGUNGS EE dxdt ee ned KAG EE EE OE OR Og 15 3 2 Register configuration 16 3 3 Powerdown modes 16 3 3 1 Types of powerdown modes 16 3 3 2 Module clock control register CPRC STBCR 18 3 3 3 Module clock control register 2 CPRC STBCR2 19 3 3 4 Sleep mode 20 3 4 Module clock stop functions 20 3 4 1 Timer unit TMU ER Ee EE a Moe ever x EUR EER IE EER P 20 3 4 2 User break controller stop function 20 3 5 Watchdog IMEF EA sne ntad tenisie AAA 22 3 5 1 Watchdog timer counter WTCNT 23 3 5 2 Watchdog timer control status register WTCSR 23 3 5 3 Watchdog timer control status register 2 WTCSR2 26 3 5 4 Notes on register access 26 3 6 Using the WDT 27 3 6 1 Using watchdog timer mode 27 3 6
36. e and interval timer mode e In watchdog timer mode an internal reset is generated on counter overflow In this Case a power on reset or manual reset can be selected e In interval timer mode an interval timer interrupt is generated on counter overflow e Any of sixteen counter input clocks can be selected scaled from the PO 8011247 Rev 5 15 58 Clock power and reset control CPRC ST40 core support peripherals 300 series 3 2 Register configuration Table 8 CPRC registers Name Abbreviation R W Initial value P4 address poca Module clock control STBCR R W 0x00 OXFFCO 0004 8 register Watchdog timer counter WTCNT R AWO ox00 OxFFCO 0008 paa Watchdog timer b R 8 control status register WICSA BA 0X00 OxFFCO 000C lu 180 Weddle ook contol STBCR2 Rw 0x00 OxFFCO 0010 8 register2 Watchdog timer b R 8 control status register 2 WE Ee RNV soe OxFFCOOD1C W 46 a The registers in Table 8 can also be accessed using translation This is described in the ST40 Core Architecture Manual Chapter 3 Resources accessible through P4 and through translations b Use word size access when writing Perform the write with the upper byte set to 0x5A OxA5 or OxAA respectively Byte and longword size writes cannot be used Use byte access when reading 3 3 Powerdown modes The ST40 supports several power down modes These modes allow selective halting of CPU and CSP functions allowing core
37. ecifies starting and stopping of timer operation Operation 0 up count stopped WTCNT value retained initial value TME 1 up count started When read Updates current value When written Returns current value Reset 0 a The up count may not be correct if WT IT is modified while the WDT is running Table 15 Clock select 3 to 0 CKS3 CKS0 bit descriptions Description CKS3 CKS2 CKS1 CKSO Clock Division Clock Division Overflow Ratio Ratio 2 N Period 0 1 32 initial value 5 123 us i 1 1 64 6 246 us d 0 1 128 7 492 us 1 1 256 8 984 us 0 1 512 9 1968 us j 1 1 1024 10 3 936 ms i 0 1 2048 11 7 872 ms 1 1 4096 12 15 744 ms 0 1 16384 14 63 ms j 1 1 65536 16 253 ms 0 0 1 131072 17 506 ms 1 1 1 262144 18 1s 0 1 524288 19 2s i 1 1 2097152 21 8s 0 1 8388608 23 32s 1 1 33554432 25 129s a Assuming a peripheral clock P of 66 MHz Note The up count may not be performed correctly if bits CKS3 CKSO are modified while the WDT is running Always stop the WDT before modifying these bits Overflow periods shown have minor rounding errors g 8011247 Rev 5 25 58 Clock power and reset control CPRC ST40 core support peripherals 300 series 3 5 3 3 5 4 26 58 Watchdog timer control status register 2 WTCSR2 The watchdog timer control status register WTCSR2 is an 8 bit readable writable register containing bits for sel
38. ecting an extended range of clock selectors WTCSR2 is initialized to 0x00 only by a power on reset using the RESET pin It retains its value in an internal reset due to WDT overflow To write to the WTCSR2 register use a word size access with the upper byte set to OxAA To read WTCSR2 use a byte size access Table 16 CPRC WTCSR2 CPRC WTCSR2 0x0c Field Bits Size Volatile Synopsis Type 7 1 5 Reserved RES Operation Reserved Reserved When read Returns 0 When written Ignored Reset 0 0 1 Yes Watchdog timer overflow flag RW This bit augments the CKS2 0 fields of WTCSR to form a 4 bit prescalar selection O default value CKS2 0 bits retain their existing meaning and Operation the prescalar selection is fully compatible with legacy ST40 cores 1 CKS2 0 bits select from 8 new prescalar values as shows in Table 15 on page 25 CKS3 When read Returns current value When written Sets the value Reset 0x0 Notes on register access The watchdog timer counter WTCNT and watchdog timer control status registers WTCSR WTCSR2 differ from other registers in being more difficult to write to Writing to WTCNT WTCSR and WTCSR2 These registers must be written to with a word transfer instruction They cannot be written to with a byte or longword transfer instruction When writing to WTCNT perform the transfer with the upper byte set to Ox5A and the lower byte containing the
39. ed by acceptance of an interrupt in the CPU 2 Theinterrupt source flag should be cleared in the interrupt handler To ensure that an interrupt request that should have been cleared is not inadvertently accepted again read the interrupt source flag after it has been cleared before clearing the BL bit or executing an RTE instruction 6 7 2 Nested interrupts To handle nested interrupts an interrupt handler should include the following procedure 11 A o NG a 8 Branch to a specific interrupt handler corresponding to a code set in INTEVT The code in INTEVT can be used as a branch offset for branching to the specific handler Clear the cause of the interrupt in each specific handler Save SSR and SPC to memory Clear the BL bit in SR and set the accepted interrupt level in the interrupt mask bits in SR Handle the interrupt Set the BL bit in SR to 1 Return the SSR and SPC from memory Execute the RTE instruction When this procedure is followed in order an interrupt of higher priority than the 1 being handled can be accepted after clearing BL in step 4 54 58 8011247 Rev 5 ky ST40 core support peripherals 300 series Revision history 7 g Revision history Table 36 Document revision history Date Revision Changes Initial release Unknown A Derived from document 7988763A modified to describe the 300 series CSP Unknown B Miscellaneous updates Unknown Miscellaneous up
40. en the value cannot be guaranteed Cancelling the user break controller stopped state The clock supply can be restarted by setting the CPRC MSTP5 bit of STBCR2 inside the CPRC to O The user break controller can then be operated again The following steps clear the MSTP5 bit to 0 to cancel the stopped state This is similar to the transition to the stopped state 1 Read CPRC STBCR2 then clear the MSTP5 bit in the read data to 0 and write the modified data back 2 Make 2 dummy reads of CPRC STBGR2 If an exception or interrupt occurs while processing these steps make sure the values in these registers are not changed in the exception handling routine Examples of stop start ing the user break controller The following are example programs Transition to user break controller stopped state 1 Initialize BBRA and BBRB to 0 mov 0 RO mov 1 BBRA R mov w RO R1 mov 1 BBRB R mov w RO R1 2 Initialize BBCR to 0 8011247 Rev 5 21 58 Clock power and reset control CPRC ST40 core support peripherals 300 series mov 1 BBCR R1 mov w RO R1 3 Dummy read BRCR mov w R1 RO 4 Read STBCR2 then set MSTP5 bit in the read data to 1 and write it back mov 1 STBCR2 R1 mov b RO R1 or H 1 RO mov b RO R1 5 Twice dummy read STBCR2 mov b R1 RO mov b R1 RO
41. en low for a certain period when powering on regardless of whether or not JTAG is used This differs from the IEEE specification Fix at ground TDI TDO Data input pin Data output pin Input Output The data input pin Data is sent to the UDI circuit by changing this signal in synchronization with TCK The data output pin Data is sent to the UDI circuit by reading this signal in synchronization with TCK Open Open NOT ASEBRK BRKACK Emulator pin Input output Dedicated emulator pin Open a Pulled up inside the chip When designing a board that allows use of an emulator or when using interrupts and resets via the UDI there is no problem in connecting a pull up resistance externally b When designing a board that enables the use of an emulator or when using interrupts and resets via the UDI drive NOT TRST low for a period overlapping NOT RESET at power on and also provide for control by NOT TRST alone The maximum frequency of TCK TMS TDI TDO is product specific refer to the appropriate datasheet The TCK frequency must always be kept below that of the ST40 s on chip peripheral module clock 8011247 Rev 5 37 58 User debug interface UDI ST40 core support peripherals 300 series 5 3 Table 24 Register configuration Table 24 shows the UDI registers Except for SDBPR these registers are mapped in the control register space and c
42. equest with an Operation unsupported opcode is received by that module from the BAD OPC packet router When read Returns current value When written Updates current value Reset 0 15 6 4 8 1 Reserved RES Operation Reserved When read Undefined When written Write 0 Reset Undefined 31 16 16 Module version RO Operation Used to indicate module version number MOD VERS When read Returns 0x0000 When written Ignored Reset 0x0000 a The values of these fields is an integration option these values may differ between systems see Integration options on page 8 8011247 Rev 5 13 58 Peripheral bridge ST40 core support peripherals 300 series PBR VCR_H Table 7 PBR VCR_H PBR VCR_H OxFFFF FFF8 Field Bits Size Volatile Synopsis Type 15 0 16 Module identity RO Operation Used to identify module MOD ID When read Ox2BA2 9 When written Ignored Reset Ox2BA22 23 16 8 Bottom memory block RO Operation Used to identify bottom memory block BOT MB When read OxFC When written Ignored Reset OXFCA 31 24 8 Top memory block RO Operation Used to identify top memory block TOP MB When read OxFF When written Ignored Reset OxFF a The values of these fields is an integration option These values may differ between systems see Section Integration options 14 58 8011247 Rev 5 g ST40 core support peripheral
43. ion or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with pr
44. k cycles The other circuits are reset and initialized in an ordinary reset The UDI circuit has 6 internal registers SDBPR SDBSR SDIR SDDRH and SDDRL these last 2 together designated SDDR and SDINT The SDBPR register supports the JTAG bypass mode SDIR is the command register SDDR is the data register and SDINT is the UDI interrupt register SDIR can be accessed directly from the TDI and TDO pins Figure 8 Block diagram of UDI circuit Interrupt reset ASEBRK BRKACK x controller wo ad o o o 7 B o p E E E d o 5 de o a 8011247 Rev 5 ky ST40 core support peripherals 300 series User debug interface UDI 5 2 lt Pin configuration Table 23 shows the UDI pin configuration Table 23 UDI pins Pin name TCK Description Clock pin VO Input Function Data is transferred from data input pin TDI to the UDI circuit and data is read from data output pin TDO in synchronization with this signal When not used Open TMS Mode pin Input The mode select input pin Changing this signal in synchronization with TCK determines the meaning of the data input from TDI The protocol conforms to the JTAG IEEE Std 1149 1 specification Open NOT TRST Reset pin Input The input pin that resets the UDI This signal is received asynchronously with respect to TCK and effects a reset of the JTAG interface circuit when low NOT TRST must be driv
45. n overview of the core support peripherals architecture Figure 1 Core support peripherals architecture P Peripheral bridge STBus STBus port target p target Peripheral bus initiator Peripheral bus VCR H VCR L O The CSP comprises the peripheral bridge and core support peripherals The peripheral bridge comprises an STBus target module and a peripheral bus initiator module These modules receive requests and place responses on to the STBus through its port The STBus requests pass to the peripheral bus initiator that places the requests on the peripheral bus These are received and serviced by the appropriate peripheral to generate responses These then pass back through the peripheral bus initiator to the STBus target to provide STBus responses The peripheral bridge has two registers the version control high VCR_H and low VCR_L registers If an access is made to a peripheral which is not present in a particular implementation of the CSP an STBus error is issued in response Such an incorrect access is recorded in the VCR error flags The following peripherals are included in the CSP e Clock power and reset controller CPRC The ST40 and CSP modules support several power down modes These modes allow selective halting of CPU and CSP functions allowing core power consumption to be reduced A watchdog timer WDT provides s
46. o TPSCO in the timer control register TCR When a TCNT counter underflows while counting down the underflow flag UNF is set in the corresponding timer control register TCR At the same time the timer constant register TCOR value is set in TCNT and the count down operation continues from the set value The TCNT registers are initialized to OXFFFF FFFF by a power on or manual reset They retain their contents in sleep mode Table 20 TMU TCNT registers TMU TCNT n where n 0 2 0x0C n 0x0C Field Bits Volatile Synopsis Type 31 0 32 3 Timer counter RW Operation 32 bit down counter counts on the clock selected by TMU TCR When read Returns current value When written Updates current value Reset OxFFFF FFFF 8011247 Rev 5 31 58 Timer unit TMU ST40 core support peripherals 300 series 4 4 4 32 58 Timer control registers TMU TCR The TCR registers are 16 bit readable writable registers There are three TCR registers one for each channel Each TCR selects the count clock and controls interrupt generation when the flag indicating timer counter TCNT underflow is set to 1 The TCR registers are initialized to Ox0000 by a power on or manual reset They retain their contents in sleep mode Table 21 TMU TCR n TMU TCR n where n 0 2 0x10 n 0x0C Field Bits Size Volatile Synopsis Type 2 0 3 Timer prescaler RW Ope
47. of 15 1111 indicates the highest level interrupt request interrupt priority level 15 A value of O 0000 indicates no interrupt request interrupt priority level O Figure 12 shows an example of an IRL interrupt connection Table 32 and Table 33 show IRL pins and interrupt levels Figure 12 Example of IRL interrupt connection Interrupt ND i ME Priority encoder requests IRL3 to IRLO A noise cancellation feature can be built in at system integration time See the appropriate product datasheet to check which mechanisms are available Table 32 IRL3 to IRLO pins and interrupt levels IRL3 IRL2 IRL1 IRLO Interrupt priority level Interrupt request 0 0 0 0 0 No interrupt request 0 0 0 1 1 Level 1 interrupt request 0 0 1 0 2 Level 2 interrupt request 0 0 1 1 3 Level 3 interrupt request 0 1 0 0 4 Level 4 interrupt request 0 1 0 1 5 Level 5 interrupt request 0 1 1 0 6 Level 6 interrupt request 0 1 1 1 7 Level 7 interrupt request 1 0 0 0 8 Level 8 interrupt request 1 0 0 1 9 Level 9 interrupt request 1 0 1 0 10 Level 10 interrupt request 1 0 1 1 11 Level 11 interrupt request 1 1 0 0 12 Level 12 interrupt request 1 1 0 1 13 Level 13 interrupt request 1 1 1 0 14 Level 14 interrupt request 1 1 1 1 15 Level 15 interrupt request 8011247 Rev 5 ky ST40 core support peripherals 300 series Interrupt controller INTC 6 5 3 6 5 4 The priority
48. on interrupt operation type with a branch to an address based on VBR and return effected by means of an RTE instruction The exception code stored in control register INTEVT in this case is 0x600 The priority of the UDI interrupt can be controlled with bits 3 to O of control register IPRC The UDI interrupt request signal is asserted when after the command is set UPDATE IR the INTREQ bit of the SDINT register is set to 1 The interrupt request signal is not negated until O is written to the INTREQ bit by software and there is therefore no risk of the interrupt request being unexpectedly missed While the UDI interrupt command is set in SDIR the SDINT register is connected between TDI and TDO Bypass The UDI pins can be set to the bypass mode specified by JTAG by setting a command in SDIR from the UDI 8011247 Rev 5 43 58 User debug interface UDI ST40 core support peripherals 300 series 5 6 5 6 1 5 6 2 44 58 Usage notes SDIR command Once an SDIR command has been set it remains unchanged until initialization by asserting NOT_TRST or placing the TAP in the test logic reset state or until another command other than a UDI interrupt command is written from the UDI SDIR commands in sleep mode Sleep mode is cleared by a UDI interrupt or UDI reset and these exception requests are accepted in this mode In standby mode neither a UDI interrupt nor a UDI reset is accepted 8011247 Rev 5 ky ST40 core s
49. ovisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 58 58 8011247 Rev 5 ky
50. power consumption to be reduced It is the responsibility of software to ensure that sequence leading to entering a power down mode is safe 3 3 1 Types of powerdown modes The following power down modes and functions are provided e sleep mode ST40 CPU only only the I clk is stopped e sleep mode ST40 CPU CSP both the I and P clks are stopped e module clock stop function CSP modules 16 58 8011247 Rev 5 g ST40 core support peripherals 300 series Clock power and reset control CPRC Table 9 and Table 10 show e the conditions for entering these modes from the program execution state e the status of the CPU and CSP e the method of exiting each mode Table 9 Powerdown mode sleep Entering conditions SLEEP instruction executed CPRC Operating or halted depends on whether the clock generator halts P clk as well as I clk Status CPU CSP Halted registers held Operating or halted depends on whether the clock generator halts P clk as well as I clk Exiting method Interrupt Reset Table 10 Powerdown mode economy Entering conditions CPRC Setting MSTP bit to 1 in STBCR or STBCR2 Operating Status CPU CSP Operating store queue and UBC may be stopped Specified modules halted Exiting method Clearing MSTP bit to 0 Reset a See Table 12 on page 19and Table 13 on page 23 8011247 Rev 5 17 58 Clock power
51. rals 300 series Peripheral bridge 2 2 1 Peripheral bridge The ST40 core support peripherals CSP are handled by a single STBus target port in the peripheral bridge The peripheral bridge allocates a partition of the address space to each peripheral device and is responsible for steering incoming STBus requests to the correct peripheral The peripheral bridge also does the following e Maintains a pair of revision and status registers called PBR VCR_L and PBR VCR_H These indicate the version of the peripheral subsystem and keep track of certain types of incorrect access which may have been made to the peripheral bridge e Handles requests to unmapped areas which are addresses allocated to the peripheral bridge but not mapped onto a peripheral Address map This section describes how the peripheral bridge allocates address space to each peripheral device Virtual addressing of a CPU s own CSP peripherals Software can access the CSP peripherals and peripheral bridge at the virtual addresses shown in Table 1 These addresses are identical to those used on earlier ST40 series Use of these addresses guarantees maximum compatibility with software for other ST40 variants The registers in Table 1 can also be accessed using address translation in the UTLB or PMB This is described in the ST40 Core Architecture Manual Chapter 3 Resources accessible through P4 and through translations Table 1 CSP virtual memory map Subs
52. ration Specifies the TCNT count clock for channel n When read Returns current value 000 counts on P94 001 counts on P916 TPSC 010 counts on Pdy64 When written 011 counts on P9256 100 counts on Pdy1024 101 reserved do not set 110 reserved do not set 111 reserved do not set Reset 000 4 3 2 Reserved RES Operation Reserved When read 0 When written Ignored Reset 0 5 1 Underflow interrupt control RW Operation Controls enabling or disabling of interrupt generation when the P UNF status flag is set to 1 indicating TCNT underflow UNIE When read Returns current value When written 0 interrupt due to underflow TUNI is not enabled 1 interrupt due to underflow TUNI is enabled Reset 0 7 6 2 Reserved RES Operation Reserved When read 0 When written Ignored Reset 0 8011247 Rev 5 ky ST40 core support peripherals 300 series Timer unit TMU 4 5 4 5 1 Table 24 TMU TCR n continued TMU TCR n where n 0 2 0x10 n 0x0C Field Bits Size Volatile Synopsis Type 8 1 3 Underflow flag RW Operation Status flag that indicates the occurrence of underflow When read 0 TCNT has not underflowed UNF 1 TCNT has underflowed O clears flag to O When written 1 write Ignored Reset 0 15 9 7 Reserved RES Operation Reserved When read 0 When written Ignored Reset 0 Operation
53. request Joyesedwog SR Cascaded i3liali input IPR IPRA to IPRD A Bus interface INTC 6 3 Pin configuration Table 30 INTC pins Name Abbreviation VO Description Nonmaskable interrupt input pin NMI Input mud nonmaskabig interrupi request Input of interrupt reguest signals Interrupt input pins IRL3 TO IRLO Input maskable by 13 to IO in the status register SR 46 58 8011247 Rev 5 ST40 core support peripherals 300 series Interrupt controller INTC 6 4 6 5 6 5 1 Register configuration Table 31 INTC registers Register PAR Initial name Description Type value P4 Address Size INTC ICR Interrupt control see Section 6 1 INTC RW c OXFEDO 0000 16 features on page 45 INTC IPRA Interrupt priority level A see Section 6 6 1 RW Ox0000 OXFFDO 0004 16 on page 51 INTC IPRB Interrupt priority level B see Section 6 6 1 RW Ox0000 loxFFDO 0008 16 on page 51 INTC IPRC Interrupt priority level C see Section 6 6 1 RW ox0000 OXFFDO 000C 16 on page 51 INTC IPRD Interrupt priority level D see Section 6 6 1 RW OxDA74 OXFFDO 0010 16 on page 51 a The registers in Table 31 can also be accessed using translation This is described in the ST40 Core Architecture Manual Chapter 3 Resources accessible through P4 and through translations b
54. reset either asserted from outside the ST40 or due to watchdog timer overflow Table 12 CPRC STBCR2 CPRC STBCR2 0x10 Field Bits Size Volatile Synopsis Type 0 1 Module stop 5 UBC RW Specifies the clock supply Id to the ST40 core internal UBC user break controller module is stopped Operation 0 UBC operating initial value MSTP5 1 clock supply to UBC is stopped When read Returns current value When written Updates current value Reset 0 1 1 Module stop 6 SQ RW Specifies the clock supply Id to the ST40 core internal SQ store queue module is stopped When stopped SQ functions Operation are unavailable 0 SQ operating initial value METES 1 clock supply to SQ is stopped When read Returns current value When written Returns current value Reset 0 7 2 6 Reserved RES Operation Reserved RESERVED When read Returns 0 When written Ignored Reset 0 a See Section 3 4 2 User break controller stop function on page 20 ky 8011247 Rev 5 19 58 Clock power and reset control CPRC ST40 core support peripherals 300 series 3 3 4 3 4 3 4 1 3 4 2 Note 20 58 Sleep mode Transition to sleep mode If a SLEEP instruction is executed the clock generator stops the I clk to the CPU and the program execution state transfers to sleep mode The CPU halts but its register contents are retained The CSP module
55. ridge has two registers e PBR VCR_L e PBR VCR_H The following access types are supported by these registers e load four bytes e store four bytes If any other type of access is presented to either of these register addresses the result of the operation is undefined Peripheral subsystem access errors All accesses made to the peripheral subsystem are decoded by the peripheral bridge according to Table 1 on page 9 If an access address is not within a 256 byte address range starting at one of the addresses given in Table 1 on page 9 it is referred to as a bad address A bad address access also occurs if an access is attempted to a peripheral not present in that particular CSP configuration If an access is not one of the permitted types for the peripheral bridge this is referred to as a bad opcode Table 4 shows the permitted access types for the peripheral bridge Table 4 Permitted access types Access types load store byte load store two bytes load store four bytes load store eight bytes Accesses which are determined to be to a bad address causes the BAD ADDR bit in the PBR VCR L PERR FLAGS field to be set See Table 6 on page 12for details Accesses which are determined to be to a bad opcode causes the BAD OPC bit in the PBR VCR L PERR FLAGS field to be set See Table 6 on page 12for details If an access is determined to be both a bad address and a bad opcode either or both of the bits BAD ADDR BAD O
56. s 300 series Clock power and reset control CPRC 3 3 1 Clock power and reset control CPRC The CSP contains a control module for clock power and reset control CPRC The clocks for the ST40 300 CPU core I clk and CSP P clk are generated by other modules which are not described in this manual Refer to the specific product datasheet for information about clock generation The CPRC also contains a watchdog timer WDT This is a single channel timer which can be used to provide either watchdog or interval timer functions Features Clock supply to the ST40 The I and P clocks are supplied to the ST40 by a clock generator elsewhere in the device When the ST40 CPU executes the SLEEP instruction it requests that the clock generator remove the I clk until the next wake up event NMI interrupt or reset When the I clk is stopped the clock generator may also stop the P clk or it may leave it running For example there may be register bits in the clock generator that allow software to determine whether or not the P clk is removed Such a feature is product specific and the appropriate manuals and datasheets should be consulted TMU clock stop The CPRC allows the P clk supply to the TMU to be stopped See Section 3 3 2 Module clock control register CPRC STBCR on page 18 Watchdog timer e The WDT has the following features See Section 3 5 Watchdog timer on page 22 e Can be switched between watchdog timer mod
57. s may continue to operate or may also be halted This depends on whether the clock generator halts the P clk as well and is product specific Exit from sleep mode Sleep mode is exited using an interrupt NMI IRL or on chip peripheral module or a reset In sleep mode interrupts are accepted even if the BL bit in the SR register is 1 SPC and SSR should be saved to the stack before executing the SLEEP instruction Exit by interrupt When an NMI IRL or on chip peripheral module interrupt is generated sleep mode is exited and interrupt exception handling is executed The code corresponding to the interrupt source is set in the INTEVT register If the following conditions arise 1 a device is using binary coded IRL that is INTC ICR IRLM 0 see Table 35 Interrupt control register INTC ICR on page 52 and 2 awake up interrupt is signalled through the IRL input to the INTC and 3 the P clk supply has been stopped during sleep mode then it is possible for the ST40 to be woken and to take the interrupt even if the signalled IRL level is lower than the current SR IMASK level Exit by reset Sleep mode is exited using a power on or manual reset either asserted from outside the ST40 or due to a watchdog timer overflow Note that a watchdog timer overflow cannot occur if the CSP is halted during the sleep because the WDT will not count when its clock is stopped Module clock stop functions Timer unit TMU Setting the M
58. setting v Set initial timer counter value v Start count Note When an interrupt is generated clear the source flag in the interrupt handler If the interrupt enabled state is set without clearing the flag another interrupt is generated Auto reload count operation Figure 6 shows the TCNT auto reload operation Figure 6 TCNT auto reload operation TCNT value TCOR value set in TCNT WA on underflow H 00000000 STRO STR2 g 8011247 Rev 5 ST40 core support peripherals 300 series Timer unit TMU 4 5 2 4 6 4 7 4 7 1 4 7 2 TCNT count timing Operating on internal clock Any of five count clocks P94 P 16 P 64 Pdy256 or P 1024 scaled from the peripheral module clock can be selected as the count clock using the TPSC2 to TPSCO bits in TCR Figure 7 shows the timing Figure 7 Count timing when operating on internal clock Po Internal clock Interrupts There are three TMU interrupt sources comprising underflow interrupts Underflow interrupts can be generated on any combination of channels O 1 and 2 An underflow interrupt request is generated for each channel according to the AND of UNF and the interrupt enable bit UNIE in TCR The TMU interrupt sources are summari
59. tandard reset and interval timer features Further details are provided in Chapter 3 Clock power and reset control CPRC on page 15 e Timer unit TMU This peripheral comprises three independent 32 bit timer channels These are based on auto reload type 32 bit down counters which can generate ky 8011247 Rev 5 7 58 Architectural overview ST40 core support peripherals 300 series interrupts when they underflow Further details are provided in Chapter 4 Timer unit TMU on page 28 e User debug interface UDI This module is a serial input output interface conforming to the JTAG IEEE 1149 1 TAP Controller Architecture Further details are provided in Chapter 5 User debug interface UDI on page 36 e Interrupt controller INTC This module allows masking and prioritizing of interrupts generated by other peripherals non maskable sources and external modules The INTC works with 15 levels of interrupts Further details are provided in Chapter 6 Interrupt controller INTC on page 45 Integration options 8 58 Several of the peripherals have a number of integration options which may create architectural differences Where these options arise they are highlighted in this manual and where applicable the default option is given For example some reset values can be altered by system integrators All integration dependent features of the CSP are highlighted in this manual 8011247 Rev 5 ky ST40 core support periphe
60. terrupts are generated at the same time they are handled according to the default order listed in Table 33 8011247 Rev 5 49 58 Interrupt controller INTC ST40 core support peripherals 300 series Updating of interrupt priority level setting registers A B C and D should only be performed whilst the BL bit in SR is set to 1 To prevent erroneous interrupt acknowledgment first read any of the interrupt priority level setting registers then clear the BL bit to 0 This secures the necessary timing internally Table 33 ST40 core interrupt exception vectors and rankings interrupt source NTEVT pret PR mir Default initial value setting unit NMI OxiCO 16 High IRL3to IRLO F 0x200 15 y IRL3to IRLO E 0x220 14 IRL3 to IRLO D 0x240 13 IRL3 toIRLO C 0x260 12 IRL3 to IRLO B 0x280 11 IRL3to IRLO A Ox2A0 10 IRL3 toIRLO 9 0x2C0 9 IRL3 to IRLO 8 0x2E0 8 IRL3 toIRLO 7 0x300 7 IRL3 toIRLO 6 0x320 6 IRL3to IRLO 5 0x340 5 IRL3to IRLO 4 0x360 4 IRL3to IRLO 3 0x380 3 IRL3 toIRLO 2 0x3A0 2 NAE IRL3 toIRLO 1 Ox3CO JA IRLO 0x240 15to 0 13 IPRD 15 12 IRL1 Ox2A0 15 to 0 10 IPRD 11 8 IRL2 0x300 15 to 0 7 IPRD 7 4 IRL3 0x360 15 to 0 4 IPRD 3 0 Low UDI RESERVED Ox600 15to0 0 IPRC 3 0 EXP a F E TMUO TUNIO 0x400 15 to O 0 IPRA 15
61. uests sent according to the priority levels set in interrupt priority registers A to C IPRA to IPRC and the INTPRI registers Lower priority interrupts are held pending If two of these interrupts have the same priority level or if multiple interrupts occur in a single 8011247 Rev 5 53 58 Interrupt controller INTC ST40 core support peripherals 300 series D mm rum module the interrupt with the highest default priority or the highest priority within its IPR setting unit is selected The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits I3 to 10 in SR of the CPU If the request priority level is higher than the level in bits 13 10 the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU The CPU receives an interrupt at a break in instructions The interrupt source code is set in INTEVT SR and program counter PC are saved to SSR and SPC respectively The block bit BL mode bit MD and register bank bit RB in SR are set to 1 The CPU jumps to the start address of the interrupt handler the sum of the value set in the vector base register VBR and 0x0000 0600 The interrupt handler may branch with the INTEVT register value as it is offset to identify the interrupt source This enables it to branch to the handling routine for the individual interrupt source Note 1 The interrupt mask bits 13 to 10 in SR are not chang
62. upport peripherals 300 series Interrupt controller INTC 6 6 1 Interrupt controller INTC The interrupt control system ascertains the priority of interrupt sources and controls interrupt requests to the CPU The INTC registers set the order of priority for each interrupt allowing the user to handle interrupt requests according to the user controlled priorities INTC features The INTC has the following features 15 levels of interrupt priority can be set By setting the three interrupt priority registers the priorities of CSP module interrupts can be selected from 15 levels for different request sources Four interrupt request lines IRLs are provided IRLs can be encoded as independent interrupts or 16 level encoded interrupts Noise cancellation is product specific Please refer to the product datasheet Software can also provide a noise cancelling function by checking the NMI input level bit Masking of NMI requests by the SR BL bit can be set It is possible to specify whether NMI requests are to be masked or accepted when the SR BL bit is 1 Other compatible interrupt controllers can be cascaded with the INTC 8011247 Rev 5 45 58 Interrupt controller INTC ST40 core support peripherals 300 series 6 2 Block diagram Figure 11 shows a block diagram of the INTC Figure 11 INTC block diagram NMI Input IRI3 to IRLO control TMU Priority VCR identifier WDT Interrupt
63. ystem Description P4 start address PBR Version control registers OxFFFF FFF8 CPRC Clock power and reset control OxFFCO 0000 TMU Timer unit OxFFD8 0000 INTC Interrupt controller OxFFDO 0000 CSP physical addressing Each ST40 core in a product has a specific physical base address CSPBASE at which its CSP peripherals and peripheral bridge are located CSPBASE is defined in the product manual or datasheet Each CSPBASE address is aligned on an 8 Kbyte boundary Table 2 defines the physical base address of each peripheral subsystem relative to CSPBASE Bits 9 0 of the physical address encode the offset of each register relative to its own subsystem base address 8011247 Rev 5 9 58 Peripheral bridge ST40 core support peripherals 300 series 10 58 Table 2 CSP physical memory map Subsystem Description P4 start address PBR Version control registers CSPBASE OxOFF8 CPRC Clock power and reset control CSPBASE 0x0000 TMU Timer unit CSPBASE 0x0600 INTC Interrupt controller CSPBASE 0x0400 Any STBus initiator in the system including other ST40 cores can access the CSP registers using the physical addressing defined in Table 2 Software running on an ST40 could use the physical address derived from Table 2 with its own value of CSPBASE to provide an alternative address range for its own CSP peripherals However the addresses in Table 1 are preferred for maximum software compatibility
64. zed in Table 22 Table 22 TMU interrupt sources Channel Interrupt source Description Priority 0 TUNIO Underflow interrupt 0 High 1 TUNI1 Underflow interrupt 1 2 TUNI2 Underflow interrupt 2 Low Usage notes Register writes When performing a register write timer count operation must be stopped by clearing the start bit STRO to STR2 for the relevant channel in the timer start register TMU TSTR TCNT register reads When performing a TCNT register read processing for synchronization with the timer count operation is performed If a timer count operation and register read processing are performed simultaneously the TCNT counter value before the count down operation is read using the synchronization processing 8011247 Rev 5 35 58 User debug interface UDI ST40 core support peripherals 300 series 5 5 1 36 58 User debug interface UDI The user debug interface UDI is a serial input output interface conforming to JTAG IEEE 1149 1 and IEEE Standard Test Access Port Architecture The UDI uses 6 pins TCK TMS TDI TDO NOT_TRST and NOT ASEBRK BRKACK The pin functions and serial transfer protocol conform to the JTAG specifications Block diagram Figure 8 shows a block diagram of the UDI The TAP test access port controller and control registers are reset independently of the chip reset pin by driving the NOT TRST pin low or setting TMS to 1 and applying TCK for at least 5 cloc

ST40 core support peripherals (ST40-300)

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