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Xcell Journal: Issue 40

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1. poe Pee Ieee Hoc memory aire win er Sake as Sosa pegged ed ool a 100 000 gc under Steet VOT Online log pele of 200 and beyond Wih all major bus andar such 25V devions UO het ull PCT comple lead cimes ders dee fate SI speeds over 200 LS uai Dip get ane ee ms EA E qu port paleo z zu ala HE 8 5 DEVICES 5 3 35 2388224552383 Xm m PIER E rin EL Rees CS ELI E OC ees e XCSWXL Ne 466 SK 196 616 112 1204 EE OIE Xu Mtana ias Se Oconee Xm e LE Im UE xam entrer sx v x d xem hee wel ee toe ae 1885 Se Seno a Y w E E oer vn eo Y ps m M CO ri XC9500 and CoolRunner CPLDs From highspeed nerwoding to power conscious portable designs g
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4. A ot o Be miler or aadar tens han gored ae 3 pletion by Geer Lagi CORE rm A The optimal solution andthe one imple mented by the Xilinx ues duce 2K primitives combined with ane Primitive uses four Block See RAM sod resource utzon of 9296 Tn addition the ulipleing logica includ ed with generated coe a second scenario consider imple mentation of a mukiplier wh has a 25 bit signed number on one input and a 35 bit unsigned number on second inpr and wes the Vinx Ebr The elution requires splinting the operanda inno slices dha are no larger than the input width of he mukiplier primitive 18 bin The width of B is 35bits and an additional bir is needed o B as signed he fill precision produc will be The implementation produced by the Multiply Generator LogiCORE is shown in Figure 3 The ix on the left hand of the diagam represent individual 18 bit multiplier primitives and the final output is shown as 600 Not only i thie imple entation dhe optimal solution it aliy provides you with all he additional logje and adders trees required vo imple ment multiplier Pipelining the calcula can drsmarkly increase multiplier throughput pipelining registers shown dashed boxes in Figure 3 The core lows you minimise or maximise the amo
5. m 4 forward they ill Mm Ie ccn ew Application Integrated Circus namely repgrammabili or availabili o and zero nonrecurring engineering NRE costs m wiring deny and fally active of the routing archi tecture allows connec tions to occur in large quantities and ar high speed thus enabling the hh high bandwidth inter connect necemary filly expla de These advantages com sore e the infrastructure that has enabled devel opment of the innovative IP Immersion superstructure Enhanced Performance Through IP immersion Te ture embodies the concept that high bandwidth hard IP blocks implement 4 in or standard cell logic can be immersed within the matrix of FPGA CLB Configurable log Blacka The women arny iret ideally suited for ehis pires ri importan properties m IPlmmemion t archie 2 con area The VirteILIPmerion accommodates virtually any pre defined rectilinear shape Programmable routing Through its step and tepeat of diles the seg memed routing of FPGA arcitecure allows the creation of specific on ampi and fram at every CLB Borde In other words because the routing architecture has some wiring segment that seart wi
6. each design poet enabling them vo focus their design efforts on masi Insight Electronics Offers Two Virtex l Development Boards Supporting either an XC2V40 or an XC2V1000 Virtex l FPGA these development kits allow designers to experiment with implement many of the new features and technologies found on chip only in Xilinx Platform FPGAs ier ee E Development Kits bti lag cis The new family fom integrates many advanced system level fea tures into a configurable single chip FPGA The Vitel architecture incorpo rate pre engineered on chip stem de ments such at DCMs dig clock man aper flexible system imerhces with technology and signal integrity control wing XCITE Impedance TEchnology any technology advancement like the architec design engineers often need very aspects of new func tions Designers need tol to shonen the leaning curve whether they are proving a new idea veing an interface to an exiting or device validating a safi TP or just gaining heuer understanding of howto technology The new development kits from ight Electonics address this need allowing designers ro tent new Vine ture quickly easily and inexpensively The kits provide the ideal develop ment platform for general purpose testing and experim
7. of he core primitive ial thar is required and the DDR egies can be inferred your source code Figure 1 demonstrates DDR and HyperTiansport implemented in Vie and lu vat correct names m p Virtex Il IP Immersion Technology Enables Next Generation Platform FPGAs sses by Eid Goong eo esd p The Fd Programmable Gate Amy Revolution began when Rom founder of Xilinx conceived the FPGA Abandoning the reins of sum produce architecture Rou uid of 16 LUT Lok Up Tb each accompanied by flip flop circuit and all interconnected wih programmable routing uva revolutionary fst deployed in 1984 in the XC2000 fare isl the basis ofall FPGA devices today opie the unprecedented in Hale of programmable logie and continual dances in de compet of the device ardens ament w the power Rosis vision thatthe FPGA lae the af time and many peo posed in the marketplace rm Introducing the Revoltonry FA 1 Today in 2001 however another revolu in programmable logie has begun with the introduction of Xilinx Platform FPGAs At the heart of this rev olution is the ability o integrate fune tions of other dicte silicon devices such as microprocessors within an FPGA platform The integration provided by the Platform
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10. Pet erf Esch embedded multiplier lock is 18518 2 complement signed multiplier The MULTISXIS primitive illustrated in Figure 5 has ewo 18 bit inputs and a 36 bit product These blocks ate opi mined for performance and low power consumption and ean vastly ouperform an 18x18 muliplier implemented in general logic Figur 5 primire seurce These multipliers can be coupled with the block RAMs and dedicated high speed interconnects between the multiplier and RAM blocks Allowing for efficient multiply accumulate Ber constructs Design Optimization Take Advantage of Leftover Multipliers and Block RAMs Here are some ways to make your designs more efficient You ean either perform a logie shift of 17 input bite by holding the MSB input low ot perform an arithmerie shift of an 18 bit 2vcomplement number effec tively sign entending the A con ventional CLB based shifer would have to an of n mukipleners each wih n inputs and require large amount of routing resources In any case shifters larger than 18 bis and barrel shifers of any length wil require external OR gating of the lock ROM State Machines Because block RAMs can be configured with any of initial values they make excellent registered ROMs As shown in Figure 1 one half of the block can be as a FSM Finite State Machine and the other half can be used
11. Viet lng dimid pede and 106 erp DDR com chante ord dios The of the HyperTanspor link have uing thie Eye panem was set to ch every 10 seconds Condon The new HypeTiaepore femel Wo homos 50 5 ere VO gives you very high ped dif ston feel UO The HyperTransport Aa Kinane or consisting of the HyperTasport VO sages of muxidemux and ri Lol lesen wil be availble on arde Ws 50 mY enee design and aplicacion Xiine will M various venions of T s Duo lt a ome in Quer Qa Kose 1 Vire U DC Dink ware automatically maintains the correer Because HyperTransport calls for double data rate the DDR registers in the ae used DDR is the equivalent of dual edge clocking bur is implemented with two docked 180 degrees apart and the resulting ouput twice the frequency of the clock Vitex tl devices designed with double dat and differential signaling applications in mind so che rowing resources and tim ing are easily accommodated The Viten contin DDR registers far inpar ouput and implementations Te the ouput or State DDR registers
12. maintains a igh impedance mate MO counts will continue to increase and sc will dock speeds The Vitel architec te makes this situation livable by offering the high speed IO standards without the difficulties of extemal termination resistors r p m How XCITE Works his ond rl maton hane on b XOT Vio parli tin ndi ndi v pl ond pd domin ss miata edad wih dv The np ol ka dt ped imped lib PG wc opr iin of Te an wh poll man of non parabal XII moy bo he vg YC s inibe ST sod snp hor The lo rer a conde lo defn pine on th oe devi d tg VO bants s ev han dd fin pin V and WRP If XI n bank pins e oak rem Mero o hv the ane th POS vo c ath ampla rm 500 XE D borra vla arr Martins he rtp e pcs During es ndn om rsh VO imped sg TEs hse yd bain rh ru n he estan iT vn ular OBUF HSTL 1 DCI oda c O dia out DCI NET rame IOSTANDARD Loci 25 Wiha cu nane oma d fe len Me PAD PAD ond eta
13. support for the extemal PHY ASSP The core LVDS buffers paired with dedicated DDR registers in the data path and LVTTL VO buffers in the FIFO path The intemal data rare is reduced by expanding the 16 bit words in DDR format on the PLA interface o 64bit ourword single edge clocked format running at half the PLA dock rate The core utilizes the DCM as shown in Figure 2 The DCM generates and ertemal clocks vo meet the sggresive system jitter requirements The cores implement sac alignment ofthe received to the clock by using the DPS Digital Phase Shif function of the DCM The DPS module permits very m leor multiple linkes or ports The PLA sink block sores daa received for a particular linkin a single FIFO buffer along with the link address information decoded from the control word preceding the bun When dara is received the address infor matin sete from the recived con tol wond The address and data are writen imo the sink FIFO Twobic Block RAMs are used to the perchan nel FIFO status betwen the PLA interface and the users aplication The PLA sink block tenets the FIFO informa tion according to contens of the FIFO The PLA source section decodes the FIFO stats channel How contol information and writes it o the dual porr black for each channel The contol infor tation is by the PLA core vo deter sin
14. OOOO ELE LULU TTT 108 BOLL Os see N RI 18 V 1I Figure t Virtexl Architecture Overview Lm m 11 5 Fiold Programmablo G Arrays Programmable blocks provide the interlace between package pins and the intemal configurable logic Most popular and leading edge UO standards are supported by the programmable 108s The internal configurable logic includes four major elements organized in a regular Configurable Logie Blocks provide functional elements for combinatorial and synchronous loge including basic storage elements BUFTs 3state buffers associated with each element drive dedicated segmentable horizontal routing resources Block SelectRAM memory modules provide large 18 storage elements of True Dual Port RAM Multiplier blocks are 18 bit x 18 bit dedicated multipliers DCM Digtal Clock Manager blocks provide sell calbrating fully digital solutions lor clock distribution delay compensation cock multiplication and division and coarse and fine grained tock phase shifting now generation of programmable routing resources called Active interconnect Technology Interconnects all of these elements Tho general routing matrix GAM is an array of routing switches Each programmable element is tied to a switch matrix allowing connections to the general routing matrix The overall programmable
15. SED Yo tere duy ete p This 2A when D 50 Therefore you should hone a apace wih 2 cur handling capability However an addi ional capacitor sharing current wich it thar de of Ch on be seduced The Bil of Materials shown in Table 2 specifies choices for the other led component Considerations Many ICs contin low voltage and curent eel analog funcions They lho require high cure high speed Compu for driving lager poser Ineegrating both of these fine tions within a single chip is the simnuitaneous yer opposing for lew noise and bigh alleviate many newer Ce have separe ground and power pound pin connections The is to localize the high curent high peed noe an independent loop which doc noc interfere withthe more sensitive lw level analog control Seton The is very important for he convert e to funcion properly Signal Ground and Power Ground PGND shoud be separated ensure hat the high pibe ouent in the Power Ground never with the sensitive connected to Sigal Ground They should only be con ead at one point acral atthe negative Side of ther the input or output capacitor 15 addition capacitor Cy should beas close ro pint 2 and 4 as pole The heat of the chip is mainly thr
16. especially when comes for free Networking System Pack for Optical Neh ty Ron Diog jis Mag ex mardi om rs elg Sete Sd Ei ur disc Xin ba developed of LogiCORE property blocks to perform the System Packer Interface SPD funcion between the Physical PHY and Dara Link layer devices fot POSISDH Packet Over SONETISynchtonous Digital Hierarchy fiber applications The cores dese the exploding demands of ner work IP Inernet Protocol raffi by ens ing Xilinx devices are compatible with the Optical Intemerworking Forums OIF PICA Phase 2 standard well as the SAT URN Development Group Level 4 PLA The cores assure compliance with the OC 192 data ander Standard by moving IP packets ar a data rate in exces of to Markt The itebce cores referred to PLA cores meke we of unique available only in the Xilinx Vinex 1I Pharm FPGA ach including DCM Digital Clock Manager enhanced Block RAM and high spend LVDS VO Combined with FPGA DDR Double Data Ra che PLA cores can support data ranes up to per pin paie rm working with the OIF and che wok backbones doubling every ix nine Mode months to provide a high per Forum to promo SPLA Phase 2 mane formance scalable stem lun dand Mong w
17. king Systeml0 Technology Promises High Speed Connectivity Across Multiple 1 0 Standards As implemented via Virtex1l Platform FPGAs SystemlO technology addresses both the physical interfaces and networking protocols for high bandwidth connectivity and throughput ty Rin Ron AS eof pens ni nc Moors Lam which compu rsen qed il ie spray uy M monde ht pred be ami By acute mar don 35 yeas The pese n pose spn ive enabled ver higher nid ne The som Lowey har bemes kare only doled die quad ey Se us Tian helle Fefomance faye ate bd ei fe dual by equal cf rice ter by de liia af the WO bur Wide pras numm emerging standards POS PHYP Led 4 10 Fe Chane ang eken pori nn iri Flam FPGAS ales th prion ef ean wih pen ein pnt re tomas a lod de yid imf and he nr 1 0 Sag Sondre Vines deve w per saying madre M ect high plis ru fe lamen merely dois above 180 oniy SSTL Gab Trina Log or HSTL High Spes Loge IO sana m Many standards inchding dhe adi tional switching standards of LVCMOS Low Voltage CMOS memory interfaces of HSTL and SSTL and even LVDS Low Voltage Diferential Signaling are not keeping pace with the increased demand foc mare bandwidth
18. tion The audio evelopment in Flam Haile MP3 encoding development and decoding platform that can recognition Be med m kek ee Viel Demet aon mam spreme diagnosis and level design It audio dams The sonam and a JTAG por The ation kit supports of hands on and LEDs provide normal the commonly UO pore bs 20d simple breadboard designs Esse and sna sige for peripherals Abo Incaded four irate but to implementa teal application simplify de use of highspeed logie porn hire Becomes wl ned he de bond pele scl tin plugs acer Aver dau dil Tha omaes hardware sealed by opi wid he Tni logic na Specific spplicatons By plugging im i Development Patr ier and provide acces to many of the bilding Macs or cur of the Verl Dewdopment key signals in a dein The signal on compan outer Plier thom in Fue pods frum he logie naar plug dey Iewederdopmen ya need 2VIG00 FPGA pots il he imo the connector on board xo your a inet far the bond ie deam high ped connections DEA Theres aa aed wet for po PCI bu wich can Ths configuration maker it easy to probe FC bow when
19. KCHV Package 40 250 soo 1000 1500 2000 3000 4000 sooo 8000 10000 csaa e 2 120 172 172 2 16456 200 264 324 FEST 392 456 42 528 FEISS 720 em FRIST su 1 104 1108 1108 B6575 32 B6725 356 55 esa em Notes 1 Al devices in a particular package are pin out footprint compatible Inaction the FG456 and packages are compatbie as re tne and FF1152 packages Virtex Il Ordering Information Vitex ordering information is shown in Figure 7 Example XC2V1000 5FGA56C ERES co as o XE le Number of Pins 4 5 6 Package Type Figure 7 Virtexl Ordering Information Virtex Il Data Sheet The complete data sheet can be found on com It contains the following modules DS031 1 Vitel 1 5V FPGAS Introduction and Ordering information Module 1 DS031 2 Vitexll1 5V FPGAS Functional Description Module 2 DS031 3 Vitexll1 5V FPGAS DC and Switching Characteristics Module 3 05021 4 Vitexll 1 5V FPGAS Pinout Tables Module 4 m 8 Referee iu 1 m u 3 3 m m 3 ue u
20. po View The Future rg aom at made it much ee for to produce bener designa ine ime We deigned de Vitex architecture from the very beginning technology plat orm on which we can build genera ios of he family This platform i optimised for use with both hand core and Sot cores allowing wt you the of programmable logic dong with the performance advantages of ded hand logic al tightly imme el with kigh level develop ment wols dar significantly increase your pouty past ege Peformance priority with of our is continuously improve the performance dene and We work very with our partners o refine four manufacturing process creating increasingly smaller geometry CMOS tech nologies that result in ster denser devices foc less cost we wil a new gen eration every year with increasingly advanced proces technology In addition we continuously developing new ways to improve device architectus to get ener performance thraigh enhanced mousing and design Today you can purchase with up to 6 million system gas a huge advancement in density over previous FPGAS Ya within or four years we ill 50 milion gate devices enough to build very complet very high per formance stems on
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22. exploiting the parallelism thar inherent in DSP mathematical models Xilinx m created the highest performance DSP platform ever The vaa logie exces present in Xilinx Viel FPGAs enable the creation of fully parallel structures for the greatest possible computational power and bandwidth These ar ributes give you the performance advantage of an ASIC Application Specific Integrated Circuit without the added expense of inflexibi vy long lesd times and hefty NRE Non Recurring Engineering The XuremeDSP Initiative delivers the highest performing programmable digital signal processing available today Computing capability is approaching one trilion muliply and accumulase opera tions per second 1 Tera more than 100 times faster than conven tional DSP solutions Vineet Platform FPGA Performance Leader The planform Figure 2 breaks new performance barriers with up to 600 bilion per second compared 8 8 billion per second fr conven tional DSP solutions This raw computa tional power allows you o implement the complex designs imaginable includ ing multiple high speed channels on a sin gle spem with reduced power con sumption and less board space Table 1 m DSP Processor Core blan MG wn to pion
23. mms EZR EES C messes 7 m 180855595 77 Wew 77 uo 3 u uma 3 domui ma ie SKE Table 2 ELZS64C Bound Bil sf Mati Ja Example Dosign The following design example will show you how easy it is to the EL7564C The following requirements are specified for the example Input voltage range Ving 45 55 voltage Vo 33V Max output voltage ripple 2 max current 1 4A Switching Frequency Fy 350 The schematic i showa Figure and the bill of material i shown in Table 2 sed ipee 1 EL7564C Cre VIN 5 Lm The falling sepa briefly cudine how dise the passive components exiled design discusion plese refet hance Application Note 18 Designing High DCDC Converter with the pe Sip Estimate your power requirement and fll out power v ll el you your power queen The power of your design ate influenced by many factory as shown in Table 1 Step 2 Choose the feedback seda divider The esto divider determines the cupa vg voie av MER is chosen to be IQ den Ros
24. offensa fll range of configu ron memory devices optimized for we with Xilinx FPGAs Our PROM product lies designed to meet same stringent demands our high performance FPGAS taking full advantage of the same advanced procesing technologies addicion they were developed in close cooperation with Xilinx FPGA designers for per formance and Our inayat amma provides a fast configuration solution available today and provides con method for reprogramming and soring large Xilinx FPGA bir meas This ily is JTAG ready and Boundry Sean enabled for raton and XC17V00 XC17S00 Our low cos XCITV and XCI7S families an ed configuration solution for cous sensitive applications XCI7V PROMs ate piaxcompatible with our XCIBV family o allow for a cose seduction migration your production volumes increase The XCU7S family is specially designed to provide low cost integrated solution foe Spartan families of FPGAs EVIE spa up Xtra E Yr Y Ta Ya 7 aT Te Malta cor E E Ms pa F x ca EEE poe raion Xerox XC E Xvo sem wm x x
25. 10 Using an interface dis IEEE andar is positioned to dive the conver gence of LAN and WAN technologie J E emerging serial chan ES Two of the most pop vir standards in his Fhe ad voi for pem age area SAN marker Fibre ee Channel ues opie ber cowl cables andlor evisted pir telephone wire provides both physical interfaces as well as various cores that support che network protocole With the transition from Shared busses to switched fabrics comes varey of different souceaynchronous parallel protocols The following are some of the leading source syachronous standards that are emerging RapidiO Originally organized vo sup port he processor and local bus mater the RapidIO interconnect architecture has been embraced by the nerwoding and sorag markens IndiniBand Founded by an industry consortium InfiniBand targets remote storage servens and neovorking devices Formerly known as LDT Lighting Transport HyperTiansport was developed by AMD and API to replace PCI in high speed computing applications Te hat grinel some in the ing space OIF SPIE Optical Imernerworking Forum Sytem Packet Interface Level XAU pronounced ZOW e Th
26. BI pit pm pm C coe DS pane ecm Samples Per Second DS Additionally Vinex devices feature Programmable Arrays Up o 10 milion syaem gates for paralel and posible DSP performance Tene of hundreds of channels per single device time market with SRAM technology nesofguraon during deve opment and in the eld Data Storage Up to 35 of True Dual Port Block RAM for implement Sion of large FFTs Fat Fourier Transforms video line buffen and aber memory intensive DSP func gr 3 Generar design eminent Up to 19 of ditibuted memo morage of coeficiems and Fonctions Up 10192 18218 embedded multipliers for optima implementation of high sped noe pipelined DSP functions lt Support up to 250 MH depending on bit wilh Multipliers unable building Mocks to high ped 32 bit mil pliers ideal fr high performance FFTs or xDSL able modems and equalizers for wireless modems satelites and Gigabit Ethernet Disuibuted aimee mukipliers con scd lookup tables for eficient Pipelined dara Fast cary chains for addition and look ahead arithmetic ing signals pipelined che through reg inen or memory Synem features such as high speed controlled impedance technol ogy
27. Blk Dium The DCM digit delay lines for high precision control af clock Phase and frequency Up to four DCM clack supa can drive global dock buffer inputs simultaneously and all DCM dock cups can simultaneously drive general touting resources including roue to out put buffert In addition you can che DCM outputs generare board level clocks off chip DOM Signal Description Figure 1 shows all of the inputs and out puts of the DCM including signals The DCM has the following WO signal CLKIN pin Clock Input to CLKFB pin Clock Feedback Input sequised to provide delay com ouspur RST input pin Resets the entire DCM m DSSEN input pin Enables the Digital Spread Spectrum DSS PSINCDEC input pin Increments when High decrements when Low the Phase Shift Factor PSEN input pin Phase Shift Enable ed in conjunction with PSINCDEC PSCLK input pin Phase Shift Clack sourced by ether CLKIN or any other dock source CLKO output pin Deb compenaed venion of CLKIN CLIQ output pin 90 of phase wih CLKISO output pin 180 out of phase wih CKO CLK270 output pin 270 out of phase wih CLKOX output Twice frequen ey of CLKIN and in phase with CLKO CLKOXI80 output pin he quency of CLKIN and 1807 of phase CIKO CLKDV
28. FPGAs comain a number of 18x18 Za complemen signed associat ed with the block Sele RAM memory This association allows high speed access to complex muleplicand coeffi iens thus supporting extremely high performance arithmetic To see why the multipliers are so valuable consider the nature of the FFT algorithm itself Ir essentially decomposes into series of mul ply accumulre functions Digital Clock Management implement OFDM the andthe must bein per fect synchronization Synchronizing to he dasa clock is always whereas carrier moneri only necessary im coherent receivers The dia dock must be recited so thatthe receiver wil sample the transmit daa symbols at the appropiate time alie appro nid incre dock fey cn be ingens ierit devel of permed in the domin Thee piti plc tions for Vill Digal Clock Manage DCM For example he inthe Vinee devices dong with a DDS Disc Digi Synthesia core can proide the complet ery demad Wai the incoming di The ning phase of ese duci ie by the cor dock and ex y adj bythe DEM timing coo The DCM dio ether fane sica ofthe amine fed dock dew nd bei The DCM cn abo dedi ihe pal the cd ne
29. Tining Analysis is delivered part of the ISE software and can easily kc as your progam mabe device checkpoint With rheupcom ing version 4 1 af ISE sofware you will abo have the option of wing Synopsys for FPGA verification ing language because the Fipe graphic imerfice suppor quick extraction of a tet suine either beginner ot expert level This automatic bench generation capa liy enhances checkpoine verification strategy operating good enl inea chat racks each module dur ing desia Design Module 1o Chip Veron There various verification methods and tools available for both the individual design modules and foc verifying the over all device HDL Simulation is an example verification option that at the module level or overall device level However high density design requirements ate driving the of new verification as well Static Timing Analysis Sate timing analysis STA is now wal erabliahed as chip design checkpoint and has been considered he rm You can bo create a STAMP model for any hed Xin high density device STAMP models let you integrate FPGA piirto pin delays ino spiele PC board ao the FPGA accurately represented in your overal spitema level analysis Farmal Verification 1n the upcoming venion 41i of Xilinx sofi wate formal verification tools
30. timing Xii design took ennie that designers and engineers make che most oftheir time verification supported STAMP Timing Modding Procedure and LMG Logie Modeling Group mart models The Xilinx ChipScope tegrated Logie Analyt is a revolutionary tool fr rine chip debugging Logie analysis jj can be ined ire atual deign and de behavior af any can be displayed lor analysis wing industry leading logie E r w Ras are extremely accurate Chipseope easily han des wide buses complex gera and multiple clocks which cus debug ging time bom weeks wo just few hours ChipScope with industry leaders tools including Agilent Technologies 16700 Serie logie and Synplicitys wok rom Platform to vnda new era in system platform design has begun The Platform FPGA fally integrates sofi and hard IP cores by part nering with the word leading technology companies By introducing the power house Vinee solution Xilin has ser the industry highest benchmark in performance and sibility Together the unique feature of the revolutionary Platform FPGA solution provide the ultimate launchpad fr sper consec sii DSP and processing applications With the rich feature set designers con develop new with Platform
31. Poincto point connection such as plementary solution is availible our benween a single PHY Layer and single manual customers With IP on ne Dara Link Layer device Suppor fot 256 ports sil for 5151 granularity in SONET SDH applications 192 and Fas Ebr granularity in Ethernet applications 100 prs data path Source synchronous clocking where the source of the dara provides a dara clock port addres Indication error control code 1VDS VO EFE 15963 1996 I ANSITIVEIA 1950 622 minimum data rate per line using double dara p Packet address delineation Information and erarcon trol coding sent in band with dara in both transmit and receive modes addition to supporting the ined PLA interface features the Xilinx PLA cores were developed With configurable FIFO buffers wing Vinerll Block RAM The Block RAM pro vides high performance data cco timmes and fur times increase density ine grained adjustments under 50 ps of the RDCLK Received Clock relative to the Received Data The fine res olution allows the RDCLK to be adjusted to the optimal sampling point relative co the eye pattern Not shown in Figure 2 are the PLA FIFO imerfice blacks for implementing the sin over previous The Ape Block RAM allows appropriate afin wo match the required
32. mr wm tm D X i2xee mm n x x pe pe xem ose wm ge x ime mm e DX xum unt mw y PE X erp x Xmas wwe 1 1 P xx T Jen Xo eax Ss Nata x a TESINE SS X OX DX X DE X xcs X DX DX xe X OX X X X X xim wem X Tx X quo QML Certified FPGAs and PROMs The Xine of radiation hardened FPGAS and PROM finding homes in many new satelite and space appl ons Both the XQRAODOXL and XQVR Vines produces being designed ino apace wil reconfigurable technology Numerous communications and GPS satelites space probe and shure mi sions aee included on the growing of pro grams shat vill be ying these devies GA Product The Virtex QPro family of high eiii ty product is experiencing high degree of success the defense market As designers find it more and more dificult to find components suitable for the han environments seen by defense systems they discovering dat they can incor porate the functions of obsolete pat ino Vinex QPro products This has the added long term advantage of significantly seducing the eau of requ
33. curent rode diver chat produces the desired diferensial signal on chip wich nend for external source termination This alongwith the new dedicated easy to use Double Dats Rate DDR rite in the input output block males the implementation of HyperTransport in Viner devices very user Gin Overview The wakes data Krom interface vo the device core and vie vena For Bbit HypeiTansprt link goes of command dat che interface wo 64 bits into the device core at a quaner of the dock frequency The link coni of 1 bi for control 1 clock and bits of com which can operate at 400 600 800 1000 1200 or 1600 per chan These dara rates apply chanel of ic one differential pair clocked on both edges of the dock DDR Therefore a 400 Mbps link has a 200 MHz dock and a toal throughput of 5200 devices an support up o 800 Mbps per chanel The bu with canal be seed to 2 4 or E of data per clock and wih addiional odes ican be expanded to 16 or 32 bis of dass For example 16bit dara requires 2 ode and 32 bit dara equis 4 lacks Because is intended to be a ver high ped ince to a wide variety of components signal crucial for this new succo Low let voltage low ight swing on VOD Diferential Voltage and on chip
34. in the IO enables four In the pat blocks wee ery standard and hey could uly oup internal programmable logie for one volage Today with the ey Pha he pocenr pins do Vinee family we suppor the major nor tale up valuable FPGA resources iey of UO in the nly you eed hon Thit allows yoa lad at combination of move dara much fate than the competi danda and drive currente we have 49 don competion embedded procer waya shat ou can progam every ingle sor does nat have che same performance or pin And we will connue oadd new Desi as our PowerPC cr Oia sash Oue philosophy isco provide all of the High Speed Saal peripherals and so as soft cores so they ire no f you eed he demand igh PS dem we cho to provide the ing sod high perform ard core because i the of gli peracond 10 for nercenecin de and tem In aon some abe new commie ieee ae wa eg Cain mem serial cadis includ dual ing POSPHYS mou Sea Vent InfiniBand ae Channel Gigabit Ethernet and s0 om MicroBlaze Soft Core Procesor Wih the Vil VO capabiliy you can connect directly o a backplane without ternal components gives you a perform ance advantage As 3 18 continues prove the pe
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36. ASIC world took 15 years to merge he silicon process solid design method ology based on clle and funcional sofowar ASIC technology became the diving force in the industry The proces that began sur rounding this technology created an effective solution for che electronics industry which led to growth and innovation But the ASIC proces has matured to the point where ic is applicable more for extremely high end design and ic is slowly mov ing of reach for the mase market 1 contrast FPGA technolo gy has taken only five years to get to he same level of functionality as ASICs FPGA technology has uniquely solved the same problems the ASIC method logy addressed but along the way also minimized the NRE risk and manufac turing issues involved at illustrated in Figure 3 Today the Xilin Vitex technology is legitimate ASIC replacement When combined with leading edge EDA sofware Virtecll FPGAs provide the electron ics industry with new acting path for growth and innovation FPGAs are now the key vehicle driving the state of the art fr new The Xilinx planform based FPGA technology brings i Fer 1 Gated Fiper2 Elation of ASIC and FPGA dein medir ipee FPGA t ASIC coe impr wih prose Mentor Graphics CEO grammabilsy o the Synem methodology Using ayer menal proces with 0 L2p highspeed transistors Vine
37. Moschee fld vo non interlace fumer wha is seen on the Fire 1 output sereen E Calor space 1422 w 44 format conversion Upldown scaling of umbral Blend and fade beeween frames video Check de Video Applications website for the te new funcion Fue algorithms include compresion of video data decion and enhancement of video imagery via DSP functions and additional bili to support the emerg ing video mandanda Conclusion The advanced system level features and the growing list of video relared Iaclecual Property make the FPGA family an ideal choice for video applications And now the Virer Video Demonstration Board gives you everything you need to quickly and easi explore video applications For more information on the demonstration hoard visit che Xilinx website at wor ails com mw m to d rer with System Agen Kits for i Design Services has devel Mone Virtexll design n sd ur k 1 4 z by Waren Miler Ki This kit allows you ro Controlled Impedance TEchnology W d ko het eig Sei evaluate the Vinerll technology and o XCITE for digitally controlled imped ar aee lean more than you could fom just read ance matching This impedance marching ing datasheet Avner Design Series capability improves perf
38. VIPwitch found the repoparamahie Xilinx FPGAs met each of these requirement ViPeeich also based heir selection on the Xilinx Controlled Impedance Technology XCITE feature which is unique to Vitel FPGAs This capabili two external reference reine to hold input and output impedance for hundreds of VO pins Benefits include a reducion in on board thar signif reduce spem coss and board re spins Eliminaring hundred of resistors using the XCITE technology designees reduced board real esne and complexi and increased The XCITE capabiliy enabled our pcc c r About VIPswitch sakar won ASIDE EE ciently resulting in fewer board respins and ome pc engin fee bo sea upgrades due to the ever hang craquer vit d at in Monon and Maud Bowyer senior vice president of For more information and programs mu pei wiih hel pa pump agement at View With fr our design on the webs FPGAs svichrouter will beche ist application of Xilinx that can be ly and repro FPGAs further demonstate pene sand an email rammed without relying on an ASIC inno the ASIC sid Clay technologically advanced vice president of the Advanced ar call 900 638 267 product family enabled us to over
39. and access our AliancaCORE and XPERT Partners wth he industry best search engine SmartSeareh means easy w access and easy downloads Complete solutions Supporting cur powerhouse programmable logic products ike Vitex SPARE Spartan FPGAs iin Try before you buy IP Center you can ty the mast eficient IP solutions available taday before ou buy Its just one more reason industry leader in Vist nodi ameet and dieto toy XILINX www xilim com XCITE Xilinx Virtexll Platform now feature the w s X C e on chip digitally controle S d impedance matching Dinosaurs Slide Rules 8 Track Tapes and now External AU mily of FPGAS bs s making PCBs Termination Resistors E High performance systems require signal necenitating impedance matching between device and PCB trace In the past as clock speede increased and standards changed system engineers and designes leamed signal termination techniques using external to Overtime more and more reiton were required account the increasing widths of ange dan buses Wih the advent of 1 500 pin packages discrete resistor placement became a major challenge making the layout procese more suming These lad to manufacturing cous and longer to have worry terminating highspeed signals XCITE making imped ance matching a pre
40. and get your prod maet than ever before cation Servins Move to the hea of the class Xilinx Education Services your technical ail be A broad range of EEES uae eibi designer of ll fom the navic he mow experienced Handeon easing ed y who end designere themselves are conducted the headquarter ia San Jo and iex worldwide the Jot The anes cover a wide range of wp Fe including Using on Using high leve design languages Synem and configuraron design iames Migration ASIC w FPGA aprico Rowdee at yos eripe Support is our solution fr ing your design youl nd Our Dubie which contine moe than 4000 proven design luin Problem Solvers you troubleshoot desir configuration sofware tion and JTAG its IUE OF COURSES EE DY RN IE UCET iS FP TRS TAE SJE SR HE nt nc SENE ro Rre m Discusion forums hat ler you share ideas and question with other designers A Web support allows you to easly submit problem and can get your quickly Supporsitin com is alway available to you 24 hour a day Support Serves Experts on Call Gold and Platinum Technical Services improve your productivity and accelerate youe design proces by reducing your design and trou
41. for 36 additional parallel outputs The memory i divided ino two completely independent half size single port memories by tying the MSB sures bit of one port high A and the oher one aw B To create a 256 sate FSM Port Ais con 2K x 9 and is used as 1K x 9 single port ROM Eight are fed back as address inputs stepping through the 256 states The remaining two address inputs determine the four way branch Any of the 256 sates can condi tionally branch any set of four new under the control of the rwo address inputs Meanwhile Port B is configured 512 x 36 and is as 256 x 36 Single po ROM Port B receives the same stue defiing address as port A and drives 36 outputs that ean be arbitrarily defined for each state Without any loss of speed 200 MHE mas you can easly modify design to a Date FSM with an cighteway branch or a FSM with a 16 way branch If you need additional branch control inputs they can be combined in input m The advantages of this design are Low cose zero if the block RAM is oth erwise not needed High sped No layout or routing issues Complete design freedom More Spaced Uses of a Blok RAM A liile creativity can go a long way Here some more design ides These solu tions are compact and fas and compete well against more conventional CLB based implementations 20 ic binary counter
42. or 18 bit binary up down counter in one block ROM configured IK x 18 running up to 200 Suedigi BCD Binary Coded Decimal counter in one block ROM configured 512 x 36 plus one CLB running up to 300 MHz These counters use one port For the les significant half of the count ex and the other port for the more sig nificant half This is posible because the count algorithm sored in the ROM is common to both halves lk RAM ood p dnl par te par Two independent 11 bit binary o 4 digit BCD converters with the block ROM configured IK x 18 and LSBs Least Significant Bis mot passing through the convertens Two independent 3 digit BCD to 10 bit binary converters with the block ROM configured 2K x 9 and the LSBs not passing through the converters Sinecesine look up tables using one for sine the other one for cosine with 90 degree shified addresses 18 bit amplitude 10 bit angular resolution slaw Alaw telephony code converter or to linear converter 9 We encourage you to any design for leftover muller and block You can chem unburden the logic fabric where possible Furthermore using multipliers as and block RAM as state machines also simplifies the design efor significantly reduces routing overhead and power consumprica and achieves higher performance i hard to beat his combination
43. rals and AvBus connectors These code interes make it to connect the appropriate FPGA pins and accessing memory LEDs ewitehen RS 232 port and audio With this kit you an have a simple design up and running inada Available as options are a variery of Xilinx FPGA development tools IP cores and Arie modules well as and design services support You can purchase Xilinx Foundation ISE packages like Foundation Elite if you dont have develop Avalable Daughtercards Planned Doughtercards PowerPC procesor me eet procesor mole UTOPIA ier Test and Opern pir Pria i e Wiles modem DSP Digitol Sod Processor module 1 Coment and plane ment environment IF cots or PCT ae also available s options and support 32 bit 33 MHz operation The and planned daugheercard modules fer the Vitel Development Platform kit ave lised in Table 1 Avnet Design Services in conjunction wich Xilinx and other Aerdistibutsd semiconductor manufacturers will be creating reference designs targeted a spe iic applications using the VirexIl Development Platform Vitex Kit A phonograph of the Vinee I Evaluation boat is shown in Figure 2 The Viner It 29406 FPGA is he heart of the board and pects the RS232 the LEDs and seis the ge
44. the maser and dp o po eh bae maia Frequency que against obsolescence Figure 1 OFDM al for prato pea urban market but here are many business actors that must be addressed if the ven io to succeed including Which of the emerging broadband wie services will generate high demand What is the peak bandwidth What it the average bandwidth per sub per eic What Quality of Service can be aed to diferentiate the new service These ie no substitute for Bed vial to answer these questions and there is better platorm for field tals than Viel FPGAs Consider where sands body new of OFDM a very likely scenario With conventional ASIC upgrade path Un workers mus climb telephone poles limb 1o the There is another dee ol Ber biiy which the Vinesll based OFDM base sation pro Vides he ability to ede olf silicon area for performance Consider dhe mater sucer described above IF it became evident through and customer venting that the average was noe a heavy con sume of bandwidth he OFDM algorithm oul be ears mor general pur pose logje Proper done this would result inthe ability to support more channels in the same device Ewentilly the FPGA allows you dynamically of silicon area for performance The product fam
45. 0 contains for the and VPN inputs sing 24 524 Ohm fangs The of thee ering and m options de beak Both kts include general purpose test and prosorype cim which most datigas need User DIP and push burton switches sevensegment LED display an RS 232 serial and user UO connectors all avilable In an effort o maximi UO all of these cits can be con echas of B2 demon ard Bk Platform FPGAS The Insight development boards demonstrate high performance LVDS low diferential signing through LVDS Four dedicated receive dita puis four data pairs and che nani and receive doc sable for prototyping high speed interfaces The LVDS cie pore includes parallel termination the transmit does na include o require shis eit For designers who want to explore bigh speed DDR double data rate DRAM the XC2V1O00 version of the develop men board includes a 16M x 16 DDR memory from Toshiba Due o limita tions the XC2V40 version of the kir does offer thi nae ected or disconnected the VO pins rough header jumpers This gives the freedom to choose how they want to implement UO pins and not valuable seines on unused dedicated cci Finally in an effort to provide development plat
46. 58 56 48 1075 5 s x s sw eme 2300 xeaveoo sexes 23782 145 44 252 46552 1455 300 1108 xeavio000 128x120 1420 2 192 1108 Notes 1 See details in Table 2 Maximum number of user VO General Description The family is a FPGA developed for high performance from low density to high density designs that based on IP cores and customized modules The family delivers complete solutions for telecommunicatian wireless networking video and DSP applications including PCI LVDS and DDR interfaces The leading edge 0 15um 0 12m CMOS B ayer metal process and the Vito architecture are opimized for high speed with ow power consumption Combining a wide variety lexible features and larga range of densities up to 10 milion system gates the Vitel famiy enhances programmable lagi design capabilities and is powerful aternatlve lo mask programmed gales arrays As shown in Tabie 1 the Vitel family comprises 12 members ranging from 40K to system gates Packaging Offerings include ball grid array BGA packages wih 0 80mm 1 00mm and 1 27mm pitches In addition to tradition
47. Designers have wied to overcome these bandwidth limits by using more pins and or larger bus wide This has made the traditional stan dards more Significar problems arise as pin counes grow ime the hundreds and thousands creating routing congestion on printed circuit boat Although Platform FPGAS can ail inside he device it i ener Jy dificil to interface with all the pins on PCB More layers of interconnect sout ing inthe PCB cause dramatic increases ia veal boad cots The number of pins running these mandanda also produces problematic electromagnetic interference Additionally the most popular bus archi tecrue is a medium where mul iple entities use the same bus each wait ing in vum for opportunity com plete is transaction As he size of audio and video data streams increase the wait ing period gess longer Ultimately overall performance decreases along with per formance predictability Therefore the trend to move frm shated bus to point to point link typically configured as a switched fibre Beyond the Shard PO Bos The most popular shared bus isthe PCI Peripheral Component Interconnect bus hat become a general purpose bus for penna computers and embedded sys tems supporting many diferent applica tions 33 MHz 32 bit PCI bus can sup Port one and five destinations with an overall bandwidth of At 66 MHz and 64
48. Voltage Positive Emitter Coupled Logic QDA Im SRAM interface Advance VO Data Buitn DDR Input and Output registers 600 Sigma RAM interlace Advance Data Proprietary high parormance Solctink Arithmetic Functions Technology Dedicated 18 bit x 18 bit multiplier blocks High bandwidth data path Fast look ahead logic chains Double Data Rate DDR ink Flexible Logic Resources Web based HDL generation methodology Up to 122 880 internal registers latches wilh Supported by Xilinx Foundation and Aliance Clock Enable Series Development Systems Up to 122 880 look up tables LUT or cascadable Integrated VHDL and Verilog design flows 16 bit shit registers Compilation of 10M system gates designs Wide multiplexers and wide nput function support _Intemet Team Design ITD tool Horizontal cascade chain and Sum of Produeis SRAM Based In System Configuration support Fast SeleclMAP configuration Internal 3 stale bussing Data Encryption Standard DES security High Performance Clock Management Cirouitry option Bitstream Encryption Up o 12 DCM Digital Clock Manager modulos I EE1532 support Precise clock de skew Partal reconfiguration Flexible requency synthesis Unlimited re programmablity High resolution phase shifting Readback capabilty 16 global clock multiplexer butlers Power Down Mode Active interconnect Technology 015 um Bayer Metal process wi
49. Xilinx Xereme DSP igh performance DSP dei in environment wih and i pre 3 complete ser of for lowcost DSP implementa tion tha provide Xtreme Dinibucd DSP resources uch lookup bls reg ites mules memory and seg routing allow optimised implementation of algorithme Pls Table 1 Extreme Performance A Function Processor Coro WW MACs por second Multiply and accumulate 8 Bilion FIR Filter m TIMSPS 150 MSPS Ji hit aafcoficems 11GHz G180MMr 1024 point complex data 77 and imaginary comp ues Software Solutions version Development Systems Quick Reference Guide Xin development systems give you the speed you ned With che initial release of our venion 3 solutions ins phr andmute times are at two minutes for our 200 000 gate XC25200 device and 30 minutes for our onemilion gue system level XCVIOE Vinex E device That males Xilinx development sywems the fet im de industry for de deiga of logie devices PLD And with the push of a buton our tole are cresting dar support UO spenh in curs of 800 Mbps and eral dock in exces of 300 MH newest devices in the Vitex seris the Vine family are fly supported by the Xin developmen Advanced design flows includ ing modular and inc
50. bits the bandwidth rises to 4 Ghis but then the bus only support one source and two The PCI shared bos race has diminishing per formance returns is less predictable than a point to point solution and is limited to internal Ideally we would like vo establish a link and then buns the data over a rely Wide data bus This would maximize bus efficiency Bus efficiency is highest with long burns Decreased bus has many causes Although we may have economie of wale for mos applications the shared PCI bus compromises graphics performance For example when using PCI graphics cud the graphics cand need every few milliseconds In onder todo this it ees o have immediate and frequent acetas o the PCI Asa result other PCI cade cannot send huge daa burt This is because arbiter is designed vo ensure that one component can send large buss of dara In intensive applications an AGP Advanced Graphies Pon ia much bener choice than a PCI bus Although AGP is based on PCI technology is designed especially for high throughput require ment of 3D graph ia Rather dun Wing the shared PCI bus for graphies das transmission the AGP introduces piden dedicated point row channel so that the graphics directly sce main memory Pom FPGAS 3 support both PCI and AGP VO stan om dads
51. designer unprecedented design capa bur now designers had no way o protec thelr IP Property from being cloned Current FPGA technology requires the device to configuration dats fom enema source This makes it easy for a Pirate or clone a design by ap ping configuration pins and soring the design configuration for elsewhere Now however new Vier devices have on chip deceyptors that have their keys loaded during board manufacture in a secure environment Once the devices have been programmed with the correct kep the devices can be configured with bitstreams You can use random kep or dioo your own software using the powerful Triple Dats Encryption Algorithm Triple DES is the standard employed by the United States govern for secure communication and by banks around the world for maney rne fens Both DES and DES are available in Vinex devices Using three Sorbie keys makes a design virtually impenetrable m How to Encryption simple you enter and simulate your design as you normally would In the last step of imple mentation BitGen you set that tell the software to encrypt the bitten and what keya to This creates a spe key The JTAG Programmer ues the key fle vo program the keys in the Vistes device Once the key are in pla
52. different sec within the same design The Xilinx DSP tool set supports different bi widths pipeline stages and implementa tion alternatives For some channels that more bits of precision compared to others you can juse change the IP oer 4 The Nile pem Genter tbo fiom deiga FPCA impli Soon parameter and the sofware accommo ater the new data configuration With the Nine DSP tools you can ely optimize for performance silicon area or power dinipation when realizing your By implemening he grin in a ly you can achieve she posible dara chroughpur You canal employ ths technique ta ove power by slow ing spem dock Convery by implementing the algorithm in a fly serial mode you can achieve the silicon and de lowest and meet he specified perform ance requirement The DSP vol set isthe only available FPGA sofware chat sup any numberof bies proceed in parab 14 fom one to all bits rene Requirements Demand Sens Designer are already using Xilinx FPGAs for high dein high performance DSP solir tions in emerging 3G wil base sation VOIP Voice over Interner Proto HDTV stp bos video on demand systems and Aig cinema applications Because the Initiative complete solution DSP enhaned FPGAS development tools and supporti provides a compete advange to synem designers and OEMs who a
53. engineered scion XCITE can be to terminate variety of UO standards All of HSTL High Speed Transistor Logie SSTL Solid Track Link GTL Gunning Logie and LVCMOS Low Voltage Complementary Metal Oxide Semiconductor ate supported Designers Noe only doe XCITE make PCB less comm plicated it actually improves signal quali With termination residing inside device insted of few centimeters away ub relee ion in dininaed as a design coc XCITE a bee solution than discrete temors because continually adjusts the termination imped ame match the impedance In conventional ayes temperans and alge variations can ply hav with the cally engi ected impedances of a pul Wih XCITE he teminaion TO impedance ofthe driver o is continually compared against a reer ener suis Over the fall range of temperate che eter m ip need only specify signal standard he software In case of he bidirec tional standard HSTL Chas the exter mal resistors usually required for the source and deninarion are implemented on chip see Figure 1 The PCB designer only has to route 500 trace from the output of one device che input of another Figure 2 voltage and proce vasi ations
54. output pin Divided vesion CLKEX output pin Frequency synthe sized dock MID CLKIN CLKEXISO output pin 190 phase shifted venion of CLKEX LOCKED output pin Asend High when all enabled DCM circuis have locked STATUS output pins Indicates loss of the input clock CLKIN PSDONE output pin Indicates com pletion of requested Phase Shift The FPGA configuration DONE output sig the completion of congu ration ofthe Vitel device The DONE signal can be delayed unl afer the DCM has achieved lock such when all the DCM outputs have sailed This delay guarantees dur the chip doe not begin operating the sym clocks generated by the DCM have stabilized This delay is accomplished by selecting he appropriate configuration option orren ren a T V Fee 2 DOM devel ups Tace 1 lc DOM Tre 2 amp CLAD ley competed DCM oput lat phe lumen or ack of hw the CLIN input and de f de DCM DOR The Vinal DCM provides a complete on chip and off chip clock generator with pow fl dock management nes rk DeStow The DCM generates new system clocks either internally or exer to the FPGA that ase phasealigned to the input clock recy Sli The DCM can wide range of ouput clack frequencies very flexible clock on and divison flax Sing The DCM ean p
55. pait The 16760A can adipe single ended signals and then comet wo LVDS analy is dlong with he Vine lt FPGA Godin Debugging high performance systems that diferencial ig naling i sow much easier with the Agilent 16760A saue and timing analysis module For more information on Agilent products go tar mum agilnt com fn fatpacket M you want o kam more about Aglent logic analysis produc and he solution plene egis ter fot the Fast Packet Tou a half day seminar with series of technical Papers creamed to help meet chal lenges of highspeed IP neworking equipment design You will be able to expr and o par ticipate in live demonstrations wagen dy Agilent Technologies eon or n Plattorm FPGA for SiberCAM Arrays You can quadruple your network speed by imple T Reus LEE TL RG by Mog Wa parkus blo on ess 32 bit host proceso procesor with one or more SbeCAM co procesors The SiberBridge Unies searches obs search resus and performs maintenance operations for the SCAM packet forwarding sub system through a single 32 bit synchronous SRAM RAM interface The SiberBridge ofer fully symthesiable Verilog VHDL reference code operating ar 100 to dramatically simpli dy board design maximize spate performance and time to ma
56. pem Terabit Newading Farum an all day focusing on porrum pom rapidi ptem for the net mma Deg Gaal 001 San sing ny The et 001012 te WY vention Cemer on August 21 201 ad wil provide a overview coreg en cu nee ngs Mt pu EE M im Bios and lon slo Over 500 coke working executives system architeco ERES WILL dig engineer and technical produc and markering nun Smia Geel Fs expected to amend the event The form will 911 Enh Spinne Sgt Garry leading cde technologies and provide an under Wald sanding of he vend that wil help you improve per formance and ay on che freon of networking and ca Yen 2001 Pasi Event Sad technologies For spin and program infor mation ve wis comer Kien PI Interface Standards fa Presentations will be made by industry analysts and experts at well as Xilinx technology Topics will include 10 Gigabit Noar 2001 Japanese Event Schedule Ethernet HyperTanspert Infniband POS PHY Level 4 and Level 5 FapidlO and 3GIO interconnect tech June 2001 ae 2001 Tokyo and Japan nologies and more There will also be live demonstrations of Wall Tail Seis 2001 Japon ond SE Asia interface standards
57. reu Platform based FPGAs have taken the problems found by previous ASIC SoC designers and minimized them by pro IP immersion Designing an ASIC SoC requires a highly experienced wam of engineers fom mul tiple disciplines This team must Hearn how to use proceso develop software on it and connect TP into the synem These learning curves are long and riddled TODAY THE XILINX VETERE TECHNOLOGY 1S A LEGITIMATE ASIC REPLACEMENT WHEN COMBINED WITH LEADING EDGE EDA SOFTWARE FPGAS PROVIDE THE ELECTRONICS INDUSTRY WITH A MEW EXCITING PATH FOR GROWTH AND INNOVATION Munt im Dama urna siding a proven recommended path for success In the history of electronic design innovation and productivity ate at their peak when proven methodologies permeate the industry 0 wih And because all blocks come from different places inte tin rarely works on the fist Plaform based FPGAs solve some of the big iue thar limit the development of ASIC SoCs by addresing IP Inversion inue as shown in Figure 4 The Xilinx IP immersion technology mas performance and density by providing a ied and proven sructur to incepet hand and soft IP inco the silicon Plaform based FPGAS using embedded processors Will be the next key tech nology der will push FPGA design forward By limiting support to only certain CPU architeerures all integration information is predefined for functions s
58. such embed del FPGA configuration techniques are complex design challenges requiring valuable development rins For ample sym gins mast devote design eor to devel p and miropncenor code for FPGA configuration Furthermore sup timer are delayed the microprocesor temper manage gene system and FPGA configuration simultaneously Bus contention is also a danger during sys tem startup when he FPGAS compete with ther board resources for microprocessor and memory acces Moreover embedded solutions require extra board space forthe additional configuration storage memory Using JTAG Boundary Scans for board tening and FPGA programming can equine separate trace lines and can control devices When using FPGAs and CPLDs Complex Programmable Logic Devices as congu ration a device is added vo he board simply conver FPGA dodes wo increments and in mode to serialize dara The FPGA ao needs aequas PROM to config he The System ACE listo Slaton the oprions desibel above and the growing need for configuration designen wing Berl The ACE configuration manager a lt ax ACE multiple FPGAS were medal ef and am onboard ACE Conall lagie deriet faced with the need to male a den Use a sl contained pre engineered uli PROM solution at the expense of bois space or devote engineering devel op
59. the piss in one scene multiplied by a fection alpha while the pinea in the ther scenes are multiplied by one minus the faction 1 alpha Varying the frac tion from zero to one produces the blend ing effect The master controller or technician view ing the diferent video input streams and the resulting video commands to manipulate the input scams Thus just at in typical video production the master queues video up an such as ging to a commer ul and the FPGA executes the mathe behind the command The of vide effects cur tently supported are Fade from black Fade through black Dissolve Horizontal wipe Vera wipe Over time mote effets will be available These expanded efc will appear the xi video application notes m Beord level Block Diagrams The video demonstration board a num ber of input soues of ive video anda num ber of purae frame bus to support the ammount of ane and bandwidth meded by the exa live seams An audio codec i for embeddad audio as well supporting potential audio algorithms updates network connection The scd can ako dive a TV monitor A Bde ager ie shown in Board Four sores of live video input cher NTSC or PAL Composite and S Video inputs fom a Separare ed graphic image loaded fr
60. the same bank and the same package ball loca tion including LVDS Low Voltage Difkeenial Signaling paie The main benefit here is hat you can re use tame PCB omnc for as many as six devices of differen dense in one package Fot cumple a BP957 package wich its fd ball accommodates de XC2V2000 XC2V3000 XC2V4000 XC2V6DOO XC2V8000 and XC2V 10000 devices This represents a 5K dens in a single Table 2 summation pinout compar of the enire Vitel family The ful pinout compatibility of each of the 10 packages can be found in he individul pinou tables in Module 4 of he Data Sheet No Comet NC information is provided for the smaller devices in each package When wo devices have a No Connect the NC of the lager device marches the NC of the smaller one to ciue pinout migration Pot Acres devices even more Ax because vo package both pinout and compel In other word devices that pinout compaible within a package ype abo com wih another npe The Pinunlfoonprint compatible package pir sre wirebond FCAS6 amp FGST6 and fip ip FF896 amp FF1152 This additional allows you to pro duce a single PCB tha can accommodate anything fiom the XCZV1000 in FF896 to the XC2V10000 in FFILS2 This represents forget competit across eight devices foe a density raio of
61. you cn buld run at The PCI the pins of the sufice mount devi on our own wi plag and gi Cove canbe the PCL the oan and pede debug nd vo oet ran can be punch aan psn he ak m Avnet Design Serves us The platforms SDRAM maduleimertces remaining signale amd rn deve 3 produced simple dimly m FPGA and ues Xilas opment bead ineo a includes Viel Platform FPGA con nected to a PCT bus wealth of DRAM m m tem applications and IP core develop ment You can select from a variery of of theahelf hardware modules compliant with the AvBus specification to build complete and application apecifie devel opment platform This allows hardware integration and teing to begin immedi ately skipping the lengthy process of designing and building a protuype PC board This building block approach uing the AvBus based platform reduces development time dramatically making changes matter of minutes or days not Development Platform Contents The development platform it includes the board detailed user manual datasheet quick stat guide and schema A demonstration program along with the source code and netlist is provid ed The demo program giver several examples and for al periph
62. 10X As shown in Figure the FF896 pinout diagram i dene on a transparent page to demonstrate the footprint compatibility Wih the FF1152 Complete definitions of all the pin ypes listed in the pinout 45 avaible in Module 4 of the Data Sheet Pakage FOLS MISIZ 1055 IST mu m m mm e m __ s xw xm mas 7 s 7 Imm TE 7 EZ 7 Jon z 2 2 2 2 2 oum 7 Ez z 7 pino compel Woo All the contol pins and powefgsound pins match the FF896 and FF1152 bal All Os 100 compat ible exept the LVDS pairs Because of the migrasion fom one package anot a particular pin cold have a di ferent pin name athe same physical loca tion Pad locations across the wo different packages use following rules ThE FF1152 has two more rows of balls on the top bottom left and right edges A particular FFS96 package location in the FF1152 location i calculated as fol lows Pin location is referenced by Lenes Namber or example A2 Lener indicates a row Number indices a column FF1152 Lerter Number FF596 Lener 2 Number 2 For example the A2 pin of FFB96 is the CA pin of FF1152 Using the shove informasion an
63. 130 AL DCM apu m ane 3m phase off te ih m Assn example ifthe input fequeney F 50 M 333 and D 100 the generated output frequency i correctly 16650 ren though both 333 x 50 MHz 1 665 GH and ME2 100 500 rousse che range of the frequency eu shat Mand D values have no common and therefore cannot beri Figure shows the waveforms of the frequency synthesized ouput with 3 Det and F 100 MHz Phase Shifting The DCM ako allows you wo shift the phase of dock signals so you can adjust the setup hold tines of signals High sola tion phase din has following charac The DOM provides quadrature phases of source clock CLKO and CLK270 which can be we simultaneously A phase sified our with a elution of o 1256 of the input dock psi can be created fine phase silting es al the outputs of the DCM The phase shift can be fined table by configuration dynamically adjusted configuration The dynamic phase can be ued to opine by adjust ing the set up and bold ies while the ye ia nunning The quain for the phase shift ix stewsPhase Shi x PERIOD CLIN Figure 4 shows the phase shift eects in the and malle moder of operation The phase shift isa facon of the dock peti od N1250 The phase shift granularity is the grener
64. 2300 Sip 3 Choose the switching Switching frequency has a influence on the efficiency of the DC DC convert er and the size of the inductor Usually higher efficiency is achieved ar lower fre quencies a swiching losses of the semiconductors are lower However inductor component sine decreases as quency increases The EL7564C data sheet shows he v Cosc cune For Fy 350 Kha the curve indicates that C Sp 4 Choose inductor LI The EL7564C wes current mode control A summing compare generes the dury ele of titel power FET This com compares the feedback vlog with the intemal preset reference with he patented cunt sense input the comparator determines the ON and OFF time forthe power FET For opti smal operasion the inducir eure ripple ange should be less than The dope of the curent ramp is funcion of and m MAL 034 1 1 too eg Therein choose Ly 47H Step 5 Choose output capacitor C7 The output voltage ripples AV and ouput ciment ripple normally determine the Cy The ESR equivalent series of Cy must be es thane ig Set Vo 2 08A Choose Cy meer ESR sequen for output volt age tipple AVo 2 Step 6 Choos input capacitor Cla 1 all the AC current is handled by the input capacitor RMS current is
65. 25 V Class Land Ii AGP2X The XCITE digitally controlled impedance DCI feature automatically provides controlled impedance drivers and on chip termination or single ended 108 This eliminates the need for extemal resistors and improves signal integrin The feature can be used on any by selecting one ot the DCI I O standards The system adjusts the impedance changes due 1o voltage and or temperature fluctuations The elements also support the following differential signaling UO standards NDS BLVDS Bus LVDS uvos LyPECL Two adjacent pads are used for each differential pair Figure 3 Two or four blocks 08 connect to switch to access the routing resources XUN LT Figure 3 Input Output Tile Configurable Logic Blocks CLES CLB resources include four slices and two 3 state buffers As In Figure 4 each see is equivalent and contains Two function generators F amp G Two storage elements Arithmetic logic gates Large multiplexers Wide function capabiliy Fast carry look ahead chain Horizontal cascade chain OR gate E ED Figure 4 irte Slice Configuration Tho function generators amp G are configurable 4 input look up tables as 16 bit sh
66. A Ld was ow we s ow mas ow os wem ow mas ow os ow o wen aw w 2 poe om wan wem 1 7 a ow pas wu ou ow wu su os ow pos su os ow pus su ow ow ou os sur os ow wemu s You can your ASIC on it esperti aly flrs costs eres also mip Delay Locked Loops combination AM and and our and pice In ac wih neice ecb 200 00 syste gates dock et speeds beyond 200M and lightning fast comple ines sparan FPGAS you The lie IP Center brings you al the ihe best dolar value in the Industry SPARTA cres reference deis design et i of the risk eres and tir pay support you could Now youve got the design ish al easly via the eb been wating ir vito any annoying NRE S gt Fad out more today by visting us a ang production umes or the design Ya soon see sce wth a typlcal ASK To save stem Wy you can bt your ASIC onus 5 XILINX me gue ge Cms www xilinx com Virtex Series FPGAs FPGAS you unpeecdent The Viste EM Extended Memory The original Vitex andy oni of devices ed capability and Re tiliey The fest of he family consists of owo devices that
67. Cycles thereby reducing the required FPGA resources in exchange for band id The input daca wid of the mul tips can be configured independently iom 1 64 in width and can be signed unsigned ot dynamically You can ako create constant coefficient mailen that can be ately dynam reloaded Ifthe input is dynamic you given the option to hale the mukiplieri operation while a new con stants loaded Options are also available ro pipelining to vary the ouput width and to include a clock enable pin Exons To illustrate the power that lies behind the convenient interface of the Xilinx CORE Generator it is useful to Took at the designs it produces Consider cresting a Kb memory con figured as a GK amy using the dedicated Block SeeoRAM resources Themersnigulo Figure 2 Tire Blick Meme ative ward solution wold divide array in depth and vo six 118 primitives as illustrated in Figure 2 For dissolution you would need to add logic to multiplex the ouput of these primitives To this muktiplesing logic a second solution would be to parition the dara bus in wide instantiate primitives and to concatenate their busses For both these solutions the memory requirement 66 bur che implementa tion requis six SelertRAM and represents of only 61 61
68. DCM es you lei to choose and division factos that integer whose ranges are specified in de dara ahoen This can help reduce the number of highspeed dodla in your design Frequency synthesis enables you ote a single prem level clock to generate any frequency within he operating range Besides the Mille frequency synthesis described above the DCM also offers basie frequency For example multiplication by 2 CLK2X CLK2X180 and dock division CLKDV of the wer source dock by up to 16 Any one of the following numbers can divide the clock input to the DCM 15 2 25 3 3 3 4 45 5 55 6 65 7 75 8 9 10 11 12 13 14 15 016 Clack muliplicstion give you number of desig example 100 MHE source lock on your PCB doubled och by the DCM can dive an FPGA design operating at 200 This technique sime plies board design because he dock path on the board can be slower giving you benter dial neg Wich multiplied dock you can do time domain mukiplezing wing one icit wice per clock which con m sutomascly compensates for the delay on the routing newark the delay iom the external port othe individual dock loads within the device Dy taking advantage of the deskew to on chip delay you can simplify and improve deiga involv
69. DM Orthogonal Division OFDM thee two principal 4G development technologies contending for attention CDMA and OFDM Code Division Multiple Access is wellknown standard and hat been for several years However OFDM is relatively new OFDM with many technical variants i endorsed by Nokia Cisco Lucent and Philips Semiconductor and is represented the succensor ro frequency hopping and direct sequence I is also posi tioned as th technique af choice for nexe generation wireless LANs and metropoli tan networks The capability of OFDM to cancel multipash ditonion spec tally eficient manner without requiring mukiple local cultor kas won adber ents in the IEEE 80211 and 80216 working groupe However despite the support of many key industry players OFDM is not actually deployed in main wireless sens Todd Carothers vice president of marker ing for Adaptive Broadband recently sear ed Weve developed commercial OFDM sytem fot one application and we think OFDM has rel advantages in the mobile arena but we dont see it for fied point We think thar adaptive time divison multiple acest solution for fixed point to mukipoint and state that we still have the fastest system there and che extensively deployed Gee of WILAN sid recently There ia no quesion thar OFDM and CDMA are in contention for s
70. E Summer 2001 Xcell journal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS SOFTWARE Integrated Synthesis Environment Simplifies Advanced System Design NEWS Advance Data Sheet for 1 5V Virtexil FPGAs P ALES wim Roetanats Talks About the Future of Cover Story Rhines lentor Graphics CEO wade 14 4 g LETTER FROM THE EDITOR Xilinx Virtex4l Platform FPGAs The Fusion of Silicon Software and Support his s he ie Special Edition of the Xeell Jounal entirely devoted to one produc line the state of heart Platform FPGAS This Vinter family is the result of the largest silicon and software R amp D in the history of programmable logic Walden C Rines CEO of Mentor Graphics notes in his Cover Story the Platform FPGA gives a whole new level of meaning to the concept of The Xilinx paform based FPGA technology brings programamabilisy oo che methodology Not only do the Vit Platform FPGAs offer on chip programmabili they ao affer on chip processors in both hand and In his View from the Top column Xilin CEO Wim Roelands explains how you can soon get an IBM PowerPC processor embedded within the pro gramme logie brc or you can choose the Xilinx soft core or you can hare both on the same Platform FPGA Read Peggy Abusid s article Phalorm FPGA Solu
71. FPGA architecture delivers these performance made posible by high bandwidth low latency coupling of intellectual Configurable layout Because hard IP blocks auch as microprocessori have particular shape the designer can out juse the right amount of creating an empoy space for the IP block As a resul high performance hard IP blocks such as the TBM PowerPC 405 32 bit RISC CPU an be implemented using advanced circuit design and your techniques dut maz imie performance and minimize IP Immersion Technology ad Although Platform FPGAs tepretent revolutionary m errr interconnect with the logic memory and of the FPGA platform To provide the wanstion beween the platform fabrie and the habi Viel devices induce new ile an immersion tl The immer din dle allows programmable inter connections between the IP block and the brie much like he inerconnec ion of discrete devices on printed board For example a designer can inseaneiare a block and wire it to other parts of the system In wiring this Mock the designer cam hoo to connect an out 3 High performance fune tionality The high property IP blocks api d cd od o kl od a d ad df cf od aid put pin to a net leave an Enhanced architectural dii a o od add o all ad ad and ll id output unconnected tie BE nm muc E T
72. FPGAS at he heat of their designa morrow SANs Storage Area Networks VoIP Voice netter Protocol viden and vielen applications A ITE VIPswitch Partners with Xilinx to Move Beyond ASICs Remotely programmable chips are a perfect fit for new line of Optical Terabit Routers by Bere Wiks z Matt Comms WPS offered he best pice lily and thematically simplifies board design and smallest 1 really provided jut maximizes system performance what we needed experienced many benefis of using devices FPGAS ate the offering in the new Xilinx Platform FPGA family and represent Alexie solution dut integrates a wide of hard and soft IP cores on a in device whose hardware and firmware an be upgraded at any dine The pro of the architecture reduces synem development time yet enabler a sigle FPGA to be targeted at multiple applications When engineers at set out to deign ther newest product the Open V MAN 160G optical Terabit they were locking for flexible and cost effective solution that would enable chem to bring their innova tive technology to the market ahead of the competition The dein team lso needed the ability to reprogram the system in the field to provide their cus tomers with upgrades even afier inselli tion at the customer facli
73. PLE IDCODE and USERCODE nor test instructions The EXTEST INTEST and HIGHZ test instructions are also supported Configuration devices aro configured by loading data into intemal configuration memory using the folowing five modes Slave serial mode bit serial configuration Master serlal mode bit serial configuration Slave mode byle wide configuration Master SeleciMAP mode byte wide configuration Boundary Sean modo 1532 m vinex 15V Fietd Programmable Gato Arrays Virtex Il Device Package Data Encryption Standard DES docryptor is available on chip to secure the bitstreams One or wo triple DES key sets can be used to optionally encrypt the configuration information Readback and Integrated Logic Analyzer Configuration data stored in Vitex ll configuration memory can be read back for verlication Along With the configuration data the contents of all lip lopslatchos distributed and SelectRAM memory resources can be read back This capabily is useful for realtime debugging The integrated Logic Analyzer ILA core and software provides a complete solution for accessing and verifying devices Power Down Mode Activated by Ine power down input this mode reduces supply curent and retains he Vitexll device caniguration ations and Maximum I O Wire bond and lip chip packages are available Table 4 and Table 5 show
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75. The LEDA tools are also exible for use with customized coding style to assure hat your design meets your own specie cor porate coding Physical Synthesis The owo uime intensive steps in implementation are place and toute and seth These rwo critical design phas are usualy loops of multiple iterations Where you spend moat of your design Mort modifying your design and rerun ning the sofware attempting to meer che timing requirements for a module Xilinx has pioneered a new technology physical synthesis to help shorten this design ee and make the implementation loop much more With physical synthesis for FPGAs the aep can now make intelligent decisions wo help speed the overal design results becuse has some knowledge of your Hoorpam physical device configuration and any placement information The plcrand route process an also pas timing information back vo the synthesis tal once critical delays have been identified Therefore number of iterations is reduced and device perform ance is increased Thpicd eae woda wih ar our mme neds and cml and carn XST phat XST Xii Synthesis Technology OST included with the software and is focused on optimising your designs for the specie Xi device technolo gy you wing XST was developed help remove pro rama device implement ion barriers and then pa
76. a high densi The lows w per jm on of e teda mihi an FPGA ded and i flee das ren wih hod som you wo vion sl ime and plo den rro dina Vie uing he Ciscoe m Vos can qid dom FPGA liy ap fcn ad tar re The riy ii ge enabler oe design velice Sa of dees ing ne comple including the using eds palaging HLL High Level Language design tol are under development chat will far ther simplify the of FPGAS for DSP designers Through leveraging internal and new technology the Xilinx roadmap to design includes plans to induce Cr and Java FPGA folios well and atelier tioning and co imularion Devers Extreme Fy Xilinx FPGAs provide structure of ing logic memory and other festus to allow the integration of an entire system no just the DSP algorithms You can consolidate spem features such as memory bus interfaces cock management system control and other support logie in che same package as he central DSP design to reduce overall produer size and Unlike fixed width general purpose DSP processors ASSP Application Specie Standard Tan FPGAS give you the freedom to create castor word lengths for
77. a single chip In addi tion Vine devices now operae imer nal clock sponds above 200 Mhz equal af many custom ASIC Yes every or he nent four to Bve years we expect a perform ane increase of 30 50 The inherent icon performance increase is about 30 Then we improve de song and so on we expec up another 20 As you can se programma e logic technology i advancing very quick ll giving you more options more capably more xdi and more to move from ASICs and d logic designs The bic of an FPGA determines ins capabili and i of use it abo determine aly to evolve a new technologie developed and implemen co You want your FPGA to wh your eed having 1o new tools proceses and techniques Thats why we developed flexible highly predictable forvantthinking architecture that can custom logic hand and mised capi With the Vinex family you ll not only achieve high performance youll do it with a high degree of and ly sublity which is key to your pro ductivity Plus migrating o larger devices with higher performance as they ate developed is easy m JH all sarts wih rong FPGA tig integrate with high level devel open ons and hee end sight to where his ly on ga Cora device densities
78. al wire bond interconnects lip chip interconnect s used in some of the BGA The use lip chip interconnect offers mare I Os than is possible in wite bond versions ofthe similar packages Fip Chip construction offers the combination of high pin count with high thermal capacity Table 2 shows the maximum number af user Os available The Vitex ll device package combination table Table 6 at the end of this briel data sheet details the maximum number of NOs lor each device and package using wire bond or lip chip technology FC XILINX 1 54 Fleld Programmable Gate Arrays Table 2 Maximum Number of User I O Pads Device WireBond Flip Chip 88 120 200 XG2VS00 264 328 2 EI Ez 2 000 720 D 2 6000 1104 1108 XGaVi0000 1308 Architecture Virtex Il Array Overview Vitel devices are user programmabie gate arrays wih various confiurabe elements The Vito architecture is optimized or high density high pertormance logic designs shown In Figure 1 he programmable device comprised inpuoutput blocks 08 and internal configurable loge blocks CLES block mutipilers and Digtal Clock Managers DCMS ics oe x TTT gt EH LULL 000
79. am fim The MathWorks Toc With this ol you can automatically generate an optimized Ger implementation for he FPGA Through excuse alliance Xilin and The MathWorks creased de System Generator bridge beeen archi system design and hardware imple menion of DSP systems Naw you can build high perfomance FPGA applications using DSP and vericaion tole The Xii Sytem Generator wod in con junction with the popular Simulink and MATLAB modding wols fom The MachWoeks 4 The System Generator combined with a library of para and optimized algorithms om ew you gp fom a behavior sem model an FPGA imple mentation Using sig reduces development time mini the rak of insoducing errans and eases your lesming curve You cin run apeiments on the behavior of DSP functions enabling you to quickly determine shi cade cf betwen performance power consumption nd silicon XPower Tools The XtemeDSP Inte abo indu sew XPower adds tol and lancent de ChipScope Integrated Logic Anais debugging d hae afi daran tine cc which cei i naive tat you ponet which tcc presente dea XPower oes ende af anl cde tat well fc developing high performanc
80. ance DCI As shown in M 0 Figure 3 the DCI capability of the inex I Sateotthean SptemIO capabiliy Architecture PICA cola deque m iae suppor interfaces for RapidlO PCF i pe fine lesion architecture is while reducing de X OIF SPL4 designed to aid the seamle number of external needed for Fleas 4 and HyperTransport integration of wide variety of new hard impedance matching components on print known as LDT Lightning Daa Transport standards Proprietary IP designs are protected piracy and reverie engineering by on chip DES Dats Encrypted encryption High logie capaciy devices Provide up to 10 million systema gates Platform FPGAs support up o 4 5 Mb of memory SQDRIDDR Quad Data Ratel Double Dara Rare registers deliver move than 400 performance Active Imerconneet rout img technology optimizes throughput over wide buses A single device provides as many as 192 muliplles capa ble of up 250 of pipelined performance FPGAs out mote tha 600 bilion muliply and accumulate operations second for XtemeDSP Perforemance pe 2 A pica Vire I in block 5 4 circi boards Thus FPGAs wih DCI technology reduce
81. anguage statements though simple herbs and easily ana yee syntax for miming language late 1980s graphie entry became a popu ar design method bur as device density grew ie proved too cumbersome Coupled with the use of Xilinx Modular Design graphic entry is making a serong comeback as design work concentrates on implementation of smaller modules not the overall device With our recent purchase of VSS Visual Sofware Solutions StateCAD is mow tightly integrated into the Xilinx standard tools StaeCAD offers sate diagram finite machine Using Property To meet seriet deadlines you increasingly need reliable affordable pre engineered designs that can be modified for your specific application Thats why the growing design option far high density design is Ih or Intellectual Property which includes fiee and pur cated cores and the re use of your own captured and verified code The very nature of the FPGA device fib allows IP o give you quick product turnaround in a reliable repeatable formar The commercially available cores have already been verified for in specif de device familie eli naning the need for al con verification which thus reduces your over all design time There are a wide range of fully verified complex cores from which to choose which frees you to con centrase on other critical design areas Through che Xi
82. as well as pane discusion focusing on eyo the challenges of imerface adoption interoperability and compliance in an exploding ofen undefined marketplace ain pison hbang en mae This industry impact event will provide an unparalled opportunity to meet with peers and industry leaden o you indicus common opportunities nd challenges and derive your own ratis for succes m n Virtex Il 1 5V XILINX Field Programmable Gate Arrays XGELL v1 0 March 20 2001 Advance Briet Data Sheet Summary of Virtex Il Features Industry First Platform FPGA Solution XCITE Digitally Controlled impedance DCI UO P lmmersion Architecture on chip termination resistors lor single ended lO Densities from 40K to 10M system gates standards 420 MHz intemal clock speed Advance Data PCLX 133 MHz PCI 66 MHz and 33 MHz 840 UO Advance Data compliance SeleciRAM m Memory Hierarchy Dire Signaling 2 3 5 Mb of True Dual Portitm RAM in 18 Kbi block 840 Low Voltage Differential Signaling I O SelectRAM resources LVDS with current mode drivers Up to 1 9 Mb of distributed SeloctRAM resources Bus LVDS 110 High perlormance interfaces lo external memory Lightning Data Transport LOT VO with curent 400 Mb s DDR SDRAM interface Advance Data diver butlers 400 Mb s interface Advance Data Low
83. as well as rte many pu Another drawback E the PCI bus is E that i has no emi mation rather i is series terminated This means char it relies on reflective wave switching Although reflective wave wich ing inexpensive and has relatively low power consumption series termination the system to for ion so we valuable time Sith Fabric Advantages A switched fabrie more sealable for bigh Performance and a lower cost solution for high bandwidth applica tions che past data rases werent bigh enough to warn using a switched Bic a systern because this would require many point to point connections and would increase synem compen With the dramatic increases in performance enabled by the new inteehce standards however switched fabric solutions ate becoming cour effective With huge PCI bridges are reed to interconnect var ious high performance UO standards Platform FPGAs are key building Blocs in he wransition fim shared buses tw etched fibris The architec m rure appara univer switching capabili to these new standarda making them the chaie for sytem designen As we mentioned earlier the key advan tage of technology is that 4 This standard s defined for 10 Echernet applications and optical networking applications demanding OC 192 performance
84. ation Xin Smart IPP Technology deve high per formance exi and vith pina cons give you both reducal rand fuer me to made Products More dan 40 LogCORE produc such s parameter able DSP building blacks nd memory cores induded with the Xii CORE Generator which componen of your Xilinx Foundation Series or Allace sofware LagiCORE prod es such ss PCI PCIX Reed Slomen and aer advanced funcion core separately licensed and avaiable on che Center web Miana CORE cooperstive pro gram wich tin IP suppliers who sell ind support rheit ely with Xilinx Gomes AlnaCORE produc must mex ceria that ensure hey deliver vale and performance in a Xil device ary tence reference designs t pro Side fully functional modular that fer considerable development ime eng APERIS Pater Program The worldwide XPERTS Program provides more than 70 connues cried in delivering system designs for the Xi adiectum Including PCI designs new method and spem evel desi slong vith ad negation IP Teele The Xilinx CORE tol enables cataloging and eration of core tar high performance proche and integrat cl with sptem len design tole The coe provided in VHDL and behavioral description The Contor Internet Portal Tha website y
85. ations o be initiated wing 32 bit registers Up to 32 concurrent search requests can be supported cach in The SiberBridge imerface contains wo that can be written to or read by the procesor in 32 bit quantities hae regem communicate with the SbeCAM device wing 72 transfers These ae initiated by wating to the For consider a maintenance write operation The opcode address and dati ae all writen to the Site data Once dat is loaded writing to the GO register rs the data to the SberCAM device and the operation commence Search operar tions are initiated in a similar manner For maintenance operations that get the SiberCAM device the SiberBridge captures the data in 72 bit quantis The data i then stored in the Rogister read data register file until it is accessed by the proceso The does not decode the data written the wite data register Ava red ii unaware of whether mainte mance opeaion will dan While this simplification significandy reduces the of the SiberBridge it does pos slightly greater sofware burden The has to know when expect data The Bock diagram in Figure 3 states he thar wine data to the SiberCAM device and capture data from it Vitel Soon for Next Generaton Networking Combining SiberCAM co procesor with an ex
86. bles you are optimal solutions dt se specifically Tailored for your specifie application m sing the CORE Generator When you select the dual block mem LogiCORE in CORE Generator the in Figure 1 appe interlace allows you to customize the Fg Dl tor Bk Log ORE Block Selec RAM on your tage cel device and to create the required mem ry You may select memory as lange as IM words and word widths up te 256 bits The initial content of the memory can be specified by fle or by a You can configure m have ent of the memory space and to independently obey one ofthe duce write modes suppor el by the architecture The Real Before Wite mode offers the of using the ouput data during write operation which can increase the cive bandwidth of the block sdecing the Design Options burton another window is opened enabling further tation choices including pipeline central and optional pins initiation of the opum a dock enable and var ous handshaking signals A dini user interlace en fr nubiles allowing you to gen trates paralid sequential tiple implemented in either the Aodicted multiplier hic or in the general purpose FPGA fabric A sequential or serial multiplier ime mii the over several dock
87. bleshooting time Ae Platinum customer you receive access to dedicated sol free number North America only so you can get quick asi tance with any daign problem you have to dedicated seam of tilled senior application engineers the best in he business You also ten edu cation for Xilinx wining courses to improve your sil Gold customer you receive standard level of service at Senior Application Engineers no die Vi te ium or Goll piece See enin Dad ien Vea Pj Tum Vid Xn Dig ev g De ete Lordi epic b Tum yis A pes id grim lesu tem Te Deip Sedes ta Cube up SLES daa See wonsapport sili com for mere information on all af ow service Dedicated Free Number Proactive Status Updates Priority Case Resolution Ton Education Credits Service Packs and Software Updates Application Engineer Customer Ratio 2XGold Level Standard Applian North America Only P be dor el of ree proide pos pp PLAS Wc your ne vis C Runner igh taser sh he mont unique the CoolRunner XPLAS family frm Tink ot the anges power lt unbeatable performance tp 50 fey 200 ME small om factor packaging a
88. board design and maximizes system performance IP Immersion architecture enables integration af hard and soft IP XtremeDSP delivers over 600 bilian of processing power Unique Digtal Clock Managers allow unparalleled levels of in high speed customized dock design Watch for more on the FPGA its where the system design wortd is poing FX XILINX www xilinx com
89. ce you can load bitstreams encrypted with your keys he other hand you donit ned seuri y you can configure device with non bit and the on chip keys are simply ignored Eicher way you dont nerd to make any changes to your download methodology Simply the FROM microprocesor or cable you normally would Only sent ineo einer mal memory cells encrypted The keys sored in a small amount of on chip RAM that should be backed up with a banery Because the power con sumption is small for this RAM small watch battery can maintain the keys in place far many years When the proper voltage ie applied the battery no curent This allows the bariery be replaced withou risking the integri ty of the RAM based keps Even if would be chief monito your device bitstream that is encrypted is completely useless 1f that bitstream is program a difieren device without the onec key the device will not program 1 addition your device cannot be altered onc it ie programmed with scuse bit sem Partial reconfiguration and tead back are bath imposible neither can be dare without clearing the configuration memory Thus IP designs cannot be copied or reverse engineered 9 Xiliscencypted are to generare and yet they provide extend robust protecion With DES and Tipl DES manufactur ate ensured t
90. ce Riqua by adding dial d s Tha ein a char ls delayed bur has peret phase to he lal receiver equezey can drive global lack rescues general lope interconnect and pads simultaneously This provides sail when placing loi m High Peformance The mos valuable feature of the Vines for implementation of advanced systems the extremely higher france This gives you a great degree of freedom that is not available with alema tive implementations such ASICS To the value of this advantage consider the following scenario OFDM Fld Deployment Example example OFDM synem it deployed on an expeimen basis by a wireless service provider Ie is located in an Alccated Bandwidth FERRY ope of buildings and so on and manually upgrade circuit boards in the base sations Keep in mind that many of these base sta tions are deployed in regions of the wodd that cacti extremes This expen tive and dangerous upgrade path is of cost of ewnenhip of a ae ation conven tional ASICS Ney anion Vida Viel Pm FPGA the core of dn ele be ion y be compe singly by wane new Gen he cone af piper Sev can be eof anata ier a ing ty Th pee Ver dom you M ncn the prc to
91. cm do be video IP deepen ad quen Mal The video band i pl venion ofa oed The add of Nh landed ideo rana om vau video tour lo citron ecler ipee Tho ing math yos can manip and mese the vdeo The Vine FPGA provider high sce to dese od mens high ds ida and Be nay coral ag The Vinee high lias by lel 2s complemen block m iple which id kigh pad ma Dig Manages DCM which dock dede equi quie Se clock phe hiking ind EMI reli Global lack multiplexer buffers which provide clock muhiplexing clock buffering and disibuton connection to a Local Area Network LAN and the Interner so you an remotely update the inter nal algorithms Configuration fiom compact fash memory providing way to update and store changes to the program ming bit team of the device Supported Effects Using the Video Demonstration board yos can mix video steam fom many diferent sources in interesting ways For example you can easily perform the all video fade or alpha blend from one scene o another where the cur rent video stream such at basketball game live fed from disappears and a new scene appears sch as a commercial To accomplish thit
92. come Product Group for With ever dissipation performance and foot increasing bandwidth requirements syi print ues that are usually found in ra tem engineers extreme signal integri vii ditional FPGAs was hand to justify the ty issues Our XCITE signal integrity switch co of an ASIC when Vinexll FPGAs technology in the Vintec It FPGAS des m m Mentor Graphics CEO Discontinuity at the Gate A New ME Era in FPGA Desin Tc append when you gie he design li vision in programmi will how you weed hi platform that conis 10 milion sem ized this and quis 300 internal cock speeds Lern ppm pe dign methodology Dy providing sich robust capabilities in programmable for mat you create a discontinuity in the indus chat previo mcn baie the product development process The Xilinx Perm FPGA family embodies this emerging tech nology the change our eure design Today a 20000 mi bie merap son on NRE dun id nd Aten doe i mar Ae nao a cll P rert ipic v 200 000 Thi mnie ii D pnt depen Sens sar ei FPGAs Coming of Age The puh to harmony beren design tools and is extremely challenging For example showa in Figure 2 in the
93. content of che memory by ether swapping removable modules or programming item The ACE Controller chip comes with cool logic and a variery of spe alie interfaces This device i the inter ace tothe ACE Flash module the FPGA an environment and a microprocessor The ciety is optimised for reading data from and writ ing dara o the ACE Flash module The default configuration mode takes bic ireas from the memory module and configures chain of FPGAs via JTAG rm uin There a test JTAG interface for programming and testing of any devices supporting JTAG Boundary Sean The two main advantages of the Spm ACE solution are synem configuration management and upgrade management System Management Synem ACE technology is the fit pe engineered centralized configuration solution provide both bit density and the contol logic to manage configu ration for all FPGAs within system Along with an optimized memory FPGAchsin chere also an interface for access to the FPGA chain by external proprammenltesten and a generc microprocesor interface far ine grating ACE technology with the Ten of the synem configuration management minimises board space simplifies chang ing bitstreams either during prototyping ot in the field and allows system micro processors vo have mort vole in leveraging seconiguration to incre ayt
94. d the mulipler resource are connected to four switch matrices to access the general routing resources Global Clocking The DCM and global clock multiplexer butlers provide complete solution for designing high speed clocking schemes Up o 12 DCM blocks are available To generate de skewed intemal or extemal clocks each DOM can be used to eliminate clock distribution delay The also provides 90 180 and 270 degree phaso ehitod versions of ts output cocks Fino rained phase shiting offers high resolu tion phase adjustments in increments of 1 256 of the clock period Very lexible Irequency synthe provides cock ouput frequency equal to any MD ratio of the input clock frequency devices have 16 global clack MUX bullers with up to eight clack nets per quadrant as shown in Figure 6 Each global clock MUX buffer can select one ol the clock inputs and switch lich roe one clock the other 15V Field Programmable Gate Arrays FE XILINX EE HP oon dian BELT E B wow B H E ow mam ES Figure 6 Virtexll Clock Distribution Routing Resources The CLB block SeleciRAM multiplier and elements all use the
95. din every CLB these starting segments provide an ideal way for the block to Taken together these three properties consiste the key ingredients of the new Vines IP Immersion Condesion The series of Platform FPGAS ate engineered to provide leading edge functionality in logic outing clocking DSR memory and UO Thanks to the innovative IP Imamension achienute and evelopment relationships with leading companies such as IBM Xilinx Vies Platform FPGAs facilitating the next of advanced syer desigas Sofware Using Xilinx ISE Software Tor High Density Design Creafirig your Virtex 4I design is easy with Xilinx world dass development systems The latest Xilinx ISE software provides support for advanced design capabilities including incremental Synthesis modular design and integrated logic analysis along with the fastest place and route run tim s ip This means that you g t the features and performance youneed quickly and easily And because of our cooperative develop mei fforts you can take full advan age of tie lot st odvarices from our EDA Alliance partners as well by lee Hosen gates and paths together and you Hlooplaming at the beginning of the S Podo Hak can simplify your design by reducing the _ process serves three main lohan number of interface ports berween mod and m
96. dm nds poe 5 el Too Math Su Boga ese ls DCDC ems Sat for Yo FG ugg S S Vit Fs Shui Ae Hem POL Su 4 ou 200 Wald TS Ved Pa Gat Min Pec i FPGA Platform FPG olution Launches New Era of High Performance System Design The result of the largest silicon and software R amp D effort in the history of programmable logic the Virtex I Platform FPGA solution hd produced major improvements in engineering productivity silicon efficiency and system flexibility Up 12 DOM the inne of mao bling Moda gel Ch Manges pep Xi FRGA deir slow igs thing ck dsc tad bc EM Fiene adiu do cuis Sige Ths luce Mode dr wr nw in depen design from such athe IBM Lr mon and highspeed Thee now yog own in 1 hard macros dramatically increase the gd ali GAS e ph b _ a Vince i aes IS dar Or wich many s the alime 0 1 108 user tem design isthe Best in the semiconductor pine 554 differen Vir I Paire for today s cuting industry to provide on chip digitally con ial LO pai edge applications _ rolled imped
97. domain and direct implementation inthe FPGA Doriga Managment With the Xilinx ISE sofware you can wi lise many diferent tools and design mesh ods To help you man age these options and deive your design to a smooth completion provide the Project Navigator as shown in 3 CORE Gorter Using the CORE Generator are customizable allowing you to modify them for your specific mech manage chis process Xilinx provides the CORE Generator as shown in Figure 3 The availible cores ae dis played in library interface so you ean easily choose the appropriate core for your needs The coe adjustable for the parameters you want vo customize and the arclpeed trade offs appropriate to your specific design You can link the CORE Generator to the Xilinx IP Cemer and receive regulat core updates Internet for IP is bo integrated imo the Core Generator to facilitate design euse You can capture your corpo tatedeveloped IP as standardized cores and use the CORE Generator as cata loging and delivery vehicle Your cores then appear in the library inerce for later selection and use Using Standard Functions Using a cor to solve a critical design chal enge is only a part of the overall solutions you also have to interface thar funcion to the cutie world key feature of the family is high speed connectivi m the internal logie t
98. e core logic Alona the average deny of FPGA designed ino new sperms ie growing rap ly According Dues rg a tidal FPGA deni ge 1 in 1999 and 67 in 2000 Challenges The increased of FPGAs in individ val electronic yer is leading to a grow ing focus on FPGA configuration When only one or two FPGAs are used in system often only one configuration bit stream needed In this a dedicated configuration PROM is a fast and simple configuration solution The speed and ene of implementing solution the of additional board space taken up by the PROM m As she number of FPGAs per spem and the need for im grows however using muliple dedicated PROMS becomes unwieldy With muli FPGA sytem it becomes more eficient have a centralized source for configuring all FPGAS The standard solution has been te an fash memory by an embedded microprocessor or PLD Wich microprocessor configuration data i pulled directly from system memory over the memory bus and fed to the FPGAS through he JTAG interface Alternatively PLDs paired with commodity flash memo ry ean be configure FPGA chains supplying dat either serially or eighe at a ime PLDs manage the chip enable and addres lines while configura tion daea is fed to the FPGA chain While these are valid option
99. e the channel of che bus Once the coe fow cont informa tion it determines the link des and amount of data send The core monitors the fil level of the source FIFO vo deter sine wheter to send dota or idle contol wonde on the PLA Condonin The Xilinx POS PHY Level 4 cores are available as designed to imer operate with industry leading POS ATM framers and mapper to achieve carrier dat performance The have been configured vo inre to a single channel OC 192 device a lohanne by IGbls device and a channel by 25 device Working in collaboration with engineering teams fom PMC Sierra and others Xilinx in verifying the by wing reference designs provided by each product developer The Xilinx wam solves system 10 Gbps performance require by offering interoperable standards compliant Packet Over SONET cores FPGA Configuration System ACE Technology Configuration Manager Breakthrough designers today face unprece ested challenges and opportunites in New configuration manager technology from Xilinx provides e a flexible pre engineered high density configuration solution and standards ae con and changing Customer pon d log to Beet ments achieve system flexibility and per formance targets and tap into new tech nologies sooner concen sta
100. elopment Platform and Vireo Evaluation Ki Elantec DCDC fects Converter Solution for Virtex FPGAs 2222 interface power supplies the interface requires 53V and core ci requie either 25V or LV You ned sulle power supplies and you nex to coor inate he power teaching and sequencing beeen supplies Many board design are challenged by these Monopower Integrated FET DCDC Converters provide n optimal solu tion for FPGA designs The EL7564C a unique Synchronous Buck Convener wih FETS and Internal Current Sensing These enable high higher frequency which leads to smaller inductors and fewer external component hing in minimum board space Gore Foun d Open Tia as Vo Seda ening Dey pet Dind Tile Rar The EL7SG C can supply accurate of 33V 25V LAV and L5V in quantities up to 4 Device can also be d to deliver up vo 8 Amp or more These devices meet power needs of the Vine Vines and FPGAs In addi the Elantee EL7S6AC i able to sup ply adjustable voltages for terminations down to 109 8 d Wwe GOO GG
101. em flexibility In systems with multi ple boards connected through baci plane ACE module can be the per board to manage he FPGA con figuration of esch board I however one JTAG chain connece all FPGAs across multiple boarde ote ACE module con configure all FPGAs across muliple nos Sytem ACE technology allows for the of multiple bitstreams atone time in one location permining one board design to serve multiple purposes For example if slight variations of an FPGA based system are being shipped vo differ ent markets for example to accommo date diferent interface or elec trical standandi single board can be designed for all these markes simply with disent default system configuration bit determining system funerionaliry For designs using FPGAs with Empower embedded processors Sytem ACE can be used to configure the FPGA provide the boot code for the embedded proces sor core and store and deliver the ation sofware to be run on the proces sor core This gives self contained drop in configuration and sofvare stor age solution for FPGAS with embedded procesos requiring interaction with an external processor pg Syeem ACE gay upgrading or debugging FPGA acd y Bep Sistem i ACE T 7c plus oy piel epg Emo oc cw Because System ACE technology uses removable media s
102. entation see Figures 1 and 2 Koy Features The developmen kits affer low cost devel opment board solutions and provide an aorment of useful for the designer Based on the 256 ball ball grid FG256 package bonds avail able with either 40000 0 or onemilion gate 21000 Viste It devices The can be to configure the FPGA directly or io load the included XC1800 series ISP PROM Both Insight Viterll development boards house two on board dock oscilla tors that operate at 100 MHZ and 24 MHz enabling ues to incide multiple dock domains within their The boards provide additional extemal dock inputs for a total of four clock inpun Using System1O technology the Kits feature user selectable bank and rer ence voltage jumpes that support many emerging 1O standards The VBANK Jumper senings allow che user vo config ture each bank of LO pins on the boards to operate in 15V LEV 25 or 33V modes Six wer selecrable VREF settings enable the user to inpar a threshold volt ages tequied by some input sandanl cer tain user pins Alo among the Vinel development ges the high preci do 30 Ohm VRN and VEN iners on M dhe UO asks These reto XCITE DCI comb A bak ok
103. es inevitable but mow isa way make dem much faster and far es expensive The FPGA family unique migaton maim PCB compatibility scs diferent device densities and packages You can increase or decrease density from 40K w 10M spe the sme PCB footprint Whats more you can change chip packages without losing foot compu Wah lie planning you won t have replace your boarde when you upgrade to a new FPGA The Vien family consists of 12 devices cffeed in 10 diferent packages While of course they not completely interchange able strategie Xilinx engineering has deli trod unparalleled design migration flexibility This anile explains the rules and advantages of compatible deicelptcloge pinouts and Footprints and a special overlay chat graphically compa ible pinout migration All 10 Vineet package ball gid CS denotes wie bond chip scale BGA 080 sus S144 in 03 ram pitch FG denotes wirebond fine pitch BGA 100 s denotes flip chip ine pitch BGA 1 00 mm denotes BGA 27 mm pic B6575 BE denotes ip ip BGA 127 mm pic Foc mom deuil see the Vines Data Sheet 4 of he Vict Pam FPGA ter wns Patpa dev
104. fom Synopsys and Verplex will be supported Formal verification i unique new tech nology bought about by the transition even higher densiy design projec As the potential gate counts of designs have grown need for test vectors has grown cordingly ata goomettc rae Device ver ication therefore becomes a daunting task This has led vo the growth of formal for pro gramme designu Inthe equivalence checking venion of for mal verification mathematical algorithms are verify de logic at each phase of the design the version By comparing of logic equivalence checker can compare designs in a marter of instead of the hours or days that sequined uing tradicional simn ation techniques Whenever a new mage ofthe design fow bas been completed you an quidlly and the equiva lence checker o verify that the sil System Using a logie analyaer common way verily the accuracy of hardware so Xiline created debugging tool that integrates a logic salyer otto the silicon uel Our ChipScope software combined with the Integrated Logic Analysis core allows realtime aces to any node in the FPGA with an easy to use GUI interface You can easily and verify device functionality without the added overhead of creating et and amuses For Platform FPGA desi
105. formas that to we all power supply sources are included onboard Voltage references for SV 33 25V LBV and 15 ae all derived from the 5 VDC input 110 VAC to 5 VDC adapter even included to get you up and tunning as soon you open the bor A Compete Solution Like many other demonstration boards and development kits that Insight Eletronics offers the Viner kits accelerate your design effort by providing the fatus you need to complere your deiga The boards ome with several reference designs for test ing he LVDS using the RS 232 implementing an interface to the DDR memory and much more of these designe dowa loadable via Insights Reference Design Center www insight eeconicscom elutoral Web bud availble development kit owners Insight abo offer a special WEDPACK kit version that includes the XC2V40 based Vitel board and power supply WebPACK CD and a JTAG programming cable The WAPACK CDM comnis the implementation tools w take users all the way from VHDL or Verilog design entry and synthesis to digo implementation and device programming nights worldwide led applications engineers provide technical support can teach you how the demonstration heute and devdop ment took and they can recommend application Insight Electonics has introduced owo VinexI development ki that help devel
106. gn particularly in ladle packages ChipScope delivers realtime on chip debugging The Xilinx ISE software contains a variety of verifeaion methodologies that enable you vo verify your Vine I At the module level or the device level you can ensure har your designs will work corer the real world For mare information on Xilinx ISE software go te apt heer rins xil prodeat landingpage ptt Designs Tools SIE Designing High Performance Memories and 15 605 Using by Kista M Mods eng Manapa Sos ih nt The Vinal architecture offers exiting sev design because indudes numerous high performance embedded memories and maliplien These seo components form the many applications appearing in a wide range of functions including digial filers FFT FIFOs serializers encoders and analyzers Because memories and multipliers appear inthe functions of an application is neil thar they te optimize foe resource ulia and performance Because of thei ubiquity ic is equally esen tial that they can be implemented repeatedly without significant Milina provides core gener Aon sofware that produces ready to use high performance design solutions for dhe embedded memories and multipliers of the family The CORE Generator ena
107. hat their proprietary Vitex I implemented designe ae safe fom piracy For mare information vefer 1o tbe Victa Platform FPGA Handbook at rr iles handbook m New 05 Xilinx XtremeDSP Initiative Meets the Demand for Extreme Performance and Flexibility An FPGA DSP solution boosts performance while Conserving space for demanding wireless ond video The ies mete prm The XremeDSP Initiative With the new Xilinx Initiative you now have flexible DSP solutions that you can optimize for numerous applications Furthermore under the initiative you gain wide range of integrated development tools that offer an added advantage when developing new products or upgrading enining ones The XiremeDSP Initiative delivers nne Pokemon RAM based Viert and Viner series FPGAS Barone Pedy easy to use system level design tools optimised DSP algo riche IP cores and world dass DSP service and support program oven ity maximized perform ance minimized seduced devel opment time and extended produer trome DSP Delivers reme Performance Components such at hyper fast adaptive files 3G mibo coders and rake receivers used in next generation commu nication products ike spread spectrum radios require new high performance and flexible DSP architectures
108. have that range fiom 50000 up to one milion mew laform FPGAs Viner Seis high RAM o logic ratios that target pa This family supports 17 LO delivers enhanced system memory and specific applications such as gigabiwper standarde 5 V PCI compliance lighming fst DSP through a IP second network switches and me immen on fabric devices definition graphics me gt Sent H ala DEE F in dg ll DIE E UE hseiii sci Spee ENS ROSE EE Slice Se ae HEE ee naana ee foam menier of nee Seto ESS AXI Elis E Sa Gee aes uk The VinerE family upe toons sax an pue err tf o at Mem Dem a FEE E pee Pro meme mre everti EE EE RDS BOK sz Y X and Bus LVDS 3 nem am Y x AGES AE Satay E EAH E E Y t zu m SPARTAN
109. he of memory logie gas in the Vines family vill continue to incre over tie because tomers demanding more and more memory The amount of block RAM and disrbuted RAM wil increase as well ably to access of chip memory memory standards evolve wil memory interface capably Clock management is another ctl aor in sg designs The Delay Locked Loop Digal Clock Manage is already the mos advanced rich dock manager in the industry Te eliminates dock skew pro Vides very lexible clock synthesis capabilities and gives you the abiiy to dive and rosie docks bol on and off thus elimi nating The embedded multipliers in the Vinex family you to creste the fastest possible DSP deigna cusomer are achiev ing unprecedented speeds well over 600 billion Multiply Aceumulate Cycles per second Many customers are pushing the performance and den diy in designs requiring very sophisticated DSP algorithms co the data from the thes hand multipliers so useful in a wide range of applications they will be dded to every Vitaly FPGA We will continue to develop hand and soft cores thar make ll use of he Vines any architecture to bring you all exe ose and performance advantages that make Plor FPGAS so VO Philosophy Over the few years we hue made tremendous
110. high performance lock manage ment cireu try and DLLs Delay Locked Loops for complere sytem integration including DSP memory and conto logie Up to 420 MHz internal deck speed 840 Mbps UO performance The Vitel architecure provides the unique Xilina Active Interconnect vechnolo which drives seg outing each building block lement on the FPGA Combined with Smart IPTA technology Active Interconnect cnius performance is consent the endire of FPGA device sises and it inde pendent of the surrounding werloge and level of integration Devers Extreme Productivity Having high performance proceing platform only part of the solution implementing DSP functions in a design requies eny use IP Intellectual Property cores and develop ment tools Thus complere solution inconportes to provide design time efficiency and the ability o customize data Through he XuemeDSP Initiative Xilinx provides solution diat allows you to produce the optimal imple mentation any given application or sero numerous applications The Initiative alo provides wide inge of DSP algorithme or IP cores in the Log CORE series and the design of communications and image proceuing applications A new fer generator woo for instance allows you work in MATLAB a high performance simulation progr
111. ices have pine Programmable user fom in and FG256 package o 1 108 in the FF1317 pce Control pins including configuration JTAG and special purpose pins such as VBATT dhe pin types are similar regardless of the devicelpackage combination The number of pins always 16 including VBATT The number of powerlgound pins and user UO pins however depends on each devicelpackage combination The total number of available for each device package hated on limitations Maximum number of pins on the package Gee Vitel Data Sheet 1 ZWineBond Packages Information and Hi Chip Packages Information Maximum number of pade on the die different for wirebond verus flip chip application For example the FF1517 package limits the number of wer MOs o 1 108 pins in the XC2V10000 device 1 0 Banking are split eight banka te provide more in choices and XCITE cubitis The VOCO and VREF voltages necessary m ecl Vitel banis fr wie band pelas S FG ad BG support standards 15V 33 connected to pins dat serve banks of WO pine The bank organization depends on the package Figure 1 represents up View for wite bond packages CS FG and with banks in clockwise onder and Figur 2 sh
112. ici respective mod eed in a single tightly integrated package partition your design as shown in Figure 1 Tand engineering manager can later eg wil consin Mechel mol andyis fonctions without Gall design management and pie blesto specife pa aes of the devs outing all mols vo be comple mention environmen sina are known design man ager can also map them or 1O Floorplanning helps vo accelerate imple Integration for de most widely uel for fre we ima ayasbesis engines in program mable daiga inducing Synopsys Synpliciy and and eny design Simulation integration wih The place and oute technology avail able for logie implemen EDA partner integrasion your exiting design sofware Parting To make your design proces more manageable fest pation your design into hierarchical func tional modules By parti tioning your design cor you can accelerate timing closure by keeping m 0 Design Croation The ISE software offers a wide range of alternatives for creating your design VHDL and Verilog Design Entry The mon common method of design today ie through either VHDL Verilog language text entry using a stan dand text editos or contes sensitive lin gage editors These editos allow you to emner complere l
113. ign Bow facilitates eficient what f analyses accelerates timing closure and increases em performance High level floorplan Ping and modular design make it casy to nm realize he primis of true team design The Xilinx System Generator together with The MathWorks MATLAB and Simaulink modeling program provides a powerful design package using tole already familiar to system and DSP design These software tok and the library of Smar IP cores which are pre optimised for Xilinx devices enable Rene 3 NCTE capabili designees vo incre overall design pro duci and reduce time to masker Engineering produci is also enhanced by de Xilinx IP delivery proces Everything from IP building blocks sophisticaned IP cores for design reuse at the designers command with Xilinx CORE Generator sofware Up to the minute new IP cores and IP updates are avilable from the Xilinx IP Cener ar Verification Slaton One of todays biggest challenges is the verification bondeneck Platform FPGA programmabilig makes many time con suming verification tasks such as chip level signal analysis and scan insertion unnecessary Xilinx design rool allow eficient of desktop and inlab verification times With complete support Sor all verification checkpoints including RTL Register Transfer Level simulation accelerated timing simulation and even Powerful
114. ily i uniquely sited the demanding dig signal pro esing that will be roll oue next generation broadband wireless services Powerful suite of dedicated high peraem ance logic functions such as the high speed multiplies and DCM along with extremely versatile high performance gen eral logic define an optimal solution for designs T in Pls dy for mu eventualy you have to verify the operation of the actual dece 38 ty Soda Poehimann ny at on lol ges pbb Dat on Debugging complex high performance FPGA designs can be a challenge With sin you cin simply connec a to all of the ines going ino and cu of a complex device and gather dita to verily the system or locate the case of a ise Today however many highspeed designs ase wing diferential signaling such LVDS to minimise switching and ront noise and ro allow raes rater than one gigi per second The Vinecll FPGA fay includes LVDS capably on all VO pins Tie Sein The challenge you when debugging signals ic comeing them to a log ana The Agilent approach you to connect directly wo the FPGAS LVDS signals The 16760A and im inganalysi module or the 16700 series logie analyzers alone you to diely pure dif ayer connected directly vo these tinct shown in Figure 1 A
115. in tions Because thee systems can retain consistent form fit and function through the use of Vitex QPro FPGAS This cannot be achieved with costly and inflexible ASICs or custom logic visit hic forall the information shout these products including some new applications notes FEATURES al 1 Els iH Devico 3 35 4 8 55 TET ea a xam 009 imm ser ios zm Y xanxaepgaxt 9A Performance jamas 2300 5 376 vat Y x KONOBSKL Memory sess 3136 7 108 Y Wee zx wo v X 10 mme e snas o v X SIRS am ies umm mr x n Samet BAM ones 224 Y x EI M DELL pom QPro OML Cortified PROMS tap ae MM Wm m dium m mm e 5 XOR devices are radiation hardened XO des ori wo Xilinx Intellectual Property Solutions The Most Comprehensive and Highest Quality Solution in the PLD Industry The Xin Propeny Solutions Divison offs the of Propeny solutions a wide vide of industries and applic
116. ing high performance DOM pti eps Tace 18 CLIO eg ed DOM opt Tince 2 ic the eme of CLAD and phar aed CLIO Tae 3 ates expt with MoS D 1 and pha aliod with Tince it CLE 180 out of phar with Thi diagram whe feque pb generering a clack output het t 3X the cock CLKIN Mar 1 a a E ew Fired Pha si ce umes resources than two copies ofthe lle Frequency Synthesis implemented by sing the 1 and CLKFKISO The frequency of thee dicks equis the input dock F multiplied by MID the numerasor is the multiplea ion and D the denominator is the These wo counter pase quencyapbeisd cupis can deve global dk mning within the devices they are wellbuffered vo minimize clock shew duet diffrence in or lod ing To de ikew these a feedback signal must be provided ro the CLKFB input ofthe DCM either CLKO or AEEY WI TEY rar nien gere 5 DOM pha Tae 1o 100 clack input DCM Tace 2 it CLAD lycopene with a fine phate shif of 13m with CLEIN Tre 3 ie CLISO 2 out af hue with CLD end Trace is uie the fey of CLEIN and in ph with CIKO Thi hg she te pla if fue of he DCM withthe pha if nale 934 100058
117. inimizing delay 0 divides your desig ISE Overview pin manageable sub modules foor planning the design manager can erate With the Viel family and the Many will determine how these black box definitions to define the Tim iain ramble sadler shoul bedi HDE modules This each designo log has mare ins oii the corer dan defi as simple lu logie Programmable What ae kills and sent fae of module and devices now the cenena components in lable designen the design manager can xl geom advanced designs because af he device can prior design functions at any ime fom the ther high performance deni Wor be led top Hack of the device without requir and advanced To fl advan ing ll the modis to be complere of dee advanced devices you meni How many funtion can be implement vanced high peomance devdopment through core or puch IP using forplaming the engineering tools as well and thats what you ger with Which areas of the design will manager can create module boundary the Min requise unique or intensive design definitions to initially describe the work and rework HDL module entities This allows The Yin negated F 2 signee 1o receive he conet design Environment provides everything you che Xilinx High Level Floorplanner to einen for d
118. interconnection is hierarchical and designed to support high speed designs All programmable elements Including the routing resources are controlled by values stored in static memory cells These values are loaded in the memory cells during configuration and can be reloaded fo change the functions of the programmable elements Virtex Il Features This section describes the main Vitex features Input Output Blocks IOBs are identical and programmable and can be categorized as follows input block with an optional single data rate SDR or double data rate DDR register Output block with an optional SDR or DDR register and an optional 3 state butler to be driven or through an SDR or DDR register Bi directional block any combination of input and output configurations As shown in Figure 2 the IOBs include six storage elements Those registers are ether edge riggered D type flops or levelsensitve latches m 5v Field Programmable Gate Arrays Bp 1 bol ies l pi Figure 2 Virtex 10B Block 1085s support the folowing single ended standards LVTTL LVGMOS 33 V 25 V 1 8 V and 15 V PCLXat 133 MHz PCI 33 V at 33 MHz and 66 MHz GTLand GTL MSTL Class LI Il and IV 8511 33 and
119. is mew standard targets 10 serial channels by bonding four 3 125 Gbe transceivers XAUI targets the OC 192 and 10 Gb s Eaherne markens for WAN and LAN routers Condon Having solution that support all hee var ste interes is crucial ro success in the The Vinerll FPGAS solution offers emaily thia support for physical interfaces as well cores that support the protocols For all the common and emerging yem interfaces FPGAs enable high performance inerhcts vo memories fom Cypress IDT Micon SiberCore GSI Technology and as well as nerworking ASSP Application Speciie Standard Parts from vendors such as PMC Sierra and Vitesse Now with Vines solution you can pick any standard and any vendor offering that standard in their and rest dur Xilin Platform FPGA wil uppor andan p Pinouts Footprints in Silicon Compatible Pinouts in Virtex lI Devices Enhance Design Flexibility Advanced Virtell architecture allows you to change FPGA densities without changing PCB designs by Belet Pr phar Manos ea production deg changes are comman in today s produerion environment These changet often force you to new PC boards and incur lang dal because you ite a larger or smalle FPGA meet your new Dein chang
120. ith other ending ner papnsm Est itary eee Tu dign and deployment of das siding The POSSDH Physical Layer Level 4 and routing produc using impedi interface he intr networking wchnologin The connection of Physical Layer devices Data improved and lover per Link Layer devas in 1OGhls POS ATM packer transfe make ie applications While Xii an enabling technology for gigabit FLA core can perform the inte funcione techie and switches anda wide range of miser ice DWDM Dense Wave Division Multiplexing and SONET SDH based anni on sems The PLA coms implemented in Vinerll FPGA allow next generation owed developers o seduce thee eto mathe In addition providing fally standatd complisnt cores is collaborating with leading device dee induding PMC Sierra AMCC and Conexant vo ensure imeropenbiliy on boh sides of che PLA bus shown in Phase 2 heroe Madal Figure 1 the FPGA implementation gen intended to operate the Data Link bereen Xilinx neworkingcorerandthe Layee aide aes industry produces By combining the performance of The SPL PLA ince has the following deis Xilinx PLA cores and PMCSiemis mel characteris orCanetants OC 192 PHY devices acom
121. iting proces can increase or switch throughpur by at much as four times For example a router Wih a processor operating at 622 Mbps can increase its throughput to 2 488 Mbps by adding SiberCAM co proce The enabling technology Virer Platform FPGA is single chip solu tion With as many as 10 million system an abundance of on chip memory options and advanced routing resources the Virer Platform FPGA interface enables you to eliminate external termi nation resistors with on chip XCITE digitally controlled impedance technolo y manage 16 pre engineered low skew dock domains and fequency and phase with digit clock manager Furthermore on chip DDR tegiters and output and 18 Kb dual pore RAM make the Viel Platform FPGA the technology of choice for next generation of network switching and routing subsystems For more information see rra inm combsapplespp 254 pdf and mrms bereore Mtm Networkin Xilinx Announces Terabit Networking Forum Industry leaders to discuss next generation sys tem Mond bra that e fe Year 2001 Worldwide Xilinx Event Schedules network demands of the terabit revolution EE Jone BAD Les Vagas A ty Ron ne HD bpo M Mop Jai Wed 200 Sst ag A in clarion with indy lede ishing he HUG 01 Boa
122. itt registers SAL16 as 16 bit distributed Select RAM memory RAMS In addition the two storage elements are either edge triggered D type flip flops consita latches Each has internal fast interconnect and connects to a switch matrix to access general routing FX XILINX viet 1 54 Fleld Programmable Gate Arrays Block SelectRAM Memory The block SeleciRAM resources aro 18 Kb of True Dual Port RAM programmable from 16K x 1 bit to 512 x 36 bits for each in various depth and width configurations As shown in Figure 5 each is totally synchronous and independent fering three read during wrta modes Block SelectRAM memory is cascadable to Implement large embedded storage blocks Supported memory configurations for dual pon and single port modes are shown in Table 3 3j Figure 5 18 Kb BRAM In Dual Port Table 3 Dual Port And Single Port Configurations TKI aK xa bite 12x36 bls A mulligier block is associated with each SeleclRAM memory block The multiplier block is dedicated 18 x 18 bit multiplier and is optimized for operations based on the block SelectAAM content on one port The 18 x 18 multiplier can be used Independently ol the block SelectRAM resource Road muliplyaccumuiato operations and DSP fiter structures are extremely efficient Both the SelactRAM memory an
123. ive you complete range of value oriented produc XCS0U Offers industry leading while giving you the of an enhanced cusomerqroven piecocking architecture along with extensive 1491 Boundary Scan support Offers the patented Fase Zero Power FZP design technology combining low power and high sped Thee devices offer standby currents of 100 mieroupe operating currents 50 67 lower than CPLD and pin to pin speed of 5 0 ne A WebPOWERED Software Solutions Offers you the to target Xilinx CPLD and FPGA products online or on the desktop including Offers you an online and evaluation tool dar HDL ABEL or nes files and provides all reports simulation models and programming iles along with price quote Available to support all Xilinx CPLD produces ISE Offers downloadable desktop solutions that offer CPLD and FPGA sofware modules for ABELIHDL synthesis and simulation device ning and JTAG programming Through leading performance free Internet based Web POWERED software and the industry s lowest power coneump tion has the right CPLD and FPGA foc every designeri need Soe wena com for mere information E 8 8 i i Bs H e E Em MIN FPGA Configurations N PRO
124. keep increasing becomes even mare importane tat we pro videa wide range of neler property or cores which you quickly develop your design Without cores would take many engincer ram 1o complete 1O million gate design With cores you can quickly create key parts of your synem using proven doble designs pluformi philosophy ito provide both hard and soft cones that take full advantage of four Vinex architecture Hard cores such as the PowerPC ate scaled logje design that we incorporate imo the FPGA device architecture Wherever posible wel ofier soft cree to salve your design challenges because they ae more exible and a ied on an 2 basie Well tages The Vitex architect allows you vo integrate both types of cores ino your designa giving you the animum Bey and performance Hard Cones As we more forward well integrate more and more hard core into our FPGA plat Form vo increase the performance and ete of we Examples include central proces sors memory blocks dock managers multipliers and high speed UO systems Processo cores you a lot of develop ment time and they give you a known telible design Our philosophy tightly integrare our processor ingo the FPGA fabric so you can achieve tremendous performance advantages that would nor be available if you used sepa proceso chip Memory is a critical of most T
125. l serial design fow Using Timing Constraints Wih Modular Design you on on sealer design modis and each of hoe modules can be implement eb separately Therefore ing timing constrains foc synthesis very similar v the general synthesis rules for small to moderate designs However there Few key facon that will alit high density implementation Be careful not wo owerconamin your design Many designers operae under he mistaken belief diat by ovenconamining a module they will guarantee timing However over constraining can force the oo o induce extr gates into the finished module One method to con fide i to begin implementation by syn without ding Let the tol work forthe bese design and peior to you dar will use problems then you can go back and constrain only those portions of the mod har need bener timing Lm Use Good Coding Practices Timing can also be seriously affected by how well your design code can be synthe tized Xilinx recently announced the LO coding syle guide for the Synopsys LEDA Library of Eficient Data Types and Algorithms tool language checkers The LEDA tools can verify your module standard good coding practices This reduces chance of problema dur ing implementation due to bad coding styles such as introducing unnecessary latches ino the finished module which may cause timing analysis mistakes
126. linx LogiCORE program hundreds of standard TP functions are available These indude such as multipliers filters FIFOs error conecion uncions HDLC con The ISE Project Navigator shown in Figure 2 wher you drive design e contains a complete VHDL Verilog ln ge editing envionment with comes sensitive help and language templates to help you quickly enter your code Graphic Design Entry Graphie deign entry experiencing in high density design In the Mo and truth table and flowchart logie entry that can you can then output as VHDL or Verilog code Thee graphic entry methods also help you to document your design in a very readable and easily understood format they the prefered method of entry fer a growing number of design en neers depending on the size of the rar module lls od video blocs The AllsneeCORE of de bent dis pay IP available And the Reference Design progam fies advice and design applications from design cemen throughout the world Xin Jas bundled this information together and makes it available through the Xilinx IP Center wrewailinecordipcene Hete youl find everything you need to design with including the recently announced procesor core LAB Simulink and GRE 0 a Te lt a ware bridging the gap beween ayitem deign
127. ll FPGAS provide designers with the performance and density they need to create an SOC design With features like digital clack management select ulema technology and active interconnect designers can apend more time on function al verification knowing that the main silicon and problems have already been solved In addition with IP immenion technology FPGA designers can now work at a mach higher level of aba tion and move the gates per day metic to level where silicon utilization maximized Platform Bead FPGAs The Valo of History resting and pur ting boundary conditions on a design process can development and shonen time to market The ASIC SOC development proce in place today is an open ended approach to design with alot an infinite degree of freedom This free dom provides and has enabled the creation of extremely complicated cir lis but i has also created high risk methodology with a step learning curve In contrast provide a approach to design From the designers point of view the beauty of cresting an FPGA is thatthe FPGA vendors about all the issues of the design proces icon methodology and sofware Piper Pla bed FPGAs IP bogie From the FPGA vendor point of view they need to provide their customer vith solution that enables high quality repeatable
128. mation every lock yd with completely CUN due pp ae predictable senis When operating inthe scil envonmenl lint is he DCM ot cd by alae ae sik ange QUSS 1 ded 00 norte hangs and ne a ped Table 1 is a comparison of the power and ground pins or extemal net Fue show the pba thi in the DCM DCM wh Cypres Rabel on oe te PCB key ou ia phu src 13 whe 10 at inthe cock period m ipse 6 the of die ouput with both the pate dif and the synthesis eure being Meunier aal denloccenly In 6 the FIT phase dift value is 30 or 12 Cooled 1 2 ms whee 10 the dod period M 5 and D 3 D The driani high ecu phase Ing fete of he DCM makas Vini OR Mn pine dese the only FPGAS a he indue vo lir a ipeo dock management sh rm Tiler erm hod The sales density devices ety Hoher Integration Sold be Just forthe alone replacing devices such as the Cypress Tablet lt Comparten of Vire and Use Triple DES for Ultimate Virtex l Design Protection learn how to protect your intellectual property from piracy with encrypted bitstreams using on chip decryptors ty Michal Pete gon Me ec nia poten The Viet architect provides hard ware
129. ment and debug time to design cur lexible configura solutions using onboand resources solve this peoblem Xii developed the Sytem Advanced Configuration Environment ACE configuration manager pre engineered highdenigy confusion solution modis FPGA stems The System ACE cone figuration manager is a very lexible piece configuration solution comprised of the Hab module and the ACE Colli chip shown in Fir 1 The ACE Fash interface accommodates removable CompactFlash 64 Mb to more han 1 Gb modules ar the IBM 2 Gb 8 Gb all with the same tor and board space einen figuration iar 2 Thi poem ACE board Viren FPGA an ACE C nmall hip nd a 256 Mb ACE moda For_penpeetive individual Virer FPGA require fom 300 Kb to 33 5 Mb of configuration This means that more than 200 of de members of the VAI family can be configured with one System ACE solution The CompactFlash interface gives system designers access to high density fash memory in a very efficient footprint that docs change with denny or product generation This technology gives design the to change the density of ACE Flash memory without board redesign Because CompactFlash inter fce suppers removable media designers can change or upgrade the
130. n programmable loge bie wll of cee a woking spem making your PC the pins are avalible othe bu simpler and spen goal TO isto make our acre so that you will never have to glue logic or understand of ach new san dank For example by a varity of different memory ino our FPGAs you can easily connect any known memory device without having to create own custom interface design All ofthese ends wil continue the new UO standards are induced well make them availible on our FPGAS xare The Xilinx Controlled Impedance TEchnology XCITE is another eram ple of PC board simplification and improved signal integrity XCITE places digitally controlled termination resistors on the FPGA so you doni have to man ually terminate your signals with buge samben of discene external resistors This not only saves you a lot af board space and cost it makes board layout mach simpler This bultin termination for temperature and voltage variations as well so your boards are not oniy less expensive they alio mare libe XCITE solves the signal integrity issues d both circuit and PCB designe now dealing with allowing you to Tun your PC boards full speed and get them to marker quickly FPGAs add mare than just logie they are tremendously more valuable because they make your design simpler hey elimi nate othe compone
131. n tools and device programming oliva WeRPACK ISE now includes support for all CPLD families C9500 series and CoolRunner seris and entire FPGA family as well as che 300 000 systm gate Vitex XCV300E FPGA WebFITTER URL wowaxilins com sepresso webfiterhtm WebPACK ISE URL wow zlins com sxpresso webpack hem wo m Version 3 Development Systems Feature Comparison Guide vg LA FOL Er LI ai Des ege Lge avi AT Suis Tig Ae 21777 re igen nob p ML Taina poe De Bok O Tising Tin Dien Puce anion gee Pic nd hate Prestiti CAA TET Device Comparison Guide Lg Ween Moana Antia isn soe domus occu Mam Ancona wc cam Xilinx Global Services Extend your technical capabilities and accelerate your ime market with Global Services portfelio of educa support and design services along wih our award winning website up will give you the expert you need ahead of your com petition and be the to market withthe mos efficent and com We can reduce your learning curve speed p your design cine jump tr your prod uct development ecl
132. nance operations to be performed in parallel with search operations the SiberCAM device can be wed in a 2 pore mode In this mode the maintenance operations performed using the search data Figure 1 In either case the SiberCAM device expects maintenance operations to be performed in 36 bit 72 bi multiplesed quantities ite SberCAM Optimal performance of the SiberCAM vies achive when ics used ins native Spore or mode However in some applications eis desirable to perform main tenance operaio initiate search opera tions and search om a single 32bit interface for example when the SbeCAM device used pcc with proce The Sbeide RTL reference design pemim single device or a cascade of device to connect o Single 32 bit Typically 32 bit would be on a processor With SiberBridge this processor can initiate searches search and perform maintenance operations all using a single synchro nous SRAM or ZBT Zero Bus Turnaround SRAM interface The Vines DCM block SeleetRAM and on chip DDR spite combine wo make the Xilinx FPGA an ideal for this interface Fue 2 shows signals beween the SiberCAM devic on one side of the design anda nerwork processor on the other How Werks The Siherhridge deign enables nance and seach oper
133. nd full reprogrammabiliy N s fs it ool i where the industry sing Extended battery without asleep mode The CoolRunner family runs at 1 1000 the standby power of competitive produet enjoy extended batery with our Fast Zero Posen EZP technology supertow thermal emission and a desig that is allways active because CoolRunner doesn t need a sleep mode Supported by FREE WebPOWERED software The CoolRunner XPLAS family fully supported by the industry leading completely web hosted design environment WebFTTTER or downloading a free copy of WebPACK Talk to your local Xilinx distributor today visit for more information on the coolest CPLD ever XILINX www xilinx com THE PLATFORM FOR POWERFUL SOLUTIONS THE FIRST PLATFORM FPGA here The ne generation of the mast remarkable programmable logic device ever introduced the Vitex FPGA The frst embodiment ofthe Platform FPGA the Vitex solu tion is the ultimate system design platform delivering Systemic interfaces to bridge emerging standards and address all aspects of system connectivity For the frst ime in the industry designers facing the challenges of signal integrity system timing issues and design security have programmable platform that heralds a new era in high pertrmance designs The words first Digitally Controlled Impedance Technology dramatically simplifies
134. neral purpose IO connectors and he daughter connector The RS 232 port pro vides simple com munication port for diagnostics and sim ple application devel opment The switches and LEDs provide the normal initialization input and tequired by your design The general purpose connec tort allow you o tese the board to existing hardware to provide any needed VO capability perhaps to te or debug a portion of a design oro evaluate an IP ove The AvBus daughtecan connector ean be used 10 plug the card into an AvBus complist development pater giving the platform additional logic capa loy and access fearures available only in the Vinecll family of FPGAS Design Services Yo Service Desig Services is the echnical arm of Avnet Inc a odd leder in electronics ADS has sever A design around the wodd with FPGA design consultan available vo ait ou with your deiga ADS akso has an of Geld aplica tion engineers knowledgeable im the design of application wing FPGA devices technology and Thee engines available Ares can help you under sand select and design with Xilinx FPGAs and can alo recommend the ADS FPGA k t thar would be the best fc your design ests Vis for more information om fr for sevice erige comming and e current arabilis pricing irr erature om the Vires Dev
135. nts on your board and they concinue decrease your devdop mene time and co ME you wane build the systema of the and keep your eats dows you nel a solid foundation on which your designs adanca You eed a logie solution thae wil row with you and help you solve problemas that have yet to be encountered You ned the devices toob and company support that make complere solucion Thats what you wich the Xilinx Vinx Poem FPGA Fab already the industry eade by fat and i jus keeps gening bener 1 hope you enjoy this Special Editon of our Kel Joumal feel the need Line arto your design Kins pice up to Btimes taster tor small designs and upto 12 times taster fox he mast Ng deans Clock Management The Virtexll Digital Clock Manager Higher system bandwidth requires higher data rates between devices and advanced clock Eficient clack management i one ofthe keys to creating robust high performance designa When you have precise control of your clocks your design ia much easier to cree and it is much mote reliable The Digital Clock Manager DCM in FPGAs is the most advanced clocking technology avaiable today and it helps you create complex designs quickly and exi
136. o exter mal systems such ss memories network bri PC peripherals and other ASSP To implement these functions you can standard cores such as PCI PCI X RapidlO POS PHY Flexbus SDRAM controllers UTOPIA and soon You dott ned to spend time recreating common interface funcions worry about spending ime translaring bus logi Using DSP Functions Xilinx FPGA offer the highest perform ance DSP processing power you can get anywhere with speeds beyond 600 bil lion even mainstream dedicated digital signal procesors cannot match our performance help you make fll use of this power Xilinx launched the XremeDSP initia tive which provides all the cores the development tool and the support you need Cores such as advanced DSP filers Reed Solomon filters modulators rans orms math building blocks video and imaging algotichma and wireless cores are all available today And through our ce with The Mathworks Xilinx provider seamlessly integrated MAT Figure 2 For each module of your design de Project Navigator launches the correct tool for a given process and tracks the module from ere ion through Gaal implementation Contest sensitive design flows provide puskburan processes to correctly imple menta module and you can see the of all processes You can aloo take anapibons of the running processes enable revision control you can ily re
137. of the two limiting the minimum delay ine 50 pe and the minimum phase shift sep 1 256 x ingur dock period The masimum phase stilling range is the lemer of the imit ing the maximum delay line range E 1n for FIXED mode and 5 ns for VARIABLE mode and che maximum DCM Applications The advanced frequency synthesis be used to generate frequencies in key x plications such a Mob gb 10 bi o bit encoding with 100 MHz input and 125 MHz output FEC code rates such as 528 512 and 8 7 The shifer high resolution phase adjustment feature can be used for Modifying dock to ou timing Maximizing and hold time margin Clock and data recovery for OC 3 appli E TET aea Masterlalave hovlitandby switching All of these features can be accessed simul Fg 6 DOM Pac if and Oupa Tae 00 in a single DCM Bar 14 CLAD dely competed DOM wih the fc phe Lo t pe Ter 3 O0 tof pe th and 4 feque heut MoS Jad pee The Vies DCM isthe most reliable liga wtb CL and easy dock management tech bh eo pha if foggy cs fat ing ad tology available The DCM diga sande ne DEM imr signal proceson phase infor aei mec oral dm 12 bi he i
138. om Compact Faih memory video ouput rouch and or NTSCIPAL ouput Composite and S Video NTSCIPAL video and RGB output Video fides wipes and soos Compact Fash FPGA configuration Touchacrenselected video source and The wouch semen is enabled by RS232 port video source and ici also pashbuton enabled Audio 10 BaseT and 100 Bae TX Elea support XC2VGOOOFFIS17 Platform FPGA support Univeral power supply module Veg Modder The follwing of winen initially im Velo available or ae with Vineell Video Demonarstion Board User Interface Push buton sam affects memory interface contest Drives data to and om the FPGA and ZBT RAM Outputs data to computer monitor apts for NTSC or PAL The module will work with any resolution given the right mount of memory the channel ver Son will support 1024 x768 the nel venion runs at 800 1600 Clack generation Generates four differ ent dock rates supporting various video funcions the audio codec at 25576MBHs G the DCM will work with the required ratio and 25 for Line eld decoder Aie in identifying fame and Geld parameters FC seria standard Loads ini parameters the FPGA the vdeo peripheral chips On chip line bulis Allowing algo tid piel to be proceed verically
139. ome of the same wireless madens We believe that OFDM enjoy 2 number of significant advannages however Bow it Worta OFDM is diferent fom other modulation schemes Int it should probably not be considered modulation scheme at all because it may be namine via AM FM QAM Quadrature Amplitude Modulation and so on OFDM is proper defined as a mathematically elegant rech forthe generation and demodulation of radio waves Although i origins dae back tothe second World Was i applic to wireless communione new 1n OFDM die shape is a aquare wave The tak of forming and modulation can be performed by a simple Inverse Discrete Fourier Transform DET which can be implemented very in Viteell FPGAs as an Inverse Fast Fourier Tandorm IFFT To decode the transmission receiver need oniy implement an FFT you can see in Figure 1 dhe of the subcarriers overlap By using an IFFT the spacing of he subcarriers i varied in such a way dat at the target of the received signal indicated as the signals ase ser This is known as hre quency orthogonality Thi contra with Direct Sequence CDMA which uses a Walsh code to achieve code orthogonal OFDM and Vitex Vineri FPGAs offer several architects al advances d x allow you cree implementations of OFDM systems Multipliers
140. opers tex and prototype the many new features of the Vite architecture The low boards come with reference designs documentation and optional Xilinx software bundles The 40 000 gate XC2V40 development board is available for 295 the onemilion gate XC2V1000 development board is avail for 695 For moreinformation see www insight electronice com schist by Hawes SoS ests c on Vinecll FPGAs ae the platform for developing video applications No other FPGA can provide the combination of 18x18 2 complement signed block mul pliers Digital Clock Managers DCM global dock multiples Bus 150 and DDR which all ccna pisce math and he kigh handed ned for managing and manip lating video data am To demonstrate the many video indy fea tuts and the video IP application module of he FPGA Baily weve demonstration board dar pre vides a Vineet FPGA interlaced 10 the eel video support functions a Lage fat ame memories Video inputs 4 NTSC or PAL CCIR 601656422 Video outputs 1 NTSC or PAL CCIR 6011656 4 22 oma Video viuis 1 RGB 24 bir forms connection Sper configuration devices a Virtexll Platform FPGA are many winging sibl propery fo te donation bed wth mon of na adora vid Thi band
141. ormance reduces Wah m de offers hamion canter workshops noiae and eliminates dhe need external qp range new family of online learning and couse matching resistors on the memory gal Pho FPGAs now filly consin the wate xo support customers who wish o lr als allows the signals be opti ley quem building blocks for quickly learn che detail of new mined for the memory module ex generation applications This new chs Xilinx produces The evaluation kit docs used in the design Of FPGAs requises anew approach ro noe have all the supporting components opment platforma In response Avnet and available on the develop standard components connected o Design Services has ened wo new design platform but it does feature seven he Platform FPGA an RS 232 port an basic Evaluation Kirand segment and single bit LEDs switches p pe pisa Ed the Vitex Development RS 232 port general purpose O 394 JTAG for configuration am fein Dis g testing The 15 232 portis convenient for eee emote contol you deum and diagnosis of prototype Confira LEDs Swiches de niin dewlap and get Memo Butons running on the development based application o marker ahead of bea mative part of the appli
142. ou get all he ational FPGA bence provides access Logi CORE and AlianeCORE products and reference FPGA technology for fst digs via the engine You teat vgn charges fan iy find the IP that you med at ime io market wo give you a com ires conipcenter Advanced func petitive in cores are available for IP evaluation and be purchase froen the IP Center Feld upgradable systems using or product n DERSE EEE eue no your IP with simubrion model x Vends and PDF or HTML fen Then PS sn fona and Yu I hp a Unique comninedeiven Fiker CORE Geneon Ges for performance The REALP PC X 64 66 Cores Xilinx T complete solutions offer the performance Power estimator tol Xpower foc very compliance and needed by sy low power DSP implementations DSP die mens Parameterizable PCUPCLX cons prototyping lace cor thar developmen time by on and Xilinx FCUPCL XPERTS com lined with a proven design and New DSP fatus added wo the timing mae Minx PCUPCLX de ol he debugging Our cachu Peformance Tabie listas sive FPGA pannenhip wih The the amazing performance you can achieve MathWorks enable you to create comple Yih
143. ough the PGND Maniking the around these pina i prece 1 addition solid ground plane is always helpful for the EMI performance es easy to power your Vine using the EL7564C DCIDC converter For data sheets application bi and addi informaron contr Elane online at or send an email ayer dlannec cm The EL7564C DC DC Converter Features Benefits sland lud Soa M tpi Nata aks Current Mode Control del qe Limiting pom p tmp Pen D at tlm Up peu herd aay pou aa Ky 4G Wireless Systems in Virtex ll Designers of he 4G iles systems tcu ae cote wh challenging product develop ment sues he urcatinty dh fundamenta system standards s s pac planetary emper nd so an Base here used nct you dose eio 5 tsk management making sue your designs can nde vith he hanging stondis by mes Mason x Aas opone nc pe Vines FPGAS an ideal platform for with ambiguous or evolving san dande Because of the inherent programmability and extremely high per formance spprosimately 0 6 Tera MAC of Viner devices you can en differ aivinerfce schemes and varians in and you can quickly he y tem performance In particulas Viel FPGAs make to develop hybrid syr such as multicanier or QAM modulated OF
144. overall sys tem cows and board layout comple Furthermore XCITE increases overall term reliably and anes designers im meeting their goals eive Technology With up to 10 million system gates he capacity in he indutery the Vien architeeure with Active Interconnect nology enables designes to achieve optimized pre dicable rowing delays in their designs thus mani mizing frontend design performance On chip suppor for high speed UO standard with up to 1 108 ser UO pins is included Advanced DSP applia tions such s echo canel ation forward etorcor maion and image com presion decompresion benefit the abun dance of embedded high speed 18 bit x 18 bit mul iple within the Virer FPGAs The Vinexll solution enables rapid development of the two most tech challenging application dia communications and digital signal procesing These system applications characterized by the need for high logic integration bat and complex routing of wide buses extensive pipeline and requirements for FIFO memory Design The Vinel solution is empowered by a mine desig tod chat sup he industry s ri times and most advanced design methodologies This combination delivers unequalled produc vy and the ites posible ime tomar ket of any logie solution available today The Xilinx innovative incremental des
145. ows top view packages FF and BF with banks in coun terclockwise order All the pinout dis Rare 2 Vite 1O fh pta FF and game provided in Chapter 4 of the Plafirm FPGA User Guide top views of the package For example Table 1 the masi mum number of pins per bank for the FGISG package The wer count includes the VREF VRP VRN and non configuration pins The defn tion of each pin sype in the Vineell Dita Sheet Module 4 ENTTNTTEET m m m m E Em 3 3 me 12 E CE 10 1 E 1 CET 3 3 1 Dek 3 1 Dak 3 1 w w 3 3 3 1 Jak ma Vs 10 w EAT 3 1 3 w w w w w vangan D D D i D Y 0 0 1 Y 7 E FOES Pot Pinout compatibility across different devices gives you major advantage when designing your application devices in a particular package 100 pinout compatible The 16 contr pins are always located on same package power and ground balls at che sme Package location Each programmable VO has the same ball name in
146. r Miele devdoped by Maan uer about 800 cells requies abour the Through our Conexant ening physical pace as the PowerPC and runs at we accom the higher 12 By next yea wl be runing peed available at over 150 ring ue ely M Being e Meise i fil ingen with PERG Wi rie ie Com Cook M stes utet iet means it can use peripheral modules Sedo to each 10 Gps or mama miri nw he pees mode qur proces and design technologies co ta fc you can use it in addition to the Sut to improve Vinet nis u an we inn ote il allow you to make of tht combination of the PowerPC and or more MicroBlase ences spread Pro ic dl using the same memory and Weinen to you a choice of pce Peripherals The are limi sors using both ord and core sll No oder company har this exible mali he same peripheral so you canens Plus our Mise iy combine in your deigna Slt core uns mona ata our compe Ca iei n co Our PowerPC hard coneis being developed Baad gration Proh jm with 1e gies you Wik tach sew of the Viner wellknown very high performance nly we more and more of We will embed thedacecomponca sree i
147. re ramping up product capabilities sais che high bandwidth high performance low power and low demands of he broadband marker By selecting programmable solution yeu can changing procol and shrinking product with more confidence because eld upgrades will be posible without replacing the device As designers take heir applications wo the generation and beyond a poses edle DSP enhanced solution can proveo be a significan advantage on the fox to high performance high deni and SOC Stem On a Chip luos For more information on the Xtreme DSP Initiative aching vidos oa demand p and niet 800 Mbps per channel by Sem Koontz bg aod oft The series provides new kow voltage signaling standard called HyperTamepor w formerly known as Lightening Data Transport or LDT which is an configuration arail able on all wer pins HyperTransport is a new high performance ineconnecr proposed by Advanced Micro Devices Ine for interfacing o procemors mem ry and LIO devices and source point to point interface Ina FPGA when an VO i con igure for HyperTransport the adjacent is automaticaly determined by sofware and configured with a very lowakew rou for he N side of the dier The HyperTransport bulkr
148. remental dein now for use desing of Vinee I FPGAS Xilinx deloop design solutions combine powerful technology with an to use interface help you achieve the best posible designs within your project schedule regardless of your experience level For mote information on any Xil produer visie com Misc Sere Stns The Alliance Series solutions contain powerful open systems implementation tools that engineered plug and play within your enining design ow This combination of advance aure deles high performance rene on che toughest Minx Foundation Series ISE Soto The ins Foundation Ig Sys Environmene ISE i ur nex generation complete ade environ f ment opido deliver the brefs of an HDL methodology Foundation ISE packed with technologies in addi on to Aliance dign ene tools helping you bring your product to market stet Xilinx Web based design solutions give you the ability engage in digital design activities online using Xilinx application serves or dawnload design and implementation sofware modules for in your own design environment These applications include gt warmam Web design har lovs you to olane your deis wing Klin COS Web series CPLD and CoolRunner series ISE The WebPACK ISE collection of free downloadable software modules including ABEL v73 VHDL and Verilog yas implementatio
149. rka Tam Durkin Managing Edie Virtexll Platform FPGA Solution spa ds penis dar peti diac and tn bly Cover Story Discontinuity Gate Th te in b d how you CIE Xiinx Contoled Impedance Technology E Wes aay mel pede matching mination rese SystemlO Technology Delivers High Speed Connediviy Wo Plain Ps mode ail sol tig pi View rom Top The Future of Platform FPGAs kt Ven famiy dodge New Products XtremeDSP Meets Demand for Performance and Flexibility ec DSP tn es roman wl conan tod gc ke oman webs wok vi Data Sheet Sorry itr Fes Mr Don bnt rds gece far Wed 15 2001 te FPGA Sen New d Bh Deomm Spon am ec Mon NU Dont the Goe a cod sto Tampa eta aeri lok Fant Shon Capa Prost a itt Doves Era Dep dl d Per The DCM Dg Cod lar gla DES or inan Vet Dg Pci Hi rr bli Mac he Dan hey icing Spd D nerd Pieces Tc idis etiatn Pamm FPO Aeg ns E aa FPGA De Voie 5 o Mit f ter Rie 48 Venet Sp Sym Plo Sida fe V E Selen AE hl oor T idt Betis ese Vend e
150. rket for newark equipment developers The SiberBridge che dal features of the Vinexll FPGA architecture DCM Digital Clock Manager eae the spe dock Dedicated block SeleetRAM for enhanced performance in saving context reda DDR Double Data Rate rsen in blocks to burst dats ino the SbeCAM device reference design the SierBridge hata ow gate count Device Overview Content Addressable 2 Memory device designad to quickly determine whether paniodar value exists in ts memory and ifs at which locaton The SbcCAM device uses a terna ty sach operator dut takes hee 0 1 and dont cane Data can of sible width Daa is presented mode device on its search port several dock cele a raul in provided ls search reni This reali the address of the bese match wen he input dara and dara Within the SiberCAM device m The SiberCAM device is either config ured or loaded with ternary data by forming maintenance operations mazimise performance these main tenance operations can be done at the same time a search operations by using a separate 36 bit maintenance port Both the search data and search resule ports remain available permitting interrupted address lookups For applications that not requite mainte
151. rovide bod aane and phase ding with dytam ie phase shift conta vo compensate for voltage and temper drif De Shew Synchronous depend on deck dition achieve high perform ance and ve avoid violating halime requirements The Xilinx clock bale and so on ensure lowakew dock signal dinibuion both within the Vix device wing the clock neo and eneralyo0 lel The welkbufiered global dock disribution ne wok dock shew regardless of leading difkenences The Viner DCM provides fly digi on chip dedew wih em propagation delay low cock skeve beeen clock signals died throughout the device and advanced dock domain con tao The dese circuitry has an inp quency range of 24 MH o 420 MHz and an frequency ange of 1 5 Ms to A0 MH Thede dew circuitry can tolerate upto Los few le to By monitoring a sample of the output duck or de deskew circuit lok Figure 2 showa the waves of the deskew vith an input dock quency of The deskew can also act as a clock tino By driving the CLKD or out chip and then back in again the can be board ler clock serving multiple Frequency Synthesis To avoid high frequency clock dination printed cic boards PCI lack multiplication and division are squid Frequency seis ia the
152. s ng dis rats that the dat lid window o dil Reliable require thatthe log analysers combined setup and hold window mu be small an the darsi window of the sigh ie i quiring The 16760A has a combined setup and tiene alow as 500 ps manch ing the dae valid window ol very high speed buses Aglenis proprietary eye Rader technology the and hold window on each logic analyzer channel with 10 resolution This eliminates need foc ianua and ensures the high et confidence in accurate measure at speede to 125 Automaton ot only relieves you of the burden of mak ing these adjustments manualy bur alao you opimis logje analyt ex so you dont wate time acquiring fly dat In aon at the system temperature voltage changes or you move oa difer ent you can use eye finder to quickly optimize logje analyser and have conf dence in the da Single Ended Signals timet you may it easier to single ended signals so you can ite ro legacy ASICs or ther The Vineell FPGAs allow you to create your design for differential signaling and then set the pint single ended san dard When verifienion is needed the FPGA cam be reconfigured to the LVDS VO standin with the same pin the development software vil automatically grab an adjacent Pin forthe N channel of the ferential
153. same interconnect scheme and same access to the global routing matrix Timing models are shared greatly improving the predictability of he performance of high speed designs There a total of 16 global clock lines with eight available por quadrant In addition 24 vertical horizontal long lines per row or column as well as massive secondary and local routing resources provide last interconnect Vita uffred interconnects are relalvely unaffected by net fanout and tho Interconnect layout is designed to minimize crosstalk Horizontal and vertical routing resources for each row or column include 24 ong lines bidirectional wires that distribute signals across the device 120 hex lines routes signals to every third or sth block away 40 double lines routes signals to every first or second block away 16 direct connect lines routes signals to neighboring blocks total in all four directions Boundary Scan Boundary scan instructions and associated data registers support standard methodology for accessing and configuring devices that complies with IEEE standards 1149 1 1993 1532 A system mode and a test mode are implemented In system mode a VirtexII device performs its intended mission even while executing non test boundary scan instructions In test mode boundary scan test instructions control he lO pins for testing purposes The ost Access supports BYPASS PRELOAD SAM
154. sier o correct HDL Simulatie HDL simulation is a solid verification method for individual design modules Xilinx integrates the flexibility of HDL simulation ineo the ISE implementation tools so cach module can be verified at disent stages of design work During HDL creation To verify logie functionality synthesis To check design func tionality before going to Place and Route Aher Place and Route Using back annotated device path delays The Xilinx ISE Foundation software includes venion of the wellknown mily of HDL simulators offered by Mode 8 Technologies gs you the spent and needed fr high density HDL simulation The sofware alo sup Pores the various HDL simulators fed by les EDA vae supplies Genitation For HDL simulation you must create test for each module that rapid y espanda as your designs become larger particularly when HDL simulation is ed vo verify device To automate this proces Xilinx now offers the HDL Beacher sofi wars part of the ISE software package shown in Figure 1 With the HDL Bencher software you can quiddy and easily a testbench for each design module in the design proce With the HDL Bender sofware you dont have o spend ime generating test sector or learning a script level timing verification for FPGAs for sev end years Xilinx
155. ss those technology omo the engines provided by our parten such Synopsys and Exemplar M your design is running below your per formance requirements try running an implementation through XST You get beter speed and eliminate sev eral design iterations Condesion The Vinecll Platform FPGA family will continue va increase in density ance and features andthe Xilinx ISE sofi ware will connue vo make your design productive combining the latest sofware technologies from Xilinx and our partners you get the fastest and most pro ductive development platform ever and it Jost keepa genting benie For mare ile TSE fier qot role coll prodeat ndigpote pie Design Tone Verification for FPGA Design m Platform The Xilinx software offers a wide range of design verification options by Le Hosen owas ot Maat Hay n m designs can be very large and complex A common srategy to complete these large density degna i to partition them into modules To verify these indi vidual modules and then verify the final design you need the robust verification contained in he new ISE sofware fom Xilinx Verification The Xilinx ISE allow you veri By your designs each sage of development These you identify any potential problems early in your design Where they ane ea
156. store your design at any point allowing you vo easily differen design ideas without losing any of your work The Navigatoe provides a starus window feedback thar is Web enabled so eror mesages can be passed tothe Xilinx Solution Center where solutions kept up to date This gives you the mos disc and accurate answers eliminat ing the time spent browsing help ies and documentation to find the correer answer Modular Design By saning with foorplaning you can new leverage a new technology Xilinx has pioneered 1o make high density design even faster Modular Design Xilinx Modular Design is a productivity that works in addition to d design sofware With Modular Design you can all Xilinx implementation tools independently and completely on each module of your design enabling design ears to work in parallel to com plete cheir individual module Modular Design delivers speed and productivity in high density designe by offering a eve vam design environ mene that allows paralel implementation of partitioned design modules But more important Modular Design wets ach module as a separate design by completing and then locking down imple mentation results on a module by module bass change to one module docs not affect the imple mention or timing of completed modules With Modular Design high density designs ied much faster than ina tradi tiona
157. t very high speeds the capacitive loading highly capacitive wil introduce fle in addition reducing dew rata and changing ning in your cic The probes forthe 16760A lave only 15 pF of probes capacitance including the con necu These high denity connect ground pins every pit of signal pins providing excellent channel isolation at high speeds thus enabling high dl signal capu ferential signals with am input as low 200 mV P P t spende up to 125 Gbps This module operates up to 800 Mbps state analy sis and 125 Gbps in half channel mode I has a memory depth of 64 MB and a 500 ps setup and hold time capably Each module contains 34 channels or 17 channel when ing tine Up to 170 channel peras on a tme base and The 16700 series logie analyzers provide many tole vo in analyzing the dita once it is acquted For example che Agilent B G OB Data Communications ool Set adds many protocol analysis capa Te provides a view ofthe data and powerful sine colton features to asst you in finding complex problems Low Capacitance Probes The probes for dine LVDS analysis mist be designed into your system Mating connec ae placed on the boad and the logic m Automatic Setup and Hold Time Adjustment Another by ever increa
158. termination some of the specs of HyperTansport that contribute to a reliable interface The VO specications proposed by AMD cal for low voltage diferensial signal ing similar to IEEE LVDS specifier tions AMD has nor proposed a bbe tional implementation lor HiperTanpon bur such implementation is not precluded because it designed o be scalable at both bur wilh and quency Using Hyperonprt Vitex Devices Implementing HpeTanqurt in device is very snighelorward Simply instante the HyperTransport UO bufer in HDL and the sar does the ret Vinter devices have new improved for HyperTransport and LVDS When one of these buffers is used the soft wae wil statically route the N channel an adjacent Either the N channel or the P channad can be locked and the sofi Table 1 provide the DC been tested However Eye diagram characteristics of the Vinerll shown in Figure 2 demonstrates the Vineell HyperTransport UO which HyperTransport functioning ar 840 provides on chip source termina DDR clock rae 420 Wan FE tion only receiver ermina This tet eerie one interface ie cry fr sed by 152 LER pring Pes pe Tek an Mane 10 rong MES Tha meen er hse
159. th 0 12 um high Fourth generation segmented routing structur speed transistors Predictable fast routing delay independent ot 1 5 V core power supply dedicated 33 V fanout auxiliary and VECO UO power supplies Seloct O Utra m Technology IEEE 1149 1 compatible boundary scan loge support Up to 1 108 user Os Flp Chip and Wire Bond Ball Grid BGA 19 single ended standards and sx diferential packages in three standard fine pitches 0 80mm standards 00mm and 1 27mm Programmable sink current 2 mA to 24 mA per 100 factory tested o Ss ne A nam Nir EIECTUS alee rater or icr re WO TEE 15V Fiold Programmablo G Arrays FC XILINX Table 1 Virtex ll Fleld Programmable Gate Array Family Members 1 CLB 4 slices Max 128 bits n os system Muttipior Devico SY ae Pads sates Array locks RAM 0 Row x Col Stes Distributed Blocks RAM Kbits ere 2 g 2 3 8 su 1 g 20K 156 a a 3072 5 2 we Xcavig 5120 160 x s xcavisoo 15 exa 78 2 sw s
160. the maximum possi ble numberof user in wie bond and fip chip packages respectively Table 6 shows the num ber ol available user tor all device package combinations CS denotes wire bond chip scale ball rid array BGA 0 80 mm pitch FG denotes wire bond fine pitch BGA 1 00 mm pitch FF denotes flip chip fine pitch BGA 1 00 mm pitch BG denotes standard BGA 1 27 mm pitch BF denotes flip chip BGA 1 27 mm pitch The number of Os per package include all user Os except the 15 control pins CCLK DONE Mt M2 PROG PWRDWN TCK TDI TDO TMS HSWAP_EN DXN DXP AND RSVD and Table 4 Wire Bond Packages Information Package 6256 FG676 86575 o80 109 100 127 127 Se mm 1x2 17x37 23 23 27 27 31 31 35 35 Vos 56 Table 5 Fllp Chip Packages Information Package FFISI7 ach mm 100 100 100 127 Size mm 35 35 40x40 40 40 TOs G2 1308 15V Field Programmable Gate Arrays Table 6 Device Package Combinations and Maximum Number of Available Os Advance Information Available TOs XG2V KEV XXV XCIV XCV XGAV XGAV
161. tic ot custom logie elements Ty meet the demands of state of the art designers with cuing edge design tools Sandal che necessary implementation tech aided vo design advanced pro FPGA based scr Ode of the m t importan considerations gie mien fe er die and comple of FPCA pet sytem grow providing a pre engi and high density contigu becomes even more critical She pat of tee Platforms FPGA Initiative lin Had developed the System ACE WG fia manage Thir solution pro pryceme configuration im Sorge densi and solli in a drop in ready to irmplement module in FPGA Usage Uns znd programmable loi devices a gue logie ing Various system functions together and acting penc ge ped iene loge GA une weal nid one so dois per Now owe de o the integration of expansion of perfomance and sion FPGAs becoming he core of amen perf ing a vey of epi taal and gee FPGAs a atthe rc of spem developo mer de Xilinx FPGA Ine spe died high performance poles Soot and inte ite the FPGA Be The of FPGAs vo in a wodd of pel compen podus devil cps the we of FPGAs for ay
162. tion Launches New Era of High Performance System Design for an overview of the breakthrough technologies including System XCITE IP Immenion Digital Clock Managers XtemeDSP and new design sofware There are numerous other ails in this Special Edition dat describe these technologies in depth as well as examples of practical applications For those who are looking for Jast the check out the Vinx Advance Brief Data Sheet and Vintec I Product Guide Not only is this edition of Journal dedicated to one product line it is also the fise in which 1 Tom Durkin have published as Managing Editor 1 join Carlit Collins Editor in Chil in continuing o bring you the best and most useful information in the programmable logic industry We are dedicated to keeping you informed of not only what field programmable logic devices can do but abo wha people are doing wich our products In coming issues we will report the hunt for the last subatomic particle the Higgs boson at the Fermi National Accelerator Laboratory and we will investigate evolutionary algorithms that make Xilinx FPGAS capable of redesigning Enen in times of economic uncertainty Wim Roelandts says it bese ns just keepa gening benter and the looks very bright We hope you enjoy this Vine Special Edition of the Xel Journal and we invite your commens and suggestions 7229 Lo
163. uch at control signals locks and data buses Soft IP is pre engineered to work with these defined buses se the designer juse need to con nec these fed IP objects to the buses For the uer delied section of the chip the design has been made easier because ie bound ary conditions are known To take advantage of these fae CPU platform based FPGAs designers will look for new applications and Since the com of implementation will be in everyones reach we should see esr of the guageabop mentality and new ouf he bot thinking Enabling Innovation Together Mentor Graphies we enjoy collaborat ing with partner thar locks at the big piene and asks How do 1 change the The Xilinx vision in progr ble logic will change how we do dig design Mentor has recognized this and is omitted tothe FPGA market We con tinue to develop point tools and solutions solve the tough design problems Mentor realises that dedicated FPGA flows ested and integrated tightly with the vendor sofware will provide the eh nology that will Enable Innovation for the of die electronic industry The only IP Center iving into Center IP Center is only web portal that brings together cores reference designs design reuse tools and design sences Everything the system designer cul wish far engine Get to the cores design tools you want fast
164. ur of pipelining As wih all Logi CORE implementations the generated design is fully ested and verified These examples lustrate both the complex and ui that underlie designa generat via the CORE Generator I pro vides full support foc the wealth of architec tural features of the Vinx and provides you with the ability w quickly ere solutions with building blocks By simply invoking the CORE Generator and entering the required config uration an optimized and verified design is created using SmanlP technology The combination of generation technology and the new Vier device anre guantes you and piles timer mater m Virtex ll Building Blocks Each embedded block SdeaRAM is 18Kb of True Dusl Port RAM with rwo filly independent ace por in Figure 4 Each port behaves synchronously relative chock input Thee eo separate dwa ut bumen one for accening dats and the aber for diced pariy Table 1 the aspect ratio of the pots available in de 18 Block SleaRAM primitives For applicions that do require parity information the wo busses can be combined yield lager memory wide wont PARTY US 1 wan 1 um Wk ww ums 3 104 ADS MH w 3 52 AS MAGIS
165. versions for North America South America Europe and Asia see Figure 3 Also Xilinx FPGA deiqn ers with Empower embedded procesor an sore the FPGA configuration and the processor microcode in the same source System ACE technology handles the initialization of both the FPGA cells and the delivery of microprocesor initial ain software In addition to configura tion dara designers ean relase infor mation with the bisteama including notes revision history user guides FAQs or any other supporting fler The microprocessor interface belpa to fully the ACE Fah capacity for purpose other than biutseam storage such at generic scratchpad memory System ACE software is sally el wit ening Xilinx programming saft A standard fle management allow for dag and drop fle manipulation ACE Fish modules fom any Window environment Unix venions wil akso be available in 2001 Deigpess can ACE modules sup id by Xilinx 128 Mb or 256 Mb arany sandari Compac Fiash modules avilable a vay of hin parey supplies Microdrives may ako be wed The ACE Cones wil be im 14in ondion FPGAs are becoming the core logic of modern decwoni stems ruling in rowing demand pre engineered Dele ood robust configuration solutions System ACE technology frees systema fom reinventing an FPGA configuration
166. y uer IO of one package can be easily located in the second one IF digitally controlled imped ance technology is used in Bank 4 you have the choice betwee f Select MAP parallel configuration is not used the alternative ALT VRP and ALT VRN pins can be used as reference resistors for Bank 4 and the are fully pinout compatible 1E he regular VRP and VRN pins in Bank 4 are used however then these two Pins are comparible In the pinout diagrams of Figure 3 dedi pins squares and programmable user circles these pins match For ench location The extreme of Vill device pinouts eariy PCB protoryping The large number of devices as many at ght tig in one footprint offers you a choice of variable configurations for the same boat while reducing the cst of the overall Vitel solution Bank 2 Barka Figure 3 Pinout Compatibility Diagram Bank 1 244588 My CEN FF896 FF1152 Barko 718 92 22922872890 181202222324252872823031323334 cs 5 susvoour 9 cows DLDUAT M 8 5 H N i Y Bank Bank atout aa ag Ed Barks EJ Corresponding Pos oo
167. ystem managers or designers can easily remove an ACE Flash memory module See Figure 2 and either reprogram ic on a desktop or replace with another module contining the updated bistseam files Whether for a protoyping board n a lab or an insealled system in the ied manually reconfigur Pore pil Sem ACE ree ing an FPGA based system using Synem ACE technology requires ile effort ACE Flash memory can ilio be pro grammed and read in system facilitating updates and revisions This capabiliey eliminates many requirement for to be manually updated In system pro amming can be accomplished by down load cable or through a network reconfiguration of System ACE memory eliminates the need for direct iere Designers can remotely update debug by transmining a new over nerwork such Intenet or witless WAN In addition the ability o sore multiple bitsereams and have the microprocessor activate any bit stream at any time allows system adminis maintain direct access ro all pre vious venions of system configuration The ACE Flash fle structure simplifies he storage and management of muliple bit scams This ipl empowers designers to single ACE lah card to run BIST Built In Self Ter patterns PCI applications or to store multiple variations on single design for example

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