M3A-HS60 User`s Manual
Contents
1. CHANGE 236 D 0 31 SVDDO SVDDQO H5 H6 svooo P 1 T 1 svopao avec 3vcc R23 00 ag 236 0 25 SA 1 15 R26 MAO DUMPING REGISTER for SDRAM SDRAM i SZ H 32bit MODE us d 50131 0 RAG 307 1 16 D 8889999 m 95709080 DE AW Hs 5 SA14 21 53 3031 504 MV 1811 46 SA1 SATS 0915 5030 503 ERE RE o LA SAZ apo 50 5029 502 LW 02 12 182 SA12 0913 48 025 DT Mi Di 145 Lian A A AN pQ12 4 027 07 e 184 42 34 bon 45 5026 AW 40 SAG SAJ A Dato SD25 1A6 1B6 20 SAT Das 24 NO 1A7 187 32 AS E AT Das H 3022 JAS 187 38 ma avec AZ 098 023 RAZ Hd 188 E lt DOS 022 5015 1 16 015 1A10 1810 H X SAS 29 10 5021 5014 AWN Dit aa A Das Li S020 AW 6 J HS 5013 14 013 2 1 281 5 a N 5019 5012 4 ANM 1 012 uu 2 2 282 dri A1 092 2 7 Evi ET SAT2. ES ee ix m COOSA Eg ee 8 e 2 E mu E n e n 2 949 2 845 E EE soso Ile UR ur cr JE ee s k um eseo 5 mu ge 29 e ES e e e i muj LIL ma iniumini EB g e ee gum jm ee a m MK P E n e Ho 1 5 zm e 2020202020066 e nunnnoc 5 000000606 ee 000000000 mi 2 38 900 Figure3 3 1 Outline Dimensions of 60 Rev
3. Figure3 1 1 560 Connector Assignment Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 3 2 Operational Specifications 3 3 1 1 H UDI Connector J1 3 1 1 H UDI Connector J1 The 560 includes an H UDI J1 connector for connection to the E10A USB emulator Figure3 1 2 shows a pin arrangement of the H UDI connector Q Board edge Top view of the Component side Board edge Side view Figure3 1 2 Pin Arrangements of the H UDI Connector Table3 1 1 lists pin assignments of H UDI connector Table3 1 1 Pin Assignments of H UDI Connector J1 Pin Signal Name Pin Signal Name 1 AUDCK PEO 19 TMS 2 GND 20 GND 3 AUDATAO PE6 21 TRST 4 GND 22 GND 5 1 23 TDI 6 GND 24 GND 7 AUDATA2 PE4 25 8 GND 26 9 AUDATA3 PE3 27 ASEBRKAK ASEBRK 10 28 GND 11 AUDSYNG PA16 29 3 3V 12_ GND 30 _ GND 13 NC 31 RES 14 GND 32 GND 15 NC 33 GND 16 GND 34 GND 17 TOK 35 NC 18 GND 36 GND RENESAS REJ11J0002 0100Z 3 3 1 2 Serial Port Connector J2 Op
4. 3 1 3 1 M3A HS60 Connectors en nest reris nns 3 2 3 1 1 H UDI Connector JT seinge agna ar a na er 3 3 9 1 2 Port Connector Ur EEE EEE 3 4 3 1 3 External Power Supply Connectors J3 and 45 4 3 5 3 1 4 Power Supply Connector U4 ennt enne 3 6 3 1 9 User I O Connectors 46 48 iere cid tte tese ieee 3 7 3 1 6 Extension Connectors 9 13 etre sitne tnnt ennt nennen nnns 3 9 3 2 Outline of Switches and 3 13 3 2 1 Power Supply Select Jumpers JP1 0 02 3 14 3 2 2 Switch and LED F nctions 3 15 3 3 Outline Dimensions 560 nian 3 17 coq OP A 1 M3A HS60 Schematics Rev 1 00 June 1 2005 RENESAS i REJ11J0002 0100Z Chapter1 Overview 1 Overview 1 1 Overview 1 1 Overview The M3A HS60 is the CPU board designed for users to evaluate the function
5. gt tOEH M gt tCS tWP tas iCH Mo uS J ta OE 4 34 105 WDHi 4 105 tWDH1 ta AD gt tRDH1 gt tWDD1 tWDD1 IDH ta CE1 tRDS1 gt tDF OE 015 00 DATA DATA Rev 1 00 June 1 2005 REJ11J0002 0100Z Figure2 3 2 Flash Memory Read and Write Access Timing 2 5 TENESAS 2 Functional Overview 2 3 3 External SDRAM 2 3 3 External SDRAM The 60 includes two pcs of 16 Mbyte SDRAM for an external SDRAM as standard equipment The SH7206 s internal bus state controller can be used to control the SDRAM Note that the SDRAM can be switched between 32 bit bus access and 16 bit bus access For 16 bit bus access only one pc of 16 Mbyte SDRAM can be used Table2 3 3 lists SDRAM specifications used in M3A HS60 Figure2 3 3 shows a block diagram of SDRAM Table2 3 3 SDRAM Specifications Used M3A HS60 Specification Content Part number EDS1216AATA 75E Configuration 16 Mbytes 16 bit bus width x 2pcs Capacity 32 Mbytes Access time 5 4ns CAS latency 2 At 66 2 bus clock Refresh interval 4 096
6. 7 8 Signal Name Pin Signal Name 1 D16 IRQ0 POE4 AUDATA0 PD16 1 5 5 2 D17 IRQ1 POE5 AUDATA1 PD17 2 AN6 DAO PF6 3 D18 IRQ2 POE6 AUDATA2 PD18 3 AN7 DA1 PF7 Rev 1 00 June 1 2005 RENESAS REJ11J0002 0100Z 3 8 3 3 1 6 Extension Connectors J9 J13 Operational Specifications 3 1 5 User I O Connectors J6 J8 The M3A HS60 has the trough hole for extension bus connectors to which the I O pins of the SH7206 are connected MIL Standard connectors can be mounted to J9 J13 and it is available for the connection to extension boards or monitoring the SH7206 bus signals The bus signals of SH7206 are connected with J10 J12 of the terminal connector via 9 J13 49 J13 are connected to the terminal connector J10 J12 J9 J13 49 and J13 are mounted for the monitoring signals by the measuring instrument When the extension boards are made J10 and J12 of the terminal connector are recommended to be used to prevent the waveform distortion because of the reflection of the signal Figure3 1 7 shows a pin assignment of extension bus connector Board edge 40 39 19 20 20 19 oo J11 20 12 19 40 39 49 2 1 Board edge J10 Top view of the Solder side Figure3 1 7 Pin Assignment of Extension Connectors J9 J13 Rev 1 00 June 1 2005 REJ11J0002 0100Z RENE
7. estne nnns nnne enne nnns 1 3 pie External FM EE 1 4 1 5 M3A HS60 Block 1 1 6 560 1 6 1 7 1560 Memory Mapping fep 1 8 1 8 Absolute Maximum nnne 1 9 1 9 Recommended Operating Conditions 1 9 Chapter2 Functional 2 1 2 1 uentrem 2 2 2 2 EE 2 3 eko 7 e LU Du MI nin i 2 3 2 3 NE 2 4 2 3 1 SH7206 s Internal s R 2 4 2 3 2 Flash Memory M5M29KT331AVP included as standard 2 4 2 3 9 External SDRAM 2 6 2 4 Serial Port Interface teta 2 9 2 5 VO 2 10 Puce isse Ael 2 12 2 7 Glock 2 13 2 9 Reset Module Per HER EE Redes extre t E Ad KAD pected 2 14 2 ONNIGIKUDISWIIONES mio ona KEC ETO Antal 2 14 2 10 ETOA USB Intetface tren 2 15 Chapter3 Operational Specifications
8. A D i 21 A DQ1 Do 25 SDRAM sz 489 n 20E4 189 RAS PROTEZA ____ avec 169 we nc 0 R36 00 DOMLU 26 WE1 DQMLU AM 39 23 6 _WEO _DQMLL RST 1 3 Decoupling Caps CP25 2 CKIOL 0 1yF us 2226 SVDDQO SVDDQ1 SVDDO SVDD1 2000009 777 2999988 EDS1216AA CP27 CP28 OP29 CP31 CP32 CP33 CP34 OtpF T 0 1HF 0 1HF 1 4 4 DRAWN CHECKED DESIGNED APPROVED SDRAM 4 7 SCALE Ver 1 0 rare 05 06 01 DK30477 A 1 2 3 a 5 1 2 3 4 5 H UDI INTERFACE ANCO avcc avec SERIAL CONNECTOR COM us R38 lt R39 1 UART connector RA10 E v mount hole GND C1 avcc
9. Pin Signal Name Pin Signal Name 1 NC 2 NC 3 RD 4 D15 TIOC4DS PD15 5 D14 TIOC4CS PD14 6 D13 TIOC4BS PD13 7 D12 TIOC4AS PD12 8 D11 TIOC3DS PD11 9 D10 TIOC3CS PD10 10 D9 TIOC3BS PD9 11 D8 TIOC3AS PD8 12 D7 13 pe 14 D5 15 pa 16 D3 17 pe 18 D1 19 DO 20 GND Table3 1 11 Pin Assignments of Extension Connector J12 Pin Signal Name Pin Signal Name 1 5V 2 5V 3 WAIT DACK2 PA17 4 D31 TIOC3AS ADTRG PD31 5 D30 TIOC3CS IRQOUT PD30 6 D29 CS3 TIOC3BS PD29 7 D28 CS2 TIOC3DS PD28 8 D27 DACKi TIOC4AS PD27 9 D26 DACKO TIOC4BS PD26 10 D25 DREQ1 TIOC4CS PD25 11 D24 DREQO TIOC4DS PD24 12 D23 IRQ7 AUDSYNC PD23 13 D22 IRQ6 TICS5US AUDCK PD22 14 D21 IRQ5 TIC5VS PD21 15 D20 IRQ4 TIC5WS PD20 16 D19 IRQ3 POE7 AUDATA3 PD19 17 D18 IRQ2 POE6 AUDATA2 PD18 18 D17 IRQ1 POE5 AUDATA1 PD17 19 D16 IRQO POE44 AUDATAO PD16 20 GND 21 TENDO TIOCOB PE1 22 DREQ1 TIOCOC PE2 23 RD 24 D15 TIOC4DS PD15 25 D14 TIOC4CS PD14 26 D13 TIOC4BS PD13 27 D12 TIOC4AS PD12 28 D11 TIOC3DS PD11 29 D10 TIOC3CS PD10 30 D9 TIOC3BS PD9 31 D8 TIOC3AS PD8 32 D7 De 34 05 35 pa 36 D3 37 pe 38 D1 39 00 40 GND Rev 1 00 June 1 2005 TENESAS REJ11J0002 0100Z 3 11 3 Operational Specifications 3 1 5 User I O Connectors J6 J8 Table3 1 12 Pin Assignment of Extension connector J11 Pin Signal Name Pin Signal Name 1 IRQ1 POE14 SDA PB3 2 IRQO POEOA SCL PB2 3 CS3 TCLKB PA7 4 RD_
10. B3SN 3012 Decoupling Caps m 1 RESET td 34ms 0 34 Cd pF usec vid 4 4 SWITCH Vs 2 5V 1 25 Ra Rb Rb VOUT VREF 1 Rb Ra IADJ Rb 777 All regulator TABs are VOUT User Port 5V 1 25V STEP DOWN REGULATOR R53 R54 R55 R56 avec vec 3300 3300 3300 3300 1 2VCC IN LED2 LEDS 1804 LEDS R60 GREEN GREEN 1 GREEN GREEN u12 M 4704 1 2V EXTERNAL PE1 1 a PAIS T T Swe 12 t t 1 2 6 TENDO TIOCOB PE1 PEZ PATO BREQ TENDO PINT2 PA18 2 6 PVIN2 SwP2 2 6 DREQ1 TIOCOC PE2 PES 24 BACK TEND1 PINT3 PA19 2 6 ARIS ES 4 2vec EX 2 6 SCK2 TIOC3A PE8 4 Lo PADS DREQ3 PINT6 PA24 2 6 RUN SS SWN1 R61 15 26 TXDZ TIOC3C PE10 25 2 6 SVIN SWN2 28ko 65 4104 SYNCIMODE a tour tr VFB ceo ADDPAZEIDSA ponto R62 PGOOD T Ww T avec 150KQ 4 49 9KQ Mode AW ITH 777 1 0N SDRAM SZ L 16bit access cr 58 sonp 4 Switch l OFF SDRAM SZ 32bit access siloj er 55 2 0 MD_CLK2 L A 1 2VCC 12 IN 1 2VCC 2 OFF MD CLK2 H LTC1875 3 0N RESERVED2 L 3 0FF RESERVED2 T EE E d 4 0N RESERVED1 L 7 3 PA 4 OFF RESERVED1 WP EA 5 0N FLASH WRITE PROTECT SDRAM SZ 24 5 OFF FLASH UNLOCK MD_CLK2 2 1 2 Fixed 1 2V RSVD2 2 RSVD1 5 2 3 External 1 2
11. Functional Overview 2 3 2 Flash Memory M5M29KT331AVP included as standard equipment Table2 3 2 Examples for Bus State Controller Settings Flash Memory Write Read User Area Applicable Device Bus State Controller Settings CSO M5M29KT331 AVP CS0 Space Bus Control Register CSOBCR Specify idle state in write to read and write to write intervals Specify data bus CSO Space Wait Control Register CSOWCR Address 50 assert gt RD WEn assert delay cycle SW 1 0 B 01 1 5 cycles Specify access wait cycles WR 3 0 B 0110 5 cycles RD WEn negate gt Address CSO negate delay cycle HW 1 0 01 1 5 cycles Initial value H 36DB 0600 when MD2 and MDO L Recommended set value H 1000 0400 IWW 2 0 B 001 1 idle cycles inserted BSZ 1 0 B 10 16 bit bus width Initial value H 0000 0500 Recommended set value H 0000 1 lt Write and Read Timing gt Write1 Write2 Read1 Th Ti Twi Tw4 Tw5 T2 Tf Tawi Th Ti Twi Tw2 Tw3 Tw4 Tw5 2 Tf Tawi Th 1 Twi Tw2 Tw4 Tw5 T2 Tf CKIO Li Li Li a a IN la 1 1 tAD1 tADi ADI d j ARC A21 A1 lam gt 01 ICSD1 ICSD1 50 tCSD1 12501 50 gt 80 tRSD RD
12. NN EXTAL CKIO NVV Not mounted VW EXCLK Extension connector XTAL io CY2305SC 1H Cypress Ceramic Resonator AV gt CLKIH SDRAM upper bytes gt CLKIL SDRAM lower bytes i Not mounted T CSTCE G16M67 Murata 1 To mount ceramic resonator remove the resistor 18 2 To mount a clock buffer remove the resistor 14 Figure2 7 1 Block Diagram of Clock Module Rev 1 00 June 1 2005 2 13 TENESAS REJ11J0002 0100Z 2 2 8 Reset Module Functional Overview 2 8 Reset Module This module controls the reset signals connected to both the SH7206 and Flash memory mounted in the M3A HS60 Figure2 8 1 shows a block diagram of the reset module in 560 3 3V a Reset IC Ra 10KW M51957BFP Output Input Rb lt 10KW Delay capacitance Open collector output 2 9 Interrupt Switches 3 3V ResetlC output delay time td 0 34 x Cd pF usec 34ms ResetlC output detection voltage Vs 1 25 x aa 2 5V H UDI connector O RESA Flash memory RP Extension connector RESET SH7206 RES E 0 1uF Reset switch d 2 SW 2 Figure2 8 1 Block Diagram of Reset Module As for the M3A HS60 both the SH7206 s NMI interrupt pin and MRES pin have a push switch connected MRES switch can be used for controlling manual reset for SH7206 When manual reset is done
13. User s Manual LENESAS RenesasTechnology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
14. g 6 AN7 AN7 DA1 PF7 58 PLLVSS Decoupling Caps 8 92 gs 12NCC 5 2 2 IRQO PD16 5 DADA D D D A D D D D a 88888383 Kol IRGOIPD IS TROTPDIT 2 99999999 8 22299999 e e gt o 2 46 IRQZ PD18 Roe a loj IRGAPDIO 3 PD19 CP4 5 CP10 11 CP12 Heel IRQUPD20 1804 2020 22 22nF 22nF 22nF 22nF 22nF 225 225 146 IROS PD21 BEN 4 6 IRQ6 PD22 806022 E li E als 146 PD29 bs POR Decoupling Caps aveca Tlocacs 46 TIOC4BS 195025 L 46 TIOC4AS CP13 CP14 CP15 CP16 CP17 CP18 CP19 CP20 T 22nF 22nF 225 225 225 225 225 225 47 a 2 DRAWN CHECKED DESIGNED APPROVED CPU SH7206 277 e SCALE Ver 1 0 05 06 01 3 2 4 6 D 0 31 lt gt 2 4 6 0 25 gt DQ15 A 1 DQ14 DQ13 DQ12 DQ11 DQ10 009 OS gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt 55 5 43424 FLASH CSC CHANNEL 0 16bit access 4MB M5M2 9KT331AVP IN 2 5 6 RESET 2 6 _CSO 2 4 6 _WEO _DQMLL Decoupling Caps 5 FLASH WPE gt EVDD M5M29KT331AVP RENESAS SOLUTIONS CORPORATION HS 60 NECS cusck DEsTeNEOI approve FLASH MEMORY DK30477 A DATE 05 06 01 o Em e 0 CHANGE
15. 022 13 1 IRQSIPD21 D21 14 IRQ4 PD20 020 1 t IRQ3IPD19 219 16 TROZPDIS DIS 1 MRES SWITCH RAPD DiT 18 CIRCUIT 1 TRQO PD16 016 19 1 0 avcc 3 1 TENDU TIOCOB PET 1 2 DREQTITIOCOCIPEZ 22 3 RD 23 015 4 DIS 4 R78 D14 t 014 10KQ DI3 6 013 26 012 012 D11 8 DIT 28 R79 1000 R80 on MRES 010 9 010 WW E pIi 5 i D8 y 08 1 5 D7 T 1 D7 _ 05 137 De 33 swe MRES TE 05 14 05 4 B38N 3012 o SWITCH D4 1 1 D4 0346 Da 26 02 1 02 Di T 18 Di 38 DO 19 DO 9 20 40 777 777 XG1C2031 645403 i 25 TENDO TIOCOB PE1 25 1 2 RENESAS SOLUTIONS CORPORATION M3A HS60 DRAWN CHECKED DESIGNED APPROVED BUS CONNECTORS PUSH SW E Sj SCALE Ver 1 0 05 06 01 DK30477 A 1 2 3 a 5 TEST PIN MOUNT HOLE UNUSED LOGIC MOUNT HOLE MH3 U6F MOUNT HOLE HD74LVC14T AGND GND MOUNT HOLE RENESAS SOLUTIONS CORPORATION M3A HS 60 NECS cusck DEsTeNEOI approve OTHERS SCALE DK304 7 DATE 05 06 01 CHANGE This is a blank page SH7206 CPU Board M3A HS60 User s Manual Publication Data June 1 2005 Rev 1 00 Published by Renesas Technology Corp Renesas Solutions Corp 2005 Renesas Technology Corp All rights reserved Printed in Japan M3A HS60
16. 1 18 SW3 2 PA19 we PA24 BN 07704 25 Figure2 5 1 Block Diagram of SH7206 I O Ports Rev 1 00 June 1 2005 2 10 TENESAS REJ11J0002 0100Z Functional Overview REJ11J0002 0100Z TENESAS 2 5 I O Ports Table2 5 1 Functions of SH7206 Ports SH7206 Port Name Connection in the 560 1 Serial port connector PA2 Extension connector SDRAM_SZ signal input PA3 PA6 PA11 PA17 Extension connector 20 21 PA4 PA5 Flash memory and extension connector PA7 PA9 PA13 PA22 PA23 SDRAM and extension connector 12 Flash memory SDRAM and extension connector PA13 SDRAM and extension connector PA18 SW1 1 and extension connector PA19 SW1 2 and extension connector PA24 SW1 3 and extension connector PA25 SW1 4 and extension connector PB2 PB3 Extension connector PB4 PB5 SDRAM and extension connector PB9 Flash memory and extension connector PCO Extension connector PC1 Flash memory SDRAM and extension connector PD8 PD15 Flash memory SDRAM and extension connector PD16 PD31 SDRAM when 32 bit bus selected and extension connector PE1 LED2 and extension connector PE2 LED3 and extension connector PE7 PE9 PE12 PE13 PE16 Extension connector PE8 LED4 and extension connector PE10 LED5 and extension connector PE11 LED6 and extension connector PE14 LED7 and extension connector PE15 LED8 and extension connecto
17. 1 1 shows the M3A HS60 connectors assignments lt Top view of the component side gt 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 244 R72 0 se el a 28 7 J8 919 15 17 19 21 23 25 27 29 31 33 35 37 39 4 3 2 9n E ee 7 lt lt J2 8 99999 QK30477 A MADE IN JAPAN 1 2 J3 J5 Say toy 412 2 DK30477 A MADE IN JAPAN ee 5 EB lt J6 2 oa CP27 ma INN 23 LT CP30 y E 48 1 Tis SEBE a 8 R36 1124 oF ka woe EE R29
18. 5 User J2 LED Serial Port Connector swe Reset Switch SW3 U2 U9 SW6 NMI User Clock Oscillator RS 232C MRES Switch DIP Switch Buffer 16 67MHz Driver Switch Top view of the Sidas Solder side U10 3 3V Power J6 Regulator U12 1 25V Powe Regulator N Address Shift Buffer U6 Logic IC LVC14 Uti Reset IC 2 e es si e m 12V 3 3V 39 J10 Extension connector not mounted Figure1 6 1 M3A HS60 Board Overview Rev 1 00 June 1 2005 RENESAS REJ11J0002 0100Z Overview 1 1 6 M3A HS60 Board Overview Table1 6 1 lists main components mounted in M3A HS60 Table1 6 1 Main Components Mounted 560 Recommended parts Symbol Component name Note number for not mounted components Makers U1 CPU SH7206 by Renesas U2 Clock Buffer Not mounted CY2305SC 1 by Cypress U3 Flash Memory M5M29KT331AVP by Renesas U4 U7 Address Shift Buffer U5 U8 SDRAM EDS1216AATA 75 U6 Logic IC 09 RS 232C Driver U10 3 3V Power Regulator U11 Reset IC M51957BFP by Renesas U12 1 25V Power Regulator XI 16 67MHz Oscillator 16 67MHz X2 Ceramic Resonators Not mounted 16 67MHz CSTCE G16M67 by Murata J1 H UDI Connector J2 Serial port Connector J3 J5 External Power Supply Connector Not mounted A2 2PA 2 54DSA by Hirose J4 Power Supply Connector J6 Extension connector Not mounted XG4C 2634 Right angle 26pin MIL Standard Connector J7 J8
19. Specify data bus BSZ 1 0 B 10 16 bit bus width BSZ 1 0 B 11 32 bit bus width CS3 Space Wait Control Register CS3WCR Initial value H 0000 0500 Recommended set value H 0000 2892 Precharge completion wait cycles WTRP 1 0 01 1 cycles Wait cycles between ACTV command gt READ A WRITE A command WTRCD 1 0 10 2 cycles Area 3 CAS latency 1 0 01 2 cycles Precharge start wait cycles TRWL 1 0 B 10 2 cycles Idle cycles between REF command self refresh deactivation gt ACTV REF MRS command WTRC 1 0 B 10 5 cycles SDRAM Control Register SDCR Initial value H 0000 0000 Recommended set value H 0000 0809 Refresh control RFSH B 1 Refresh enabled Refresh control RMODE B 0 Auto refresh Bank active mode BACTV 0 Auto precharge mode Area 3 row address bits A3ROW 1 0 B 01 12 bits Area 3 column address bits A3COL 1 0 01 9 bits Refresh Timer Control Status Register RTCSR Initial value H 0000 0000 Recommended set value H A55A 0010 Clock select CKS 2 0 B 010 16 Refresh times RRC 2 0 000 1 time Refresh Time Consiant Register RTCOR Initial value H 0000 0000 Recommended set value H A55A 0041 The following shows refresh request intervals in cases when clock select is set to B 6 16 1 cycle 240ns 66 2 16 4 125MHz Refresh request intervals for the SDRAM every 15 625us 15 625us 240ns 64 0x41 cycles per re
20. always be ON SW4 5 OFF Releases write protect for the flash memory WPO pin state H FLASH _WP ON Write protects the flash memory WPO pin state L When using the J6 connector make sure the SDRAM bus width is set to 16 bit access SW4 1 OFF Table3 2 5 lists the functions of the LEDs mounted in M3A HS60 Table3 2 5 Functions of the LEDs Mounted in M3A HS60 No Color Functions Remarks LED1 Red Power on LED LED1 lights when 3 3 V power is supplied LED2 Green Open to the user LED2 lights when PE1 outputs L LED3 Green Open to the user LED3 lights when PEZ outputs L LED4 Green Open to the user LED4 lights when outputs L LEDS Green Open to the user LED5 lights when PE10 outputs L LED6 Green Open to the user LED6 lights when PE11 outputs L LED Green Open to the user LED7 lights when PE14 outputs L LED8 Green Open to the user LED8 lights when PE15 outputs L Rev 1 00 June 1 2005 REJ11J0002 0100Z 3 16 RENESAS Operational Specifications 3 3 3 Outline Dimensions of M3A HS60 3 3 Outline Dimensions of M3A HS60 Figure3 3 1 shows the outline dimensions of M3A HS60 Connectors can be mounted on J6 J13 so that it is easy to connect extension boards lt Top view of the component side gt Unit mm 100 000 61 000
21. er 32 avec Ned of m 9 uvec Nc Hs 2 x 2 AUDCK 4 NC ras i 5 artoj 0 35 CEZ 121 RALLY i AUDCK NC T R1OUT RIIN ER 0 4uF 2 AUDATAO MV Vot 34 AUDATAO 5 2 T10UT ro 2 AUDATA1 4 AUDATA1 GND s T2IN T20UT o aca 2 AUDATA2 Raz gt 2 AUDATA2 GND 2 RXDO ko R20UT 2 AUDATA3 ANN 9 AUDATA3 GND SP3232E t ra GND 2 _AUDSYNC 4 lid AUDSYNC GND 77 Decoupling Caps TEK i 1 ee R44 XM2C 0912 112 for SP3232E 19 TMS GND 2 _TRST 210 TRST GND B 190 x 25 SND __ gt _ASEMD 2 2 _ASEBRAK _ASEBRK _ASEBRAK GND 1 RES GND GND boa GND 5V TO 3 3V LINEAR REGULATOR 3 3V EXTERNAL POWER LED 3 3VCC ND GND GND 3vcc 777 GND pec a mizo T DXSUMGE 1 2 Power On be 2 3 Power Off AZZPAZSIDSA CES RAS voc avec D 4 Power On Reset Sou zi VO 0 NOUS eil J Vout 3 302V 3vcc Switch 4 3 777 LED1 T m INS as OUT BR1102W 52 SWi 1 5 RED 1 5 2 9 3VCC_EX 3VCC 3VCC_CPU MS 12AAH1 li cea 1 JP1 HH R48 R49 ces CES Ra Power 22uF T 22uF 15 Un UB usc Connector 3 gour gt RESET 236 Rb Ret becoupling Caps 9 IADJ 25pa 1800 EY 9764 MW HDZALVC14T HD74LVCA4T 51957 000 1 2 Fixed 3 3V 1519571 2 3 T V ve RR i T Seis we 2 3 External 3 3V 10 Ca
22. refresh cycles every 64ms Row address A11 AO Column address A8 AO Number of banks 4 bank operation controlled by BAO and BA1 SDRAM 39v 3 3V bus size setting e SDRAM SZ Qo SDRAM_SZ Low 16 bit access using SDRAMx1 SDRAM SZ High 32 bit access using SDRAMx2 5 EDS1216AATA SH7206 alt 32 bit Access 8Mx16 bits 14 Ki 13 2 15 14 14 15 1 7 VA MA11 0 BA1 0 laj A 16 CS3 P Er qCS DQ15 DQ0 gt SH72060 031 016 A A 1 bo DQMUU ANN DQMU DQMUL AAA DQML CKIO Vv CLK CKE AN RD WR gt ANN J WE RASL gt WWW Oj RAS CASL p ANV CASA 16 bit Access A 12 1 A14 13 EDS1216AATA 8Mx16 bits 14 11 0 1 0 ZN 4jCS 0015 000 8 72060 015 00 x 1 DQMLU AM DQMU DQMLL ANN DQML ANN CLK CKE WE o RAS CAS Figure2 3 3 Block Diagram of External SDRAM Rev 1 00 June 1 2005 2 6 TENESAS REJ11J0002 0100Z Functional Overview 2 2 3 3 External SDRAM Table2 3 4 lists bus state controller settings for operation with the SH7206 Bus clock at 66 67MHz Table2 3 4 Examples for Bus State Controller Settings SDRAM Read Write User Area Application Device Bus State Controller Settings CS3 EDS1216AATA 75E CS3 Space Bus Control Register CS3BCR Initial value H 36DB 0600 Recommended set value H 0000 4400 for 16 bit bus or H 0000 4600 for 32 bit bus Specify memory TYPE 2 0 B 100 SDRAM
23. supplied from regulator 1 2VCC 1 25V System Power Supply Voltage 1 15V to 1 35V Relative to VSS Normally supplied from regulator Maximum Power Consumption in the Board Within 1A Topr Operating Ambient Temperature 5 to 50 C dewdrops allowed Use in corrosive gas environment prohibited Rev 1 00 June 1 2005 RENESAS 1 Overview 1 8 Absolute Maximum Ratings This is a blank page Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 2 1 Chapter2 Functional Overview 2 2 1 Functional Overview Functional Overview 2 1 Functional Overview Table2 1 1 lists the functional modules of 60 Table2 1 1 Functional Modules of 60 Sections Function Content 2 2 CPU SH7206 Slnput XIN clock 16 67MHz Bus clock 66 67MHz max CPU clock 200MHz max 2 3 Memory Following items of memory are included SDRAM 32 Mbytes max By switching a DIP switch the following memories can be selected When 16 bit bus width is selected EDS1216AATA 75E x 1 16 Mbytes When 32 bit bus width is selected EDS1216AATA 75E x 2 32 Mbytes Flash memory e M5M29KT331AVP x 1 4 Mbytes Data bus width fixed to 16 bits 2 4 Serial port interface Connects SCIFO of the SH7206 to the Serial port connector 2 5 ports Connects to the I O ports of the SH7206 2 6 Power Supply Circuit Controls the system power supply of the M3A HS60 2 7 Clock
24. 1 00 June 1 2005 3 17 TENESAS REJ11J0002 0100Z Operational Specifications 3 3 3 Outline Dimensions of M3A HS60 This is a blank page Rev 1 00 June 1 2005 3 18 RENESAS REJ11J0002 0100Z Appendix M3A HS60 Schematics A 1 This is a blank page A 2 SH 2A SH7206 CPU BOARD M3A HS60 SCHEMATICS TITLE INDEX CPU SH7206 FLASH SDRAM UDI RESET UART POWER BUS CONNECTORS PUSH SW OTHERS Note VCC 5V 3VCC 3 3V 1 2VC G gt CE CP Fixed Resistors Resistor Array Ceramic Caps Tantalum Electrolytic Caps Decoupling Caps mounted RENESAS SOLUTIONS CORPORATION 5 6 Li 3VCC CPU 12NCC 1 1 aveca MD2 MDO BUS Size ni 32bit Bus 1 avec To ul M E 0 16bit Bus SH7208 8 4 nir 8bit Bus 0 25 346
25. 1 23 25 27 29 31 33 35 37 39 MN is 10000000000 DK30477 A MADE IN JAPAN s e e 13 3 3V 2 SW1 0 LED1 GND Q 4 FLWP L I B M SW4 sw e NCK2 L 72 Koj 50 16 32 1 2 35 1 2 FIX 12V sego 2 3 073 39 semi o e KII E llel o si 72 R41 5 LL e gt ezo rel o ze9e e e 9 SP3232 e ET 28 tov SW6 Figure3 2 1 M3A HS60 Operational Component Assignment Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 3 Operational Specifications 3 2 1 Power Supply Select Jumpers JP1 and 2 3 2 1 Power Supply Select Jumpers JP1 and JP2 The SH7206 uses 3 3V and 1 25V power supply voltages The JP1 and JP2 allow the sources for the SH7206 power supply voltages 3 3V and 1 25V to be selected Figure3 2 2 shows the SH7206 Power Supply Voltage Select Jumpers Assignment JP1 and JP2 Table3 2 1 and Table3 2 2 list jumper settings for selecting SH7206 power supply voltage Initial Setting Board edge 1 2V PWRSEL view of the component side JP2 33V JP1 al PWRSEL Figure3 2 2 SH7206 Power Supply Voltage Select Jumper Assignment JP1 and JP2 Table3 2 1 Jumper Settings for Selecting SH7206 Power Supply Voltage JP1 Jumper Setting Fu
26. 1 AVREF id 8888889880808 29599999 6 wow Reserve lt 999999999999 51 A0 MoDo A moo A2 H ES RI o A4 AW MD_CLKO 4 A5 i A5 MD2 pin is fixed to H H3 as Hi 3 MDO pin is fixed to L 8 mm RY Rsv tvs E RSV2 PVSS CSO 16bit Fer 1 aN XTAL H KO RI 220 ENTAR RA 20 R5 220 1 avcc 4 CKIOH 14 RE 220 15 A16 16 26 AT rot 18 Me 19 29 AZO A20 35 6 RESET 20 _RES A21 IRQ7 _ADTRG _POE8 PB9 45 6 1434 NMI A22IDREQ1 IRQTISCK1 PA5 4L 522 fe WDTOVF _WDTOVF A23 TXD1 PA4 ro A24 RXD1 PA3 42 A25 2050 esp cso A25 DREQO IRQO SCKO PA2 L 00 31 3 4 6 zi ES1 POESIPA11 6 CS2 TCLKAIPAG 1080 7 Cs2 TCLKAIPAG PI 4 1 111 4 6 _CS3 TCLKB PA7 161 D2 2 R13 on 6 _ 8 16 TCS8 PE16 02 182 03 E MV lt ES 03 36 RD RD pa 1568 avec 3 4 6 WEO DQMLL Ed WEO DQMLL POE6 PA12 Ds H DE 46 WE1 DQMLU 2 DAMLU POEZIPA13 pe 154 D 4 6 WE2 DQMUL 1710 ICIORD DQMULITICSV PA22 07 DS 4 6 _WE3 _DQMUU wea ICIOWRI DQMUU TICEW PA23 DB TIOC3AS PD8 H DS 6 _WAITIDACK2IPA17 TWAITIDACK2 PA17 D9 TIOC3BS PDo 151 D40 TIOC3CS PD10 120 pA D11 TIOC3DS PD11 448 DIZ xi D12 TIOC4AS PD12 _BSIRXD2TIOC2B _UB
27. 241 PD30 r 24 2 EXCLK L 2 ANO 221 2 IRQ1 POE1 SDA PB3 2 1 3 3 2 IRQ0 POEO SCL PB2 A9 A AS 5 He ee l XG4C 2634 AB AB 5 8 24 ROLWR Pg in Sip fn fn fn fl KEE fS s 67 i 26 2 3 4 WEO DOMLL 24 DOMLU avcc 5i 8 24 _WE2 DQMUL 3 3 24 _WE3 _DQMUU 10 30 64 R72 14 01 AT 124 24 CASL 3300 AQ 13 A0 2 _CS8 PE16 023 a eM 2 5 SCK2 TIOC3A PEB 2 _CS1 POESIPA11 1 25 TXD2MIOCICIPE10 LEDS 2 _CS2 TCLKA PAG 16 26 2 BSIRXDZTIOCZB UBCTRG PE7 R GREEN 2 _RASUIPINT4 _Cs4 PA20 pate 25 DREQS PINTG PA24 1 MI GARRA IS Cr Rm mare EE E iecur ato sf 31908 AJ 25 19 O O TI G4C 2031 G4C 4031 TIOCAD PET5 NMI SWITCH CIRCUIT avec R73 R77 on 00 R74 1000 R75 00 AW AW gt g 2 2 WAITIDACK2IPA17 Ko NMI CEM UGE Ra SW5 ATF HD74LVC14T HD74LVC14T P NET B3SN 3012 lo SWITCH 234 0031 WAITIDACK2 PA17 T 031 4 l 030 029 eJ T 028 100445 DACKTPD2 D27 8 TIOCABS DACKUPD26 026 9 77 TIOCACS DREQI PD25 D25 10 DREQU PD24 D24 11 IRQ7IPD23 023 1 T IRQGIPD22
28. A 0 a pat SDIS E 09 Rea loss 28 285 19d cs sos 88 E 2A6 286 29 28 RASL R28 AMON 18d RAS 2 7 287 PB 26 _ 19 cas ma 2A8 288 22 26 RD WR B29 90 160 we Nc 20 2A9 289 26 RM od Nc Ex RAB 2A10 2810 2 6 _WE3 _DQMUU DOMUU 39 mE 1 16 023 2 00 DOMU M i 26 WE2 DOMUL AM 15 mE AM 022 10E4 Nc H spo AWN ia 20E 28 33 a SDCKE a 32 E I3C16210 avcc 12 38 CLK 5019 Ai 519 ds VC da o 5018 D18 HD74LVC14T 8838883 NH DIE 9999999 016 EDS1216AATA 0 RAJ 3031 1 16 031 030 AW 530 777 5029 RAMI 14 D29 5028 ALT D28 5027 AW D27 SVDD1 SVDDQ1 D26 6 NY 11 D26 o ES svop1 1 svopat sw 2 avc avec 0 SDRAM SZ L 16bit MODE Bat OA RIS AM 00 1M 181 H e 1 2 182 45 uoJ 9 1A3 183 4 SA 1M 184 ex 4 8885555 1A5 185 Hi AS gt gt gt 1A6 186 AT 2255 1A7 1B7 5 0015 SDIS 182 38 SATS 20 51 5014 15 siao SA9 0914 50 5013 en 1159 36 SATO SA12 0913 a 5012 ATT A i DIT SAM ATO MO Dan DIO 2A1 281 4 4 PA 281 SAIZ SAD 2910 py 509 242 282 SATS SAB Ed 508 oy 281 SATA SAT A E Das 507 ea 5 por x 20 26 286 29 9 A4 5 10 pe 5 21 27 287 28 EH 26 A3 pas 2A8 503 Zu BE Eii 28 2A10 2810 25
29. B 56 TENDO TIOCOB PE1 TENDO TIOCOB PE1 5 56 DREQITIOCOCIPEZ DREQ TIOCOC PE2 110 16 66MHz TEK TEK B 5 777 9 56 _BREQ TENDO PINT2IPAI8 _BREQ TENDO PINT2 PA18 TDI TO 6 CERALOCK 3 5 6 _BACK TEND1 PINT3 PA19 LBACKITEND1 PINT3 PA19 TDO TDO 5 5 6 DREQ3 PINTG PA24 LCE2A DREQS PINTG PA24 TRST pitt _ 5 E 56 DACK3 PINT7 25 LCE2BIDACK3 PINT7 25 _ASEMD TASEMD 5 R14 00 _ASEBRKAK _ASEBRK P04 31 TASEBRAK _ASEBRK 5 ASEBCK 207 Reva RSV3 PVCC avec uz 6 TIOC4D PE15 DACKI CKE TIOCA4D IRQOUT PE15 CKIO 6 _MRES TIOC4B _MRES TIOC4B PE13 DREQO TIOCOA AUDCKIPEO AUDCK 5 REF CLKO 6 TIOCAC PE14 WE3 ICIOWR AH DACKO TIOCACIPE14 WE3 ICIOWR AH DOMUU DREQ2 CKE AUDSYNC PA16I AUDSYNC 5 CLK1 6 TIOC4A PE12 TXDS TIOC4A PE12 ere gt EXCLK 6 6 TIOC3DIPE11 RXD3 TIOC3D _CTS3 PE11 A DKTAS 0 4uF CLK3 l 6 TIOC3B PE9 SCK3 TIOC3B RTS3 PE9 CS7 SCK3 TIOC2A AUDATAO PE6 84 AUDATAT AUDATAO 5 AVREF _CS6 _CE1B TXD3 TIOC1B AUDATA1 PES AUDATAZ 5 23055 1 EE TOIS16 RXD3 TIOC1A AUDATAZIPEA E AUDATA2 5 ia TEND 1 TIOCOD AUDATA3 PE3 AUDATAS 5 Bv EJ AVREF For SH7206 Bus Connector CLK 6 ANOJPFO 12VCC 6 ANTIPF1 T 6 2 ANZIPF2 PLLVCC E e 8 6 AN3 AN3 PF3 6 E 6 ANS 5 One 6 ANG DAO PF6 9
30. CTRGIPE7 lt gt PE 14 8SIRXD2ITIOC2B UBCTRGIPE7 D13 TIOCABS PD13 14 4 R10 A 180 XIN 14 014 L CP1 VCC OUT AN D14 TIOCACS PD14 141 DIS i D15 TIOC4DS PD15 ONE oE 60 D16 IRQO PD16 ISGROOZCA 16 1 6 _FRAME CKE TCLKD IRQ3 PA9 D16 IRQO _POE4 AUDATAOIPD 16 140 017 1861707 46 RD WR E 49 RD WRIIRQ2 TCLKC PA8 D17IIRQ1 POESIAUDATA1 PD17 188 DIS 1827618 16 66MH 4 6 RASL 1 0 RASLIRO2 POE2IPBA LO D18 IRQ2 POEG AUDATAZ PD 18 138 DIS TROSPDIS 2 6 _RASUIPINT4 _CS4 PA20 15 RASUIPINT CSAIPA20 D19 IRQ3 _POEZ AUDATASIPD 19 182 TRORIPDOD 14 6 CASL _ 5 D20 IRO4 TICSWS PD20 021 IROS PD21 a aa 6 _CASUIPINTSI_CS5 _CE1A TICSU PA21 TCASU PINTS _CS5 _CE1A TICSU PA21 D21 IRQS TICSVS PD21 022 iRQG PD22 pas Co D22 IRQ TICSUSIAUDCK PD22 134 555 XOUT R82 1M0 Li SEKA IRQ1 POE1 SDA PB3 D23 IRQ7 _AUDSYNC PD23 i AM 6 IRQO POEO SCL PB2 IRQO POEO SCLIPB2 D24 DREQO TIOCADS PD24 130 T D25 DREQT TIOCACSIPD25 122 D TIOCABS D26 DACKO TIOCABS PD26 D27 TIOCAAS 5 lt _CS5 _CE1A PINT1 TXDO PA1 D27 DACK1 TIOC4AS PD27 I 555 gt 15 RXDO D28 CS2 TIOC3DS PD28 124 525 N D29 _CS3 TIOC3BS PD29 530 PD30 L J D30 TIOC3CS IRQOUT PD30 031 POST 5 6 TXD2 TIOC3C PE10 TXDZ TIOC3C PE10 D31 TIOC3AS ADTRG PD31 121 CET ENMS 56 SCK2 TIOC3AIPEB SCK2 TIOC3A PE
31. Extension connector Not mounted A2 3PA 2 54DSA MIL Standard Connector J9 J11 J13 Extension connector Not mounted XG4C 2031 20pin MIL Standard Connector J10 J12 Extension connector Not mounted XG4C 4031 40pin MIL Standard Connector LED1 Power LED Red LED2 8 User LED Green SW1 Power Switch SW2 Reset Switch SW5 NMI Switch SW6 MRES Switch SW3 User DIP Switch SW4 System setup DIP Switch Rev 1 00 June 1 2005 RENESAS 1 7 REJ11J0002 0100Z Overview 1 1 7 60 Memory Mapping 1 7 M3A HS60 Memory Mapping Figure1 7 1 shows the memory mapping example of SH7206 in the M3A HS60 Logical address Logical space of theSH7206 Memory Mapping of the M3A HS60 H 0000 0000 Flash Memory 4MB H 003F FFFF CSO space 64MB bus User area H 0400 0000 CS1 space 64MB User area H 0800 0000 CS2 space 64MB User area 0 00 0000 CS3 space 64MB H OCFF FFFF User area H ODFF User area H 1000 0000 CS4 space 64MB User area H 1400 0000 CS5 space 64MB User area 1 2589 0000 Reserved area CS6 space 64MB Disabled pas Reserved area CS7 space 64MB Disabled H 2000 0000 CS0 CS7 spaces CS0 CS7 spaces non cacheable area non cacheable area H 4000 0000 CS8 space 1GB User area meee ku Reserved area Reserved area Disabled Disabled H FFF8 0000 Internal RAM 128KB Internal RAM 128KB Tree Internal RAM Reserved Internal RAM Reserved H FFFC 0000 Internal periph
32. L IRQ2 POE2 PB4 lt gt RES CASL IRQ3 POE3 PB5 gt MRES TIOC4B PE13 BS RXD2 TIOC2B UBCTRG PE7 c c WDTOVF SCK2 TIOC3A PE8 gt 7 BREQ TENDO PINT2 PA18 IRQ1 POE1 SDA PB3 BACK TEND1 PINT3 PA19 IRQO POEO SCL PB2 lt gt ike citie gt A25 DREQO IRQO SCKO PA2 TXD2 TIOC3C PE10 lt gt DMAC GPIO lt gt A24 RXD1 PA3 TENDO TIOCOB PE1 lt gt MTU2 Address bus 23 A23 A1 DREQ1 TIOCOC PE2 lt gt Eik SCK3 TIOC3B RTS3 PE9 lt gt D31 TIOC3AS ADTRG PD31 TXDSHTIOGANPETE D30 TIOC3CS IRQOUT PD30 MESI SJNTIO IBS PDRO DACKI CKE TIOC4AD IRQOUTAYPE15 lt gt 5 UR WE3 ICIOWR AH DACKO TIOC4C PE14 C lt gt D27 DACK1 TIOCS4AS PD27 SINKI lt gt D26 DACKO TIOC4BS PD26 AUDATAO 3 lt gt D25 DREQ1 TIOC4CS PD25 TOR Data bus lt gt D24 DREQO TIOC4DS PD24 TMS lt gt D23 IRQ7 PD23 TDI D D22 IRQ6 TIC5US PD22 TDO gt lt gt D21 IRQ5 TIC5VS PD21 TRST B lt gt D20 IRQ4 TIC5WS PD20 ASEBRKAK ASEBRK lt gt D19 IRQ3 POE7 PD19 AUDCK gt lt gt D18 IRQ2 POE6 PD18 AUDSYNC D17 IRQ1 POE5 PD17 ASEMD lt gt 16 D16 IRQ0 POE4 PD16 ASEBCK lt gt D15 0 ASEBRK CSO TXDO Serial port 1 11 RXDO Interface CS24 TCLKA PAG Bue CS3 TCLKB PA7 5 6 A D Converter lt gt CS4 RASU PINT4 PA20 AN6 DAO PF6 C D A Converter lt gt CS5 CE1A CASU PINT5 TIC5U PA21 AN7 DA1 PF7 c
33. Module Controls the clock 2 8 Reset Module Controls device reset mounted on the M3A HS60 2 9 Interrupt switches Connects to NMI and MRES pins 2 10 E10A USB Interface SH7206 H UDI AUD interface Operational specifications Connectors switches and LEDs SH7206 extension connector Switches and LEDs H UDI connector Detailed in Chapter 3 Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 2 2 Functional Overview 2 2 2 CPU 2 2 2 2 1 SH7206 The M3A HS60 contains SH7206 the 32 bit RISC microcomputer which operates with a maximum 200MHz of CPU clock frequency The SH7206 includes 128 Kbyte RAM 8 Kbyte instruction cache and 8 Kbyte data cache and it can deal with a wide range of applications from data processing to equipment control The 60 can be operated with a maximum 200MHz of CPU clock frequency external bus 66 67MHz max using a 16 67MHz input clock Figure2 2 1 shows the block diagram of SH7206 in the M3A HS60 SH7206 WAIT DACK2 PA17 c Clock lt RD gt WE0 DQMLL POE6 PA12 lt gt WE1 WE DQMLU POE7 PA13 gt gt 3 3V MD2 _ space WE2 ICIORD DQMUL TIC5V PA22 lt gt Bus control ode GND MDO Fixed 16 bit bus WE3 ICIOWR AH DQMUU TIC5W PA23 gt gt MD_CLK2 Mode 2 RD_WR IRQ2 TCLKC PA8 lt gt L GND MD_CLKO FRAME CKE TCLKD IRQ3 PA9 lt gt RAS
34. OH tWDD2 ltoHZ tWDH2 00 31 Rev 1 00 June 1 2005 REJ11J0002 0100Z Figure2 3 4 Typical SDRAM Single Read Write Timing TENESAS Functional Overview 2 2 4 Serial Port Interface 2 4 Serial Port Interface The SH7206 included in the M3A HS60 contains a UART module As for the M3A HS60 SCIF channel 0 is connected to serial port connector Figure2 4 1 shows a block diagram of serial port interface in the M3A HS60 Serial port RS 232C connector SH7206 driver 1 pcp RXDO b 2_ TXDO 3 GND e GND 6 psi 7 RTS L U NC 24 RIE Figure2 4 1 Block Diagram of Serial Port Interface Rev 1 00 June 1 2005 2 9 TENESAS REJ11J0002 0100Z Functional Overview 2 2 5 I O Ports 2 5 I O Ports As for the M3A HS60 the SH7206 s I O ports are connected to the extension bus connector of the M3A HS60 board Some ports are connected to DIP switches and LEDs of the M3A HS60 board Users are free to use these ports Figure2 5 1 shows a block diagram of SH7206 I O ports Table2 5 1 shows the functions of SH7206 I O ports 3 3V oen e e e e LED8 LED7 LED6 LED5 LED4 LED3 LED2 GREEN GREEN GREEN GREEN GREEN GREEN GREEN SH7206 AA PE1 PE2 PE8 PE10 PE11 PE14 PE15 3 3V e DIP Switch SW3
35. REJ11J0002 0100Z NESAS SH7206 CPU Board M3A HS60 User s Manual Renesas32 Bit RISC Microcomputers SuperH RISC Engine Family SH7200 Series SH7206 Group Rev 1 00 Renesas Technology Issued June 1 2005 WWW renesas com Microsoft MS DOS Windows and Windows NET are registered trademarks of Microsoft Corporation of the U S in the U S and other countries IBM and AT are registered trademarks of International Business Machines Corporation of the U S Adobe and Acrobat are registered trademarks of Adobe Systems Incorporated All other brand names and product names are registered trademarks or trademarks of the respective proprietors Requests for Safety Design Renesas is constantly making efforts to improve the quality and reliability of its products However not all semiconductor products are trouble free they may become faulty or operate erratically To ensure that no accidents such as injury or a fire or no social damage may arise from Renesas semiconductor products should they become faulty or operate erratically please pay careful attention to the safety design of your system by for example considering redundancy design and incorporating measures to check the spread of a fire and prevent device malfunction Precautions on Using This Manual This manual only provides reference information to help customers purchase the appropriate type of Renesas Technology product that suits the intended purpose of u
36. SAS 3 9 3 Operational Specifications 3 1 5 User I O Connectors J6 J8 Table 3 1 8 to 3 1 12 list pin assignments of extension connector Table3 1 8 Pin Assignment of Extension connector J9 Pin Signal name Pin Signal name 1 NC 2 NC 3 EXCLK 4 AQ 5 A8 6 7 7 8 9 4 10 11 A2 12 1 1 13 _ AO PCO 14 CSO 15 CS1 POE5 PA11 16 CS2 TCLKA PA6 17 RASU PINT4 CS4 PA20 18 CASU PINT5 CS5 CE1 A TIC5U PA21 19 RESET 20 GND Table3 1 9 Pin Assignment of Extension connector J10 Pin Signal name Pin Signal name 1 3 3V 2 3 3V 3 WDTOVF 4 A25 DREQO IRQO SCKO PA2 5 A24 RXD1 PA3 6 A23 TXD1 PA4 7 A22 DREQ1 IRQ1 SCK1 PA5 8 A21 IRQ7 ADTRG POE8 PB9 9 A20 10 19 11 18 12 17 13 16 14 15 15 14 16 13 17 12 18 11 19 Ato 20 GND 21 NC 22 NC 23 EXCLK 24 AQ 25 ag 26 7 27 28 A5 29 4 30 31 A2 32 1 1 33 34 CSO 35 CS1 POES5 PA11 36 CS24 TCLKA PAG 37 RASU PINT4 CS4 PA20 38 CASU PINT5 CS5 CE1 A TICSU PA21 39 RESET 40 GND Rev 1 00 June 1 2005 RENESAS REJ11J0002 0100Z 3 10 Operational Specifications 3 1 5 User I O Connectors J6 J8 Table3 1 10 Pin Assignments of Extension Connector J13
37. V FLASH WP 3 ABS 5101 DRAWN CHECKED DESIGNED APPROVED H UDI RESET UART POWER 5 7 SCALE CHANGE 1 0 DATE 05 06 01 DK30477 A 4 5 Extension Connector Extension Bus Connector avec 964 Res 1 on oo IRQO PD16 24 IRQOPDIS RATED pe Re eee dia 24 IRQWPD17 ROPNE 2 4 IRQ2 PD18 g C gt l l 24 TIOC4AS 1 241 TIOC4BS i 234 0 25 robi 106403 DREQOIRQUISCKOIPA2 A25 4 BI RXDI PAS_A24 l aera TIOC4B TXDIPAJ 423 6 TIOCSDIPETT DREQIRGUSCKIPAS 22 2 TIOCADIPE1S 1 T TRO7 ADTRGI POEB PBS AZT 8 1 2 TIOCAD PE15 2 AN5 Lu 2 TIOCACIPE14 BEN 02 ANG MS i 24 IRO4 PD20 BI AN7 1 Roepe TROGIPOZZ AZ3PA 2 54DSA 1 24 IROS PD19 16 13 2 4 IRQ3 PD19 ANZ t A15 14 l 7 AN AN3 1 14 1 B ANA AS 16 2 R67 t 1 PD28 11 18 BAr Pe PD29 ATO 18 24 PD29 d t
38. WR IRQ2 TCLKC PA8 5 WEO DQMLL POE6 PA12 6 WE1 WE DQMLU POE7 PA13 7 __ WE2 ICIORD DQMUL TICSV PA22 8 WE3 ICIOWR AH DQMUU TIC5W PA23 9 FRAME CKE TCLKD IRQ3 PA9 10 RASL IRQ2 POE2 PB4 11 CASL IRQ3 POE3 PB5 12 CS8 PE16 13 SCK2 TIOC3A PE8 14 TXD2 TIOC3C PE10 15 BS RXD2 TIOC2B UBCTRG PE7 16 CE2A DREQ3 PINT6 PA24 17 CE2B DACK3 PINT7 POE8 PA25 18 BREQ TENDO PINT2 PA18 19 BACK TEND1 PINT3 PA19 20 GND Rev 1 00 June 1 2005 3 12 RENESAS REJ11J0002 0100Z 3 2 Outline of Switches and LEDs The 60 includes switches and LEDs as its operational components Figure3 2 1 shows the M3A HS60 Operational Component Assignment lt Top view of the component side gt oc 2 1 e e e FLASH Oo NMI 48 E 5 J12 LED sim TT LED6 6 8 LED7 E i LED8 PE15 Hee e u M 28 dee Lee S Eu LED 2 5 JP1 JP2 PE ZME 4426 4 ede WR 200008000080 Serene ee 6 sv0000 GOS Eo De 132 20 19 u m n 12V PWRSEL k o 30 31 ON Operational Specifications 3 2 Outline of Switches and LEDs OFF 91017206 ENES S et 555 SW2 SW3 SW5 17 19 2
39. and performance of original microcomputers of Renesas Technology the SH7206 series With the board you can develop and evaluate the application software for the SH7206 series The SH7206 s data bus address bus and pins of various internal peripheral circuit function are connected to the extension bus connector of the M3A HS60 Thus you can evaluate the timing relationships with peripheral devices by using measurement instruments You can also develop extension boards depending on development purposes Furthermore the E10A USB the on chip emulator made by Renesas Technology can be connected to the M3A HS60 1 2 Configuration Figure1 2 1 shows an example system configuration using M3A HS60 1 SH7206 CPU Board Power supply M3A HS60 5V 1 5A or more H UDI AUD Application Board xtension Serial port connector onnector l l l l 757 debugger High performance 1 Embeded Workshop HEW SANI SuperH RISC engine 1 E10A USB 71 C C compiler package Host 1 Computer 1 Option Items It is necessary to prepare separately for software development Figure1 2 1 Example System Configuration of 560 Rev 1 00 June 1 2005 RENESAS REJ11J0002 0100Z 1 1 3 External Specifications Overview 1 3 External Specifications Table1 3 1 lists external s
40. e J6 connects the pins multiplexed to data bus 031 016 of SH7206 Therefore the data bus 031 016 becomes unusable when the J6 is used Please set the SDRAM bus width to 16 bit wide 015 00 when the J6 is being used Board edge Board edge Top view of the Solder side Top view of the Component side Figure3 1 6 Pin Assignment of Extension Connectors J6 J8 Table3 1 6 and Table3 1 7 list pin assignments of the extension connectors Table3 1 6 Pin Assignments of Extension Connector J6 Pin Signal Name Pin Signal Name 1 5V 2 GND 3 NC AN3 PF3 when R66 is mounted 4 D27 DACK1 TIOC4AS PD27 5 D26 DACKO TIOC4BS PD26 6 D25 DREQ1 TIOC4CS PD25 7 SCK3 TIOC3B RTS34 PE9 8 TXD3 TIOC4A PE12 9 MRES TIOC4B PE13 10 RXD3 TIOC3D CTS3 PE11 11 DACK1 CKE TIOC4D IRQOUT PE15 12 WE3 ICIOWR AH DACKO TIOC4C PE14 13 D20 IRQ4 TIC5WS PD20 14 D21 IRQ5 TIC5VS PD21 15 D22 IRQ6 TIC5US AUDCK PD22 16 D19 IRQ3 POE7 AUDATA3 PD19 17 AN2 PF2 18 19 AN4 PF4 20 NC AN4 PF4 when R67 is mounted 21 D28 CS2 TIOC3DS PD28 22 D29 CS3 TIOC3BS PD29 23 D30 TIOC3CS IRQOUT PD30 24 D31 TIOC3AS ADTRG PD31 25 ANO PFO 26 AN1 PF1 Rev 1 00 June 1 2005 3 7 RENESAS REJ11J0002 0100Z Operational Specifications 3 1 5 User I O Connectors J6 J8 Table3 1 7 Pin Assignments of Extension Connectors J7 and J8
41. eral module Internal peripheral module Note There is the cacheable area from H 0000 0000 H 1FFF Figure1 7 1 Memory Mapping Example of SH7206 Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 1 1 8 Absolute Maximum Ratings Table1 8 1 lists the absolute maximum ratings of 60 Overview 1 8 Absolute Maximum Ratings Table1 8 1 Absolute Maximum Ratings of M3A HS60 Symbol Parameter Rated Value Remarks VCC 5V System Power Supply Voltage 0 3V to 6 0V Relative to VSS 3VCC 3 3V System Power Supply Voltage 0 3V to 4 6V Relative to VSS 1 2VCC 1 25V System Power Supply Voltage 0 3V to 1 7V Relative to VSS Topr Operating Ambient Temperature 5 C to 55 No dewdrops allowed Use in corrosive gas environment prohibited Tstr Storage Ambient Temperature 10 C to 60 C No dewdrops allowed Use in corrosive gas environment prohibited Note The ambient temperature refers to the air temperature in the closest place from the board 1 9 Recommended Operating Conditions Table1 9 1 lists the recommended operating conditions of the M3A HS60 Table1 9 1 Recommended Operating Conditions of 60 REJ11J0002 0100Z Symbol Parameter Rated Value Remarks 5V System Power Supply Voltage 4 75V to 5 25V Relative to VSS 3 3V System Power Supply Voltage 3 0V to 3 6V Relative to VSS Normally
42. erational Specifications 3 1 2 Serial Port Connector J2 The M3A HS60 includes a serial port connector for serial communication J2 Figure3 1 3 shows a pin assignment of serial port connector Board Board o V J J2 OO i edge Top view of the Component side Side view Table3 1 2 lists pin assignments of serial port connector Figure3 1 3 Pin Arrangement of Serial Port Connector J2 Table3 1 2 Pin Assignments of Serial Port Connector J2 Pins 4 8 are loopback connected Rev 1 00 June 1 2005 REJ11J0002 0100Z RENESAS Pin Signal Name Pin Signal Name 1 NC 6 DSR 2 RXD PAO RxDO 7 RTS 3 TXD PA1 TxDO 8 CTS 4 DTR 9 NC 5 GND 3 4 Operational Specifications 3 3 1 3 External Power Supply Connectors J3 and J5 3 1 3 External Power Supply Connectors J3 and J5 The M3A HS60 has the through hole for two external power supply connectors J3 for 3 3 V and 45 for 1 25 V for the SH7206 Figure3 1 4 shows a pin assignment of external power supply connectors J3 J5 Top view of the Component side e qu Board edge Figure3 1 4 Pin Arrangement of External Power Supply Connectors J3 and J5 Table3 1 3 and Table3 1 4 list pin assignments of external power supply connectors Table3 1 3 Pin Assignments of External Power Supply Connect
43. erview 1 5 M3A HS60 Block Diagram Figure1 5 1 shows the system block diagram of M3A HS60 User I O Connector Flash memory 4MB M3A HS60 SH7206 CPU Board Serial port 7206 200MHz SDRAM 16MB x 2 16 or 32 16 or 32 External 66 67MHz Extension connector Enables to connect extension boards or enables to monitor all of bus and peripheral I O signals Rev 1 00 June 1 2005 REJ11J0002 0100Z Figure1 5 1 System Block Diagram of 60 TENESAS 1 1 6 M3A HS60 Board Overview Figure1 6 1 shows the M3A HS60 board overview Overview 1 6 M3A HS60 Board Overview J4 Power SW1 JP1 JP2 Top view of the Power Supply Supply LED1 Component side Use LED Select Jumper Connector Power LED NN 44444 SW4 System setup DIP switch 6 sv0000 svo 1 1 5 H UDI Connector ae 36 pin 9 LILE LED2
44. fresh AC Characteristics Switching Register ACSWR Initial value H 0000 0000 Recommended set value H 0000 0009 AC Characteristics Switch ACOSW S 0 B 1001 Switches characteristics and extends the delay time Rev 1 00 June 1 2005 2 7 TENESAS REJ11J0002 0100Z Functional Overview 2 3 3 External SDRAM apne SINGLE READ SDRAM SINGLE WRITE le me tRC gt le 1RAS sla tRP gt lt tRAS gt lt gt tRCD gt tDPL gt l tDAL gt ACT READA ACT WRITEA ACT Tr Trwi Trw2 Tct Tdi Tde Tap Tr Trwi Trw2 Trw11 Trw12 Tap Tr x j 4 La 4 1 CKE gt 4151 gt tS gt lt 1 gt lt gt tCSD1 tCSD1 gt tCSD1 tCSD1 tRASD1 gt lt tHl kisi tRASD1 gt tRASD1 tRASD1 RASL gt HI gt 4151 gt tCASD1 tCASD1 tCASD1 ICASD1 CASL tRWD1 tRWD1 RD WR tDQMD1 tDQMD1 tDQMD1 gt tDQMD1 DQMUU LL AE a ES I tAD1 1AD1 tAD1 gt tAD1 gt tAD1 gt IAD1 gt A11 A2 A9 A0 qu D 4 SEES 1 gt gt 01 tAD1 gt AD1 gt tAD1 A12 A10 AP gt 4 4 ADI gt FADI gt tAD1 HtAD1 gt A15 A14 BA1 0 eee Gee ee 4 18052 pl lt gt tRDH2 gt 15 7 t
45. lt gt CS8 PE16 lt gt CE2A DREQ3 PINT6 PA24 lt gt CE2B DACK3 PINT7 POE8 PA25 Figure2 2 1 Block Diagram of SH7206 Rev 1 00 June 1 2005 2 3 TENESAS REJ11J0002 0100Z 2 2 3 Memory Functional Overview 2 3 Memory The M3A HS60 includes the internal RAM of the SH7206 128 Kbytes external Flash memory and external SDRAM These memory chips are detailed below 2 3 1 SH7206 s Internal RAM The SH7206 contains an internal 128 Kbyte RAM 2 3 2 Flash Memory M5M29KT331AVP included as standard equipment The M3A HS60 includes the Flash memory shown in Table2 3 1 as standard equipment The memory can be used as the storage in which to save the user program The Flash memory to boot is fixed to 16 bit mode of external bus and operates with a single 3 3 V power supply voltage The write protect of Flash memory can be enabled or disabled by using a DIP switch Figure2 3 1 shows a block diagram of Flash memory Table2 3 2 lists bus state controller settings write read for operation with the SH7206 bus clock at 66 67MHz Table2 3 1 Outline of the Flash Memory Part Number Bus Size Capacity Access Time M5M29KT331 AVP 16 bit mode 4 Mbytes 16 bits x 2 Mword x 1pc 70ns M5M29KT331AVP SH7206 2 M Word x16 bit 19 DQ15 DQ0 3 3V _C BYTE RY BY Rev 1 00 June 1 2005 REJ11J0002 0100Z Figure2 3 1 Block Diagram of Flash Memory TENESAS 2 4
46. nction JP1 1 2 3 3 V fixed power supply voltage supplied from regulator 3 3V PWRSEL 2 3 External power supply voltage supplied from J3 Table3 2 2 Jumper Settings for Selecting SH7206 Power Supply Voltage JP2 Jumper Setting Function JP2 1 2 1 25 V fixed power supply voltage supplied from regulator 1 2V PWRSEL 2 3 External power supply voltage supplied from J5 Note Do not change jumper settings while the M3A HS60 is being operated Be sure to turn off the power of the M3A HS60 before changing jumper settings for all the time Rev 1 00 June 1 2005 3 14 RENESAS REJ11J0002 0100Z 3 3 2 2 Switch and LED Functions The M3A HS60 includes six switches and eight LEDs Figure3 2 3 shows the 560 Switch and LED Pin Assignment Table3 2 3 lists the switches mounted on M3A HS60 Operational Specifications 3 2 2 Switch and LED Functions Top view of the d ON EET OFF component side SW1 LED1 11 LEDO I OM PE14 I LED7 5 l Dm 2 4 15 LEDs Pm PE1 LED2 2 LED3 LED4 1 LEDS O o 9 9 n a 6 6 SW2 SW5 AAAS ON UNI Sue i 2 3 g E YYYY RST NM i MRES Figure3 2 3 M3A HS60 Switch and LED Pin A
47. or J3 Pin Signal Name Pin Signal Name 1 3 3V 2 GND Table3 1 4 Pin Assignments of External Power Supply Connector J5 Pin Signal Name Pin Signal Name 1 1 25V 2 GND Rev 1 00 June 1 2005 3 5 RENESAS REJ11J0002 0100Z 3 3 1 4 Power Supply Connector J4 The 560 includes a power supply connector for the board itself Figure3 1 5 shows a pin assignment of power supply connector Operational Specifications 3 1 4 Power Supply Connector J4 Board edge Board edge TO 1 J4 I 2 view of the Component side Side view Figure3 1 5 Pin Arrangement of Power Supply Connector J4 Table3 1 5 lists pin assignments of power supply connector for M3A HS60 Table3 1 5 Pin Assignments of Power Supply Connector J4 Pin Signal Name Pin Signal Name 1 45V 2 GND Rev 1 00 June 1 2005 RENESAS REJ11J0002 0100Z 3 6 Operational Specifications 3 3 1 5 User I O Connectors J6 J8 3 1 5 User I O Connectors J6 J8 The through hole for the extension connector pin connecting the pins of the on chip peripheral functions such as MTU2 and AD which is suitable for the motor control of SH7206 is mounted on M3A HS60 Figure3 1 6 shows a pin arrangement of extension connector Note Th
48. part of the entire system not singly as a technical content program or algorithm alone to determine in advance whether they are actually suitable for your system Renesas Technology will not assume responsibility for the suitability of said items in systems The products presented herein are not designed or manufactured for use in equipment or systems that are used under conditions where human life is concerned If you plan to use the products presented herein forl special applications such as transportation mobile medical aerospace nuclear control or submarine repeater equipment or systems please consult Renesas Technology or Renesas Technology Sales or other distributors This manual may not be copied or reproduced in whole or part without prior written consent of Renesas Technology For more detailed information or for questions or doubts about this manual please consult Renesas Technology or Renesas Technology Sales or other distributors Revision History SH7206 CPU Board M3A HS60User s Manual Rev Date of Issue Content of Revision Page Points 1 00 June 1 2005 First edition issued Table of Contents rc aA 7 Sees ____ _______ 1 1 Wal Mc M I 1 2 pereo nifl M 1 2 1 3 External Specifications
49. pecifications of 60 Table1 3 1 External Specifications of M3A HS60 No Item Content CPU SH7206 R5S72060 Input XIN clock 16 67MHz Bus clock 66 67MHz max CPU clock 200MHz max Memory Following items of memory are included eSDRAM 32 Mbytes max Following memory selectable by a DIP switch When 16 bit bus width is selected EDS1216AATA 75E x 1 16 Mbytes When 32 bit bus width is selected EDS1216AATA 75E x 2 32 Mbytes Flash memory e M5M29KT331AVP x 1 4Mbytes Data bus width fixed to 16 bits Connectors Extension connector bus I O VCC GND 100 pins User I O connector SH7206 s MTU2 and A D function pins 32 pins Serial port connector D sub 9 pins H UDI connector 36 pins LED POWER LED 1 pc User LED 7 pcs Switches Reset switch 1 pc MRES switch 1 pc NMI switch 1 pc User DIP switch 1 pc 4 poles System setup DIP switch 1 pc 5 poles Package Dimensions Dimensions 100 mm x 100 mm Mounting form 4 layer double side mounted Board configuration 1 board Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 1 Overview 1 4 External View 1 4 External View Figure1 4 1 shows the external view of 560 Figure1 4 1 External View of M3A HS60 Rev 1 00 June 1 2005 REJ11J0002 0100Z RENESAS 1 1 5 M3A HS60 Block Diagram Ov
50. r PFO 7 Extension connector Rev 1 00 June 1 2005 2 11 2 Functional Overview 2 6 Power Supply Circuit 2 6 Power Supply Circuit 60 accepts a 5V power supply as its input and generates 3 3V and 1 25V by using a regulator The regulator used here is an output voltage variable type so that any desired voltage can be generated by changing the resistance value Figure2 6 1 shows a block diagram of power supply circuit in the M3A HS60 Extension connector Extension connector Flash memory External 5V power supply J3 SH7206 External power supply J5 Figure2 6 1 Block Diagram of Power Supply Circuit Rev 1 00 June 1 2005 2 12 TENESAS REJ11J0002 0100Z 2 Functional Overview 2 7 Clock Module 2 7 Clock Module The clock module in the M3A HS60 consists of the following two blocks Output from a oscillator connected to EXTAL of the SH7206 Ceramic resonator connected to EXTAL and XTAL The M3A HS60 has a 16 67MHz oscillator connected Furthermore the bus clock output from the SH7206 is connected to the SDRAM via a damping resistor To connect an extension board to the extension connector we recommend including a clock buffer that contains a PLL to ensure that the board will be supplied with a stable clock signal Figure2 7 1 shows a block diagram of clock module i SH7206 A ay Oscillator R18 CLK
51. se and the technical information contained herein does not implicitly or otherwise grant a license or rights to use the intellectual property or other rights of Renesas Technology Renesas Technology will not assume any responsibility for damage or losses or infringement on the third parties rights arising from the use of product data diagrams tables programs algorithms or example application circuits presented in this manual The product data diagrams tables programs algorithms and all other information presented herein reflect the latest that was available at the time this manual was issued and Renesas Technology reserves the right to change the products or specifications described herein without prior notice When purchasing Renesas Technology semiconductor products please contact Renesas Technology or Renesas Technology Sales or other distributors to obtain the latest information and also keep abreast of the information published at Renesas Technology home page http www renesas com or through other media The information contained herein was carefully prepared and is believed to be correct However Renesas Technology will not assume responsibility for losses that the customers by any possibility may suffer because of erroneous description in this manual To use the technical contents in product data diagrams or tables or the programs or algorithms presented herein for your system please carefully evaluate their suitability as
52. ssignment Table3 2 3 Switches Mounted on M3A HS60 No Function Remarks SW1 System power on off switch SW2 System reset input switch Refer to section 2 8 for details SW3 User DIP switch 4 pole SW3 1 OFF PA18 H ON PA18 L SW3 2 OFF PA19 H ON PA19 L SW3 3 OFF PA24 H ON PA24 L SW3 4 OFF PA25 H ON PA25 L PA18 PA19 PA24 and PA25 are pull upped Refer to section 2 5 for details SW4 System setup DIP switch 5 pole Refer to Table 3 2 4 for function lists SW5 NMI interrupt switch Refer to section 2 9 for details SW6 Manual reset switch Refer to section 2 9 for details Although an internal state of CPU is initialized in manual reset each register of the on chip peripheral module is not initialized Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 3 15 3 Operational Specifications 3 2 2 Switch and LED Functions Table3 2 4 lists the functions of the switch SW4 Initial Setting Table3 2 4 Functions of the Switch SW4 No Setting Function SW4 1 OFF SDRAM SZ H 32 bit access Sets SDRAM bus width SDRAM SZ ON SDRAM_SZ L 16 bit access W4 2 FF MD CLK2 pi Disabl tti S state Disable setting MD CLK2 ON MD CLK2 pin state L clock mode 2 SW4 3 OFF Disable setting Reserved ON This setting should always be ON Reserved SW4 4 OFF Disable setting Disable setting Reserved ON This setting should
53. the internal condition of CPU will be formatted but each register of on chip peripheral module Figure2 9 1 shows a block diagram of interrupt switches SW 5 SW6 MRES switch SH7206 O NMI switch MRES PE13 Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS Figure2 9 1 Block Diagram of Interrupt Switches 2 14 2 2 10 E10A USB Interface Functional Overview 2 10 E10A USB As for the 560 36 pin H UDI connector to connect it with the E10A USB is mounted Figure2 10 1 shows a block diagram of the E10A USB interface GND GND GND GND H UDI connector 36 pin type AUDCK 3 3V o o gt AUDATAO AUDATA1 AUDATA2 AUDATA3 AUDSYNC N C N C TCK TMS TRST TDI TDO GND ASEBRKAK ASEBRK UVCC GND Reset signal pb Figure2 10 1 Block Diagram of the E10A USB Interface SH7206 AUDCK AUDATAO AUDATA1 AUDATA2 AUDATA3 AUDSYNC TCK TMS TRST TD TDO ASEBRKAK ASEBRK Rev 1 00 June 1 2005 REJ11J0002 0100Z TENESAS 2 15 2 Functional Overview 2 10 E10A USB This is a blank page Rev 1 00 June 1 2005 2 16 TENESAS REJ11J0002 0100Z 3 1 Chapter3 Operational Specifications Operational Specifications 3 1 M3A HS60 Connectors Outline 3 1 M3A HS60 Connectors Outline Figure3
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