User`s Manual
Contents
1. CONNECTION ina dida de bee Seale se eae ea E E ad baa 5 2 1 CONNECTOR DIAGRAM ect nose Shans beens bod Ree Wb eels ia 5 2 ANALOG INPUTS sara la tatty awa et nd 5 2 2 SINGELE ENDED Meit bei deg see Pa Rape ta OS tae tes satan 6 23 FLOATING DIFFERENTIAL ious aie asters wees e Shera daa 6 24 FULLY DIFEFERENTIAE e oe Bi atl 6 2 3 DIGITAL OUTPUTS S INPUTS gt casio sad wed eta Sadhana ade Wendie sd RR ane 6 3 REGISTER ARCHITECTURE 0 0 ranner unaren arenaer aaeeea 7 4 PACER COUNTER TIMER CIRCUIT ooon cee n eben een enes 11 5 SPECIFICATIONS hee beak hele oor Reise ee Sea an ea ater A iaa 12 This page is blank 1 INSTALLATION The CIO DAS802 16 boards are an extension of the popular CIO DAS08 architecture The CIO DAS802 16 has a set of registers identical to the CIO DAS08 and an additional set of registers for the extended features Soft ware written for the DASO8 will work without modification but will not provide access to the extended features The connector is nearly identical to the ClIO DAS08 and more closely resembles the CIO DAS08 PGA 1 1 SOFTWARE INSTALLATION Before you open your computer and install the board install and run nstaCal the installation calibration and test utility included with your board InstaCal will guide you through switch and jumper settings for your board Detailed information regarding these settings can be found below Refer to the Software Installation manual for InstaCal instal2. voltage OH 0 4 mA Absolute maximum input voltage Interrupts Interrupt enable Interrupt sources Environmental Operating temperature range Storage temperature range Humidity Source internal 1 MHz oscillator Gate programmable disabled or user connector Gate 2 Output user connector Counter 2 Out and optionally to Counter 1 input software selectable 10 MHz max 30 ns min 50 ns min 50 ns min 50 ns min 0 8V max 2 0V min 0 4V max 3 0V min Input FPGA Output 74LS08 Two ports 3 input and 4 output 0 8V max 2 0V min 0 25V typical 0 4V max 3 4V typical 2 7V min 0 5V 5 5V Jumper selectable levels 2 3 4 5 6 7 or not connected Positive edge triggered Programmable External IR Input XCLK A D End of conversion A D FIFO half full 0 to 50 C 20 to 70 C 0 to 90 non condensing 13 For your notes 14 EC Declaration of Conformity We Measurement Computing Corp declare under sole responsibility that the product CIO DAS802 16 Part Number Description to which this declaration relates meets the essential requirements is in conformity with and CE marking has been applied according to the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents EU EMC Directive 89 336 EEC Essential requirements relating to electromagnetic compatibility EU 55022 Class B Limits and methods of measurements of radio
3. 4 Register Read Functions READ Functions Data Bits Function Register D7 D Ds ba ba Dz MA A A A A Base 0 Low byte read n a ol al EN A al oe Base 4 8254 C T 0 Status Register High byte read Status Register 1 Kaka i a Gain Control Status Base 5 8254 C T 1 Status Register Base 6 8254 C T 2 Status Register Function depends on value of CS0 1 bits in Base 3 sei Se I CS1 0 HCEN GTEN INTE IEOC DTEN CASC Status Register 2 0 0 0 1 1 0 cs1 0 1 1 1D7 1D5 ID4 ID3 ID2 ID1 ID Reg 801 2 802 3 Table 3 5 Bit Definitions AD11 0 R_ Analog data input Read low byte firs Cd DT R State of Digital Trigger 1 Trigger occured Cd Enable Interrupt on FIFO Half Full Req IEOC 1 HCEN must 1 to enable FIFO EOC R End of conversion 1 busy 0 ready FFOV R FIFO Overflow full 1 0 if HCEN 0 Interrupt Source 1 End of Convert 0 Ext CA R __ DigitalInputbits o Internal Time Base 8254 Enable MA2 0_ RW _ Mux address bits Cd OP4 1 W __ Digital Output bits o O R3 0___ RW AD Range bits See Table 3 3 Cd I Asterisk indicates that HCEN is required as a final step to make this bit functional Table 3 6 Special Programming Instructions Reser O Conv Control HCEN is used as a master enable for AD Pacing Set HCEN last by itself i e write 80h set the other bits first Scan Limits Ending channel n can be lower than
4. CIO DAS802 16 User s Manual MEASUREMENT COMPUTING Revision 4 August 2001 LIFETIME WARRANTY Every hardware product manufactured by Measurement Computing Corp is warranted against defects in materials or workmanship for the life of the product to the original purchaser Any products found to be defective will be repaired or replaced promptly LIFETIME HARSH ENVIRONMENT WARRANTY Any Measurement Computing Corp product which is damaged due to misuse may be replaced for only 50 of the current price I O boards face some harsh environments some harsher than the boards are designed to withstand When that happens just return the board with an order for its replacement at only 50 of the list price Measurement Computing Corp does not need to profit from your misfortune By the way we will honor this warranty for any other manufacture s board that we have a replacement for 30 DAY MONEY BACK GUARANTEE Any Measurement Computing Corp product may be returned within 30 days of purchase for a full refund of the price paid for the product being returned If you are not satisfied or chose the wrong product by mistake you do not have to keep it Please call for a RMA number first No credits or returns accepted without a copy of the original invoice Some software products are subject to a repackaging fee These warranties are in lieu of all other warranties expressed or implied including any implied warranty of merchantability or fitnes
5. active when down In Figure 1 1 switches 9 IIttttt ae and 8 are down all others are up Weights 200h and 100h are active A3 08 totaling 300h base address Table 1 1 lists PC I O assignments BASE ADDRESS SWITCH Address 300H shown here Figure 1 1 Base Address Switch Table 1 1 PC I O Assignments HEX FUNCTION HEX FUNCTION RANGE RANGE 000 00F 8237 DMA 1 2C0 2CF EGA 020 021 8259 PIC 1 2D0 2DF EGA 040 043 8253 TIMER 2E0 2E7 GPIB AT 060 063 8255 PPI XT 2E8 2EF SERIAL PORT 060 064 8742 CONTROLLER AT 2F8 2FF SERIAL PORT 070 071 CMOS RAM amp NMI MASK AT 300 30F PROTOTYPE CARD 080 08F DMA PAGE REGISTERS 310 31F PROTOTTYPE CARD 0A0 0A1 8259 PIC 2 AT 320 32F HARD DISK XT 0A0 0AF NMI MASK XT 378 37F PARALLEL PRINTER OCO ODF 8237 2 AT 380 38F SDLC OFO OFF 80287 NUMERIC CO P AT 3A0 3AF SDLC 1F0 1FF HARD DISK AT 3B0 3BB MDA 200 20F GAME CONTROL 3BC 3BF PARALLEL PRINTER 210 21F EXPANSION UNIT XT 3C0 3CF EGA 238 23B_ BUS MOUSE 3D0 3DF CGA 23C 23F ALT BUS MOUSE 3E8 3EF SERIAL PORT 270 27F PARALLEL PRINTER 3F0 3F7 FLOPPY DISK 2B0 2BF EGA 3F8 3FF SERIAL PORT 1 4 DIFFERENTIAL SINGLE ENDED INPUT SELECTION The CIO DAS802 16 has differential analog inputs Differential inputs are 3 wire analog hookups consisting of a signal high signal low and chassis ground The benefits of diffe
6. bove the PC bus Eee ee interface gold pins The factory default setting is that no interrupt level is set re ieee ots IRQ LEVEL the jumper is in the X position Figure 1 4 Interrupt Level Jumper Refer to Table 1 2 for typical IRQ assignments Table 1 2 Hardware Interrupts NAME DESCRIPTION NAME DESCRIPTION NMI PARITY IRQ8 REAL TIME CLOCK AT IRQO TIMER IRQ9 RE DIRECTED TO IRQ2 AT IRQ1 KEYBOARD IRQ10 UNASSIGNED IRQ2 RESERVED XT IRQ11 UNASSIGNED INT 8 15 AT IRQ3 COM OR SDLC IRQ12 UNASSIGNED IRQ4 COM OR SDLC IRQ13 80287 NUMERIC CO P IRQ5 HARD DISK XT IRQ14 HARD DISK LPT AT IRQ6 FLOPPY DISK IRQ15 UNASSIGNED IRQ7 LPT Note IRQ8 15 are AT only 1 7 WAIT STATE A wait state can be enabled on the CIO DAS802 16 by selecting WAIT STATE ON at the jumper provided on the board Enabling the wait state causes the personal computer s bus transfer rate to slow down whenever the CIO DAS802 16 is written to or read from The wait state jumper is provided in you have a computer has an I O bus transfer rate that is too fast for the CIO DAS802 16 If your board were to fail sporadically in random ways try using it with the wait state ON 1 8 INSTALLING THE BOARD IN THE COMPUTER 1 Turn the power off 2 Remove the cover of your computer Be careful not to dislodge any of the cables installed on the boards in your computer as you slide the cover off 3 Locate an empty expan
7. female 37 pin D type connectors such ero TO 36 Ch 1 High Ch 2 Low 17 35 Ch 2 High as those on the C73FF 2 2 foot cable with connectors The con Ch 3 Low 16 34 Ch 3 High i Ch4Low 15 33 Ch 4 High nector pin names Ch High and Ch Low are the differential Ch5 Low 14 ace 5 High inputs Ch 6 Low 13 31 Ch 6 High Ch 7 Low 12 30 Ch 7 High __ LLGND 11 29 PC Bus 5 If frequent changes to signal connections or signal conditioning Digital Out 4 10 28 Digital Gnd Digital Out3 9 27 Digital In 3 is required please refer to the information on the CIO Digital Out2 8 26 Digital In 2 si nt Digital Out 1 7 25 Digital In 1 Trig TERMINAL and ClO MINI37 screw terminal boards If addi Counter Out 6 24 IR input XCLK tional channels or signal conditioning is required refer to the esate ake 23 Gate 2 nter n information on the CIO EXP32 32 channel analog multiplexer Prarie Out 3 5 aa ifi i ifi i Counter O In 2 20 15V From DC DC amplifier Isolation amplifiers may be mounted using the ISO AS meal A oar rom RACKO8 and 5B isolation modules Lo 2 1 ANALOG INPUTS The analog inputs may be configured in three different ways Figure 2 1 37 Pin Analog Connector 1 True differential inputs For sources with a separate ground common to the PC 2 Pseudo differential inputs used for floating sources has noise rejection capability 3 Single ended inputs Also used for floating sources The manner of configuring the analog inputs and t
8. he schematic of those configurations is explained earlier in the manual This section covers the implications of a given connection and shows how to make that connection WARNING PLEASE READ Measure the voltage potential difference between the ground signal at the signal source and the PC Use a volt meter and place the red probe on the PC ground and the black probe on the signal ground If there is more the 10 volts do not connect the board to this signal source because you will not be able to make any reading If it is more than 30 volts DO NOT comnect this signal to the board because it will damage the board and possibly the computer 2 2 SINGLE ENDED A single ended input is two wires connected to the board a channel high CH High and a Low Level Ground LLGND The LLGND signal must be the same ground the PC is on The CH High is the voltage signal source Single ended mode is selected by closing a switch 2 3 FLOATING DIFFERENTIAL A floating differential input is two wires from the signal source and a 10K ground reference resistor installed at the board input The two signals from the signal source are Signal High CH High and Signal Low CH Low The reference resistor is connected between the CH Low and LLGND pins This is done with the SIP resistor pack A floating differential hookup is useful when the signal source is floating with respect to ground such as a bat tery WARNING Check it with a voltmeter that the signal
9. interference characteristics of information technology equipment EN 50082 1 EC generic immunity requirements IEC 801 2 Electrostatic discharge requirements for industrial process measurement and control equipment IEC 801 3 Radiated electromagnetic field requirements for industrial process measurements and control equipment IEC 801 4 Electrically fast transients for industrial process measurement and control equipment Carl Haapaoja Director of Quality Assurance Measurement Computing Corporation 16 Commerce Boulevard Middleboro Massachusetts 02346 508 946 5100 Fax 508 946 9500 E mail info measurementcomputing com www measurementcomputing com
10. lation instructions 1 2 INSTALLATION SWITCH SETTINGS There are two banks of switches and two jumpers to set on the CIO DAS802 16 before installing your board into your computer 1 BASE ADDRESS SWITCH A base address must be chosen and selected via switches 2 INPUT SELECT SWITCHES Analog inputs are differential or single ended You may choose either on a channel by channel basis The set of DIP switches on the board labeled S2 0 through 7 correspond to the channels 0 to 7 of the analog inputs 3 INTERRUPT SELECT JUMPER In order to take advantage of high speed transfers you must provide the board with an interrupt that is not used by other devices in your computer Use the IR jumper to select an interrupt level between 2 and 7 or to disable interrupts X 4 WAIT STATE JUMPER A wait state jumper allows you to slow down a potentially too fast computer bus but we have not seen the need for it yet Set jumper WS1 to ON to enable wait states 1 3 BASE ADDRESS The base address of the CIO DAS802 16 is set by switching a bank of DIP switches on the board This bank of switches is labeled ADDRESS and numbered 9 to 3 Refer to the Software Installation Manual for instructions for using InstaCal as an aid in setting the base address switches 987 6 5 4 3 SW HEX Ignore the word ON and the numbers printed on the switch pe 100 The switch works by adding up the weights of individual switches to make Ae a a base address A switch is
11. n use by the A D are available for other tasks but are limited to some extent by the wiring and access to I O pins The first counter CTRO is fully avail able for your use Figure 4 1 is a simplified block diagram of the 82C54 and related logic functions 5VDC ALL 4 10K CTR 0 OUT q airen 22 GATE 1 GATE amp TRIGGER LOGIC of CTR 1 OUT 10 MHZ CRYSTAL DIVIDE BY OSCILLATOR 10 CASCADE CONTROL LOGIC DIN 1 TRIG START CONVERT INT INPUT XCLK IRQ lt _ GATE amp TRIGGER LOGIC Figure 4 1 Pacer Counter Timer Block Diagram 11 5 SPECIFICATIONS Power consumption 5V quiescent Analog input section A D converter type Resolution Number of channels Input ranges Polarity A D pacing A D Trigger sources Data transfer Channel configuration DMA A D conversion time Throughput Accuracy Differential Linearity error Integral Linearity error No missing codes guaranteed Gain drift A D specs Zero drift A D specs Common Mode Range CMRR 60 Hz Input leakage current 25 deg C Input impedance Absolute maximum input voltage 430 mA typical 675 mA max AD7805PB Successive Approximation 16 bits 8 10V 5V 2 5V 1 25V 0 to 10V 0 to 5V 0 to 2 5V 0 to 1 25V fully programmable Unipolar Bipolar software selectable 11 ms max switching delay Programmable internal counter o
12. r external source IR Input XCLK falling edge or software polled External hardware Digital In 1 Trig rising edge Interrupt or software polled from 256 sample FIFO buffer Differential or pseudo differential with installation of a SIP resistor or single ended switch selectable for each channel None 10 us including signal acquisition time 100 kHz 0 0015 of reading 1 5 LSB 1 5 1 LSB max 1 5 LSB max 16 bits 10 ppm C 5 ppm C 10V 90 dB min 100 nA 10 Mohms 35V 12 Counter section Counter type Configuration 82C54 3 down counters 16 bit resolution Counter 0 independent user counter Source external user connector Counter 0 In Gate external user connector Gate 0 Output user connector Counter 0 Out Counter 1 ADC Pacer Lower Divider or independent user counter Source user connector Counter 1 In and optionally Counter Out selectable by software Gate programmable disabled or user connector Gate 1 Output user connector Counter 1 Out and optionally to A D start convert software selectable Counter 2 ADC Pacer Upper Divider Clock input frequency High pulse width clock input Low pulse width clock input Gate width high Gate width low Input low voltage Input high voltage Output low voltage Output high voltage Digital I O section Digital type Configuration Input low voltage Input high voltage Output low voltage IOL 8 mA Output high
13. rential inputs are the ability to reject noise which affects both signal high and low and the ability to compensate for ground loops or potentials between signal low and chassis ground Although differential inputs are often preferable to single ended inputs there are occasions when the floating nature of a differential input can confound attempts to make a reading In such cases the CIO DAS802 16 inputs are converted to single ended or modified differential The CIO EXP16 and CIO EXP32 were designed to interface to a single ended input Failure to set the switches to single ended when an EXP is connected will result in floating unstable readings from the EXP The analog inputs of the CIO DAS802 16 may be set up as single ended or differential There are two ways to select between them The first method of selecting between the single ended and differential inputs is via a set of eight switches located near the connector and labeled 0 7 in white lettering on the board In the down or off position the input associated with that switch is in differential mode In the up or on position the input associated with that switch is single ended Channel 0 High To A D Circuit Low Level Ground Switch for Differential Open Single Ended Closed Channel 0 Low Figure 1 2 Differential to Single Ended Switching Figure 1 2 is a diagram of one analog input and the single ended differential swi
14. s for a particular application The remedies provided herein are the buyer s sole and exclusive remedies Neither Measurement Computing Corp nor its employees shall be liable for any direct or indirect special incidental or consequential damage arising from the use of its products even if Measurement Computing Corp has been notified in advance of the possibility of such damages MEGA FIFO the CIO prefix to data acquisition board model numbers the PCM prefix to data acquisition board model numbers PCM DAS08 PCM D24C3 PCM DACO2 PCM COM422 PCM COM485 PCM DMM PCM DAS16D 12 PCM DAS16S 12 PCM DAS16D 16 PCM DAS16S 16 PCI DAS6402 16 Universal Library InstaCal Harsh Environment Warranty and Measurement Computing Corp are registered trademarks of Measurement Computing Corp IBM PC and PC AT are trademarks of International Business Machines Corp Windows is a trademark of Microsoft Corp All other trademarks are the property of their respective owners Information furnished by Measurement Computing Corp is believed to be accurate and reliable However no responsibility is assumed by Measurement Computing Corp neither for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or copyrights of Measurement Computing Corp All rights reserved No part of this publication may be reproduced stored in a retrieval system or
15. sion slot in your computer 4 Insert and push the board firmly down into the expansion bus connector If it is not seated fully it may fail to work and could short circuit the PC bus power onto a PC bus signal This could damage the motherboard in your PC as well as the board 1 9 CALIBRATION AND TEST The CIO DAS802 16 is supplied with InstaCal software for calibration and test If you have not done so install this software in order to test your board and when necessary calibrate it Every board is fully tested and calibrated before shipment For normal environments a calibration interval of 6 months to one year is recommended If frequent variations in temperature or humidity are common re calibrate at least once every three months It takes less than 30 minutes to calibrate the CIO DAS802 16 2 SIGNAL CONNECTIONS Signal connection can be one of the most challenging aspects of applying a data acquisition board In addition to just plain wrong connection which is the most common cause of customer calls to tech support is the possibility of ground loops floating signal sources and excessive common mode voltage Please follow the examples shown here and use care with grounding between the PC and the signal source Refer to Figure 2 1 2 1 CONNECTOR DIAGRAM Lo The analog connector is a male 37 pin D type connector acces sible from the rear of the PC through the expansion backplate ChOLow 19 37 Ch 0 High The connector accepts
16. so are used to control external EXP boards all four outputs and to trigger and gate A D con versions Digital In 1 3 REGISTER ARCHITECTURE All of the programmable functions of the CIO DAS802 16 are accessible through the control and data registers The CIO DAS802 16 is controlled and monitored by writing to and reading from 16 consecutive 8 bit I O addresses The first address or BASE ADDRESS is determined by setting a bank of switches on the board Register manipulation is best left to experienced programmers as most of the possible functions are implemented in easy to use Universal Library routines Summaries of the registers and their read and write functions are given on Tables 3 1 through 3 6 Table 3 1 Register Write Functions Write Functions Data Bits Function z Base 2 Special Function Depends on value of CS0 1 E E SEGA rer oor A A gt PA EES ATEO AAA TEA eee a ry 8254 Counter Timer Control Register Register Table 3 2 Control Register Select Coding oS 0 ControrReg 7 Status Register 2_ 0 Scan Limis Reg Status Register 2_ ID Register Table 3 3 Range Gain Select Codes R2 Ri Ro CIO DAS802 16 o o 0 Bip istov g 1 o 0 Unis 0 to 10V__ g 1 o 1 O Bipissv g 2 lt o0 1 Uni Otos5v _ g 2 i o o Bip 2 5V_ g 4 o Uni Oto2 5V g 4 1 1 o Bip 1 25V g 8 Uni O to 1 25V g 8 Table 3
17. source really floating before risking the board and PC 2 4 FULLY DIFFERENTIAL A differential signal has three wires from the signal source There is Signal High CH High Signal Low CH Low and Signal Ground LLGND A differential connection allows you to connect the board to a signal source with a ground that is different from the PC ground but less than 10V difference and still make a true measurement of the signal between CH High and CH Low EXAMPLE A laboratory instrument with its own wall plug There are sometimes voltage differences in wall grounds between outlets 2 5 DIGITAL OUTPUTS amp INPUTS All the digital inputs and outputs are TTL level TTL is an electronics industry term short for Transistor Tran sistor Logic with describes a standard for digital signals which are either at TTL low or TTL high levels which are detected by all other TTL devices For a listing of the TTL level specifications for these digital lines please see the specifications at the end of this manual There are four digital outputs and three digital inputs The digital outputs are controlled by a register on the board and are updated each time the register is written to The digital inputs are buffered by a register on the board and each time the register is read from the current high low state of the digital I O lines is obtained The lines are pulled high so a logical one is read when no signal is connected to an input The digital lines al
18. starting channel m Select Start and End Channel before setting EACS ro Only the 1st two bits are needed for software the upper six are for compatibility with KMB software ID 1 0 0 0 DAS800 KMB only 0 1 reserved 1 0 DAS801 1 1 DAS802 Gain Range Range bits can be written only when bit 7 is 0 CS1 0 bits can be written only when bit 7 is 1 Not all of the CIO DAS08 PGA gains are supported Operating Modes Pacing CTR2 divides the 1 MHz time base AD converts when CTR2 counts to zero Cascade CTR1 decrements each time CTR2 counts to zero AD converts when CTR1 counts to zero Triggering Requires DTEN 1 GTEN 0 Gate Requires DTEN 1 GTEN 0 INT XCLK External Interrupt and External Pacer Clock are mutually exclusive External Interrupt is rising edge External Pacer is falling edge 10 4 PACER COUNTER TIMER CIRCUIT There is an 82C54 counter timer on board which can be used to e Pace analog conversions e Measure frequency e Count events e Precisely time intervals The software to support the timer is in the Universal Library The connections to the hardware are explained here For detailed information on the 82C54 registers please refer to the Intel or AMD data sheet for this part if you wish to program the 82C54 registers directly The 82C54 contains three counters each 16 bits wide Of the three counters two are dedicated to the pacing of analog to digital conversions These two CTR1 and CTR2 when not i
19. tch It shows the switch in the Open position so the input mode is differential The second method of converting the inputs to single ended is to install a SIP resistor pack at position RN2 This package of 10K resistors provides a reference to ground for each of the eight Low Input lines This type of input OoOO 2 vr behaves like a single ended input in that there is a reference to ground and floating sources may be measured and it also To A D is able to reject a certain amount of noise Circuit Figure 1 3 shows an analog input line with the SIP resistor installed Low Level Ground a area Note that the SIP resistor is installed to all eight lines so Resistor SIP 1 none of the analog inputs are fully differential after the SIP Single Ended RN2 Installed is installed Figure 1 3 Differential to Single Ended If you intend to use an EXP board with the CIO DAS802 16 do not install the SIP resistor but you should set the SE DI switch to ON for both the EXP channel and the CJC channel 1 5 INTERRUPT LEVEL SELECT The interrupt jumper need only be set if the software you are using requires it The Universal Library and other programs which take advantage of the REP INSW high speed transfer capability of the board require and interrupt If you do set the interrupt jumper please check 2 3 4 5 6 7 X your PC s current configuration for interrupt conflicts Benne There is a jumper block on the CIO DAS802 16 located just a
20. transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without the prior written permission of Measurement Computing Corp Notice Measurement Computing Corp does not authorize any Measurement Computing Corp product for use in life support systems and or devices without the written approval of the President of Measurement Computing Corp Life support devices systems are devices or systems which a are intended for surgical implantation into the body or b support or sustain life and whose failure to perform can be reasonably expected to result in injury Measurement Computing Corp products are not designed with the components required and are not subject to the testing required to ensure a level of reliability suitable for the treatment and diagnosis of people Copyright 2001 Measurement Computing Corp HM CIO DAS802_16 lwp Table of Contents 1 INSTALLATION ta da Seen 1 1 1 SOFTWARE INSTALEATION ordii oa dial ee oe BA aaa eae ac Hah BA eee we 1 1 2 INSTALLATION SWITCH SETTINGS 0 0c cee eee eens 1 T3 BASE ADDRESS visado ad nts dave aie ato es 1 1 4 DIFFERENTIAL SINGLE ENDED INPUT SELECTION 0 0 0 0 ce eee eee eee 2 IS INTERRUPT CLEVE SELECE cnt iat os ek la a ale dd ec 3 L WALT STATES a AS a eee he Reed ete 4 1 8 INSTALLING THE BOARD IN THE COMPUTER _ 0 cece eee eee eee 4 F9 CALIBRATION AND TEST lisas ted olga ee ties Whale tes E Asa 4 2 SIGNAL
Download Pdf Manuals
Related Search