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Series Six Bus Controller User`s Manual, GFK-0171B

1. BUS CONTROLLER MEMORY a42892 INPUT SHARED B C INPUTS ro lt 27 Ram K RaM K FROM CPU MEMORY MEMORY ANALOG BLOCK TRANSFER OCCURS TRANSFER OF A SINGLE VALUE DURING VO SCAN OCCURS DURING PROGRAMMER WINDOW The Bus Controller begins organizing input data from the blocks listed above at the start of the programmer window portion of the CPU sweep and continues until all the data has been organized If the program includes DO I O instructions to obtain the latest data from the block or if the program is very short program logic should be used to extend the time of the programmer window This will allow the Bus Controller time to complete the task before the 1 0 update begins 3 10 Interfacing Genius I O Blocks to the Series Six PLC GFK 0171 Logic to Extend the Programmer Window To find the total time needed to update inputs during the programmer window find the contributions of any analog RTD Thermocouple High speed Counter PowerTRAC or Power Monitor Blocks on the bus that are assigned I O Reference Numbers Number of analog RTD Thermocouple and x 0 057mS mS PowerTRAC blocks Number of High speed Counters x 0 422mS mS Number of Power Monitor Blocks x 0 503mS ms total mS Subtract the programmer window time 0 311mS mS delay required To extend the programmer window add one of the following commands to the program before any I O update either normal I O update or DO J O instructions
2. B I un vl iid owed e 3 E o E E a T E xz ac p E 9 3 OD pe E oO y EL f 4 D e HURTO s eA 3 BE REE i 3 E Q O gt E y fa Age sw a E 8 x B D D Ey E Y 2 CO p 0 e i2 E V Y ct Es o 2 Q S o E gt O u Q E t 2 00 vx D E A SS ob 3 3 9 mu 48 E gt E 5 2 930 y 3 od z D am E ob 2 As a A 0 A O Q Qa bb o O HO my 2 e iu fl fa Oh d 9 v a Y a c m 2 gt LEL 0 ba gs 3580902 EG IBIS S El gt prm Y VE S o NIYIN o Bon E Y ou 2 ii rad f Q x EQ D i Q Ly Cc 9 Qm a 20 i alles E o EB AN 9 ESSE a SISS Sol 3 o ER a 5 BELA So 6 EEN ET SITES amp o B8 2 A 2020377 y q a e A Q 3 E v ARRQ aa 9 uma Hos aa eo mi en eoo 7 5 IS AS gy AO 2 6 Bee ellas 8 Sag B ge m 5 n n w el a WA A 4 y 20 OQ 38 z 2 65 Y amp Ou Y 3 N E BRS g CE E 9 312 as o 9 K Fx m ha 00 z H O GMS E 3 a sic Sa 2 nas i Ere S y 2 ba d y Q F or H 4pASBS 598 Hlase 3 35358 E LEE 3 E Qed Q un gt y OO Mi ann 0 2 Q UC UN ry p NM e aOR a s alzoao g co HD o n pO c n 9 E pad Bb a E SSX 2 q s V r 5 pal N A ES e qQ oul n U e l i enga El PER HL nx A7 PEI a b O b S e lI 1 4 Y O c bD De o T Q y d lt gt yO A m o bL Q ea e Y x dd cr d 7 A 9 sz A Po V VES x c d i 3 7 907 A Y pn o ease li 25 e 3 Y amp Sag 8 g A SugB5o q E gt s 8 s
3. LU wed 3 mest N C 7 OO d no c2 p e m e e pn AA c AG b b B b Det QRO KU g N VWV O MY E oO yd pl wem ped et el ved gt e O O O amp p AS AS A404 AZ AG AG AS Appendix B Bus Controller Compatibility This manual describes the operation and use of Phase B Genius I O Bus Controllers Basic differences between Phase B Bus Controllers and the earlier Phase A versions are explained below Feature Phase A Bus Controller Phase B Bus Controller Power Supply and 5V and 12V req CPU rack or High 5 volts only May use High Capacity I O rack regular Rack Requirement Capacity I O Rack I O rack or CPU rack Bus Scan Time Less than 250mS Less than 400mS Multiple Bus Not supported Supported Controllers Bus Controller Bus Controller outputs can be disabled allowing it to monitor inputs and diagnostics from other devices on the bus used as a Monitor Not supported Baud Rate Uses 153 6 Kbaud only Selectable baud rates 153 6 Kbaud standard 153 6 Kbaud extended 76 8 Kbaud or 38 4 Kbaud Permits longer cables and better noise immunity Detection of Device Number Conflict Duplicate Device Numbers not de tected Tests for another device on bus with the same Device Number as the Bus Controller If there is a Device Number Number conflict both LEDs on the Bus Control ler will flash in unison The conflicting Bus Controller must be
4. Interfacing Genius I O Blocks to the Series Six PLC 3 3 GFK 0171 The following example shows a non Expanded I O system with two Bus Controllers on the same I O chain CPU 240730 1 0 RACK 1 0 RACK A eee er fa UR HAE UP am Epome BUS 1 BUS 2 Lnd mmm 5 1 1 Lol BLOCK TYPE INPUT REFERENCES The first Bus Controller is assigned to references 1 through 48 Block 1 on bus 1 is a discrete 8 circuit block with inputs only It is assigned to Reference Number 0049 reserving 8 input references 10049 10056 Because the block is configured for inputs only outputs 00049 00056 are not reserved they can be used by other blocks On the same bus block 2 is a discrete 16 circuit block configured to use outputs only Reference Number 0049 can also be assigned to that block The block will use 16 references O0049 O0064 in the output table Depending on the actual I O mix some input or output references will not be used for physical devices References not used by I O on a block such as inputs 10057 10064 in this example are not available for use by other physical I O However they can be used for logical coils in the program Block 5 on the same bus is a discrete 8 circuit block that uses 5 inputs and 3 outputs Reference Number 0065 is assigned to the block Because it is a combination block it needs equivalent references in both the input table 10065 10072 and the output table O0065 O0072 However only 5 inp
5. 5 18 Programming Window Commands GFK 0171 Using DO I O to Update Analog Inputs If the program must know the most current values of analog inputs as the logic executes use a Read Analog Inputs command not a DO I O instruction DO I O reads input values from shared RAM Since the Bus Controller updates shared RAM only once per CPU sweep multiple DO I O instructions in the same program sweep will return the same values each time PROGRAM 242893 READ ANALOG SHARED B C ALL INPUTS RAM RAM FROM MEMORY MEMOR BLOCKS ONE NEW VALUE LATEST VALUE EACH CPU FOR EACH CHANNEL SWEEP EACH BUS SCAN Example program logic for Read Analog Inputs is shown on the next page Command Block for the Read Analog Inputs Command Format of the Command Block for the Read Analog Inputs command is Register 1 Bus Controller Reference Number plus 1000 for a DPREQ Register 2 Command number 7 Register 3 Status Code supplied by the Bus Controller Register 4 Ten bit Reference Number of the device whose input data will be read Register 5 Pointer to a register address where returned analog data will be placed For analog blocks the Bus Controller provides input values received from the block to the PLC in the following format register numbers are relative Register 1 Input channel 1 16 bit engineering units Register 2 Input channel 2 16 bit engineering units Register 3 Input channel 3 16 bit eng
6. 3 read the Global Data address of another CPU on the same bus This command is immediate if sent to the target Bus Controller It is non immediate if sent to a block or another bus interface module elsewhere on the bus Command Block for the Read Status Table I O Reference Command Command Block format for the Read Status Table I O Reference Command is Register 1 Bus Controller Reference Number plus 1000 for a DPREQ Register 2 Command number 9 Register 3 Status Code supplied by the Bus Controller Register 4 5 bit Device Number of device to be read 0 31 Register 5 Pointer to pair of registers where the I O reference information from the device is to be written in the CPU Data Returned by a Read Status Table I O Reference Command to an I O Block If register 4 contains the Device Number of an I O block the following data about the block is returned to the CPU Register 1 10 bit Status Table Reference of block requested above Register 2 bits 0 1 Block I O Configuration 1 Inputs only 2 Outputs only 3 z I O combination bits 2 15 not used zero Data Returned by a Read Status Table I O Reference Command to a Bus Controller If register 4 contains the Device Number of a Bus Controller or any other Global Data device the following data about the device is returned to the CPU Register 1 starting address of Global Data for a Global Data device on the same bus FFFF no Global Data Register 2 3 Any devic
7. GFK 0171 Disabling Outputs at Powerup Under certain conditions it is possible that the Bus Controller may begin transmitting output data before the CPU program has set up the desired output values Setting a Bus Controller DIP switch see below prevents possibly incorrect operation of outputs at powerup This requires the use of program logic to enable the outputs after correct system operation is assured To do this 1 Set Bus Controller DIP switch 4 at position U16 to disable outputs when the Bus Controller is powered up a42193 Disable Outputs Enable Outputs not used x open off ol L 2 At a subsequent time determined as suitable by the application enable outputs to some or all of the blocks under control of the program If switch 4 is open the Bus Controller will hold off output transmissions until it completes its powerup sequence If the PLC is stopped because the Bus Controller has powered down which is typical it must execute two sweeps in Run Disabled mode While the PLC is in Run Disabled mode the Bus Controller will continue to withhold output transmissions These two sweeps typically permit the Bus Controller to be updated with correct outputs for the blocks However this does depend on the relative lengths of the PLC sweeps and the Genius bus scans Switch 4 only determines what happens after the Bus Controller is powered up It has no effect if the Bus Controller is in a rack that is powered up and the PL
8. In the other CPU use logic to open communica tion between the CPU and its bus interface mod ule Use DPREQ or WINDOW instruction to send Write Point Datagram Read the Global Data address of another inter face module on the bus Handling Global Data transfer up to 128 bytes of data between CPUs using Global Data Send up to 128 bytes of data to a Bus Controller or PCIM as a Datagram Read up to 128 bytes of data from another CPU on the bus as a Datagram Set or clear up to 16 individual data bits in another CPU Chapter 2 2 1 Setup and Installation GFK 0171 Before a Bus Controller is installed its on board and backplane DIP switches can be set to select the features described below The board is shipped from the factory with default settings A discussion of each setting follows CPU SHUTDOWN MODE SWITCH 1 BAUD RATE SWITCHES 2 3 DEVICE NUMBER SWITCHES 4 8 DISABLE OUTPUTS SELECT TERMINATING IMPEDANCE EXPANDED ADDRESSING SWITCH 4 CHANNEL NUMBER SWITCHES 1 3 Terminating impedance for the communications bus If the Bus Controller is not at the end of the bus do not change the default switch setting CPU shutdown mode If program execution should continue in the event of Bus Controller failure do not change this Baud rate The default setting is 153 6 Kbaud The Bus Controller s baud rate must match that of
9. T It is possible for several immediate window commands to execute during the same CPU sweep e A Non immediate command is not completed during the same CPU Bus Controller window When a Non immediate command is accepted the CPU opens a window to the Bus Controller and sets the Status Code to 1 In Progress If the command cannot be executed immediately the Bus Controller puts the command into a queue and the window closes While the window 1s closed the Bus Controller will not accept any more non immediate window commands for the Bus Controller After the Bus Controller has finished processing the command for example sending configuration data to a block or reading configuration data from a block it changes the status to complete during the next available window to that Bus Controller This probably will not occur during the same CPU sweep In the interim the status indicates in progress If the processing fails to complete perhaps due to a broken cable the Bus Controller sets the status to 20 transfer error 5 6 Programming Window Commands GFK 0171 The table below shows how long the CPU Bus Controller window may be open for both immediate and non immediate commands Immediate Window Time Immediate for a Bus Window Time mcns Kor a Peck Controller Idle Read Configuration Write Configuration Read Diagnostics Read Analog Inputs Read Status Table Reference Switch
10. These registers will show the fault type for each of the 19 faults Programming for Diagnostics Using Bus Controller Input References 8 21 GFK 0171 If a fault occurs rung 6 creates another table of 19 registers Each register in this table can contain Bus Controller input references 17 32 for one fault These references indicate the location of an I O circuit fault lt lt RUNG 6 gt gt KEKKKKKKKKKEKKKKKKKKKKKKKKEKKKEKKKKKEKKKKKKKKKKKKEKKKKKKKKKKKKKK KKK KKK KKK KRKKKK Registers 121 through 139 store Input Status bytes 3 and 4 from the Bus Controller for each fault that occurs This is the circuit reference number in binary e e e e ee e ce oe ee e ee ke e cese e ee ecce e ce eoe oe se ce ce e e ce ce e e ee ce ce ce e de cec e de de e e ce ce ce de e de ee e de de e KK KKK KKK A FAULT CIRCUIT HAS REF OCCURRD STORAGE 00909 10273 R00120 Const SRC ADD TO TOP LIST LEN 019 Now the assignment of register memory is R100 pointer for R101 R119 R101 fault 1 fault type R102 fault 2 fault type R103 fault 3 fault type R119 fault 19 fault type R120 pointer for R121 R139 R121 fault 1 location if I O circuit fault R122 fault 2 location if I O circuit fault R123 fault 3 location if I O circuit fault R139 fault 19 location if I O circuit fault O ID ee ee mes mm Laa Na a a gt Oe Tl m Dives linme Trina D oxfaeaenae O hide Progr amming 10r
11. an Q GIAN e e S gt an gt O fed 4 9 ade E j ad QR E BHBH Pp S858 8 8 eee sess 2 Os Y d 4 c r D O 0 0D ms sm M o Sg GOA Sleee se Be BE ES nO 4 882822BB O eB SIY e D z B B ry 2 rg A oO 2 A A t A O O m H A Q Q is e e E A EOL sag 4 e jus d d 3 00x uvwo A lt CI A 9 gt o w o b z Peps oge E5 88883 Pee wes CTE RS AAA y gt QO ie AL a aaao do TS on Mls HEB SS B S Y s a b E amp E B B e B B Q DSS SER 234343439385 eb i QR Gun ete z SAS Oc D 3 G Q e vtr S3uUE Ex A dq z HIRA Cc 4 oe vi i a 3 a Q te S 5 Ps so amp AES 2 mi o 7 O eh S IDB H E Pie 22738 420 4 os amp llo n lt 3sQ mhe w Chapter 1 0 10 1 Troubleshooting GFK 0171 This chapter lists errors that might occur and suggests corrective actions you can take Errors are most likely when a new system is being started up They are often caused by mistakes in cabling or field wiring or by faulty logic in the CPU s application program If problems occur consult the troubleshooting information in this chapter It will help you isolate any problem that originates in a Bus Controller If these steps do not pinpoint the problem the cause may lie in the CPU or programmer Y ou should refer to chapter 5 of the Series Six Plus Installation and Maintenance Manual GEK 96602 for further troubleshooting information If you have questions that are not answered in thi
12. pa O o 9 7 O 0 c e e v OIA A EXC D e b e a e2 gt ea 6 med un e e 2 Se N se i CR O e US amp BSdog d z 3 c S g 20 OL 3 Husos oo 4 O 90 f 0 Un e El c 5 Y o oO ASIS 48 E yi 1 7 z O om Ls t d 2 2020 g 2 aj hes 3 E dozgz 82 B i O gt oles s Qd 5 B eS 7 oS So 3 ml OZ T ADe 3 e 4 pr Om F2 f FL FL O ed a A S c Qala a a d o o os m En 5 ZA ICI a A m A i 6 0 6 i 0 zz 2 GBRE E E z e 3 A ADA a QA S oc eoooo o c c p Qe ei n nd c e O o Y 5 281 TE i Ey 9 P m a 2 bb 3 e a Omo AIE g3 8 BO A y DO D B4 X A O 4 3 ed bb a OE Q 4 4 e t SUM ox e 6 EST OS E O A on 2 Sah 283 aH y m5 oe c Ei C2 ES Ag zr EH O bi A E Od ES r lt XE En ci n fx E v gt gj O O Ee i ye O p T S v BAS o e D e o oe O 858 gt ac Q a edd md E amp lt ga gt YN m YD O a dc ey o Un EE e e E Cj t NC E E 60 a e goi uN 2 v ei O 3 0 v eco gt o S gt p R te A ed FO g O Or wd pr a lt E 2 e th 9 0 y po a o E emo E E Eb e i 2 gt c ag CA e S pe oe 23 g vd 2 8 X8 y H 8 Q E o vi Y f n E e s og mgs S Re pr hao Be wa 22 y 4 2 D bh t D e Y o e o0 gQ 00 Ou ge Ske Bs oS aAa o DS h e ucc O 07327398 lt 5 O hl A 9 5 d V SLZ Nu g y PG E Bm m Q 04 NO M2 a O N S oo w vnl
13. the other devices on the bus Selection of a baud rate is based on cable length and type and the use of phase A devices on the bus Device Number The default Device Number is 31 Unless there is another bus interface module on the same bus this number need not be changed Expanded I O addressing If the PLC system uses Normal I O addressing or if the Bus Controller will be installed downstream of an I O Transmitter module that will select Expanded I O addressing do not change the default setting Outputs disabled or enabled when Bus Controller powers up By default outputs are automati cally transmitted to the blocks when the Bus Controller powers up with the PLC in the Run Enable mode This can be changed to disable outputs at powerup The program can subsequently enable these outputs Refer to the descriptions that follow to determine whether the defaults should be changed A sample configuration worksheet form is provided at the end of this chapter A copy of this worksheet can be used to record the configuration of the Bus Controller In addition to the on board switch settings a Reference Number for the Bus Controller is selected using DIP switches on the rack backplane 2 2 Setup and Installation GFK 0171 Selecting Terminating Impedance Each Genius communications bus must be terminated at both ends by its characteristic impedance A jumper on the Bus Controller is used to select impedance Zar Edr This position
14. 2 explains how to set the on board and backplane DIP switches when installing a Bus Controller Chapter 3 Using Genius I O with the Series Six PLC Chapter 3 includes information about assigning Reference Numbers and describes special programming for analog blocks Chapter 4 Automatic Diagnostics and Fault Clearing Chapter 4 explains how the Expanded Functions of the Series Six Plus PLC can automatically capture display and clear faults Chapter 5 Programming Window Commands Chapter 5 explains optional programming to read or write configuration data read diagnostics read analog inputs read a status table address or switch a BSM Chapter 6 Datagrams Chapter 6 explains optional programming for Datagram and Global Data communications between devices on the bus Chapter 7 Global Data Chapter 7 explains optional programming for Global Data communications Chapter 8 Programming for Diagnostics using the Bus Controller Input References Chapter 8 describes optional programming to obtain diagnostics information from the Bus Controller Chapter 9 Programming Commands to I O Blocks using the Bus Controller Output References Chapter 9 describes optional programming to clear faults Pulse Test discrete outputs or selectively disable outputs Chapter 10 Troubleshooting Chapter 10 lists errors that might occur and suggests corrective actions Appendix A Expanded I O Addressing Appendix A shows how Expanded I O is mapped for C
15. 3 94 9 amp 2 AY TEE So E oo 9 od Os 8 LEE I res sa i wo U re med s 5 bf e A e d Q 3 Ad w Q t A 9g o G d S o E g B esq og t D wq 9 4928 E 254 8 Se FB gt BE Bued 28 TEETE THERET pis S Ss aa E um ids Boo sm reese p Uim A oo GG Hu 2 or D ex si SEN Sn lt a Q amp Bo 5 Im g Hu eg o Y SUE Daga E he DEl 9 m U gd n E Q e OCC H E SaR A Pl 2 eS 35 Tc o gg E EYS Fa do dog S g 283 Y mA qm zi ey O Ne e G oO o0 0 2 T a an o r3 4 O T D 2 p H E a F B B 2 Q E ag 5 0 m s t Buda p 9 a O ae co o B c xs zi a a an d 9 y 4 d E gt i O y A s U 4 o S g Q 5008 i E A 2 5 SH B E y oe E 8 25 A S r y a s la mal TELA amp 4 E S RI E a gt 3 3 D P1 oc B4 y a an a gt 3 330 O e ba 3 Q QA Oo a AQ A V o e E La eo S 53353 Sog A E DT 9 utt r Sag AE coma a 2 Hoe rl E 8955 ME AoA O o D ES E E oH 9 4 Programming Commands to I O Blocks Using the Bus Controller Output References GFK 0171 Clearing all Faults on the Bus To have the program automatically clear all faults on the bus and all circuit faults buffered in the Bus Controller set bit 2 for one CPU sweep The bit must transition from 0 to 1 to clear faults 4 3 2 1 bytes 2 bits B bit 2 Clear All Faults The Clear All Faults command causes the blocks to attempt to clear their faults once If a fau
16. 585 593 601 609 617 625 633 641 649 657 665 End 512 520 528 536 544 552 560 568 576 584 592 600 608 616 624 632 640 648 656 664 672 INPUTS USED OUTPUTS USED Ref Start 673 681 689 697 705 713 721 729 737 745 753 761 769 777 785 793 801 809 817 825 833 End 680 688 696 704 712 720 728 736 744 752 760 768 776 784 792 800 808 816 824 832 840 INPUTS USED OUTPUTS USED Ref Start 841 849 857 865 973 881 889 897 905 913 921 929 937 945 953 961 969 977 985 993 End 848 856 864 872 880 888 896 904 912 920 928 936 944 952 960 968 976 984 992 1000 INPUTS USED OUTPUTS USED 3 6 Interfacing Genius I O Blocks to the Series Six PLC GFK 0171 Analog Input and Output Data An analog block of any type such as a 4 Input 2 Output Analog block or an RTD block uses 24 references in the input table A 4 Input 2 Output Analog block also uses 32 references in the output table Analog input data is multiplexed into the input table references so that data from only one of the circuits on the block is presented each sweep The next input circuit is presented during the following sweep The number of sweeps required is the same as the number of input circuits on the block Analog Output Data Analog blocks with 4 inputs and 2 outputs use 32 output references for the two circuits 32 17 16 l pne E E msb lsb msb lsb __ Output 2 __ Output 1 Unlike input data described below output data is not multiplexed Data for output 1 is stor
17. 752 760 768 776 081 088 096 104 112 417 424 432 440 448 753 760 768 776 784 089 096 104 112 120 425 432 440 448 456 761 768 776 784 792 097 104 112 120 128 433 440 448 456 464 769 776 784 792 800 105 112 120 128 136 441 448 456 464 472 777 784 792 800 808 113 120 128 136 144 449 456 464 472 480 785 792 800 808 816 121 128 136 144 152 457 464 472 480 488 793 800 808 816 824 129 136 144 152 160 465 472 480 488 496 801 808 816 824 832 137 144 152 160 168 473 480 488 496 504 809 816 824 832 840 145 152 160 168 176 481 488 496 504 512 817 824 832 840 848 153 160 168 176 184 489 496 504 512 520 825 832 840 848 856 161 168 176 184 192 497 504 512 520 528 833 840 848 856 864 169 176 184 192 200 505 512 520 528 536 841 848 856 864 872 177 184 192 200 208 513 520 528 536 544 849 856 864 872 880 185 192 200 208 216 521 528 536 544 552 857 864 872 880 888 193 200 208 216 224 529 536 544 552 560 865 872 880 888 896 201 208 216 224 232 537 544 552 560 568 873 880 888 896 904 209 216 224 232 240 545 552 560 568 576 881 888 896 904 912 217 224 232 240 248 553 560 568 576 584 889 896 904 912 920 225 232 240 248 256 561 568 576 584 592 897 904 912 920 928 233 240 248 256 264 569 576 584 592 600 905 912 920 928 936 241 248 256 264 272 577 584 592 600 608 913 920 928 936 944 249 256 264 272 280 585 592 600 608 616 921 928 936 944 952 257 264 272 280 288 593 600 608 616 624 929 936 944 952 960 265 272 280 288 296 601 608 616 624 632 937 944 952 960 968 273 280 288 296 30
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19. Bus Controller Input References 8 7 GFK 0171 Detecting I O Circuit Faults A Bus Controller with Diagnostics uses input reference bit 3 to report circuit faults Note that circuit diagnostics are obtained from devices on the bus that have been assigned Reference Numbers in I O memory Automatic diagnostics are NOT performed on devices assigned Reference Numbers in register memory See chapter 3 for more information Byte 1 Mid Circuit Fault For each fault reported bit 3 is set to 1 for one sweep When this bit is 1 the other Bus Controller input references contain the following information 6 5 4 3 2 ij byte number 48 41 37 33 25 17 9 3 bit I O reference bit 3 1 Circuit Fault bit 9 1 input reference affected bit 10 1 output reference affected Loc ORES dd 24 least significant 8 bits of reference within channel most significant 2 bits of reference within channel Ll nn ES 20 7 E bits 33 36 block type bits 37 40 relative circuit number on the block bits 41 48 Circuit fault type Bits 9 through 16 indicate whether input or output references or both are affected If bit 9 is 1 the circuit is an input If bit 10 is 1 the circuit is an output If both are 1 the circuit is an output with feedback or the fault affects an entire block which is configured as a combination block Byte 2 16 15 14 13 12 11 10 Input reference affected Output reference affecte
20. Byte Location This is an address shared by ALL Bus Controllers in the system for status and control information The Logicmaster 6 software defaults this address to 993 which reserves references 993 to 1000 in both the input and output tables in the Main 1 O table for the Bus Controllers Any byte of available memory may be assigned however it is important that the contents of this memory location not be used for any other purpose by the program If the application program requires the use of I O addresses 993 1000 in the Main I O chain change this entry on the CPU Configuration Setup Menu Computer Mailbox Enabled The Computer Mailbox is an area of memory that can be reserved for communications between devices If the Computer Mailbox is enabled any device that needs to communicate with another device can place a command and address of the other device in the Computer Mail Box The CPU detects that a command is waiting and opens a window to that device The device should look in the mailbox registers for a command then either read or write data depending on the command specified Devices that can communicate using the Computer Mailbox include the Series Six CPU the ASCII BASIC Module the CCM Module and the Bus Controller The Computer Mailbox occupies the last 70 consecutive registers out of the total number avallable Therefore its starting address varies according to the CPU register memory size For example for a CPU with 8K register
21. CPU Configuration instruction 4 1 CPU register size 4 4 CPU Shutdown mode 2 3 CPU Sweep 1 9 8 4 CPU Sweep Time 6 3 7 5 D Data Coherency B 2 Datagram 6 1 Assign Monitor 6 5 incoming 6 3 priority 6 2 Read Device 6 12 timing 6 4 types 6 1 Write Device 6 7 Write Point 6 10 Datagrams supported B 2 Device Number 2 3 Device Number conflict B 1 Diagnostic range 4 3 Diagnostics enabled 4 2 Diagnostics from Bus Controller 8 1 Diagnostics programming 1 12 Disable outputs 2 5 DPREQ instruction 5 1 E Error rate 1 12 Expanded Functions 4 1 Expanded I O 2 3 B 2 Expanded I O addressing A 1 F Fault clearing 1 12 4 10 Fault Table 4 4 4 8 Force I O 8 15 G Global Data 7 1 Global Data address 5 20 Global Data address and length 5 11 Global Data vs Datagrams 6 2 H Hand held Monitor Connector 1 2 High speed Counter 3 9 I I O Addressing 2 3 I O block compatibility B 1 B 2 I O block references 3 2 I O block status 1 12 I O fault detection 8 7 I O force detection 8 15 I O memory 3 2 I O Transmitter module B 2 I O Transmitter Modules 1 5 Idle command 5 7 Inputs only blocks B 2 L LEDs 1 2 10 1 Logicmaster 6 version 2 4 Login of bus devices B 2 Loss of block detection 8 10 M Memory mapping A 1 O Output states 1 12 Outputs disable 2 5 5 11 5 13 9 3 P Phase A B compatibility B 1 Phase A phase B compatibility 1
22. Diagnostics A Bus Controller without diagnostics IC660CBB903 uses eight input references one byte to report its Status and the status of the serial bus to the CPU once each CPU sweep 8 1 bits bit 1 Bus Controller OK bit 2 Bus Error Of these assigned references bits 3 8 are not used Bus Controller with Diagnostics A Bus Controller with diagnostics IC660CBB902 uses 48 input references six bytes The Bus Controller places fresh diagnostic data in these references every CPU sweep 6 5 4 3 2 1 byte number 48 41 33 25 17 9 1 I O reference _ bit 1 Bus Controller OK _ bit 2 Bus Error _ Circuit _ bit 3 Circuit Fault Reference _ bit 4 Loss of Block _ bit 5 Addition of Block _ Fault Type __ bit 6 Address Conflict Circuit Number _ bit 7 Pulse Test Active Q block _ bit 8 Circuit Forced 1 discrete 2 analog _ Input Output __ Fault Description The program can monitor this data as explained below Programming for Diagnostics Using Bus Controller Input References 8 3 GFK 0171 Logic to Monitor Diagnostic Information The ladder logic can monitor the Bus Controller input references for faults and use Source To Table Moves or other program instructions to capture the data A fault or system change is sent to the CPU for one sweep only The Bus Controller buffers up to 60 faults and sends one at a time to the CPU every CPU sweep Thus input status bits chan
23. E fad On A p O gt A A ej o D e i m pad cj o MES EE be OD A o GULES SESE o FRASER AB 9 85 ux 4 y P 2 O SSES e585 B dog od3 He gt 28 T O e e pu E 4 c a Fw A AQ vo Yooh Bes E o Bed A 33 g O lt gt E gt a E Ej ra O E O D x Es E E S E e A lt y Seal l y lt 90321 S amp a au mega E Bn be E Q Sea LOHE o BROS JG J 2 d ody Goth BSR ee w g 8 qd IBER gta HM FEY GA Fe Pd DE e O gno a oO Sey bs be E 1 9 Eg C r yr ir Q i O Q O 4 e o po U A QU t O c 2 ep ae Sas y Pa d a o d S o P If S88 uoo no 000 Bw lt 202239508 U Be BED uns a i nad 4 e 8 2583 23 g Sg988g89 OQ mx 8 Q ond bh E a O e e oO a El A Y DE 0 o A a ay YD Gs FL t 4 Ail a fg Show BS FoR ESS BS 8 lo 5B 58560 38 o tb NS gas So B T Ne Q e a E D O Mn As el z Eb on s E vo S 5528 v2 2 e Sec 28 Eg O lo A Boas Mae gt RAOSBSE ASO FS A 1 fullv the sweep times o 24 7 59 P Kn Ou SSI Detween tw 1 9 1 ometimes used to set up a heartbeat 3 O O ata is s check the operat Chapter 9 8 1 Programming for Diagnostics Using Bus Controller Input References GFK 0171 This chapter shows the format of the diagnostic data provided by the Bus Controller You will not need this information if you are using the automatic diagnostics features of the Logicmaster
24. See chapter 3 for more information Updating I O Points with Register References For most applications I O points are assigned Reference Numbers in I O memory and are updated during the I O scan portion of the CPU sweep If I O points have been assigned Reference Numbers which are in register memory instead of I O memory the points will not be updated during the I O scan An Idle command can be used to open a communications window during which these I O points will be updated 5 8 Programming Window Commands GFK 0171 Read Configuration The Read Configuration command is used to request current configuration data from the Bus Controller or a block It cannot request data from another interface module on the bus a Hand held Monitor or a block that has been assigned a register Reference Number If configuration data is requested from the Bus Controller no message is sent on the bus the Bus Controller returns its configuration data to the CPU during the same window If configuration data is requested from a block the Bus Controller schedules a Read Configuration message to the block as a background task then returns the Status Code 1 In Process to the CPU and closes the CPU Bus Controller window The Bus Controller accepts no additional non immediate CPU Bus Controller window commands from the CPU until the task is completed With the window closed program execution resumes The Bus Controller reads the configuration dat
25. The Read Configuration Write Configuration Read Diagnostics and Read Analog Inputs commands cannot be send to a block that is assigned a register Reference Number These functions must be done using Datagrams 3 2 Interfacing Genius I O Blocks to the Series Six PLC GFK 0171 Assigning Reference Numbers in I O Memory Reference Numbers can be selected from any available references in a chain or channel in an Expanded I O system Each Reference Number must begin on an even byte boundary A byte boundary is a number that always leaves a remainder of 1 when divided by 8 1 9 17 The references used by each device go up in sequence 0001 0002 0003 to the maximum required by the device always multiples of 8 references In an Expanded I O system it will probably be most convenient to assign the first references in each channel to the Bus Controller then assign the I O blocks to references beginning at 49 Avoiding Reference Number Conflicts References assigned to any Genius block must not conflict with or overlap references assigned to other devices anywhere else in the PLC system This includes other blocks on the same or any other bus other Bus Controllers or conventional I O modules In an Expanded I O system if multiple Bus Controllers on the same bus are installed directly in the CPU rack and any references assigned to blocks on that bus overlap a bus fault message will be generated However if the Bus Controllers
26. an I O Transmitter Module as explained below Locating the Bus Controller Downstream of an Auxiliary I O Module If the I O points on a bus will be given program references in the auxiliary I O table or in Expanded I O channels 9 F the Bus Controller must be installed downstream of an Auxiliary I O module Locating the Bus Controller Downstream of an I O Transmitter Module If the PLC system uses Expanded channelized I O addressing channel selection can be made by either the Bus Controller phase B only or an I O Transmitter module If an I O channel has Genius I O only the Bus Controller can select channelization and no upstream I O Transmitter module will be permitted A Bus Controller set up for channelization must not be located downstream of an I O Transmitter Module It is possible to have Genius I O blocks controlled by a Bus Controller set up for channeliza tion while conventional I O modules are also assigned to the same channel It is important to be sure that the reference numbers assigned to the Genius blocks and I O modules do not overlap It is also possible to have several channelized Bus Controllers assigned to the same channel as long as overlap ping references are avoided Ideally if a system includes both conventional I O and Genius I O blocks they should not be mixed on the same channel However if the two I O types must share a channel restricting each to a predeter mined part of that c
27. an outputs only block you must set the MSB bit 15 to 1 Register 5 Pointer to block of registers where configuration data for the block or Bus Controller starts Data Written by the Write Configuration Command The configuration data to be written must be set up in the registers before the command executes The data must have the format shown for the Read Configuration command Also see the Genius I O System User s Manual Read Configuration Reply Items marked Read Only are ignored by the blocks Changing the register values for one feature such as disabling outputs will not change another feature such as Global Data if the registers for that feature retain their previously configured values Programming Window Commands 5 13 GFK 0171 Enabling and Disabling Outputs When sent to the Bus Controller the Write Configuration command can be used to enable or disable the sending of output messages from the CPU to some or all of the blocks on the bus This applies to input only blocks too as they rely on receipt of the null output message to turn their I O Enabled LEDS on and off Enabling Outputs at Powerup The Bus Controller s on board DIP switch can be set to disable all outputs at powerup as explained in chapter 2 With program logic use the Write Configuration command to enable outputs to the blocks which are intended to be under the control of this Bus Controller This includes input only blocks Disabling Out
28. and 1 Fault Type If the fault is a circuit fault bits 41 to 48 of the Bus Controller input references identify the fault type The meaning of these bits depends on whether the block is a discrete or analog block Fault type bits for a discrete block Byte 6 edil lili Loss of I O power Short Circuit Overload No Load Present outputs or Open Wire inputs Overtemperature Failed switch not used Fault type bits for an analog block Byte 6 headed al be Soon Input Low Alarm Input High Alarm input Underrange Input Overrange Input Open Wire Output Underrange or Input Circuit Wiring Error Output Overrange or Internal Fault Input Circuit Shorted for RTD blocks only 8 10 Programming for Diagnostics Using Bus Controller Input References A APA KK GFK 0171 Detecting the Loss or Addition of a Block To have the program detect the loss or addition of a block on the bus use logic to monitor Bus Controller input reference bits 4 and 5 Byte 1 je vt er si er stat ay Loss of Block Addition of Block If bit 4 is 1 the Bus Controller has detected the loss of an I O block that was previously operating If bit 5 is 1 the Bus Controller has detected the addition of a block to the bus Either of these bits may be 1 for one CPU sweep for each detected loss or addition they are never both equal to 1 at the same time If either of these bits is equal to 1 the other Bus Co
29. can be used to monitor block faults and configuration changes Blocks broadcast their inputs to all devices on the bus inputs will be received by a monitoring device automatically In addition one or more blocks can be instructed to send extra fault and configuration change messages to the assigned monitor These extra reports will add to the bus scan time as explained in the Genius I O System User s Manual There can only be one device assigned as a monitor to any given block Send the Assign Monitor Datagram to all blocks that should report faults and configuration changes to the monitor The message contains the Device Number of the monitor If necessary the assigned monitor may be changed by issuing another Assigned Monitor Datagram with a new Device Number to the block CONTROLLER MONITOR a42480 BUS PCIM CONTROLLER LLL VO BLOCKS The Assign Monitor Datagram can be sent to phase B Genius I O blocks only If sent to phase A blocks or to bus interface modules the Assign Monitor command has no effect A complete listing of phase A and phase B Genius devices is located in the Genius I O System User s Manual GEK 90486 Command execution is not immediate the Bus Controller will not set the Status Code to 2 Done until it receives an acknowledgement from the block 6 6 Datagrams I gt _ ____ _ _ _ ___ _ _ _ ____ gt EEEOEP gt A AK kK AGA GFK 0171 Comman
30. change is needed If there will be more than one bus interface module Bus Controller or PCIM on the samebus it is necessary to assign each a different Device Number Switches 4 through 8 at position U3 select a Device Number A Bus Controller may use any available Device Number except in CPU Redundancy mode In Redundancy mode the blocks require Bus Controllers at Device Numbers 30 and 31 Selecting Expanded I O Addressing The DIP switches at position US9 select the type of 1 0 addressing used by the Bus Controller Do not change the default switch settings if the system uses Normal I O addressing or if the Bus Controller will be installed downstream of an I O Transmitter module which will be selecting an Expanded I O channel 2 4 Setup and Installation GFK 0171 If the system uses Expanded 1 O addressing with the channel selected by the Bus Controller use the switches at position US9 to select Expanded I O addressing and specify the channel number 242182 SWITCH SETTING es 01234567 Aux 9 ABCDEFS X X Xx x XX Xx XK XXX x open off Default is all closed ES The Bus Controller must be installed downstream of an Auxiliary 1 0 Module to address the Auxiliary I O chain or Expanded I O channels 9 through F A phase A Bus Controller cannot be used for channel selection and must be installed downstream of an I O Transmitter module in an Expanded I O system Logicmaster 6 Version Number It is i
31. defaulting outputs Defaulting outputs means automatically setting outputs to a predetermined state if the block ceases to receive CPU communications for 3 bus scans When to default outputs is determined by the I O blocks If program action causes the CPU to disable outputs while the system is in operation any blocks that stop receiving outputs as a result will default their outputs to the appropriate predetermined state The blocks will also default outputs if CPU communications are lost for any other reason such as a broken cable BUS CONTROLLER BLOCKS 42527 a A E Can DISABLE outputs to Can DEFAULT outputs to predetermined blocks and other bus devices state if outputs from CPU cease How Outputs can be Enabled or Disabled There are three different ways to disable or enable outputs First All outputs on a bus can be disabled or enabled at powerup by setting a DIP switch at position U16 This 1s explained on the next page Second All outputs from the Bus Controller can be disabled and enabled together during system operation This might be done in a system with two or more CPUs on the same bus where one was used only for data monitoring Third Outputs can be enabled or disabled during system operation on a block by block basis by setting and clearing individual Disable Outputs bits This might be done in a system where two or more CPUs were used for selected control of blocks on the same bus 2 6 Setup and Installation
32. done when the device acknowledges the message However if FF is specified in register 4 command execution is non immediate register 3 is set to done as soon as the message is sent with no guarantee that the devices have received the message Device Number serial bus address of the bus interface module that will receive the Datagram To broadcast the message to all devices on the bus enter FF hex in this register Location in register memory of the Write Device datagram See register n below Length of message 9 bytes Command code Lower byte OB hex Write Point datagram Upper byte 20 hex for normal priority AO hex for high priority Content of the Write Point Datagram Register n Register n 1 Register n 2 Register n 3 Register n 4 Lower byte must be 00 hex Upper byte contains 2 least significant hex digits of the absolute memory address in the destination CPU where the data will be placed See Write Device Datagram for instructions on specifying absolute memory addresses Lower byte contains 2 most significant hex digits of the destination CPU absolute memory address Upper byte must be 00 hex Lower byte must be 80 hex Upper byte AND mask for bits 0 7 For the AND mask set to 0 any bits to be changed Set to 1 all other bits Lower byte OR mask for bits 0 7 For the OR mask set to the desired state any bits to be changed Set to O all other bits Lower byte AND m
33. e to extend the programmer window by 1 2mS direct an extra idle status 0 DPREQ or WINDOW instruction to the Bus Controller e to extend the programmer window by 5mS program a DPREQ or WINDOW instruction with no Bus Controller address Using the Read Analog Inputs Command Another way to update inputs from these devices is with a Read Analog Inputs command which reads values from the Bus Controller s own RAM memory not from shared RAM This area of memory always contains the latest values from all input circuits on each such device If the program is required to have the most current values of these inputs as the logic executes a Read Analog Inputs command should be used instead of a DO I O instruction DO I O reads input values from shared RAM Since the Bus Controller updates shared RAM only once per CPU sweep multiple DO I O instructions in the same program sweep will return the same values each time PROGRAM a42893 READ ANALOG f ONE NEW VALUE LATEST VALUE EACH CPU FOR EACH CHANNEL SWEEP EACH BUS SCAN For more information about the Read Analog Inputs command see chapter 7 Chapter 4 4 1 Automatic Diagnostics and Fault Clearing GFK 0171 This chapter explains how set up an application program to use the built in Genius I O diagnostics and fault clearing features of the Logicmaster 6 software Use of these features requires the Expanded Functions in both the PLC and in the software If the system will make us
34. gt ae E B 8 2 2 E E E e o g mM m oF Pa KR c oO OQO r lt El El f i v N SQ v 4 o wn m S N 6 88 FCR t 6 S Wo m 889 m Jr m fe wa O 2 ra E Q 9 O G H Y d ct A o O de O 4 0 Vl 90 m X Q e O C n 4 2 3 o0 boe rj Q 4 e sE E un As e o 0 e a lo ER San a 2138 e SA ed ET bi P eA e y Ha p o o O e mM O 9 O A gt 0 O Y Y x e 4 se 00 d O v v a G iS ia ob o0 ES dd ov t CU DEEP XS f 4 de 4 b d N 2 pend es TUN l 9 pa a e dd N A dmg 0 0g li Ao Se ee ES E e 6 Q J s OS Ex d 0 v E 2 XS Lo sH O A JED E E B a O 0 F L Ho 5 S e od ES LE 4 Programming for Diagnostics Using Bus Controller Input References 8 9 GFK 0171 Bits 37 40 contain the relative number from 0 to 15 of the circuit where the fault occurred The value zero represents the topmost circuit on the block The higher value is the bottom circuit on the block for example 7 for a 8 circuit block For analog blocks Bits 33 36 indicate the block type Bits 37 40 indicate the relative circuit number 0 to n for inputs 0 to n for outputs where the fault occurred Byte 5 ia aise 0 0 1 0 circuit fault on 4 In 2 Out Analog block 0 1 0 0 circuit fault on RTD or Thermocouple block Relative circuit number 0 n For the 4 Input 2 Output Analog block bits 9 and 10 indicate whether the circuit is an input or output Input circuits are numbered 0 3 Output circuits are numbered 0
35. it is sent to the Bus Controller If diagnostics data is requested from a block the Bus Controller schedules a background message to the block and returns the Status Code 1 In Process to the CPU The Bus Controller then closes the CPU Bus Controller window and accepts no additional non immediate window commands from the CPU With the window closed the Bus Controller reads the diagnostic data from the block in 16 byte increments When all the data has been received the Bus Controller transfers it to the CPU at the start of the next available CPU Bus Controller window and sets the Status Code to 2 Done then closes the window Command Block for the Read Diagnostics Command Command Block format for the Read Diagnostics command is Register 1 Bus Controller Reference Number plus 1000 for a DPREQ Register 2 Command number 4 Register 3 Status Code supplied by the Bus Controller Register 4 Ten bit beginning reference address of the block or Bus Controller from which diagnostic data is to be read If the diagnostic data is read from an outputs only block set the MSB bit 15 to 1 Register 5 this register contains a pointer to an address where the returned diagnostic data will be stored in the CPU registers Data Returned by the Read Diagnostics Command The exact content of the Read Diagnostics reply message depends on the type of device being queried Read Diagnostics Reply message contents for the Series Six PLC Bus Controller a
36. memory the Computer Mailbox is located from R8123 through R8192 If the Computer Mailbox is not enabled these registers are available for other use for example for the CPU fault table described above Automatic Diagnostics and Fault Clearing 4 7 GFK 0171 Genius Bus Controller Locations Screen After completing the CPU Configuration Setup Menu the next step is to indicate the locations of the Bus Controllers Press B C Map F1 from the CPU Configuration Setup Menu The screen will show each possible Bus Controller location in the system L M OFFLINE GENIUS BUS CONTROLLER LOCATIONS CURSOR CHANNEL 0 LOCATION 0001 MAIN CHAIN CHANNEL LOCATIONS AUX CHAIN CHANNEL LOCATIONS 0 1 2 3 4 5 6 7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 hj bj OU b oo 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 INSERT CPU 2 BC 3 8CONFIG The number beside the word LOCATION represents a possible Reference Number that might be assigned to a Bus Controller using the backplane DIP switches The cursor first appears at the rightmost location in the Main I O chain location 0001 Move the cursor to select a location then press F2 to insert a Bus Controller For example this partial screen shows a B
37. of this reference contains the Device Number of the bus interface module which will receive the fault reports lt 29 a However if FF is specified in register 4 the command is immediate register 3 is set to done as 4 If the message is sent to one device it is a non immediate See register n below t command the status register will indicate done when that device acknowledges the message A To broadcast this w 4 soon as the message is sent with no guarantee that the devices have received the message ho a v Device Number of the bus interface module to which the Dataeram will be sent a Ld ae ge to the number of data bytes up to w ur ae 4 a Duces S equ hex in this register r FF ls sx end Datagram 4 This i A 3 memory of the Write Device Datagram to be sent 1 O Status code supplied by the CPU t Register nt 1D i msb lumber gt y m v P3 a Bus Controller Kererence LS umber 12 S message to all devices on the bus ente v Register ntl msb ata Comman _ P m Pas Pu sm Register 2 Register 3 Register n ur ur e amp e msb Register 6 Register 5 Register 4 Register 1 b address a most Significant hex O NY h V 44 Oh ig be 80 AR length in bytes aN M
38. position is indicated see Register n below Registers 6 8 not used The content of the data sent from the CPU registers to the target device is Register n BSM position bit 0 0 bus A 1 bus B If not 0 or 1 syntax error number OC hex is returned in the status code Chapter 6 1 Datagrams GFK 0171 This chapter describes Types of Datagrams Supported Normal or High Priority Datagrams Using Datagrams instead of Global Data Programming for Incoming Datagrams Effect of Datagrams on the Genius I O Bus Maximum CPU Sweep Time Increase Assign Monitor Datagram Write Point Datagram Write Device Datagram Read Device Datagram Types of Datagrams Supported The Series Six Bus Controller supports the following Datagrams Subfunction Code Message Type Hex Read Configuration Read Configuration Reply Write Configuration Assign Monitor Begin Packet Sequence End Packet Sequence Read Diagnostics Read Diagnostics Reply Write Point Report Fault Pulse Test Pulse Test Complete Clear Circuit Fault Clear All Circuit Faults Switch BSM Read Device Read Device Reply Write Device Configuration Change Read Data Read Data Reply Write Data Window commands can be used to send Read Configuration Write Configuration and Read Diagnostics Datagrams to the Bus Controller or to blocks on the bus which are assigned to I O memory For blocks assigned to register memory the Send Datagram and Receive Data
39. removed and assigned another Device Number Then power to the Bus Controller must be cycled Powerup Tests Will turn off both LEDs if communi Will flash both LEDS in unison if powerup communica cations test fails Does not test MIT tions test or MIT test fails Bus Error Detection If 1 bus error is detected in a 250mS If 10 bus errors are detected in 10 seconds Comm OK period Comm OK LED turns off LED goes off Comm OK also goes off if Bus Controller Comm OK also goes off if the Bus misses its tum on the bus Comm OK LED goes back on Controller misses its turn on the bus if no new errors are detected in 250 mS The bus error count 1s cleared every 10 sec Clear All Faults Clears all faults and completely clears Clears all faults but does not remove Addition or Loss of Command the fault queue Block or Bus Controller Address faults from the queue Use of 16 32 Updates the input table during the Updates the input table during the regular I O portion of Circuit Blocks programmer window part of the sweep the sweep DO I Os may be able to capture updates with latest inputs from blocks DO I Os provide no updates Use of Analog Blocks Updates the I O table during the No change programmer window DO I Os pro vide no update same input same data until next programmer window B 2 Bus Controller Compatibility GFK 0171 Phase A Bus Controller Phase B Bus Control
40. the Status Table reference of the Bus Con troller or a block Programming for Diagnostics and Fault Clearing Program logic can be used in addition to or instead of automatic diagnostics to access specific types of information and to send commands to I O blocks on the bus DESCRIBED FEATURE HOW TO DO IT IN CHAPTER Detect failure of Bus Controller self test Monitor Bus Controller input reference bit 1 Detect bus error condition Monitor Bus Controller input reference bit 2 Detect I O circuit faults Monitor Bus Controller input reference bit 3 Detect addition or loss of block Monitor Bus Controller input reference bits 4 and 5 Monitor Bus Controller input 5 reference bit 6 Detect duplicate or overlapping reference num bers Detect execution of a Pulse Test Detect force condition on the bus Create register table to store faults Clear all faults on a bus from program Clear fault s on a specific circuit from the pro gram Monitor Bus Controller input reference bit 7 Monitor Bus Controller input reference bit 8 See example logic in chapter 5 Set Bus Controller output reference bit 2 Set Bus Controller output reference bit 3 use additional references to specify circuit Introduction 1 13 GFK 0171 Programming for a Bus with Redundant Interface Modules If the bus will interface additional Bus Controller or PCIM modules program logic may be needed for CPU
41. to 0 Register 8 Fault time seconds bits 0 7 tenths of seconds 00 09 two binary coded decimal digits bits 8 15 seconds 00 59 two BCD digits Register 9 Fault time minutes hours bits 0 7 minutes 00 59 two BCD digits bits 8 15 hours 00 23 two BCD digits Register 10 Fault time days bits 0 7 days 00 99 two BCD digits bits 8 15 hundreds of days 00 99 two BCD digits Add 16 to tbis if fault type is 1001 Bits 0 3 will show faults 1001 and 0100 but no further decoding is performed in register 6 or 7 Logicmaster 6 version 4 01 decodes the Bus Controller status bytes for this information 4 6 Automatic Diagnostics and Fault Clearing GFK 0171 The size selected for the fault table will depend on the amount of register memory available and the number of faults that are expected to accumulate before an operator is able to clear them The amount of register memory available for the Fault Table depends both on the entry for CPU Register Size above and on the Computer Mailbox Appendix A shows the allocation of registers in CPU memory The Computer Mailbox is explained on the next page If the Computer Mailbox is enabled it will occupy some of the register memory that would otherwise be used for the fault table Maximum table lengths number of faults that can be stored are listed below MAXIMUM TABLE LENGTH REGISTER COMPUTER MAILBOX ENABLED SIZE NO YES 68 399 Bus Status Control
42. to the Remote I O Receiver module a modem cannot be used Communications between the Remote I O Transmitter and Remote 1 O Receiver modules are via a serial twisted pair link of two unidirectional data lines Transmit Data and Receive Data This method of I O update is slower than normal Genius I O service Up to 496 total I O references can be included in one Remote I O station Because of the reduced capacity of the remote I O communications link this type of system does not support the use of any communications commands and is not recommended for fast acting I O In addition diagnostics may not always reach the CPU Using Remote I O also requires more complex logic in the application program Operation of Genius I O in a Remote I O System With a Bus Controller in a Remote I O rack communications between the Remote I O Transmitter and Remote I O Receiver modules must be set at 57 6 Kbaud The I O will be serviced each time the upstream Remote I O Receiver module performs a partial Series Six I O sweep The update rate is affected by asynchronism between the Series Six I O sweep and the transmission time required for data on the serial link between the Remote I O Transmitter and Remote I O Receiver modules The Remote I O Receiver module scans the Bus Controller for current inputs from the Genius I O blocks It then transmits input data and the Bus Controller status to the Remote I O Transmitter module via the serial link until the next programmer
43. window occurs On the next CPU I O sweep these same inputs are read from the Remote I O Transmitter module into the Series Six Input Status Table If an output changes in response to an input or status bit the earliest the new output will get from the CPU to the Bus Controller is 11mS after the next programmer window See GEK 83537 Remote I O Modules for a discussion of system delay times New output states on a given I O sweep are not guaranteed to be picked up by the Remote I O Transmitter for transmission so care must be taken to ensure that output states of short duration actually get to the output The Remote I O Transmitter provides a handshake bit to assist in this Since faults that are reported for one scan may be missed by the CPU the application program should periodically issue a Clear All Faults command to the Bus Controller Introduction 1 7 GFK 0171 Bus Controller Operation All data transfer between the PLC and the devices on a bus is handled by the Bus Controller The Bus Controller interfaces two completely separate and asynchronous activities e the Genius bus scan a cycle of communications between the devices on a bus this includes the Bus Controller itself e the CPU sweep the cycle of actions that includes communications between the CPU and the Bus Controller The Bus Controller manages data transfer between these two asynchronous cycles by maintaining two separate on board RAM memories One interface
44. 0 0005 0000 0000 0000 00190 0000 0000 0000 0000 0000 0000 OFAO OFAO 0000 0007 0200 0000 0000 0000 0000 0000 0000 0000 0000 0205 0000 00210 0002 01C3 0000 0148 0001 0000 0000 003E 0000 001E 00220 0000 0000 0000 0000 0000 0000 0000 0000 0205 0000 00230 0000 0000 0000 0000 0000 0000 0000 0000 0205 0000 00240 0002 01C3 0000 0148 0001 0000 0000 003E 0000 0000 DEC SIGNED HEX DBPREC TEXT FL PT CHANGE DISPLY lDISPLY 2DISPLY 3DISPLY 4DISPLY SDISPLY 6DISPLY 7 ALL SREF TB In addition to the Register Table display the Mixed Reference Tables function could be used to create custom tables of register I O and text data To create a Mixed Reference display see the Logicmaster 6 Software User s Manual for instructions In the preceding example register R100 is the pointer to registers R101 through R119 which store the fault types see rung 5 The number currently in this pointer register is the number of faults that have occurred Looking at register R100 shows that two faults are stored in the fault table L M OFFLINE REG REGISTER 00101 EQUALS 0000000000000010 00100 A 01C3 0000 0148 0001 0000 0000 003E 0000 0000 2 faults Programming for Diagnostics Using Bus Controller Input References 8 27 GFK 0171 Registers R101 through R119 store the fault type for 19 possible faults The information in these registers is copied from Bus Controller input references 1 through 16 bit 1 Bus Controller OK bit 2 Bus Error bit 3 Circu
45. 00000111 Register 2 Block Configuration Bit Assignments 14 13 12 11l10 9 8 7 6 5 4 3 2 1 P No of active devices on bus 1 32 READ ONLY TE A A A A NN not used 0 Bus Controller Device Number 0 31 READ ONLY Register 3 Baud Rate hex binary ie 14 13 12 11 10 9 8 71 6 5 4 Baud __ Rate 153 6 Kbaud ext 4 100 153 6 Kbaud std 3 011 76 8 Kbaud 2 010 38 4 Kbaud 1 001 Registers 4 19 Bit map of active blocks read only A binary 1 in a bit indicates that the corresponding addresses 8 references are assigned to a block Some blocks such as 16 circuit discretes require more than 1 bit in this map Registers 4 11 are a bit map of INPUTS assigned to active blocks Registers 12 19 are a bit map of OUTPUTS assigned to active blocks Register Register Register Register Register Register Register Register 4 12 5 13 6 14 7 15 8 16 9 17 10 18 11 19 O 00 10 Un PWN KH 7 e pod c 001 008 009 016 017 024 025 032 033 040 041 048 049 056 057 064 065 072 073 080 081 088 089 096 097 104 105 112 113 120 121 128 129 136 137 144 145 152 153 160 161 168 169 176 177 184 185 192 193 200 201 208 209 216 217 224 225 232 233 240 241 248 249 256 257 264 265 272 273 280 281 288 289 296 297 304 305 312 313 320 321 328 329 336 337 344 345 352 353 360 361 368 369 376 377 384 385 392 393 400 401 408 409 416 417 424 425 432 433 440 441 448 449 456 457 464 465
46. 0264 The Bus Controller s 48 assigned input references are 10257 through 10305 so bit 1 is located at 10257 RUNG 2 gt gt KKEKKKKEKKKKEKEKKEKKKKKKKEKKKERKKEKKEKKKEKEKKKEEKKEKKRKEKEKEKKKEKKRKEKEKKKKKKEKKKEKKEKKEEKKRKEEE This rung monitors the Bus Controller OK bit from the Bus Controller and the latched bus error output from the next rung is NOT OK or if there are 10 or more bus communications errors within 10 seconds output 1 will indicate the problem by turning off e fe e cede coe fe e ce e je ee dece ke oe dece ec oe e ke oe e eee ce ee ce oe de dece de e ede e e fe de de oe ce e je ce de ee oe ce cde ce oe ce e ck ecce coe cce x x BUS CNTRLR BUS OK BIT ERROR 10257 00904 If the Bus Controller GENIUS BUS IS OK 8 18 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Rung 3 checks for bus errors by monitoring Bus Controller input bit 2 located at 10258 lt lt RUNG 3 gt gt k se se A A A A A AA A A A e AA A A A A A A A A A A A A de e A A je A eode A A ode A A A A A de A A A A A A AA AAA AAA dee de jede RRA AAA RARA SR This rung latches the Bus Communications Error bit It will turn on if 10 or more errors occur within 10 seconds Output 1 Genius Bus OK will turn off if an error occurs The previous rung Can reset output 1 by turning on input 1 KKKK KKK KKK KKK KKK KEKE KKEKKEKEKKKEKKEKEKEKKKKKKEKKKKKEKRKEKKEKEKKKKKEKKKKKKKKEKEKKEK
47. 1 PLC system setup 1 11 Power Supply B 1 PowerTRAC 3 9 Powerup tests B 1 Programmer window 3 10 Pulse Test detection 8 14 Pulse Test outputs 9 3 Pulse test programming 1 12 R Rack B 1 Read Analog Inputs command 3 10 5 17 Read Configuration command 5 8 Read Device Datagram 6 12 index 1 3 eu UI A A el GFK 0171 Read Diagnostics command 5 15 Read I O type 1 12 Read Status Table command 5 20 Redundancy programming 1 13 Redundant bus termination 2 2 Reference Number 1 12 2 7 Reference Number configuration worksheet 3 5 Reference Number conflict 8 12 Reference number block 5 20 Reference Numbers 3 1 Register Memory 3 1 Remote I O 1 6 S Subfunction codes 6 1 Switch BSM B 2 Switch BSM command 5 21 T Troubleshooting 10 1 W WINDOW instruction 5 2 Write Configuration command 5 12 Write Device Datagram 6 7 Write Point Datagram 6 10 GE Fanuc Automation North America Inc Charlottesville Virginia
48. 10 Analog blocks 3 1 3 9 Analog I O B 1 Analog I O data 3 6 Analog I O Programming 1 11 Assign Monitor Datagram 6 5 Assigned monitor 5 14 B 1 Automatic diagnostics 4 1 Auxiliary I O 1 5 B Baud Rate 2 3 5 10 B 1 Block I O type 5 20 Block reference number 5 20 Bus 1 3 Bus Controller 8 2 input references 8 2 Set up 2 1 Status bit 8 4 Terminating impedance 2 2 Bus Controller baud rate 2 3 Bus Controller compatibility B 1 Bus Controller configuration worksheet 2 8 Bus Controller Device Number 2 3 Bus Controller diagnostics 5 16 Bus Controller fault status 1 12 Bus Controller Location 1 4 Bus Controller locations screen 4 7 Bus Controller model numbers 5 10 Bus Controller number on bus B 1 Bus Controller Operation 1 7 Bus Controller output references 9 1 Bus Controller references 2 7 3 3 4 9 Bus Controller Setup 1 10 Bus Controller status byte 4 6 Bus Controller types 1 1 Bus error detection 8 6 B 1 Bus Scan 1 7 Bus scan time 1 12 5 16 6 3 B 1 Bus Switching Module 5 21 B 2 Bus termination 2 2 Bus Wiring Terminals 1 2 Busses number 1 3 C Channelized I O B 2 Clear all faults on bus 9 4 B 1 Clear circuit fault 9 4 Command block format 5 3 Command Number 5 4 1 5 4 11 5 4 12 5 4 13 5 4 2 5 4 3 5 4 4 5 4 7 5 4 9 5 4 Communications programming 1 13 Communications timing 5 5 Computer mailbox 4 6 5 2 Control data B 2 CPU address 6 8
49. 13 Communications on the bus are intermittent or lacking This may be caused by mixed baud rates To check this power up blocks one at a time and look at their respective baud rates using HHM If you find different baud rates they must be changed All devices on the bus must use the same baud rate Any change to baud rate in block will not take effect until block power is cycled For Phase A devices check for duplicate Block Numbers Power devices up one at a time and confirm Block Numbers using the HHM 10 4 Troubleshooting GFK 0171 The terminating resistors on the bus may be missing or incorrectly chosen or placed Check terminators at ends of the bus for correct resistance value BSM cluster stubs should not be terminated The cable may be too long Shorten the cable or configure all devices on the bus to use a lower baud rate Please refer to chapter 5 of the Genius I O System User s Manual for more information about cabling and baud rate selection Wires may be open shorted or reversed Check all bus electrical connections 14 The COMM OK light on the Bus Controller blinks excessively and or there are propagation delays on the bus and or the bus is operating but the CPU repeatedly receives Addition of Block and or Loss of Block diagnostics There is excessive ambient noise on the bus This can be corrected by lowering the baud rate re routing the communications cable or shielding the source o
50. 24 Programming for Diagnostics Using Bus Controller Input References GFK 0171 lt lt RUNG 11 gt gt KKEKKKKEKKKKKKEKKKKKKEKEKKKEKEKEKKKKKKEKKKKKERKEEKKKKKKKKEKKKEEKEKEKEEKKEKKRKKKKKKKKKKK This rung times the on portion of a flashing indicator light ke e ee ee oce dede e eee ce eee de ce e oe hee e hee he ce ode e he ce e cfe dece obe ce de ce de ce e e e cde de ce de ce de ce fe de ce fe ce e de oe je de e che eoe eec ko FLASH ON Const 00905 Po PRESC TT 003 o FLASH o OFF 0 00906 R00002 C ACCRG R RUNG 12 kc sc ke e e e de ke e e eoe de ce eee e e e e de e ede ehe fe he e e fe de ce e e ce cede e de e ce de dece ce e e ce e ce he e ce e e e e ce cce cde e ce ce ce e oec cce ec e x This rung times the off portion of a flashing indicator light e e ee he eee e oe de e ce nde fece de dee e nhe KK RE fe ce de ce ce de dece e de de ce e fe ce nde dece e e cede cfe coe oe ce ne fe ce deck de ce ce fe ck eee AAA ee ox FLASH FLASH ON OFF 00905 Const 00906 tee 2 2 PRESC TT 003 FLASH OFF 00906 RO0003 T ACCRG R Rungs 13 and 15 are used to reset clear registers and the Bus Controller OK bit Rung 14 turns off the Bus Controller OK bit at t
51. 4 200000 lt lt RUNG 2 gt gt KKEKEKKKEKKKKKKEKKKKEKKEKEKKKEKKKKKKEKKKKKKKKKKEKKKKEKEKKKEKKKKEKEKKKKKKKEKKEKKKKKKEKKE Other logic in the program tests the state of the Bus Controller OK bit If the Bus Controller is OK this DPREQ instruction will execute the READ ANALOG INPUTS command every other CPU sweep KEEKKKKEKKEKKEKKKEKKKEKEKKKEKKKKEKKKKKKKKKKKKKKKKKKEKKEKKKKEKEKKKKEKEKKKKKKKKKKEKKEKKEKKKEE BUS CONTRLR ANALOG OK DPREQ 10257 00957 R0011 dp pe DPREQ C lt lt RUNG 3 gt gt k e e e e e eee ee e e ce e eee ce eoe e e ee he e e e ede e ce he e the e de ce e ce ce ce ce ee ce ce e ce ce e ce ce e e ce eoe eee ck e e ecc cc A A XX The rung below checks the READ ANALOG INPUTS command block status register to determine whether the current status of the command is 2 x indicating successful completion If the status is not equal to 2 x input data may not be current and could be invalid ui KAKKEKKKKKKKKKKEKKKEKEKKKKKKKEEKKKKKKKKEKKKKEKEKKKKREKKKKRKEKKKKEKKKEKKKKEKKKEKEKKKEKKKKE ANALOG ANALOG ALWAYS ALWAYS DPREQ IN DATA 00002 00002 STATUS VALID Const R0010 R0010 R0013 o0001 A MOVE B A o B C 00002 5 20 Programming Window Commands GFK 0171 Read Status Table Reference The Read Status Table Reference command is used to 1 read the Reference Number of the Bus Controller 2 read the Reference Number and I O type of an I O block
52. 4 609 616 624 632 640 945 952 960 968 976 281 288 296 304 312 617 624 632 640 648 953 960 968 976 984 289 296 304 312 320 625 632 640 648 656 961 968 976 984 992 297 304 312 320 328 633 640 648 656 664 969 976 984 992 1000 305 312 320 328 336 641 648 656 664 672 977 984 992 1000 xxx 313 320 328 336 344 649 656 664 672 680 985 992 1000 xxx xxx 321 328 336 344 352 657 664 672 680 688 993 1000 xxx xxx xxx 329 336 344 352 360 665 672 680 688 696 Interfacing Genius I O Blocks to the Series Six PLC 3 5 GFK 0171 I O Reference Number Assignment Configuration Worksheet Main I O Chain corresponds to channel 0 Auxiliary I O Chain corresponds to channel 8 Expanded I O Channel Number 1 7 9 F Channelization provided by Bus Controller Y N Ref Stat 001 009 017 025 033 041 049 057 065 073 081 089 097 105 113 121 129 137 145 153 161 End 008 016 024 032 040 048 056 064 072 080 099 096 104 112 120 128 136 144 152 160 168 INPUTS USED OUTPUTS USED Ref Start 169 177 185 193 201 209 217 225 233 241 249 257 265 273 281 289 297 305 313 321 329 End 176 184 192 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336 INPUTS USED OUTPUTS USED Ref Start 337 345 353 361 369 377 385 393 401 409 417 425 433 441 449 457 465 473 481 489 497 End 344 352 360 368 376 384 392 400 408 416 424 432 440 448 456 464 472 480 488 496 504 INPUTS USED OUTPUTS USED Ref Star 505 513 521 529 537 545 553 561 569 577
53. 472 473 480 481 488 489 496 497 504 505 512 513 520 521 528 529 536 537 544 545 552 553 560 561 568 569 576 577 584 585 592 593 600 601 608 609 616 617 624 625 632 633 640 641 648 649 656 657 664 665 672 673 680 681 688 689 696 697 704 705 712 713 720 721 728 729 736 737 744 745 752 753 760 761 768 769 776 777 784 785 792 793 800 801 808 809 816 817 824 825 832 833 840 841 848 849 856 857 864 865 872 873 880 881 888 889 896 897 904 905 912 913 920 921 928 929 936 937 944 945 952 953 960 961 968 969 976 977 984 985 992 993 1000 Programming Window Commands 5 11 GFK 0171 Registers 20 and 21 read write For Bus Controllers IC660CBB902 and 903 only registers 20 and 21 are used as Output Disable flags with one bit for each device on the bus The least significant bit of register 20 represents Device Number 0 and the most significant bit of register 21 represents Device Number 31 Register 21 Register 20 Output disable bit for device 0 Output disable bit for device 31 For each bit a one causes the CPU to read the block s inputs but not to send outputs When a bit is 0 outputs are sent to the corresponding Device Number No more than two CPUs on the same bus should have their outputs enabled to the same blocks This table can be defaulted to all 0 or all 1 at powerup using the Disable Outputs DIP switch on the Bus Controller see chapter 2 Register 22 R
54. 6 software If the Logicmaster 6 software Expanded Functions are enabled as described in the chapter 4 the CPU can access this data automatically and lengthy programming can be avoided The following diagnostic information is available from the Bus Controller Bus Controller OK all Bus Controllers Serial Bus Error all Bus Controllers I O Circuit Fault Bus Controller with Diagnostics Loss or Addition of Block Bus Controller with Diagnostics Address Conflict Bus Controller with Diagnostics Pulse Test Active Bus Controller with Diagnostics HHM Force Active Bus Controller with Diagnostics Program logic can be used to monitor this information In addition the program can use the Bus Controller s output references to clear faults or to disable outputs see chapter 9 Additional Programming for Diagnostics In addition to monitoring the Bus Controller data described in this chapter the ladder logic can obtain diagnostics data directly from devices on the bus using the Read Diagnostics command See chapter 5 for more information 8 2 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Bus Controller Input Reference Formats A Bus Controller provides diagnostics data to the CPU in its assigned input references The format of data in these references depends on whether the Bus Controller has diagnostics capabilities Each diagnostic is available for exactly one CPU sweep Bus Controller without
55. 65 BUS CONTROLLER L PHASE B 1 0 BLOCKS Output data for these blocks will be supplied by one or more other CPUs on the same bus CONTROLLER MONITOR a42566 PLC PLC BUS BUS CONTROLLER CONTROLLER OUTPUTS DISABLED pu OUTPUTS a er uum PHASEB 1 O BLOCKS J A device that is assigned as a monitor should have all its outputs disabled This can be done using a Write Configuration command in the program or by setting the Bus Controller DIP switch If a Bus Controller is used as a monitor it cannot be located in the same CPU as any other Bus Controllers on the same bus Otherwise the CPU would receive input data from both Bus Controllers for the same references and parity errors could result Programming Window Commands 5 15 GFK 0171 Read Diagnostics The Read Diagnostics command can be used to request diagnostic information about a block and its I O circuits or the status of Bus Controller and the bus It cannot be sent to a block that has been assigned a register Reference Number The diagnostic data returned by blocks in response to this command indicates faults that have occurred since powerup or since the last Clear Faults message was issued Current diagnostic state can be found by first issuing a Clear Faults command to the circuit s or channel s to clear the fault history then issuing a Read Diagnostics command A Read Diagnostics command is completed during the same window only if
56. BOS kK OR ot SN E GANE H O mk H 2 N k e k Ox A 9219 X oh uns pcd M b E 21 Cee 5 A E k e PE Sgap feast asd 438 AE reggo S 3 1 BT EE 9 omp N NA i H 0000 o e i jt k px a ss en tA bs T T d n d Dp x 10 MH i 9 O at Q HH E won a NS h paruis de ud o gon E nt xK kx A Suc o ra de B n 9 9 9 paar os UN 9 DE ues x 3 3 A e a 4 s o Eb a E L2 P i B HH ae OO EE TO c EN e Coin A 5 db us k Ek Ss S8 pon ds i eg greene eed SE E s RC EE a GA QO Ox Ex a bb Mw S 5 i O d N Hg O Qk x 0 0 1D 7 Y H Oo E U JEFE MEM TIN Jii da 5 if385 34 ae iff G K c YY K iz E Koc y i oC PR oo x ps Ho 2 e A oe a OF e LUE oe Lo eee M ui h Q T ob d E S hno s s ins S an aia A a dom dc F tans Ss BUM Lond 2 AS E E dux i joco d 6 r E e tr o x OF V NA x ia d o x 050 O E e cd Y A9 k 0 n4 i Op oO VHO m K Yon dH Y DE k p om U i x Ig E I KORU O hi H cd i oe T ep uo DM x b rt x iu N d k o 5 d 2 a Soe i K p 08550 Ug u Y Y Od 2 gt S x Ox ml Ss 2 Bok i kho E dowuy p HE S B Ro c UD x o pce p gt x Dx kx E Ag k 0 2 DE N 5 afa i SS RoR eed pe kT 8 yooh pi r om tB Nn x r 3 T rA K m E i 3 d c tf ng i 0 MUYA O a EW Q o x Bt a 9 i O H ex C c mo on n UU A K x i e YN e x H x X N mM K 4 u H O 1 O x 3 28 NE RERE Tooo o dais P o 8 k w y x i EAA ON a xO rd a Wok i5 See 2 Sh O Oo 2 E A i M i D A A x z Soo j n Ax D m 5 H
57. BSM Send Datagram Receive Datagram n a the command cannot be sent to that type of target device or to another bus interface module on the same bus non immediate if directed to a specific device If a Datagram command is broadcast to all devices on the bus it is an immediate command When estimating CPU sweep time add together the times of all windows the CPU might open to Bus Controllers in the system during the same sweep Remember that a Bus Controller will only accept one non immediate command at a time For each Bus Controller the types of commands used and the relationship of the CPU sweep to the bus scan will determine how many commands are actually executed in one sweep In addition to these window times the sweep time estimate must include the time required by some commands to transfer the requested data to the CPU Each byte of data will add approximately 031mS to the CPU sweep time For non immediate commands this data will be returned during the next available window after receipt of data by the Bus Controller handling the command Programming Window Commands 5 7 GFK 0171 Idle The Idle command opens a window from the CPU to the Bus Controller but does not specify a task to be executed Some program uses for the Idle command are 1 to delay the CPU sweep 2 to update I O points that have been assigned register Reference Numbers 3 to receive communications from other bus interface modules
58. C is powered up later Thus if switch 4 is closed the Bus Controller will update outputs as soon as its powerup sequence is completed or as soon as the CPU goes into Run Enabled mode whichever is later With switch 4 open the onset of output updating is determined by program logic in the PLC Setup and Installation 2 7 GFK 0171 Bus Controller Reference Number Each Bus Controller in the Series Six PLC system must be assigned a Reference Number by setting the DIP switches on the rack backplane The Reference Number assigned to each Bus Controller is a beginning address in the I O Table where the Bus Controller s input and output data will be located This data includes diagnostics and command information Be sure each Bus Controller on an 1 O chain has a unique Reference Number Also be sure no Bus Controller on the Main I O Chain has the same Reference Number as a Bus Controller on the Auxiliary I O Chain References used by Bus Controllers must not overlap with those of any Genius 1 O blocks or of any conventional I O modules References Required 8 Bus Controller without Diagnostics Assign Reference Numbers for a Bus Controller without Diagnostics on a byte boundary 9 17 25 This type uses 8 references both inputs and outputs References Required 48 Bus Controller with Diagnostics Reference Numbers for Bus Controllers with Diagnostics must be assigned on 64 point boundaries unless Diagnostic Table
59. CK TRANSFER OCCURS TRANSFER OF A SINGLE VALUE DURING VO SCAN OCCURS DURING PROGRAMMER WINDOW During the 1 O scan portion of the CPU sweep one input per analog block and its circuit number are picked up by the CPU automatically from the block s assigned input references On successive CPU sweeps other inputs from the block overwrite the same input references As explained in chapter 3 logic must be used to copy the input values into other registers to prevent their being constantly overwritten Using Read Analog Inputs The Read Analog Inputs command reads input values from the direct access area of memory in the Bus Controller not from shared RAM This area of memory always contains the latest values from all blocks on the bus Since Read Analog Inputs supplies a register bank into which the analog input values are to be transferred circuits do not overwrite one another Only the data values are supplied one value per register no circuit number is supplied Logic for a Bus with More than 5 Analog Blocks If there are more than 5 analog blocks a High speed Counter or a Power Monitor Module on the bus the programmer window may be too brief for the Bus Controller to copy all the input data for those modules from its RAM memory into shared RAM A Read Analog Inputs command can be used to obtain input values as described above See chapter 3 for information about using analog blocks High speed Counters and PowerTRAC Modules
60. CKS USING THE BUS CONTROLLER OUTPUT REFERENCES Bus Controller Output References 9 Enabling or Disabling all Outputs from the Bus Controller 9 Pulse Testing Outputs 9 9 9 ho E pa EA EA ka ON QV tA t OO OO OO OO QO OO OO OO OO Clearing all Faults on the Bus Clearing a Specific Circuit Fault CHAPTER 10 TROUBLESHOOTING How to Begin 10 Identifying the Problem 10 APPENDIX A Expanded I O Addressing A Expanded I O Addressing for 8K and 16K Registers A Expanded I O Addressing for 1K Registers A 2 Expanded I O Addressing for 256 Registers A 2 APPENDIX B Bus Controller Compatibility B 1 Chapter 1 1 1 Introduction GFK 0171 The Series Six PLC Bus Controller is used to interface a Genius I O serial bus to the Series Six PLC The bus can serve up to 31 other devices including Genius I O blocks Hand held Monitors and other interface modules The bus can provide 1 O service to all types of Genius I O blocks It can also be used for programmed communications between the Series Six PLC and other devices The same PLC system may include several busses interacting with a wide range of I O devices as well as other PLCs and host computers Types of Bus Controller Two types of Bus Controller are available e a Bus Controller with Diagnostics IC660CBB902 which automatically sends diagnostic reports from Genius I O blocks to the CPU e a Bus Controller without Diagnostics IC660CBB903 which does not
61. Diagnostics Using DUS vontrouer input neierences GFK 0171 x an 1 Similarly Tung 7 creates a table that stores additional information for each of the 19 faults lt lt RUNG 7 gt gt ck e coe he e ke e dee je he de ce the e cfe e e e de e e ce de ke e e cde ke cde le e de e cde se de e de fe de fe de dee defe de je ce e e de e cde e che e de e je e che ce ce ce ee ck ec ck ox Registers 141 through 159 store Input Status bytes 5 and 6 from the Bus x Controller for each fault that occurs The first eight bits store whether the fault is internal to a block a discrete circuit or an s analog circuit Also the relative circuit number on the block is stored The second eight bits of each register are a description of what type m k AF ma mr de mee de pp e V he Wer edo do New Ub ado doo de CA Ui al V Vo Vo Ub do do T Veo c he e e e e e e se AA A e e de A je je e de de oe eoe e ce fe e e e A de de de de fe oe de je e e de de e e e de A se e oe de de e A e de e A de de de oe dde A AA A A eco n X x s FAULT FAULT HAS DESCRIP PO FEA PFATTT WRT AAS BR um OCCUR STORAGE 00909 TORO 00140 Can ar We w W o a W dom dl a A N WM ade OM Na sf de de ta iu SRC ADD TO TOP LIST LEN I 019 ow ew Programming for Diagnostics Using Bus Controller Input References 8 23 GFK 0171 Rungs 8 through 12 of thi
62. Diagnostics from the blocks are still available to the Hand held Monitor when this Bus Controller is used Both types of Bus Controller send the CPU diagnostic information about their own operation and the condition of the bus This book describes phase B Bus Controllers IC660CBB902 and CBB903 These enhanced modules are required for e A bus which uses any baud rate other than 153 6 Kbaud standard or which is than 2000 feet e A bus that includes RTD blocks or any Genius I O block that has more than 64 input bits or 64 output bits e Programmed communications from one CPU to another Redundancy more than one bus to the same group of I O blocks more than one CPU that is able to communicate with the same group of blocks or more than one Bus Controller controlling J O on the same bus Using Phase B Bus Controller with Phase A Products A complete programmable controller system may include both phase A and phase B Bus Controllers IC660CBB900 and CBB901 Phase B Bus Controllers can be used to replace phase A Bus Control lers or be added to a PLC system that already includes phase A Bus Controllers However only one phase B Bus Controller can be located on a bus with any Phase A products of any kind For more information about differences between Phase A and Phase B Bus Controllers see appendix A 1 2 Introduction GFK 0171 The Bus Controller is a standard rack mounted Series Six PLC module BOARD OK LED CO
63. E O vo y NS 4 a eO o 0 cos e ES 00 WO mh g S RE eco Odea a E a 10 ot x bd Oouwwo gt 4 T o ed og H 0 3 R mo BO M 8 9 82 2 o 8 8 KEE eg ral 20 27 BA S 4A2 S OO q Cl o O h oF bh uN T3 ED OO v al 03 B q YQ amp ui Sw 29 89 55 HSY 887 HD Sa co b a9 Udi rd iz NA oO a 0 m om s Y fj ra O ta E c o o dB 09 34022 o o m y Y 39 SEa B 48 Y a SB N ep 28 o9 28 8y8 ABBY g fi D ry ed O ha 2 OQ RS AUG U t n amp gt E l 50 O QD A y th S E ba pr O H o y Q H uc Y On we C ao boD amp cz T G4 TX j O C N c a O I b A iz v S9 gr gU ws 9 amp mmu ud d e o un e O 3 se t SH ae E e D 4 SE a yA B9B p 8 bo gN Ho ones fez BO 9g gS SPRS yi 33238 dg 2 3 ASTE f bo RB wm F E Oy S c m Y O o a f Q 8 e E J ej i ty Q gt S 5 pa o D 3 Y E d Eg 838388 AN 2 BSE Q oO 5 A A C CR peel mand a og AR us Qqu98 S gst amp ud O4 3 De ai S S ve Q nd t E S O v Q e Q N E o 8 va O D i 5 S 1 T fy LG aA o a N a a ee dd on Qe O mA ps O EA E E t 0 i e Ma 9 O3 3 Ee t o9 cd d a 60 t e Gu d a E i AO uto POET SO Yo 20 S JFO0S zz udo AE Ho 9 8 E ae S O Qood wo 05 MR A HRS gt Ou bb Y 3 E 9 UO X POA SB ms09 x s O p nH amp 6 A d Uv Ww z4 ty 0 Global Data 7 3 GFK 0171 Example Ladder Logic for Global Data The ladder logic that follows is an exam
64. GE Fanuc Automation Programmable Control Products Series Six Bus Controller User s Manual GFK 0171B July 1991 GFL 002 WARNINGS CAUTIONS AND NOTES AS USED IN THIS PUBLICATION WARNING Warning notices are used in this publication to emphasize that hazardous voltages currents temperatures or other conditions that could cause personal injury exist in this equipment or may be associated with its use In situations where inattention could cause either personal injury or damage to equipment a Warning notice is used CAUTION Caution notices are used where equipment might be damaged if care is not taken NOTE Notes merely call attention to information that is especially significant to understanding and operating the equipment This document is based on information available at the time of its publication While efforts have been made to be accurate the information contained herein does not purport to cover all details or variations in hardware and software nor to provide for every possible contingency in connection with installation operation and maintenance Features may be described herein which are not present in all hardware and software systems GE Fanuc Automation assumes no obligation of notice to holders of this document with respect to changes subsequently made GE Fanuc Automation makes no representation or warranty expressed implied or statutory with respect to and assumes no responsibility for the accu
65. Genius I O Blocks to the Series Six PLC GFK 0171 Transferring Analog Inputs to CPU Registers Because each analog input value stays in the CPU s input table for just one CPU sweep logic should be used to capture analog inputs from these references and move them into registers Example logic is shown below lt lt RUNG 1 gt gt KAKAKKKKKKKKKKKKKKKKKEKKKKKKKKEKKEKKKKKKKKKKKKKKKK KK KKK KK KKK KKK KKK RK RK KK KKK KKK KKK The rung below moves the input circuit number to a register R0001 It will be used as a pointer in the next rung to demultiplex the four analog input circuits and to store the data into a table of four registers 5 KAKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRKKKKRKKKK KKK KKK KEK BUS INPUT TABLPTR CONTRLR CIRCUIT ANALOG OK NUMBER INPUTS 10257 10353 R0001 MOVE RIGHT 8 BITS o lt lt RUNG 2 gt gt KAEKKKKKKKKKKKKKKKKKKKKKKKKKKK de de He de ke ke AAA KKK KKK KK KK KK k k k k k k k k k k k k k k k A ke ke e te ke k kkk The Source to Table Move instruction below takes the analog input data for each of the four input circuits from I0337 through 10352 and then stores it into a table starting at register R0002 Register R0001 contains the analog circuit number and is the pointer to one of the four registers in the table Six should be used for an RTD block LEN 6 KEKKEKKKKKKKKKKKKKKKKKKKEKKKEKKEKKEKEKKEKKEKKEKKKKKKKKKKKKKKKKKRKKKKKKKK
66. Inputs Read Status Table Reference Content pd po pod BA de je e E 1 E oJ Ah WN WN Ny APO Oo BOR WWW WWW WW m mM O OO O 4 2 4 7 4 10 4 10 PRD J tA CA ke M2 or r2 ma 00 m 00 OV N Un CA CA CA CA CA CA vi Content GFK 0171 CHAPTER 5 PROGRAMMING WINDOW COMMANDS cont Switch BSM CHAPTER 6 DATAGRAMS Types of Datagrams Supported Using Datagrams instead of Global Data Normal or High Priority Datagrams Programming for Incoming Datagrams Effects of Datagrams on the Genius I O Bus Maximum CPU Sweep Time Increase for Datagrams Assign Monitor Datagram Write Device Datagram Write Point Datagram Read Device Datagram CHAPTER 7 GLOBAL DATA Programming to Send Global Data 7 2 Example Ladder Logic for Global Data 7 3 Programming to Receive Global Data 7 5 7 5 7 5 qr N N Po3 d d UU rH nm E gt CO Un vv de 6A R Rh doro rac UJ ma Maximum CPU Sweep Time Increase for Global Data Using Global Data to Check CPU Operation CHAPTER 8 PROGRAMMING FOR DIAGNOSTICS USING BUS CONTROLLER INPUT REFERENCES Bus Controller Input Reference Formats Monitoring Bus Controller Status Checking for Bus Errors Detecting I O Circuit Faults Detecting the Loss or Addition of a Block Detecting Reference Number Conflict Detecting Execution of a Pulse Test Detecting a Force Condition on the Bus Storing Diagnostic Information in CPU Registers CHAPTER 9 PROGRAMMING COMMANDS TO YO BLO
67. K x d x U A OO u K KK KK OF x k 09 x x k k Qu x an O x SE x T A x d c rio I 4 A d kd p E i n 9 D s x E oo k A l m n t k 0 re f x ond x t x 4 E 4c x A eo n x K D KES x l x Y c x l HO k m gt amp p v l Y 9 UH l 0 k gt o b CQ Xx x 1 Q xK EE i n KA x K A E raf i io PE ES rpg oe tdt ov 4 P e 1 O SE S O j K B M Y E N Ri je rl u c 3 K l mw k O0 5 j x O e X O UW mk oo x n 4 O Mm O e ER S ORAK i O dior o Y m o o d k o E O E p x d K rd 9 o poox l k 0H lt A E o Q O x Hk 79 X koc Hoo Ok tropa e o ox Gd KD x i k MO H S T D d Q t Ls 2 PT E k D b Hx o ey de O zo E m e 0 E E S i B D qu 5 A A i o p d o d o x g B K K K l t i Sec bon E Td GA uk Ooo o m t e Dx ge x U x i k d v o9 x M 1 ti oO tS X O yo c x E hi n i x d d O0 le h x H i e y H 3 N x o K o ES k dt 4 ae MAHO o uao 7 P a O cn x cd i c4 gt Gz LO O 4 X U i d t og i p x H E A p e x a o w pi 0 M gay Hous f E totes 2 sae S ie F xK r x 1 BUG EN E db LV gt I2953 S hd S Iii T Om a i fc pe O A 0 eN Li k O OD O Q x e x G Ax K r H M nx ib DO p T X o Q x 9 v E CE E 2S Huet H EKURO re ae e 6 zu k cix i pa SAN an y a E e O Y 3 ON x Ed e o E 0 U O x i K H Ow K o k u O C Own x J x S x x 0 O O d HOO k 2 K gt O d ON N dk S
68. KK KKK KK KKRKEK BUS ANALOG TABLPTR CONTRLR DATA ANALOG OK IN INPUTS 10257 10337 R0001 Const SRC TO TABLE LEN 004 lt lt RUNG 3 gt gt KKKKKKKKKKKKKKKKKKKKKKKKKKKKEKKKEKKKKKKKKKKKKKEKKKKKKKKKKKRKKK KKK KK KK KKK KKK KKK This rung turns off the Bus Controller OK bit at the end of each CPU sweep so that the Bus Controller can turn it back on It is then used in the logic above to enable the analog data to be processed If the Bus Controller OK bit does not come back on the analog data is not processed KEKKKKKKKKKKKKKKKKKKKEKKKKEKKKEKKKKKKKKKKKKKEKKKKKKKKKKKKEKKKKKKKKKKKKKKKKKKKKKKRE BUS CONTRLR OK Const 10257 Const BIT CLEAR MATRIX LEN 00001 001 Logic is needed to transfer analog inputs only Analog outputs and discrete inputs and outputs are not multiplexed Interfacing Genius I O Blocks to the Series Six PLC 3 9 GFK 0171 Special Programming Required for Analog Blocks all types High Speed Counter Blocks PowerTRAC Blocks The application program may need to include logic to extend the programmer window time if the following blocks are assigned to I O references e 5 or more analog RTD or Thermocouple blocks e 5 or more PowerTRAC blocks IC660BPM100 version C or later e 1 or more High speed Counter blocks e 1 or more Power Monitor Modules IC660BPM100 version B or earlier This logic should be located before any logic that tries to access the input information
69. KKEKKKKKKKKKKKKKKKKKKKKKKKKKEKEKKKEKKKKKEKKKKKKKKRKKREK 0X 4 X HF o 00042 R00290 qs esl BLOCK MOVE pee E Y 01513 00013 00000 00031 00350 00006 08222 lt lt RUNG 3 gt gt KKAKKKKKKKKKKKKKKRKKKKKKKKKKKKKKKKKEKKEKKEKKKKKKKKEKKKEKKEKKKKEKKKKKKKKKKKKKKKKRKKRKKEK Rung 3 contains the Read Device header R0297 R0299 First register is the address where the received data will be placed Enter this in decimal The second register is the data length this value will be supplied by the Bus Controller Enter the third Block Move register in hex 201F Pressing the Accept key converts it to the decimal value shown in R0299 below 3 eee eee ee eee eee eee ee hehe A AAA A ce ce ce e e de ce e ce ce e ce ce ce AA ee ce ce ce A e cc e cc ce ce ce e ce oe e A e cde A oe A de oec cc se de ce ACA AA AA A ox 00042 R00297 A eee BLOCK MOVE J Ww 00350 00000 08223 00000 00000 00000 00000 0X 6 14 Datagrams GFK 0171 lt lt RUNG 4 gt gt KHKKKKKKKEKKKKKKKKEKEKKKKKEKKKKKEKKKKEKKEKEKKKEKEKREKKKKEKKEKEKKEEKEKKKEEKKKEKEKKEKKEKKKEKKEKKEKKKEK Rung 4 is entered in hex format Registers R0350 and R0351 contain the destination device absolute address in hex 40 Al hex register R0162 RO350 Al 00 hex 24320 decimal Lower byte 00 hex Upper byte destination device absolute address byte 1 LSB Al hex in this example RO351 00 40 hex 0064 decimal Lower byte destinatio
70. KKKEKE BUS COM ERROR BUS BIT ERROR 10258 00904 4 2 LATCH L RESET BUS COM ERROR 7 10001 T UL ERROR ERROR BIT I0258 00904 4 LATCH L Programming for Diagnostics Using Bus Controller Input References 8 19 GFK 0171 Rung 4 checks for the presence of any 1 O circuit fault by monitoring input bit 3 10259 the addition or loss of a block 10260 and 10261 or a reference number conflict lt lt RUNG 4 gt gt KKEKEEKKKKKKKEKKKKKKKKKEKKEKEKKEKKKKKKKEKEKKKEEKKKKKEKKKKKKEKKRKEKKKEKKKKEKEKKEKEKKEKEK This rung monitors the Circuit Fault bit Loss of Block bit Addition of Block bit and Address Conflict bit from the Bus Controller If any of these types of faults occur output 909 is turned on This is used in the next several rungs to cause the fault information to be logged into registers KEKKKKEKKKEKKKKKKEKKKKKKKKEKKKEKKKKKEKKKKKKKEKKKKEKRKEKKEKEKEKKKEKEEKEKKKKEKKKKKKKKKKKKEK CIRCUIT BUS A FAULT FAULT CNTRLR HAS BIT OK BIT OCCURRD 10259 10257 00909 t eaten EN o LOSS OF BLOCK BIT 10260 ADD OF BLOCK BIT 10261 ADDRESS CONFLCT BIT 10262 8 20 Programming for Diagnostics Using Bus Co
71. M failure Communications port shared RAM failure ot used Communications Port microprocessor failure not used Error Count register 3 is a sixteen bit rollover count of the number of CRC receive errors detected on the serial bus This count will roll over from 65 535 to 0 and may not be reset An FFFF value in Register 4 indicates that the scan time has exceeded 400mS which means that the Bus Controller must have missed its turn on the serial bus PY PPR PP Programming Window Commands 5 17 GFK 0171 Read Analog Inputs The Read Analog Inputs command is used to read all of the input values from an analog block and certain future devices during one CPU sweep Read Analog Inputs is an immediate command and can therefore always be executed Note that this command cannot be sent to a block that has been assigned a register Reference Number How Analog Inputs are Obtained by the CPU An analog block broadcasts current values for all of its input circuits each bus scan The Bus Controller receives these values and stores them in its on board RAM memory Once each CPU sweep during the programmer window the Bus Controller transfers the latest inputs for a specific analog circuit on the block into the portion of its RAM memory it shares with the CPU Each sweep the circuit number changes on a rotating basis BUS CONTROLLER MEMORY 042892 ONE ALL INPUT SHARED B C INPUTS To CL Ram K RAM FROM CPU MEMORY MEMORY ANALOG BLO
72. MM OK LED J M 1140 HHM CONNECTOR LJ 1 0 BUS WIRING TERMINALS uM A Bus Controller may be located in the CPU rack or in a regular or High capacity local I O rack that is a rack communicating with the CPU via a parallel chain Each Bus Controller draws 20 units of load one unit 300mW at 5 volts A phase B Bus Controller does not use 12 volts The only limit on the number of Bus Controllers used in a PLC system is the I O addressing capacity of the CPU LEDs The Bus Controller has two LEDs e BOARD OK shows the status of the Bus Controller e COMM OK shows the status of the bus Hand held Monitor Connector The Hand held Monitor connector on the Bus Controller faceplate provides access to all devices on the bus All Hand held Monitor functions except I O block configuration can be performed with the HHM connected to the Bus Controller Bus and block operation can be monitored circuits forced or unforced outputs Pulse Tested diagnostic messages displayed and faults cleared from a convenient central location Bus Wiring Terminals The upper four terminals on the terminal strip are used for the serial bus and shield wiring connections The lowest connector jumpers Shield Out to chassis ground The remaining connectors are not used Introduction 1 3 GFK 0171 The Bus A shielded twisted pair cable connects the Bus Controller to up to 31 other devices These may be Genius I O blocks Hand held Monitors or ot
73. No input data at CPU No output data at block Window commands to the Bus Controller cause a syntax error Window commands to the Bus Controller don t show any status change The Bus Controller is not communicating on the Genius I O serial bus The Bus Controller begins operating but does not seem to be operating normally 10 There are no functioning circuits on one bus but other busses are working 11 There are no functioning circuits on more than one bus in AUN 0 00 10 On 4 D Pr fei la 2 T Q a amp a O So i O E Eg pS 5 E G E o ba vad O Q Q E E 3 T 5 E P e i 9 ME q bb OG g 2 ej om r Q P C O E 2 E o ed ed I cd gt E we t C 2 O E E Q ne gt E V S OD nod i D 2 c oO i fel rd gt E 5 2 om O em ed A i A O Q bb O z Q A c O z 1 Q pu pa Q ey V ie Q ry t T Q v o O d B e A o gt y d 3 g 8 om a A e C D ope S i4 e un c Ma ra O 2 co Q Ao d d E p f Q 4 D i 0 o 2 Rar 7 Q i uo cb 3 Oo Q7 Bg Bn eps Li 3 v Oo E 0 n t 45 aa e D dH Og j amp 8 u P zm O r7 v b amp E qo o 2 2 O r zai i n a U T So 07 A x 3 HO S a9 o O q 5 RO e 2 A amp 9 d Yo o 9 OR E Bua e 4 0 E Q n 1 ta YO ml Q out orm 9 O WU H 3 m SEER eo g S An E d dmo aoe ds 1825038 8 2 9godU0 e98 2 B Aya d Q Mn O O O Y t DH STIS yxy OYA S EP O pa V oO a an 4 ui O 8 Y o p O E J d wv 2 A 4 m 7
74. OK and bus error bits maintains an output which can be used to flash an indicator light and clears the table pointer lt lt RUNG Q gt gt Start of Program RUNG 1 gt gt KKEKKKKKKKKKKEKKKKKEKKKEKKRKEKKKKKEKKKEKKKEKREKREKKEKKKKKEEKEKKKREKKEEKKKKEKRKEKEKKKKEKEKKK This program will monitor fault diagnostic information from the Bus Controller and establish a fault table in CPU register memory This program assumes the Bus Controller s starting address is 257 KKEKEKKKKKKKEKEKKEKEKKEKKKKEKKKEEKEKKEKKEEKKKKEKKKKEKKKEKKKEKEKKEKKEKEKEKEKKKEKEKKEKKKKEKKKKEKE NO OP NO OP NO OP NO OP NO OP NO OP NO OP NO OP NO OP Programming for Diagnostics Using Bus Controller Input References 8 17 GFK 0171 First the logic checks the condition of the Bus Controller by monitoring Bus Controller input bit 1 the Bus Controller OK bit This bit should always be equal to 1 6 Ml 41 5 4 3 2 1 byte number 33 25 17 9 bits I O references a pit __ bit Circuit EE ns Reference a DAE a bit __ Fault Type os DOE Circuit Number END O block _ bit 1 discrete 2 analog __ Input Output __ Fault Description 0 10 0 4 t0 fo 2S Bus Controller OK 10257 Bus Error 10258 Circuit Fault 10259 Loss of Block 10260 Addition of Block 10261 Address Conflict 10262 Pulse Test Active 10263 Circuit Forced 1
75. PLC System The Logicmaster 6 programming software LM6 is used to set up Expanded I O scanning and specify the use of automatic Genius 1 O diagnostics for the entire PLC system DESCRIBED IN CHAPTER HOW TO DO IT Enter CPU Configuration instruction as first rung in ladder Use LM6 Expanded Functions menu Use LM6 Expanded Functions menu Use LM6 Expanded Functions menu Use LM6 Expanded Functions menu Use LM6 Expanded Functions menu Enable disable Expanded functions Enable disable automatic diagnostics Enable disable Expanded I O scan Specify channel pairs for I O scanning Specify channel pairs for diagnostics Select length of the fault table for automatic diagnostics Default is 8 uncleared faults for system Specify locations of Bus Controllers that will report diagnostics Create internal status table for all I O points with diagnostics Make selection on LM6 Expanded Functions menu Select Y for Diagnostic Tables panded Functions menu Assign Bus Controller on 256 bit reference boundaries on LM6 Ex Programming for Analog I O If there will be analog I O blocks on a bus logic must be added to the program to store input values for each analog block If there are more than 5 analog blocks on the bus additional logic must be used to assure that all inputs are received by the CPU Copy multiplexed analog inputs from block s in put referen
76. PUs with different amounts of memory Appendix B Bus Controller Compatibility Compares the features of phase A and phase B Bus Controllers Related Publications For additional information refer to the following publications Logicmaster 6 Software User s Manual GEK 25379 This book is the primary reference for the Logicmaster 6 programming software It serves both as a software user s guide and a programmer s guide The first part of the book describes the operating features of the Logicmaster 6 software such as 1v Preface GFK 0171 file handling display tables and program printout The second part of the book defines ladder logic instructions for the Series Six and Series Six Plus PLCs Series 90 70 Bus Controller User s Manual GFK 0398 This manual describes the Series 90 70 Bus Controller and explains how to interface a Series 90 70 PLC to a Genius bus Series Six Bus Controller data sheet GFK 0025 This data sheet describes operation installation and specifications of the Bus Controller Genius I O PCIM User s Manual GFK 0074 This manual describes the Genius I O IBM PC Interface Module PCIM The PCIM module is used to interface a Workmaster or CIMSTAR I industrial computer or an IBM PC XT AT industrial computer to the Genius I O serial bus Series Five Bus Controller User s Manual GFK 0248 This manual explains how to set up a Series Five PLC Bus Controller and how to interface a Series Five PLC to
77. R0322 and 23 of the Bus Controller configuration table Register R0322 contains the Global Data address R00001 R0323 contains the number of data bytes to be transferred 2 KEEKKEKKKKKKKEKKEKKEKKKKKKKKKEKKKKKKKKKEKKKKKKKKEKEKKEKKEKKKEEKEEKEKKKKKKKKRKKKKK KKK KKK 00042 R00322 BLOCK MOVE J 00001 00002 00000 400000 2 400000 2 400000 2 400000 lt lt RUNG 4 gt gt KAKKEAKKKKKKKKKKKKKKKKKKKKKKKKKKKEKKKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKE Rung 4 can be used to stop the Global Data transfer If I0009 passes power to the right the value FFFF hex will be moved into R0322 beginning Global Data address register Then the value 00 is moved into R0292 communications status KEAKEKEKKKEKKKKKEKEKKKKKKKKKKKKKKKKKKKKKKKEKKEKKEKKKKKKKEKKEKEKEKKKKEKEKKKKKKKKKKKRKKKKKKRKRKK I0009 Const R00322 Const R00292 A MOVE Bo j A MOVE B j FFFF 0000 lt lt RUNG 5 gt gt KAKKKKKKKKEKKKKKKKKKKKKKEKKKKEKKEKKEKKKKEKEKKKKKKKEKKKEKKKKKKEKKKKKKKKKKKKKKKKKKKRKKKKKKE DPREQ instruction opens the communications window It should be tied to left rail KKKKKKKEKKKEKKKKKKEKKKKEKEKEKKKEKEKKKKEKKKKKKKKEKKKKKKKKEKKKEKKKKKKEKKKKEKKKKKKKKKKKKKKKKEKK R0290 DPREQ lt lt RUNG 6 gt gt KHEKKKKKKKKEKKKKKKKKKKEKKEKEKKKKEKKEKKKKEKEKKKKEKKEKKEKKKKKKKKKKKKKKKKKEKKKKKKKKEKKKKKKKEKE Rungs 6 and 7 implement the increment counter in R0001 which is transmitted on th
78. R03265 to R03328 R03329 to R03392 R03393 to R03456 R03457 to R03520 R03521 to R03584 R03585 to R03548 R03549 to R03712 R03713 to RO3776 RO3777 to RO3840 R03841 to R03904 RO3905 to R03968 R03969 to R04032 R04033 to R04096 R04097 to RO4112 R04113 to R04116 R04117 to RO4119 R04120 R04121 to Rxxxxx R08123 to R08192 R16315 to R16384 O 0001 to O 1024 0001 to 1 1024 O1 0001 to 01 1024 11 0001 to 11 1024 02 0001 to 02 1024 I2 0001 to 22 1024 03 0001 to 03 1024 13 0001 to 13 1024 04 0001 to 04 1024 14 0001 to 14 1024 O5 0001 to O5 1024 15 0001 to 15 1024 06 0001 to 06 1024 16 0001 to 16 1024 07 0001 to 07 1024 I7 0001 to I7 1024 O8 0001 to O8 1024 I8 0001 to 18 1024 O9 0001 to O9 1024 19 0001 to 19 1024 OA 0001 to OA 1024 IA 0001 to IA 1024 OB 0001 to OB 1024 IB 0001 to IB 1024 OC 0001 to OC 1024 IC 0001 to IC 1024 OD 0001 to OD 1024 ID 0001 to ID 1024 OE 0001 to OE 1024 TE 0001 to IE 1024 OF 0001 to OF 1024 IF 0001 to IF 1024 Bus Ctr bit map User registers Real time clock Fault table pointer Fault table entries Computer Mailbox 8K Computer Mailbox 16K S N 8 A 1 n a1 Y 1 24 are mapped into tne 3 A A A o 17 102 it 0 A e Auxiliary discrete references A 1 e e3 A 3 gs 4 S0 un m En MU e 2 q Z EA 7 Z WD As a 2 2 rad O 330 8 095g 9 98 p EB See TEENS En 3838 do9o S95 E 8 5 S 299 29
79. Run mode or when outputs to the block are enabled Some versions of block firmware are responsible for this effect 8 16 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Storing Diagnostic Information in CPU Registers The CPU will automatically create a fault table in register memory if DIAGNOSTICS ENABLED is set to Y on the CPU Configuration Setup Menu see chapter 4 Alternatively logic can be used to copy individual diagnostic reports from the Bus Controller s input references as described below Because of its complexity this method is not recommended Creating Diagnostic Tables The information in the Bus Controller input references changes each CPU sweep The following example shows program logic to copy the content of these references to register memory Ladder Logic Example This example logic captures and displays diagnostic information from one Bus Controller for which automatic diagnostics is not enabled For a system with multiple Bus Controllers additional logic would be needed The logic creates a table which will store up to 19 faults at a time The logic monitors Bus Controller input reference bit 3 Circuit Fault bit 4 Loss of Block bit 5 Addition of Block and bit 6 Address Conflict If any of these bits is equal to 1 during a CPU sweep the program turns on an output which causes fault data to be logged into registers The example program also monitors the Bus Controller
80. See chapter 6 for information The Idle command takes approximately 1 2mS to execute if there is no pending operation to delay its Starting or data transfer to delay the window s closing The Idle command is immediate it is always accepted Once the Idle command is accepted if the previous command requested data from a device on the bus or if an incoming Datagram has been received the window will remain open while the data is transferred to the CPU Similarly the Bus Controller will transfer all Global Data it has received during the previous CPU sweep to the CPU during the first available window in the program If the Idle command is first in the sweep Global Data will be transferred at that time adding 031mS per byte to the CPU sweep Command Block for the Idle Command The Idle command uses only registers 1 3 Command Block format for Idle is Register 1 Bus Controller Reference Number plus 1000 for a DPREQ Register 2 Command number 1 Register 3 Status Code supplied by the Bus Controller Delaying the CPU Sweep More than 5 Analog Blocks The Idle command can be used to delay the CPU sweep at a selected place in the program For example a delay might be programmed if there were more than 5 analog blocks on the bus This delay would allow the Bus Controller enough time to update all analog input values in its shared RAM When used for this purpose the Idle command should be located before any I O update in the program
81. a from the block in 16 byte increments When all the data has been received the Bus Controller transfers it to the CPU at the start of the next available CPU Bus Controller window and sets the Status Code to 2 Done Command Block for the Read Configuration Command Command Block format for Read Configuration is Register 1 Bus Controller Reference Number plus 1000 for a DPREQ Register 2 Command number 2 Register 3 Status Code supplied by the Bus Controller Register 4 Ten bit beginning address of the device from which configuration data is to be read If the data is requested from an outputs only block not outputs with feedback bit 15 MSB must be set to 1 For an inputs only block bit 15 must be 0 Register 5 Pointer to the group of registers in the Series Six CPU where the configuration data will be placed after the command executes Programming Window Commands 5 9 GFK 0171 Data Returned by a Read Configuration Command The content of the reply message depends on the type of device being queried Read Configuration Reply contents for the Series Six PLC Bus Controller are shown on the following pages Read Configuration Reply messages for I O blocks are defined in the Genius I O System User s Manual Data Returned by a Read Configuration Command to a Bus Controller If the command requests the configuration of the Bus Controller the Bus Controller immediately returns to the CPU its software revision numbe
82. accommodate both the input data and the output data Inputs are stored before outputs and the input data and output data must each begin on a register boundary For example if a block with 8 inputs and 8 outputs were assigned to register memory two registers would be required one for the inputs and one for the outputs If the beginning address assigned to the block was R0129 the input data would be occupy the first 8 bits of R0129 and the output data would occupy the first 8 bits of R0130 When the following blocks are assigned to 1 0 memory they may require some special ladder logic to avoid premature access to data in the input table while the Bus Controller is still updating that input data 4 Input 2 Output Analog Blocks Current source Analog Blocks RTD Input Blocks Thermocou ple Blocks PowerTRAC Blocks See page 3 9 for more information Programming Required for Blocks Assigned to Register Memory Automatic diagnostics and automatic I O update are not performed on blocks assigned to register references References in register memory are NOT updated during the I O scan portion of the sweep A window must be opened using a DPREQ or WINDOW instruction at the beginning of the sweep to update I O points assigned to register memory An idle DPREQ or WINDOW instruction can be used To obtain fault reports from a block assigned to register memory a Read Diagnostics Datagram must be sent to the block using the Send Datagram command
83. ailbox For most applications a DPREQ will be used if the system is set up for Normal I O addressing main and auxiliary I O chains only A WINDOW instruction will be used if the system is set up for Expanded channelized I O addressing Format of the DPREQ Instruction The ladder logic instruction for the DPREQ has this format Register where the address is stored Address of the device communicating with the CPU Do not use a DPREO in a system with Expanded addressing It would be broadcast to the specified address on all channels If that address were used for more than one intelligent device for example more than one Bus Controller conflicting replies would be received 5 2 Programming Window Commands GFK 0171 Format of the WINDOW Instruction The WINDOW instruction is similar to a DPREQ except that it specifies both an address and a channel When the CPU encounters a WINDOW instruction in the program it opens a communications window to the device at the specified address on the specified channel The ladder logic for the WINDOW instruction has this format First register in the Command Block or Computer Mail Box Const R0800 pm WINDOW Address Comm Block 0601 Address of the device communicating with the CPU The WINDOW instruction is available with Logicmaster 6 software release 3 0 and later It requires a CPU with microcode version 110 or greater Using the Comput
84. are on different busses there will be a bus conflict resulting in erroneous I O data for the overlapping references This problem may be difficult to detect when the system is operating If multiple Bus Controllers are installed downstream of an I O Transmitter module and any references assigned to the I O blocks on those Bus Controllers overlap a system parity error may result and the system may shut down I O References Used by a Block 4 Input 2 Output analog blocks and RTD Input blocks use 24 references in the input table 4 Input 2 Output analog blocks also use 32 references in the output table Analog block data format is shown later in this chapter The references needed for a discrete block depend on the number of circuits it has and whether it has all inputs all outputs or both Point 1 on a discrete block occupies the lowest numbered reference assigned which is also the block s beginning address e All inputs discrete blocks or I O blocks configured as inputs only blocks need one reference in the input table for each circuit on the block e All outputs blocks or blocks configured as outputs only blocks use references in the output table only Discrete blocks with both inputs and outputs will use references in both the Input and Output Tables beginning at the configured Reference Number This includes blocks configured as combination blocks even if the I O circuits on the block are set up as all inputs or all outputs
85. ask for bits 8 15 Upper byte OR mask for bits 8 15 2 ES D AN P T s D Q e Q D o B Wy Lui pa Q Nr eb JE D T E T O zi w d bet C E v V d q ed 3 B E 2 gt a p A A D z 4 r i C z um mi gt D gt d O S O a 3 EE i t Do a E mb pe A p o wo bD T oO what Uv e d S9 amp ZEN js E 5 id P y C a A A g D d O O u Q g 9 By g E 4S ge PE g P 2 A Efi q d A bh E 0 E hs O pd QU BE Ss gaud 38 g E Ep u E 5 F n JL 1 d Abg g o T4 8 p cp a AS 38 De x 3 S ca ri AQ o b C aa O q d cd eb a z b O a d o E A o ja 8 9 028 9 EE 5 D a Q 3 gt AY A 1j rer 9 gt gt Y w t o a S 9 s 4 oO g 2 d o gt a 9 2 a Bi gt E A Q e 9 amp pa E 9 S 4 2 d yq 8 553 Bs d Q sS sot TH 4A y B Eq 0 2 92 o Oo 5 Q 4 e 8 2 Ss tz B Du oR BE D EX pe CESA o H g Y Q9 S920 0 E E B uu y Busy d 05 y wu 889342585581 8 E y 0 f 5 e E a D g gr E OH Bo 4 E gp E t 0 d E g 8 42 EE 38583330850 S wg nOn AAREJOQA A ER x Q d 9 0 S 6 2 a r gt O e aa g BH Adra SS s ba bh th M G t t4 R ed sgag dg g J o0 bi E n Uu Y Y v v uU U X ste EB b 5902 BS 5 bd 4 mn gos o 0 AAA AAA E ERA QU O 2l go go Ihe content of the Iirsf three 1 Data returned by Te Datagrams 6 13 GFK 0171 Example Ladder Logic for the Read Device Datag
86. ay be assigned either Normal Priority or High Priority During one bus scan there may be one Normal Priority datagram followed by up to 31 High Priority Datagrams or up to 32 High Priority datagrams sent by the devices on the bus If the bus will also be used for I O block control Normal Priority datagrams are recommended to allow other messages such as fault reports which the system handles as Normal priority Datagrams to get through In addition Normal Priority Datagrams ensure that bus scan time is only modestly delayed for communications Bus scan time affects the response time of any I O data on the bus If there are 1 0 blocks on the bus use High Priority only if the Datagram transmission cannot be delayed Normal Priority will work satisfactorily except when there are many devices attempting to send Datagrams simultaneously Datagrams 6 3 GFK 0171 Programming for Incoming Datagrams The Bus Controller may receive Write Point Read Device or Write Device Datagrams from other interface modules on the bus The Bus Controller will transfer the received Datagram message to the CPU during the next open CPU Bus Controller window To open a window a DPREQ or WINDOW instruction with the address of that Bus Controller must be present in the program If the application program does not include any window commands to the Bus Controller an Idle window command can be used It is important to handle incoming Datagrams efficiently
87. bit 33 If bit 33 was 1 on the previous sweep a Bus Controller fault is triggered If it was 0 on the previous sweep no additional fault occurs Because bit 33 is an accurate reflection of the Bus Controller state on the previous CPU sweep the program can monitor Bus Controller status by reading this bit The program should NOT clear output bit 33 8 6 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Checking for Bus Errors To have the program detect errors such as an open bus or excessive noise in the bus use logic to monitor bit 2 of the Bus Controller input references Byte 1 unes Serial Bus Error This bit is normally set to 0 it is set to 1 if 1 the Bus Controller receives ten or more corrupted messages within a 10 second time period It will be set to 0 again when the error rate falls below ten errors in a 10 second period If bit 2 is continuously set to 1 there are multiple errors from one or more devices The bus may continue to operate in spite of these errors 2 the Bus Controller does not obtain its turn on the serial bus at least once every 500mS This bit is 1 for at least one scan It is set to O if the Bus Controller is able to transmit data on two successive scans If bit 2 is equal to 1 for several scans it means the Bus Controller cannot access the bus due to duplicate Device Number assignment or bus scan greater than 500mS Programming for Diagnostics Using
88. ces Read all inputs from an analog block during the same CPU sweep Store inputs from more than 5 analog blocks on the same bus Use program logic to read one input per sweep into registers Program Read Analog Inputs command using DPREQ or WINDOW instruction Program Read Analog Inputs command using DPREQ or WINDOW instruction 1 12 Introduction GFK 0171 Additional Programming Capabilities The program may also include logic to do the following DESCRIBED FEATURE HOW TO DO IT IN CHAPTER Pulse Test discrete outputs from program Set Bus Controller output reference bit 4 Read or write configuration data for the Bus Use DPREQ or WINDOW instruction with a Controller or a block Read or Write Configuration command Read the I O type assignment of any point on the Use DPREQ or WINDOW instruction with a bus Read Configuration command to the Bus Con troller Use DPREQ or WINDOW instruction with a Read Configuration command to the Bus Con troller Use DPREQ or WINDOW instruction with a Read Diagnostics command to the Bus Control ler Use DPREQ or WINDOW instruction with a Read Diagnostics command Use DPREQ or WINDOW instruction with Read Status Table command Determine whether outputs are disabled to a de vice on the bus Determine error rate on bus or bus scan time Determine the current fault status of the Bus Controller or a block Read
89. ck the Bus Controller first reads the intended configuration data from the CPU registers during the CPU Bus Controller window and schedules background Write Configuration messages to the block The Bus Controller returns the Status Code 1 In Process to the CPU then closes the window The Bus Controller accepts no more non immediate window commands from the CPU Once message transmission begins the Bus Controller sends the configuration data to the block in 16 byte increments The block does not use any of the new configuration data until it all has been received No new commands can be sent to the block until the operation has been completed When all the data has been sent the Bus Controller changes the Status Code to 2 Done at the next available DPREQ or WINDOW instruction then closes the window NOTE When performing a Write Configuration command to the Bus Controller pay special attention to the output enable disable bits to ensure that these are changed only when that is the intent Outputs should be disabled if there are no blocks on the bus Command Block for the Write Configuration Command Command Block format for the Write Configuration command is Register 1 Bus Controller Reference Number plus 1000 for a DPREQ Register 2 Command number 3 Register 3 Status Code supplied by the Bus Controller Register 4 Ten bit beginning reference address of device to which configuration data is to be written If the data is written to
90. d not used Ip Hou eferences jut R vu e a ng for Diagnos qQ Programmi mi 65 Q e Pp oe Hc 88 o 3 9 rd Eo N vu amp o a V e P iic n V VO Tr ed d b 4d rc 0 o a tE a O runs n XA p Vo io Y ed an d d qo a p pw Q n Q d amp wc e n d m Eb 4 TN M n D O ne pad D Y Y e vd 4 a a 2 gt A n H la f e d D O Dog 0 U i un oD Sn a D CG e ord A E 9 3 Ne a B p B 36 4 c V u A 4 o B amp B BISSSESS Fe 37 ae rd 5 lt e e es eS e e f am gt ad Q 3 BB T E B e TE i r a O em E ct n A kH f O Y uu g 4 e N p Wm SS 2 Lo Ss v Y D s fx ec ri ed du E O0 AO oo o a N N q S vw e c O OO 3 2 Jal 33333 sz eg Zt p f vend o Q T Q Pens ne se Be S ARABS nga d m es 0 00 U c a a Dd D ce o 09 2 Te i 3 a 3 8 O 5 Q i 4 E ry h 7 9 EB ada e E O 8 zi poser H 0 Da Z D PePeee Pj un ii i o 40 n p 0 gH Alsgss2d 2 m GE ee E y oe S EEERER yes 28 7 82 EF A u a t ob o ob ob 5 p 2 0 o s cr o 23 ES E nee qe nme mas Ea e O hs ng n y 38 3g LE FIR o E o 46 Sa 54 acme ESI E e HA Ay ES Gok OS Mm aed E E 33m m We E E E e xum TN ha e pum b aman ry a m D H cn 2 42 ia E 3 3 O 9 en 5 E o MES o Os J 343050 oO Qa on i joo x o B gt 882585 Sd 21 95 d r 7 n NO rate V E a B a a 8 34 a 2 E e Y S o lo uU r 4 f 4 c Dp O np 4 o3 rd d Ad
91. d Block for the Assign Monitor Datagram Command Block format for the Assign Monitor Datagram 1s Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Bus Controller Reference Number Command Number 12 Send Datagram Status code supplied by the CPU If the message is sent to one device Assign Monitor is a non immediate command the status register will indicate done when that device acknowledges the message However if FF is specified in register 4 Assign Monitor is an immediate command register 3 is set to done as soon as the message is sent with no guarantee that the devices have received the message the Device Number serial bus address of the block which should issue extra fault reports If all blocks on the bus should issue extra fault reports enter FF hex in this register If only some blocks should report to the faults to the assigned monitor for example to minimize bus scan time program separate Assign Monitor commands to each one the location in register memory of the Assign Monitor Datagram header plus data to be sent See register n below Length of message 1 byte Command code Lower byte 08 hex for Assign Monitor Datagram Upper byte 20 hex for normal priority or AO hex for high priority Content of the Assign Monitor Datagram Message length for the Assign Monitor message is 1 byte Register n The least significant byte
92. e bus as Global Data KREKKKKKKKKAKKKEKKEKEKEKEKKEKERKKKKEKEKEKKEKKKKKEKEKEKEKKEKKKKEKEKEKKKKEKKKKKKEKKKKKKKKKKE Const R0OO288 A MOVE B 0001 lt lt RUNG 7 gt gt R0001 R0288 R0001 A B C RUNG 8 ENDSW lt lt RUNG 9 gt gt ENDSW gt C o 2g agy BgcPBS 8 ES SHa ys HABO g 23 S85EH 9o9B589g88 bo Q y M C A S n 7 d c 5 Cu H U c o e a M an das oO amp SoU Qo w mun T 2558 Sey aoe a o gt E B 0 3 6 a bb ES zi Ei aa P os O 8 3 i P O m 5 UY 4 amp ay 8 Z d z H a e E A SA v z o 9 amp 8 ES O D SuB8 5 S0 O Y uy Bot 9055 8 w BZ o 8 8 bs B O gaS oS a a O ED B Mu o m 4E doo 2 O gQ US wuuw ou oz E Q i 200 845 SES cod ga oo O B ou dao a p A nnn E F p us O 3 Bi i BEBE D p o d Ep ESS Bat gt read an S Be OD q ono sa DOSa3390205 d e eod H f E VO S e O C Ly A D uv 0 poe Y H ES e A40 E eS Pr T b 2 P B Ev 5 Aaga A EHESS pa ad QA E a d v9 ty 3 C a 696d 2705 A goa a io O95 MA CE O 82 0 2 42 2g H o s o Q O x mam 0 ya Ly G g L Ag A os dtc w J oe bp O 4 e 3 fu 1 Y 23 Ro mego ux om O 5 4 x r gt ed 9 g q s OH 9 m 28330 SS 9 e v soa pee s OBRO Beye g 09 2 29 8 A p el mi y D p un S SESE sp2 S8 MEHOES 35 3 3 A SSe 28488 E assume gt E mUaHE X S B S Q QO amp 8 Ha rm t H 89 ma rg d bb E o O Nt 1 e E OQ O 1 o ex b 3 a z
93. e of more than one application program at different times each program should be set up as described in this chapter Begin by starting up the Logicmaster 6 software and loading the application program into programmer memory The CPU Configuration Instruction To access the Expanded Functions the CPU Configuration instruction must be placed in the ladder logic program When this has been done the following line should appear as rung 1 of the program SERIES SIX CONFIGURATION DATA If there is already a CPU Configuration instruction in the program do not enter another one With the CPU Configuration instruction in the program the screens shown on the following pages can be used to set up and display information about the Bus Controllers and Genius I O in the PLC system If you change any of the setup screens for a program that was already stored to the Series Six CPU the program must be stored to the CPU again for the changes to be used Expanded Functions Menu Press F7 Expanded Functions from the Supervisor menu to display the Expanded Functions menu L M OFFLINE FUNCTION CPU CONFIG Display Modify CPU Configuration I O FAULTS Display Clear Genius I O Faults MSD FUNC Display Modify Machine Setup Data 90 70 CONFIG Display Modify 90 70 operands 90 70 DSPLY Display 90 70 operands and status SUPERV MENU Return to Supervisor Menu CPU I O 90 70 90 70 SUPERV 1CONFIG 2FAULTS 3 5CONFIG 6DISPLY 7 8 MENU This menu is used to s
94. e on the bus which is capable of sending Global Data will return this information it does not actually have to be using this feature Programming Window Commands 5 21 GFK 0171 Switch BSM Use the Switch BSM command to cause a Bus Switching Module to select a bus in a dual bus system The program must already know which bus is currently selected The CPU may issue the Switch BSM command at intervals to ensure continued proper bus switching capability If the command is successful the CPU will report a Loss of Block diagnostic for the BSM Controller block and for any other block on the same bus stub If the dual bus system includes a second Bus Controller in the same CPU or another CPU controlling the other bus that Bus Controller should report an Addition of Block diagnostic for each of those blocks If the BSM position is currently forced by the Hand held Monitor the command will be ignored It is also ignored if the block does not control a BSM Command Block for the Switch BSM Command Format of the Command Block for the Switch BSM command is Register 1 Bus Controller Reference Number plus 1000 for a DPREQ Register 2 Command number 11 Register 3 Status Code supplied by the Bus Controller Register 4 5 bit Device Number of the discrete block that controls the BSM Be sure the block is the BSM Controller this command does not check the block s configuration Register 5 Pointer to the register in which the desired BSM
95. ead write For Bus Controllers IC660CBB902 and 903 only register 22 contains the Starting register address for the Global Data in the resident CPU The Bus Controller defaults register 22 to FFFF hexadecimal indicating no Global Data to be sent See chapter 7 for information about using Global Data Register 23 Read write For Bus Controllers IC660CBB902 and 903 only register 23 contains the length in bytes number of registers times 2 to be transmitted from resident CPU to another CPU on the bus using Global Data Maximum is 128 bytes 64 registers At powerup the Bus Controller defaults register 23 to 0 5 12 Programming Window Commands GFK 0171 Write Configuration The Write Configuration command is used to send configuration data from the CPU to the phase B Bus Controller or to a block on the bus lt cannot be sent to another bus interface module or to a block that has been assigned a register Reference Number When sent to the Bus Controller this command is immediate completed during the Bus Controller window The Write Configuration command can also be used to 1 enable or disable outputs from the CPU to devices on the bus 2 start or suspend Global Data transfer see chapter 7 I O blocks can be configured or reconfigured using this command However each block must first have its Reference Number and Device Number serial bus address entered using the Hand held Monitor If configuration data will be sent to a blo
96. ed in relative references 1 16 Data for output 2 is stored in relative references 17 32 Their data formats are identical and are in two s complement format They represent a scaled engineering units value Refer to the Genius I O System Uses s Manual for information about scaling analog data Analog Input Data During each Genius I O bus scan analog blocks send data from all of their input circuits to the Bus Controller and the Hand held Monitor During the CPU sweep the CPU reads from the Bus Controller the value of one analog circuit per block This analog value is placed in the block s input references as shown below 17 msb lsb i mc a an o Circuit data 0 not used __ CLECULE number 0 3 or 0 5 References 1 16 store the circuit data The content of these bits depends on whether the input is configured for Normal Input Mode or Alarm Input Mode Alarm Input Mode which is a feature of the 4 Input 2 Output Analog block only replaces actual circuit data with alarm data Interfacing Genius I O Blocks to the Series Six PLC 3 7 GFK 0171 In Normal Input Mode bits 1 16 store the two s complement engineering units value of a circuit Bit 1 is the LSB and bit 16 is the MSB 2 sea m a s lsb E an nT Engineering units for the circuit indicated Circuit Number In Alarm Input Mode bits 1 2 store the Alarm Input mode data for the circuit Bit 1 1 indicates that the current input value exceeds the p
97. eference bit 7 Byte 1 ei vr el st at st al Pulse Test Active Bit 7 is set for one CPU sweep after a Pulse Test is commanded by the CPU It remains 1 until all discrete I O blocks configured for the Pulse Test have completed the test To determine whether any faults have been generated as the result of a Pulse Test Failed Switch Loss of I O Power Short Circuit or No Load monitor bit 3 Circuit Fault Programming for Diagnostics Using Bus Controller Input References 8 15 IIA e e M GFK 0171 Detecting a Force Condition on the Bus The Hand held Monitor can be used to force circuits which removes them from program control Such a force condition must also be removed with the Hand held Monitor The program can detect whether a force exists by monitoring Bus Controller input reference bit 8 If this bit changes to 1 the program can alert an operator that a forced condition exists on the bus The operator can remove the force with a Hand held Monitor Byte 1 eroi erst at st ta HHM Force Active Bit is equal to 1 if any discrete or analog circuit is forced No indication is provided as to which I O block or reference contains the force condition If forces or unforces occur while the CPU is in Stop mode or while outputs are disabled to the block being forced or unforced this bit may not reflect changes and may not be accurate when the CPU is returned to
98. elect several different Expanded CPU functions not all are related to Genius I O diagnostics 4 2 Automatic Diagnostics and Fault Clearing GFK 0171 CPU Configuration Setup Menu The first step in customizing the application program is to match it to the intended characteristics of the system This is done by completing entries on the CPU Configuration Setup Menu To access this menu select F1 CPU Configuration from the Expanded Functions menu L M OFFLINE CP CONFIGURATION SET UP MENU EXPANDED I O ENABLED Y Y N SCAN BEGIN RANGE CHANNEL 0 POINT 1 END RANGE CHANNEL O POINT 1024 GENIUS I O DIAGNOSTICS ENABLED Y Y N DIAGNOSTICS DIAGNOSTIC TABLES Y Y N B C gt POINT FAULTS N Y N DIAGNOSTIC RANGE LIMIT 7 0 7 CHANNELS CPU REGISTER SIZE 2 REGISTERS FAULT TABLE LENGTH 8 ENTRIES BUS STATUS CONTROL BYTE LOCATION 993 COMPUTER MAILBOX ENABLED B C 1 MAP 2 The CPU Configuration Setup Menu displays entries for selecting e Expanded I O scanning e Automatic diagnostics and fault clearing e The Computer Mail Box When the CPU Configuration function described on the previous page is placed in the program it uses the entries currently selected on this menu Check the entries on the screen against the descriptions in this chapter Diagnostics Enabled Setting this entry to Y causes the CPU to create a fault table to automatically store Genius I O faults The table will occupy the number of register
99. er B 1 c a veni am AL TL a Of ESCRR lt 8 y Teo fa o 2 amp og Y E 3 o 4 A 5 p Nm i P Q c i E e fer a n ODO d 2 VY 2 A 3 5 S C1 e st fn c4 N vmi e ve Y 2 1 1 ntrolier Power tHows tnrougn tne m Tw 4 nth other modules in the 1 13 O 1 1 21 11 gt s lad varticulariy for ov INUIDDCI 1S airea NAT 1 2 e 11 a ontroller 1s installed in the correct slot vic AT a 1c T a fm DUS v ure th 4 8 es T D The Window Comm Problems 4 rT Troubleshooting 10 3 GFK 0171 Be sure wires to the Serial 1 Serial 2 terminals on the module are not crossed or shorted together or to ground Check the baud rate Check the Device Number serial bus address assigned to the Bus Controller against the intended Device Number from your records of system configuration New Bus Controllers are shipped from the factory already set up to use Device Number 31 Use the HHM to compare Device Numbers and Reference Numbers Check the Bus Controller s Outputs Disabled bits using Read Configuration command to the Bus Controller Also check Bus Controller output 1 Disable All Outputs Problems 9 12 9 The Bus Controller begins operating but does not seem to be operating normally Be sure serial bus wiring has been completed in a daisy chain fashion Make sure the communications cable is not close to high voltage wirin
100. er Mailbox The Computer Mail Box is an automatic communications window that operates when the CPU is in Run mode The only ladder logic required to enable the Computer Mail Box is the CPU Configuration instruction as the first rung in the program Use of the Computer Mail Box must be set up on the CPU Configuration Setup Menu as described earlier Any device that needs to communicate with another can place a command and window address of the other device in the Mailbox At the end of the CPU sweep the CPU detects that a command is waiting and either reads data from the Mailbox or places data in the Mailbox to be returned to the requesting device The window that allows the Bus Controller to access the Mailbox is generated automatically by the CPU at the end of the CPU sweep It is the last Executive window after the PDT DPU and CCM windows It has a 5mS timeout length The CPU continues to open windows to the specified address every sweep there is a valid address in the Mailbox To stop opening windows the address must be cleared out of the Mailbox by the device that accepts the window or the device or program that set up the address in the Mailbox Although one of the registers in the Mailbox contains a status code the CPU will not examine this register and will not automatically close the window The Computer Mail Box always uses the last 70 consecutive registers out of the total number available The location of the Computer Mail Box registers de
101. f test Byte 1 er E st sp al st 20 3 Bus Controller OK If this bit fails to become 1 at powerup and remain 1 with power applied the Bus Controller may need to be replaced If bit 1 is 0 none of the other Bus Controller input reference bits have meaning The way the program can monitor the Bus Controller status data will depend on whether DIAGNOS TICS ENABLED has been set to Y on the CPU Configuration Setup Menu and whether the Bus Controller is included within the range of I O specified for diagnostics scanning Monitoring Bus Controller Status Diagnostics is NOT Enabled If the Bus Controller is not set up for automatic diagnostics as defined above the ladder logic can test bit l once every CPU sweep then clear it using a Bit Clear instruction Monitoring Bus Controller Status Diagnostics IS Enabled If the Bus Controller is set up for automatic diagnostics the CPU automatically checks bit 1 during the diagnostics portion of the sweep V EXECUTIVE WINDOW PROGRAM LOGIC SOLUTION I O SCAN DIAGNOSTICS lt Bit 1 checked here CLEAR BUS CONTROLLER OK lt Bit 1 cleared here BIT bit 1 Programming for Diagnostics Using Bus Controller Input References 8 5 GFK 0171 If bit 1 is 1 indicating that the Bus Controller has passed its self test the CPU automatically clears it at the end of the CPU sweep This sequence of diagnostics and bit clearing by the CPU means that bit 1 will always a
102. f the CPU register size is either 8K or 16K diagnostics can be stored for 16K inputs and 16K outputs If the Scratch Pad has already been set up this entry should be correct for the CPU If it is not correct change it by entering 256 or 1 for 1K or 8 for 8K or 16 for 16K Fault Table Length If DIAGNOSTICS ENABLED is set to Y this entry specifies the size in registers of the area in CPU memory where faults will be stored The length of the fault table determines the number of faults that can be stored at the same time A fault will remain in the table until it is cleared by the program or from the computer keyboard If the table became full there would be no room for additional fault storage and the overflow faults would be lost No new faults would be stored until the table was cleared The default fault table length is 8 Each fault occupies 10 registers of memory The default Fault Table size therefore is 80 registers Automatic Diagnostics and Fault Clearing 4 5 GFK 0171 Each entry in the Fault Table has the following format Register 1 Bus Controller Address bits 0 9 Reference of Bus Controller 1 1000 bits 10 11 zeros bits 12 15 Bus Controller channel 0 F Register 2 Series Six I O Address bits 0 9 I O reference of circuit 1 1000 within a channel bit 10 1 input reference affected bit 11 1 output reference affected bits 12 15 Series Six I O channel number 0 F Register 3 bits 0 3 relative number o
103. f the circuit on the block 0 15 d with zeros if the fault is not a circuit fault bits 4 7 unused set to zero bits 8 15 Bus Controller status byte 3 Register 4 bits 0 7 Bus Controller status byte 4 bits 8 15 Bus Controller status byte 5 Register 5 bits 0 7 Bus Controller status byte 6 bits 8 15 Fault type bit 8 1 Bus Controller not responding 0 Bus Controller OK bit 9 1 Serial bus error bit 10 1 Circuit fault bit 11 1 Loss of block bit 12 1 Addition of block bit 13 1 I O address conflict bit 14 1 Block terminal assembly EEPROM failure bit 15 unused set to 0 Register 6 Fault type bits 0 3 0000 Block headend fault 0001 discrete circuit fault 0010 analog circuit fault 1001 discrete circuit fault circuits 17 32 only 0100 RTD circuit fault bits 4 7 unused set to 0 bits 8 15 Fault description bit 8 1 Loss of I O power Isolated block only bit 9 1 Short circuit bit 10 1 Overload bit 11 1 No load open line bit 12 1 Over temperature bit 13 1 Switch failed bits 14 15 undefined Register 7 Fault description bit 0 1 Analog input low alarm bit 1 1 Analog input high alarm bit 2 1 Analog input under range bit 3 1 Analog input over range bit 4 1 Analog input open wire bit 5 1 Analog output under range or RTD wiring error bit 6 1 Analog output over range or RTD internal fault bit 7 1 not used or RTD circuit shorted bits 8 15 undefined set
104. f the electrical noise The proper solution to these problems will depend on the application Please refer to chapter 5 of the Genius 1 0 System User s Manual for information on cabling baud rates and ambient electrical noise GFK 0171 App endix A Expanded VO Addressing The tables that follow show how Expanded I O is mapped for CPUs with different amounts of memory Expanded I O Addressing for 8K and 16K Registers For a CPU with either 8K or 16K of register memory e Real I O references 00 0001 to 00 1024 I0 0001 to 10 1024 O8 0001 to O8 1024 and 18 0001 to 18 1024 can not be used as program references However internal I O references O0 0001 to 00 1024 10 0001 to 10 1024 08 0001 to O8 1024 and 18 0001 to 18 1024 can be used e Channel 1 7 real I O references are for the Expanded Main I O channels e Channel 9 F real I O references are for the Expanded Auxiliary I O channels REGISTERS USED FOR REGISTERS USED FOR Aux I O Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Gen use Channel 9 Channel E Channel F R00001 to R00064 R00065 to R00128 R00129 to ROO192 R00193 to R00256 R00257 to R00320 R00321 to R00384 R00385 to R00448 R00449 to ROOS12 R00513 to ROOS76 R00577 to RO0640 R00641 to R00704 R00705 to ROO768 R00769 to R00832 R00833 to ROO896 R00897 to RO0960 R00961 to RO1024 R01025 to RO1088 R01089 to RO1152 RO1153
105. g Look for a broken cable Check for intermittent cable breaks and connections Ensure that cable shielding is properly installed and grounded see chapter 6 of the Genius I O System User s Manual 10 There are no functioning circuits on one bus but other busses are operating normally From the CPU see if the Bus Controller has its Outputs Disabled This selectable feature allows a module to receive inputs but not to send outputs See the chapter 1 for more information Check to see if the Bus Controller is properly installed seated properly and receiving power Check the on board DIP switches especially switch 4 at position U16 Pull out the Bus Controller and reinsert Check for loose communications cable connections or breakage If necessary replace the Bus Controller 11 There are no functioning circuits on more than one bus Please refer to the documentation for the Series Six PLC for troubleshooting information 12 The CPU system shuts down with parity errors after operating for a short time or after changing the system configuration There may be duplicate or overlapping I O references coming from different busses Unplug one Bus Controller refer to the configuration worksheets and use the HHM to read Reference Numbers If necessary check other buses the same way Verify that no conventional I O module has reference numbers that overlap references assigned to Genius I O devices Problems 13 14
106. ge each CPU sweep when faults exist To use this diagnostic data the program should look first at bits 1 8 of the Bus Controller input references Bits 9 48 have meaning only if bit 3 4 5 or 6 is set to 1 Bits 3 6 can be 1 for only one sweep of the CPU and only one bit between 3 and 6 can be 1 at a time Bits 1 2 7 and 8 are independent They can be 1 or O regardless of the state of the other inputs For example 6 5 4 3 2 1 byte number 41 33 25 17 9 I O reference ous Reference of the Circuit Fault bit 1 1 Bus Controller OK _ bit 3 _ bit 8 l Circuit Fault 1 Circuit Forced _ bit 9 1 Input circuit bit 10 0 __ Input 33 0 Discrete block Inputs 37 40 Number of the circuit Circuit Fault Description Automatically cleared by the CPU if DIAGNOSTICS ENABLED is set to Y on the CPU Configuration Setup Menu In this example three bits in status byte 1 are currently 1 They indicate that the Bus Controller is communicating with the CPU at least one circuit is forced and a circuit fault is being reported during this scan Status bytes 2 through 6 describe the circuit fault 8 4 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Monitoring Bus Controller Status Bus Controller input reference bit 1 the least significant bit indicates the status of the Bus Controller It is set ON within one second of power up if the Bus Controller passes its sel
107. gogse 7 55 5 BORD peg 43 E y Y d os On g e OD d E a 99 YAA s o un E 34 E 838 8 S UT Non 4 A ERO Bu y 3 a 2 Le 0 oD y S Q Q DOS a aw od o 9 fi rj rd e ou 4 9 9 ap mU 3 2 88 dong E amp 3 C a3 3 V 0 Bg 9 c A948 3 EZ E 00 2 S Sq n 5 Y e m 7 Six ba A E i 4 gt HA Q A As e 4 H A d E d o m Y D O l 10 Y mi rj A cur 1 TE o 3 lt s i go 2 2 qo d og Y B 9 E eeg 9 69 E O E MD se a woos ss E do A Ed oom g o6 EAT ys v ye JENS O n U m a 0 5 pg 5 o o BE oR eS 5 gn D 238 EE E Spa Be g 28 Seo BS 3S E fay wens oF e d 1 MP w 0 t j X t gQ ord A e Q Qu ry E E 3 paz A ed P OB IN du amp z P aug S gt EZ RT 2 2 E puami D E wd ven La t G m 9 a amen C Y 3 ud panal 4 md HA Q e 4 d i ed i 3 N O of Q 4 m E a gs JE Bg 365286 NN EE dl dc 5 S E Zod 4 O a BED 2 Eb O 3 9 Oc O 2 2 E b uo ocd O c B A Y O O nm Y E qi 5 Qs 3 9 O it cud o oc 2 Q Ey e opni u d E sj y Qo Q p 4 j ra O la t4 Q Y 4 pu 4 YO 3 Yo z o 5 Shas 538 PS E 9 y Rab DELE du 8 E E ber p in a 0 6 O E O H i f E eQ g d 9 A E Q Ps S S 253 a t 8 o n 2965 SH t Toga ee Ra B E gt A E pa PE Q y G i dum ed N i e 4 m i ed gt O H4 B UY fa Yo 5D e o 5 o H o 9D 5 E m a E a D a v 2 O 2 e 24 Be e as O 4 9g V SUES oga amp oBeof 5 og
108. gram commands described in chapter 5 can be used to send these Datagrams instead 6 2 Datagrams GFK 0171 Using Datagrams instead of Global Data Datagrams and Global Data can be used to send messages between CPUs on the same bus Datagrams are individual messages while Global Data is transferred automatically and repeatedly CPU to CPU Datagrams can be used together with Global Data or can replace Global Data Consider using Datagrams instead of Global Data if 1 Global Data takes up too much serial bus scan time for the application 2 The data does not need to be sent every serial bus scan 3 CPU sweep time becomes too long for the application In addition Datagrams can be sent to either I O or register memory in the receiving CPU while Global Data must be sent to register memory Normal or High Priority Datagrams The Bus Controller handles Datagram commands in the same way as the other window commands described in chapter 7 When a Datagram command is encountered in the program the CPU opens a window to the specified Bus Controller The Bus Controller reads the command sets the status then closes the window The Bus Controller sends the Datagram according to its assigned priority see below Until transmission of the Datagram is complete the Bus Controller will not accept any other non immediate CPU Bus Controller window commands for processing A Bus Controller can send exactly one Datagram per bus scan That Datagram m
109. grammable features The tables on the following pages will help you locate the information you need for Setting up a Bus Controller Setting up the PLC system Programming for analog I O Programming for diagnostics and fault clearing Programming for communications between CPUs Each topic is explained in more detail later in the book Setting up a Bus Controller Each Bus Controller in the system and the I O blocks on the bus must be configured DESCRIBED HOW TO DO IT IN CHAPTER Set DIP switch 4 at position U16 Prevent program from sending unwanted outputs to blocks following powerup of the Bus Control ler Indicate whether failure of the Bus Controller s self test should stop the CPU Match the Bus Controller s baud rate to the other devices on the bus Select a Device Number for the Bus Controller Set up Bus Controller for Expanded I O scan ning and select channel Select terminating impedance for the Bus Con troller Select the Bus Controller reference number Automatic I O update Use switch 1 at position U3 Use switches 2 and 3 at position U3 Use switches 4 through 8 at position U3 Use switches 1 3 at position US9 For single bus cable use jumper on Bus Control ler For redundant cable use resistor Set backplane DIP switches Assign I O not register reference numbers to O blocks Introduction 1 11 GFK 0171 Setting up the
110. han the CPU Sweep Time If the bus scan time is significantly shorter than the CPU sweep time you can estimate the number of DPREQ or WINDOW instructions that must be sent to the Bus Controller to accommodate incoming Datagrams on that bus First determine how many scans can occur in one CPU sweep For example if the bus scan were 20mS and the CPU sweep were 90mS the ratio between them would be 4 5 to 1 This should be rounded upward to 5 This is the maximum number of Normal Priority Datagrams that might be received in a single CPU sweep Plan to have the same number of DPREQ or WINDOW instructions in the program to handle the incoming Datagrams For High Priority Datagrams multiply the number found above by the total number of devices on the bus that might send a High Priority Datagram to the Bus Controller in one bus scan This is the total number of incoming Datagrams from that bus the program might have to handle in a single CPU sweep Plan on this number of DPREQs or WINDOW instructions 6 4 Datagrams GFK 0171 Effects of Datagrams on the Genius I O Bus Normal Priority Datagrams allow fault reports and Hand held Monitor communications on a bus to continue undisturbed Only one Normal Priority Datagram is allowed each bus scan so the scan time stays relatively constant and I O update timing varies only by small increments If High Priority Datagrams are being transmitted constantly the Hand held Monitor will not funct
111. hannel for example one half will help prevent reference conflicts Bus Strea Upstream Controller Main I O Aux VO Channel Channelized Transmitter Transmitter 9 F no no 0 8 no yes or 0 8 yes no AUX VO mam vo CHANNEL 0 accommodates conventional I O in the channel as dejo well as Genius I O modules phase A or phase B Bus Controller phase B Bus Controller only ICAA 8 CHANNEL 1 CHANNEL 2 CHANNEL A CONVENTIONAL VO CHANNEL 1 6 Introduction GFK 0171 Locating Bus Controllers in Remote I O Racks A Bus Controller may also be placed in a Remote I O rack but this is not recommended If the application requires great distance between the CPU and I O blocks it is better to use a longer bus between a Bus Controller and the I O blocks than to place the Bus Controller in a Remote I O rack The cable from the Bus Controller to its I O blocks can be up to 7500 feet long At maximum length the Bus Controller supports up to 15 I O blocks providing up to 480 discrete references on the bus In addition the Bus Controller can be placed in a high capacity Local I O rack up to 2000 feet from the CPU giving a total maximum distance from the CPU to the end of the bus of 9500 feet Such a system provides all of the diagnostics and communications features of Genius I O Placing a Bus Controller in a Remote I O rack severely limits its capabilities The Remote I O rack must be hardwired from the Remote I O Transmitter module
112. hannel F Switch 4 Expanded I O Addressing no default yes If yes enter channel number Position U16 Switch 4 Disable Outputs at powerup yes default no A Switches 1 through 3 must be OPEN Select the terminating impedance using the on board jumper JP7 none default JP1 750 JP2 1000 JP3 1500 Select the Reference Number using the backplane DIP switches Reference Number 1 993 Chapter 3 3 1 Interfacing Genius I O Blocks to the Series Six PLC GFK 0171 Each Genius I O block in a Series Six PLC system must be assigned a Reference Number when the block is configured using a Hand held Monitor The Reference Number is the address in PLC memory reserved for use by the block s inputs and outputs This chapter explains e Assigning Reference Numbers in I O or Register Memory e Analog block input and output data formats e Required programming for analog inputs e Required programming for analog blocks High speed Counter Blocks and PowerTRAC Modules in I O memory Assigning Reference Numbers in I O or Register Memory When a block is configured either an I O reference or register reference can be assigned as its Reference Number For most applications I O blocks should be assigned Reference Numbers in I O memory However a block might be assigned a register reference to conserve I O references or to permit more devices to be used on the same bus When register references are used allow enough to
113. he end of each sweep This function is performed automatically by Logicmaster 6 software release 3 0 or later Programming for Diagnostics Using Bus Controller Input References GFK 0171 lt lt RUNG 13 gt gt KRAKKKKKKEKKKKKKKKKKEKKEKKKEKKKKEKKKKKKKKKKKKKKKKKKK KKK KK KKK KKK KKK KK k KK KK k k k k kkk kk This rung insures that all of the fault storage registers are cleared if the CPU is restarted or if the fault list pointers are equal to 00000 KKEKKKKEKKKKKKEKKKKKKKEKKKKKKEKKKKEKKKKKKKKKKEKKKKKREKKKKKKKKKKKKRKKRKKRKR KK KKK KKK ARA A POWER FAULT FAULT FAULT UP TYPE TYPE TYPE RESET STORAGE STORAGE STORAGE 00908 ROO100 R00100 R00100 Const A EOR B C LEN 060 FAULT LIST EMPTY 00910 4 lt lt RUNG 14 gt gt HHKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK AAA AAA AA AAA E EE This rung turns off the Bus Controller OK bit at the end of each CPU sweep so that the Bus Controller can turn it back on It is then checked to always be on in the program above If it is ever found to be off output 1 is turned off to indicate the problem KKKKKKEKKKKKKKKKKKKKKEKKKEKKKEKKKKKKKKKKKKKKKKKKKKKKEKKKKKKKKKKKKKKKKKKKKKKKKKK BUS CNTRLR OK BIT Const I0257 Const BIT CLEAR MATRIX LEN 00001 001 lt lt RUNG 15 gt gt KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKEKKKKKKKKKKKKKKKKKKKKKKKKKRKKK KAR RA RRA This rung generates the power up reset pulse used
114. her interface modules Bus Controllers or PCIMs a42564 ci CONTROLLER HAND HELD MONITOR COMMUNICATIONS ESSE E BUS A bus can serve all types of Genius I O blocks Phase A Genius I O blocks can be located on a bus that meets the restrictions for use with phase A blocks In a basic I O control system one bus may serve up to 30 Genius I O blocks and one Hand held Monitor The total number of I O circuits that can be included on the bus depends on the types of I O blocks that are used Genius discrete I O blocks are available in several different types with 8 to 32 circuits each The maximum number of I O circuits possible on one bus would result from using 30 discrete blocks with 32 I O circuits each The total number of discrete circuits would be 960 For applications requiring very fast response times fewer blocks might be located on a bus with additional blocks distributed on other busses Analog blocks including the low level analog RTD blocks have 6 circuits each Therefore the maximum number of analog circuits on one bus is 6 circuits times 30 blocks or 180 Because of the length of time required to transmit analog data special programming see chapter 3 will be required if more than 5 analog blocks are used on the same bus c5 HA AAA O BLOCKS L Number of Busses in the System The only limit to the number of busses in the system is the I O addressing capacity
115. in the CPU Registers 4 10 The remaining registers in the Command Block are used for varying purposes by different commands as indicated later in this chapter Not all registers are used by all commands Programming Window Commands 5 5 GFK 0171 Program Structure Window instructions can be programmed as separate rungs with conditional logic It may be preferred to use just one window command and change the content of the Command Block each time If that method is used conditional logic should check the current Status Code in Command Block register 3 before the content of the Command Block is changed If the program will also include programmed CPU to CPU communications there are additional considerations for using window instructions which are explained in chapters 6 and 7 Timing for Window Commands The impact of window commands on the CPU sweep time depends on the type of commands used and the relationship between the CPU sweep and the bus scan e An Immediate command is started and completed during a single window The Bus Controller returns data to the CPU in the same instruction in which the command was issued and indicates Done 2 in the Status Code Command Block register 3 PROGRAM CPU BUS CONTROLLER DEREO Read Configuration l opens window of Bus Controller 2 sends command gt 1 reads command 3 transfers data lt gt 2 transfers data 4 resumes logic lt 3 closes window execution fo co o
116. in the program above Output 908 is always on except during the first sweep of the CPU when it is first powered up or restarted KAEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRKKKKKKKKKRKKKRKKKKKRKKKKRKKKKKKKKKKKKKKKKKRKEK POWER UP RESET 00908 NO OP 2 2 2 2 2 2 2222 2 22 22222222222222222222 2 2 2 22 2 2 C ENDSW 8 26 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Displaying the Example Diagnostic Table The Display Register Tables function of the Logicmaster 6 software can be used to display the information currently in the fault table registers assigned by the example program logic The Register Tables display shows a full screen of register values in either decimal or hexadecimal format Initially register values are in decimal Pressing the Change All F7 key and the Hex Display F3 key converts all values to hexadecimal L M OFFLINE REG REGISTER 00101 EQUALS 0000001100000101 00100 0002 01C3 0000 0148 0001 0000 0000 003E 0000 0000 00110 0000 0000 0000 0000 0000 0000 0000 0000 0205 0305 00120 0002 01 3 0000 0148 0001 0000 0000 003E 0000 0000 00130 0000 0000 0000 0000 0000 0000 0000 0000 0032 0031 00140 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00150 0000 0000 0000 0000 0000 0000 0000 0000 0411 0801 00160 O3E9 0000 0000 0000 0000 0000 0000 0000 0000 0000 00170 0002 0002 00C7 4420 4924 0000 0000 0000 4074 4074 00180 O3E9 0000 000C 0000 0000 000
117. ineering units Register 4 Input channel 4 16 bit engineering units Register 5 Input channel 5 16 bit engineering units RTD only Register 6 Input channel 6 16 bit engineering units RTD only Programming Window Commands 5 19 GFK 0171 Example Program Logic to Read Analog Inputs The example logic that follows would repeatedly execute a communications command to read analog inputs from a 4 Input 2 Output analog block The program would store the engineering units values of the analog inputs in four consecutive registers starting at register R0131 Therefore R0131 would always contain the value of input 1 R0132 would contain the value of input 2 and so on lt lt RUNG 1 gt gt KAKKKKKKKKKKEKKKKKKKKEKEKKKKKKKKKEKKKKKEKKEKKKKKKEKKKKKKKEKKKKKKEKKKKKKKKEKKKKKEKKKKKRKK The Block Move instruction below moves seven constants to seven consecutive registers starting with R011 Five of these constants represent a READ ANALOG INPUTS command that will read the four analog inputs from an Analog I O block with I O table address 337 and will store the engineering units values into four consecutive registers starting at R0131 00957 is permissive logic set elsewhere in the program to control execution of the DPREO kkkkkkkkkkkkkxkkkkkkkkkkkkk xkkkkkkkkxkk kkkkkkkkkkk xk xkkxkkkkkkkkkkkkkkkkkkkkkkkk o X 0E F ANALOG DPREQ 00957 R0011 raaj eet BLOCK MOVE pe ub 9 01257 400007 00000 00337 00131 00000
118. ion properly fault reports from blocks will be prevented from being transmitted on the bus and regular DPREQ or WINDOW instructions such as Write Configuration commands to that Bus Controller will fail with a transmission error For these reasons use of High Priority Datagrams on a bus with I O blocks should be avoided if possible If High Priority Datagrams are transmitted infrequently they will cause some delay in the Hand held Monitor communications and other normal system messages but the delay should not be noticeable High Priority Datagrams will typically put more pressure on the Bus Controller to transfer multiple Datagrams per CPU sweep However this can also occur with Normal Priority Datagrams if the bus scan time is much shorter than the CPU sweep time Maximum CPU Sweep Time Increase for Datagrams To estimate the impact of Datagrams on CPU sweep time add together the times required for all Datagrams that might be sent between the Bus Controller and the CPU during one sweep Repeat this for each Bus Controller in the Series Six PLC that sends or receives Datagrams total Datagram Bytes Sent aX 031mS may be none LARGEST incoming Normal Priority Datagram Received bytes aX 031mS OR total incoming High Priority Datagram Bytes Received EE 031mS T 2 5mS to 5 5mS for each window command used ms 1 20 mS ms Datagrams 6 5 GFK 0171 Assign Monitor Datagram A Bus Controller or CPU on the bus
119. is correct if the Bus Controller is not physically installed at the end of the bus If the Bus Controller is at either end of the bus move the jumper to select 75Q 100Q or 150Q terminating impedance The Genius I O System User s Manual explains correct terminating impedance and baud rate for different cable types and lengths Terminating Impedance on a Redundant Bus A bus that uses two Bus Controllers for redundancy on the same bus requires special planning for termination If either Bus Controller will be located at the end of such a redundant bus do not select terminating impedance using the on board jumper Instead install a resistor of correct impedance across the Serial 1 and Serial 2 terminals on the Bus Controller s faceplate This will make it possible to keep the bus properly terminated and in operation should removal of the Bus Controller ever be necessary Setup and Installation 2 3 GFK 0171 CPU Continue CPU Stop CPU Shutdown Sweep Sweep 1 X Baud 153 6 76 153 6 Rate standard extended a42190 1111111111222222222233 01234567890123456789012345678901 XX XX XX XX XX XX XX XX TX X X X X X X X X X X X Xx X X X X X open off Default is all open Enabling CPU Shutdown Mode Switch 1 of the DIP switch pack at position U3 determines whether Bus Controller failure will stop the CPU sweep The default selection is for the CPU sweep to continue If the CPU sweep should stop becau
120. it Fault bit 4 Loss of Block bit 5 Addition of Block bit 6 Address Conflict bit 7 Pulse Test Active bit 8 Forced Circuit bit 9 Input If bits 9 and 10 are both 1 bit 10 Output Input and Output bits 11 16 not used Moving the cursor to R101 would display its binary equivalent beside the word EQUALS L M OFFLINE REGISTER 00101 EQUALS 0000001100000101 00100 0002 01C3 0000 0148 0001 0000 0000 003E 0000 0000 00110 0000 0000 0000 0000 0000 0000 0000 0000 0205 0305 __ R101 This is the fault type information for fault 1 EQUALS 0000001100000101 Bits 1 3 9 and 10 are 1 showing that the Bus Controller is OK bit 1 is 1 and there is a Circuit Fault bit 3 1s 1 Bits 9 and 10 are both equal to 1 so the circuit with the fault is an output with feedback If the cursor were moved to R102 the binary content of Bus Controller input bytes 1 and 2 for the second fault would appear beside the word EQUALS EQUALS 0000001000000101 Bits 1 3 and 10 are equal to 1 The Bus Controller is OK and there is a Circuit Fault Bit 10 is set to 1 showing that the circuit is an output Registers R121 through R139 each store Bus Controller input references 17 through 32 for one of the 19 faults see rung 6 If a fault is an I O circuit fault its reference number will appear in the appropriate register Register R101 shows that fault 1 is a circuit fault Its reference number would be stored in register R121 In the previo
121. ler Number of Analog If the number of analog blocks plus No restriction on the use of discrete blocks on one bus If Blocks and 16 32 ckt discrete blocks on bus ex the number of analog blocks of any type exceeds 8 the Discrete Blocks ceeds 8 the program must prevent I O program must prevent I O scanning until the Bus Control on a Bus scanning until the Bus Controller has ler has updated all inputs See chapter 3 for more infor updated all inputs Idle DPREQ or WINDOW instruction provides auto matic buffer time mation Idle DPREQ or WINDOW provides automatic buffer time Bus Controller version 1 6 IC660CBB902G or CBB903G or later is required to guarantee data coheren cy for future devices such as the High speed Counter and PowerTRAC Discrete blocks same as phase A Discrete blocks 8 bit 1 byte quanti ties only Analog blocks 16 bit channel values handled as coherent data Data Coherency Analog blocks same as phase A Control Data Sent Does not send control data message to Sends null message to any inputs only block on each to Inputs Only inputs only blocks Block I O Ena scan This turns on I O Enabled LED If the block stops Blocks bled LED goes on when logged in receiving this message for 3 scans its I O Enabled LED never goes off goes off Channelized 1 O Use of Expanded I O channels re Bus Controlle
122. lt condition for example a short circuit still exists the fault is reported again Clearing a Specific Circuit Fault To have the program automatically clear just one fault set bit 3 for one CPU sweep The bit must transition from O to 1 to clear the fault 4 3 2 1 bytes bits bit 3 Clear One Fault 1 circuit to be cleared is on inputs only block 0 circuit to be cleared is on outputs only block circuit reference Use bit 9 to indicate whether the block has inputs only or outputs only Bit 9 will be ignored if the block has both input and output circuits Y a 4 ed Y IS BG e 5 3 T N E COR 2 323 du 3 3 7 oO OE 24 m O 3 45 t n Y VJ Q R D D amp Pao id 0 L M Q DE Ne um 3 E a ux V Q E LS 38 a 2 0 m o e DES ES Sisssases Q QO Les uoo p gt 60 05 co 00 co oo d Rh ERES 4 no Oo oooo mo 920 e 5 2g Be B y Q Per 3 2 M o 5 5 ES 82 n uu MAN e en S ed 2 e 9 u uw n n un 5 84s HgS j 838333 Ez ges 9 z S 5 A A A A A m 4 An i Q Q QQQ E Ezg aag 228228 32 DS 9 9 oooo0oo0Do 4 RN bo O p Y o 2 p Iz g e o 8 OTR D D O9 9 9 9 o9 ROS 4 2 OQ ioooooD o Q 5 Va 9 2 0 m 28 R E 2 8 Y ES q 3 b tb OD OD OD tb S O lt x i g g gg gg ca ASE d BEE i EI oO SAAS Hs 9 WEES c g ANANN A ez UE v O E y E eet RENT ee ent 1 3 A w 50 Y D w O U E O SO vr E id EX S0 ma ma O 2 h MZ 2 ed 3 Q G4 N B Ci
123. mmunicates with other devices The CPU sweep is executed independently of the Genius bus scan During one CPU sweep the Bus Controller Transfers all discrete inputs and one channel input value 16 bits per analog or RTD block from shared RAM memory to the CPU Input Status Table To update all the inputs on an analog block during a single CPU sweep the command Read Analog Inputs can be added to the ladder logic program Receives current outputs and new commands from the CPU Output Status Table and places them in shared RAM Reports its status and that of the serial bus A Bus Controller with Diagnostics also reports the status of the I O blocks and provides one new diagnostic if any to the CPU Diagnostics data is moved to the Input Table starting at the address set with the backplane DIP switches May communicate with the CPU in response to window instructions in the application program If the program directs DPREQ or WINDOW instructions to a Bus Controller a communications window to that Bus Controller opens during the ladder logic portion of the sweep The Bus Controller may also receive messages from other devices on the bus These messages will be returned to the CPU when the program opens a communications window to the Bus Controller CPU SWEEP BUS CONTROLLER a43044 BUS TOKEN 1 10 Introduction GFK 0171 Completing the Interface The rest of this book explains how to install a Bus Controller and describes pro
124. mportant to know which version of Logicmaster 6 software is being used because that determines which Expanded I O channels the CPU scans by default Logicmaster 6 software version 4 and later defaults to scanning channels 0 and 8 which correspond to the Main and Auxiliary I O chains For Logicmaster 6 version 3 0 the software defaults to the first 4 channels enabled channels 0 3 The setup of the Bus Controllers must match the channels scanned by the CPU As an example suppose the system has one Bus Controller and that it has been installed without changing its DIP switch settings That means it is not set up for Expanded addressing Subsequently the system is powered up using Logicmaster 6 software version 3 This software defaults to Expanded I O Enabled and scans channels Q 3 Because the Bus Controller has not selected a particular channel it receives outputs on successive CPU sweeps as though they were intended for Bus Controllers set up for channels 0 1 2 and 3 That means it receives constantly changing output data from the CPU To avoid this problem the application program and the Bus Controller setup must match Setup and Installation 2 5 GFK 0171 Disabling Outputs The Bus Controller can be used to disable outputs from the CPU to the blocks Disabling outputs means preventing the transmission of output information to the block s from the CPU this is determined at the Bus Controller Disabling outputs is not the same as
125. n device absolute address byte 2 MSB 40 hex in this example Upper byte 00 hex R0352 02 80 hex 0640 decimal Lower byte 80 hex Upper byte 02 hex length of data 2 in this example The example hex entries look like this A100 0040 0280 00000 2 400000 2 400000 00000 O E F OF OF OF Pressing the Accept key converts them to the decimal values shown below KHKKKKKKKEKKKEKKKKEKEKKEKKKKKKKEKKKEKKEREKKEKEEKREKKKKKKEKEKEKKEKKKKEKEKKEEKKKEKEKKEKEKEKEKKKE 00042 R00350 BLOCK MOVE J 24320 00064 00640 4 400000 2 400000 400000 2 200000 RUNG 5 Sc e e e e e de eee e ee ee fe ee e ce e ke e ceo e oe ce oe ce e ce dece efe eode ce decode e ecc ee dece e dece e e ce oe ce oe ce fece dece ce ce ek ec e eee ck ec ecc A X DPREQ opens the communications window It should be tied to the left rail KKKEKKKKKKKKKKKEKKKEKKKKEKKKKKKKKKEKEKEKEKEEKEEKKKKEKKKKRKEKKKKKEKRKEKKKKKKKEKKKKKKKKEKEKKEKKEKK R0290 DPREQ 6 lt lt RUNG 6 gt gt ENDSW lt lt RUNG 7 gt gt ENDSW Chapter 7 7 1 Global Data GFK 0171 This chapter explains how to program Global Data communications between CPUs on the same bus If registers in one CPU are required as data by any other CPUs on the bus and the data must be constantly updated use Global Data Attempting to transfer register data using repeated Datagram messages will have a nega
126. ntroller Input References GFK 0171 If a fault occurs rung 5 creates a table of 19 registers Each register can contain the first 16 Bus Controller input references for one fault lt lt RUNG 5 gt gt s c c oc e te ke e e e de ce e ke e e dee ke oe nde ce e ce ede ee de e e e e de eoe e de ck de dece e dece ce efe ok ce dece ce ce ce dece ce e e he ce e e ce ce oe ce nee e e ce ox x Registers 101 through 119 store the first two input status bytes for each of 19 possible faults Each register can contain the following In each register bit 1 Bus Controller OK bit 2 Bus Error bit 3 Circuit Fault bit 4 Loss of Block bit 5 Addition of Block bit 6 Address Conflict bit 7 Pulse Test Active bit 8 Forced Circuit bit 9 Input If bits 9 and 10 are both on bit 10 Output Input and Output bits 11 16 not used KKKEKKKKKKKKKKEKKKKEKKKEKEKKKKEKKKKKEKKKKKKKKKEEKEKKKEKEKEKKKKKERKEKKKKEKEKKKKEKKKEKEK A FAULT BUS FAULT HAS CNTRLR TYPE OCCURRD OK BIT STORAGE 00909 T0257 R0O0100 Const SRC ADD TO TOP LIST LEN 019 The result of this rung is R100 pointer for R101 R119 R101 fault 1 fault type R102 fault 2 fault type R103 fault 3 fault type e R119 fault 19 fault type The first register assigned by the Add to Top function is a pointer to the rest of the entries in the list The first fault information will be placed in R101
127. ntroller input reference bytes describe the block that was lost or added Byte 2 indicates the block s I O type all inputs all outputs or combination Byte 2 16 15 14 13 12 11 10 Input reference affected Output reference affected If 9 and 10 both 1 block has both input and output circuits not used Bytes 3 and 4 contain the block s starting I O reference Byte 3 24 23 22 21 20 19 18 17 I O Reference Least Significant 8 bits Byte 4 32 31 30 29 28 27 26 25 I O Reference Most Significant 2 bits O not used Bytes 5 and 6 contain the number of input and output references used by the block Byte 5 contains the number of input references used by the block Byte 5 40 39 38 37 36 35 34 33 Number of input references used by the block gt f et Ay ty y c e e A Qo 9 js Number of output references used by the block 8 12 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Detecting Reference Number Conflict If the program should check for possible assignment of duplicate or overlapping Reference Numbers monitor bit 6 of the Bus Controller input references Bit 6 is set to 1 for one sweep for each conflict reported Byte 1 eL er Sr a at 20 3 Address Conflict If bit 6 is 1 indicating a conflict bits 9 and 10 indicate whether the conflict involves input references input 9 is 1 or
128. of the Series Six CPU Different busses in the system can be different lengths use different cable types have different I O response times and operate at different baud rates Each bus in the system is essentially indepen dent from the others Care must be taken to ensure that individual busses do not interfere with I O references assigned to other Genius Bus Controllers I O blocks or conventional I O modules in the system 1 4 Introduction GFK 0171 Bus Controller Location A Bus Controller can be placed in the CPU rack or in a local I O rack up to 2000 feet from the CPU Multiple Bus Controllers can be placed in one rack Since each Bus Controller consumes 20 units of 1 O power as many as six Bus Controllers can be placed in a Series Six Plus CPU rack or ten in a High Capacity I O rack pO RACK a O RACK nm Using More than One Bus Controller on an I O Chain or Channel 041630 jc F 3 HH HF UP TO 7500 FEET UP TO 30 BLOCKS UP TO 7500 AAA TO 30 BLOCKS gt PH 3 PA FS TERMINATION RESISTOR Within each I O chain or channel there can be more than one bus and Bus Controller as long as references assigned to the blocks on different busses do not overlap Introduction 1 5 GFK 0171 Using I O Transmitter Modules and Auxiliary I O Modules Depending on the I O addressing used for the system the Bus Controller may need to be located downstream of an Auxiliary I O Module and or
129. one or more Genius I O busses In addition each Genius I O product has its own data sheet which includes basic reference information and installation instructions Jeanne Grimsby Technical Writer V GFK 0171 CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 INTRODUCTION Types of Bus Controller LEDs Hand held Monitor Connector Bus Wiring Terminals The Bus Bus Controller Location Bus Controller Operation Completing the Interface SETUP AND INSTALLATION Selecting Terminating Impedance Enabling CPU Shutdown Mode Setting the Baud Rate Changing the Bus Controller Device Number Selecting Expanded I O Addressing Disabling Outputs Bus Controller Reference Number INTERFACING GENIUS I O BLOCKS TO THE SERIES Assigning Reference Numbers in I O or Register Memory Assigning Reference Numbers in I O Memory Analog Input and Output Data Programming for Analog Inputs Special Programming Required for Analog Blocks High Speed Counter Blocks PowerTRAC Blocks AUTOMATIC DIAGNOSTICS AND FAULT CLEARING The CPU Configuration Instruction Expanded Functions Menu CPU Configuration Setup Menu Genius Bus Controller Locations Screen Genius I O Fault Table Screen Clearing Faults Printing a Copy of the Fault Table Screen PROGRAMMING WINDOW COMMANDS Program Instructions Program Structure Timing for Window Commands Idle Read Configuration Write Configuration Read Diagnostics Read Analog
130. output references input 10 is 1 or both inputs and outputs both bits are ON Byte 2 16 15 14 13 12 11 10 d Input reference affected Output reference affected not used Bytes 3 and 4 contain the lowest reference 0 993 involved in the conflict Byte 3 24 23 22 21 20 19 18 17 I O Reference Least Significant 8 bits Byte 4 32 31 30 29 28 27 26 25 I O Reference Most Significant 2 bits O not used Byte 5 is the Device Number the serial bus address of the block that was not accepted That block is left in a default state no inputs are accepted and no outputs are activated Byte 5 40 39 38 37 36 35 34 33 A Device Number 1 31 of the block 0 Programming for Diagnostics Using Bus Controller Input References 8 13 GFK 0171 Byte 6 contains the Device Number 1 31 of the block that is already using the I O references requested by the second block Byte 6 SS Device Number 1 31 of the block using the I O reference in conflict 0 8 14 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Detecting Execution of a Pulse Test The program can periodically issue a command to Pulse Test discrete outputs on a bus see chapter 6 Additional program logic can monitor execution of the Pulse Test and determine whether the Pulse Test has located any faults To check execution of the Pulse Test monitor Bus Controller input r
131. pends on the CPU register memory size For example for a CPU with 8K register memory the Computer Mail Box is located from R8123 through R8192 For a CPU with 16K register memory the Computer Mail Box is located from R16315 through R16384 Programming Window Commands 5 3 GFK 0171 The Command Block The DPREQ and WINDOW instructions and the Computer Mailbox are programmed with a group of registers called a Command Block The Command Block contain the instructions for the data transfer A typical Command Block has the following content Register 1 Rogister 3 Register 4 Data can be placed in the Command Block registers with one or more Block Moves or similar program instructions Permissive Typical Command Block Contents Logic R0201 Block Move 01257 01257 00002 00000 400321 400211 00000 00000 lst Register in Command Block R0201 DPREQ 04E9 5 4 Programming Window Commands GFK 0171 The exact content of the Command Block depends upon the type of command it describes as summa rized below In this discussion the term Register 1 simply means the first register of a group Register 2 is the second register and so on Register 1 The first register of the Command Block provides the backplane address of the Bus Controller to which the CPU sends the command For a WINDOW instruction use the Bus Controller s address For example 257 For a DPREQ use
132. ple of programming Global Data This program initiates Global Data transfer of two bytes of data The Global Data address for both CPUs is R0001 Start of Program pe lt lt RUNG 1 gt gt KKK KKK KKK IKK RICK KK KKK KEIR KR KKK KI RR RR KK RR KR RK KR RK RK KR RK A RR KR A RA AAA AA Rung 1 uses a one shot to create permissive logic used to load the Command Block and data registers in subsequent rungs i KKEKKEKKKEKKKKKKKKKKEKEKKEKKKKKEKEKKKKKKKKKKKKEKKKKKEKKKEKEKKKKEKKKKKKKKKKKKKKKKKKKKRKRKK 11008 00042 lt lt RUNG 2 gt gt KKEKEKKKKKKKKKKKKKKKKKKEKKKKEKKKKEKKKKKKKKKKEKKKEKKKKKKKKKEKEKKKKKKKKK KKK KKK KKK KKK KK KKK Rung 2 contains the Write Configuration command block R0290 Bus Controller I O reference 1000 decimal RO291 Command Number 3 R0292 Communications status supplied by CPU R0293 I O reference of the Bus Controller This is the same as R0290 above except that 1000 is not added for a DPREQ R0294 Pointer to the first register of the data storage buffer in the CPU in this example RO301 KREKKKKKKKKKEKKKKKKKKKKKKKKKKKKKKEKKKKEKKKKKKKKEKKKKKKKKKKEKKKKEKKKKKKKKKKKEKKKKKKKEEK RR X t 4 E X 00042 R00290 BLOCK MOVE J 101513 00003 2 700000 2400513 400301 400000 2 400000 7 4 Global Data GFK 0171 lt lt RUNG 3 gt gt KRHKAEKKKKKKKKKKEKKKKKKEKKKKKKKKKKKKKEKKKEKKKEKKKKKKKKKKKEKKEKKKEKKKEKKEKKEKKEKKKKKKKKKKKKKK Rung 3 contains registers 22
133. ppear to be 0 during the program logic solution part of the sweep Therefore if automatic diagnostics are enabled for the CPU program logic cannot monitor input reference bit 1 to determine the status of the Bus Controller However the program can monitor the status of Bus Controller output bit 33 Monitoring Bus Controller Status using the Bus Controller OUTPUT Bit 33 A Bus Controller with Diagnostics uses 48 references in the output table Of these 48 references bits 1 through 32 are used to send commands to I O blocks 4 3 2 1 byte number _ bit 1 Disable Outputs _ bit 2 Clear All Faults o CLECULE _ bit 3 Clear Circuit Fault Reference _ bit 4 Pulse Test __ bits 9 16 Inputs only block If DIAGNOSTICS ENABLED is set to Y on the CPU Configuration Setup Menu the CPU also reserves Bus Controller output reference bits 33 through 48 for diagnostics information Of these additional 16 bits only bit 33 and bit 34 are used bit 34 Serial Bus Error last sweep bit 33 Bus Controller OK last sweep 48 41 L 251 17 9 i bits bit 1 Disable Outputs __ bit 2 Clear All Faults o CRECULE _ bit 3 Clear Circuit References Fault bit 4 Pulse Test _ bits 9 16 Inputs only block Before clearing Bus Controller input bit 1 the CPU copies it into Bus Controller output bit 33 On the next sweep if the Bus Controller fails to reset input reference bit 1 to 1 the CPU looks at output reference
134. puts on a Communications Bus If the bus is used for communications and has no blocks outputs should be disabled to conserve scan time Selectively Disabling Outputs for Distributed Control of I O Blocks Some systems use two or more CPUs on the same bus for distributed control of I O blocks Each CPU sends outputs to and receives fault reports from certain blocks on the bus and not others This is accomplished by selectively enabling or disabling outputs with a Write Configuration command to the Bus Controller a42485 BUS BUS BUS INTERFACE INTERFACE INTERFACE MODULE MODULE MODULE DEVICE 31 DEVICE 30 DEVICE 7 eS BS e k Fk k Ay F 3k Fk Obtaining Diagnostics from Blocks with Outputs Disabled Diagnostic messages are automatically sent from a block only to the Bus Controller that is sending or has previously sent it outputs If the CPU should receive all diagnostics reports from one or more blocks to which outputs are permanently disabled the Assign Monitor Datagram can be used 5 14 Programming Window Commands GFK 0171 Disabling Outputs for an Assigned Monitor In some systems the Series Six PLC will be used as a monitoring device only to receive I O data from the blocks on the bus When being used as a monitor the PLC can also receive fault reports and configuration change messages from any blocks that have been sent the Assign Monitor command CONTROLLER MONITOR 2425
135. r the current I O configuration of the bus the states of the Outputs Disable bits and its Global Data if any starting address and length Data format is shown below register numbers below show relative locations Bus Controller Type see Bit Assignments Software revision number bits 0 4 No of devices on bus 1 32 Bus Controller Device Number 0 31 Serial bus baud rate see Bit Assignments not used Bit map of input points 1 128 Bit map of input points 129 256 Bit map of input points 257 384 Bit map of input points 385 512 Bit map of input points 513 640 Bit map of input points 641 768 Bit map of input points 769 896 Bit map of input points 897 1000 Bit map of output points 1 128 Bit map of input points 129 256 Bit map of output points 257 384 Bit map of output points 385 512 Bit map of output points 513 640 Bit map of output points 641 768 Bit map of output points 769 896 Bit map of output points 897 1000 Bus Outputs Disable flags for devices 0 15 Controller Outputs Disable flags for devices 16 31 CBB902 Global Data starting address or CBB903 Global Data Datagram length in bytes only Programming Window Commands GFK 0171 Device Type lsb of register 1 may be Decimal Binary Bus Controller w diagnostics IC660CBB900 1 00000001 Bus Controller w o diagnostics IC660CBB901 3 00000011 Bus Controller w diagnostics IC660CBB902 6 00000110 Bus Controller w o diagnostics IC660CBB903 7
136. r DIP switch used to select Expanded I O quires channelized I O Transmitter and select channel unless down stream of channelized I O cards Transmitter card RTD Block Not supported Only supports analog Supported maximum number of channels is 128 for any Support blocks with 4 input channels or few analog block er Relatively slow Must process login messages 1 per bus scan Fast Can handle multiple login messages per scan Phase A blocks won t recognize some of these and will revert to phase A login procedure which will go more slowly Supports use of the Bus Switching Module and Switch BSM message Additionally version 1 5 or later supports BSM switching for BSMs controlled by analog blocks Switch BSM Message Not supported Programmed Communications Supports Datagrams and Global Data between Bus Con trollers CPUs in addition to phase A features Also Send Receive Datagram functions for Datagrams without built in support or for devices assigned to regis ter memory Fully supported as either DPREQ or WINDOW com mands Used to send or request messages not covered by existing commands Also used for CPU to CPU commu nications Specific Datagrams between the Bus Controller and blocks only Send Receive Datagrams These DPREQ or WINDOW com mands not supported Syntax error Index Active blocks map 5 10 Addition of block detection 8
137. r logic program includes the CPU Configuration function and if Genius I O diagnostics is enabled in the CPU Configuration Set Up Menu The table includes both I O block faults and the following faults which may be reported directly by the Bus Controller e Bus Controller fault e Bus Error e Loss of block e Addition of block e Address conflict e EEPROM failure Fault definitions are given in chapter 5 The format of each fault listing in the table is explained on the following pages Automatic Diagnostics and Fault Clearing 4 9 GFK 0171 Fault Table Display Definitions The entries in the fault table show the following information about a fault If a fault occurs that has more than one category see below each description is listed as a separate line in the table B C Addr Bus Controller I O Reference Displayed for all faults This entry has two fields Series Six Channel Number The first field is the number of the channel where the error occurred A hex value from 0 to F The Main I O Status Table is shown as 0 and the Auxiliary I O Status Table is shown as 8 MAIN AUXILIARY YAN ha YN amp O iimMUQW woo Channel Byte Address The second field is byte address of the error within the indicated channel Range 0 to 125 Point Addr Series Six Point Address Not displayed for a Bus Controller or Serial Bus fault This entry has two fields Input Output The first two characters indicate an input I or outpu
138. racy completeness sufficiency or usefulness of the information contained herein No warranties of merchantability or fitness for purpose shall apply The following are trademarks for products of GE Fanuc Automation North America Inc Alarm Master CIMSTAR Helpmate PROMACRO Series Six CIMPLICITY GEnet Logicmaster Series One Series 90 CIMPLICITY 90 ADS Genius Modelmaster Series Three VuMaster CIMPLICITY PowerTRAC Genius PowerTRAC ProLoop Series Five Workmaster Copyright 1991 GE Fanuc Automation North America Inc All Rights Reserved iii Preface GFK 0171 This manual explains how to set up and install a Series Six PLC Bus Controller It also provides programming information needed to complete the interface between a Series Six PLC and one or more Genius I O communications busses Use the Genius I O System User s Manual GEK 90486 as your primary reference for information about Genius I O products It describes types of systems system planning installation and system components Contents of this Manual This book contains 10 chapters and 2 appendixes For basic information about the functions of a Bus Controller in a Series Six PLC system begin by reading chapter 1 Lists of topics at the end of chapter 1 will help you find additional information Chapter 1 Introduction Chapter 1 describes Bus Controller types the serial bus Bus Controller operation and system operation Chapter 2 Setup and Installation Chapter
139. ram This logic uses a Read Device datagram to read two bytes of data from another CPU The DPREQ contains the address of the resident Bus Controller 513 1000 decimal The ladder logic for the other CPU must include a communications instruction with the address of its Bus Controller to be able to provide the data requested Start of Program lt lt RUNG 1 gt gt KAKEKKKKKKEKKKEKKKKKKKEKKKKKKKKEKKKKKKKKKKKKRKRKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRKEK Rung 1 uses a one shot to initialize the program The output 00042 will be used as a permissive in subsequent rungs The datagram is only sent once to send a new datagram the status byte should be cleared and set to zero KEKKEKKKKKKKKKKKKKKKKKEKKKEKKKKKKEKKKKKKKKKKKKEKKKKEKKKKKKKKKKKKKKEKKEKKKKKEKEKKKKKKKKKKKKK 11008 00042 lt lt RUNG 2 gt gt KAKEKKKKKEKKKKKEKKKKKKKKKKKKKKEKKKKKKEKKKKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK AA A A Rung 2 uses output 00042 from rung 1 to initiate loading the Command Block R0290 Bus Controller address 1000 1513 R0291 Command Number 13 Receive Datagram R0292 Communications status R0O293 Device Number of second Bus Controller 31 R0294 Pointer to the location of the Read Device header R0350 R0295 Length of the Read Device header in bytes always 6 R0296 Command Code Lower byte 1E hex for Read Device datagram Upper byte 20 hex for normal priority 201E hex 8222 decimal KKAKKKKKKKKKKKEKKKEKKKKKKKKEKKKKKK
140. re shown on the following page Read Diagnostics Reply messages for I O blocks are defined in the Genius I O System User s Manual The PLC can also obtain diagnostic information from I O blocks by 1 enabling the automatic diagnostics features of the Logicmaster 6 software as described in chapter 4 2 monitoring the Bus Controller input references as described in chapter 8 5 16 Programming Window Commands GFK 0171 Data Available using a Read Diagnostics Command to a Bus Controller If the Read Diagnostics command is sent to the Bus Controller the retumed data has the following format register numbers below are relative locations If the Bus Controller does not have diagnostics capabilities IC660CBB901 or 903 an error message is returned This command is immediate when sent to the Bus Controller the data is returned during the same window DESCRIPTION 1 Isb Device type msb Software revision number 2 Isb Self test Diagnostics msb not used always 0 Serial bus error count Serial bus scan time in milliseconds 3 400 decimal Number of active blocks 0 31 3 4 Device Type lsb of register 1 may be Decimal Binary Bus Controller w diagnostics IC660CBB900 1 00000001 Bus Controller w diagnostics IC660CBB902 6 00000110 Self test Diagnostics Register 2 may be 7 6 5 4 3 2 3 O Bus Controller Manager microprocessor failure EPROM failure RAM failure Series Six shared RA
141. redundancy distributed control or an assigned monitor DESCRIBED FEATURE HOW TO DO IT IN CHAPTER Prevent the Bus Controller from sending outputs Program Write Configuration command to Bus to one or more devices Controller using DPREQ or WINDOW instruc tion Set Bus Controller output reference bit 1 Disable all outputs from a Bus Controller used as a monitor Set up blocks to issue extra fault reports and configuration change messages to an assigned monitor Switch a Bus Switching Module to a specified bus Use DPREQ or WINDOW instruction Assign Monitor Datagram Use DPREQ or WINDOW instruction with Switch BSM command Programming for Communication between CPUs If the Series Six PLC will send or receive Datagram or Global Data messages on a bus with other Bus Controllers or PCIMs additional program logic will be needed DESCRIBED FEATURE HOW TO DO IT IN CHAPTER Read or write Global Data address Global Data Use DPREQ or WINDOW instruction with a length Read or Write Configuration command to the Bus Controller Use DPREQ or WINDOW instruction with Read Status Table command Use DPREQ or WINDOW instruction to send Write Configuration command to Bus Control ler Use Idle DPREQ or WINDOW instruction to transfer Global Data to from the Series Six CPU Use DPREQ or WINDOW instruction to send Write Device Datagram Use DPREQ or WINDOW instruction to send Read Device Datagram
142. rogrammed Low Alarm limit Bit 2 1 indicates that the current input value exceeds the programmed High Alarm limit If both bits 0 no alarm limits have been exceeded 24 16 A mx Circuit Number High alarm 1 __ Low alarm 1 Relative references bits 17 19 store a number that identifies the circuit on the block The circuit number is a binary value ranging from 0 which represents input circuit 1 to 5 depending on the number of inputs on the analog block The value remains in the CPU s input table for only one CPU Sweep On the next sweep it is replaced by the value of the next analog input on the block and the circuit number is changed accordingly Programming for Analog Inputs The input circuit number and circuit value from one analog input per block are automatically placed in the block s assigned input references each CPU sweep No ladder logic is required to move the value into the references although ladder logic is needed to capture this value and place it into a register This is explained on the next page DO I O instructions do not obtain data that is any fresher than the data already available and therefore should not be used for analog inputs If faster update of analog inputs is desired ladder logic can be used to read all of a block s analog inputs directly into registers in a single CPU sweep For information see the description of Read Analog Inputs in chapter 5 3 8 Interfacing
143. roller with Diagnostics receives any fault messages issued by devices on the bus and stores up to 60 in an on board fault table The Series Six Plus PLC can be set up to provide its own internal fault table for storage of diagnostic messages and can access these diagnostic messages automatically In addition ladder logic can be added to the program of any Series Six CPU to access diagnostic messages Sends any command received from the CPU for example Clear Circuit Fault to the appropriate device Bus Scan Time The amount of time required for one complete rotation of the token to all devices will depend on the baud rate the number and types of blocks the number of bus interface modules Bus Controllers and PCIMs and the occurrence of optional Global Data and of programmed messages on that bus Bus scan time directly affects the response time for servicing I O on the bus the time required for programmed communications to be transmitted on the bus the relationship between the bus scan and the CPU sweep time Because CPU sweep time is probably less flexible it may be necessary to change I O block distribution or programmed communications to create a balance The Genius I O System User s Manual explains bus scan time in detail Introduction 1 9 GFK 0171 The CPU Sweep The CPU sweep is the PLC s regular cycle of operations During each sweep the CPU updates inputs and outputs executes the application program and co
144. s Bus Controllers with Diagnostics only Bus Controller Output References The length and content of the Bus Controller output references depend on whether the Bus Controller has diagnostics capabilities Bus Controller without Diagnostics A Bus Controller without Diagnostics IC660CBB903 has 8 output reference bits Only the first bit is used Bits 1 to 32 are used by the Bus Controller directly 1 byte number H bit number B bit 1 Disable Outputs bits 2 8 not used 9 2 Programming Commands to I O Blocks Using the Bus Controller Output References GFK 0171 Bus Controller with Diagnostics A Bus Controller with diagnostics IC660CBB902 has 48 output reference bits The first four bytes are used for commands to the blocks Bits 1 to 32 are used by the Bus Controller directly Bits 33 and 34 are controlled by the PLC if the Bus Controller has been entered on the Logicmaster 6 software Bus Controller Locations screen _ bit 34 Serial Bus Error last sweep __ bit 33 Bus Controller OK last sweep 48 41 33 25 17 9 i bits bit 1 Disable Outputs __ bit 2 Clear All Faults CLECULE __ bit 3 Clear Circuit Reference Fault bit 4 Pulse Test bits 35 to 48 reserved __ bits 9 16 Inputs only block Bits 1 4 are used for commands Bits 9 32 are used only for the Clear Circuit Fault command they contain the circuit reference of the fault and its I O type Bit 33 can be monitored to detect a Bu
145. s Controllers in the same Series Six PLC The second Bus Controller in the PLC would always write Global Data received from the first into the same registers it was sent from so the data in those registers would never change In this example there are three Series Six CPUs on the same bus Each CPU sends 16 registers of Global Data to both of the other CPUs CPU 1 CPU 2 CPU3 01 0001 0256 3 01 0001 0256 gt 01 0001 0256 02 0001 0256 02 0001 0256 gt 02 0001 0256 03 0001 0256 E 03 0001 0256 E 03 0001 0256 If the receiving device is a bus interface module in another type of CPU the data may be stored differently So rm 21 e 3 ontiguration command to the bus Contro pu onfieuration data for Bus Controller begins VM oe EMEN eo th 3 wh FADE uf Gb MEER Pointer to the first register Command number 3 a mm _ Register 5 o N ou an T Y 1 Y e my oe S Fr Y t E Y m iiv 0 B a jaa AQ E D A 5 B D GB m 4 D pU O od p EO we amp oC O 4 9 a Os TE du E g 9 t Os ga E 9 0 333 S y ya e p ye oD pi gs 2 25 Er vog ya 27 3 O92 QMS po p Q a 9 3 Qu En 2 0 wu H i ws O d e Hu UU E amp e gt UGE LOG AS o0 Od B d 8 F g 4 A0 gt A d oO 1 agg 0 a5 o 9 gt pb EH d 7 Hog j es 0 o bo ei e SES wu mw ud 4 un 4 p b4 l Haa EGE a Sr E bb e M in baa 23 MO A E rd NS aos
146. s Controller error see chapter 8 en e 9 j z fa OO A O d i i4 a un u t aS T 4 7 Q O05 2 ae E 9 2 H aog M phages 8 amp c TP popas X D O o 3 qm 22 SE 8985084 y so gg ea Ho amp E o ei oe 3465 y Qe Y N 3 eC rat fe gt I oo ro Q S 3 aay 8 6508 eg 8 Sa R573 Sg du 9 eoesm O 230908 do ES sau fea 345 2 an Dl Gag 0 ES as A A P d cm c 4 Bu ROI O Y a y Y g yo U BR t 3 a o 4 o Q o M e CO im e Q e 75 E gt AOT omg e n r pem ed FW o A Ad ied 5 pi e dad 7 gud 4 P e Qaa m 3022 g t Qn gh e AE ES i fy 2 c Q Y Omg Ena A C a Y 6 gt S o CR E o 1 5852 E O B nE O ngg 5 8 O eae 9 os md o 332 op 0 b De QO 8s Ow dH c L T Q he c r un A r amp b o cb e Qo 7 mi OD As bn har gt ey ome Q Ke Lm U e bz a D T EJ Q OQ L r Y o har 3 o ed e A AE o s i u 9 f Nes E ius N ye Q 3 rj V V o e Qo y p pu H Er e O by o ya uu a oa Q 2 is b da Q E o0 O 0 ci es D O O gw de D 0 oO d o do gt E hd O S O d v Y Y OQ e B 3 N ra or o O C O wo 0 4 A a o eo c t O A m oU y 4 P N C v T Q 2 pa i cj Y Y e Y oy t r g s 3 E 2 Q X e 5 ODO A c A 2 26 BEF ga ye EE os p 3838250 By Py a 2 Ze a 73 B8 eB ES g 8 122515 y q 1 9 a m T S 0 bd d Uu d A e nf Es pa p ya y b dd ba i 1 an S E o 0 53098 gH aD 6 K H A 29 a 6 O 9 5 Y o6 mug i 2523 Beas d x e
147. s are enabled as explained below Because the Bus Controller uses only the first 48 references the final 16 references in each 64 reference block can be assigned for general I O use For some Series Six Plus PLC applications register memory can be used to store the current diagnostic status of all I O points on the bus If DIAGNOSTIC TABLES is selected on the Logicmaster 6 software CPU Configuration Setup Menu Bus Controller Reference Numbers must be assigned on 256 reference not 64 reference boundaries The Bus Controller will use the first 48 references for diagnostics and will place the current diagnostic status of all I O points on the bus in the remaining 208 references 2 8 Setup and Installation GFK 0171 Bus Controller Configuration Worksheet Bus Controller Type Bus Controller with diagnostics IC660CBB902 Bus Controller without diagnostics IC660CBB903 Description General Information Location to install this board Before installing the board configure it using the DIP switches and jumpers Position U3 Switch 1 CPU Shutdown Mode continue default stop Switches 2 and 3 Baud Rate 153 6 Kb standard default 153 6 Kb extended 76 8 Kb 38 4 Kb l Switches 4 through 8 Device Number 0 31 default is 31 Position 59 Switches 1 through 3 I O channel Main 1 O Chain channel 0 default through 7 Auxiliary I O Chain must be downstream of Auxiliary I O Module Aux 1 0 table default through c
148. s example logic cause an indicator light to flash if any type of fault has occurred lt lt RUNG 8 gt gt ERERERARARERA RARA KA ARA KKK KKK KKK KKK RARA RARA RRA RARA RR KARA RRA RARA This instruction forces R23 to always contain 00000 kkk kkk kkk kkk kkk k kkk kkk k k de A de k de KKK KK KKK KK de de e k KK de e KK KK de KK KK e e KKK k k ke ke k k k ke k k k e ALWAYS ZERO Const R00023 A MOVE B J J 00000 lt lt RUNG 9 gt gt KREKKEKKKKKKKKEKKKKKKKKKEKKKEKKKEKEKKKKKKEKKKKKKKEKKKEKKKKEKEKKKEKKEKKKKEKKEKKKKEKKEKKKK This rung compares one of the storage list s pointers to determine if any faults exist If R120 compares with the 00000 in R23 no faults exist and output 910 is turned on KKKKEKKKKKKEKKEKKKEKKKKKEEKKKEKEEKKKKKKKKKRKEKKEKKKKKKKKKEKKEKKKEKKKKKKKKKEKKKKKKRKEKESK CIRCUIT FAULT REF ALWAYS LIST STORAGE ZERO EMPTY R0120 R0023 00910 A B lt lt RUNG 10 gt gt e ee e ee e ke ke e e e ce e oe de de ee ee ede cede eee fe ee eoe e ce ede ce fede de de e de ce ce ce e ce e eoe de ce ce ce ee ode ce oe e ce ce de cec e ee eek If any faults are stored in the fault storage registers R120 will not equal 00000 and output 910 will be off This allows output 6 to flash on and off to indicate that at least one fault exists kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FAULT GENIUS LIST FLASH FAULTS EMPTY ON EXIST 00910 00905 00005 8
149. s manual or in the other documentation for your system contact your local authorized GE Fanuc distributor After business hours please don t hesitate to call the Programmable Control Emergency Service Number 804 978 5747 DIAL COMM 8 227 5747 An automatic answering device will direct you to the home phone of one of our Programmable Control Service Personnel Thus you are never without backup help How to Begin e Check the operating mode of the CPU and if appropriate the programmer e Check the status LEDs on the CPU If some of the CPU status LEDs are off refer to the Series Six Installation and Maintenance Manual If all the CPU status LEDs are on but either of the Bus Controller LEDs is not refer to the troubleshooting information on the following pages If all the CPU and Bus Controller LEDs are on check cabling then proceed to I O block troubleshooting Refer to the Genius I O System User s Manual Identifying the Problem If a problem occurs look for a description of the problem in the list that begins below Then refer to the troubleshooting suggestion with the same number on the pages that follow 1 Both Bus Controller LEDs are off The Bus Controller BOARD OK LED is off and the COMM OK LED is on The BOARD OK LED is on and the COMM OK LED is off The BOARD OK and COMM OK LEDs are flashing in unison The Bus Controller is not communicating with the CPU Intermittent or total lack of communica tions
150. s specified by the entry FAULT TABLE LENGTH see the next page The maximum length and location of the fault table depend on the CPU memory capacity See appendix A for the maximum fault table length and location for your CPU Individual Bus Controllers will always be capable of reporting faults and clearing faults Selecting Diagnostics Enabled YES allows all fault reports from all configured Bus Controllers to be automatically gathered together it also allows all faults on all busses to be cleared with a single action from the programmer or PLC A Bus Controller with diagnostics automatically provides fault information for this table If diagnostic reports are not needed from a Bus Controller it may be excluded from diagnostics scanning by specifying a smaller range with the entry for DIAGNOSTIC RANGE LIMIT see below If this entry is set to N the CPU will not store diagnostics information neither automatic nor programmed diagnostics or fault clearmg from the programmer will be possible Automatic Diagnostics and Fault Clearing 4 3 GFK 0171 However fault reports and fault clearing will still be accessible with a Hand held Monitor on the bus Diagnostic Tables This is an optional selection for most applications it should be set to N If this entry is set to Y when an I O circuit fault occurs the CPU sets the internal bit which corresponds to the circuit reference to 1 For example if a fault occurs at 12 0003 the CPU
151. s with the bus and the other referred to as shared RAM interfaces with the CPU The Bus Controller automatically transfers data between these two memories making data available to the bus or to the CPU when it is needed The Genius Bus Scan A Genius bus scan consists of one complete rotation of a token among the devices on the bus a42561 BUS INTERFACE MODULE TOKEN PATH DEVICE 31 1 8 Introduction GFK 0171 Durmg a bus scan the Bus Controller automatically a42562 INPUTS 1 per sweep PLC BUS OUTPUTS CONTROLLER 1 per sweep rp 4 DIAGNOSTICS Storage Automatically one per sweep max c maximum A COMMANDS jf 1 per sweep max via output table 1 per window INPUTS OUTPUTS BLOCK To selected blocks Automatically one per scan max On CPU logic command Limit 1 Datagram per scan Receives and stores all inputs from the I O blocks on the bus Updates outputs as permitted on the I O blocks With a phase B Bus Controller transmission of outputs from the CPU can be disabled for one or more blocks on the bus For all systems this feature can be used to initialize outputs at startup For advanced systems with distributed control of outputs or computer monitoring of I O block data outputs can be disabled to individual blocks Both phase A and phase B Bus Controllers can disable output updates as described in chapter 5 A Bus Cont
152. se one of the Bus Controllers has failed its self test then the program must be able to detect the failure If the Expanded Functions are enabled this requires Logicmaster 6 software release 3 0 or later the CPU will continually check for Bus Controller failure If an earlier software version is used the ladder logic program must check for a Bus Controller failure by resetting the Bus Controller OK status Bit every CPU sweep For more information about this status bit see chapter 5 Setting the Baud Rate All devices on a bus including the Bus Controller and the Hand held Monitor must be set up to use the same baud rate Other busses connected to the PLC may operate at different baud rates however The default baud rate selected for a new Bus Controller is 153 6 Kbaud standard This default is provided so that the Bus Controller is compatible with phase A devices However 153 6 Kbaud extended will provide better performance Depending on the length of the bus and other factors it may be desirable or necessary to change this to 153 6 Kbaud extended 76 8 Kbaud or 38 4 Kbaud using switches 2 and 3 at position U3 The Genius 1 0 System User s Manual gives guidelines for baud rate selection Changing the Bus Controller Device Number Each device on the bus must have a bus address which is referred to as its Device Number For a new Bus Controller the Device Number 31 is selected by default Jf there is just one Bus Controller on the bus no
153. sets the internal bit at 12 0003 to 1 Because this function will operate over the entire range of Genius I O for which diagnos tics is enabled by the entry DIAGNOSTIC RANGE LIMITS it requires that an amount of memory equal to the amount for which diagnostics scanning is enabled be set aside in the CPU For example if Expanded I O scanning is enabled for channel pairs 1 3 and 9 B the CPU will use registers R129 R512 and R1153 R1472 for inputs and outputs If Diagnostic Tables were enabled by setting this entry to Y the CPU would use registers R2177 R2496 and R3201 R3520 to store I O circuit faults If this entry is set to Y it is important to avoid using any registers within the reserved area for any other purpose the location of internal references in register memory is shown in appendix A In addition Bus Controller reference numbers must be assigned with the backplane DIP switches on 256 reference boundaries NOT on 64 reference boundaries The Bus Controller will use the additional references for I O diagnostics B C gt Point Faults This entry is an extension of the one directly above it defaults to N Unless the application requires all I O point status bits to be set in case of Bus Controller failure do not select Y for this entry If both entries above were set to Y setting this entry to Y would cause the CPU to set all 208 input and 208 output point fault bits associated with a Bus Controller to 1 during any CPU
154. sweep if the Bus Controller failed to communicate with the CPU This would affect only the internal status table it would not change any real I O states To use these internal references additional program logic would be required Diagnostic Range Limits This entry specifies the upper limit for diagnostics scanning The CPU scans I O channels as pairs For a system with non Expanded I O addressing this entry should be 0 to scan the Main Auxiliary I O chain pair For a system with Expanded I O addressing it defaults to the highest channel pair for which I O scanning is enabled For example if Expanded I O scanning for channels 0 3 and 8 B were enabled but diagnos tic reports were not needed from channels 3 and B you would enter the number 2 here ENTRY MAIN I O CHAIN AUX JO CHAIN 0 8 aux 1 CHANNELS 2 A BEING SCANNED 3 E B 4 5 NO 6 DIAGNOSTICS 7 In this example the program would report diagnostics from channel pairs 0 2 and 8 A 4 4 Automatic Diagnostics and Fault Clearing GFK 0171 CPU Register Size This defaults to the number of registers in the Scratch Pad The availability of register memory may limit the number of I O points for which diagnostics can be stored If the CPU register size were 256 diagnostics could be stored for only the first 256 inputs and outputs in the Main I O chain For a CPU register size of 1K diagnostics would be stored up to the first 1024 inputs and 1024 outputs of the Main I O chain I
155. t O Both may appear for some faults Address The second field shows I O reference address of the error within the channel base address for analog blocks Range 1 to 1000 Circuit Number The circuit number on the block Displayed only for a circuit fault Range 1 to 32 Fault Category This entry shows the category of error that has occurred BC FAULT BUS ERROR CIRCUIT FAULT LOSS OF BLOCK BLOCK ADDITION ADDRESS CONFLICT EEPROM FAILURE Fault Type 1f the fault is an I O block circuit fault this entry shows the error type BLOCK DISCRETE or ANALOG For other types of faults this field is blank 4 10 Automatic Diagnostics and Fault Clearing GFK 0171 Fault Description Displayed only if the Fault Category is CIRCUIT FAULT Multiple lines are displayed if more than one description is associated with a fault data entry Some example descriptions are EEPROM FAILURE LOSS OF POWER SHORT CIRCUIT OVERLOAD NO LOAD OVER TEMP SWITCH FAILED LOW ALARM HIGH ALARM UNDER RANGE OVER RANGE OPEN WIRE BC NOT OK SERIAL BUS ERROR LOSS OF MODULE ADDITION OF MODULE I O ADDRESS CONFLICT IN WIRING ERROR INTERNAL FAULT INPUT CHAN SHORT Fault Time The day hour minute second and tenth of a second The value of the CPU s real time clock when the error report was received from the Bus Controller Clearing Faults Press the F3 Clear Faults key to clear all faults in the table This sets the fault count to zero clears o
156. the Bus Controller s address plus 1000 For example 1257 For the Computer Mailbox use channel number times 1024 plus starting I O reference Use the decimal equivalent of the channel number For example Bus Controller location 257 on channel E 14 decimal would be calculated like this 14x1024 257 14593 Register 2 The second register contains the Command Number which may be one of the following Idle Read Configuration Write Configuration also used to start stop Global Data Read Diagnostics Read Analog Inputs Read Status Table Reference Switch BSM 12 Send Datagram Assign Monitor Write Device Write Point 13 Receive Datagram Read Device Register 3 Status Code This register should first be cleared to zero by the CPU It will be loaded by the Bus Controller at the end of the window command when status is available Its content may be O A YN 11 Hex Decimal 0000 00000 Not accepted CPU or Bus Controller busy with previous DPREO 0001 00001 Command in process but not completed 0002 00002 Command completed successfully 000C 00012 Command terminated due to syntax error 0014 00020 Command terminated due to data transfer error The Bus Controller verifies the Command Block for valid command syntax and the absence of a command of that type already in execution If any syntax errors exist the Bus Controller writes the error code 12 into the Status Code in the third register of the Command Block
157. tive impact on system features as previously described Each interface module can send Global Data to all other interface modules on the bus A Global Data message may consist of up to 128 bytes of register data Each interface module will receive all Global Data on the bus Global data differs from the Read Device and Write Device Datagrams which can also be used to send 128 bytes of data in several ways 1 Global Data is used for automatic and repeated register data transfer Datagrams are used to send specific messages 2 After being initialized in the program Global Data will be sent by the Bus Controller repeatedly with minimal additional programming Idle command required Each Datagram requires a DPREQ or WINDOW instruction both to send and to receive and status must be monitored 3 The Bus Controller sends all the Global Data it has received to the CPU once each CPU sweep This requires only one DPREQ or WINDOW instruction to the Bus Controller For Datagrams each message received requires a separate window command to transfer the embedded data to the CPU 4 Global Data cannot be read from or written to I O memory Datagrams can A Global Data message is always associated with a specified memory address in the sending CPU If the receiving device is a Bus Controller in a Series Six PLC the data is placed into the same registers it occupied in the sending CPU For this reason Global Data cannot be sent by two or more Bu
158. to RO1216 RO1217 to RO1280 Channel A RO1281 to RO1344 R01345 to RO1408 Channel B RO1409 to RO1472 R01473 to RO1536 Channel C R01537 to RO1600 R01601 to RO1664 Channel D RO1665 to RO1728 RO1729 to RO1792 RO1793 to RO1856 RO1857 to RO1920 RO1921 to RO1984 RO1985 to RO2048 AOO0001 to AO1024 AI0001 to AI1024 O14 0001 to 01 1024 114 0001 to 11 1024 02 0001 to O241024 124 0001 to I24 1024 O34 0001 to 03 1024 134 0001 to 134 1024 O44 0001 to 04 1024 144 0001 to 144 1024 O5 0001 to 05 1024 154 0001 to 15 1024 06 0001 to 06 1024 16 0001 to 16 1024 07 0001 to 07 1024 17 0001 to I7 1024 09 0001 to 09 1024 19 0001 to 194 1024 OA 0001 to OA 1024 IA 0001 to IA 1024 OB 0001 to OB 1024 IB 0001 to IB 1024 OC 0001 to OC 1024 IC 0001 to IC 1024 OD 0001 to OD 1024 ID 0001 to ID 1024 OE 0001 to OE 1024 1E 0001 to TE 1024 OF 0001 to OF 1024 IF 0001 to IF 1024 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel A Channel B Channel C Channel D Channel E Channel F R02049 to R02112 R02113 to RO2176 R02177 to RO2240 R02241 to R02304 R02305 to R02368 R02369 to RO2432 R02433 to RO2496 R02497 to R02560 R02561 to RO2624 R02625 to RO2688 R02689 to RO2752 R02753 to R02816 R02817 to RO2880 R02881 to RO2944 R02945 to R03008 R03009 to R03072 R03073 to R03136 R03137 to R03200 R03201 to R03264
159. to prevent data loss Each Bus Controller maintains an area in its RAM memory where it can store 16 incoming Datagrams at the same time It transfers one to the CPU each time a DPREQ or WINDOW instruction with its address is encountered in the program If there are not enough window commands directed to a Bus Controller during one CPU sweep it may accumulate only 16 incoming Datagrams If that happens additional Datagrams will be lost This loss will not be detected by the system Because only one incoming Datagram can be sent to the CPU during a single window it may be necessary to place additional window commands in the program if multiple incoming Datagrams are expected The number of window instructions to a Bus Controller that are needed depends on whether the Datagrams have been sent using Normal or High Priority and the relative lengths of the CPU sweep time and the scan time of the bus If the Bus Scan Time is Greater than the CPU Sweep Time If all Datagrams on the bus are sent with Normal Priority there is a limit of one incoming Datagram per CPU sweep Therefore only one DPREQ or WINDOW instruction per sweep will be needed to handle the incoming Datagrams If all Datagrams on the bus are sent with High Priority the Bus Controller can receive one Datagram from each transmitting device during each scan The program should include the same number of DPREQ or WINDOW instructions as incoming Datagrams If the Bus Scan Time is Less t
160. us Controller at address 0129 in the Main I O chain channel 0 CURSOR MAIN CHAIN CHANNEL LOCATIONS Bus Controller CHANNEL 0 0 00000000 00000100 1 00000000 00000000 LOCATION 8 9 location 0129 AUX CHAIN CHANNEL LOCATIONS 00000000 00000000 00000000 00000000 In this example the CPU would use the 64 1 O references starting at 0129 for diagnostic data for the Bus Controller assigned to Reference Number 0129 in the Main I O chain This is explained in chapters 8 and 9 If there were only one Bus Controller in the system no other entries would be needed Entering the Bus Controller locations on this screen completes the setup steps 4 8 Automatic Diagnostics and Fault Clearing GFK 0171 Genius I O Fault Table Screen When the PLC system is in operation faults can be displayed and cleared from the Genius I O Fault Table screen This screen lists all the faults currently stored by the CPU Faults appear in the order they are reported to the CPU with the first fault at the top To display and clear faults from 32 Circuit DC blocks and RTD blocks Logicmaster 6 version 4 01 or later is required TOTAL FAULTS 0000 GENIUS I O FAULT TABLE date TOP FAULT DISPLAYED 0000 time FAULT DISPLAYED 0000 00 00 00 0 B C POINT CIRC FAULT FAULT ADDR ADDR NO CATEGORY DESCRIPTION DAY HR MN SC T NEXT PREV CLEAR 1 PAGE 2 PAGE 3FAULTS 4 TOP 5BOTTOM 6 This screen can only be displayed if the current ladde
161. us screen illustration the table was shown with hexadecimal values Pressing the Decimal Display F1 would show the content of register R101 in decimal 00049 This is the I O reference of the I O circuit having the fault 8 28 Programming for Diagnostics Using Bus Controller Input References GFK 0171 Registers R141 through R156 can store the following information about each fault 6 5 4 3 2 1 byte number j 41 33 25 17 9 bits I O references _ Fault Type Circuit Number O block l1 discrete 2 analog __ Fault Description Fault 1 is an I O circuit fault Its fault type and description would be stored in R141 Moving the cursor to R141 would show the binary content of this register EQUALS 0000100000000001 Bit 33 the first bit shown in status byte 5 is equal to 1 That means the fault is on a discrete block The value 0 in bits 37 40 shows that the fault has occurred on the topmost circuit on the block Finally bit 45 is set to 1 showing that the fault is an OVERTEMPERATURE fault Chapter 9 9 1 Programming Commands to I O Blocks Using the Bus Controller Output References GFK 0171 This chapter explains how setting or clearing individual Bus Controller output reference bits can Disable all outputs on the bus all Bus Controllers Clear all faults Bus Controllers with Diagnostics only Clear faults on a specific circuit Bus Controllers with Diagnostics only Pulse Test discrete output
162. ut any faults currently buffered in the Bus Controller and clears the fault data currently latched at the Genius I O blocks Subsequent incoming faults fill the Fault Table from the beginning If a condition which caused a fault has not been corrected the fault message will reappear For the serial version of Logicmaster 6 software On Line changes to the CPU must be enabled to clear faults from the programmer Printing a Copy of the Fault Table Screen When the fault table is displayed on the screen it can be printed using the ALT P keys Printing must be set up as explained in the Logicmaster 6 Software User s Manual Chapter 5 5 1 Programming Window Commands GFK 0171 This chapter explains how to use window commands if the program needs to communicate with a device on the bus Each window instruction recognizes the following commands Idle Read Configuration Write Configuration Read Diagnostics Read Analog Inputs Read Status Table Address 11 Switch BSM 12 Send Datagram 13 Receive Datagram wn Ah Y N m Can also be programmed as a Datagram See chapter 6 for more information If the system includes multiple CPUs connected by a Genius bus communications between them can be programmed as described in chapters 6 and 7 Program Instructions Communications between the CPU and one of its Bus Controllers can be specified with a DPREQ or WINDOW instruction in the program or via the Computer M
163. ut references and 3 output references will actually correspond to field devices The remaining three inputs will contain feedback data from the output circuits and cannot be used for internal program logic Block 4 on bus 1 is an input block assigned to 10073 10080 To allow for the addition of blocks to both busses in the future the second Bus Controller is assigned to I O references 513 560 The blocks on bus 2 are assigned I O references from 561 to 993 3 4 Interfacing Genius I O Blocks to the Series Six PLC GFK 0171 First and Last I O Table References Reference ranges for blocks with 8 16 24 or 32 circuits are listed below References Number assignments can be recorded on copies of the Configuration Worksheet on the next page First Last Reference First Last Reference First Last Reference Reference 8 16 24 32 Reference 8 16 24 32 Reference 8 16 24 32 001 008 016 024 032 337 344 352 360 368 673 680 688 696 704 009 016 024 032 040 345 352 360 368 376 681 688 696 704 712 017 024 032 040 048 353 360 368 376 384 689 696 704 712 720 025 032 040 048 056 361 368 376 384 392 697 704 712 720 728 033 040 048 056 064 369 376 384 392 400 705 712 720 728 736 041 048 056 064 072 377 384 392 400 408 713 720 728 736 744 049 056 064 072 080 385 392 400 408 416 721 728 736 744 752 057 064 072 080 088 393 400 408 416 424 729 736 744 752 760 065 072 080 088 096 401 408 416 424 432 737 744 752 760 768 073 080 088 096 104 409 416 424 432 440 745
164. x m x D a oO P SEE opua H I OKAN mmm x A GUA E O k k gb a m UPS b uu ko ee ae OPER Kade q I eae oe Dk U x E Ak Ok 4 E pmi MV x o d u O k 4 CQ i Kk Oc H p UOK t 7 K a E LO Wo la AR k wd Z x E 0x lt r ue q a A V q c t x uU i Ox P Hi A 3 C b H A K V x i x mom H nc i x 19 a X c 4 Q SO d 9 0 o0 O I Ox CO x US EPR COR ea c m ane rea V Kk t ok B KK X K 4 i V G R UNx o I F k cA chee cic Ma MERA Ve ae Aas Boro Lo iras e E DR Fore On caro e A A O k 2 i V x a es A yp A DE et eee ee i V k 2 fu V f EE SERERE a v E Sara aah ee T pty sense Pes on GFK 017 21 onding bits in the AND mask and the 1 A MM TTS 1 1 4 e ITesp A v Q hd dh Ne e u O E 4 tting a bit to 1 its 1 e se avr ye same 1 4 original data 3 intended bit changes ww AND mask OR mask al et the remainin 4 S A a Datagrams 6 11 GFK 0171 Command Block for the Write Point Datagram Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Bus Controller Reference Number plus 1000 for a DPREQ Command Number 12 Send Datagram Status code supplied by the Bus Controller If the message is sent to one device command execution is immediate the status register will indicate

Series Six Bus Controller User`s Manual, GFK-0171B

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