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TDC502

1. according to the level specified in the same register The level of each pin can be read via the GPIO Input Register GPIO_IN_REG regardless whether configured as input or output 6 8 2 Data and Control Lines 6 8 2 1 Overview The TDC502 provides the following data and control lines e DATA 7 0 Bi directional data bus e CSN Chip select low active e RDN Read strobe low active e WRN Write strobe low active e ADR 3 0 Address bus e ALE Address latch enable high active The processor interface provides an address latch controlled by ALE in order to make various ap plications for connecting diverse processors resp controllers possible e Separated data address bus The address latch is transparent ALE 1 Thus in principle all controllers addressing a SRAM directly are connectable e g RENESAS H8 Controller e Shared data address bus Using ALE in principle all 8051 compatible 8 bit controllers are di rectly connectable e g ATMEL AT89S53 16 bit controller such as SIEMENS C167SR are possible too 6 8 2 2 Timing Diagrams Figure 6 6 and Figure 6 7 show the read and write cycle timings for applications with separated data address bus In Figure 6 8 and Figure 6 9 the read and write cycle timings for applications with shared data address bus are shown In Table 6 1 and Table 6 2 the associated read and write cycle timing characteristics are specified TDC502RefManEngV26 doc Version 2 6 Author AP
2. Measurement Error ns 9988 3 9000 4 9026 Time ns Figure 8 5 Measurement Errors of Singleshot Measurements at 5V Measurement Mode 6 8 15 2 Simultaneous Singleshot Measurements on both Channels When measurement mode 2 or 3 is selected and the stop inputs STOP_A and STOP_B are com bined the same time difference can be measured simultaneously on both channels Averaging the two measurement results will improve the measurement s accuracy by up to approx 30 and dou ble the TDC s resolution of up to 23ps at 5V resp 33ps at 3 3V typ Table 8 23 shows the doubled resolution ps of simultaneous singleshot measurements of a TDC at 5V in measurement mode 2 as well as the singleshot standard deviation resp rms resolution o ps The measurement period is from 100 to 300ns All other conditions are the same as given in the previous Chapter 8 15 1 The one sigma area 0 contains about 68 of the simultaneous singleshot measurement results About 95 5 will fall within the two sigma area 20 Measurement Kind of Doubled Resolution ps Resolution 5V 3 3V half normal high smart Table 8 23 RMS Resolution o ps of simultaneous Singleshot Measurements MM 2 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 67 of 68 Figure 8 6 shows exemplarily the measurement errors of simultaneous singleshot measurements on both channels wit
3. typical at 5V 25 C High Resolution Maximum measurement period is shortened by half Smart Resolution Maximum measurement period is shortened to the fourth part TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 20 of 68 5 3 5 Measurement Modes 6 and 7 Mode s 6 and 7 measurements are executed within measurement range II using both the measuring core and the precounter As shown in Figure 5 8 one channel with up to 4 hits and a double pulse resolution of 7 5 tca 105ns 5V 25 C is available In this formula ca is the divided calibra tion clock period Via software channel A or channel B is selectable The minimum measurement period is 7 5 tea 105ns 5V 25 C too When the time measurement is completed in measure ment mode 6 an automatic calibration measurement on the selected channel follows according to Chapter 5 2 As shown in Figure 5 8 for each hit time measurements are divided into three stages 2 stage separated for each hit CLK START f precounter 0 0 ee PREI 1 PREI DET 0 0 1 Bes PRE2 p precounter 0 0 1 Ser PRE4 l STOP_A resp STOP_B E EES eme SE Ai f start hit 1 hit 2 hit 4 21 5 tear 105ns 2 1 5 tear 105ns Figure 5 8 Measurement Modes 6 and 7 In the first stage of the measurement the measuring core determines the time difference between the start signal and the following rising edge of the divided calibratio
4. 206 431 A TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 64 of 68 8 14 Power On Characteristics The minimum pulse width of a low active power on reset pulse connected to pin RSTN is 100us Figure 8 4 shows a possible reset circuit RC circuit VDD TDC R 1k RSTN C et GND Figure 8 4 Reset Circuit After power on reset the TDC is in the default state The TDC is not ready for measurements because the measurement channels are disabled After activating the action bit time measurement within the Init Register see Chapter 7 Programming of the TDC502 the TDC is ready for a time meas urement in measurement mode 0 and waits for a rising edge on the start input START and a rising edge on the stop input STOP_A channel A TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 65 of 68 8 15 Measurement Results 8 15 1 Singleshot Measurements and RMS Resolution Table 8 21 and Table 8 22 show the time based singleshot standard deviation o ps also re ferred to as rms resolution and the resolution based singleshot standard deviation o LSB All singleshot standard deviations are averaged values derived from measurements on both channels of a TDC502 at the conditions given below In a normal distribution the so called one sigma area to contains about 68 of the measurement results About 95 5 will fall within the two sigma area 20 Measurement period 100
5. 7 2 1 3 Hit Register HIT_REG Figure 7 5 shows the format of the Hit Register Be sure to enable not more hits burst mode meas urements than allowed within the selected measurement mode see Table 5 1 Within the mea surement modes 0 1 4 5 6 and 7 only four bits of the Hit Register are relevant depending on the channel selector bit of CTRL_REG_1 Within the measurement modes 2 and 3 all bits are relevant 7 4 3 0 Bit Default No of hits burst mode No of hits burst mode measurements channel B measurements channel A 0000 0 0000 0 0001 1 0001 1 0010 2 0010 2 0011 3 0011 3 0100 4 0100 4 0101 5 0101 5 0110 6 0110 6 O111 7 0111 7 1000 8 1000 8 1001 9 1001 9 1010 10 1010 10 others reserved others reserved Figure 7 5 HIT_REG Format TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 42 of 68 7 2 1 4 Interrupt Enable Register INT_EN_REG Figure 7 6 shows the format of the Interrupt Enable Register A detailed description of the register bits representing the enabling of the interrupt request flag set signals is given in Chapter 6 8 3 2 7 5 4 3 2 1 0 Bit 0 oT of 0 0 j 0 J Default L I_OV_CORE reserved 0 disabled I VALID 1 enabled 0 disabled 1 enabled LOV PRE 0 disabled 1 enabled I ALU END I MEAS END 0 disabled 0 disabled 1 enabled 1 enabled Figure 7 6 INT_EN_REG Format 7 2 1 5 GPIO Configuration Register
6. ALU Calculation of every hit to start and every hit to each other hit negative results possible 1 2 1 channel A or B programmable with 10 fold burst capability start stop Dead time between burst mode measurements start stop 100ns 5V 25 C ALU calculation of each start stop 5 Measurement range II 1 channel A or B programmable with 4 fold multi hit capability Double pulse resolution 1 5 divided period of calibration clock 105ns 5V 25 C ALU Calculation of every hit to start and every hit to each other hit negative results not possible 4 Measurement range I Note e In measurement modes 1 3 5 and 7 separate calibration measurements have to be performed on occasion by activating the action bit separate calibration measurement within the Init Register see Chapter 6 5 1 1 Table 5 1 Measurement Modes typical at 5V 25 C High Resolution Maximum measurement period is shortened by half Smart Resolution Maximum measurement period is shortened to the fourth part Measurement range depends on period of calibration clock TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 14 of 68 5 3 1 General Measurement Cycle Figure 5 4 shows the flowchart of a general measurement cycle At the very beginning of a meas urement cycle the measurement mode the usage of the ALU and so on has to be specified within the TDC s Control Registers In the
7. Remarks e The hitcounters are cleared on power on and soft reset or by activating the action bits time measurement or separate calibration measurement e The hitcounters are disabled during any kind of calibration measurements TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 28 of 68 6 4 Arithmetical Logic Unit ALU The ALU executes time difference calculations hit to start hit to another hit calibration and mul tiplication using a 24 bit unsigned integer number negative results are possible on the measure ment calibration and precounter values of the raw value registers in accordance with the formulas 1 to 11 see Chapter 5 3 For doing calculations the ALU requires calculation rules defined via software in the Control ALU and Multiplication Registers If the ALU is enabled via software the first ALU calculation within a measurement cycle starts automatically following a time or calibration measurement The result of the first ALU calculation within a measurement cycle is always stored in result register 0 After modifying the calculation rules an unlimited number of calculations can be initiated by activating the action bit ALU calcu lation again and again The results are stored then alternating in the result registers 1 0 1 0 During ALU calculations the status flag ALU_BUSYN is active low When the result is calcu lated and stored in one of the two result regist
8. User Manual TDC502 Page 33 of 68 DwR DATAL7 0 L LLLLLLLLLLTX KILL LLL LLL LLL LLL wRD RDWR twrn twr O WRN c tcswR twrcs CSN ADRWR ADRB3 0 L L LLLLLL LLLX__ KD WRADR Figure 6 6 Separated Data Address Bus Write Cycle Timing ALE 1 tRDD1 DATA 7 0 lt gt tRDD2 wo tcsRD trpcs CSN tapRD ADRIEN WILL LLL LLL LLL RDADR Figure 6 7 Separated Data Address Bus Read Cycle Timing ALE 1 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 34 of 68 ALEADR DwR DATA ADR Re LLLLXRATAL K K AR KD ADRALE wRD u Br N WRN twrcs CSN RDALE ALE tALE WRALE Figure 6 8 Shared Data Address Bus Write Cycle Timing tALEADR RDD2 DATA ADR ADR gt lt DATA_ ADR gt taADRALE Depp WRN RDN trp as RDN tRDCS SS DE WRALE ALE tALE RDALE Figure 6 9 Shared Data Address Bus Read Cycle Timing TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 35 of 68 E ng ee tee tm 25 m wow 8 n tw 0 m tawr 8 n war 2 m tm 0 m E E teen 25 tanna 3 CALE tALEWR WRALE tRDALE VDD 5V 10 T 40 to 85 C Load 30pF 3 0V lt VDD lt 4 5 V All times listed above have to be multiplied by 1 5 e 2 7V lt VDD lt 3 0V All times listed above have to be multiplied by 2 Table 6 1 Write Cycle Timing Charact
9. a std TDC 0 3 Measurement Error 0 2 Lm mai Tc oc A e 0 100 200 300 400 Time ns Figure 8 8 Standard Deviation and Measurement Error with Auto Noise Unit The comparison of the figures shows that on average the standard deviation is smaller when oper ating without auto noise unit When measuring the same time difference several times then the same quantisation stage LSB of the TDC is hit very often or permanently So the standard deviation becomes small whereas the measurement error approx LSB remains huge Since this error is mainly based upon the TDC s quantisation it can be minimized when operating with auto noise unit which cuts off the peaks of the characteristics So the measurement errors become smaller Further more the standard deviation of the average measurement results is improved by about 1 V64 from o 125ps singleshot measurement see Table 8 21 down to O 4 17ps The systematic offset error of approx 700ps is irrelevant here too TDC502RefManEngV26 doc Version 2 6 Author AP
10. and Multiplication Registers Activation of action bit time measurement within the Init Register Time measurement Calibration measurement ALU calculation Configuration allowed only when no action bit is set within the Init Register Possibility of separate calibration measurements via direct command New configuration of Control ALU and Multiplication Registers Activation of the action bit ALU cal culation within the Init Register Figure 5 4 General Measurement Cycle Flow TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 15 of 68 If the ALU is used now the first calculation according to the ALU calculation rules and specifica tions within the Control ALU and Multiplication Registers is executed and the result of this first calculation within a measurement cycle is always stored in result register 0 Afterwards the action bit time measurement is cleared automatically After modifying the ALU calculation rules repetitive activation of the action bit ALU calculation within the Init Register makes an unlimited number of calculations possible The results are stored then alternately in the result registers 1 0 1 After completion a calculation the action bit ALU calculation is cleared automatically each time For another time measurement the action bit time measurement has to be reactivated The first ALU calculation result
11. counter 0 1 0 Expansion of measurement range II disabled high impedance 2 _ GPIOO Bidi 4mA T general purpose T O default high impedance 9 GPIO Bidi 4mA Tt general purpose VO default high impedance 0 TDC not ready measurement channels disabled 1 TDC ready for measurement TDC waits for start 34 INTFLAG Out 4mA 0 no interrupt request 36 START In Common start input TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 10 of 68 Din Ko L t some VO Function 37 EN_STOP_B In Enable stop input channel B 0 Stop input STOP_B disabled cannot be enabled via software 1 Stop input STOP_B enabled if not disabled via software STOP_B Stop input channel B STOP_A Stop input channel A 42 EN_STOP_A In Enable stop input channel A 0 Stop input STOP_A disabled cannot be enabled via software 1 Stop input STOP_A enabled if not disabled via software In measurement range II the stop input of the selected channel has to be enabled during the whole time measurement Remarks e All inputs are CMOS e Connect all unused inputs to GND e Data bus DATA 7 0 is not allowed to float please pull up or down with e g 10kQ e Do not connect unused outputs Table 4 2 Pin Function List TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 11 of 68 5 Measuring Procedure The TDC502 provides two identical measurement chann
12. 1000 e Measurement mode 5 Calculation of the 10 burst mode measurement start stop on the channel selected via CTRL_REG_1 1010 0000 e Measurement mode 7 Calculation of the time difference between the 2 hit and the 1 hit on the channel selected via CTRL_REG_1 0010 0001 7 2 1 9 Multiplication Registers MULT_REG_1 MULT_REG 2 MULT_REG_3 The formats of the Multiplication Registers are shown in Figure 7 11 MULT_REG_1 is the low byte MULT_REG_2 is the middle byte and MULT_REG_3 is the high byte of the 24 bit unsigned integer number the ALU uses for multiplication Bit 7 of MULT_REG_3 is 1 Bit 6 is Bit 5 is 14 etc 7 0 Bit MULT_REG 3 10000000 Default MSB LSB 7 0 Bit MULT_REG 2 00000000 Default MSB LSB 7 0 Bit MULT_REG_1 00000000 Default MSB LSB Figure 7 11 MULT_REG_1 MULT_REG2 and MULT_REG_3 Formats TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 46 of 68 7 2 2 Read only Register Formats 7 2 2 1 Hit Status Register HIT_STATUS_REG Figure 7 12 shows the format of the Hit Status Register 7 4 3 0 Bit Default No of detected hits burst mode No of detected hits burst mode measurements on channel B measurements on channel A 0000 0 0000 0 0001 1 0001 1 0010 2 0010 2 0011 3 0011 3 0100 4 0100 4 0101 5 0101 5 0110 6 0110 6 0111 7 0111 7 1000 8 1000 8 1001 9 1001 9 1010 10 1010 10 others reserved others reserved Figur
13. 300ns Mode 0 9 10us Mode 6 Increment Ins Sampling rate One measurement per measuring point Calibration clock 4 MHz 2 2 MHz Division factor of the calibration clock divider 2 Automatic calibration measurement without offset generation Offset generation via separate calibration measurement before overall measurement Supply voltage 3 3V and 5V Temperature approx 28 C Reference Measurements Universal Time Interval Counter SR620 Stanford Research Sys tems Measurement Mode Kind of Resolution Resolution ps o LSB half normal high smart half normal high smart Table 8 21 RMS Resolution 6 at 5V Measurement Modes 0 and 6 Measurement Mode Kind of Resolution Resolution ps o LSB half normal high smart half normal high smart Table 8 22 RMS Resolution e at 3 3V Measurement Modes 0 and 6 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 66 of 68 Figure 8 5 shows exemplarily the measurement errors of singleshot measurements on channel A with measurement mode 6 and Smart Resolution selected at 5V The offset of the diagram is ap prox 700ps This systematic error results from a different length of cables for start and stop and is irrelevant here ac Smart_543 Resolution Singleshot from 9 to 10us Increment 1ns Cal Clock 2MHz 5V Channel A MM 6 FR Ng A
14. 3G Jy Vu cmos Up Low Voltage OND 03 03V V__ um cu Input High Voltage 0 7 Vp Vn 0 3 V__ iy Input Current Vin VonorGND_ 10 _ o n Nos cmos Output High Voltage Tou 4mA Vm 08 W Vor cmos Output Low Voltage loz 4mAa Jos y e 3 State Output Leakage Current Von Von or GND _ 10 io nA NOTE Junction temperature range 55 C to 125 C Table 8 2 DC Characteristics Vpp 3 3V 0 3 to 7 0 Ves __ Vw Input Pin Voltage L 3m Von 0 3 v _ ben CW Electrostatic Discharge 1000 JN R 1 5kOhm C 100pF Lead Temperature 260 _ IC T 105 NOTE Stresses above these values may cause permanent damage to the device Table 8 3 Absolute Maximum Ratings TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 51 of 68 8 2 Resolution 8 2 1 How to calculate the Resolution The TDC s resolution RES is calculated using the divided calibration clock period tcar and the calibration values CAL and OFFSET RES tea CAL OFFSET A0 8 2 2 Voltage Dependence Table 8 4 shows the voltage dependence of the Normal Resolution at normal conditions typical process ambient temperature approx 28 C arised from averaging the measured resolution of sev eral TDCs Supply Voltage Normal Resolution V ps Table 8 4 Resolution Voltage Dependence Ta 28 C typ At Half Resolution the specified values of Table 8
15. 43 7 2 1 7 Smart Resolution Registers SSMART_REG_A SMART_REG B 43 7 24 8 ALU Register AL URE Gy Se 44 7 2 1 9 Multiplication Registers MULT_REG_1 MULT_REG_2 MULT_REG_3 45 1225 Reag only Register Form ls uk ara ea 46 72 2 1 Hit Status Register HIT_STATUS_REG ccssccsscssscssecessccesscessessnceeseesennsees 46 72 2 2 GPIO Input Register GPIO IN REG esd ecco cute 2 46 17223 Stans Register STATUS REG as a n ii a eset 47 71 3 RAW VALUE RESISTERS Zain RR RR eae 48 7 3 1 Raw Value Resister Formal unseres 48 RES e Raw ENTREE 48 It RESULT REGIS TERS EZ conve dese nei 49 TAM Result Register F rmat nisseno Akne ems 49 TAZ Result Data Formats inean a EE EI een 49 So CIP Nera re ee 50 8 1 ELECTRICAL SPECIFICATION a De der 50 827 RESOLUTION Seelen een au 51 8 2 1 How to calculate the Resolution su uusenamenkik ea 51 3 22 Voltage RE 51 8 2 3 Temperature Dependence an 51 8 3 DIFFERENTIAL NON LINEARITY aussen a en 52 8 4 MEASUREMENT RANGE I MINIMUM MAXIMUM MEASUREMENT DR 53 8 4 1 Minimum Measurement Period se 53 8 4 2 Maximum Measurement Period 20a er 53 8 5 MEASUREMENT RANGE Il MINIMUM MAXIMUM MEASUREMENT PERIOD nsss 54 8 5 1 Minimum Measurement Period uassesscinsssannhshkuun ek us 54 8 5 2 Maximum Measurement Period A ans NND 54 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 4 of 68 8 6 DOUBLE PULSE EEN LCE 55 5 6 1 Measurement Range EE 55 8 02
16. Default Bit 0 Time measurement e Time measurement is Address space selection enabled 00 Address space 0 Result registers are cleared 01 Address space 1 Measuring core and 10 Address space 2 precounter overflows are 11 Address space 3 Bit 1 Separate calibration measurement Generation of new calibration values CAL and OFFSET for one or both channels depending on the measurement mode the channel selector bit in CTRL_REG_1 and e Bitiscl d ical the Bit Disable Offset in CTRL_REG_3 IS automatica y when the measurement cycle Measuring core and precounter overflows is completed see chapter are cleared BR 5 3 1 General Measurement Bit is cleared automatically when the cleared Bit 4 Reset INTFLAG Cycle or when the e Interrupt request flag measurgmentiis completed or when the measurement cycle is aborted INTFLAG is cleared measurement eyele isaborted via bit 5 e Bitis cleared automatically Bit 2 ALU calculation e ALU calculations calibration multiplication are executed e Bitis cleared automatically when ALU calculations are completed or when the measurement cycle is aborted via bit 5 Bit 5 Abort measurement cycle e Ongoing measurement cycle or ALU calculations are aborted e All data already stored in the raw value registers remain unaffected Result registers are cleared e Generates a new offset delay for auto noise unit e Bit i
17. Flags and Interrupt Request Flag set Signals Figure 6 10 shows exemplarily the correlation of status flags and IRQ flag set signals on the base of a correct and two faulty measurement cycles The status flags are represented as time dependant characteristics Setting IRQ flag set signals to 1 is marked as events End of time calibration End of ALU Activation of Startofa 1 raw value measurement all calculation Next activation Next start action bit time register raw values result register of action bit of a time Overflow time measure contains registers valid start contains valid time measure Overflow precounter measurement ment valid data of ALU calculation data measurement ment core TDC_READY MEAS_BUSYN VALID ALU_BUSYN OV_PRE OV_CORE faulty correct faulty pnd measurement gt lt __ measurement _ gt lt __ measurement Figure 6 10 Correlation of Status Flags and Interrupt Request Flag set Signals TDC502RefManEngV26 doc Version 2 6 Author AP 7 Programming of the TDC502 Programming the TDC configuring and reading out the TDC s status and measurement results is done via the processor interface The relevant data is read and written via the bi directional data bus DATA 7 0 7 1 Addressing As shown in Table 7 1 the TDC provides four address spaces for addressing the TDC registers the raw value registers and
18. GPIO_REG 7 6 5 4 3 2 1 0 Bit a 17 a De 0 0 Default L GPIOO operation mode 0 Input 1 Output GPIO1 operation mode 0 Input 1 Output GPIO2 operation mode 0 Input 1 Output GPIO3 operation mode 0 Input 1 Output Level of GPIOO when operating as output 0 low level 1 high level Level of GPIO1 when operating as output 0 low level 1 high level Level of GPIO2 when operating as output 0 low level 1 high level Level of GPIO3 when operating as output 0 low level 1 high level Figure 7 7 GPIO_REG Format TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 43 of 68 7 2 1 6 High Resolution Registers HIGH_REG_A HIGH_REG_B The format of the High Resolution Registers is shown in Figure 7 8 Optimal configurations of the ses registers are shown in Table 7 2 7 37 2 0 Bit LL eat reserved Fine tuning Smart and High Resolution 000 Smart and High Resolution disabled 001 010 011 100 101 110 allowed 111 reserved Figure 7 8 HIGH_REG_A and HIGH_REG_B Format 7 2 1 7 Smart Resolution Registers SMART_REG_A SMART_REG_B Figure 7 9 shows the format of the Smart Resolution Registers Optimal configurations of theses registers are shown in Table 7 2 7 6 4 3 2 0 Bit o wo ol o _ Default reserved reserved Fine tuning Smart Resolution part 1 000 Smart Resolution disabled i 001 010 011 100 1
19. Hit Register the number of hits or burst mode measurements has to be defined a measurement cycle consists of For optimization the TDC s differential non linearity the Smart and High Resolution Registers have to be configured If the ALU is used for calculation the measurement results the ALU Register and maybe the Multiplication Registers have to be configured as well For detailed information on the TDC registers refer to Chapter 6 5 The actual measurement cycle is initiated by activating the action bit time measurement within the Init Register Now the TDC is ready for measurement and waits for a start signal on the start input START After start has taken place the time measurement continues until the number of hits on the Stop inputs STOP_A and STOP_B or the number of burst mode measurements specified in the Hit Register cp Chapter 6 5 1 3 is reached If the ALU is not used for calculations the action bit time measurement is cleared automatically now in the measurement modes 1 3 5 and 7 In measurement mode 2 an automatic calibration measurement follows performed on both chan nels in measurement modes 0 4 and 6 on the channel selected in the Control Register When the calibration measurement is completed and the ALU is not used for calculations the action bit time measurement is cleared now Starting point Configuration of Control Hit High and Smart Resolution Registers Configuration of ALU
20. Rees Bee 29 65 1 6 berg Enable Register 29 6 5 1 7 High Resolution Registers sea lan Sieste 30 6 5 1 8 Smart Resolution Resistenz eek 30 6 5 1 9 GPIO Configuration Eg iS EL ana EE 30 0 5 2 Read Only RESISTELS una ee ee uk 30 6 5 2 HieStatus Register anne a 30 6 32 2 GPIO Inp t EE 30 6 5 2 3 Status Resister ee 30 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 3 of 68 6 6 RAW VALUE REGISTERS EE 31 6 7 RESULT REGISTERS ande Kr ee ee ee es 31 6 9 PROCESSOR INTERFACE en et 31 6 8 1 EELER e ee eege 32 0 8 2 Data and Control Liness ee Ee E 32 6 2 2 1 E EE 32 6 822 Emm EEGEN 32 6 8 3 Status and Interrupt Request lass u ee ee 36 6 6 3 1 Status Flags nn ENE T ERRE EEEE TE 36 6 8 3 2 Interrupt Request Has nn His 37 6 8 3 3 Correlation of Status Flags and Interrupt Request Flag set Signals 37 7 PROGRAMMING OF THE TDC502 nun 38 7 1 e 38 122 VEEDEBREGISTERS eur ass ae ed Go Sere uo S s ah done bel oa a che ae Sth Sale ch maa aoe 39 72 1 Read Write Register Formats u 222 ae il 39 72 11 Jmit Register CIN YR BG EE 39 7 2 1 2 Control Registers CRTL_REG_1 CRTL_REG_2 CTRL_REG 3 40 72 3 Hit Register HIT REG u a 41 7 2 1 4 Interrupt Enable Register INT_EN_REG ccccssscsesresssscecsnstecesresenenenenens 42 7 2 1 5 GPIO Configuration Register OGPIO RO 42 7 2 1 6 High Resolution Registers HIGH_REG_A HIGH_REG_B eee
21. VALx CAL and OFFSET in accor dance with the TDC s quantisation characteristic shown in Figure 5 2 as follows VALy VALx si CAL OFFSET 2 tres If the ALU is used for calculation the time difference tggs the fraction of formulas 1 and 2 is com puted during calibration If the ALU is used not only for calibration but also for multiplication tcaL has to be set up within the multiplication registers to numbers between 0 and 2 If the multiplication is disabled via software tcay remains and no multiplication is executed If VALx is greater than VALy within formula 2 the measurement result trgs becomes negative when using the TDC s ALU TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 17 of 68 5 3 3 Measurement Modes 2 and 3 Mode s 2 and 3 measurements are executed within measurement range I using the measuring core As shown in Figure 5 6 both channels with a common start and up to 4 hits each are available The double pulse resolution is 25ns 5V 25 C for hits on the same channel and Ons for hits on different channels When the time measurement is completed in measurement mode 2 an automatic calibra tion measurement on both channels follows according to Chapter 5 2 time measurement gt 25 ns 0 ps common start hit 1 ch A hit 1 ch B hit 2 ch B hit 2 ch A hit 4 ch B hit 4 ch A VALIA VALIB VAL2B VAL2 A evesen VAL4B VAL4 A Figure 5 6 Measurement Modes 2 and 3
22. difference trgs between hit y 1 lt y lt 4 on channel A and hit x 1 lt x lt 4 on channel B is calculated using the divided calibration clock period tcar and the raw values VALy A VALx B CAL A OFFSET A and OFFSET B in accordance with the TDC s quantisation characteristic shown in Figure 5 2 as follows _ VALy A OFFSET A VALx B OFFSET B CAL A OFFSET A CAL 8 tres If the ALU is used for calculation the time difference tres the fraction of the formulas 3 to 8 is computed during calibration If the ALU is used not only for calibration but also for multiplication tcar has to be set up within the multiplication registers to numbers between 0 and 2 If the multipli cation is disabled via software tcar remains 1 and no multiplication is executed When using the TDC s ALU the measurement result trgs may become negative Application Note When the stop inputs STOP_A and STOP_B are combined the same time difference can be meas ured simultaneously on both channels Averaging the two measurement results will improve the measurement s accuracy and double the TDC s resolution of up to 23ps at 5V resp 33ps at 3 3V typ TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 19 of 68 5 3 4 Measurement Modes 4 and 5 Burst Modes Mode s 4 and 5 measurements are executed within measurement range I using the measuring core As shown in Figure 5 7 one channel with up to 10 burst m
23. enabled by the start signal and disabled by the last hit defined in the hit register cp Chapter 6 5 1 3 With every hit the current 15 bit counter reading PRE is stored as precounter value in a raw value register In doing so the maximum measurement period of measurement range II is typnmax 2 5 tcaL cp Appendix 8 5 2 If the time difference the precounter has to measure exceeds the maximum measurement period a precounter overflow OV_PRE will occur and if enabled the signal I OV_PRE sets the TDC s interrupt request flag INTFAG cp Chapter 6 8 3 1 Thus the ongoing measurement cycle is aborted including any automatic calibration measurement and ALU calculations All data measure ment and precounter values already stored in the raw value registers will remain unaffected Even if the expansion of measurement range II is enabled via software a precounter overflow OV_PRE will occur and if enabled the signal I_OV_PRE will set the TDC s interrupt request flag INTFAG as well The ongoing measurement cycle however is not aborted and the TDC s sig nal EX_MBII toggles at every overflow of the precounter 1 overflow 0 gt 1 2 overflow 1 gt 0 3 overflow 0 gt 1 etc Remarks e Ifthe expansion is disabled EX_MBII remains on high impedance e EX MBI is only cleared on power on and soft reset or by activating the action bit time measurement whereas it is not cleared by activating the action bit separat
24. value VAL is dependant on the temperature and the supply voltage Therefore it has to be weighted according to the TDC characteristic see Figure 5 2 Offset and gradient of the characteristic have to be determined by a so called calibration measurement TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 12 of 68 TDC raw value measurement value calibration value CAL VAL OFFSET gt t res tcaL Figure 5 2 Characteristic of the TDC Measuring Core 5 2 Generating Calibration Values To generate the calibration values OFFSET and CAL shown in Figure 5 2 a calibration clock has to be provided at the TDC s pin CALCLK This clock is the absolute time reference and therefore it must have the precision of a quartz crystal The calibration clock is divided by the internal calibra tion clock divider The resulting clock CLK is the internal reference clock Its period length is mea sured during a calibration measurement using the measuring core CAL CLK tcaL Figure 5 3 Calibration Measurement Depending on the measurement mode the calibration measurement is performed for only one chan nel or both Just like a measurement value VAL the resulting calibration values CAL A CAL B and OFFSET A OFFSET B are stored in the raw value registers The time tcar is well known It is the divided calibration clock period A calibration measurement is performed either automatically afte
25. 01 110 allowed Fine tuning Smart Resolution part 2 iti teseryed 000 Smart Resolution disabled 001 010 011 100 101 110 allowed 111 reserved Figure 7 9 SMART_REG_A and SMART_REG_B Format Resolution HIGH_REG_A B SMART_REG_A B Half 0x00 0x00 Normal 0x00 0x00 High 0x04 0x00 Smart 0x04 0x65 Table 7 2 Optimal Configuration of High and Smart Resolution Registers TDC502RefManEngV26 doc Version 2 6 Author AP MSC User Manual TDC502 Page 44 of 68 MSC g 7 2 1 8 ALU Register ALU_REG Figure 7 10 shows the ALU Register s format for each measurement mode according to the ALU calculation rule format see Chapter 6 5 1 4 HIGH_NIBBLE LOW_NIBBLE 7 HIGH_NIBBLE 4 3 LOW_NIBBLE 0 Bit Modes 0 1 0001 0000 Default Event high nibble Event low nibble 0001 Hit 1 0110 Hit 6 0000 Start 9110 Hit 6 0010 Hit 2 0111 Hit7 0001 Hit 0111 Hit7 0011 Hit 3 1000 Hit 8 0010 Hit2 1000 Hit 8 0100 Hit 4 1001 Hit 9 0011 Hit3 1001 Hit 9 0101 Hit 5 1010 Hit 10 0100 Hit4 1010 Hit 10 others reserved 0101 Hit5 others reserved 7 HIGH_NIBBLE 4 3 LOW_NIBBLE 0 Bit Modes 2 3 o o al og ___ Default Channel high nibble Event high nibble Channel low nibble Event low nibble 0 Channel A 001 Hit 1 0 Channel A 000 Common Start 1 Channel B 010 Hit 2 1 Channel B 001 Hit 1 011 Hit 3 010 Hit 2 100 Hit 4 011 Hit 3 others reserved 100 Hit 4 ot
26. 4 have to be doubled at High Resolution the values have to be shortened by half and at Smart Resolution they have to be shortened to the fourth part 8 2 3 Temperature Dependence The Normal Resolution increases by factors of approx 0 6 ps K at Vpp 3 3V and approx 0 4 ps K at 5V At Half Resolution the factors have to be doubled at High Resolution the factors have to be shortened by half and at Smart Resolution they have to be shortened to the fourth part TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 52 of 68 8 3 Differential Non Linearity The quality of a measurement not only depends on the TDC s resolution but also on its so called differential non linearity DNL The DNL is a criterion for the variation of the quantisation stage s width LSB width Figure 8 1 shows a typical histogram of the TDC s LSB widths for Normal Resolution at Vpp 5V where the average LSB width is identical with the resolution RES Furthermore the figure il lustrates the definition of the DNL TDC502 LSB width at Normal Resolution 250 It max A 200 fl Si sel Lei 150 LSB width ns maximun differential non linearity max DNL max A RES 50 medium differential non linearity m DNL m A RES 0 4 SN cb SD di CO QD Vv wi wD oh o
27. 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 10 Setup and Hold Time EN_STOP_A B to STOP_A B Timing Characteristics TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 57 of 68 8 9 Timing when initiating and starting a Time Measurement Figure 8 3 shows the timing of the TDC s pins WRN START and TDC_READY when initiating and starting a time measurement In Table 8 11 the associated characteristics are specified They are relevant for falling edge triggered start signals too WRN when setting the Init Register s bit 0 to 1 TDC_READY Load 30pF START Figure 8 3 Timing when initiating and starting a Time Measurement Conditions gt Setup time for start Minimum pulse voltage temperature process detection twrns ns width fu er ns 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst ter is relevant only when the retrigger unit is not enabled Maximum values Table 8 11 Timing Characteristics when initiating and starting a Time Measurement 8 10 Dead Times Due to the measurement principle a TDC has got a dead time tror after the execution of a time measurement Depending on the configuration and the measurement mode this time period differs within a wide range During the dead time the start and stop detection of the TDC s measuri
28. 7 15 the width of all raw value registers is 16 bit Therefore two read cycles are necessary to read out a complete raw value via the 8 bit processor interface see Table 7 1 The raw value registers are not resettable so there default state is undefined after power on or soft reset 15 8 7 0 Bit Default High byte Low byte Figure 7 15 Raw Value Register Format Table 7 3 shows the raw value register mapping which depends on the measurement mode oe wu vama vaa Table 7 3 Raw Value Register Mapping 7 3 2 Raw Value Data Format All raw values are 16 bit unsigned integer numbers Thus the maximum number for measurement and calibration values is Oxffff 65535 Because the MSB of precounter values is fixed to 0 at all times there maximum number is 0x7fff 32767 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 49 of 68 7 4 Result Registers The TDC provides two read only result registers ERG_REG_O and ERG_REG_1 which are filled with ALU calculation results alternately within a measurement cycle beginning with ERG_REG_0 7 4 1 Result Register Format The width of the result registers is 32 bit Therefore four read cycles are necessary to read out a complete measurement result via the 8 bit processor interface see Table 7 1 Figure 7 16 shows the format of the result registers 31 24 23 16 15 8 7 0 Bit 00000000 00000000 00000000 00000000 Default High byte Low byte Hig
29. ASIC Design Center VERTRIEBS GMBH User Manual TDC502 Version 2 6 Date 2006 08 14 MSC Vertriebs GmbH ASIC Design Center IndustriestraBe 16 76297 Stutensee Author AP Phone 497249 910 288 Fax 497249 910 268 Email ap msc ge com competence in electronics User Manual TDC502 Page 2 of 68 Contents e a Hee Ee NOTE 5 20 FEATURES seele ie 6 3 BOG IGT EAN ORAM EE A E E E nel need ease 7 4 PACKAGE AND PIN GCONPIGURA TION Mau he 8 4 1 PACKAGE nk er re er ee 8 AD PINCONFIGURATION ns HERE 9 5 MEASURING PROCEDURE senken es sea 11 5 1 TIME DIFFERENCE MEASUREMENT unseren 11 5 2 GENERATING CALIBRATION VALUES an ze Re Seed 12 5 3 MEASUREMENT RANGES AND MEASUREMENT Monte 13 5 3 1 General Measurement Cycle ns asia 14 5 3 2 Measurement Modes EE 16 5 3 3 Measurement Modes 2 and 3 u a hierdie oles 17 5 3 4 Measurement Modes 4 and 5 Burst Modes t 19 5 3 5 Measurement Modes 6 and Tara ee naar 20 6 PUNGEHIONABDESERIP HON une use el 22 6 1 CALIBRATION CLOCK DIVIDER ne ne ee 22 6 2 VIMBASUREMENTCHANNEES leerer S 23 02 4 Input Unten 23 0 2 27 ee 24 6 23 TROIS er Unit ae Heeres ie 25 624 Auto NOISE Unit snanar I nu en 25 6 2 3 Messurins E 27 6 3 HITCOUNTER lee 27 6 4 ARRITHMETIGAL LOGIC UNIT AL WM 2 2 Nena E EE E eS 28 6 5 RR geg 28 GR e Read Write RG Si SUCKS ee 28 69 1 5 PIE Reste E 28 e EE Control Resister ik ke 29 6 5 03 E KEE 29 Col A SALUReBISIer with Eee eg 29 6 35 13 Multiplieation
30. L 175ns 2 5 tcar 175ns 3 6V 40 C best 1 5 tcaL 65ns 1 5 tcaL 60ns 2 5 tcaL 60ns 3 3V 25 C typ 1 5 u tcaL 120ns 1 5 cat 110ns 2 5 tca 110ns 3 0V 85 C worst 1 5 tca 285ns 1 5 tcar 270ns 2 5 tcar 270ns Notes e Pin INTFLAG with Load 30pF e tca divided calibration clock period e If the auto noise unit is enabled the time tay shown in Table 8 16 has to be added to ty up tv sc m and ty sc o e If the retrigger unit is enabled the time tgr shown in Table 8 16 has to be added to ty ve tv sc m and ty sc o Table 8 18 Timing when the first raw value of a measurement is generated When using the status flag VALID or the IRQ flag set signal I_VALID for pin INTFLAG please be sure not to re initiate the TDC for another time measurement or to start a separate calibation meas urement before the end of the measurement s dead time see Appendix 8 10 8 13 Current Consumption The current consumption of the TDC502 is one of the most important criteria if it is to be used in battery operated devices The current consumption basically depends on the runtime of the meas uring core shown in Table 8 20 and the ALU calculations times shown in Table 8 17 If there are no measurements calculations or I O activities then the TDC only needs its quiescent supply cur rent Table 8 19 shows the typical current consumption for each relevant com
31. Measurement Range RN 55 8 7 MINIMUM PULSE WIDTH OF START AND TOp SIONALS 56 8 8 SETUP AND HOLD TIME EN_STOP_A B TO STOP_A B ccc ccccccccccssssssseeeeceeeeesensseeees 56 8 9 TIMING WHEN INITIATING AND STARTING A TIME MEASUREMENT cceeeeessseeeeeeeeeeeeeees 57 gl EIERE 57 8 10 1 Dead Time at the End of a Time Measurement in Measurement Range I 58 8 10 2 Dead Time at the End of a Time Measurement in Measurement Range H 59 8 10 3 Dead Time between Burst Mode Measurements cccessssccecccceeeeesssseeeeeceeeeseees 59 8 10 4 Dead Time of a Separate Calibration Measurement 60 8 10 5 Dead Time Increase due to Auto Noise and Retrigger Unit sssseessssrsssressrssesesee 60 3 111 ALU CALCULA TION KE 61 8 12 TIMING WHEN THE FIRST RAW VALUE OF A MEASUREMENT IS GENERATEID 61 8 13 CURRENT CONSUMPTION a2 2m air seinen 62 8 14 POWER ON CHARACTERISTICS nes ae Zain 64 8 13 _ MIBASUREMENT RESUETS ars sa au 65 8 15 1 Singleshot Measurements and RMS Resolution u022200sssssnssnnensnnneennnnnnnnen 65 8 15 2 Simultaneous Singleshot Measurements on both Channels uu s0er nern 66 8 15 3 Auto Noise Unit Effect on Measurement Error and Standard Deviation 67 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 5 of 68 1 Introduction MSC Vertriebs GmbH has many years of experience in the development of high precisio
32. Page 26 of 68 see Chapter 5 3 When averaging all the single measurements there quantisation errors are averaged as well TDC raw value CAL with auto noise CAL VAL with auto noise VAL OFFSET with auto noise OFFSET time difference to be measured offset enlargement by delaying the stop signal quantisation stage LSB width resolution pAr ea OR RRR Ra nO Sa ea E different offsets generated ech ia by auto noise unit ps Figure 6 4 Influence of the Auto Noise Unit on the Characteristics of the TDC Measuring Core If the auto noise unit is enabled a channel specific delay is generated by a pseudo random number generator This delay is added to the already existing offset of the respective channel and can be changed with every activation of the action bit clock auto noise within the Init Register The pseu do random number generator provides 32 different states each generating another delay The pseu do random number generator is cleared on power on reset only Remarks e Maximum auto noise delay I Ins 5V typ see Appendix 8 10 5 e The auto noise unit is available only in the measurement modes 0 to 5 measurement range I e For accuracy reasons averaging over 32 64 96 etc measurements is recommended TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 27 of 68 6 2 5 Measuring Core The measuring core determines the time
33. The time difference tres between hit x 1 lt x lt 4 on channel A resp channel B and common start is calculated using the divided calibration clock period tcar and the raw values VALx A CAL A and OFFSET A resp VALx B CAL B and OFFSET B in accordance with the TDC s quantisa tion characteristic shown in Figure 5 2 as follows Bs Gee VALx A OFFSET A CALA OFFSETA resp Gy ieee VALx B OFFSET B CAL B OFFSET B Kal The time difference tres between hit y 1 lt y lt 4 and hit x 1 lt x lt 4 on the same channel is cal culated using the divided calibration clock period cat and the raw values VALy A VALx A CAL A and OFFSET A for channel A VALy B VALx B CAL B and OFFSET B for channel B in accordance with the TDC s quantisation characteristic shown in Figure 5 2 as follows TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 18 of 68 VALy A VALx A CAL A OFFSET A 5 tres cat resp VALy B VALx B CAL B OFFSET B 6 tres tcaL The time difference tres between hit y 1 lt y lt 4 on channel B and hit x 1 lt x lt 4 on channel A is calculated using the divided calibration clock period tcar and the raw values VALy B VALx A CAL B OFFSET B and OFFSET A in accordance with the TDC s quantisation characteristic shown in Figure 5 2 as follows _ VALy B OFFSET B VALx A OFFSET A i CAL B OFFSET B CAL 7 tres The time
34. VALID is set to T when the first raw value of a time or calibration measurement is generated VALID remains 1 until it s cleared VALID is cleared only on power on and soft reset or by activating the action bits time measurement or separate calibration measurement MEAS_BUSYN After the first start on the start input the flag MEAS _BUSYN is set to 0 no matter if the retrigger unit is enabled or not Time measurement or calibration measurement automatic separate is in action since the measuring core and or the precounter is busy In the burst measurement modes 4 and 5 MEAS_BUSYN remains 0 between the burst mode measurements In the measurement modes with automatic calibration measurement modes 0 2 4 and 6 MEAS _BUSYN remains 0 between time and calibration measurement No time or calibration measurement is in action default ALU_BUSYN ALU is in action calibration multiplication ALU is idle default OV_CORE No measuring core overflow Default Measuring core overflow OV_CORE is cleared on power on and soft reset or by activating the action bits time measurement or separate calibration measure ment No precounter overflow Default Precounter overflow No matter if the expansion of measurement range II is enabled or not OV_PRE is set to 1 at the first overflow of the precounter OV_PRE is cleared on power on and soft reset or by activatin
35. ailed information on the individual register bits refer to Chapter 7 2 1 9 Multiplication Registers MULT_REG_1 MULT_REG_2 MULT_REG_3 6 5 1 6 Interrupt Enable Register In this register up to six IRQ flag set signals can be enabled for interrupt generation on pin INT FLAG For detailed information on the individual register bits refer to Chapter 7 2 1 4 Interrupt Enable Register INT_EN_REG TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 30 of 68 6 5 1 7 High Resolution Registers There is a High Resolution Register for each channel In order to achieve an minimized differential non linearity fine tuning for High and Smart Resolution is done in these registers For detailed information on the individual register bits refer to Chapter 7 2 1 6 High Resolution Registers HIGH_REG_A HIGH_REG_B 6 5 1 8 Smart Resolution Registers There is a Smart Resolution Register for each channel In order to achieve an minimized differential non linearity fine tuning for Smart Resolution is done in these registers A detailed description of the individual register bits is given in Chapter 7 2 1 7 Smart Resolution Registers SMART_REG_A SMART_REG B 6 5 1 9 GPIO Configuration Register The TDC provides four general purpose I O pins GPIOO GPIO1 GPIO2 and GPIO3 individually configurable as input or output via this register A pin configured as output drives a 0 or 1 ac cording to the level specifi
36. ard deviation Every time difference was measured 64 times within measurement mode 0 at the following conditions once with and another time without using the auto noise unit Measurement period 100 400ns Increment Ins Sampling rate 64 measurements per measuring point Calibration clock 4 MHz 2 2 MHz Division factor of the calibration clock divider 2 Automatic calibration measurement without offset generation Offset generation via separate calibration measurement before every single measurement Supply voltage 5V Resolution Half Resolution Reference measurements Universal Time Interval Counter SR620 Stanford Research System TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 68 of 68 Std Deviation Measurement Error Ch A half res 64 x per Meas Point Increment ins 5V MM 0 without AN o N o D o gt std TDC Measurement Error ld a u hu Gi 100 200 300 400 o Ze Standard Deviation ns and Measurement Error ns o EI Time ns Figure 8 7 Standard Deviation and Measurement Error without Auto Noise Unit Std Deviation Measurement Error Ch A half res 64 x per Meas Point Increment Ins 5V MM 0 with AN fan rn pe NET eon Standard Deviation ns and Measurement Error ns oO
37. b dh oi adi ab oi db vi SO NS cb NA OD 6 O WwW wo Si SY WH oi NY NY ox D d i d di Ni edhe oh K bi LP d i LY di SE D FP AR TT SH MH TEENS LSB No Figure 8 1 Resolution LSB Width and Differential Non Linearity Table 8 5 shows the differential non linearity for all kinds of resolution based upon measurements of several TDCs at Vpp 5V and 3 3V and using the configurations of Table 7 2 for High and Smart Resolution Registers Resolution m DNL max DNL 5V 3 3V 5V Table 8 5 Differential Non Linearity TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 53 of 68 8 4 Measurement Range I Minimum maximum Measurement Period 8 4 1 Minimum Measurement Period If the retrigger unit is disabled the minimum measurement period is tupmin Ops If the retrigger unit is enabled the minimum measurement period after the first start is typmin 0 8 ts The time t is the minimum pulse width of start and stop signals cp Appendix 8 7 After any retriggering start the minimum measurement period is Ops as usual 8 4 2 Maximum Measurement Period The maximum measurement period typimax depends on the resolution At Normal and Half Reso lution the maximum measurement period is approximately tapimax 2 bo AD The time ty in formula A1 is a specific internal parameter of the measurement range I In Table 8 6 tu is given for different conditions Conditions vo
38. ck signals will reach the measuring core and no measurement will take place As an exception calibration measurements take place no matter if the measurement channels are enabled or not TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 24 of 68 e Enable Stop A Enable Stop_B Using the pins EN_STOP_A and EN_STOP_B the stop inputs STOP_A and STOP_B of the measurement channels can be disabled No stop signals will be passed to the measuring core If the stop inputs are enabled by EN_STOP_A or EN_STOP_B they can also be enabled disabled by software Please notice that in measurement range II the stop input of the selected channel has to be enabled during the whole time measurement e Polarity Start Polarity Stop_A Polarity Stop_B The edge sensitivities of the TDC s start and stop inputs START STOP_A and STOP_B are adjusted independently from each other by software The input unit therefore triggers on rising or falling edges of the start and stop signals depending on the configuration Furthermore the input unit decides which signal start stop or calibration clock has to be passed on as a start or stop signal to the measuring core depending on the measurement mode and on the partial step of the measurement cycle 6 2 2 Precounter In measurement range II the precounter counts the clock periods tca of the divided calibration clock CLK between the start signal and up to four hits The precounter is
39. difference between the start signal and the hits with a pro grammable resolution of 45ps Smart Resolution 90ps High Resolution 180ps Normal Resolu tion or 360ps Half Resolution 25 C 5V The measuring core stores the measurement and cali bration values in the raw value registers for further processing If the time difference the core has to measure exceeds the maximum measurement period cp Chapter 8 4 2 a measuring core overflow OV_CORE will occur and if enabled the signal I_OV_CORE sets the TDC s interrupt request flag INTFAG cp Chapter 6 8 3 1 Thus the ongo ing measurement cycle is aborted including any automatic calibration measurement and ALU calculations To achieve a high precision accuracy electrical coupling effects can be minimized applying the TDC s separated power supply pins for the measuring core 6 3 Hitcounter Two hitcounters are provided one for each channel Depending on the measurement mode and the channel selector bit within the Control Register CTRL_REG_1 the hitcounters register the hits detected on the respective channel If the number of hits resp burst mode measurements defined in the Hit Register cp Chapter 6 5 1 3 is reached the time measurement is completed and an automatic calibration measurement or ALU calibration may follow The Hit Status Register HIT_STATUS_REG cp Chapter 6 5 2 1 readable via the processor inter face reflects the current state of the hitcounters
40. dy for readout will be the calibration value CAL resp both calibration values CAL A and CAL B In Table 8 18 the following maximum time periods for raw value detection are given for different conditions e ty mpr Time period between the first hit of a time measurement resp the stop of the first burst mode measurement in measurement range I and the rising edge of the interrupt request flag INTFLAG ty mgn Time period between the start of a time measurement in measurement range II and the rising edge of the interrupt request flag INTFLAG ty sc m Time period between the rising edge of WRN when activating the action bit separate calibration measurement within the Init Register and the rising edge of the interrupt re quest flag INTFLAG The calibration measurement s offset generation is enabled e ty sco Time period between the rising edge of WRN when activating the action bit separate calibration measurement within the Init Register and the rising edge of the interrupt re quest flag INTFLAG The calibration measurement s offset generation is disabled TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 62 of 68 Conditions voltage temperature process 5 5V 40 C best tv vpn 1 5 tea 60ns 1 5 tcaL 55ns 2 5 tcaL 55ns 5 0V 25 C typ 1 5 tcaL 95ns 1 5 tcaL 90ns 2 5 tcaL 90ns 4 5V 85 C worst 1 5 tcar 185ns 1 5 tca
41. e Edge sensitivity STOP DR 0 rising edge 1 falling edge Expansion measurement range II 0 Overflow precounter gt measurement cycle abort Pin EX_MBII high impedance 1 Overflow precounter gt no measurement cycle abort Pin EX_MBII 0 1 0 1 etc Enable STOP A 0 Stop input STOP_A disabled cannot be enabled via pin EN_STOP_A 1 Stop input STOP_A enabled if pin EN_STOP_A 1 Enable STOP_B 0 Stop input STOP_B disabled cannot be enabled via pin EN_STOP_B 1 Stop input STOP_B enabled if pin EN_STOP_B 1 Auto Noise 0 Auto Noise off 1 Auto Noise on Retrigger S 0 Retrigger off 1 Retrigger on In measurement range II the stop input of the selected channel has to be enabled during the whole time measurement Bits relevant only for measurement modes 0 up to 5 Have to be set to 0 for modes 6 and 7 Figure 7 3 CTRL_REG_2 Format TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 41 of 68 5 a GE 0 Bit 7 6 oO To 00 o 0 Detut reserved reserved Calibration clock division 000 1 1 100 1 16 001 1 2 101 1 32 010 1 4 110 1 64 Disable Offset 0ll 1 8 111 1 128 1 Generation of OFFSET is dis ALU calculation abled during 00 without ALU calibration measurement 01 ALU with calibration only 0 CAL and OFFSET 10 reserved are generated 11 ALU with calibration and multiplication Figure 7 4 CTRL_REG_3 Format
42. e 7 12 HIT_STATUS_REG Format 7 2 2 2 GPIO Input Register GPIO_IN_REG The format of the GPIO Input Register is shown in Figure 7 13 7 4 Bit 3 2 1 0 Default reserved Level of pin GPIOO Level of pin GPIO3 Level of pin GPIO1 Level of pin GPIO2 Figure 7 13 GPIO_IN_REG Format TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 47 of 68 7 2 2 3 Status Register STATUS_REG Figure 7 14 shows the flags of the Status Register TDC_READY is the only flag accessible via pin too A detailed description of the status flags is given in Chapter 6 8 3 1 5 4 3 2 1 0 Bit po Foti tt o o Default 7 reserved OV_CORE 0 Measuring core ok 1 Overflow measuring core OV_PRE 0 Precounter ok 1 Overflow precounter MEAS BUSYN 0 Measurement in progress measurement core and or precounter 1 No measurement in progress ALU_BUSYN 0 ALU is calculating calibration multiplication 1 ALU is not in action VALID 0 All raw value registers are empty 1 Raw value registers contain at least one number TDC_READY 0 TDC not ready measurement channels are disabled 1 TDC is ready for measurements Figure 7 14 STATUS_REG Format TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 48 of 68 7 3 Raw Value Registers The TDC provides 12 read only raw value registers ROH_REG_0 to ROH_REG_11 7 3 1 Raw Value Register Format As shown in Figure
43. e calibration measurement for example e Ifthe expansion is enabled ALU calculations are only valid before 1 overflow TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 25 of 68 6 2 3 Retrigger Unit If the retrigger unit is enabled the measurement is re started at the appearance of every start at the TDC s start input START as long as no stop resp hit has been detected As shown in Figure 6 3 the determined time difference trgs is the time between the last start and the stop hit If the retrigger unit isn t enabled then the time difference between the first start and the stop hit is measured The retrigger unit can be enabled by software for the measurement modes 0 to 5 measurement range I START EE SG EG tres With Retrigger Unit tags Without Retrigger Unit gt Figure 6 3 Measurement with and without Retrigger Unit Remarks e The maximum measurement period in measurement range I is Jus resp 5 us High Resolution 2 5us Smart Resolution 25 C 5V see Appendix 8 4 2 no matter if the retrigger unit is enabled or not So if the time differ ence between a retriggering start and the start before exceeds the maximum measurement period a measuring core overflow OV_CORE will occur and if enabled the signal I_OV_CORE sets the TDC s interrupt request flag INTFLAG cp Chapter 6 8 3 Thus the ongoing measurement cycle is aborted including any automatic calibration
44. ed also in this register A detailed description of the individual register bits is given in Chapter 7 2 1 5 GPIO Configuration Register GPIO_REG 6 5 2 Read only Registers 6 5 2 1 Hit Status Register The Hit Status Register reflects the current number of hits or burst mode measurements detected for each channel A detailed description of the individual register bits is given in Chapter 7 2 2 1 Hit Status Register HIT_STATUS_REG 6 5 2 2 GPIO Input Register The levels of all four general purpose I O pins GPIOO GPIO1 GPIO2 and GPIO3 can be read via the GPIO Input Register A detailed description of the individual register bits is given in Chapter 7 2 2 2 GPIO Input Register GPIO_IN_REG 6 5 2 3 Status Register The Status Register reflects the current state of the TDC The Status Register contains six status flags which are described in detail in Chapter 6 8 3 1 Status Flags and Chapter 7 2 2 3 Status Register STATUS_REG TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 31 of 68 6 6 Raw Value Registers The TDC provides 12 read only raw value registers in which the measurement values VAL of each hit resp each burst mode measurement the calibration values OFFSET and CAL and the pre counter values PRE of each hit in the measurement range II are stored for further processing The width of all raw value registers is 16 bit The registers can be read out via the processor interface For addr
45. els A and B with a common start input and two independent stop inputs The resolution of both channels is identical Via the processor inter face a resolution of 45ps Smart Resolution 90ps High Resolution 180ps Normal Resolu tion or 360ps Half Resolution is selectable SV typ 5 1 Time Difference Measurement As shown in Figure 5 1 one edge sensitive start input and two edge sensitive stop inputs are avail able for measuring the time differences trgsi The stop inputs represent the measurement channels A and B A start on the start input starts the time measurement in the measuring core Depending on the selected measurement mode every stop on the stop inputs is detected as a so called hit and the time hit start is measured and stored as measurement value VAL in one of the raw value regis ters The time measurement ends when the last hit up to 10 hits are configurable is detected With the measurement values of the raw value registers all possible time differences trgsi hit to start hit to another hit can be calculated either externally or using the internal ALU The ALU s measurement results positive and negative time differences are possible are stored in the result registers TDC502 raw value START registers measuring core V AL RES result registers CALCLK start 1 hit 1 hit 2 hit channel A channel B channel A Figure 5 1 Time Difference Measurement Example The measurement
46. ent period is approx tupnmin 180ns 8 5 2 Maximum Measurement Period The maximum measurement period is approximately t SE A3 MBIImax CAL In measurement range II the measuring core has to measure 1 5 calibration clock periods at the most Therefore the following condition has to be satisfied too TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 55 of 68 tear lt 2 3 tupimax A4 The time twpimax in formula A4 is the minimum measurement period of measurement range I cp formula Al Chapter 8 4 2 Example As calculated in Chapter 8 4 2 for Normal and High Resolution at 5V the maximum measurement period of measurement range I is approx tMBImax 10us typically According to formula A4 the divided calibration clock has to be 150kHz at least Using formula A3 this results in a maximum measurement period of approx tMBIImax 210ms 8 6 Double Pulse Resolution The double pulse resolution of a TDC with multi hit capability is defined as the minimum possible time difference between two hits on the same stop input so that the second hit is definitely detected 8 6 1 Measurement Range I Table 8 8 shows the double pulse resolution tppr for different conditions in measurement range I Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 8 D
47. eristics UaDRALE tALEADR TALE tALERD tRDALE VDD 5V 10 T 40 to 85 C Load 30pF 3 0V lt VDD lt 4 5 V All times listed above have to be multiplied by 1 5 2 7V lt VDD lt 3 0V All times listed above have to be multiplied by 2 Table 6 2 Read Cycle Timing Characteristics TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 36 of 68 6 8 3 Status and Interrupt Request Flags 6 8 3 1 Status Flags Six status flags are provided reflecting the current state of the TDC The status flags are accessible via the Status Register see Chapter 7 2 2 3 In Table 6 3 all status flags are described in detail Status Flag Description TDC_READY 0 TDC not ready measurement channels are disabled default Set by activation of action bit time measurement TDC is ready for meas urement and waits for a start signal on the start input START After start has taken place TDC_READY is cleared until the next activation of action bit time measurement If the retrigger unit is enabled the TDC remains ready as long as no stop resp hit is detected In the burst measurement modes 4 and 5 the TDC will be also ready between the burst mode measurements until the number of burst mode measurements specified in the Hit Register cp Chapter 6 5 1 3 is reached Raw value register empty No valid data for readout default At least one raw value register contains valid data for readout
48. ers the status signal ALU_BUSYN is cleared reset to 1 and if enabled the signal I ALU_END sets the TDC s interrupt request flag INTFAG cp Chapter 6 8 3 1 The ALU is provided with its own clock generator and is independent from TDC external clocks A calibration takes approx 1 2us 25 C 5V and the following multiplication approx 2us 25 C 5V Please see Appendix 8 11 for exact ALU calculation times calibration multiplication 6 5 TDC Registers The width of all TDC registers is 8 bit They are accessible via the processor interface see Chapter 6 8 For addressing the registers refer to Chapter 7 1 6 5 1 Read Write Registers All read write registers are written with the rising edge of the signal WRN Please notice that it s only allowed to write the Control Hit Highresolution Smartresolution ALU and Multiplication Registers when no action bit is set within the Init Register cp Chapter 5 3 1 6 5 1 1 Init Register The Init Register provides direct commands which are executed by setting the register s bits to 1 activation of the action bits In doing so a time measurement a separate calibration measure ment or a ALU calculation is started or a soft reset is executed For detailed information on the in dividual register bits refer to Chapter 7 2 1 1 Init Register INIT_REG TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 29 of 68 6 5 1 2 Control Reg
49. essing the raw value registers see Chapter 7 1 and Chapter 7 3 6 7 Result Registers The TDC provides two read only result registers in which the measurement results RES of the ALU calculations are stored alternately within a measurement cycle beginning with result register 0 The width of the result registers is 32 bit The registers can be read out via the processor interface For addressing the result registers see Chapter 7 1 6 8 Processor Interface Figure 6 5 shows the block diagram of the processor interface 2 result registers GPIO 3 0 12 raw value registers BEE ADR 3 0 interface ALE DATA 7 0 TDC registers RDN WRN CSN CTRL_REG_1 2 3 I_VALID PHIGH_REG_A7B MUL_REG_I 2 3 SEN INTELAG I_OV_PRE TDC_READY INIT_REG GPIO_IN_REG Figure 6 5 Block Diagram Processor Interface Via the processor interface the access to all TDC registers is performed as well as the access to the raw value and result registers In addition to data and control lines the processor interface provides a status flag an interrupt re quest flag and four general purpose I O pins individually configurable as input or output TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 32 of 68 6 8 1 General Purpose I O Pins The TDC provides four general purpose I O pins individually configurable as input or output via the GPIO Configuration Register GPIO_REG A pin configured as output drives a 0 or 1
50. for a new measurement is always stored in result register 0 Please notice that configuring the Control Hit ALU Multiplication Smart and High Resolu tion Registers is only allowed when no action bit is set within the Init Register TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 16 of 68 5 3 2 Measurement Modes 0 and 1 Mode e 0 and 1 measurements are executed within measurement range I using the measuring core As shown in Figure 5 5 one channel with up to 10 hits and a double pulse resolution of 25ns 5V 25 C is available Via software channel A or channel B is selectable When the time measurement is completed in measurement mode 0 an automatic calibration measurement on the selected channel follows according to Chapter 5 2 time measurement gt 25 ns START sTOP_Aresp sTOP B TLTII a start hit 1 hit 2 hit 10 VALI VAL2 VAL10 Figure 5 5 Measurement Modes 0 and 1 The time difference trgs between hit x 1 lt x lt 10 and start is calculated using the divided calibra tion clock period tcar the calibration values CAL and OFFSET and the measurement value VALx in accordance with the TDC s quantisation characteristic shown in Figure 5 2 as follows G tags NVALX OFESET ST CAL OFFSET At The time difference trgs between hit y 1 lt y lt 10 and hit x 1 lt x lt 10 is calculated using the di vided calibration clock period tea and the raw values VALy
51. g the action bits time measurement or separate calibration measurement Table 6 3 Status Flags TDC_READY is the only status flag also accessible via pin For timing characteristics of pin TDC_READY refere to Appendix 8 9 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 37 of 68 6 8 3 2 Interrupt Request Flag For interrupt generation at the connected processor the TDC provides an interrupt request flag on pin INTFLAG Via software up to six IRQ flag set signals can be enabled at the same time I VALID Set to 1 when the first raw value register is filled with valid data I_MEAS_END _ Set to 1 when separate calibration measurement or time measurement with without automatic calibration measurement is finished All relevant raw value registers are filled with valid data if the measurement was correct I ALU_END Set to 1 when ALU calculations are completed and the relevant result register is filled with valid data I OV_CORE Set to 1 when a measuring core overflow occurs I_OV_PRE Set to 1 when the first precounter overflow occurs INTFLAG and all IRQ flag set signals are cleared on power on reset on pin RSTN or by activating one of the following action bits within the Init Register reset INTFLAG ALU calculation soft reset separate calibration measurement time measurement 6 8 3 3 Correlation of Status
52. h byte Low byte Integer portion Fractional portion Figure 7 16 Result Register Format 7 4 2 Result Data Formats The measurement results are 32 bit fixed point numbers with a 16 bit integer portion and a 16 bit fractional portion In measurement range I the four most significant bits of the integer portion are either 0 gt result is positive or 1 gt result is negative In addition negative results are repre sented via the ones complement only of the integer portion In measurement range II the measure ment results are positive at all times Examples e Pos result in measurement range I Ox OAIE4F71 2590 20337 65536 2590 310318 e Neg result in measurement range I Ox FEC2 F432 317 62514 65536 317 953888 e Result in measurement range II 0x CO2B 2723 49195 10019 65536 49195 152878 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 50 of 68 8 Appendix 8 1 Electrical Specification Von Supply Voltage SS SS Vu cmos Input Low Voltage 1 JOND 03l _ 03V V__ Vm cmos Input High Voltage 2 0 7 Von _ Vom 03 V iy Input Current Vin VonorGND_ 10 o nA Nos ou Output High Voltage Ton 4mA Vm 08 IN o ous Output Low Voltage Uz 4mA_ Toz 3 State Output Leakage Current Von Von o GND 10 io n NOTE Junction temperature range 55 C to 125 C Table 8 1 DC Characteristics Vpp 5V Voo Supply Voltage 8S
53. h measurement mode 2 and Smart Resolution selected at 5V The measurement period is from 100 to 300ns The systematic offset error of approx 575ps is irrelevant here too Smart_543 Resolution Singleshot from 100 to 300ns Increment 1ns Cal Clock 2MHz 5V Chan A B MM 2 dh ol io Measurement Error ns a o t e o o og sg DH o o vw o o oi o e e r NN o 9 YT 2 02 oO oe E GBH DD NN o D o DW o o o D o o D NN Oo Oo Time ns Figure 8 6 Measurement Errors of simultaneous Singleshot Measurements at 5V Mode 2 8 15 3 Auto Noise Unit Effect on Measurement Error and Standard Deviation If there is the possibility to measure the same time difference several times a higher precision can be achieved by calculating the average measurement result With an increasing number of meas urements and taking into account all systematic errors such as the TDC s quantisation error see Chapter 6 2 4 or offsets caused by different length of cables for start and stop the average measurement result will converge the real time difference which has to be measured So the meas urement error of the average measurement result is getting smaller and smaller In doing so the standard deviation is a good measure of the variation of the individual measurement results around the average Comparing Figure 8 7 with Figure 8 8 shows which effects the auto noise unit has on the measurement error and the stand
54. hers reserved 7 HIGH_NIBBLE 4 3 LOW_NIBBLE 0 Bit Modes 4 5 0001 0000 Default Event high nibble Event low nibble 0001 Measurement 1 0110 Measurement 6 0000 Start 0010 Measurement 2 0111 Measurement 7 others reserved 0011 Measurement 3 1000 Measurement 8 0100 Measurement 4 1001 Measurement 9 0101 Measurement 5 1010 Measurement 10 others reserved 7 HIGH_NIBBLE 4 3 LOW_NIBBLE 0 Bit Modes 6 7 0001 0000 Default Event high nibble Event low nibble 0001 Hit 1 0000 Start 0010 Hit 2 0001 Hit 1 0011 Hit 3 0010 Hit 2 0100 Hit 4 0011 Hit 3 others reserved others reserved Figure 7 10 ALU_REG Formats TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 45 of 68 I the following some examples for configuration the ALU register are shown e Measurement mode 0 Calculation of the time difference between the 3 hit and start on the channel selected via CTRL_REG_1 0011 0000 e Measurement mode 1 Calculation of the time difference between the 6 hit and the 2 hit on the channel selected via CTRL_REG_1 01100010 e Measurement mode 2 Calculation of the time difference between the 1 hit on channel B and the 3 hit on channel A 1001 0011 e Measurement mode 2 Calculation of the time difference between the AN hit on channel A and Common Start 0100 0000 e Measurement mode 3 Calculation of the time difference between the 2 hit on channel B and Common Start 1010
55. isters There are three Control Registers all in all Here the measurement mode the division factor for the calibration clock divider as well as the edges of the start and stop signals on which the TDC will trigger are selected A detailed description of the individual register bits is given in Chapter 7 2 1 2 Control Registers CRTL_REG_1 CRTL_REG_2 CTRL_REG_3 6 5 1 3 Hit Register In the Hit Register the number of hits for both channels is defined a measurement cycle consists of In the burst mode the number of burst mode measurements start stop is defined For detailed information on the individual register bits refer to Chapter 7 2 1 3 Hit Register HIT_REG 6 5 1 4 ALU Register In this register the ALU calculation rules are defined according to the formulas 1 to 11 see Chap ter 5 3 ALU calculation rule format Calculate the time difference between the event of the register s HIGH_NIBBLE hit burst mode measurement and the event of the register s LOW_NIBBLE hit start common start In short HIGH_NIBBLE LOW_NIBBLE For detailed information on the individual register bits refer to Chapter 7 2 1 8 ALU Register ALU_REG 6 5 1 5 Multiplication Registers In these three registers a 24 bit unsigned integer number value range O to 2 is specified If the multiplication is enabled via software the ALU uses this value for multiplication according to the formulas 1 to 11 see Chapter 5 3 For det
56. ltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 6 Time ty in Measurement Range I At High Resolution typimax has to be shortened by half and at Smart Resolution typimax has to be shortened to the fourth part Using the typical value of Table 8 6 at 5V the maximum measurement period for Normal and Half Resolution is approx tmBimax 10us for High Resolution approx Sus and for Smart Reso lution approx 2 5us TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 54 of 68 8 5 Measurement Range II Minimum maximum Measurement Period The minimum and maximum measurement periods depend on the divided calibration clock period tca cp Chapter 5 2 Generating Calibration Values 8 5 1 Minimum Measurement Period The minimum measurement period is approximately tupnmin 1 5 tear tp A2 The time tp in formula A2 is a specific internal parameter of the measurement range II In Table 8 7 tp is given for different conditions Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 7 Time tp in Measurement Range II Using the typical value of Table 8 7 at 5V an external calibration clock of 20MHz and the division factor 1 1 the minimum measurem
57. measurement and ALU calculations and the retriggering start will not restart the measurement e After the first start the minimum measurement period is 0 8 t The time t is the minimum pulse width of start and stop signals cp Appendix 8 7 After any retriggering start the minimum measurement period is Ops as usual 6 2 4 Auto Noise Unit The characteristic of the TDC is a straight line with offset and upward gradient which due to the digital measurement procedure possesses quantisation stages so called LSBs Least Significant Bits with the width of the resolution For a single measurement one therefore gets a quantisation error of up to one quantisation stage at ideal quantisation This precision is sufficient for most ap plications A higher precision can be achieved when the measurement of the same time is repeated several times and statistical methods are used Changing the existing offset of the characteristic for each single measurement by delaying the stop signal according to Figure 6 4 causes sampling at different positions of the characteristic especially when measuring very constant time differences of a low noise signal If the same offset shift is still present during the generation of the calibration values for the associated measurement value the total offset is eliminated during the time difference calculation according to the formulas 1 to 11 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502
58. measurement in About 2 calibration clock periods tcar 1 6 tp tp range II see Table 8 7 Automatic calibration 1 calibration clock period tcar 0 8 tac tac measurement see Table 8 13 Separate calibration 1 calibration clock period tcar 0 8 tsc tsc measurement see Table 8 15 Note If the auto noise unit is enabled the time Lu shown in Table 8 16 has to be added to the runtime of the meas uring core Table 8 20 Runtime of the Measuring Core Example 2500 start stop measurements sec in measurement mode 6 each with a measurement period of 0 1ms on the average followed by ALU calculations for calibration and multiplication operating at Vpp 3 3V The external calibration clock CALCLK is 4 MHz which is divided by the calibration clock divider down to a 2MHz internal clock CLK After each measurement the result registers are read out 4 read cycles and the next measurement is initiated by activating the action bit time measurement 1 write cycle gt Calculation of the current consumption Quiescent current 150nA 3 3V 5V 99nA Meas core 32mA 3 3V 5V 2 500ns 1 6 135ns S00ns 0 8 110ns 2500 s 62 8661 A ALU 8mA 3 3V 5V 1440ns 2465ns 2500 s 34 02uA Precounter 100u A MHz 3 3V S5V 2MHz 0 1ms 2500 s 21 78uA Calibration clock input 45u A MHz 3 3V 5V 4MHz 78 408u A Read and write cycles 1 7 A 1000 3 3V 5V 2500 44 1 9 257 A Over all current consumption
59. mum measurement period is shortened to the fourth part Measurement range depends on period of calibration clock TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 7 of 68 3 Block Diagram Figure 3 1 shows the block diagram of the TDC502 EN_STOP_A EN_STOP_B EX_MBII or e START interface STOP_A channel A GPIO 3 0 result ess channel B register 0 CALCLK a result et register 1 TDC_READY 12 raw value registers TDC registers RSTN Figure 3 1 TDC502 Block Diagram The TDC offers two channels A and B for time measurement between one start at the start input START and up to 10 hits at the stop inputs STOP_A and STOP_B The uncalibrated measurement values are stored in the raw value registers and can either be read out via the processor interface or processed within the ALU Calculation of every hit to start and every hit to each other hit cali bration and multiplication using a 24 bit unsigned integer number The ALU s measurement results are stored in the result registers and can be read out via the processor interface The configuration of the TDC as well as the selection of the measurement mode and range is done by writing the TDC registers via the processor interface Status information can be accessed by reading the TDC registers The calibration clock necessary for the calibration of the uncalibrated measurement values has to be supplied by an externally genera
60. n Time to Digital Converters TDCs Our first TDC was developed in 1990 and implemented in a cost effec tive Gate Array technology This manual describes the TDC502 the latest member of our TDC family The TDC502 is imple mented in a 0 6um CMOS process OT featuring 2 7V 5 5V operation and is delivered in a LQFP44 0 8 mm fine pitch package Supplied with 5V the TDC502 achieves a typical resolution of up to 45ps This resolution cannot be achieved using conventional time measuring components In combination with its multi hit capa bility the multi channel function of the TDC502 allows simultaneous and or successive measure ment of time differences The Burst Measurement Mode and the integrated ALU complete the TDC502 s performance The integrated measurement principle together with the technology used allows high precision time difference measurement at low power consumption The integration of the TDC502 in battery powered applications is acommon procedure The TDC502 is perfectly suited for measurement of time differences Applications like distance measurement using laser phase measurement ultrasonic positioning temperature measurement etc have been implemented successfully with our TDCs many times Go ahead and discover the world of our TDCs LQFP Low Profile Quad Flat Package TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 6 of 68 2 Features Channels Resolution 5V ty
61. n clock for all hits in common The output is stored as measurement value VALO in a raw value register In the second stage of the measurement the precounter counts the clock periods tca of the divided calibration clock CLK between the start signal and each hit The results are stored as precounter values PREx 1 lt x lt 4 in the raw value registers In the thirdstaget of the measurement the time between each hit and the following rising edge of the divided calibration clock is measured using the measuring core once again The results are stored as measurement values VALx 1 lt x lt 4 in the raw value registers TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 21 of 68 The time difference tres between hit x 1 lt x lt 4 and start is calculated using the divided calibra tion clock period tcar and the raw values VALO VALx PREx CAL and OFFSET in accordance with the TDC s quantisation characteristic shown in Figure 5 2 as follows VALO VALx CAL OFFSET 10 res k prex 3 tcaL The time difference tars between hit y and hit x 1 lt x lt 3 2 lt y lt 4 x lt y is calculated using the divided calibration clock period tcar and the raw values VALx PREx VALy PREy CAL and OFFSET in accordance with the TDC s quantisation characteristic shown in Figure 5 2 as follows VALx VALy CAL OFFSET 11 tres l PREy SH tcaL If the ALU is used for calculation the time diffe
62. ng core is disabled because of post processing Trying to re initiate the TDC for another time measurement by re setting the Init Register s bit O to 1 before the end of dead time is not legal and will be ignored Due to the fact that the TDC s measuring core is not available for time measurements during auto matic or separate calibration measurements this time periods are also considered as dead times ALU calculation times see Table 8 17 are considered as dead times as well TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 58 of 68 8 10 1 Dead Time at the End of a Time Measurement in Measurement Range I The dead time at the end of a time measurement in measurement range I is defined as the time pe riod between the last hit of a time measurement resp the stop of the last burst mode measurement and the rising edge of the status flag MEAS_BUSYN resp the rising edge of the interrupt request flag INTFLAG set by I MEAS_END if enabled For the measurement modes 1 3 and 5 modes without automatic calibration measurement the maximum dead time tror mB o at the end of a time measurement is specified in Table 8 12 Conditions TOT MBLO voltage temperature process ns 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Values for pin INTFLAG Load 30pF Table 8 12 Maximum Dead Time tror ve o Wi
63. ode in Table 8 17 the maximum times tary car and tatu mut the ALU needs for a calibration and the following optional multiplication are specified Conditions tatu caL ns tatu muL ns voltage temperature Measurement Modes Measurement Modes process 0 1 4 5 2 3 6 7 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 17 ALU Calculation Times for Calibration tary car and Multiplication tatu MUL 8 12 Timing when the first Raw Value of a Measurement is generated Using the status flag VALID or the IRQ flag set signal I_VALID for pin INTFLAG allows to de tect the moment when the first raw value of a time or calibration measurement is generated and written to the raw value registers for readout Depending on the TDC s operation mode this moment can be a long time before the end of the measurement When executing a time measurement in measurement range I the first hit resp the stop of the first burst mode measurement generates the first raw value VALI resp VALI A or VALI B When executing a time measurement in measurement range II the first raw value to be generated is VALO Executing a separate calibration measurement with offset generation generates the raw value OFFSET resp both raw values OFFSET A and OFFSET B at first When executing a seperate calibration measurement without offset generation the first raw value to be rea
64. ode measurements start stop is avail able Via software channel A or channel B is selectable For each burst mode measurement the whole measurement range Ops 10us is usable The dead time between burst mode measure ments is 100ns 5V 25 C see Appendix 8 10 3 When the last burst mode measurement is com pleted in measurement mode 4 an automatic calibration measurement on the selected channel fol lows according to Chapter 5 2 burst mode measurements gt 100n START eeng D el ee e ER EBEN STOP_A resp STOP_B il n E ee VALI10 measurement 1 measurement 2 measurement 10 ENA VAL2 Figure 5 7 Burst Modes 4 and 5 The time difference tres of burst mode measurement x 1 lt x lt 10 is calculated using the divided calibration clock period tcar the calibration values CAL and OFFSET and the measurement value VALx in accordance with the TDC s quantisation characteristic shown in Figure 5 2 as follows VALx OFFSET i CAL OFFSET 9 tres If the ALU is used for calculation the time difference tres the fraction of formula 9 is computed during calibration If the ALU is used not only for calibration but also for multiplication tcar has to be set up within the multiplication registers to numbers between 0 and 2 If the multiplication is disabled via software tca remains 1 and no multiplication is executed When using the TDC s ALU the measurement result tres may become negative
65. of the divided calibration clock CLK is limited as follows 4 5V lt VDD lt 5 5 V 20 MHz 3 0V lt VDD lt 4 5 V 10 MHz 2 7V lt VDD lt 3 0 V 6 MHz In order to achieve high precision accuracy when measuring in measurement range I the division factor should be selected in such a way that the largest time difference to be measured is in the range of half the calibration clock period length To achiev best measurement results in measure ment range II the period of the divided calibration clock should be as long as possible High Resolution 5us Smart Resolution 2 5us xE High Resolution 3 3us Smart Resolution 1 6us TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 23 of 68 6 2 Measurement Channels Figure 6 2 shows the block diagram of the measurement channels Enable TDC Polarity Start Enable Stop A Polarity Stop A Enable Stop_B Polarity Stop_B Retrigger retrigger Auto Noise Enable measuring core auto noise unit precounter gt OV_PRE EX_MBII PRE VAL OFFSET CAL OV_CORE Figure 6 2 Measurement Channels Block Diagram 6 2 1 Input Unit The input unit handles the incoming start stop and calibration clock signals using the following control signals e Enable TDC The measurement channels are enabled by activating the action bit time measurement within the Init Register If the channels are disabled no start stop and calibration clo
66. ouble Pulse Resolution tppr in Measurement Range I 8 6 2 Measurement Range II In measurement range II the double pulse resolution tppr depends on the divided calibration clock period tear and is identical with the minimum measurement period typimin see Chapter 8 5 1 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 56 of 68 8 7 Minimum Pulse Width of Start and Stop Signals Table 8 9 shows the minimum pulse width t of signals on the start and stop inputs START STOP_A and STOP_B as well as on the inputs EN_STOP_A and EN_STOP_B for different con ditions The time t is relevant for both high and low level of the signals Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 9 Minimum Pulse Width t of Start and Stop Signals 8 8 Setup and Hold Time EN_STOP_A B to STOP_A B Figure 8 2 shows the timing diagram of setup and hold times tens and tenn for EN_STOP_A resp EN_STOP_B to STOP_A resp STOP_B In Table 8 10 the associated timing characteristics are specified for different conditions EN_STOP_A B STOP_A B polarity falling edge STOP_A B polarity rising edge Figure 8 2 Setup and Hold Time EN_STOP_A B to STOP_A B Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V
67. p Measurement ranges SV typ Measurement modes Calibration clock Calibration measurement ALU Voltage range Temperature range Processor interface Internal memory Configuration Measurement improvement Package 2 channels with identical resolution consisting of a common Start and two Stop inputs programmable edge sensitivity of the inputs retriggerable Start input separated power supply for the Measuring Core Half Resolution 360 ps Normal Resolution 180 ps High Resolution 90 ps Smart Resolution 45 ps range I short time measurement Ops 10us range II long time measurement 180ns 210ms 1 8 measurement modes with up to 10 fold multi hit capability and up to 10 measurements within a burst external calibration clock required 500 KHz 20 MHz internal programmable clock divider automatically after time measurement or stand alone calculation of every hit to start and every hit to each other hit cali bration and multiplication using a 24 bit unsigned integer number 2 7V 5 5V 40 C 85 C 8 bit data bus 4 bit address bus programmable interrupt pin 4 individually programmable I O pins up to 10 uncalibrated measurement values up to 2 calibrated multiplied measurement values programmable via processor interface Auto Noise Unit LQFP44 with 0 8 mm pitch High Resolution Maximum measurement period is shortened by half Smart Resolution Maxi
68. ponent of the TDC at Voo 5V Ta 25 C Component Duration of Current Consumption Quiescent current all the time 150nA Measuring core during measuring core runtime 32mA ALU during calculations 8mA Precounter between start and last hit resp stop of a 100 A MHz measurement within measurement range II during calibration clock runtime during read and write cycles Current Consumption Calibration clock input Read and write cycles 45uA MHz 1 7u A 1000 cycles Measurement conditions Inputs WRN RDN and CSN Mon all other inputs and bidis GND all outputs open Please refere also to Table 8 1 and Table 8 2 The quiescent current increases exponentially to the temperature Table 8 19 Typical Current Consumption of TDC502 components at Vpp 5V Ta 25 C TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 63 of 68 When operating with supply voltages other than 5V the following voltage dependence have to be taken into account The quiescent current drops increases linearly to the supply voltage The current consumption of all other components drops increases squarely to the supply volt age Kind of measurement Measuring core runtime Comment Time measurement in Time between start and last hit resp stop 0 8 tror_MBLO range I troT_MBLO see Table 8 12 Burst mode Time between start and stop 0 8 tror B tror B measurement see Table 8 14 Time
69. r a timing measurement or has to be started separately from time to time depending on the measurement mode Unlike the measurement and calibration values VAL and CAL the offset is very constant within a wide range of temperature and supply voltage So it s not necessary to generate OFFSET all the times a calibration measurement is performed Via software it s possible to disable the offset generation during calibration measurement resulting in a higher precision accuracy when adapted to the measurement application properly TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 13 of 68 5 3 Measurement Ranges and Measurement Modes The TDC502 offers two measurement ranges e Range I use of TDC core for short time measurement Ops 10us 2 e Range II use of TDC core and precounter for long time measurement 180ns 210ms The TDC502 provides eight measurement modes programmable via the processor interface In Table 5 1 all measurement modes are listed Measurement Auto Short description mode calibration Measurement range I 1 channel A or B programmable with 10 fold multi hit capability Double pulse resolution 25ns 5V 25 C ALU Calculation of every hit to start and every hit to each other hit negative results possible Measurement range I 2 channels with common start and 4 fold multi hit capability each Double pulse resolution Ops different channels resp 25ns same channel 5V 25 C
70. rence tres the bracket term of formulas 10 and 11 is computed during calibration If the ALU is used not only for calibration but also for multiplica tion tcar has to be set up within the multiplication registers to numbers between 0 and 2 If the multiplication is disabled via software tca remains and no multiplication is executed In measurement range II the TDC s ALU computes positive results only TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 22 of 68 6 Functional Description 6 1 Calibration Clock Divider Figure 6 1 shows the principle function of the calibration clock divider ZEHREN 2 eh EK e DAAT en Tr m 1 128 Figure 6 1 Calibration Clock Divider The external calibration clock CALCLK is divided by the calibration clock divider The division factors are programmable and can be set to 1 2 4 8 16 32 64 or 128 Since a calibration measurement is always done by the TDC s measuring core it is necessary to ensure that in measurement range I the clock period tcar of the divided calibration clock CLK is not larger than 10u s 5V typ Otherwise the measuement of the calibration clock period would cause a measuring core overflow OV_CORE cp formula A1 in Appendix 8 4 2 In measurement range II the divided calibration clock period tca shouldn t be larger than 6 6us SV typ cp formula A4 in Appendix 8 5 2 Depending on the power supply VDD the maximum frequency
71. s cleared automatically e Bit is cleared automatically after generating a clock pulse for the pseudo random number generator Bit 4 amp Bit 5 simultaneous Soft reset Bit 3 Clock auto noise e TDC is resetted to its default state Ongoing measurement cycle or ALU calculations are aborted and all interrupt request and status flags are cleared e Bits are cleared automatically Execution of this direct command allowed only when the action bit time measurement is not set Do not clear this bit manually In doing this anyhow e g when resetting INTFLAG via bit 4 during a time measurement the measurement cycle is aborted irregularly and immediately Figure 7 1 Init Register INIT_REG Format TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 40 of 68 7 2 1 2 Control Registers CRTL_REG_1 CRTL_REG_2 CTRL_REG_3 7 6 4 3 2 0 Bit o o 00 Defut Resolution Measurement mode 000 Normal Resolution 000 Mode0 100 Mode 4 001 Half Resolution 001 Model 101 Mode 5 010 High Resolution 010 Mode2 110 Mode 6 100 Smart Resolution 011 Mode3 111 Mode 7 others reserved Channel selector bit for modes 0 1 4 5 6 and 7 reserved 0 Channel A 1 Channel B Figure 7 2 CTRL_REG_1 Format 7 6 5 4 3 2 1 0 Bit po otaiti tot ofo o Defut L Edge sensitivity START 0 rising edge 1 falling edge Edge sensitivity STOP_A 0 rising edge 1 falling edg
72. surement depends on the divided calibration clock period tea cp Chapter 5 2 and is calculated as follows tror sc 2 5 tcar tsc A7 The time tsc in formula A7 is a specific parameter of the separate calibration measurement Table 8 15 tsc is given for different conditions Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Values for pin INTFLAG Load 30pF Table 8 15 Time tsc for Dead Time of a Separate Calibration Measurement 8 10 5 Dead Time Increase due to Auto Noise and Retrigger Unit If the auto noise unit is enabled all dead times in Chapters 8 10 4 and 8 10 3 are increased by tan If the retrigger unit is enabled the dead times in theses chapters are increased by trr In Chapter 8 10 1 the dead times for measurement modes 1 3 and 5 are increased by tan and or trr for measurement modes 0 2 and 4 by 2 t n and or 2 trr The maximum values for tan and tgr are specified in Table 8 16 Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 16 Auto Noise Unit Offset tan and Retrigger Unit Offset ter TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 61 of 68 8 11 ALU Calculation Times Depending on the measurement m
73. tac A6 The time tac in formula A6 is similar to measurement range I the specific parameter of the automatic calibration measurement In Table 8 13 tac is given for different conditions 8 10 3 Dead Time between Burst Mode Measurements The dead time between burst mode measurements is defined as the time period between the stop of a burst mode measurement start stop and the following rising edge of the status flag TDC_READY on pin TDC_READY enabling the next burst mode measurement start stop Table 8 14 shows the maximum dead time tror g between burst mode measurements for different conditions Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Pin TDC_READY with Load 30pF Table 8 14 Maximum Dead Time tror g between Burst Mode Measurements TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 60 of 68 8 10 4 Dead Time of a Separate Calibration Measurement The dead time of a separate calibration measurement is defined as the time period between the ris ing edge of WRN when activating the action bit separate calibration measurement within the Init Register and the rising edge of the status flag MEAS _BUSYN resp the rising edge of the interrupt request flag INTFLAG set by I MEAS_END if enabled The dead time tror sc of a separate calibration mea
74. ted quartz oscillator clock at the input CALCLK The calibration clock is divided by the internal calibration clock divider circuit TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 8 of 68 4 Package and Pin Configuration 4 1 Package Figure 4 1 shows the TDC s Plastic Quad Flat Package with 44 pins LQFP44 and 0 8 mm pitch The package dimensions are specified in Table 4 1 The TDC s marking is MSC TDC502 V2 L D1 gen z S Ec IS E El Si Er B mm S 12 ei I Je mag De Figure 4 1 Package E1 DI A At A2 e b L a D E Cop min 00 135 030 045 BEE BE ee I nl I I nm max 160 015 145 105 os oio Table 4 1 Package Dimensions mm TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 9 of 68 4 2 Pin Configuration Table 4 2 shows the TDC s pin configuration Pin names of low active signals end with N in Mo Pinname 10 Function piso BE a 28 35 39 2 6 12 GND Ground for internal logic and I O s ies We eee 44 VDDC LI Power supply formeasuringcore _ 43 GNDC_ Ground for measuring eege 1 RSTN____ Un Power on reset ow active _ DD 2 CALCEK at for calibration clock 500 kHz 20 MHz ___ EX_MBI Tri state Expansion of measurement range II enabled Out 4mA EX_MBII toggles at every overflow of the pre
75. the result registers via the address bus ADR 3 0 The address spaces are selectable via the bits 6 and 7 of the Init Register The Init Register the Hit Status Register the GPIO Input Register and the Status Register are visible within all address spaces In Table 7 1 all read write registers are marked in gray color all read only registers are unmarked Address space 0 Address space 1 Address space 3 INIT_REG 7 6 00 INIT_REG 7 6 01 Address space 2 INIT_REG 7 6 11 INIT_REG 7 6 10 D7 DO D7 DO D7 DO1D7 DO J ERG REG_OP3 16 _ ROH_REG_3 7 0 ROR REG O70 _PERG_REG_1 31 24 _ ROH_REG_SUIS 8 _ ROH_REG_IIUIS 8 _ GPIO IN REG MSB LSB MSB LSB MSB LSB MSB LSB ADRI 3 0 Default address space after power on or soft reset Table 7 1 Address Spaces and Register Addresses TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 39 of 68 7 2 TDC Registers The TDC provides 15 read write registers and 3 read only registers 7 2 1 Read Write Register Formats 7 2 1 1 Init Register INIT_REG Figure 7 1 shows the format of the Init Register Via the bits 6 and 7 the address spaces for ad dressing all registers of the TDC are selectable Setting the other bits to 1 activation of action bits starts direct commands When the direct commands are completed the relevant bits are cleared to 0 automatically 7 6 5 4 3 2 1 0 Bit o CE 0 o o J
76. thin the Measurement Modes 1 3 5 Because of the automatic calibration measurement this dead time is increased for the measurement modes 0 2 and 4 to tror mBIM tror mato 2 5 tcaL tac A5 The time tac in formula A5 is a specific parameter of the automatic calibration measurement In Table 8 13 tac is given for different conditions Conditions voltage temperature process 5 5V 40 C best 5 0V 25 C typ 4 5V 85 C worst 3 6V 40 C best 3 3V 25 C typ 3 0V 85 C worst Table 8 13 Time tac for Measurement Modes 0 2 4 and 6 TDC502RefManEngV26 doc Version 2 6 Author AP User Manual TDC502 Page 59 of 68 8 10 2 Dead Time at the End of a Time Measurement in Measurement Range II The dead time at the end of a time measurement in measurement range II is defined as the time pe riod between the last hit of a time measurement and the rising edge of the status flag MEAS _ BUSYN resp the rising edge of the interrupt request flag INTFLAG set by I_MEAS_END if enabled For the measurement mode 7 mode without automatic calibration measurement the maximum dead time tror mBo at the end of a time measurement depends on the divided calibration clock period tear and is identical with the minimum measurement period typimin see Chapter 8 5 1 Because of the automatic calibration measurement this dead time is increased for the measurement mode 6 to tror mem tror mBo 2 5 tcar

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