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SG2650 board

1. a Et N N E v DJ PI pou um pp Pp gt 5 EG 25 cycle tiating required CPU clock EGR W OTINTREQ NTACK PREQ Mas ESET UCLK wan CPURESET end SG2650_Logic N N I O C STD LOGIC out STD LOGIC STD LOGIC STD LOGIC ter Reset coming from the pushbutton in STD LOGIC out STD LOGIC reset out in STD LOGIC architecture Behavioral of G2650 Logic is alias EnegNE is ADR13 alias DnegC is ADR14 signal theClock ST when 0 we are i signal first4KMem when 1 we are signal writeToData e a bit to say if t signal first4KBit Chis qa 207 signal isTheRam when ST this is an import D LOGIC n the first 8K of a MEMORY access STD LOGIC xecuting a write to data instruction WRID STD LOGIC he first 8K are ROM 70 or 71 STD LOGIC there s a Mem access to RAM D_LOGIC this ant signal basically is OPREQ AND CPUCLOCK is guaranteed to be a good strobe to latch data stuff for I O signal theStrobe S a duplication as signal theRomOE ST delayed OPREQ signal delayedOpreq UartCS UartIsSelecte signal signal IdeHISelected IdeLowSelecte signal signal this is to genera signal IdeStrobe S signal theIdeRD ST signal theResetCount signal ResCntNotZero 7 1 signal t 26 2 16 heCpuClkDiv 5 1
2. I o ID ena M JT 7 i E B Bose dde csel 18 Figure 5 The main DIN 4192 connector v lt CDOCUME IUCONNSCH prr DIED Tu ime B ms Fik cons 4 8 EM 5 and components list Please note those images are just for reference roundoff errors in the printing and con version process make them look lightly wrong in places tracks touching each other and some misalignments NOT present in the real print Warning the PCB shown contains a few little errors and some manual corrections via wire been done after also the IDE interface never been tested yet 5 1 components list Part Used PartType Designators 1 2 K R1 R2 2 N4148 D 3 Lurk C10 4 4K7 R4 5 22K R3 6 40PIN CON1 7 74HC245 U4 8 2 74HC574 01 02 9 16 LOOnF Cl 02 CICA CS 6 CT7 C8 C9 ClI C12 C14 Cl5 Cre CIT 10 2764 U5 11 6850 U9 12 2 CANOSC2 05 1 OSC2 13 2 CON3 CON2 CON4 14 DIN 64 5 15 JTAGCONN CON3 16 2 JUMPER 21 22 17 232 U3 18 SG2650 U8 19 SW PB EE 20 UPD43256 07 21 9536 U6 20 Figure 7 Bottom Layer 000002000000 000000000000000006 6 e 22
3. 00 0 10 05 10 05 0 10 08 4 01 10 08 98 57 04 W 0000 20 3F 02 8F 3F 02 8F 05 10 CD 10 08 OC 90 OE 4 00E0 20 1A 26 E4 19 22 02 OC 10 OF 84 01 CC 00 0 10 OF 98 08 10 0E 84 01 10 OE 10 08 gt 30 7 3 Monitor command A lt aaaa gt Alter memory contents The monitor command A allows to modify memory contents starting from address aaaa address can be from 0000H to 7FFFFH it enters an interactive mode where the address and the current content are shown by entering a two digit hexadecimal number you can modify the content Entering a DOT character exits and returns to the commands prompt terminating the modify session a 2000 2000 00 1 2001 00 23 2002 00 55 2003 00 gt 7 4 Monitor command 71 lt aaaa gt Load data at address via XMODEM The monitor command L allows to load data into memory starting ad adress aaaa address can be from 0000H to 7FFFFH using the XMODEM protocol simple CRC 128 bytes packet size This allows to load code or data into a memory address for further execution When the loading is finished the monitor returns to the command prompt Transfer can be aborted in any moment by sending two consecutive CAN characters CTRL X as by XMODEM protocol gt 1 2000 Transfer aborted gt 7 5 Monitor used memory The monitor st
4. Figure 8 Silkscreen 001 TJ ua gd t a a za dou JTAGCONN 23 6 CPLD VHDL source Here follows the complete listing of the VHDL source that makes up the CPLD Company Engineer Create Date 17 20 09 03 03 2012 Design Name Module Name SG2650 Logic Behavioral Project Name Target Devices Tool versions Description Dependencies Revision Revision 0 01 File Created Additional Comments library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL use IEEE STD LOGIC MISC ALL entity ClockDivider is generic widthBits integer 2 default value is 2 Port clkin in STD LOGIC div in STD LOGIC VECTOR widthBits downto 0 clkout out STD LOGIC negreset in STD LOGIC end ClockDivider architecture Behavioral of ClockDivider is signal zeroCount STD LOGIC signal counter STD LOGIC VECTOR widthBits downto 0 signal tmpclk STD LOGIC signal tmpZero STD LOGIC begin the first step is a divide by div counter DIVIDER process clkin negreset begin if negreset 0 then counter lt others gt 0 elsif clkin event and clkin 1 then if zeroCount 0 then counter lt div else counter lt counter 1 end if end if end process zeroCount OR REDUCE counter tmpZero zeroCount 24 the second step is a divide by 2
5. CPLD map register The ROM is designed to contain the bootstrap program 2 44 The CPU I O The I O employed used Extended mode only of the CPU which means an I O address too has to be supplied As the RAM is STATIC and the bootloader does NOT touch the ram contents except its own data area a reset via pushbutton should not alter RAM contents in any way this is very useful for debugging The I O address space is only partially decoded lines ADR4 and ADR3 are used to identify four different I O areas while lines ADRO ADR2 are used by the IDE interface to address the IDE registers during an IDE cycle The space is partitioned as by the following table Table 2 I O space partitioning ADR4 ADR3 Meaning 00 CPLD memory map register 01 UART 10 IDE Low byte DO D7 11 IDE High byte D8 D15 2 2 5 CPU SENSE and FLAG lines The SENSE and FLAG lines are connected to the RS232 level translators this allows them to be used as a software programmed serial communication port The lines after the RS232 translators are routed to connector CONA Table 3 CON4 pinout Pin Signal Direction 1 Flag Output RS232 level 2 Sense Input RS232 level 3 GND Ground 2 3 The UART The UART is a 6850 ACIA clocked at 1 Mhz Its transmit and receive clock are tied together and are supplied a 16 x Baudrate clock from the CPLD Only the line TX and RX are connected to the RS232 lev
6. LOC PACE PACE C p C P28 P29 P40 Spam 5 LOC P27 LOC 24 OC P43 LOC p44 LOC P13 LOC P4 LOC P9 LOC P3 LOC P8 LOC Pll LOC P12 OC s P2 j OC P37 LOC P5 OC P33 OC P39 OC P35 LOC P36 C P38 19 Gg c P22 gt Ca p20 F C P26 OC P18 LOC p14 p34 of PACE I O Pin Assignments Start of PACE Area Constraints Start of PACE Prohibit Constraints 29 PACE End of Constraints generated by PACE of Constraints generated by PACE 7 Card monitor bootloader program The card monitor booloader program is resident in a Eprom it allows initilisation of memory and UART and contains a mini monitor program that allows to e Display contents of memory e Modify memory contents e Load a program into memory via XMODEM e Execute code The monitor is accessed by connecting a computer terminal via serial port set at 9600 Baud 8 bits no parity At power up a welcome message is displayed such as Signetics 2650 CPU Board 1Mhz C 2012 Ivan Z Llamasoft BootLoader Version 5 02 gt Any time the prompt gt is displayed the monitor is ready to accept commands Com mands are a single letter eventually followed by two or four hexadecimal digits 7 1 Monitor command Help The monitor comma
7. bcta Sou errbell lodi bctr we endstr lodi stra retc R2 RO RO R2 RO UN RO UN RO UN UN UN nd RO UN RO RO UN Offh errbell 0 StrBuf R2 1 bksp WriteCh ror WriteCh bksp WriteCh k loop k loop the bell if bell echo ch still have to 0 StrBuf R2 Writes a message absolute 15 bits WriteMsg stra RO RO save Stra R1 R1 save msg lp loda bctr w loop rede andi bctr now wrte let lodi lodi adda betes lodi inc_h stra adda stra ett end endmsg loda loda retc RO R1 R1 EQ RO S RO Rl R1 EQ RO UN RO Rl UN xMsgHi endmsg UARTS TDRE w loop UARTTX increment a 1 1 MsgLo inc h 0 MsgLo MsgHi MsgHi msg lp RO save R1 save are we at the first char if so bell put a 0 at the current position R2 go back 1 char write backspace write space over it write backspace go to get more chars go to get more chars Something is wrong put the bell char in Sound it and go back in loop add NULL in case one just presses enter R2 and add a null unconditional return NULL 0 terminated where address is in MsgHi MsgLo Save RO Save R1 RO AdrHi AdrLo if 0 end of string let be sure we can transmit first check the transmitter empty bit if zero wait until it gets 1 we ca
8. rede loda comz bcfa pkt good here the packet is good and the CRC too we can advance pointers if and only if the packet number is NOT the same of before loda coma bctr stra loda stra loda stra no updateptr no crc lodi stra stra bsta lodi bsta bcta we rede stra adda stra R1 RO R1 EQ RO RO EQ RO RO RO RO RO RO RO RO UN RO UN UN RO RO RO RO no_timeout UARTRX X_CurPknum Offh trashl 2 X Phase no timeout go in loop getting more bytes get what we got i e 255 pktnum pkt num 255 pktnum if they are correct the result has to be Oxff if it s not 255 something is corrupted wrong we can go in phase 2 now go in loop getting more bytes 2 we are getting bytes now and computing the CRC X ByteCntH noucre X_ByteCntL LO 0 1 nocere the CRE 1 UARTRX X Crc trash X CurPkNum X LastPk no updateptr X LastPk X CurAdrHi X AdrHi X CurAdrLo X AdrLo 0 X Phase X Crc XM ResetPtr CHAR ACK WriteCh no timeout UARTRX CurAdrHi X Crc is hi counter 0 no can t be the CRC is HI 0 and LO 1 no can t be the CRC get what we got get the computed CRC check if they match if they don t trash everyting and send NAK if the numbers are the same don t update the PTRs make LastPk CurPkNu
9. IDE write cycle starts In the case of a READ operation first the IDE Low Byte register has to be read with ADRO ADR2 containing the value of the IDE register you intend to read followed by a read of the IDE High Byte register Table 9 IDE Read Cycle Action Effect ADRO 2 selects IDE register IDE read cycle starts Data is latched Data LOW is read 2 Extend I O read on HI register Data HI is read 1 Extend I O read on LOW register ONLY when the IDE Low Byte register is being used a IDE WR or IDE RD signal together with an IDE CSO is generated when IDE High Byte register is being used all those signals are kept inactive In this implementation IDE CSI is hardwired to logic level 1 2 41 IDE connector A standard 40 pin IDE connector header is present on the board this connector follows the standard IDE pinout as shown below Table 10 IDE 40 pins connector assignement Pin Name Pin Name 1 Reset 2 GND 3 D7 4 D8 5 D6 6 D9 7 D5 8 D10 9 D4 10 D11 11 D3 12 D12 13 D2 14 D13 15 D1 16 D14 17 DO 18 15 19 GND 20 key 21 DMARQ 22 GND 23 DIOW 24 GND 25 DIOR 26 GND 27 IORDY 28 CSEL 29 30 GND 31 INTRQ 32 IOCSI6 33 DAI 34 PDIAG 35 DAO 36 DA2 37 ADE CSO 38 CSI 39 ACTIVE 40 GND A standard 40 pins IDC cable is supposed to be used to connect it to a hard drive or other
10. RO RO RO PtrHi save back LO RO we have an overflow of the Lo we can increment Hi unconditional return unconditional return 0 packet still to begin wait for SOH or STX and or CAN 1 stx soh got getting pktnum 255 pktnum 2 got those above now just getting data crc while computing CRC assuming somewhere the load address been put into AdrHi AdrLo 0 X Phase X OneK X TimeCntH 1 X TimeCntL Offh X LastPk 2 X CanCnt phase 0 assume we are going for 128 bytes timeout counter force a timeout last packet number Oxff CAN counter check the timeout counter X TimeCntL 1 X TimeCntL Offh nosubh X TimeCntH 1 X TimeCntl if not negative go on otherwise subtract 1 41 too nosubh timeout trash end tr no timeout Stra R0 X TimeCntH from the HI part too and save it loda RO X TimeCntH iora R0 X TimeCntL bcfr EQ no timeout if OR L 0 NO timeout we have a timeout lodi RO 0 stra RO X Phase we restart from phase 0 stra RO X Crc rede R1 UARTS let s check the UART status andi R1 RDRF any char in the RX buffer bctr EQ end tr if not stop thrashing UARTRX read and thrash chars nop nop nop waste a bit of time bctr UN trash continue to trash lodi RO CHAR bsta UN WriteCh Send a NAK lodi RO Offh restore timeout counter stra RO X TimeCntL stra RO X TimeCntH bsta UN XM ResetPtr r
11. UN UN R1 UN betr EQ iorz bcta let bsta stra stra bsta stra stra RO 5s UN RO RO UN RO RO WriteCh write it wait util we get something from the KB GetStr a CR LF hi m crlf MsgHi lo m crlf MsgLo WriteMsg 0 SkipWhite prompt 1 Rl_save ral command 32 rH no_help it s help hi m help MsgHi lo m help MsgLo WriteMsg prompt no dump no dump R1 save SkipWhite prompt prompt get a 16 bits Get8Hex MemHi X CurAdrHi Get8Hex MemLo X CurAdrLo is the first not null char we may have something to do write CR LF Start at the beginning of the string Skip the white spaces and get something in RO if it s an EQ we have an empty string brutal but because for further things we want to be PAST this char let s save R1 as index to the first non white is it a no fine as it is yes make it uppercase then A 77 what we have is it help no it s not write the help info go back to prompt is dump no it s not no it s not let s get two numbers This is DUMP lt gt want that index back Skip the white spaces and get something in RO if it s an EQ we have an empty string if it s an EQ we have an empty string number first HIGH digit in RO a copy in here too Second LOW digit in RO idem 34 l loop b loop in
12. equ equ equ equ equ Variables for C N UART UART UART UART IDE IDE 13H Ith 02H 01H 18H 06H TSH 04H control register write status register read transmit register write receive register read write to this first 8K ROM write to this first 8K RAM register High Byte register Low Byte no RX int no TX int 8 bits 2 stop Master Reset no RX int no IX int 8 bits 2 stop clock 16 if 1 data is ready in the RX register if 1 the TX register is empty Stores the address in memory where the message is place to place to place to place to couple save RO save R1 save R2 save a memory address for dump load etc of counters string buffer where readstring puts stuff in the Xmodem Loader 32 equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ set 51 51 1 UN 1009 00a 100b 100 100d 100e 00f 010 011 012 013 1014 1015 016 1017 018 019 ee RO xmodem loader phase of the state machine counter of how many CHAR CAN we received last packet received number hi low address of the packet we are receiving current packet address in memory Hi and Lo current CRC in computation bytes counte
13. percent this duty cycle is guaranteed by a flip flop acting as a divide by two clock shaper NOTE in this particular implementation a 16 Mhz CAN oscillator is first divided by 8 and then further by 2 by the clock shaper to get a perfect 50 percent duty cycle 1 Mhz clock 2 2 2 The CPU reset The CPU reset is generated by the CPLD as well and is triggered by power up or the panel reset button At power up until capacitor C10 is charged via R3 a low level is forced on the MReset pin the CPU reset pin is hold low as long as this condition persists When MReset returns high the CPU reset pin is released and set to logic 1 after four CPU clock cycles When the pushbutton P1 is pressed this fully discharges the capacitor C10 restarting the whole thing above once released 1 2 2 3 The CPU addressing space The CPU has a maximum addressing space of 32K which is split between ROM ad dressing space and RAM addressing space At power up or immediately after a reset the first 4K of addressing space are de signed as ROM and the remaining of the addressing space as RAM Table 1 CPU address space after power up or reset Addressrange Memory 0000H 0FFFH 1000 7FFFH RAM The RAM is implemented as a single chip 43256 32k x 8 bits while the ROM can be selected via jumper J2 to be a 6264 8K x 8 or a 2732 4K x 8 chip The first 4K of the addressing space can be dedicated to RAM by writing into the
14. we have an empty string if it s a end here if it s a end here assume is a valid digit get digit in RO write it into memory assume 1 for MemHI 1 for MemLo in ANY case R1 1 if 0 means Hi has to be incremented too else leave MemHi untouched save again MemLo RO 1 0 MemHi ror continue until continue until ror is it load no it s not assume 1100h as default load address want that index back skip the white spaces and get something in RO if it s an EQ we have an empty string number first HIGH digit in RO second LOW digit in RO go do the XMODEM protocol safety is it jump no it s not want that index back skip the white spaces and get something in RO if empty no jump number 37 bsta stra bsta stra bcta no jump end cmd all bcta Ski ret SkipWhite subi Skp lp oda retc comi bctr retc UN RO UN RO UN UN R1 RO EQ RO EQ UN urns R1 Get8Hex MemHi Get8Hex MemLo xMemHi prompt StrBuf R1 E skp_lp first HIGH digit in RO Second LOW digit in RO JUMP Ta ta ta ta tata ta unrecognized commands end up here ps the white spaces in a string starting at index R1 to the first non white char or NULL R1 cause the immediately after this get the char in RO if we met a NULL we can end here is it a space yes move on no we found
15. DE RD lt theIdeRD IDE WR lt IdeStrobe or not NEGR_W or IdeLowSelected IDE 50 lt not OPREQ or IdeLowSelected IDE OE3 lt IdeLowSelected or not OPREQ 28 high DE 1 read high DE OE2 write Nes high write DE CLK2 not when you rea DE CLK1 lt the end Behavioral DE BDIR NEGR W 0 latch latch OUTPUT latch STORE OUTPUT or IdeHiSelected or not IdeStrobe d low IdeRD IdeLowSelected or not it also latches remember it latches on the RAISING EDGE A when I read HI IdeHiSelected or NEGR W or not when I write on LOW which does the IDE CS cycle write OPREQ or not high gt W when I write on high NEGR W 6 1 The file for the CPLD pins assignement PACE Start Start NET ADR12 10 NET ADR13 10 NET ADR14 10 NET ADR2 LOC NET ADR3 LOC NET ADR4 LOC NET BAUDCLK NET BAUDCLK16 NET 1 CPURESET IDE BDIR NET IDE CLK1 NET IDE CLK2 NET IDE CSO NET IDE 1 NET IDE OE2 NET IDE OE3 NET IDE RD 1 NET IDE WR 1 NET 1 MAINCLK MNEGIO 1 MRESET 1 NEGR_W L NET NOTINTREQ NET OPREQ LO NET RAMOE LO NET RAMWE LO NET ROMOE LO NET UARTE LO NET UARTRW 1 NET UARTSEL NET WRP
16. E lt isTheRam or not W now let s sort out the 6580 we assume the CPU and the Uart both go the same 1 2 clock NOTE this is the NOT of the CPU clock must be 1Mhz UARTE lt not theClock DELAYOPREO process theClock begin if theClock event and theClock 1 then delayedOpreq lt OPREQ end if end process it works using a EXTENDED I O instruction ADR4 ADR3 01 UartIsSelected lt 0 when EnegNE 1 and MNEGIO 0 and ADR3 71 and ADR4 0 else 1 UartCS lt not delayedOpreq and OPREQ or UartIsSelected UARTRW lt not NEGR W neg because on the 6850 is RnegW i e 70 write 71 read UARTSEL lt UartCS BaudClkDivide ClockDivider generic map widthBits gt 2 port map BAUDCLK theBaudClkDiv BAUDCLK16 MRESET tricky part time to check about those IDE signals so we have ADR4 ADR3 10 IDE L and ADR4 ADR3 11 IDE H IdeLowSelected lt 0 when EnegNE 1 and MNEGIO 0 and ADR3 70 ADR4 1 else 1 IdeHiSelected lt 0 when EnegNE 1 and MNEGIO 0 and ADR3 71 ADR4 1 else 1 THEIDESTB process MRESET theClock begin if MRESET 0 then IdeStrobe lt 1 elsif theClock event and theClock 1 then if OPREQ 1 then IdeStrobe not IdeStrobe end if end if end process theIdeRD lt IdeStrobe or NEGR_W or IdeLowSelected I
17. O 27 28 n c 1 29 MRESET 30 BaudCLK 31 adr2 baudclk16 32 GND GND Table 13 Signals meaning Signal name Type Meaning adr14 adr0 Output Address lines d7 d0 Input Output Data lines opreq Output Operation Request negR W Output Read 0 or Write 1 WRP Output Write Pulse MNegIO Output Memory 1 orIO 0 CpuCLK Output CPU Clock 1Mhz MRESET Output Master Reset active 0 BaudCLK Output Baudrate Clock baudclk16 Output 16 X Baudrate Clock VCC Input 5v Power Supply GND Input Power Supply Ground 0 V n c means a not connected pin For more details about the signals please consult 562650 CPU User Manual 2 7 JTAG connector A 10 pins IDC type connector is present containing JTAG signals for programming of the CPLD The connector is designed to fit the XILINX Parallel 3 Upload Cable Pin number of the connector can be connected to the board VCC via jumper 11 normally this pin is NOT connected Table 14 JTAG connector pins assignements Pin Signal Pin Signal 1 VCC 2 GND 3 TCK 4 TDO 5 TDI 6 TMS 7 8 9 10 means a not connected pin 2 8 The DB9 RS232 connector On the front panel a male DB9 connector is present for the RS232 port this is for connection to a computer or terminal to access the board monitor program The pinout of the connector is as following Table 15 F
18. SG2650 board Ivan Z aka Giles gilesgoat gilesgoat com March 22 2014 Contents 1 Introduction 2 Constructional details of board 21 Thepowersuppl 22 The CPU ie ner ere he d 22 1 TrheCPU clock ou mme RR RO Rex 22 2 The CPU reset xev ax 2 23 The CPU addressing 224 TheCPUTO ii nx 264 2284 2 2 5 CPU SENSE and FLAG lines 23 The UART a cds ed mte ee e Pe RR ee 23 1 UART ouo kno p Sod 2 3 2 baud rate 2 3 3 2 3 4 The uart TX RX lines 24 IDE interface so cee Rr RR ER 24 1 IDE connector 2 5 The CPED duode poU ER SEA 2 6 The main edge connector 227 JLAG connector s hows ee 2 8 9 232 3 Jumpers settings 4 Schematics 5 The PCB and components list 5 1 components list lees 6 CPLD VHDL source 61 file for the CPLD pins assignement N NN OO amp gt HS HWW W A 20 20 24 7 monitor bootloader pro
19. are ok subi RO 32 adjust for a f dig2ok iora RO R2 Save low nibble in RO addi R1 1 make it point to the char after this retc UN unconditional return Writes the 8 hex digit in RO Write8Hex stra RO Rl save loda R2 R1 save rrr RO rrr RO rrr RO rrr RO andi RO OfH get the high nibble and mask it addi RO 70 sum this comi RO 58 is the result 58 bctr LT diglgd if yes we are ok addi RO 7 otherwise we need 7 more to be A p 40 diglgd bsta UN lower loda RO andi RO addi RO comi RO bctr LT addi RO dig2gd bsta UN retc UN WriteCh write the high nibble nibble same story R1 save OfH EOF 58 dig2gd 7 WriteCh get the low nibble and mask it sum this is the result lt 58 if yes we are ok otherwise we need 7 more to be A F write the low nibble unconditional return A subroutine to increment a 16 bits pointer IncrPtr lodi RO AddPtr adda RO bctr EQ retc UN pt inch lodi RO adda RO stra RO retc UN lodi RO E adda RO A stra r0 i bcfr EQ H lodi RO adda r0 stra r0 donel 1 xPtrLo xPtrLo pt inch PtrHi PtrHi XXXL XXXL donel XXXH XXXH Xmodem Loader phase phase phase Do Xmam lodi RO lodi RO stra RO lodi RO stra RO lodi RO let s tim check loda RO subi RO stra RO comi RO bcfr EQ loda RO subi
20. arts at address 0000H in ROM and uses some memory locations from 1000H to 1040H about to hold some variables and states Please refer to the monitor listing for more details 7 6 Monitor listing Here is a complete 2650 assembler listing of the bootloader monitor program tabs 10 8 first tab is 10 then each tab is 8 ahead width 132 prevent folding of long lines noproces disable fancy stuff speed is what we want title Bootloader 1 stitle Written Ivan Z Llamasoft 2012 name bootl 2650 the module name org 0 ROM start address LE equ 10 line feed cr equ 13 carriage return bksp equ 8 backspace bell equ 7 the bell char 31 del EQ GT LT UN UARTC UARTS UARTTX UARTRX CPLDROM CPLDRAM IDEHI IDELOW res uart uart con RDRF TDRE MsgHi MsgLo RO save R1 save R2 save MemHi MemLo 1 Cnt2 StrBuf Definitions for the XMODEM loader CHAR STX CHAR SOH CHAR CAN CHAR ACK CHAR NAK CHAR EOT equ name the condition codes 12 7 delete char we don t remember numbers anyway equ equ equ equ equ equ equ WD NU PNO zero always true name the registers equ equ equ equ Some values for I O space equ equ equ equ equ equ equ equ f equ equ Q 0000 QQ QQ equ 08h 08h 09h 09h 20h 30h equ equ 000 001 002 003 004 005 006 007 008 equ
21. ations could be done The choice of the particular format and connector also been dictated by the will of making it fit inside a standard 19 inches rack therefore the 160 x 100 mm 3U Eurocard standard format been chosen been manually constructed been designed developed etched and drilled manually as well as the construction and design of the front panel At the time this board been built the Xilinx CPLD XC8536 was still available for a new project you should replace it with the 3 3V version and add a voltage regulator for its power supply Ea aoa E Jo HOC TST a ams Lc Figure 1 Project root 15 Figure 2 The CPU with RAM ROM CPLD and reset o m DI Mounted solder side in parallel to R3 N48 vee ak Reset eee n SWPE Irem CXDOCUME I WMAINCBU SCH 16 Figure 3 The UART and the RS232 port o m ar Irem EATERY CADOCUME TX SERIAL SCH 17 Figure 4 The IDE interface and connector
22. c hm asc lp sublp noincha time to dump all this lodi stra lodi stra loda bsta loda bsta lodi bsta bsta loda bsta lodi bsta lodi lodi adda betr lodi stra adda stra loda subi stra bcfr E R1 Rl R1 R1 2 2 m RO R1 RO 16 Cntl 16 Cnt2 MemHi Write8Hex MemLo Write8Hex ror WriteCh WriteCh MemHi Write8Hex WriteCh 1 1 MemLo inc hm 0 MemLo MemHi MemHi Cnt2 1 Cnt2 b loop 16 lines counter 16 bytes at time write the high address byte write the low address byte write a couple of spaces RO AdrHi AdrLo write the byte at that mem loc write a space assume 1 for MemHI 1 for MemLo in ANY case R1 1 MemLo if 0 means Hi has to be incremented too else leave MemHi untouched save again MemLo RO 1 0 x MemHi decrement the row counter go in loop if not zero 1 line of 16 bytes been dumped new stuff lodi bsta bsta lodi stra loda comi pctr comi bctr bsta loda addi stra bcfr loda addi stra loda subi RO UN UN R1 R1 ro ror WriteCh WriteCh 16 Cnt2 X_CurAdrHi 32 no_asc 129 no asc WriteCh X CurAdrLo X CurAdrLo noincha X CurAdrHi X CurAdrHi Cnt2 the ASCII dump write a space write another space 16 bytes again at t
23. cted to the levels translator and provide an additional software driven serial communication port One DB9 male connector is present on the main bezel the two serial port as well as a reset pushbutton switch A standard 40 pins IDE PATA connector is also present on the board for connec tion with some sort of hard drive unit The main logic functions are provided via a single CPLD chip to reduce compo nents count The board also contains two CAN clock oscillators one to provide the main 1 Mhz system clock on the board and one to provide an 1 8432 Mhz used for baud rate generation 21 The power supply The board requires a single power supply at 5V VCC board consumption been not measured but it s supposed to be around various hundreds of miliampers The required tensions for the RS232 interface are derived internally from the 5V via charge pump methods by the MAX232 chip 2 2 The CPU The CPU is a Signetics 2650 clocked at 1 Mhz As the board is very minimal and the component load is small no buffering is present if other cards have to be connected to it the added card must contain its own buffers for the required lines 2 2 4 The CPU clock The CPU clock is generated by the CPLD via a divisor the main oscillator clock is divided as necessary to generate 1 Mhz The frequency of 1 Mhz been chosen because this is also the maximum frequency the UART can cope with The clock is a standard TTL level clock with a duty cycle of 50
24. el translators CTS and RTS lines are not used The RS register select pin is connected to ADRO The UART is selected via Extended I O operations any time ADR4 ADR3 are as 01 2 31 UART registers UART has 4 registers mapped as follow Table 4 UART registers mapping ADR2 I O Operation Meaning 0 Write Control register 0 Read Status register 1 Write Transmit register 1 Read Receive register For convenience here a quick look at the Control and Status register Table 5 UART Control register Bit Meaning 0 Counter Divide Select 1 CRO 1 Counter Divide Select 2 2 Word Select 1 CR2 3 Word Select 2 CR3 4 Word Select 3 CR4 5 Transmit Control 1 CR5 6 Transmit Control 2 CR6 7 Receive Interrupt Enable CR7 Table 6 UART Statusl register Bit Meaning 0 Receive Data Register Full RDRF Transmit Data Register Empty TDRE 2 Data Carrier Detect DCD 3 Clear To Send CTS 4 Framing Error FE 5 Receiver Overrun OVRN 6 Parity Error PE 7 Interrupt Request IRQ 2 3 2 The baud rate clock The UART requires a baudrate clock which must be 16 times the desired baud rate this clock is generated by a divisor internal to the CPLD starting from a 1 8432 Mhz clock The 1 8432 Mhz clock is generated by a CAN oscillator The supplied UART clock is set to 16 times 9600 so is at 153600 Hz via an in
25. eset pointers and fall back here rede R1 UARTS let s check the UART status andi R1 RDRF any char in the RX buffer bcta EQ tim check if not continue to check for timeout here we got some char from the serial port char got lodi RO Offh stra RO X TimeCntL stra RO X TimeCntH reset the timeout counter to now we process the char depending on the phase loda RO X Phase bcfa EQ x phasel if it s not 0 could be phasel x phase0 here we are in phase 0 waiting for SOH or STX rede RO UARTRX get what we got comi RO CHAR is it a CAN character maybe bctr EQ is can if yes go to process it it s not a CAN could be STX or SOH comi RO CHAR SOH is it a SOH bctf EQ maybe stx no maybe it s an STX then bctr EQ is soh yes go there CHAR 5 is it an STX maybe 42 bcfr here is an 5 lodi stra lodi stra bctr maybe eot trashl is soh go one is can x abort end tr2 comi bcta bcta RO RO RO RO UN RO EQ UN maybe eot 04h X_ByteCntH 0 X_ByteCntL go_one CHAR EOT 2 end xloader trash no could be then it means there are 1024 bytes of data set for 1024 bytes 400h and go in phase 1 is an EOT char if yes end of the file transfer unrecognized shit thrash all and send NAK it s a SOH let s reset pointers counters and CRC bsta lodi s
26. gram 71 Monitor 7 2 Monitor command D lt aaaa gt Dump memory 7 3 Monitor command A lt aaaa gt Alter memory contents 7 4 Monitor command L lt aaaa gt Load data at address via XMODEM 7 5 Monitor used 7 6 Monitor listing A Regresa IE RUE 8 Card pictures 9 Disclaimer and License 30 30 31 31 31 31 46 49 Abstract Long time ago a friend of a friend of mine gave me a bag full of really old chips some of them were some curious interesting CPUs Years later an idea to preseve the memory and knowledge of those unusal CPUs came in mind and so I did start a mission to create small but still useful boards with those CPUs This is one of those boards a simple one based around the Signetics 2650 1 Introduction The 562650 board is a single board computer based around 562650 CPU The board is a standard 160x100 Eurocard board with an DIN41926 64 pin con nectors designed to fit in a standard 19 inches 3U rack 2 Constructional details of board The board is a standalone computer with a CPU RAM ROM an UART for RS232 communication and IDE port and DIN41926 connector for interfacing with other components The UART provides 1 serial channel which is then connected to a levels translator to provide correct RS232 level two special CPU pins named SENSE and FLAG are also conne
27. ime is something between space and 127 is 32 ignore it is 127 ignore it write the char decrement the ascii bytes counter 35 no asc dolf no_dump a_loop stra bsta lodi bsta bctr RO UN RO UN UN print lodi stra lodi stra bsta loda subi stra bcfr E bcfa bcta comi bcfr bcfa is alter loda bsta bctr bcta let bsta stra bsta stra loda bsta loda bsta lodi bsta bsta loda bsta lodi bsta lodi bsta lodi bsta let bsta RO RO RO RO UN R1 UN EQ EQ UN RO UN RO Cnt2 asc lp dolf Tor WriteCh sublp a CR LF hi m crlf MsgHi lo m crlf MsgLo WriteMsg 1 1 1 1 loop 1 loop prompt AC no alter no alter R1 save SkipWhite prompt prompt let s get get a 16 bits Get8Hex MemHi Get8Hex MemLo MemHi Write8 MemLo Write8 ror WriteC WriteC xMemHi Write8 ror WriteC ror WriteC WriteC Hex Hex 5 Hex go in loop if not zero finally go next line write a dot and go in loop again write CR LF decrement the line counter go in loop if not zero go in loop if not zero end of dump is it alter no it s not no it s not two numbers want that index back Skip the white spaces and get something in RO if it s an EQ we have an empty st
28. m advance pointers restart from phase 0 reset CRC put counters and stuff back send a ACK go in loop getting chars are reading saving bytes and computing the CRC on them then get what we got Save the byte compute the CRC and update it 44 time to increment loda RO X CurAdrLo addi RO 1 stra RO X CurAdrLo bcfr EQ no inchi loda RO X CurAdrHi addi RO 1 stra RO X CurAdrHi inchi the pointer increment the low part and save it if lt gt 0 no need to increment hi increment the high part we need to decrement the bytes counter loda RO X ByteCntL subi RO 1 Stra R0 X ByteCntL comi RO Offh bcfr EQ nosubh2 loda RO X ByteCntH subi RO 1 Stra R0 X ByteCntH nosubh2 if not negative go on otherwise subtract 1 from the HI part too and save it this should never be 0 if it gets 0 here there s something weird bcta UN no timeout end of all xloader end xloader lodi RO CHAR ACK bsta UN WriteCh go in loop getting chars in a good way send a ACK waste a bit of time and trash everything that comes lodi RO 020h waste lodi R1 Offh wastel nop nop nop nop rd subi R1 1 bcfr EQ wastel subi RO 1 bcfr EQ waste lodi RO hi loadok stra RO MsgHi lodi RO lo loadok stra RO MsgLo bsta UN WriteMsg bcta UN prompt Mini routine resets PTRs waste a bit of time save address of message
29. n transmit the byte Send the character ddress now assume 1 for AdrHI 1 for AdrLo in ANY case R1 1 MsgLo if 0 means Hi has to be incremented too else leave MsgHi untouched Save again MsgLo RO 1 0 MsgHi continue with the message of transmission restore and return unconditional return Writes the char contained in RO 39 WriteCh stra RO RO save loop2 rede RO UARTS let be sure we can transmit first andi RO TDRE check the transmitter empty bit bctr EQ w loop2 if zero wait until it gets 1 now we can transmit the byte loda RO RO save get it back wrte RO UARTTX send the character loda RO RO save retc UN unconditional return get 8 bits value from hex R1 index to string buffer RO exit result Get8Hex subi R1 1 1 for index cause now loda RO StrBuf R1 get the char in R2 retc EQ if zero end subi RO 70 we do it a bit simpler way comi RO 10 bctr LT diglok if 10 we are ok subi RO 7 adjust for comi RO 16 bctr LT diglok if 16 we are ok subi RO 32 adjust for a f diglok rrl RO rrl RO rrl RO rrl RO put the high nibble where it should be stra RO R2 Save same story for the second digit loda RO StrBuf R1 get the char in RO retc EQ if zero end subri RQ 0 we do it a bit simpler way comi RO 10 bctr LT dig2ok if 10 we are ok subi RO 7 adjust for comi RO 16 bctr LT dig2ok if 16 we
30. nd H displays a help text showing the list of available commans gt h H shows help D lt aaaa gt dumps memory A lt aaaa gt alters memory to exit L aaaa XMODEM loads data X CAN J lt gt jumps to address aaaa hexadecimal 16 bits address gt 7 22 Monitor command D lt aaaa gt Dump memory The monitor command D displays an hexadecimal and ASCII dump of a 256 bytes memory block starting from address aaaa address can be from 0000H to 7FFOOH the non printable ASCII characters are replaced by dots gt d 0000 0000 20 93 CO CO CO CO CO CO 05 13 D5 08 CO CO CO CO 0010 co CO D5 08 CO CO 05 11 D5 08 CO CO 04 04 0020 10 00 04 10 01 02 04 02 0030 3F 01 FB 04 05 10 00 04 16 CC 10 01 3F 02 5F r2 0040 05 00 3F O1 FO 60 18 63 85 01 CD 10 03 4 61 1A Ree a 0050 02 4 20 4 48 98 10 04 05 10 00 04 19 CC 10 Va Ha urere Rey ere 0060 01 02 00 2B E4 44 9C 01 2B OD 10 03 0070 01 FO 60 1C 00 2B 02 Al CC 10 05 CC 10 EC iy RE ee ca oe 2 0080 02 Al CC 10 06 10 OF 05 10 CD 10 07 05 10 CD 0090 10 08 10 05 02 D4 0C 10 06 02 04 20 EE 00 0 02 8F 02 8F OC 90 05 02 D4 04 20 02 0080 04 01 05 01 8 10 06 18 02 04 00 CD 10 06 8
31. r Hi bytes counter Low in reality up to 1024 3 timeout counter Hi timeout counter Lo counter for the first 2 packet bytes pkt num current packet number if X LastPk DO NOT update ptrs 1K flag if not zero we are using packets ro 0 load status low from RO uart and all the other shit res_uart UARTC UARTC uart conf UARTC hi bootmsg MsgHi lo bootmsg MsgLo WriteMsg main prompt loop X Phase X CanCnt X LastPk X AdrHi X AdrLo X CurAdrHi X CurAdrLo X Crc X ByteCntH X ByteCntL X TimeCntH X TimeCntL X CntTwo X CurPknum X OneK PtrHi PtrLo start eorz lpsl Re nop nop nop nop nop nop lodi wrte nop nop nop nop nop nop wrte nop nop nop nop lodi wrte nop nop lodi stra lodi stra bsta prompt lodi master reset to the uart master reset to the uart configure the uart for 9600 baud 8 bits no parity 1 stop save address of message write the boot message the prompt 33 command no help bsta let bsta pri lodi stra lodi stra bsta lodi bsta iorz bctr if we are here RO now this is a bit addi stra comi bctr subi time to interpret comi bcfr lodi stra lodi stra bsta bcta comi poti bcfa is dump loda bsta UN s UN nt RO RO RO RO UN R1 R1 RO LT RO RO EQ RO RO RO RO
32. ring if it s an EQ we have an empty string number first HIGH digit in RO Second LOW digit in RO write the high address byte write the low address byte write a couple of spaces RO AdrHi AdrLo write the byte at that mem loc write a space write a question mark write a space wait util we get something from the KB GetStr 36 inc hm2 no alter go xmo no load print lodi RO stra RO lodi RO stra RO bsta UN lodi R1 bsta UN bctr EQ comi RO bctr EQ beta EQ it s not a we bsta UN stra RO lodi RO lodi R1 adda R1 bctr EQ lodi RO Stra R1 adda RO bctr UN bcta UN comi RO bcfa EQ lodi RO lodi RO stra RO loda R1 bsta UN bctr EQ let s bsta UN bsta UN bcta UN bcta UN comi RO bcfa EQ loda R1 bsta UN bcta EQ let s a CR LF hi m crlf MsgHi lo m crlf MsgLo WriteMsg 0 SkipWhite a loop Tor prompt prompt Get8Hex xMemHi 1 1 MemLo inc hm2 0 MemLo MemHi MemHi a loop a loop no load LIB X AdrHi 00h X AdrLo R1 save SkipWhite go xmo get a 16 bits Get8Hex X AdrHi Get8Hex X AdrLo Do Xmdm prompt jump R1 save SkipWhite prompt get a 16 bits write CR LF Start at the beginning of the string Skip the white spaces and get something in RO if it s an EQ
33. ront panel DB9 serial connector Pin function direction 1 not used 2 RXD input 3 TXD output 4 not used 5 GND ground 6 not used n a 7 not used n a 8 not used n a 9 not used n a 3 Jumpers settings Two jumpers are present in the card they are called J1 and J2 Jumper J1 when in ON inserted position connects the VCC of the board to the VCC line pin 1 of the JTAG connector this allows to supply power to the upload cable from the board or to the board from the cable Jumper J2 when in ON inserted position supplies VCC to the pin 26 of the ROM socket this is designed for a 2732 4Kx8 EPROM 12 Table 16 Main Board jumpers J1 and J2 On jumper inserted Off no jumper Jumper Position Meaning Vcc to JTAG Pin 1 Off JTAG Pin 1 disconnected J2 On Vcc to ROM pin 26 2732 used J2 Off ROM pin 26 disconnected Jumpers are normally both in OFF position not inserted Check the pictures for jumper locations and position 4 Schematics We have here the fulll board schematics there are various sheets such as e Project Root sheet e CPU RAM ROM and CPLD e UART and serial port e IDE interface e Main connector The choice of components been around the idea to keep the number of chips low and what I already had around and simplicity of constructing such a board with home technology Of course different choices and even better optimis
34. signal t x2 12 so heBaudClkDiv component ClockDivid generic widthB STD TD LOGIC we need it to combine for ramoe D LOGIC STD LOGIC LOGIC d STD LOGIC STD LOGIC d STD LOGIC te the ide read write signal TD LOGIC D LOGIC er STD LOGIC VECTOR 2 downto 0 STD LOGIC STD LOGIC VECTOR 2 downto 0 111 1 8432 Mhz 12 153 600 Khz 9600 x 16 STD LOGIC VECTOR 2 downto 0 101 er its integer 2 default value is 2 26 Port clkin in STD LOGIC div in STD LOGIC VECTOR widthBits downto 0 clkout out STD LOGIC negreset in STD LOGIC end component begin the CPU clock we assume is MAINCLK divided by 4 to get 1 Mhz CpuClkDivide ClockDivider generic map widthBits 2 port map MAINCLK theCpuClkDiv theClock MRESET CPUCLK lt theClock let s make a CPU reset that is guaranteed to stay for some clock cycles ResCntNotZero OR REDUCE theResetCounter or of all its bits CPURESET lt ResCntNotZero 1 as long as it s not 0 NOTINTREQ lt 1 for now no interrupts RESCPU process MRESET theClock begin if MRESET 0 then theResetCounter lt 101 5 1 4 clock cycles elsif theClock event and theClock 1 then if ResCntNotZero 1 then theResetCounter lt theResetCounter 1 end if end if end process as explained before this guarantes a valid strobe when all da
35. something Gets a string into StrBuf no longer than MAX CHARS GetStr lodi k loop rede andi bett we rede comi bcta comi bctr bcta comi pett comi betr comi comi bctr the comi bctr stra stra lodi stra subi R2 R1 R1 EQ RO RO EQ EQ RO EQ EQ RO EQ RO EQ RO LT RO GT R2 EQ RO RO RO RO R2 Offh UARTS RDRF k_loop have some char UARTRX endstr endstr lf endstr endstr bksp backspace del backspace 32 k loop 127 k loop char is good 16 errbell StrBuf R2 RO_save 0 StrBuf R2 1 1 cause the 44 this is our pointer let s check the UART status any char in the RX buffer if not just wait again is a carriage return yes we have something yes we have something is a line feed yes we have something yes we have something go handle the backspace if it s a DEL 127 char go handle the backspace is something between space and 127 is 32 ignore it is 127 ignore it can we put it in no we are already full R2 and save it into the buffer R2 and add a null dec R2 so it s ready for the next char finally echo the char loda RO RO save echo ch bsta UN WriteCh bctr UN k loop write it get a new char 38 backspace comi bctr lodi stra subi lodi bsta lodi bsta lodi bsta H becker
36. storage unit 2 5 The CPLD map register This is simply a write only 1 bit register that can be accessed by an Extended I O operation when ADR4 ADR3 are as 00 As there is no data bit connected to it instead an address line ADR2 is used for that so the value of ADR2 is used to assign the value to this register bit When the register bit is set to 1 then the ROM totally disappears deselected from the address space making the full 32K of available address space become RAM When the register bit is set to 0 the first 8K of addressing space become ROM and the remaining 24K are RAM At power up or after a reset the register bit is set to 0 Table 11 Map register write access ADR4 ADR3 ADR2 Meaning 00 0 0000 OFFFH is 00 1 0000H OFFFH is RAM We remind that 1000H 7FFFH are always RAM 2 6 main edge connector The main edge connector is the standard DIN 41612 see the table for the pins assigne ments Table 12 Main edge connector Pin Row A Row C 1 adr6 adr5 2 adr4 adr7 3 n c 11 4 adr10 5 n c adr9 6 VCC VCC 7 adr14 adr13 8 n c CpuCLK 9 n c adr12 10 n c adr3 11 n c adr8 12 13 40 14 41 15 2 16 3 17 d4 18 n c d5 19 n c d6 20 n c d7 21 n c adr0 22 23 n c opreq 24 n c negR W 25 n c WRP 26 n c MnegI
37. ta and control lines are definitely valid the fact is OPREQ goes high BEFORE the clock can do so this gives us a bit of time for settling of the signals theStrobe lt theClock and OPREQ remember NOTHING is valid until OPREQ 71 first4KMem lt 0 when MNEGIO 1 and ADR14 0 and ADR13 0 and ADR12 70 OPREQ 1 else 1 ADR13 is ALSO EnegNE 1 extended 70 NOT extended ADR4 ADR3 00 map latch writeToData lt 1 when MNEGIO 0 AND theStrobe 1 and EnegNE 1 and ADR3 0 and ADR4 70 else 0 fundamentally latch ADR2 on the rasing edge of that this shit because we do not have any data line available to latch so we latch ADR2 instead THEfirst4KBIT process MRESET writeToData begin if MRESET 0 then first4KBit lt 0 at reset it must be rom elsif writeToData event and writeToData 1 then first4KBit lt ADR2 end if end process now as simple as possible the rom ram OE WE signals 27 ROMOE lt theRomOE this combination already includes MNEGIO and OPREQ theRomOE lt 0 when first4Kbit 0 and first4KMem 0 and OPREQ 1 else 71 fundamentally MNEGIO 1 and OPREQ 1 memory access of any kind isTheRam lt 0 when theRomOE 1 and MNEGIO 1 and OPREQ 1 else 1 that s RAMOE RAMOE lt isTheRam or and that s RAMWE RAMW
38. ternal 12 divisor counter present inside the CPLD 2 3 3 uart interfacing A closer look at the 6850 timings shows that it s possible to connect it directly to the 562650 by simply supplying it with a inverted NOT clock in such a way it turns out its bus timings are going to coincide with the SG timings provided that CPU clock and UART clock are the same frequency 2 3 44 uart TX and RX lines After the TTL to RS232 translator the transmit and receive lines are routed to connector CON with the following pinout Table 7 CON2 pinout Pin Signal Direction 1 Flag Output RS232 level 2 Sense Input RS232 level 3 GND Ground 2 4 The IDE interface An IDE interface is present on board this allows IDE PATA devices to be connected to 1 The IDE interface is designed to support PIO mode only I O no support for DMA and is fundamentally a reworked P R I D E interface The CPLD posses two registers called IDE Low Byte and IDE High Byte the access modalities are the usual ones In the case of a WRITE operation first the IDE High Byte register has to be written followed by a write on the IDE Low Byte register with ADRO ADR2 containing the value of the IDE register you wish to use Table 8 IDE Write Cycle Action Effect 1 Extend I O write on HI register Data HI is latched 16 bits data HI LOW ready 2 Extend I O write on LOW register ADRO 2 selects IDE register
39. to get a 50 duty SHAPER process tmpZero negreset begin if negreset 0 then tmpclk lt 0 elsif tmpZero event and tmpZero 1 then tmpclk not tmpclk end if end process 50 duty cycle clkout lt tmpclk end Behavioral library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL use IEEE STD LOGIC MISC ALL Uncomment the following library declaration if instan any Xilinx primitives in this code library UNISIM use UNISIM VComponents all entity G2650 Logic is Port IDE Interface control signals IDE RD out 3 STD LOGIC WR out STD LOGIC out STD LOGIC out STD LOGIC out STD LOGIC out STD LOGIC out STD LOGIC out STD LOGIC BDIR out STD LOGIC Main oscillator Clock divided to get the INCLK in STD LOGIC R12 in STD LOGIC R13 in STD LOGIC R14 in STD LOGIC R2 in STD LOGIC R3 in STD LOGIC ADR4 in STD LOGIC UART 6850 chip sel R W and E lines UARTSEL out STD LOGIC UARTRW out STD LOGIC UARTE out STD LOGIC Baudrate 1 8432 Mhz clock in BAUDCLK in STD LOGIC Baud 16 clock out BAUDCLK16 out STD LOGIC Ram Rom control signals OE and WE ROMOE out STD LOGIC RAMOE out STD LOGIC RAMWE out STD LOGIC Cpu control signals MNEGIO in STD LOGIC WRP in STD LOGIC e p A B N Co Hd HH Ho Ho
40. tra lodi stra bcta loda subi stra bcfa rede andi betr rede nop nop nop bctr lodi stra lodi stra bsta bcta phasel comi bcfr UN UN RO RO RO RO UN UN RO XM ResetPtr 1 X Phase 2 X CntTwo no timeout X CanCnt 1 X_CanCnt no timeout UARTS RDRF end tr2 H UARTRX x abort hi abortmsg MsgHi lo abortmsg MsgLo WriteMsg prompt gt 1 x phase2 reset pointers phase 1 now two bytes in here pkt num and 255 pktnum we have to get continue to read chars we got a CAN let see how many CAN counter if it s not zero let s read more let s check the UART status any char in the RX buffer if not stop thrashing read and thrash chars waste a bit of time continue to trash save address of message write the abort message go back to prompt exit xmodem loader if it s not 1 could be 2 here in phase 1 we have to get 2 bytes pktnum and 255 pktnum FT loda subi stra bctr rede stra RO RO RO RO RO data crc X CntTwo 1 X CntTwo got num UARTRX n X CurPknum we got both bytes get what we got save it temporary here i e packet 0 it will get overwritten 43 got num go two bcta rede eora comi bcfa lodi stra bcta UN phase x phase2 loda bcfr E loda is HI comi bcfr is
41. tures of the completed card showing jumpers locations 46 Figure 9 The board components side ES 47 Figure 10 The board solder side note the corrections done with wire EEE 48 9 Disclaimer and License This project been done entierely as an hobby with absolutely NO COMMERCIAL APPLICATION OR INTENT whatsoever there is absolutely NO INTENT of making any money out of it This project also been developed during my little free time as a work of passion and love for retrocomputing and old hardware it s been made at best but don t expect it to be perfect or faults free I assume NO responsibility of any sort for damages and or any improper use of this documentation feel free to browse it and have fun and interest as much as I do but please accept it as it is My hope is all this can be inspirational to others to continue the study and presevation of interesting technology For the sake of clarity I declare this work to be under the Creative Commons Attribution NonCommercial 4 0 International CC BY NC 4 0 check the Creative Com mons website http creativecommons org if you need details about what this means 49
42. write the boot message end go back to prompt and counters let s rememebr a packet is soh stx blk 255 blk data 128 or 1024 crc lt crc gt sum all data ONLY XM ResetPtr lodi RO 0 stra RO X Crc Stra R0 X ByteCntL Stra R0 X ByteCntH reset CRC high bytes counter as well 45 loda RO X OneK bctr EQ is 128 we are using 128 bytes lodi RO 04h stra RO X ByteCntH otherwise is 400h bytes bctr UN set ptr go on with the rest is 128 lodi RO 128 otherwise just set the low counter to 128 Stra R0 X ByteCntL low bytes counter too set ptr loda R0 X AdrHi stra RO X CurAdrHi loda RO X AdrLo stra RO X CurAdrLo X CurAdr X Adr retc UN unconditional return The various messages bootmsg db db db Qu o m crlf 0 m help Qi Oi C ooocooooooct o abortmsg db db loadok db db db Gr LE Signetics 2650 CPU Board 1Mhz Cr C 2012 Ivan Z Llamasoft er l BootLoader Version 5 02 Cr LE 0 shows help D lt aaaa gt _dumps memory cr lf A lt gt alters memory to exit cr lf L aaaa XMODEM 1oads data X CAN cr lf aaaa jumps to address cr lf lt aaaa gt _hexadecimal_16 bits address cr lf 0 Transfer aborted cr lf 0 cr lf Data loaded OK cr lf 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 8 Card pictures Here pic

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