Home

Laboratory Experiment 7 EE348L

1. University of Southern California EE348L page24 Lab 7 Figure 7 17 HSpice netlist for obtaining I V characteristic of a p channel MOSFET MBS250 El i i e aa a ee eee G a ee a 5 B par id Ovgate 0 0 par id 0 vgatez 1 Vsg 3V lt Vth par id Ovgate 2 Vsg 4V 150m Vsg 5V n l 0 7 pU uq o0 00 07 0T qm 00 o 07 007 5 m 05 00 00 To ou T To Tot B Figure 7 18 iD vDS characteristics of MOSFET x1 in Figure 7 11 for source to gate voltages of 3V 4V and 5V 7 8 Conclusion The MOS canonic cells were presented in laboratory experiment 6 These cells are the fundamental building blocks of analog integrated circuit design This lab focused on using the canonic cells in combination to overcome their inherent limitations when used as a single cell Thus when doing circuit analysis one may always break down a circuit topology into the canonic cells in order to obtain insight into the design of a circuit An advanced understanding of these basic building blocks will allow a circuit designer to effectively use canonic cells to overcome their individual limitations and satisfy the largest possible subset of circuit design specifications 7 9 MOSFET Spice model for PMOS transistor BS250P Note that the spice model for the discrete p channel MOSFET used in this laboratory experiment BS250P utilizes a subcircuit definition which includes a first order PMOS model deck SUBCKT BS250P drain gate source MI drain gatel source source
2. Sons Inc New York 1981 9 Paul R Gray amp Robert G Meyer Analysis and Design of Analog Integrated Circuits John Wiley amp Sons Inc New York 1993 University of Southern California EE348L page27 Lab 7 7 12 Pre lab Exercises Note For Spice simulations use the model deck for 2N7000 in Figure 7 9 and the model deck for BS250P in Figure 7 11 Submit plots relevant to each question in your lab report Note The 2N7000 and BS250P are not small geometry devices so the approximation of large small signal drain to source resistance in the saturation region rds is normally valid Device Specifications Caution Never exceed the device maximum limitations during design 2N7000 Idmax 200mA Vdsmax 60V Vth 0 8V BS250P Idmax 250mA Vdsmax 45V Vth 1V 1 Confirm in Spice See the note at the bottom of page 6 that for Ip of the 2n7000 less than 100uA the transistor is in the subthreshold operating region as discussed in the common source design example in section 7 2 2 Simulate the design example for the common source amplifier with Rl 1e6 100k 10k Use an ac sweep A What happens when Rl is larger than the designed value of 10k Why B If we were to repeat this design for the load resistance being the gate of another transistor what should we set RI to 3 Design a common source amplifier Figure 7 1 in HSpice See section 7 2 for design example with source degeneration resistance which has the
3. 7 11 was increased by using the low frequency small signal resistance of a MOSFET current mirror as shown in Figure 7 14 which is much higher than the resistance that can be realized with a typical on chip passive resistor However this assumes that the drain to source or output resistance rds of a MOSFET is very large As device geometries become smaller this assumption begins to fail This next section will deal with what is known as a cascode configuration which is a cascade of the common source and common gate canonic cells that increases the drain to source resistance of a MOSFET 7 6 2 Active load cascode configuration Vig R Rout l I I PF V I M 4 J E Ry M C Figure 7 15 Common source cascode University of Southern California EE348L page21 Lab 7 The cascode configuration is shown in Figure 7 15 Going back to laboratory experiment 6 one can see that this cascode configuration is nothing more than a common gate that has been stacked on top of the common source amplifier Since we have derived the small signal transfer function of each canonic cell we should be able to calculate the small signal transfer function of the overall amplifier by inspection The new output resistance should be calculated by replacing each transistor with its ac small signal model Both of the above are left as pre lab exercises The cascode configuration has a couple of advantages over the traditional common source amplifier As
4. Figure 7 11 and Figure 7 12 for values of RL varying from 100kQ to 100Q As can be seen the cascade amplifier is able to provide gain to small loads University of Southern California EE348L page17 Lab 7 1 i 0 100 me ik i 1 Gd 100k 1M 10M 100M 1G FRENTE 4 ij n B par gaindbjri 100000 1120 8 E lon ug m EM par gaindb ri 10000 laif 20 8 H aa par gaindb ri 1000 i557 20 7 par gaindb r 100 lab 19 6 107 2011 Aor MM MM M i i i i E m i em i og 10 100 1k 10 4k 100k 1M 10M 100M 1G Figure 7 11 AC simulation for the design example of the source follower amplifier The mid band gain ranges from 20 8dB to 19 6dB for 100kQ to 100Q loads 2qu 4Qu equ epu 100u 120u 140u 160u 180u 200u 7 PO TE fo acacacacd o O O O a a E aca sacas a a aaa ma S O OT Bv outyri 100000 lab 544m l i i i v outyri 10000 lab 543m v outyri 1000 lab7_4537m v outyri 100 i457 5 483m By vin lab 3110 46Om n i 1 i 1 1 H 1 1 i 1 H 1 A 1 1 H 1 1 i H H ji H Y T j T n 3j r3 ee eC C O Se 3331433339934 730 330 in 20u 40u 60u 75uls0u 100u 120u 140u 160u 180u 200u Figure 7 12 Transient simulation for the design example of the source follower amplifier The gain ranges from 10 9 to 9 7 for 100kQ to 100Q loads No clipping can be seen University of Southern California EE348L page18 Lab 7 7 6 Hi
5. following specifications A Supply voltage of 10 V bonus points if you achieve specification with lower supply voltage between 5V and 8V B small signal gain gt 25 dB between 1kHz and 100kHz that can support a an ac coupled load resistance as low as RL 10 KQ Your answer should indicate 1 How you arrived at the dc operating point of the common source amplifier ii How the component values were chosen lil Show that the calculated small signal gain is in good agreement with that obtained from your Spice simulations iv Submit the results of both ac and transient simulations for 100kQ 10kQ 1kQ and 100Q For the transient simulation use a 50mV peak to peak sinusoidal input at 10 KHz Does the gain inferred from the transient simulation agree with the gain obtained from the frequency response small signal simulation in Spice Why or Why not NOTE Make sure your transistor is operating at above threshold 4 Design a common source common drain cascade as shown in Figure 7 9 in HSpice See sections 7 3 and 7 4 for design examples which has the following specifications A Supply voltage of 10 V bonus points if you achieve specification with lower supply voltage between 5V and 8V B small signal gain gt 25 dB between 1kHz and 100kHz that can support a an ac coupled load resistance as low as RL 100Q C Variation in mid band small signal gain due to variation in road resistance from 100Q 100kQ is no more than 5dB You
6. is impacted by circuit components In this section we will look at the systematic procedure for biasing a common source amplifier for a given set of design criteria The common source amplifier can be seen in Figure 7 1 The following are the design criteria Voltage gain A 20dB 10 Vdd 10V RI As low as 10kQ No clipping is allowed University of Southern California EE348L page4 Lab 7 Figure 7 1 Common source amplifier with variable load impedance RL The first thing we do is to set Vp to Vdd 2 so as to minimize the chance of any clipping V Vdd I R 7 1 We then solve for Rp from the gain equation gm R RI gm R RI A 7 2 1 gmRss 1 gmRss R p tRI This leads to R ARI 1 gmRss 7 3 gmRI A 1 gmRss We then plug this back in to equation 7 1 to get Al RI R Se d 14 2 gmRI A 1 gmRss Which leads to University of Southern California EE348L page5 Lab 7 Vdd AI RI 1 gmRss 2 gmRI A 1 gmRss 7 5 Now we use the following relationship between Ip and gm W gm gm 42Kn I Or n W 7 6 2Kn L Plugging this into equation 7 5 leads to the following second order equation in terms of gm Vdd Agm RI 1 gmRss 2 7 7 2Kn rs gmRI e A gmRss Using equation 7 7 we can solve for gm in terms of A RI Vdd and Rss The first three values are given to us while Rss can be chosen NOTE If A RI Vdd and Rss are not chos
7. sd 1 3k Figure 7 2 DC sweep for Rb2 to get Vss equal to 132V t T T T r i np lin 1k 14k 15k From the plot we see that for Rb2 1 23kQ we get a Vss of 132 or a drain current of 264uA Now we have our finalized design Rb1 10k Rb2 1 23k Rss 500 Rp 18 94k Ip 264mA Vgz1 095V Vss 132V The next step is to perform ac and transient analyses with a sin wave with amplitude of 50mV and a frequency of 10 kHz These are plotted for this design example in Figure 7 3 and Figure 7 4 The ac sweep is to verify the gain over frequency we desire The transient sweep is to verify the amplifier does not go out of saturation or clip NOTE Be sure to pay attention to the relationship between Rp and RI If you get a solution such as Rp 30k and RI 10k then Rp is a lot larger than RI R is affecting your gain more than Rp In this case if you need to increase your gain you would be better off reducing Rp while increasing Ip than vice versa University of Southern California EE348L page7 Lab 7 NOTE It is good practice to design your circuit to BEAT the design criteria as opposed to MEET design criteria That way you have wiggle room incase your circuit does not operate exactly as expected o LS s z 100k par gaindbyri 10000 i557 19 7 A 3 ee Ta ee TT i T T x 1 l 10 100 dk Figure 7 3 AC simulation for the design example of the common source amplifier The mid band gain is approxi
8. too small We can use the value for Kn that we found in pre lab exercise 1 which should be roughly 250 uA V 2 The gate aspect ratio of these transistors is 3 200 This yields the result University of Southern California EE348L page11 Lab 7 iss ae aa V V These solutions lead to Ip 19 2mA Ino 129 6mA NOTE We will choose the first solution since it provides us with less bias drain current This means we will consume less power to achieve our performance specs We can then find Rss2 by Vdd Vo E TR oo 2 Which yields R 260 4 As can be seen Rp does not affect this circuit performance It can be removed unless Vds of M2 becomes too large The next step is to find what Vgs is necessary to produce 19 2mA of current through the transistor This can be done by choosing a value for Rb3 and varying Rb4 until we get Vss2 5V You will use a potentiometer to do this in the lab and a DC sweep in HSpice for the pre lab Figure 7 6 shows the dc sweep for Rb4 with Rb3 10k that produces a Vss2 5V University of Southern California EE348L page12 Lab 7 JA MANC A PS C MEM v source1 lab 5 j i Pd i A i A i got 54 i oA i a i m id i y i i zT l ar 1 i P i P 52 1 ze i i i i L i F i i Pi i i b 5 E Ld i i i Pd i i i 48 i i i i i F 1 i i i i 46 i H i i 1 i id r Y i r i r r r i Y r r r i r r r r 1p lin E 16k 18k
9. with dc blocking capacitors Cc and Cc2 isolating the dc potentials at the gate and drain terminals of M2 from that of the signal source and that of the load Now we want to design the source follower to achieve the following design criteria Voltage gain A2 1 94dB 8 Vdd 10V University of Southern California EE348L page10 Lab 7 RI As low as 100Q No clipping is allowed The first thing we do is to set V to Vdd 2 so as to minimize the chance of any clipping Vss2 Roo 7 1 We then solve for Rss from the gain equation Em2 R R gm R RI A2 7 2 1 Em2 R R R RI gmR Rl This leads to A2RI 552 7 3 A2 gmRI A2 1 We then plug this back in to equation 7 1 to get Vdd A2I RI 2 A2 gmRI A2 1 7 4 Now we use the following relationship between Ip and gm W gm gn 42Kn I or Ip W 7 6 2Kn L Plugging this into equation 7 5 leads to the following second order equation in terms of gm Vdd A2gm RI 2 7 7 7 2Kn A2 gmRI A2 1 Using equation 7 7 we can solve for gm in terms of A2 RI and Vdd All of these values have been given to us NOTE If A2 RI Vdd are not chosen properly we will get only negative or imaginary solutions to the second order equation This means the circuit topology will not work In other words this circuit will only work if A2 is not too big RI is not too small and Vdd is not
10. you should find out in the pre lab the output resistance Rout in Figure 7 15 is increased especially for short channel devices with gate length lt lum Consequently the gain of the overall circuit is increased Another benefit is achieved from a speed perspective The common gate stage reduces the Miller multiplication of the gate to drain capacitance Ced of transistor M seen by the source Vs The Miller Effect occurs when a capacitor is connected between two nodes one of which experiences inverting gain with respect to the other This increases the effective capacitance seen at the input by a factor of one plus the gain In a traditional common source configuration such as Figure 7 13 there isn t an explicit capacitor between the gate and drain terminals of the MOSFET M1 However the MOSFET small signal model has a parasitic gate drain capacitance Cgd associated with it Also from laboratory experiment 6 it is known that a common source amplifier has a gain of gy R between the gate and drain Therefore the effective capacitance seen by the input to the common source amplifier Figure 7 13 is Cy C ualt g R 1 3 where R is the effective load resistance at the drain Hence one can now see that the time constant associated with this node has increased and will effectively slow the circuit down In a cascade configuration R 1 gm2 since the load at the drain of M1 is looking into the source of M2 Therefore the Miller Multip
11. 19 2k 20k 22k 24k Figure 7 6 DC sweep for Rb4 to get Vss2 equal to 5V From the plot we see that for Rb4 19 2kQ we get a Vss2 of 5 or a drain current of 19 2mA Now we have our finalized design Rb3 10k Rb4 19 2k Rss2 260 4 Rp 0 Ip 219 2mA Vg2 6 56V found using HSpice Vss2 5V The next step is to perform ac and transient analyses with a sin wave with amplitude of 50mV and a frequency of 10 kHz These are plotted for this design example in Figure 7 7 and Figure 7 8 The ac sweep is to verify the gain over frequency we desire The transient sweep is to verify the amplifier does not go out of saturation or clip University of Southern California EE348L page13 Lab 7 pig OOK cou eM MOOM steel pangaindb labz 2aco 195 f 1 i 10 E EE 40 log 1 a ds i t 1034 unm i i 10M 100M MS Figure 7 7 AC simulation for the design example of the source follower amplifier The mid band gain is approximately 1 95dB Lacu a 298 509 tO iu QU Vu DU teu 1 200u vivoutyri2 100 lab7_2 tr 39 4m f y vin lab 2 10 50m H f H ee G E merer eere m r in ie 20124 9u 40u 60u 80u 100u 120u 140u 160u 180u 200u Figure 7 8 Transient simulation for the design example of the source follower amplifier The gain is approximately 79 No clipping can be seen University of Southern California EE348L page14 Lab 7 7 4 A systematic procedur
12. LLLLLLLLLLLELLLLLLLLLLLLLLLLLII xk subcircuit definition LLELLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLII SUBCKT BS250P drain gate source MI drain gatel source source MBS250 RG gate gatel 160 RL drain source 1 2E8 C1 gatel source 47E 12 C2 gatel drain 10E 12 D1 drain source DBS250 MODEL MBS250 PMOS VTO 3 193 RS 2 041 RD 0 697 IS 1E 15 KP 0 277 CBD 105E 12 PB 1 LAMBDA 1 2E 2 MODEL DBS250 D IS 2E 13 RS 0 309 ENDS BS250P LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLELLLLLLLII circuit description LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLII x1 drain gate source BS250P LLLLLLLLLLLLLELLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLELLLLLLLII sources section 2 2k of of oft of of 2s 2 oft oft oft K K K of of of of oft oft K K of of of oft oft K K K K oft K oft K K K K K K K KK K K K K ok ok ok ok K K Vdrain drain 0 5 Vdd vdd 0 5 Vgate gate 0 5 LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLELLLLLLII probe section LLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLELLLLLLLII probe dc id par id x1 m1 LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLELLLLLLII specify nominal temperature of circuit in degrees C LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLII TEMP 27 LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLII analysis section LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLII dc vdrain 0 5 01 sweep vgate po130 12 END
13. Laboratory Experiment 7 EE34SL Aaron Curry University of Southern California EE348L pagel Lab 7 Table of Contents 7 7 1 72 1 3 7 4 7 5 7 6 7 6 1 7 6 2 7 7 7 8 7 9 7 10 7 11 7 12 7 13 Experiment 7 MOSFETS Continued ecce cete eee eee ee eren ee eee seen netta 4 WtrO MUCH OM HEP IE 4 Asystematic procedure for biasing a common source amplifier eese 4 A systematic procedure for biasing a source follower amplifier sess 9 A systematic procedure for biasing a common source source follower cascade amplifier 8 Verification of the systematic procedure for biasing a common source source follower cascade amplifiet coser GRE ERR ost OR RERO Eaton d Og egy 13 High gain amplifiers aic e e ete teet tendere opes 16 Activelloadu zoe o ER EE ER ERE SERE NE IR are EO UU Dee tude 19 Active load cascade configuration cssssssssssssssssssssssseeee nemen 2 HSpice simulation of discrete p channel MOSFET BS250P csseseeeeeee 23 CONCIUSION MP MOSFET Spice model for PMOS transistor BS250P 0c cece scence eect ee nett ene eneee en 25 Revision History 3 dec de e OO ee ee 26 References cune tede AE E AET E E EA EE a 27 Pre lab Exercises ene e reet ER ESSERE EERE E E ka 28 EAD BX etCIs6S uri e edet e Eee eter e PR e He Rut Pe cext rue Pea eet agi 30 University of Southern California EE348L
14. MBS250 RG gate gatel 160 RL drain source 1 2E8 C1 gatel source 47E 12 C2 gatel drain 10E 12 D1 drain source DBS250 MODEL MBS250 PMOS VTO 3 193 RS 2 041 RD 0 697 IS 1E 15 KP 0 277 CBD 105E 12 PB 1 LAMBDA 1 2E 2 University of Southern California EE348L page25 Lab 7 MODEL DBS250 D IS 2E 13 RS 0 309 ENDS BS250P In order to use this device in an Spice netlist the above subcircuit is defined before the start of the circuit description Then a subcircuit call is used to instantiate the BS250P in the SPice netlist as shown below X1 drain gate source BS250P D G S E Line TO92 Compatible Figure 7 19 Pin diagram of the BS250P Courtesy of Zetex 7 10 Revision History This laboratory experiment is a modified version of the laboratory experiment 7 MOSFETS Continued by B Madhaven which was a revision of experiment 7 MOSFET Dynamic circuitsII created by Jonathan Roderick University of Southern California EE348L page26 Lab 7 7 11 References 2 HSpice user manual posted on EE348L class web site 5 Adel Sedra and K C Smith Microelectronic Circuits fifth edition Oxford University Press 6 Ben G Streetman Solid State Electronic Devices Prentice Hall Inc Englewood Cliffs New Jersey 1990 7 Richard C Jaeger Introduction to Microelectronic Fabrication Addison Wesley Publishing Company Reading Massachusetts 1993 8 S M Sze Physics of Semiconductor Devices John Wiley amp
15. Regens 17 Figure 7 11 AC simulation for the design example of the source follower amplifier The mid band gain ranges from 20 8dB to 19 6dB for 100kQ to 100 loads 18 Figure 7 12 Transient simulation for the design example of the source follower amplifier The gain ranges from 10 9 to 9 7 for 100kQ to 100Q loads No clipping can be seen 18 Figure 7 13 Schematic diagram of a common source amplifier eee 19 Figure 7 14 A common source amplifier with an active load sees 20 Figure 7 15 Common source cascode cceccecssesssessecesceseceeceeeceeesecaaeceaeceaeseeeeeaeeeaecaeceseceeeeeeeeeeeeeaeenaees 21 Figure 7 16 Common source cascode with cascode current mirror essere 23 Figure 7 17 HSpice netlist for obtaining I V characteristic of a p channel MOSFET MBS250 25 Figure 7 18 iD vDS characteristics of MOSFET x1 in Figure 7 11 for source to gate voltages of 3V 4V and 5V M Wed a a ewe EE Figure 7 19 Pin diagram of ihe BS250P Courtesy of Zetex w O 26 University of Southern California EE348L page3 Lab 7 7 Experiment 7 MOSFETs Continued 7 1 Introduction Laboratory experiment 6 introduced the MOSFET canonic cells used in MOSFET amplifier design The ac small signal model was presented for each canonic cell and was used to discuss its performance What the previous lab didn t clearly pres
16. ave the proper drain current Build the cascade amplifier you designed in pre lab question 4 Verify and record your results for load resistances of 100kQ 10kQ 1kQ and 100Q for a 10 kHz sine wave with amplitude 50mV Do your results agree with you Spice results Why or why not For a 100Q load record any changes in gain when you increase the sine wave amplitude to the 100mV 200mV and 400mV Does your output clip Hint You can use a potentiometer for Rb2 to ensure Id1 is at the desired value however there is no way to adjust the gate of M2 to ensure Id2 is at the desired value Instead Rss2 can be adjusted if needed Build the circuit from Figure 7 14 Let Reff be 1k Vdd be 5V and do not use a load capacitance Use a potentiometer for the bias circuitry Rb2 of transistor M1 and adjust it until the output sits at Vdd 2 How sensitive is the output voltage to the bias scheme of M1 After you get the output as close to Vdd 2 as you can simulate with an input sinusoid with frequency of 10kHz and amplitude of 50mV What is the gain of this amplifier What happens as you increase the input amplitude University of Southern California EE348L page30 Lab 7
17. ction LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLDLLLLLLLLLLLLLLLLLLLLLL vdd vdd 0 10V vs vin 0 ac 1 sin OV 50mV 10k LLLLLLLLLLLLLELLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLELLLLLLLII specify nominal temperature of circuit in degrees C LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLELLLLLLII TEMP 27 LLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLLLLLLLII probe section LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLELLLLLLLII probe ac gaindB par 20 log10 v out LLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLLLLLLLLII analysis section LLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLLLLLLLII Op dc rb2 1k 2k 01k ac dec 100 1 1G sweep RI poi 4 100k 10k 1k 100 tran lu 200u 0 lu sweep RI poi 4 100k 10k 1k 100 LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLII models section LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLDLLLLDLLLLLLLLLLLLLLLLLLLII this Model is from supertex com MODEL nmos2N7000 NMOS LEVEL 3 RS 0 205 NSUB 1 0E15 DELTA 0 1 KAPPA 0 0506 TPG 1 CGDO 3 1716E 9 RD 0 239 VTO 1 000 VMAX 1 0E7 ETA 0 0223089 NFS 6 6E10 TOX 1 0E 7 LD 1 698E 9 UO 862 425 XJ 6 4666E 7 THETA 1 0E 5 CGSO 9 09E 9 2N7002 MODEL end Figure 7 10 Spice netlist of the cascade of common source and source follower amplifier in Figure 7 9 The simulation results of the ac and transient responses of the cascade of common source and source follower amplifiers in Figure 7 9 using the netlist in Figure 7 10 are shown in
18. e for biasing a common source source follower cascade amplifier We now want to cascade the two amplifiers so that we can get gain from the common source amplifier and then buffer the output voltage with a source follower amplifier The schematic can be seen in Figure 7 9 Figure 7 9 Cascade of common source amplifier with source follower amplifier The first thing that we see is that the load resistance of the common source amplifier is infinity since the load is the gate of transistor M2 Therefore we can redesign our common source amplifier with less stringent design criteria The second thing that we see is that we designed the common source amplifier for a Vp of 5V and we designed the source follower for a Vss2 of SV This will not work since it would put Vgs of M2 at OV We need to either increase the drain voltage of M1 decrease the source voltage of M2 or both Our HSpice simulation from our source follower design gave us a Vgs of M2 of 1 57V Thus lets split the voltage across both transistors and let Vp of M1 be 5 8V and Vss of M2 be 4 2V Our overall design criteria are listed below Voltage gain A 20dB 10 Vdd 10V RI As low as 100 No clipping is allowed Our common source amplifier has the following design criteria Voltage gain Al A A2 10 8 12 5 Vdd 10V RI infinity Voi 5 8V University of Southern California EE348L page15 Lab 7 No clipping is allowed Our source follower has the fol
19. en properly we will get only negative or imaginary solutions to the second order equation This means the circuit topology will not work In other words this circuit will only work if A is not too big Rl is not too small Vdd is not too small Rss is not too big We can use the value for Kn that we found in pre lab exercise 1 which should be roughly 250 uA V 2 The gate aspect ratio is 3 200 for these transistors By letting Rss be 5000 we get the following result mA mA m 6 5 m 2 3 2 V 2 V These solutions lead to Ij 264mA Ip 33uA NOTE The second solution Ip 33uA is not a valid solution because it implies that the transistor is in the subthreshold operation region This can be found by plotting log Ip VS Vgs while keeping the transistor saturated and finding where the plot leaves the linear region This happens at about Ip 100uA We can then find Rp by V Vdd I R Which yields R 18 94kQ University of Southern California EE348L page6 Lab 7 The next step is to find what Vgs is necessary to produce 264uA of current through the transistor This can be done by choosing a value for Rb1 and varying Rb2 until we get Vss IpRss 264uA 5000 132V You will use a potentiometer to do this in the lab and a DC sweep in HSpice for the pre lab Figure 7 2 shows the dc sweep for Rb2 with Rb1 10k that produces a Vss 132V qe I Rg gE Ig source 1 132m 1 1 r1 250m H 2 150m 1 1k 12k
20. ent are the limitations of the canonic cells These limitations are one reason why circuits don t comprise of just a single stage that incorporates a single canonic cell An integrated circuit amplifier doesn t consist on just one common source amplifier To be sure a common source canonic cell s may be used in the amplifier topology but other elements and canonic cells are also used to address the performance limitations of the amplifier Another example is the voltage buffer A voltage buffer in an integrated circuit design doesn t consist of a single common drain source follower canonic cell As you probably discovered in the previous lab the gain of a common drain source follower amplifier is less than unity and depending on the MOS technology used it can be considerably less than one This lab will present ways to combine the canonic cells in order to overcome certain inherent limitations of a single cell The design strategies and topologies presented here are not comprehensive of all the possible solutions known to overcome the limitations of MOSFET amplifiers However they should give you insight into how to approach practical problems in MOSFET analog integrated circuit design 7 2 A systematic procedure for biasing a common source amplifier In laboratory experiment 6 we simply calculated the gain of the common source amplifier without doing any design procedure However we familiarized ourselves with the gain equation and how it
21. gh gain amplifiers 7 6 1 Active load A common desire a circuit designer faces is to get more gain out of a common source amplifier One reason is the relatively low transconductance associated with a MOSFET as compared to a bipolar transistor A common source amplifier is shown below in Figure 7 13 Via Figure 7 13 Schematic diagram of a common source amplifier From the previous lab it was shown that a common source amplifier has gain V Ay Sy Tne 7 1 This is assuming that the drain to source resistance rds of the MOSFET is much greater than R If it isn t than the net effective resistance is the parallel combination of the resistor R and the drain source resistance of the device The transconductance gm of a MOSFET is defined as W Bau 2k we From these equations it can be seen that the only gain variables that a circuit designer has control over are the load resistance R the drain bias current IDQ and the gate aspect ratio or size of the transistor W L 7 2 University of Southern California EE348L page19 Lab 7 In integrated circuit design a resistor is not usually a passive element as depicted in Figure 7 13 Active devices usually realize resistances Large on chip passive resistance takes up much more area than a resistance realized by using an active device We can attempt to maximize the amount of gain that can be realistically obtained from the circuit topology in Figure 7 13 by making the sma
22. lication is reduced In short channel devices the output resistance associated with a transistor is much smaller than in long channel devices Therefore using cascode topologies is necessary in order to achieve a large output resistance In order to have a balanced cascode circuit in Figure 7 15 we would append the cascode current mirror where resistance R is located which is shown in Figure 7 16 University of Southern California EE348L page22 Lab 7 Figure 7 16 Common source cascode with cascode current mirror 7 7 HSpice simulation of discrete p channel MOSFET BS250P Figure 7 17 is an example of a netlist that can be used to plot the iD vDS characteristics of the MOSFET BS250P specified by the subcircuit named BS250P in section 7 9 We use a subcircuit University of Southern California EE348L page23 Lab 7 definition because we do not have a properly characterized model deck for the BS250P from the manufacturer that accounts for all aspects of its behavior The drain to source voltage VDS is swept from OV through 10V in steps of 0 01V at gate to source voltages VGS of 2 V 10 V 8V 4V 10V 6V and 6V 10V 4V The Spice simulation results are shown in Figure 7 18 PMOSFET I V characteristic for BS250P Written May 1 2013 for EE348L by Aaron Curry LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLELLLLLLII xk options section LLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLELLLLLLII opt post LLLLLLLLLLLLLELLLLLLLLLLLL
23. ll signal resistance as large as possible This can be done replacing the drain resistance R in Figure 7 13 with a PMOS version of the current mirror that was presented in laboratory experiment 5 as shown below in Figure 7 14 Figure 7 14 A common source amplifier with an active load Note It can be seen in Figure 7 14 that the PMOS current mirror uses a passive resistor Reff to establish the reference current Iref needed to bias the common source amplifier Normally another NMOS transistor that is either diode connected or biased with a dc voltage is used to present the required amount of resistance For the purposes of this explanation it will be left as an effective resistance Reff The current mirror formed by PMOS transistors M2 and M3 are correctly biased by appropriate choice of current Iref resistor Reff and device sizes if applicable of M2 and M3 University of Southern California EE348L page20 Lab 7 One may recognize that the small signal output resistance of the topology feature in Figure 7 14 Rout is nothing more than the parallel combination of the output resistance of MOSFET M0 and that of MOSFET M1 This derivation is left as a pre lab exercise As stated before a passive on chip resistor consumes a great deal of area and its resistance is proportional to that area Thus high value on chip passive resistors are extremely inefficient from a layout area standpoint The gain of the common source canonic cell Figure
24. lowing design criteria Voltage gain A2 8 Vdd 10V RI as low as 100 Vss2 4 2V No clipping is allowed Repeating the systematic procedure from sections 7 2 and 7 3 we get the following values Rb1 10k Rb2 1 46k Rss 1 500 Rp 7 61k Rss2 156 Rpo 1 Ip i2 55mA Ip 27mA Vglz1 27V Vssl 275V 7 5 Verification of the systematic procedure for biasing a common source source follower cascade amplifier AC coupled Common Source Source Follower cascade amplifier Written 4 29 13 by Aaron Curry LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLII options section LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLII opt post LLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLLLLLLLLII circuit description LLLLLLLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLELLLLLLII rbl vdd gatel 10K rb2 gatel sourcel rb2 m1 drainl gatel sourcel sourcel 2N7000 W 0 8E 2 L 2 5E 6 rss sourcel 0 500 rd vdd drainl 7 61k ccl vin gatel 10uF source follower amplifier dc coupled rd2 vdd drain2 1 m2 drain2 drain source2 source2 nmos2N7000 W 0 8E 2 L 2 5E 6 rss2 source2 0 156 cc2 source2 out 10uF rl out 0 RI LLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLELLLLLLLLLLLLLLLLLLII University of Southern California EE348L page16 Lab 7 xk parameters section LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLDLL param RI2100k param rb2 1 46k LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELLLLLLLLLLLLLLLLLII sources se
25. mately 19 7dB T T T Tri Tri 3 10 1k 100k 1M 10M 100M 1G University of Southern California EE348L page8 Lab 7 p 2Qu 4Qu 6Qu epu 100u 120u 140u 160u 180u rT icem ere eect ee eer eet TUM PEN ene Sf oe Yee eB ici Ca me DN EG cor re Dee LEER L Ye ct Yea v voutyri 10000 476m By vin 50mqpri 03 0 3 n ie 20u 40u 60u 75ulgu mm oou iD 120u Srey 140 B 1600 n 180u uni Figure 7 4 Transient simulation for the design example of the common source amplifier The gain is approximately 9 52 No clipping can be seen 7 3 A systematic procedure for biasing a source follower amplifier In laboratory experiment 6 we saw that a common source amplifier does a poor job at voltage amplification due to its large output impedance however a source follower does a good job at sourcing voltage since it has a relatively small output impedance The effective load impedance seen by MOSFET M in Figure7 1 the frequency range of interest when ac coupling capacitor Cc2 is a short is given by RD ll RL As we saw in the previous lab RL does not affect the gain of the amplifier in Figure 7 1 as long as it is much larger than RD However as RL becomes comparable or smaller than RD the ac small signal gain of the amplifier in Figure 7 1 begins to decrease The ac small signal gain in Figure 7 1 is given approximately by A s x NE 7 8 In order to reduce the impact of varying load resistance on the small signal gain of the commo
26. n source amplifier in Figure 7 1 we need to insert a buffer stage between the drain of MOSFET M and the load resistance RL The output impedance of the buffer needs to be low so that the variation in RL does not affect the output impedance of the buffer Since the output of the common source University of Southern California EE348L page9 Lab 7 200u it mi 200u amplifier in Figure 7 1 is a voltage signal the buffer stage is a voltage in voltage out stage with high input impedance and low output impedance The canonic cell that has these characteristics is the source follower amplifier whose output impedance is approximately 1 gm but suffers from a gain that is at best close to 1 but always less than 1 A schematic of a source follower common drain amplifier is shown in Figure 7 5 M2 is a discrete n channel MOSFET device such as the 2N7000 used in this lab experiment The function of resistor RD2 is to limit the voltage at the drain of MOSFET M2 so that it does not enter into breakdown For low values of Vdd RD2 can be eliminated from the circuit schematic The ac small signal gain of the source follower amplifier in Figure 7 5 is given approximately by A e E m2 A R 7 9 1 8m Ro I R where gm2 is the transconductance of MOSFET M2 which is biased in saturation Now since RI appears in both numerator and denominator its affect on the gain is reduced Figure 7 5 Source follower amplifier schematic
27. page2 Lab 7 Table of Figures Figure 7 1 Common source amplifier with variable load impedance RL ess 5 Figure 7 2 DC sweep for Rb2 to get Vss equal to 132V cies ceseeseeseeeeceseseseeeseeeseeeeseaceeeeseeseaeeeeenseeeaeees 7 Figure 7 3 AC simulation for the design example of the common source DE The mid band gain is approximately 19 7dB e E Figure 7 4 Transient simulation for the design example of the c common source amplien The gain is approximately 9 52 No clipping can be seen sseseeee 9 Figure 7 5 Source follower amplifier schematic with dc blocking capacitors Cc and Cc2 isolating the dc potentials at the gate and drain terminals of M2 from that of the signal source and that of the load enne nennen 10 Figure 7 6 DC sweep for Rb4 to get Vss2 equal to 5V sess rennen nen 13 Figure 7 7 AC simulation for the design example of the source follower amplifier The mid band gain is approximately 1 95dB ssessessseeeeeeeeeeeeeene ener nennen 14 Figure 7 8 Transient simulation for the design example of the source follower amplifier The gain is approximately 79 No clipping can be seen seeeenee 14 Figure 7 9 Cascade of common source amplifier with source follower amplifier 15 Figure 7 10 Spice netlist of the cascade of common source and source follower amplifier in Figure 7 9 e pep peteret eo eet de er e e rae eene ee
28. r answer should indicate University of Southern California EE348L page28 Lab 7 1 How you arrived at the dc operating point of the common source amplifier ii How the component values were chosen lil Show that the calculated small signal gain is in good agreement with that obtained from your Spice simulations iv Submit the results of both ac and transient simulations for 100kQ 10kQ 1kQ and 100Q For the transient simulation use a 50mV peak to peak sinusoidal input at 10 KHz Does the gain inferred from the transient simulation agree with the gain obtained from the frequency response small signal simulation in Spice Why or Why not NOTE Make sure your transistors are operating at above threshold 5 Derive Rseen down of the common source cascode with active load in Figure 7 16 taking into account the small signal MOSFET drain to source resistance rds How much greater is it as compared to Rsee down of the traditional common source amplifier in Figure 7 14 Assume gm rds gt gt 1 6 Derive Rseen up of the cascode current mirror in Figure 7 16 taking into account the small signal MOSFET drain to source resistance rds How much greater is it as compared to Rsee up of the traditional current mirror in Figure 7 14 Assume gm rds gt gt 1 7 Derive the Rout of the common source cascade with active load in Figure 7 16 taking int o account the small signal MOSFET drain to source resistance rds How much greater is it as compa
29. red to Rout of the traditional common source amplifier in Figure 7 14 Assume gm rds gt gt 1 Hint Rout Rsee up Rseen down 8 Simulate the high gain amplifier in Figure 7 14 with HSpice Let Reff 1k and Cl 1pF Perform a dc sweep on Rb2 to find what value is needed to put vout at vdd 2 Use this value to perform both ac and transient simulations For the transient simulation use an input sine wave with amplitude 50mV and frequency 10 KHz University of Southern California EE348L page29 Lab 7 7 13 Lab Exercises 1 2 3 Submit plots relevant to reach question in your lab report Use the supply voltage that you used in your pre lab Spice simulations for this lab Remember that an amplitude of 50mV corresponds to a Vpp of 100mV Build the common source amplifier you designed in pre lab question 3 Verify and record your results for load resistances of 100kO 10kQ 1kQ and 100Q for a 10 kHz sine wave with amplitude 50mV Do your results agree with you Spice results Why or why not For a 10kQ load record any changes in gain when you increase the sine wave amplitude to the 100mV 200mV and 400mV Does your output clip Now record the gain for an open load Is it different Why Hint use a potentiometer for Rb2 and adjust it until your drain current is the desired value To measure the drain current do NOT use an ammeter Instead use a dc voltage probe and measure the voltage across Rss When this voltage hits Vss Id Rss you h

Laboratory Experiment 7 EE348L

Contents

Download Pdf Manuals

Related Search

Related Contents