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USER`S MANUAL

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3. ATaWNassv MIYOS Qv3H Nvd 9 x ZN NO103NNOO 40 N30vds 8 lt ZN FINAONW dl JO 3415 MANOS 1v 4 9 X ZN 21 EIA TIA 422B SERIAL COMMUNICATION MODULE SERIES IP521 INDUSTRIAL I O PACK 61 109 INVHOVIG 2018 126541 TWNDIS 3HV Lr 9 NOWWOO Qe LE 92 Lz 9L LL 9 EL SNId Zd QNO BN uu ONIH3LIIJ 5 1 Alddns AS NOININOO o 21501 10OHINOO 9 dy n NOLLVINHOJNI al aov AS HOLVH3N39 S1HOd d 91901 10H1NOO v Tu 1HOd TOHINOO pis S1HOd 9 sna 553 00 p Ty N ay sna viva 1 4 id 31 GAAOWSY 38 133005 5 d 30VJ3H3 INI GALNNOW 5416 99 HOLSIS3H SYI ly 21901 18 HOLSIS3H NOLLVNIANH3L 3 1ON 9227 5 22 EIA TIA 422B SERIAL COMMUNICATION MODULE SERIES IP521 INDUSTRIAL I O PACK VVIZ LOSY TEAST IVNDIS AHL 3NIINH313Q OL H3HLONV OL 1934599 N3XV L SI 6 JNO 30 JHL ASNVOAE QHVOUNVIS NOISSINSNVYL V Q3H3GISNOO SI 22
4. 19 INDUSTRIAL I O PACK COMPLIANCE 20 APPENDIX enis 20 CABLE MODEL 5025 550 X amp 5025 551 X 20 TERMINATION PANEL MODEL 5025 552 20 TRANSITION MODULE MODEL TRANS GP 20 DRAWINGS Page 4501 434 IP MECHANICAL ASSEMBLY 221 4501 713 IP521 BLOCK DIAGRAM 22 4501 714 RS422 RS485 INTERFACE DIAGRAM 23 4501 715 RESISTOR SOCKET LOCATION DIAGRA 24 4501 462 CABLE 5025 550 NON SHIELDED 25 4501 463 CABLE 5025 551 SHIELDED 26 4501 464 TERMINATION PANEL 5025 552 27 4501 465 TRANSITION MODULE TRANS GP 28 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility Trademarks are the property of their respective owners 1 0 GENERAL INFORMATION The Industrial I O Pack IP Series IP521 module provides eight EIA TIA 422B serial communication ports for interfacing to the VMEbus PClbus or ISAbus according to your carrier board Up to five units m
5. 1 5 318v9 IWNOIS 66 6206 1300 E SSE Ni SS SS XXXX Lyd 9vWOMOV LYYd N3A3S 310 ON Se BAY Ss 77 S S31VOIONI 217 dOL 1334 p ld JILVW3HO9S 1498 4209 1300NW EIA TIA 422B SERIAL COMMUNICATION MODULE SERIES IP521 INDUSTRIAL I O PACK 97 1067 TANVd NOLLVNIW331 2489 4204 1300 SOF 02070 3 101 SUBL3WITIIN S3HONI NI SNOISN3AIG S310N MAIA 3015 TIVAOW3S 1015 33AIRJOM3SOS B 22006 333H NMOHS ONLLNNOW NIG ale SooS NI ONILNNOW Du ld NMOHS 0 0 100 YAGNNN
6. 12 XON XOFF 1 2 Registers 13 Identification Space 13 THE EFFECT OF 13 IP521 PROGRAMMING CONSIDERATIONS 14 FIFO 14 FIFO Interrupt 14 Loopback Mode 15 Interrupt 15 Software Flow 20 15 Programming 16 4 0 THEORY OF 17 EIA TIA 422B SERIAL 17 IP521 OPERATION reiten 18 LOGIC POWER 18 5 0 SERVICE AND 18 SERVICE AND REPAIR 55 5 18 PRELIMINARY SERVICE 18 6 0 5 19 PHYSICAL ritui RUTRUM ERES 19 2 2 19 19 RS422 RS485 19 RS422 RS485 TRANSMITTER OUTPUTS 19 RS422 RS485 RECEIVERS 5
7. 20 Port C Registers 21 Not Driven Organized as Port A 1 2 2 30 Port D Registers 31 Not Driven Organized as Port A 1 40 Port E Registers 41 Not Driven Organized as Port A 1 4E 50 Port F Registers 51 Not Driven Organized as Port A 1 5 5 60 Port Registers 61 Not Driven Organized as Port A q 6E 6F 70 Port H Registers 71 Not Driven Organized as Port 1 Notes Table 3 1 1 upper 8 bits of these registers not driven Pullups on the carrier data bus will cause these bits to read high 175 2 Reads Writes to IO space 1 wait state Interrupt select cycle is 2 wait states and ID space reads are 0 wait states 3 To save user manual space the registers corresponding to ports B to H have not been individually shown The registers of ports B to H are in the address space shown above To access a register in port H for example the offset of 70 hex is added to the address of the corresponding register given in table 3 1 All ports require a 16 byte memory block This board operates in two different modes In one mode this device remains software compatible with the industry standard 16C450 family of UART s and provides double buffering of data registers In the FIFO Mode enabled via bit 0 of the FCR register data registers are FIFO buffered so that read and write operations can be performed while the UART is performi
8. 0 6Kg packaged EIA TIA 422B SERIAL COMMUNICATION MODULE SERIES IP521 INDUSTRIAL I O PACK 9767 1047 14 N AIEGWASSV WOINVHOSW edlssvo OL 41000981 dl LINDYIO AYN ONIN3 LHOILL H3AO HONI 2 HO YALAW NOLMAN 92270 SI Q3QN3AWOO3H JHL S39V ld 7 NSLHOIL WALI SH3OvdS OLNI QHVOG H3lHHVO JO 3ais WALI SMAYOS QV3H 1H3SNI d31vas Suaovds ANY SHOLO3NNOO TILNA 01 55 auvoa dalguvo OL dl ATINASYVO qavoa LINDYIO SNIN3 LHOI L H3AO HONI HO YALA NOLMAN 9220 SI ANOYOL GAGNANWOOSY AHL Q31V3S 6 v WALI SH3OVdS OLNI aais 5 v WALI SM3H9S QV3H LV14 LYSSNI 2 Sqavoa daldavo AO S3dAL TIY LON AVI Q3GIAOHd 3HVMQHVH ONILNNOW SLN3W3HInoag SLI ANINYSLAG OL QHVOS H3lHHVO YNOA MO3HO NMOHS ualHuvo 0996 0696 3INAV H LIM ASN SYAOVdS L 4015 IN3NOdNO2
9. byte accesses are done on odd address locations The Intel x86 family of microprocessors use the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As Such use of this module on a PC carrier board will require the use of the even address locations to access the 8 bit data while a VMEbus carrier requires the use of odd address locations RBR LSR MSR SR LCR FCR MCR DLL ER SCR EFR XON 1 XON 2 XOFF 1 XOFF 2 Shaded registers are accessible only after writing BF to the line Control Register LCR FCR MCR DLL SCR PEERS XONA 2 XOFF 1 XOFF 2 Note that some functions share the same register address For these items the address lines are used along with the LCR Line Control Register and or the read and write signals to determine the function required The DLL and DLM registers are only accessible when LCR bit 7 is set to 1 The EFR Xon 1 2 and Xoff 1 2 locations are accessible only when the LCR is set to BF hex The IP521 is an eight port RS422 module Memory map Table 3 1 lists the addresses and registers corresponding to Port A Detailed register maps for Ports B to H are not given Since all registers corresponding to all Ports are listed in the same order it is possible to determine the address for Ports B to H by using Port A and adding the offset given in the tabl
10. channels Software Flow Control Model IP521 64 modules include support for software flow control Software flow control utilizes special XON amp XOFF characters to control the flow of data for more efficient data transfer and to minimize overrun errors Software flow control sometimes called XON XOFF pacing sends a signal from one node to another by adding flow control characters to the data stream The receiving node will detect the XON or XOFF character and respond by suspending transmission of data XOFF turns the data flow off or resuming transmission of data XON turns the data flow on Flow control is used frequently in data communications to prevent overrun errors or the loss of data For example a node might transmit the XOFF character to the host computer if the host is sending data too quickly to be processed or buffered thus preventing the loss of data The flow control characters are stored in the XON 1 2 and XOFF 1 2 registers Two XON amp XOFF registers are provided because the flow control character may be 1 or 2 bytes long The contents of the XON 1 2 and XOFF 1 2 registers are reset to 0 upon power up or system reset and may be programmed to any value for software flow control Different conditions may be set to detect the XON XOFF characters or start stop the transmission SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE When software flow control is enabled the UART of thi
11. register read operation is inhibited the status bit will not be set until the trailing edge of the read However if the same status condition occurs during a read operation that status bit is cleared on the trailing edge of the read instead of being set again Note that not all UART signal paths are used by this model and their corresponding UART pins are tied high 5V This includes CTS Clear To Send RI Ring Indicator DSR Data Set Ready and DCD Data Carrier Detect A power up or system reset sets bit 0 to 0 bit 4 is determined by the corresponding input signal All other bits are not used SCR Scratch Pad Interrupt Vector Register Ports A H Read Write This 8 bit read write register has no effect on the operation of either serial channel Itis provided as an aide to the programmer to temporarily hold data Alternately it stores the interrupt vector for the port In response to an interrupt select cycle the IP module will execute a read of this register for the interrupting port see Interrupt Generation section for more details Enhanced Register Set Ports A H The Enhanced Register Set is unique to the EXAR UART provided on the IP521 IP module The EXAR UART maintains compatibility with the industry standard 16 554 654 and 68 554 654 UARTs and provides new features to enhance serial communication operation The new features provided by the EXAR 16 654 UART summarized in the fo
12. the character size programmed in the Line Control Register If less than 8 bits are transmitted then data is entered right justified to the LSB This data is framed as required then shifted to the transmit data line TxD In the idle state TxD is held high In Loopback Mode this data is looped back into the Receiver Buffer Register The status of the THR is provided in the Line Status Register LSR Writing to the THR transfers the contents of the data bus D7 DO to the THR provided that at least one FIFO location is available The THR empty flag in the LSR register will be set to a logic 1 when at least one FIFO location is available SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE DLL amp DLM Divisor Latch Registers Ports A H R W The Divisor Latch Registers form the divisor used by the internal baud rate generator to divide the 14 7456MHz clock to produce an internal sampling clock suitable for synchronization to the desired baud rate The output of the baud generator RCLK is sixteen times the baud rate Two 8 bit divisor latch registers per port are used to store the divisors in 16 bit binary format The DLL register stores the low order byte of the divisor DLM stores the high order byte These registers must be loaded during initialization Note that bit 7 of the LCR register must first be set high to access the divisor latch registers DLL amp DLM Upon loading either latch a 16 b
13. 5025 551 x The A D connectors on the carrier board connect the field I O signals to the P2 connector on each of the Industrial Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial Pack IP Each Industrial Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AVME9630 9660 APC8610 or APC8620 P1 50 pin male header with strain relief ejectors Use Acromag 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 25 pounds 0 6kg packaged TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use card cages which provide rear exit for connections via transition modules transition
14. 58 ANI VLVG NO 1 V OL SINOdS3HHOO SIHL 9 QXL NO HOIH 3UV SulVd VLVG 8 JHL 40 ALVLS JHL 8A 18H INVHOVIG 98 20 584 1084 SAVWIV 5 ASSHL Al GAAOWSY 38 NYO ANY 5143905 NI Q3TIVISNI SYOLSISSY ASSHL 38 LON TIIM S38IM 5 40 HOVA GALVIOOSSV SHOLSIS3H SVIG MHOML3N JHL OS 3HVMLJOS VIA Q3 18VN3 ATLN3NVIAH3d NYO Q39unos AHL v ONILLINSNVYL 38V SLINN ON N3HM ONI LVO 14 MHOML3N 3H L d33 OL S3HIM TWNOIS 40 HOV3 Q31VIOOSSV SHOLSIS3H SVI8 40 LAS INO LSOW LV 38 LSNW 3H3HIL 76 TxD x a aauinoad SV GSAOWAY 38 AVN A3H L ANY 5137905 NI GATIVLSNI WHO 021 SHOLSIS3H 5 SVH 12841 FHL HOML3N JHL SANI H1O8 LV 18 SHOLSISSY ONILVNIINH3 LE 300 AYN STANNVHO SNIAI3O3H SNLLLINSNVH L SerSH ezrSH TIY 72 RxD_ENABLE lt LINN RB RE MHOML3N JHL 40 SNIAISO3H S JHL LV HOLSIS3H ONLLVNIAH3LL V TIV LSNI IHOML3N 2275 NV HOS 71 LY IVAONW3H ANY LN3IN3OV Id HOLSIS3H SALON 23 qH Ee
15. 64 Character FIFO Buffers Both the transmit and receive channels of each serial port provide 64 byte data buffering to reduce CPU interactions and interrupts This allows the external processor to handle more tasks within a given time Programmable Character Size Each serial port is software programmable for 5 6 7 or 8 bit character sizes SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE Programmable Stop Bits Each serial port allows 1 1 1 2 or 2 stop bits to be added to or deleted from the serial data stream Programmable Parity Generation amp Detection Even Odd or No Parity generation and detection is supported e Line Break Generation amp Detection provision for sending and detecting the line break character is provided False Start Bit Detection Prevents the receiver from assembling false data characters due to low going noise spikes on the RxD input line Programmable Baud Rate The internal baud rate generator allows the 921 6K maximum baud rate to be divided by any divisor between 1 and 279 providing support for all standard baud rates interrupt Support Individually controlled transmit empty receive ready line status data set amp flow control interrupts may be generated Unique interrupts can be assigned to each port Interrupts use a priority shifting scheme based on the last interrupt serviced preventing the continuous interrupts of one port from
16. Acromag IP module as well as a generic OLE control for non Acromag IP modules IP MODULE VxWORKS SOFTWARE Acromag provides a software product sold separately consisting of IP module VxWorks drivers This software Model IPSW API VXW MSDOS format is composed of VxWorks real time operating system libraries for all Acromag IP modules and carriers including the AVME9660 9630 APC8610 and APC8620 The software is implemented as a library of C functions which when linked with existing user code makes possible simple control of all Acromag IP modules and carriers 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions lt is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected
17. internally instead of by the external hardware paths However no interrupt requests or interrupt vectors are actually served in loopback mode and interrupt pending status is only reflected internally 2 Bits 5 7 are only programmable when the EFR bit 4 is set to The programmed values for these bits are latched when EFR bit 4 is cleared preventing existing software from inadvertently overwriting the extended functions However these MCR bits can not be set if the LCR is set to BF hex A power up or system reset sets all MCR bits to 0 LSR Line Status Register Ports A H Read Write Restricted The Line Status Register LSR provides status indication corresponding to the data transfer LSR bits 1 4 are the error conditions that produce receiver line status interrupts a priority 1 interrupt in the Interrupt Identification Register The line status register may be written but this is intended for factory test and should be considered read only by the application software Line Status Register Data Ready 0 Not Ready reset low by CPU DR Read of RBR or FIFO 1 Data Reagy set high when character received and transferred into the RBR or FIFO Overrun 0 No Error Error OE 1 Indicates that data in the RBR is not being read before the next character is transferred into the RBR overwriting the previous character In the FIFO mode it is set after the FIFO is filled and the next character is received The over
18. the Enhanced Feature Register EFR Bit 7 must be low to access the Receiver Buffer Register RBR the Transmitter Holding Register or the Interrupt Enable Register IER A power up or system reset sets all LCR bits to 0 A detailed discussion of word length stop bits parity and the break signal is included in Section 4 0 Theory of Operation MCR Modem Control Register Ports A H R W The Modem Control register controls the interface with the modem or data set as described below For this model DTR is used to enable the receiver to enable input of RxD RTS is used to enable its corresponding transmitter for output of the TxD signal The four modem control inputs CTS DSR DCD and RI are disconnected from their receiver input paths In addition the four modem control outputs DTR RTS OUT1 and OUT2 do not have transmitter output paths Bit 3 of this register must be set to a logic 1 to enable the corresponding port to issue an interrupt Modem Control Register Data Terminal 0 DTR Not Asserted Inactive Ready Output 12 DTR Asserted Active Signal DTR A DTR signal path is NOT SUPPORTED by this model Instead this output is used to enable the receiver of the port RxD 0 RTS Not Asserted Inactive 1 RTS Asserted Active A RTS signal path is NOT SUPPORTED by this model Instead the output is used to enable the transmitter of the port TxD Ready to Send Output Signal RTS
19. the basic functionality of the circuitry used on the board is also provided Refer to the Block Diagram shown in Drawing 4501 713 as you review this material EIA TIA 422B SERIAL INTERFACE The Electronic Industries Association EIA in conjunction with the Telecommunication Industries Association TIA introduced TIA EIA 422B as a balanced differential serial data transmission interface standard between Data Terminal Equipment DTE and Data Communication Equipment DCE By definition DTE is commonly used to represent the data source data sink or both DCE is used to represent the devices used to establish maintain and terminate a connection and to code decode the signals between the DTE and the transmission channel Most computers are considered DTE devices while modems are DCE devices The EIA TIA 422B interface is the second revision of this standard and specifies a balanced driver with balanced receivers Balanced data transmission refers to the fact that only two conductors are switched per signal and the logical state of the data is referenced by the difference in potential between the two conductors not with respect to signal ground The differential method of data transmission makes EIA 422B ideal for noisy environments since it minimizes the effects of coupled noise and ground potential differences That is since these effects are Seen as common mode voltages common to both lines not differential they are rejected by t
20. the data buffer or FIFO When the ANY XON function is enabled MCR bit 5 is set the UART will automatically resume transmission after receiving ANY character after having recognized XOFF and suspended transmission Note that the UART will automatically transmit the XON character s after the flow control function is disabled if the XOFF character s had been sent prior to disabling the software flow control function Special cases are provided to detect the special character and stack it into the data buffer or FIFO and these conditions are configured via bits 0 3 of the Enhanced Feature Register EFR Programming Example The following example will demonstrate data transfer between one channel of the host IP521 and another node Both nodes will use the FIFO Mode of operation with a FIFO threshold set at 60 bytes The data format will use 8 bit characters odd parity and 1 stop bit Please refer to Table 3 1 for address locations The H following data below refers to the Hexadecimal format 1 Write 80H to the Line Control Register LCR This sets the Divisor Latch Access bit to permit access to the two divisor latch bytes used to set the baud rate These bytes share addresses with the Receive and Transmit buffers and the Interrupt Enable Register IER 2 Write to the Divisor Latch MSB DLM Write 60H to the Divisor Latch LSB DLL This sets the divisor to 96 for 9600 baud i e 9600 14 7456MHz 16 96 3 Wr
21. variable e g unique calibration information ID Space bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PC ISA or PCI buses The IP521 ID Space contents are shown in Table 3 3 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID information Execution of an ID Space Read operation requires 0 wait states 203 Table 3 3 IP521 ID Space Identification ID Hex Offset From ID Base Address 01 ASCII Character Equivalent Numeric Value 49 All IP s have FE e e 1504 09 Aeremagib Code 25 P Code Not Used 0 00 Reserved ID Low Byte ID High Byte ID Bytes pem 17 tpe tono i9to3F _____ yy Notes Table 3 3 1 The IP model number is represented by a two digit code within the ID space the IP521 model is represented by 25 Hex THE EFFECT OF RESET A software or hardware reset puts the serial channels into an idle mode until initialization programming A reset initializes the receiver and transmitter clock counters It also clears the Line Status Register LSR except for the transmitter shift register empty TEMT and transmit holding register empty THRE bits whi
22. 1 are used to set the RTS delay timer trigger level 0 Disable Automatic CTS flow control 1 Enable Automatic CTS flow control CTS Hardware Flow Control Notes 1 For this model RTS is used to enable its corresponding transmitter for output of the TxD signal The RTS signals do not have transmitter output paths on this model The CTS signals do not have a receiver input path on this model A power up or system reset sets all EFR bits to 0 XON XOFF 1 2 Registers Ports A H R W These registers hold the programmed XON and XOFF characters for software flow control XON or XOFF characters may be 1 or 2 bytes long The UART compares incoming data to these values and restarts XON or suspends XOFF data transmission when a match is detected Note that access to these registers is granted only after writing BF to the Line Control Register LCR All XON XOFF bits are set to 0 upon power up or system reset Identification Space Read Only 32 odd byte addresses Each IP module contains identification ID information that resides in the ID space per the IP module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID space Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP521 ID Space does not contain any
23. ACK INTERFACE FEATURES High density Single size industry standard IP module footprint Four five units mounted on a carrier board provide up to 32 40 serial ports in a single system slot Local ID Each IP module has its own 8 bit ID information which is accessed via data transfers in the ID Read space 8 bit I O Port register Read Write is performed through 8 bit data transfer cycles in the IP module space High Speed Access times for all data transfer cycles are described in terms of wait states 1 wait state is required for reading writing channel data 2 wait states for interrupt select cycles and 0 wait states for reading the ID space see the Specifications section for detailed information SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board including Acromag s AVME9630 9660 3U 6U non intelligent VMEbus carrier boards Additionally PC AT carrier boards are also supported see the Acromag Model APC8620 PClbus carrier board A wide range of other Acromag modules are available to serve your signal conditioning and interface needs Note Since all connections to field signals are made through the carrier board which passes them to the individual IP modules you should consult the documentation of your carrier board to ensure compatibility with the following interface products Cables M
24. Acromag 9 Series 521 64 Industrial I O Pack Octal EIA TIA 422B Communication Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 1998 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 596 C11M004 SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 GENERAL 2 KEY IP521 EEATURES erret ees 2 INDUSTRIAL I O PACK INTERFACE FEATURES 3 SIGNAL INTERFACE 3 INDUSTRIAL I O PACK SOFTWARE LIBRARY 4 IP MODULE OLE CONTROL SOFTWARE 4 IP MODULE VxWORKS 5 4 2 0 PRE
25. CR bits 5 7 This feature prevents existing software from altering or overwriting the enhanced functions 1 Enables the enhanced functions Allows the IER bits 4 7 ISR bits 4 5 FCR bits 4 5 and MCR bits 5 7 to be modified Special 0 Disable special character detect Character 1 Enable special character detect Detect Incoming receive characters are Control compared with Xoff 2 data If a match exists the receive data will be transferred to FIFO and ISR bit 4 will be set to indicate detection of special character Bit 0 of the Xoff Xon registers corresponds with the LSB bit for the receive character When this feature is enabled the normal software flow control must be disabled EFR bits 0 3 must be Set to a logic 0 SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE EFR Bit FUNCTION PROGRAMMING RTS 0 Disable Automatic RTS flow Hardware control Flow 1 Enable Automatic RTS flow Control control The RTS pin can be automatically controlled to indicate local buffer overflows to remote buffers When automatic hardware flow control is enabled an interrupt will be generated when the receive FIFO is filled to the program trigger level and RTS will go to a logic 1 at the next trigger level RTS will return to a logic 0 when data is unloaded below the next lower trigger level RTS functions normally when hardware flow control is disabled FCTR bitsO
26. DULE 6 0 SPECIFICATIONS PHYSICAL Physical Configuration Length Width Board Thickness Max Component Height Connectors P1 IP Logic Interface P2 Field l O Power 5 Volts 5 ENVIRONMENTAL Operating Temperature Relative Humidity Storage Temperature Non Isolated Radiated Field Immunity RFI Electromagnetic Interference Immunity Electrostatic Discharge ESD Surge Immunity Electric Fast Transient Immunity Radiated Emissions Warning This is a class A prod Single Industrial Pack Module 9 880 in 98 5 mm 1 780 in 45 2 mm 0 062 in 1 59 mm 0 290 in 7 37 mm 50 pin female receptacle header AMP 173279 3 or equivalent 50 pin female receptacle header AMP 173279 3 or equivalent 285mA Typical 340mA Maximum Standard Unit 0 to 70 C E suffixed units 40 C to 85 5 95 Non Condensing 55 to 125 C Logic and field commons have a direct electrical connection Designed to comply with IEC1000 4 3 Level 10V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 There shall be no loss of functionality occasional cor
27. LINSNVYL TIV IVAOWHH LN3IAN3OV Id HOLSISdH SALON e ei 9 4 6 LeSdl LOG V A8 GAISLLNAG SI NOLLISOd 1 Seu FLZ LOG ONIMVHG 33S 3H3HM LN3IA3OV 1d3H TVAOW3H HOS 86H ONIMVHG NOILVOOT YOLSISSY 15 SVI8 ANY 10841 24 EIA TIA 422B SERIAL COMMUNICATION MODULE SERIES IP521 INDUSTRIAL I O PACK 79 5 318V2 IWNOIS 066 lt 205 1340 OlLVW3HOS X SS SZ S 1300 ANI 91530 SI NO Z E J 2 7 _ SSS 2 2002 216 001 ID NNOO 0000000 NON NOLVNIAH3L davo EIA TIA 422B SERIAL COMMUNICATION MODULE SERIES IP521 INDUSTRIAL I O PACK 597 1067 Se ONIZIW10d
28. NAL Ato to 0 BINARY 1 SPACE OFF MARK ON Positive Differential Voltage Negative Differential Voltage Start and stop bits are used to synchronize the DCE to the asynchronous serial data of the DTE The transmit data line is normally held in the mark state logical 1 The transmission of a data byte requires that a start bit a logical O or a transition from mark to space be sent first This tells the receiver that the next bit is a data bit The data bits are followed by a stop bit a logical 1 or a return to the mark state The stop bit tells the receiver that a complete byte has been received Thus 10 bits make up a data byte if the data character is 8 bits long and no parity is assumed Nine bits are required if only standard ASCII data is being transmitted 1 start bit 7 data bits 1 stop bit The character size for this module is programmable between 5 and 8 bits Parity is a method of judging the integrity of the data Odd even or no parity may be configured for this module If parity is selected then the parity bit precedes transmission of the stop bit The parity bit is a O or 1 bit appended to the data to make the total number of 1 bits in a byte even or odd Parity is not normally used with 8 bit data Even parity specifies that an even number of logical 1 s be transmitted Thus if the data byte has an odd number of 1 s then the parity bit is set to 1 to make the parity of the entire
29. Not Used No Effect on External Operation Port Interrupt 0 Interrupt Disabled for this port 0 Loop back Disabled 1 Loop back Enabled 5 Xon Control 0 Disable Xon In received will enable Xon Not Used Must be logic 0 7 Divide by Four 0 Divide by one The crystal frequency is unchanged it is further divided by 4 see Table 3 2 Notes Modem Control Register serial output connected to the TXD driver is set to the marking logic 1 state and the UART receiver serial data input is disconnected from the RxD receiver path The output of the UART transmitter shift register is then looped its associated pin is forced to its high inactive state Thus in the loopback diagnostic mode transmitted data is immediately received permitting the host processor to verify the transmit and receive data paths of the selected serial Disable Enable port 1 Interrupt Enabled for this 1 Enable any Xon function this mode any RX character 1 Divide by four After the crystal frequency is divided by 16 1 MCR Bit 4 provides a local loopback feature for diagnostic testing of the UART channel When set high the UART back into the receiver shift register input The control output RTS is internally connected to the control input DSR while channel In this mode interrupts are generated by controlling the state of the four lower order MCR bits 10 SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE
30. O parity error framing error or break interrupt indication Cleared by a host CPU read of the LSR if there are no subsequent errors in the FIFO FIFO read of offending character is also required Note that LSR Bits 1 4 OE PE FE are the error conditions that produce a receiver line status interrupt a priority 1 interrupt in the ISR register when any one of these conditions are detected This interrupt is enabled by setting IER bit 2 to 1 A power up or system reset sets all LSR bits to 0 except bits 5 and 6 which are high SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE MSR Modem Status Register Ports A H Read Write The Modem Status Register MSR provides the host CPU with an indication on the status of the modem input line from a modem or other peripheral device However for this model the four modem control inputs CTS DSR DCD and RI are disconnected from their receiver input paths Modem Status Register ACTS NOTSUPPORTED 4 CTS If the channel is in the loopback mode MCR bit 4 1 then the state of RTS in the is _5 DSR NOT SUPPORTED 6 RI NOT SUPPORTED DCD NOT SUPPORTED An Asterisk is used to indicate an active low signal Note that reading MSR clears the delta modem status indication bit 0 but has no effect on the bit 4 status bit For both the LSR amp MSR the setting of the status bits during a status
31. PARATION FOR 4 UNPACKING AND 4 CARD CAGE 5 4 BOARD 4 CONNECTORS 2 Devas 4 IP Field Connector 2 4 Noise and Grounding Considerations 5 IP Logic Interface Connector 1 5 3 0 PROGRAMMING 6 ADDRESS 6 RBR Receiver Buffer 7 THR Transmitter Holding Register 7 DLL amp DLM Divisor Latch Registers 7 IER Interrupt Enable Register 8 ISR Interrupt Status 9 FCR FIFO Control 9 LCR Line Control 9 MCR Modem Control 10 LSR Line Status 11 MSR Modem Status 12 SCR Scratch Pad Interrupt Vector Register 12 Enhanced Register 5 12 Enhanced Feature 5
32. STRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE INDUSTRIAL I O PACK SOFTWARE LIBRARY Acromag provides an Industrial Pack Software Library diskette to simplify communication with the board Model IPSW LIB M03 MSDOS format Example software functions provided All functions are written in the C programming language and can be linked to your application Refer to the README TXT file in the root directory and the INFO521 TXT file in the IP521 subdirectory on the diskette for more details IP MODULE OLE CONTROL SOFTWARE Acromag provides a software product sold separately consisting of IP module OLE Object Linking and Embedding drivers for Windows 959 and Windows compatible application programs Model IPSW OLE PCI MSDOS format This software provides individual drivers that allow Acromag IP modules and our personal computer carriers to be easily integrated into Windows application programs such as Visual C Visual Basic Borland Delphi Microsoft Office 97 applications and others The OLE controls provide a high level interface to IP modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers all the complicated details of programming are handled by the OLE controls These functions are intended for use in conjunction with an Acromag personal computer carrier and consist of a Carrier OLE Control and an OLE control for each
33. VNIINH3 L H QXL WHO 02 NOLLVNIINH3L 3 QXH WHO 021 NOLLVNIINH3LL 3 QXL WHO 02 NOLLVNIINH3 L WHO 02 _2 lt 0 NOLLVNIANH3 L Q GXL WHO 02 NOLLVNIINH3LL WHO 02 NOLLVNIINH3 L 8 QXL WHO 021 NOLLVNIINH3LL V QXH WHO 02 NOLLVNIINH3 L V OXL WHO 02 NOILONN 4 NOILVOISILNACI HOLSIS3H INWA 6 5 8 2 3 9 a 8 v Vv 2 e 92H GATIVLSNI SHOLSIS3H 415 TIV Q3ddlHS SI INGON TVLIA 92 9 SZ be EZH NMOHS SV 3UV 5315 HOLSIS3H qaulnoau 41 dGd3AOW3H 38 NVO ANY 51371905 NI 5415 HOLSIS3H 6 SH3AIHG ASSHL 4 GAAOWSY NYO ANY S133908 NI GATIVLSNI SYOLSISSY ASSHL G3Q33N LON TIIM S3HIM 1 6 40 Q31VIOOSSV SHOLSISSY SVI8 MHOMLAN FHL OS dHVMLJOS VIA Q3 T8VN3 38 NVO V SANIT SLY ANY ONLLLINSNVH L SLINN ON N3HM ONI LVO 14 MHOML3N 3H L OL S3HIM IWNDIS HOV3 Q31VIOOSSV SHOLSIS3H SVI8 40 LAS JNO LSOW LV 38 LSNW 3H3HL 72 WHO 021 SHOLSISAY NOLLVNIINH3LL 415 NI DfY 1d 318V3AOIW3H SVH JHL MHOMLAN JHL JO LV LH SHOLSIS3H ONILVNIIAH3 L AYN STANNVHO OSNIAIH393H ANY ONIL
34. ay be mounted on the PClbus carrier board to provide up to 40 asynchronous serial ports per PCI system slot The IP521 can also be used to implement an EIA 485 interface operating in full duplex In this mode more than one transmitter is connected to differential pair and only one transmitter can be enabled at any given time The transmit and receive paths of each channel include generous 64 byte FIFO buffers to minimize CPU interaction Character size stop bits parity and baud rate are software configurable Prioritized interrupt generation is also supported for transmit receive line status and data set conditions The IP521 utilizes state of the art Surface Mounted Technology SMT to achieve its wide functionality and is an ideal choice for a wide range of industrial communication interface applications that require a highly reliable high performance interface at a low cost The IP521 is available in standard and extended temperature range modules The IP521 64 model is the standard temperature range 0 to 70 version The IP521 64E model is the extended temperature range 40 C to 85 version KEY IP521 FEATURES High Density Provides programmable control of eight EIA TIA 422B serial ports Four units mounted on a VMEbus or ISAbus carrier board provide 32 serial channels in a single system slot On the PClbus carrier up to five units may be mounted to provide up to 40 asynchronous serial ports per PCI system slot
35. blocking the interrupts of another port Socketed Termination and Bias Resistors The network termination and bias resistors are installed in sockets on the board and may be easily inserted or removed where required Failsafe Receivers The receivers employed in this model include a fail safe feature which guarantees a high output state when the inputs are left open or floating Internal Diagnostic Capabilities Loopback controls for communication link fault isolation are included Break parity overrun and framing error simulation are also possible Compatible with Industry Standard UARTs The UART of this IP module is compatible with the industry standard ST16C554 654 ST68C554 654 and TL16C544 Additionally this device can operate in a 16C450 UART family software compatible mode The transmit and receive channels are double buffered in this mode Hold and shift registers eliminate the need for precise synchronization between the host CPU and the serial data Software Flow Control One or two sequential receive data characters are compared to a programmed Xon or Xoff character value Data transmission can be suspended or resumed via software flow control Sleep Mode The UART can be set via register control to a special sleep mode to reduce power consumption when the chip is not being used Extended Temperature Performance Option Model IP521 E units support operation from 40 C to 85 INDUSTRIAL I O P
36. ch are set to 1 note that when interrupts are subsequently enabled an interrupt will occur due to THRE being set The Modem Control Register MCR is also cleared All of the discrete signal lines memory elements and miscellaneous logic associated with these register bits are cleared de asserted or turned off However the Line Control Register LCR divisor latches Receiver Buffer Register RBR and Transmitter Holding Register THR are not affected The following table summarizes the effect of a reset on the various registers and internal and external signals REGISTERS All bits low except bits 5 amp 6 Bits 0 3 low bit 4 Reset XOFF 1 2 Reset Reset All bits low All bits low SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE SIGNALS INTERNAL amp EXTERNAL Reset Interrupt Read LSR RCVR errors Reset Interrupt Read RCVR RCVR data Buffer ready Register Reset Read ISR Write THR Reset Read MSR Reset Interrupt THRE Interrupt Status Changes IP521 PROGRAMMING CONSIDERATIONS w w w w Each serial channel of this module is programmed by the control registers LCR IER DLL DLM MCR and FCR These control words define the character length number of stop bits parity baud rate and modem interface The control registers can be written in any order but the IER register should be written last since it controls the int
37. character even Likewise if the transmitted data has an even number of 1 s then the parity bit is set to 0 to maintain even parity Odd parity works the same way using an odd number of logical 1 s Thus both the DTE amp DCE must have the same parity If a byte is received that has the wrong parity an error is assumed and the sending system is typically requested to retransmit the byte Two other parity formats not supported by this module are mark and space parity Mark parity specifies that the parity bit will always be a logical 1 space parity requires that the parity bit will always be 0 The most common asynchronous serial data format is 1 start bit 8 data bits and 1 stop bit with no parity The following table summarizes the available data formats START BIT Binary 0 a shift from Mark to Space DATA BITS 5 6 7 or 8 Bits PARITY Odd Even Stick or None STOP BIT Binary 1 1 1 1 2 or 2 Bit times With start stop and parity in mind for an asynchronous data byte note that at least one bit will be a 1 the stop bit This defines the break signal all 0 bits with a 1 stop bit lasting longer than one character A break signal is a transfer from mark to space that lasts longer than the time it takes to transfer one character Because the break signal doesn t contain any logical 155 it cannot be mistaken for data Typically whenever a break signal is detected the receiver will interpret whatever follows as a comman
38. d rather than data The break signal is used whenever normal signal processing must be interrupted In the case of a modem it will usually precede a modem control command Do not confuse the break signal with the ASCII Null character since a break signal is longer than one character time That is it is any SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE space condition on the line that lasts longer than a single character including its framing bits and is usually 1 1 2 to 2 character times long The baud rate is a unit of transmission speed equal to the number of electrical signals signal level changes sent on a line in one second It is thus the electrical signaling rate or frequency at which electrical impulses are transmitted on a communication line The baud rate is commonly confused with the bit transfer rate bits per second but baud rate does not equate to the number of bits transmitted per second unless one bit is sent per electrical signal However one electrical signal change in signal level may contain more than one bit as is the case with most phone modems While bits per second bps refers to the actual number of bits transmitted in one second the baud rate refers to the number of signal level changes that may occur in one second Thus 2400 baud does not equal 2400 bits per second unless 1 bit is sent per electrical signal Likewise a 1200bps or 2400bps modem operates at a signal
39. de The clock oscillator circuit is disabled in sleep mode The UART will not lose the programmed bits when sleep mode is activated or deactivated The UART will not enter sleep mode if any interrupts are pending 0 Disable the Receive Xoff Interrupt 1 Enable the Receive Xoff Interrupt When software flow control in enabled and one or 4 1 2 3 5 two sequential receive data characters match the preprogrammed Xoff 1 2 values an interrupt will be issued SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE 0 Disable RTS Interrupt 1 Enable RTS Interrupt This Interrupt is generated when the RTS pin transitions from a logic 0 to a logic 1 RTS is not output by this module Instead RTS is used to enable the transmitter of the port This interrupt should always be disabled 0 Disable CTS Interrupt 1 Enable CTS Interrupt This interrupt will be issued when the CTS pin transitions from a logic 0 to a logic 1 Since CTS is not used on this module this interrupt should always be disabled Notes Interrupt Enable Register 1 Bits 4 to 7 are only programmable when the EFR bit 4 is set to 1 A power up or system reset sets all IER bits to O bits 7 0 forced low ISR Interrupt Status Register Ports A H READ Only The Interrupt Status Register is used to indicate that a prioritized interrupt is pending and the type of interrupt that is pending Six levels of prioritized inte
40. dently enable disable the serial port interrupt sources Each of the eight ports have seven unique interrupt sources which are all mapped to INTREQO of the IP module Interrupts are disabled by resetting the corresponding IER bit low 0 and enabled by setting the IER bit high 1 Disabling the interrupt system IER bits 7 5 and 3 0 low also inhibits the Interrupt Status Register ISR and the interrupt request line INTREQO In addition to enabling the desired bits in the IER bit 3 of the Modem Control Register MCR must be set to 1 to enable interrupts Interrupt Enable Register IER BIT INTERRUPT ACTION 0 Disable Interrupt 1 Enable Interrupt This interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation Note that the receive FIFO must also be enabled via bit 0 of the FCR for a receive interrupt to be issued 0 Disable Interrupt 1 Enable Interrupt This interrupt will be issued whenever the THR is empty and is associated with bit 1 in the LSR 0 Disable Interrupt 1 Enable Interrupt This interrupt will be issued whenever a fully assembled receive character is available 0 Disable Interrupt 1 Enable Interrupt Modem Status Interrupt Since the modem input signals are not used on this module this interrupt should always be disabled 0 Disable Sleep Mode 1 Enable Sleep Mo
41. e below For example Port E s LCR can be accessed at word address 40 06 or 46 hex which is Port A LCR at 06 hex plus Port E Offset at 40 hex ADDRESS SPACE OFFSET Table 3 1 521 1 0 Space Address Hex Memory Map Base MSB LSB LCR Base Addr D15 D07 D00 Addr Serial Port A Registers Bit7 Not Driven 0 01 Bit7 Not Driven 0 01 Bit7 Not Driven 1 01 Bit7 Not Driven 0 Bit7 Not Driven 1 BE BL BUCH owe READ RBR Port A Receiver Buffer Register WRITE THR Port A Transmitter Holding Register R W DLL Port A Divisor Latch LSB R W IER Port A Interrupt Enable Register R W DLM Port A Divisor Latch MSB READ ISR Port A Interrupt Status Reg WRITE FCR Port A FIFO Control Reg R W EFR Port A Enhanced Feature Register R W LCR Port A Line Control Register R W MCR Port A Modem Control Reg R W Xon 1 BF R W LSR Port A Line Status Not Driven N A Register R W Xon 2 BF SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE Table 3 1 Continued 1 521 I O Memory Map Base MSB LSB LCR Base R W MSR Not Driven Port A Modem N A Status Reg R W Xoff 1 BF Not Driven Low Byte Hex R W SCR Not Driven Port A Scratch N A Pad Interrupt Vector FIFO Count R W Xoff 2 BF Not Driven High Byte Hex 10 Port B Registers 11 Not Driven Organized as Port A 1 1 1
42. ects the Break Interrupt when the break character is at the top of the FIFO It is detected by the host CPU during the first LSR read Only one 0 character is loaded into the FIFO when occurs Transmitter 0 Not Empty Holding 1 Empty indicates that the Register channel is ready to accept a new Empty character for transmission Set high THRE when character is transferred from the THR into the transmitter shift register Reset low by loading the THR It is not reset by a host CPU read of the LSR In FIFO mode this bit is set when the Tx FIFO is empty and cleared when one byte is written to the Tx FIFO When a Transmitter Holding Register Empty interrupt is enabled by IER bit 1 this signal causes a priority 3 interrupt in the ISR If the ISR indicates that this signal is causing the interrupt the interrupt is cleared by a read of the ISR Transmitter 0 Not Empty Empty 1 Transmitter Empty set when TEMT both the Transmitter Holding Register THR and the Transmitter Shift Register TSR are both empty Reset low when a character is loaded into the THR and remains low until the character is transmitted it is not reset low by a read of the LSR In FIFO mode this bit is set when both the transmitter FIFO and shift register are empty 7 Receiver 0 No Error in FIFO it is always 0 FIFO Error in 16C450 mode FCR bit 0 low 1 Error in FIFO set when one of the following data errors is present in the FIF
43. eeds all written Industrial specifications per ANSI VITA 4 1995 for 8MHz operation for Type Modules Electrical Mechanical Single Size IP Module Space 16 bit 8 bit ID Spaco m 16 bit 8 bit Supports Type 1 32 bytes per IP consecutive odd byte addresses Not Used Generates INTREQO interrupt request per IP and interrupt acknowledge cycles via access to IP INT space 8 bit read of Scratch Pad Interrupt Vector Register contents Memory Interrupts eere Access Times 8 2 Clock ID Space 0 wait state 250ns cycle Channel Registers Read 1 wait state 375ns cycle Channel Registers Write 1 wait state 375ns cycle Interrupt Registers Read 2 wait states 500 5 cycle Interrupt Registers Write 2 wait states 500ns cycle APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet maximum Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Application Used to connect a Model 5025 552 termination pan
44. el to the AVME9630 9660 non intelligent carrier board A D connectors both have 50 pin connectors Length Last field of part number designates length in feet user specified 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Non Shielded cable model see Drawing 4501 462 For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packaged TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 APC8610 or APC8620 Boards Application To connect field 1 signals to the Industrial Pack IP Termination Panel Acromag Part 4001 040 20 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field signals and connects to the AVME9630 9660 3U 6U APC8610 or APC8620 non intelligent carrier boards field connectors only via a flat ribbon cable Model
45. erations can be performed while the UART is performing serial to parallel and parallel to serial conversions Two FIFO modes of operation are possible FIFO Interrupt Mode and FIFO Polled Mode In FIFO Interrupt Mode data transfer is initiated by reaching a pre determined trigger level or generating time out conditions In FIFO Polled Mode there is no time out condition indicated or trigger level reached The transmit and the receive FIFO s simply hold characters and the Line Status Register must be read to determine the channel status 14 make programming and communicating with the board easier Acromag provides you with the Industrial I O Pack Software Library diskette The functions provided are written in the C programming language and can be linked into your application Refer to the README TXT file in the root directory and the INFO521 TXT file in the IP521 subdirectory on the diskette for details Acromag also provides a software diskette of IP module Object Linking and Embedding OLE drivers for Windows 95 compatible application programs Model IPSW OLE PCI MSDOS format This software provides individual drivers that allow all IP modules and the APC8620 carrier to be easily integrated into Windows application programs such as Visual C Visual Basic Borland Delphi Microsoft Office amp 97 applications and others The OLE controls provide a high level interface to IP modules el
46. errupt enables The contents of these registers can be updated any time the serial channel is not transmitting or receiving data The complete status of each channel can be read by the host CPU at any time during operation Two registers are used to report the status of a particular channel the Line Status Register LSR and the Modem Status Register MSR Serial channel data is read from the Receiver Buffer Register RBR and written to the Transmitter Holding Register THR Writing data to the THR initiates the parallel to serial transmitter shift register to the TxD line Likewise input data is shifted from the RxD pin to the Receiver Buffer Register as it is received The Scratch Pad Register is used to store the interrupt vector for the port In response to an interrupt select cycle the IP module will provide a read of this port As such each port may have a unique interrupt vector assigned Interrupts are served in a shifting priority fashion as a function of the last interrupting port serviced to prevent continuous interrupts from a higher priority interrupt channel from freezing out service of a lower priority channel This board operates in two different modes In one mode this device remains software compatible with the industry standard 160450 family of UART s and provides double buffering of data registers In the FIFO Mode enabled via bit 0 of the FCR register data registers are FIFO buffered so that read and write op
47. for evidence of mishandling prior to applying power CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 434 and the following discussion for configuration and assembly instructions Model 21 communication boards have no hardware jumpers s
48. gt JI8VN3 N LINN 88 IH 31Q 1 LINN SUP SW JAVNI ems oue a 0 MHOMLAN dOUGILINN 1104 58 5 22 5 8 189 OXY gt Bb NT 8 8H 410 L LINN XL lt q TI TT 189 WHOMLAN 3GON OML TINA 22759 EIA TIA 422B SERIAL COMMUNICATION MODULE SERIES IP521 INDUSTRIAL I O PACK VSLZ LOSY SVI8 1 WHO 098 SVI8 WHO 098 SVI8 H QXL WHO 098 SVI8 O QXL WHO 098 SVI8 1 WHO 098 SVI8 8 0 1 WHO 098 SVI8 3 QXL WHO 098 SVI8 1 WHO 098 AS SVIE 3 ax WHO 098 AS SVI8 WHO 098 AS 5 H QXL WHO 098 AS 5 O QXL WHO 095 20 020 m o SVIg 9 QXL WHO 099 SVIG 9 WHO 09S 4 OXL WHO 09S AS SVIG V OXL NOLLVNIIAH3 L 9 QXH WHO 095 WHO 08 NOLLVNIINH3 L 9 QXL WHO 08 NOLLVNIIANH3LL 4 WHO 08 NOLLVNIIANH3LL 4 0 1 WHO 021 NOLLVNIIAH3 L O QXH WHO 021 NOLLVNIINH3 L AXL WHO 021 NOLLVNIINH3 L H QXH WHO 02 NOLL
49. he receivers Additionally balanced drivers have generally faster transition times and allow operation at higher data rates over longer distances The EIA TIA 422B standard defines a unidirectional terminated single driver and multiple receiver configuration By providing a separate data path for transmit and receive full duplex operation is accomplished The maximum data transmission cable length is generally limited to 4000 feet without a signal repeater installed EIA TIA 422B is electrically similar to EIA 485 except that EIA 485 supports multiple driver operation Consequently this board may be used to implement a full duplex EIA 485 interface see Drawing 4501 714 However for true half duplex EIA 485 operation please see the Acromag Model IP502 With respect to EIA TIA 422B logic states are represented by differential voltages from 2V to 10V The polarity of the differential voltage determines the logical state A logic 0 the space or OFF state is represented by a positive differential voltage between the terminals measured to B or to A logic 1 the or ON state is represented by a negative differential voltage between the terminals measured A to B or to Note that at the interface a logic 0 is represented by positive voltage and a logic 1 by a negative voltage The line receivers convert these signals to the conventional TTL level associations 17 EIA TIA 422B SIG
50. iminating the need to perform low level reads writes of registers and the writing of interrupt handlers all the complicated details of programming are handled by the OLE controls These functions are intended for use in conjunction with an Acromag personal computer carrier and consist of a carrier OLE control and an OLE control for each Acromag IP module as well as a generic OLE control for non Acromag IP modules In addition Acromag provides a software product sold separately consisting of IP module VxWorks drivers This software Model IPSW API VXW MSDOS format is composed of VxWorks real time operating system libraries for all Acromag IP modules and carriers including the AVME9660 9630 APC8610 and APC8620 The software is implemented as a library of C functions which when linked with existing user code makes possible simple control of all Acromag IP modules and carriers FIFO Polled Mode Resetting all Interrupt Enable Register IER bits to 0 with FIFO Control Register FCR Bit 0 21 puts the channel into the polled mode of operation The receiver and transmitter are controlled separately and either one or both may be in the polled mode In FIFO Polled Mode there is no time out condition indicated or trigger level reached the transmit and the receive FIFO s simply hold characters and the Line Status Register must be read to determine the channel status FIFO Interrupt Mode In FIFO Interrupt Mode data transfer is in
51. ing rate of only 600 baud since they encode 2 and 4 bits respectively in one electrical impulse through amplitude phase and frequency modulation techniques However for this device the baud rate is considered equivalent to the bit rate Pins 1 40 of the field I O connector P2 provide connectivity to serial Ports A H of this module Refer to Table 2 1 for pin assignments Note that a suffix of _A _B _C is appended to the signal names to indicate their port association The receive and transmit signals are described in detail below EIA TIA 422B Signal Descriptions Receive Data Line DCE to DTE This is the receive data line from the modem to the DTE The signals on this line are in serial form For data to be received the DTR signal is used to enable the receiver of the port Transmit Data Line DTE to DCE This is the transmit data line from the DTE to the modem When no data is being transmitted the signal line is held in the mark state For data to be transmitted RTS must all be in the on state asserted An Asterisk is used to indicate an active low signal IP521 OPERATION Connection to each serial port is provided through connector P2 refer to Table 2 1 These pins are tied to the inputs and outputs of EIA TIA 422B line receivers and drivers The function of the line receivers is to convert the required EIA TIA 422B signals to the TTL levels required by the UART Universal Asy
52. it baud counter is immediately loaded this prevents long counts on initial load The clock may be divided by any divisor from 1 to 2197 The relationship between the baud rate the divisor and the 14 7456MHz clock can be summarized in the following equations _ 14 7456 2 Divisor 16 x Baud Rate x MCRDIV _ 14 7456MHz Baud Rate His x Divisor x MCRDIV The MCRDIV term represents the state of bit 7 of the MCR Mode Control Register as follows MCRDIV 1 If MCR bit 7 0 MCRDIV 4 If MCR bit 7 1 The following table shows the correct divisor to use for generation of some standard baud rates based on the 14 7456MHz clock A different external crystal can replace the 14 7456MHz crystal on the circuit board to obtain unique clock rates You may contact Acromag Applications Engineering to explore options in this area Table 3 2 Baud Rate Divisors 14 7456MHz Clock HEX 7 1 Bit 7 0 HEX HEX 50 20 468 12 00 300 1200 768 03 00 600 240 38 0 80 1200 4800 12 00 CO 2400 9600 00 60 3600 14400 64 00 40 400 19200 48 00 30 7200 28800 32 00 20 9600 38400 24 00 19200 76800 12 00 28800 115200 8 00 38400 153600 6 00 57 600 230400 4 00 230 00 921600 1 00 With respect to this device the baud rate may be considered equal to the number of bits
53. ite OBH to the Line Control Register LCR This first turns off the Divisor Latch Access bit to cause accesses to the Receiver and Transmit buffers and the Interrupt Enable Register It also sets the word length to 8 bits the number of stop bits to one and enables odd parity 4 OPTIONAL Write xxH to the Scratch Pad Register This has no effect on the operation but is suggested to illustrate that this register can be used as a 1 byte memory cell Optionally this register is also used to store the interrupt vector for the port A read of this register will be performed in response to an interrupt cycle 5 Write 07H to the Interrupt Enable Register IER This is the first step to enable the receiver line status interrupt Note bit 3 of the must also be set to logic 1 to enable interrupts The line status interrupt is used to signal error cases such as parity or overrun errors The received data available and transmit holding buffer empty interrupts have also been enabled to aide control by the host CPU in moving data back and forth 6 Write C7H to the FIFO Control Register FCR This enables and initializes the transmit and receive FIFO s and sets the trigger level of the receive FIFO interrupt to 60 bytes 7 Read from the Interrupt Status Register ISR This is done to check that the device has been programmed correctly The upper nibble C indicates that the FIFO s have been enabled and the lowe
54. itiated by reaching a pre determined trigger level or generating a time out condition Please note the following with respect to this mode of operation When the receiver FIFO and receiver interrupts are enabled the following receiver status conditions apply 1 LSR Bit 0 is set to 1 when a character is transferred from the shift register to the receiver FIFO It is reset to 0 when the FIFO is empty 2 The receiver line status interrupt ISR 06 has a higher priority than the received data available interrupt ISR 04 3 The receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the FIFO is cleared when the FIFO drops below its programmed trigger level The receive data available interrupt indication SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE 58 04 also occurs when the FIFO reaches its trigger level and is cleared when the FIFO drops below its trigger level When the receiver FIFO and receiver interrupts are enabled the following receiver FIFO character time out status conditions apply 1 AFIFO character time out interrupt occurs if minimum of character is in the FIFO e The last received serial character is longer than four continuous prior character times ago if 2 stop bits are programmed the second one is included in the time delay e Thelast CPU read of the FIFO is more than four continuous character times earlier A
55. llowing register descriptions and includes software flow control via Xon and Xoff The Enhanced Register Set includes the following registers e Enhanced Feature Register EFR e Xon 1 Xon 2 e Xoff 1 Xoff 2 In order to access the Enhanced Registers the LCR must be set to BF hex Each of these registers will be described in the following EFR Enhanced Feature Register Ports A H Read Write The Enhanced Feature register is used to enable or disable enhanced features including software flow control This register is also used to unlock access to programming the extended register functionality of IER bits 4 7 ISR bits 4 5 FCR bits 4 5 and MCR bits 5 7 Enhanced Feature Register EER Bi FUNCTION Software 00XX No Transmit Flow Control Flow 10XX Transmit Xon1 Xoff1 Control 01XX Transmit Xon2 Xoff2 11XX Transmit Xon1 and Xon2 Xoff1 and Xoff2 XX00 No receive Flow Control XX10 Receiver Compares Xon1 Xoff1 XX01 Receiver Compares Xon2 Xoff2 1011 Transmit Xon1 Xoff1 Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 0111 Transmit Xon2 Xoff2 Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 1111 Transmit 1 Xon2 Xoff1 and Xoff2 Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 0011 No transmit flow control Receiver compares Xon1 and Xon2 Xoff1 and Xoff2 Enhanced 0 Disable and latch the Enhanced Function Functions the IER bits 4 7 ISR Control bits 4 5 FCR bits 4 5 M
56. modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 100 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold the mating area MIL G 45204 Type Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 3M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Grade C Connects to AVME9630 9660 boards within the card cage flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Six layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 to 85 Storage Temperature 55 C to 105 C Shipping Weight 1 25 pounds
57. nchronous Receiver Transmitter The line drivers convert the UART TTL levels to the EIA TIA 422B voltage levels The UART provides the necessary conversion from serial to parallel receive and parallel to serial transmit for interfacing to the data bus Additionally it provides data buffering and data formatting capabilities A programmable logic device is used to control the interface between the UART and the IP bus Note that the field serial interface to the carrier board provided through connector P2 refer to Table 2 1 is NON ISOLATED This means that the field signal return and logic common have a direct electrical connection to each other As care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring this effect may cause errors in operation and with extreme abuse possible circuit damage Refer to Drawing 4501 714 for example communication wiring connections LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 refer to Table 2 2 Not all of the IP logic P1 pin functions are used P1 also provides 5V to power the module A programmable logic device installed on the IP Module provides the control signals required to operate the board It decodes the selected addresses in the and ID spaces and produces the chip selects control signals and timing required by the communication registers as well as the acknowledgement signal req
58. ng serial to parallel and parallel to serial conversions Two FIFO modes are possible FIFO Interrupt Mode and FIFO Polled Mode Some registers operate differently between the available modes and this is noted in the following paragraphs RBR Receiver Buffer Register Ports A H READ Only The Receiver Buffer Register RBR is a serial port input data register that receives the input data from the receiver shift register Note that the RBR will only receive data if the transceiver is first enabled to receive data The transceiver is enabled to receive data by setting bit 0 of the MCR Modem Control Register to a logic 1 The RBR holds from 5 to 8 bits of data as specified by the character size programmed in the Line Control Register LCR bits 0 amp 1 If less than 8 bits are transmitted then data is right justified to the LSB If parity is used then LCR bit 3 parity enable and LCR bit 4 type of parity are required Status for the receiver is provided via the Line Status Register LSR When a full character is received including parity and stop bits the data received indication bit bit 0 of the LSR is set to 1 The host CPU then reads the Receiver Buffer Register which resets LSR bit 0 low If the character is not read prior to a new character transfer between the receiver shift register and the receiver buffer register the overrun error status indication is set in LSR bit 1 If there is a parity error the error i
59. odel 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 8610 or 8620 carrier boards to Model 5025 552 termination panels The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog applications The suffix of the model number is used to indicate the length in feet Termination Panels Model 5025 552 A DIN rail mountable panel that provides 50 screw terminals for universal field I O termination Connects to Acromag AVME9630 9660 APC8610 or APC8620 carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 Transition Module Model TRANS GP This module repeats field I O connections of IP modules A through D for rear exit from a VMEbus card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth It connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to 9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 or 5025 551 SERIES IP521 INDU
60. op bit 0 Odd 1 Even 0 Disabled 1 Enabled When parity is enabled stick parity causes the transmission and reception of a parity bit to be in the opposite state from the value selected via bit 4 This is used as a diagnostic tool to force parity to a known state and allow the receiver to check the parity bit in a known state 0 Break Disabled 1 Break Enabled When break is enabled the serial output line TxD is forced to the space state low This bit acts only on the serial output and does not affect transmitter logic For example if the following sequence is used no invalid characters are transmitted due to the presence of the break 1 Load zero byte in response to the Transmitter Holding Register Empty THRE status indication Set the break in response to the next THRE status indication 3 Wait for the transmitter to become idle when the Transmitter Empty status signal is set high TEMT 1 then clear the break when normal transmission has to be restored Data Bits Data Bits Length Sel 2 Stop Bit Select 3 Parity Enable 4 Even Parity Select Stick Parity Break Control DLL DLM and EFR Enable Bit 2 0 Access Receiver Buffer 1 Allow Access to Divisor Latches DLL amp DLM and Enhanced Feature Register enabled EFR Note that bit 7 must be set high to access the divisor latch registers DLL amp DLM of the baud rate generator or access
61. ovides individual control for generation of transmit receive line status and data set interrupts on each of eight channels Each channel shares interrupt request line 0 INTREQO according to a unique priority shifting scheme that prevents the continuous interrupts of one channel from freezing out another channels interrupt requests After pulling the INTREQO line low and in response to an Interrupt Select cycle the current highest priority interrupt channel will serve its interrupt vector first Interrupt serving priority will shift as a function of the last port served A unique interrupt vector may be assigned to each communication port and is loaded into the Scratch Pad Register SCR for the port The IP module will thus execute a read of the scratch pad register in response to an interrupt select cycle Two wait states are required to complete this cycle Interrupt priority is assigned as follows Initially with no prior interrupt history Port A has the highest priority and will be served first followed by port B followed by port C etc to Port H However if port A was the last interrupt serviced then port B will have the highest priority followed by port C etc to Port H then port A in a last serviced last out fashion Priority continues to shift in the same fashion if Port B or Port C was the last interrupt serviced This is useful in preventing continuous interrupts on one channel from freezing out interrupt service for other
62. pported These bits are used to set the trigger level for the transmit FIFO interrupt An interrupt will be issued when the number of characters in the FIFO drops below the selected trigger level One of four trigger levels can be selected bit 5 bit 4 Trigger Level 0 0 08 0 1 16 1 0 32 1 1 56 These bits are used to set the trigger level for the receiver FIFO interrupt An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level One of four trigger levels can be selected bit 7 bit 6 Trigger Level Notes FIFO Control Register 1 Bits 4 and 5 are only programmable when the EFR bit 4 is set to 1 A power up or system reset sets all FCR bits to 0 LCR Line Control Register Ports A H Read Write The Line Control Register is used to specify the asynchronous data communication format The word length the SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE number of stop bits and the parity are selected by writing the appropriate bits in this register The individual bits of this register control the format of the data character as follows Line Control Register 00 5 Data Bits 10 7 Data Bits 0 1 Stop Bit 1 1 5 Stop Bits if 5 data bits 2 Stop Bits if 6 7 or 8 data bits selected 0 Disabled 1 Enabled A parity bit is generated and checked for between the last data word bit and the st
63. r Framing error or Break Interrupt Received Transmit FIFO level reached or Character Time Out or Xon Xoff Special Character Detect 1200 Termination Resistors are installed in sockets on the module and may be removed if required see Drawing 4501 715 for location For an 5422 network install a terminating resistor at the end of the network only For an RS422 RS485 network transmitting and receiving channels may have terminating resistors RT at both ends of the network see interface Drawing 4501 714 5600 to 5V on output lines 5600 pull down to GND on lines installed in sockets on board and may be removed if required see Drawing 4501 715 for location RS422 RS485 Transmitter Outputs Differential Output Common Mode Output Voltage Propagation Delay Driver Rise and Fall Time RS422 RS485 Receiver Inputs Data Input Voltage Range Input High Threshold Input Low Threshold Input Resistance 2 0V Minimum Loaded 500 3V Max 60ns Max 540 100 40ns 540 100 Up to 2 5 Mbps 8V to 12 5 DC Maximum 2 0V Minimum 0 8V Maximum 12KQ SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE INDUSTRIAL I O PACK COMPLIANCE Specification This device meets or exc
64. r nibble 1 indicates that no interrupts are pending 8 Write OAH to the Modem Control Register MCR This enables interrupts and sets the Ready To Send bit and asserts the RTS signal line It is used to enable transmit data output for the port Note the modem control lines either input or output have no effect on the parallel to serial output data or serial to parallel input data These lines interact only through CPU control to provide the handshaking necessary for this data transfer protocol 9 The host should begin writing data repeatedly to the Transmitter Holding Register This loads the transmit FIFO and initiates transmission of serial data on the TxD line The first serial byte will take about 100us to transmit so it is likely that the transmit FIFO will fill before the first byte has been sent 10 Read data repeatedly from the Receiver Buffer Register After 60 bytes have been received or fewer bytes with a timeout an interrupt will be generated INTREQO will go active to signal the host CPU that it can begin reading the receive FIFO 11 The host should acknowledge the interrupt To acknowledge and clear it an interrupt select cycle should be executed Then begin reading the receive FIFO data 16 SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE 4 0 THEORY OF OPERATION This section contains information regarding theTIA EIA 422B serial data interface A description of
65. rity as the received data available interrupt The Transmitter Holding Register Empty interrupt has the same priority as the Transmitter FIFO Empty interrupt Loopback Mode Operation This device can be operated in loopback mode useful for troubleshooting a serial channel without physically wiring to the channel Bit 4 of the Modem Control Register MCR is used to program the local loopback feature for the UART channel When set high UART 5 serial output Transmit Data Path is set to the marking logic 1 state and the UART receiver serial data input lines are disconnected from the RxD receiver path The output of the UART transmitter shift register is then looped back into the receiver shift register input Thus a write to the Transmitter Holding Register is automatically looped back to the corresponding Receiver Buffer Register The RTS modem control output of the MCR Register is internally connected to the corresponding modem control input monitored via the Modem 15 Status Register while their associated pins forced to their high inactive state Thus in loopback diagnostic mode transmitted data is immediately received permitting the host processor to verify the transmit and receive data paths of the selected serial channel Further modem status interrupt generation is controlled manually in loopback mode by controlling the state of CTS internally Interrupt Generation This model pr
66. rrupts are provided to minimize software interaction Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced No other interrupts are acknowledged until the pending interrupt is serviced Whenever the interrupt status register is read the interrupt status is cleared Note only the current pending interrupt is cleared by the read A lower level interrupt may be seen after re reading the interrupt status bits The eight individual ports share the IP module INTREQO signal Each port has an opportunity to issue an interrupt in a round robin fashion That is interrupt vectors are served according to a shifting priority scheme that is a function of the last interrupting port served The following interrupt source table shows the data values bit 0 5 for the six prioritized interrupt levels and the interrupt Sources associated with each of these interrupt levels PRIORITY ISR BITS Source of the Interrupt LEVEL to 000110 Receiver Line Status see 1 58 bits 1 4 Level reached 2 000010 Transmitter Holding Register Empty 010000 Received Xoff signal special character 100000 CTS RTS change of state Note that ISR bit 0 can be used to indicate whether an interrupt is pending bit O low when interrupt is pending ISR bits 1 amp 2 are used to indicate the highest priority interrupt pending ISR bit 3 is always logic 0 the 160450 mode ISR bit is set along
67. run error is detected by the CPU on the first LSR read after it happens The character in the shift register is not transferred into the FIFO but is overwritten This bit is reset low when the CPU reads the LSR Parity Error 0 No Error PE 1 Parity Error the received character does not have the correct parity as configured via LCR bits 3 amp 4 This bit is set high on detection of a parity error and reset low when the host CPU reads the contents of the LSR In the FIFO mode the parity error is associated with a particular character in the FIFO LSR Bit 2 reflects the error when the character is at the top of the FIFO Framing 0 No Error Error FE 1 Framing Error Indicates that the received character does not have a valid stop bit stop bit following last data bit or parity bit detected as a zero space bit This bit is reset low when the CPU reads the contents of the LSR In FIFO mode the framing error is associated with a particular character in the FIFO LSR Bit 3 reflects the error when the character is at the top of the FIFO Line Status Register continued 4 Break 0 No Break Interrupt 1 Break the received data input has been held the space logic 0 state for more then a full word transmission time start bits data parity bit stop bits Reset upon read of LSR In FIFO mode this bit is associated with a particular character in the FIFO and refl
68. ruption of communication packets is permitted under the influence of EMI from switching solenoids commutator motors and drill motors Complies with IEC1000 4 2 Level 8KV AKV air direct discharge to the enclosure port and European Norm EN50082 1 Not required for signal I O per European Norm EN50082 1 Complies with IEC1000 4 4 Level 2 0 5KV at field input and output terminals and European Norm 50082 1 Meets or exceeds European Norm 50081 1 for class equipment uct In a domestic environment this product may cause radio interference in which the user may be required to take adequate measures 19 UART RS422 RS485 PORTS Channel Configuration Data Rate Cable Character Termination Resistors Bias XR16C654 Eight independent non isolated EIA TIA 422B serial ports with a common signal return connection 921 6K bits sec Maximum Limited by 14 7456MHz crystal Asynchronous serial only 4000 feet 1200M typical Software Programmable 5 to 8 bits Software Programmable odd even or no parity Software Programmable 1 1 1 2 or 2 bits The data registers are double buffered 166450 mode or 64 byte FIFO buffered FIFO mode Receiver Line Status Interrupt i e Overrun o
69. s model will compare two sequential received data bytes with preprogrammed XOFF 1 2 characters When an XOFF match is detected the UART will halt transmission after completing the transmission of the current character The receive ready flag of the Interrupt Status register will be set ISR bit 4 is set to 1 when the XOFF character has been detected only if enabled via bit 5 of the Interrupt Enable register IER bit 5 is used to enable the received XOFF interrupt and bit 3 of the MCR An interrupt will then be generated After recognition of the XOFF characters the UART will compare the next two incoming characters with the preprogrammed XON 1 2 characters If a match is detected the UART will resume transmission and clear the received XOFF interrupt flag Interrupt Status Register bit 4 After more data has been received the UART will automatically send XOFF 1 2 characters as soon as the received data passes the programmed FIFO trigger level causing the host to suspend transmission The UART will then transmit the programmed XON 1 2 characters as soon as the received data reaches the next lowest trigger level thus causing the host to resume transmission received data trigger levels are 8 16 56 and 60 When single XON XOFF characters are selected the UART compares the received data to these values and controls the transmission accordingly XON restart transmission XOFF suspend transmission These characters are not stacked in
70. s included below A complete functional description of all P2 pin functions is included in Section 4 0 Theory Of Operation P2 Pin Signal Descriptions Receive Data Line Input This is the receive data input line During Loopback Mode the RxD input is disabled from the external connection and connected to the TxD output internally Transmit Data Line Output This is the transmit output data line In the idle state this signal line is held in the mark logic 1 state During Loopback Mode the TxD output is internally connected to the RxD input Noise and Grounding Considerations The serial channels of this module are non isolated and share a common signal ground connection Further the IP521 is non isolated between the logic and field 1 grounds since signal common is electrically connected to the IP module ground Consequently the field interface connections are not isolated from the carrier board and backplane Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections The signal ground connection at the communication ports are common to the IP interface ground which is typically common to safety chassis ground when mounted on a carrier board and inserted in a backplane As such be careful not to attach signal ground to safety ground via any device connected to these ports or a ground loop will be produced and this may adversel
71. s indicated in LSR bit 2 If a stop bit is not detected a framing error indication is set in bit 3 of the LSR Serial asynchronous data is input to the receiver shift register via the receive data line RxD From the idle state this line is monitored for a high to low transition start bit When the start bit is detected a counter is reset and counts the 16x clock to 7 1 2 which is the center of the start bit The start bit is judged valid if RxD is still low at this point This is known as false start bit detection By verifying the start bit in this manner it helps to prevent the receiver from assembling an invalid data character due to a low going noise spike on RxD If the data on RxD is a symmetrical square wave the center of the data cells will occur within 3 12596 of the actual center providing an error margin of 46 875 Thus the start bit can begin as much as one 16x clock cycle prior to being detected THR Transmitter Holding Register Ports A H WRITE Only The Transmitter Holding Register THR is a serial output data register that shifts the data to the transmit data line TxD However the THR data will not pass to the TxD line unless the tranceiver is first enabled The transceiver must be enabled to transmit data by setting bit 1 of the MCR Modem Control Register to a logic 1 The Transmitter Holding Register THR is a serial port output data register that holds from 5 to 8 bits of data as specified by
72. t 300 baud and with 12 bit characters including start stop and parity bits the FIFO time out interrupt causes a latency of 160ms maximum from received character to interrupt issued 2 From the clock signal input the character times can be calculated The delay is proportional to the baud rate 3 The time out timer is reset after the CPU reads the receiver FIFO or after a new character is received when there has been no time out interrupt 4 A time out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO When the transmit FIFO and transmit interrupts are enabled FCR Bit 0 1 and 01 a transmitter interrupt will occur as follows 1 When the transmitter FIFO is empty the transmitter holding register interrupt ISR 02 occurs The interrupt is cleared when the Transmitter Holding Register THR is written to or the Interrupt Status Register ISR is read One to 128 characters can be written to the transmit FIFO when servicing this interrupt 2 The transmit FIFO empty indications are delayed one character time minus the last stop bit time when the following occurs Bit 5 of the LSR THRE is 1 and there is not a minimum of two bytes at the same time in the transmit FIFO since the last time THRE 1 The first transmitter interrupt after changing FCR Bit 0 is immediate assuming it is enabled The receiver FIFO trigger level and character time out interrupts have the same prio
73. to avoid incorrect assembly The pin assignments of P1 are standard for all IP modules according to the Industrial Pack Specification see Table 2 2 Note that the IP521 does not utilize all of the logic signals defined for the P1 connector and these are indicated in BOLD ITALICS SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE 3 0 PROGRAMMING INFORMATION ADDRESS MAPS This board is addressable in the Industrial Pack space to control the interface configuration data transfer and steering logic of eight EIA TIA 422B serial ports As such three types of information are stored in the space control status and data These registers are listed below along with their mnemonics used throughout this manual The space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IP521 uses 64 lower byte locations of this space The space address map for the 521 is shown in Table 3 1 Note that the base address for the IP module space see your carrier board instructions must be added to the addresses shown to properly access the space accesses are performed on 8 bit word basis 00 07 This manual is presented using the Big Endian byte ordering format Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Thus
74. transmitted per second bps The bit rate bps or baud rate defines the bit time This is the length of time a bit will be held on before the next bit is transmitted A receiver and transmitter must be communicating at the same bit rate or data will be garbled A receiver is alerted to an incoming character by the start bit which marks the beginning of the character It then times the incoming signal sampling each bit as near to the center of the bit time as possible To better understand the asynchronous timing used by this device note that the receive data line RxD is monitored for a high to low transition start bit When the start bit is detected a counter is reset and counts the 16x sampling clock to 7 1 2 the center of the start bit The receiver then counts from 0 to 15 to sample the next bit near its center and so on until a stop bit is detected signaling the end of the data stream Use of a sampling rate 16x the baud rate reduces the synchronization error that builds up in estimating the center of each successive bit following the start bit As such if the data on RxD isa symmetrical square wave the center of each successive data cell will occur within 3 125 of the actual center this is 50 16 providing an error margin of 46 875 Thus the start bit can begin as much as one 16x clock cycle prior to being detected IER Interrupt Enable Register Ports A H R W The Interrupt Enable Register is used to indepen
75. uired by the carrier board per the IP specification It also prioritizes the serving of port interrupts 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Acromag s Application Engineers can provide further technical assistance if required When needed complete repair services are also available from Acromag 18 SERIES IP521 INDUSTR IAL PACK EIA TIA 422B SERIAL COMMUNICATION MO
76. witches to configure CONNECTORS Connectors of the 521 module consist of one IP module field I O connector and one IP module logic connector These interface connectors are discussed in the following sections IP Field Connector P2 P2 provides the field I O interface connections for mating modules to the carrier board P2 is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly SERIES IP521 INDUSTRIAL I O PACK EIA TIA 422B SERIAL COMMUNICATION MODULE P2 pin assignments are unique to each IP model see Table 2 1 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board Table 2 1 521 Field I O Pin Connections P2 Pin Description Number Pin Description Number COMMON 6 XDB 8 9 In Table 2 1 a suffix of A to is appended to each pin label to denote its port association A brief description of each of the serial port signals at P2 i
77. with bit 2 when in the FIFO mode and a timeout interrupt is O 1 i 000000 MSR Modem Status Register _6 pending Bit 4 set indicates a Xoff special character detected interrupt pending Bit 5 indicates a pending interrupt due to a change of state on the CTS or RTS signals Bits 6 and 7 set when bit 0 of the FIFO Control Register is set to 1 A power up or system reset sets ISR bit 0 to logic 1 and bits 1 to 7 to logic 0 FCR FIFO Control Register Ports A H WRITE Only This write only register is used to enable and clear the FIFO buffers set the transmit receive FIFO trigger levels and select the type of DMA signaling DMA is NOT supported by this model FIFO Control Register When set to 1 this bit enables both the Tx and Rx FIFO s All bytes in both FIFO s can be cleared by resetting this bit to 0 Data is cleared automatically from the FIFO s when changing from FIFO mode to the alternate 16C450 mode and visa versa This bit must be a 1 when other FCR bits are written to or they will not be programmed When set to 1 this bit clears all bytes in the Rx FIFO and the resets counter logic to 0 this does not clear the shift register When set to 1 this bit clears all bytes in the Tx FIFO and resets the counter logic to 0 this does not clear the shift register When set to 41 this bit sets DMA Signal from Mode 0 to Mode 1 if FIFO Control Register Bit 0 1 DMA Not Su
78. y affect operation The communication cabling of the P2 interface carries digital data at a high transfer rate For best performance increased signal integrity and safety reasons you should isolate these connections away from power and other wiring to avoid noise coupling and crosstalk interference EIA TIA 422B communication distances are generally limited to less then 4000 feet Always keep interface cabling and ground wiring as short as possible for best performance IP Logic Interface Connector P1 P1 of the IP module provides the logic interface to the mating connector on the carrier board This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 Screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Table 2 2 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number i Do 4 Do2 6 04 8 05 9 Do 10 35 2002 11 11 RESERVED 46 Di2 An Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by this IP Model Field and logic side connectors are keyed

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