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User Manual - Hytec Electronics Ltd

1. The EN bit 15 when set as a 1 will cause the current value of the register to be down loaded to the 10bit digital pot On completion of the write the EN bit is cleared The rest of the contents of the register remain unaltered PD bit when set to 1 loads the digital pot range data held in FPGA flash to registers in the FPGA This is for production use only CWR bit copies wiper register in in digital pot to the non volatile register in digital pot This is for production use only The user can use this register to tweak the gain error of the unit if required This maybe be used to compensate for ambient temperature 5 8 DAC Registers Read write Address Byte 10hex 4Ehex Word 8hex 27hex The 16 DACS are updated from these registers when ARM is set EX bit is zero On completion the ARM bit is cleared Straight binary data format or Twos Complement Code set by BTC bit of CSR Ext register 16 bit code as Hytec 8402 this uses address 10hex to 2Ehex Word 8hex 17hex for channels 1 to 16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS D04 D03 D02 DOI DOO C17 C16 C15 C14 C13 C12 Cll CIO C9 C8 C7 Co C5 C4 C3 C2 18 bit code this uses address 10hex to 4Ehex Word 8hex 27hex i e channel 1 address of low word is 10hex Word 8hex D15 D14 D13 D12 D
2. HYTEC ELECTRONICS Ltd HEAD OFFICE 5 CRADOCK ROAD READING BERKS RG2 0JT UK Telephone 44 0 118 9757770 Fax 44 0 118 9757566 E mail sales hytec electronics co uk Copyright 2010 Hytec Electronics Ltd Data and specifications are subject to change without notice DAC8415 16 CHANNEL 18 BIT DAC INDUSTRY PACK USERS MANUAL PCB Issue 1 0 Firmware Version 8415V102 Document Nos DAC8415 UTM G x 1 1 Date 09 02 2012 Author MRN 6 Hytec Electronics Ltd 8415 UTM G 2 1 1 Revision History The following table shows the revision history for this document Date Version Revision 21 10 10 1 0 Initial release 09 02 12 1 1 Tidy up of manual CRITICAL APPLICATIONS DISCLAIMER THIS PRODUCT FROM HYTEC ELECTRONICS LTD USES COMPONENTS THAT ARE NOT DESIGNED OR INTENDED TO BE FAIL SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL SAFE PERFORMANCE SUCH AS IN LIFE SUPPORT OR SAFETY DEVICES OR SYSTEMS CLASS IIT MEDICAL DEVICES NUCLEAR FACILITIES APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE INDIVIDUALLY AND COLLECTIVELY CRITICAL APPLICATIONS FURTHERMORE SOME COMPONENTS USED IN THIS HYTEC ELECTRONICS LTD PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT UNLESS THERE IS A FAIL SAFE OR REDUNDANCY FEATURE AND A WAR
3. PiD2 Ne Piz N C PLC2 AIG PiD22 33V PIZ2 4 N C C N C ND N C ND N C GND N C IRQ5 3 3V GND IRQ4 N C N C A29 A30 A31 A32 aci iaci lazi lazi A lazi iaz d Al Al Al Al 02 03 04 05 06 07 ND C ND ND ND AS ND M4 07 06 05 04 03 02 0l 5V P1 Pin Assignment IRQ3 IRQ2 IRQI N C aci lazi lasi lazi las T Gl d mee Clr JN uw P1 C29 P1 D29 N C P1 229 3 3V GND N C P1 C30 P1 D30 3 3V P1 230 P1 C31 P1 D31 N C P1 Z31 Page 20 5V P1 C32 P1 D32 45V P1 Z32 6 Hytec Electronics Ltd 8415 UTM G 21 1 1 ROWA SIG ROWB SIG ROWC SIG ROWD P2 A01 P2 B01 P2 C01 B_AGND P2 D01 P2 A02 3 4 B P2 B02 P2 B04 P2 B06 A Chan 2 P2 A0 P2 A0 P2 A0 P2 A06 GND P2 C02 P2 D02 C P2 C04 P2 D04 P2 C06 P2 C07 A Chan 2 N N SIG C 12V C AGND C AGND B Chan 1 B Chan 24 B Chan 2 B Chan 3 ROWZ SIG P2 207 B Chan 3 A Chan 3 P2 C08 A Chan 3 B Chan 4 P2 Z08 GND A Chan 4 P2 C09 A Chan 4 B Chan 5 P2 Z09 BChan4 A Chan 5 P2 A11 P2 A12 P2 A13 P2 A14 P2 A15 P2 A16 P2 A17 P2 A18 P2 A19 P2 A20 P2 A2 P2 A2 P2 A2 P2 A2 P2 A25 P2 A26 P2 B22 A 12V 1 P2A11 P2 A12 P2 A13 P2 AI4 P2 AIS P2 AI6 P2 A17 P2 A18 P2 A19 P2 A20 P2 A21 P2 A2
4. 01 5V 10 0 10V amp 11 0 5V BTC 0 DAC input data straight binary 1 DAC input data twos complement MT Multi trigger mode RP Cycle memory in Multi trigger mode IFW Do not set this bit as setup and calibration data maybe lost This bit enables the FPGA flash write from buffer command EFW Do not set this bit as setup and calibration data maybe lost This bit enables the External flash write by writing to IP mem i e switches off RAM E Do not set this bit as setup and calibration data maybe lost This bit enables the External flash chip or sector erase when do a IP write to mem If IP data is 0x10 then chip erase 64s time taken if IP data is 0x30 then sector erase where the sector address is given in the IP memory address lines If chip erase then IP mem address 0x555 and data 0x10 CAL If set to 1 unit does not use on board flash calibration for register updates only If EX 1 then this has no effect Used for production test EN16 If set to 1 makes the unit same as the Hytec 8402 16 bit DAC This bit can also be set by jumper J3 on PCB Page 10 6 Hytec Electronics Ltd 8415 UTM G 11 1 1 5 7 Digital Potentiometer Data Register Read write Address Byte Chex Word 6hex This is used for calibration only during production test on the units D15 D14 D13 D12 D11 D10 D09 DOS DO7 D06 DOS D04 D03 D02 DO1 DOO EN PD CWR X X X P9 P8 P7 P6 PS P4 P3 P2 Pl PO
5. the NOC operation 5 4 Clock Rate Read write Address Byte 6hex Word 3hex The clock rate register is a four bit register DOO to D03 which enables codes 0 13 to enable frequencies of 1 Hz to 50kHz in multiples of 1 2 5 or 10 E g 0 1Hz 1 2Hz 2 5Hz 3 10Hz and so on to OxD 20KHz OxE 50KHz Each clock pulse will initiate all 16 DAC updates from memory Clock rate Reg Frequency Clock rate Reg Frequency D3 to DO Hz D3 to DO Hz 0000 1 1000 500 0001 2 1001 1MHz 0010 5 1010 2MHz 0011 10 1011 5MHz 0100 20 1100 10MHz 0101 50 1101 20MHz 0110 100 1110 50MHz 0111 200 1111 Page 9 oz Hytec Electronics Ltd 8415 UTM G 10 1 1 5 5 Interrupt Vector Read write Address Byte 8hex Word 4hex The vector register is a 16 bit register which stores the interrupt vector value D15 D14 D13 D12 D11 DIO D09 DOS D07 D06 DOS D04 D03 D02 DO DOO V15 V14 V13 V12 V11 VIO V9 V8 V7 V6 V5 V4 V3 V2 VI VO 5 6 Extended Control amp Status Register CSR Ext Read write Address Byte Ahex Word 5hex This gives added functionality over the 8402 D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DO1 DOO EN16 CAL E EFW IFW RP MT BTC RI RO R This sets range from 00 10V
6. to enable memory updates and ARM to unit with a software command A trigger can then be issued either by a software command or by an external trigger to start down loading the data held in memory to the DACs via the registers as detail above In this mode the registers are updated with new data from the memory at the update clock rate which is derived either internally or externally The memory address is automatically incremented The unit can be programmed to generate an interrupt when memory is Half Full Full or when the programmed number of outputs has occurred When the programmed number of output has occurred the unit will stop and ARM will be cleared In continuous mode when the programmed number of output has occurred the address counter will be zeroed and the output repeated until the ARM bit is cleared or the Cont bit in the CSR is cleared no interrupt generated in continues mode If the Cont bit is cleared the unit will stop when the programmed number of output NOC has been reached The following should be loaded in to the NOC to output whole or half the memory in the following modes Memory Size Mode NOC Values 1MB in CSR Half memory Full Memory 2Mb 18 Bit 0x4000 0x8000 2Mb 16 Bit 0x8000 0x0 1Mb 18 Bit 0x2000 0x4000 1Mb 16 Bit 0x4000 0x8000 When 1Mb is set the only change is when the Full and Half Full memory flags and interrupts occur as shown in the above table The user must ensure t
7. 0080h Base 88 Hytec ID low word 0300h Base 8A Model number 8415h Base 8C Revision 1102h This shows PCB Iss 1 and FPGA firmware at Ver 102 Base 8E Reserved 0000h Base 90 Driver ID 0000h Base 92 Driver ID 0000h Base 94 Flags 0006h This shows 8MHz and 32MHz operation Base 96 No of bytes used 001Ah Base 98 Cal Type 0000h 0 No Calibration factors Base 9A Serial Number xxxxdec Base 9C Not used 0000h Base 9E Not used 0000h Page 13 6 Hytec Electronics Ltd 8415 UTM G 14 1 1 8 POWER UP AND POWER DOWN AND RESET OF 8415 DAC 8 1 Power Up During power up the 8415 outputs should remain approx zero volts with transients as shown below File Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help 2 5 ret Range Change EN ISP ND OUTPUT ry imebase 280 ms Trigger C1 2 00 Vidiv 2 00 Vidiv 10 0 Vidiv 100 msidiv Normal 246V 4 300 V offset 5 200 Y ofst 4 30 V offset 250kS 250 kS s i Positive LeCroy OoOo se 8 2 Power Down At power down the 8415 outputs are not guaranteed to remain steady 8 3IP Reset An IP reset will set the DAC output voltage to zero and set the range to 10V Reset clears the following registers CSR NOC All DAC registers are zeroed Page 14 6 Hytec Electronics Ltd 9 CHANGING RANGE OF 8415 DAC 8415 UTM G 15 1 1 The DAC 8415 powers on in the 10V range When the range is change by writing to bits 0 and 1 of the ExtCSR the DAC will be offline f
8. 11 D10 D09 D08 D07 D06 DOS D04 D03 D02 DOI DOO C15 C14 C13 C12 Cll C10 C9 C8 C7 C6 C5 C4 C3 C2 CI CO i e channel 1 address of high word is 12hex Word 9hex 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C17 C16 D15 D14 D13 D12 D11 D10 DOI D08 D07 D06 DOS D04 D03 D02 DOI DOO 5 9 Digital Potentiometer Calibration Registers Read Address Byte 60hex 66hex Word 30hex 33hex D15 D14 D13 D12 D11 D10 D09 DOS DO7 D06 DOS D04 D03 D02 DO1 DOO X X X X X X P9 P8 P7 P6 PS P4 P3 P2 Pl PO These four registers hold the digital pot calibration factor for each of the DACs voltage ranges The values are loaded at power up from the FPGA flash or when PD bit 14 of the digital pot register 1s set to 1 this is cleared at the finish When the range is changed the data held in the associated register is loaded to the digital potentiometer The calibration values held in the FPGA flash are programmed in during production test The digital pot can still be changed using the Digital Potentiometer Register above but the digital pot will reload its self from the calibration registers on power up and on a range change Page 11 6 Hytec Electronics Ltd 8415 UTM G 12 1 1 6 MULTI TRIGGER AND REPEAT MULTI TRIGGER MODE Multi trigger
9. 2 43 XCIk 12VX 1 19 2 0 45 21 Output11 46 22 47 Output10 AGND AGND 44 23 24 AGND 49 25 Output12 48 DVX NC 1 1 N GND C Es C C GND 2VX GND 2VX GND 2VX GND E GND Outputl3 50 Page 18 oz Hytec Electronics Ltd 8415 UTM G 19 1 1 APPENDIX C HYTEC TRANSITION CARD 8202 CONNECTIONS VO Connector 50 way on transition panel Signal Pin AGND 29 AGND 30 Signal AGND 29 Output4 k AGND ____ 30 Outputs AGND 32 Output 7 AGND 36 Output 11 Output 15 XCLK N XCLK P AGND AGND AGND AGND Pin HEINE 7 8 ME 10 18 25 7 8 9 40 41 42 XTRIG N 43 XTRIG P 45 47 49 50 Page 19 6 Hytec Electronics Ltd 8415 UTM G 20 1 1 APPENDIX D VME64X PIN ASSIGNMENT ON HYTEC 8002 4 IP CARRIER BOARD FOR DAC8415 P0 A19 P0 pin assignment ROWA SIG ROWB SIG ROWC SIG j ROWD SIG ROWE SIG ROWF SIG FORD PO A02 D Chan 4 P0 C02 D Chan 4 PO DO2 D Chan 5 PO E02 D Chan 5 P0 A03 D Chan 6 PO BO3 D Chan 6 PO CO3 D Chan 7 PO DO3 D Chan 7 PO EO3 D Chan 8 P0 A04 D Chan 9 PO CO4 D Chan 9 PO DO4 D Chan 10 PO E04 D Chan 10 P0 A05 P0 B05 D Chan 11 PO CO5 D Chan 12 PO DO5 D Chan 12 PO E05 D Chan 13 PO A06 PO AO7 PO A08 PO A09 PO A10 PO A11 P0 A12 PO A13 PO A1
10. 4 PO A15 PO A16 POAT FOATB PO B19 Po C19 TE Iy PO D19 c AGND PO E19 X6 AR WO PO FIS P1ROWA SIGNAL PI ROWB SIGNAL PI ROWC SIGNAL P1ROWD SIGNAL PI ROWZ SIGNAL AO AO A04 A05 DO1 d BO1 N C Pico Dos PIDOI N C P1 Z01 B02 N C P1 C02 Do9 P1 D02 N C P1 202 B03 B04 d BGOIN BGOOUT N C P1 C03 P1 D03 N C P1 Z03 P1 C04 P1 D04 N C P1 Z04 N C N C A06 BGIIN N C GND A07 BGIOUT N C N C o oo aci laci tazi lazi lazi lazi lazi lazi lazi lazi lazi lazi lazi lazi lazi lazi lazi tata tata La CA LA LALALA Koz keel Eni eA k E a OA a K f Al A 0 5 2 3 9 2 3 0 2 2 2 2 A A A24 N CA DO D D D D GND GND G G G G G en d es rd os ee eel eel eed leek es DTACK IACKIN IACKOUT a BG20UT BG3IN BG30UT c nire EE Et o woo w Q gt A al api ee fee d vleel lolmlElII le e d wua w N asi lazi laz lasi la wait N ies IRQ7 ool ve NJN Un O ON N GND C P1 C09 P1 D09 N C P1 Z09 P1 C10 P1 D10 N C P1 Z10 P1 C11 P1 D11 N C P1 Z11 piele BIA GND P1 C23 AIS P1 D23 P1C24 AA PID24 3 3V P1 224 Ur gt N P1 Z19 G i G P1 Z23 N C N C N C N C AMO AMI AM2 AM3 PICIO Al9 PLDI9 NC GND Piczo als PLD20 53v PLZ20 NC Picar al
11. 5 P2 A26 P2 C10 A Chan 5 ND V C C C C C C P2 D C P2 C20 P2 D20 IC ND P2 C22 P2 D22 IC IC P2 C24 P2 D24 IC C P2 C26 pan P2 D P2 D P2 D P2 D 0 1 2 3 4 5 6 7 8 9 N N B Chan 5 B Chan 6 B Chan 7 B Chan 8 B Chan 8 B Chan 9 B Chan 10 B Chan 11 B Chan 11 B Chan 12 B Chan 13 B Chan 14 B Chan 14 B Chan 15 B Chan 16 N C N C B XTrigger P2 Z10 ND 1 G GND GND ND ND P220 GND P222 GND P2 726 B X Trigger A 12V N C GND A 12V Q B XCLK N C N C P2 A31 Out 3 3V_ P2 B31 P2 A32 P2 B32 P2 pin assignment z zz z O GND 5V P2 C31 Out 3 3V P2 D31 P2 C32 Out 5V P2 D32 B XCLK GND PC 5V GND Denotes pins with thickened tracks which can be used for power inputs Page 21
12. D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DO1 DOO C15 C14 C13 C12 C11 C10 C9 C8 C7 Co C5 C4 C3 C2 CI CO 5 3 Number of updates NOC Read write Address Byte 4hex Word 2hex The number of updates register allows the number of updates per trigger to be programmed If the memory buffer size is exceeded the update values will wrap around from the upper memory to the base of the lower memory D15 D14 D13 D12 D11 D10 D09 DOS D07 D06 DOS D04 D03 D02 DO1 DOO N15 N14 N13 NI2 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 NI NO If the CONT bit 1 set in CSR then the set number of outputs is output continuously If CONT not set then set nos bit output then the TRIGEN is cleared CC in the CSR needs to be cleared before a further trigger is seen The following should be loaded in to the NOC to output whole or half the memory in the following modes NOC Values Mode Half Full Full 18 Bit 2Mb 0x4000 0x8000 16 Bit 2Mb 0x8000 0x0 18 Bit 1Mb 0x2000 0x4000 16 Bit 1Mb 0x4000 0x8000 When 1Mb is set it only changes when the Full and Half Full flags and interrupts occur as shown in the above table The user must ensure that the correct NOC value is entered as the setting of the 1Mb in the CSR does not effect
13. L POTENTIOMETER CALIBRATION REGISTERS sees ese ee ee ee se ee ee ee ee ee ee ee ee ee ee ee ee ee ee 11 6 MULTI TRIGGER AND REPEAT MULTI TRIGGER MODE 06000000000000000 000000000000 00000 0000o 12 6 1 MULTI Mites Ne N EE OE N EE N N 12 6 2 REPEAT MULTI TRIGGER MODE iese sesse ee ee ee E Gee Gee Re ee Re Gee ga d a TG ee Re ee a 12 Ts ID oU soete sesse se Ee O 13 8 POWER UP AND POWER DOWN AND RESET OF 8415 DAC sees sees see es ge ss ges gee ig 14 8 1 POWERUBR A Ee AE SE E N EE Re EA ATR re nn 14 82 POWER DO EE EE EE EE e e NE OE EE EN NE 14 8 3 dad RE EA ia 14 9 CHANGING RANGE OF 8415 DAC sesse esse ese esse ese ee see gese ee Ge bee bee etse Ge Ge ee ee Ge Ge Ge ge e 15 10 RANGE RESOLUTION AND INSTALLATION CONSIDERATIONGS 00000000000000000000000000 16 11 EPICS AND ASYN SOFTWARE DRIVER PLUS LINUX WINDOWS API 16 12 SELECTION OF THE 12 VOLT POWER SUPPLY o nconcccnonononocinncnononononcnonconoononononoconoconos 16 AAA EE RR EE N EE 17 APPENDIX EE DE RO EE cena 18 APPENDIX ERAS Ed CPI N Ee dan anana 19 APPENDINK mec 20 Page 3 Hytec Electronics Ltd 8415 UTM G 4 1 1 1 INTRODUCTION The Hytec IP DAC 8415 is a single width Industry Pack that provides 16 channels of simultaneously updated digital to analogue conversion with the following characteristics 16 independently programmed channels 18 bits resolution 18 bits monotonic 16 or 18 bit operation se
14. NING SIGNAL UPON FAILURE TO THE OPERATOR THE CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF HYTEC ELECTRONICS LTD PRODUCT IN CRITICAL APPLICATIONS Page 2 Hytec Electronics Ltd 8415 UTM G 3 1 1 CONTENTS Ti INTRODUCTION er 4 2 PRODUCT SPECIFICATIONS eere ect ve ee gee ego ge ee ee gee va oge ge sees Vee vac ona ee ke ie ee ee Nep ee va ee sed e sve eva 5 3 COPERATING MODES ete 94559970675098 Ee ee ee epe eee ee od ee gee ee eg Ge ee ee de Ge ee ee sage ee ee dei 6 3 1 USING REGISTER TO UPDATE DACS 0000000000700000 ee see ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee entes 6 32 USING MEMORY TO UPDATE DACS ees esse esse see ee se ee ese ee ee ee ga a Gee Gee GR ee Re Re ee ee 6 4 MEMORY ALLE OE N RE EE EE ER RO ED 7 5 APPLICATION REGISTERS 60005008909090 6099 0900000080000000 nga o ke oe eke dees een ee seed cere asbes ee ee ee 8 5 1 CONTROL amp STATUS REGISTER CSR esses ener anaa nenanem anana entrent nns 8 5 23 MEMORY POINTER idee A OR P HR Ferr Reti e ER te de f De teases 9 5 3 NUMBER OFUPDATES NOC 00 is 9 5 4 oCLOGK RATE coin St HER CIRCE E TU EE EE OE ite tate ers 9 5 5 INTERRUPT VECTOR encina dd aii 10 5 6 EXTENDED CONTROL amp STATUS REGISTER CSR EXT eene 10 5 7 DIGITAL POTENTIOMETER DATA REGISTER iese see ee ees see ese ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee eg 11 0 SAC REGISTERS ceria ALI INS de ae i EA ON alana AE eii E 11 5 9 DIGITA
15. cation Registers 5 1 Control amp Status Register CSR Read Write Address Byte Ohex Word Ohex D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS DO4 D03 D02 DO DOO ARM EX ST XC ET EE FE HE BS SSU IMB MH CONT CC F HF ARM Writing a 1 to ARM bit causes the values loaded in to the DAC registers or the memory to be loaded in to the DACs When all the DACs have been updated from the registers the EX bit set to 0 the ARM bit is cleared If the DACs are being updated from the memory the EX bit set to 1 the ARM bit is not cleared In this mode if a number of triggers occur which cause the end of the memory to be reached a subsequent trigger will cause the memory pointer to wrap around to the start of memory EX Enable trigger and memory update EX 0 The outputs will be loaded from the DAC registers EX 1 Allows external trigger or software trigger to initiate programmed updates from memory In this mode the Number Of Updates Register NOC needs to be set between 0 to 64K updates ST Software trigger Triggers the programmed number of updates from the memory as set by the Number of Updates register XC Enable the external clock 0 internal clock used for the sample rate 1 external clock used for the sample rate ET When set to 1 enables Inhibiting via the Lemo of the 8002 via the IP Strobe line The Inhibit
16. hat the correct NOC value is entered as the setting of the 1Mb in the CSR does not effect the NOC operation Page 6 Hytec Electronics Ltd 4 Memory Map On board RAM Memory is 1M x 16 bits 64K samples per channel for 16bits 32K for 18bits When used in the sixteen bit mode there are two main buffer memories of 512k updates each lower and upper buffers These are each divided into sixteen segments allocated to updates for DACI to DACI6 8415 UTM G 7 1 1 When DACI6 has been updated from the top of the lower buffer the Half memory Flag status is set and when it has been updated from the top of the upper memory buffer the Full Flag status is set Lower Conversion Memory Upper Conversion Memory DAC16 conversions DAC16 conversions DAC15 conversions DAC15 conversions DAC14 conversions DAC14 conversions DAC13 conversions DAC13 conversions DAC12 conversions DAC12 conversions DAC11 conversions DAC11 conversions DAC10 conversions DAC10 conversions DAC9 conversions DAC9 conversions DAC8 conversions DAC8 conversions DAC7 conversions DAC7 conversions DAC6 conversions DAC6 conversions DAC5 conversions DAC5 conversions DACA conversions DACA conversions DAC3 conversions DAC3 conversions DAC2 conversions DAC2 conversions DAC1 conversion 16k bits16 17 DAC1 conversion 16k bits O 15 DAC1 conversio
17. lectable by hardware or software On board RAM Memory 1Meg x 16 bits 64K samples for 16bits 32K samples for 18bits 10V full scale output range 5V full scale output range 0 to 10V full scale output range 0 to 5V full scale output range Ranges software selectable 10mA current drive capability with continuous short circuit protection Drives capacitive loads to 10000pF Straight binary or Two Complement input code Internal External update clock rates Internal update clock rates programmable 50KHz 20KHz 10KHz 5KHz 2KHz 1KHz 500Hz 200Hz 100Hz 50Hz 20Hz 10Hz 5Hz 2Hz and 1Hz Maximum 64KHz external clock rate Simultaneous up date Power on disable outputs set to OV on boot up System to plant isolation to 100V when externally powered Board type Board serial number PCB issue and firmware version held on ROM External Triggering Continuous function generation Multi Trigger Mode Repeat Multi Trigger Mode Field upgradeable firmware requires Xilinx compatible device to program built in FPGA flash memory via the FPGA JTAG port The units are factory set to have an output range of 10V on power up Page4 Hytec Electronics Ltd 8415 UTM G 5 1 1 2 PRODUCT SPECIFICATIONS Size Operating temp Number of channels DAC resolution Data format 10V Data format 5V Data format 0 10V Data format 0 5V Output current Capacitive load Short circuit duration OverV withstand U
18. mode is set by bit 4 MT in the Ext CSR This allows the user to repeatedly trigger the unit The number of updates is set by the NOC register When the unit is triggered and the required number of updates output the CC flag in the CSR is set and the unit stopped 6 1 Multi Trigger Mode In this mode the memory address pointer is not cleared On the subsequent triggers the CC flag is cleared then at the end of the number of update is reset If the half full or full points of the memory are reached then the half Full and Full Flags will be set If memory reaches full it will wrap a round and repeat either with the next trigger or 1f number of updates take it over the memory full then it will wrap Also the memory Half Full and Full flags will NOT be cleared once set D A Multi Trigger Mode C O CM 1 RP 0 u t 1 p u t i f r 1 o i i m i M i e i i m 1 i o i i r 1 i y i T1 T2 T3 T4 6 2 Repeat Multi Trigger Mode Repeat multi trigger mode is set by bit 5 RP in Ext CSR In repeat multi trigger mode the address pointer is cleared on each trigger Repeat Multi Trigger Mode C CM 1 RP 1 Oo u t p u t f r o m M e m o r y Page 12 6 Hytec Electronics Ltd 8415 UTM G 13 1 1 7 ID PROM The ID data is stored in Flash memory The word addresses are as below Base 80 ASCII VI 5649h Base 82 ASCII TA 5441h Base 84 ASCII 4 3420h Base 86 Hytec ID high byte
19. n 16k 1 bits16 17 DAC1 conversion 16k 1 bits O 15 DAC1 conversion 2 bits16 17 DAC1 conversion 2 bits O 15 DAC1 conversion 1 bits16 17 DAC1 conversion 1 bits O 15 DAC1 conversion 32k bits16 17 DAC1 conversion 32k bits O 15 DAC1 conversion 32k 1 bits16 17 DAC1 conversion 32k 1 bits O 15 DAC1 conversion 16k 2 bits16 17 DAC1 conversion 16k 2 bits O 15 DAC1 conversion 16k 1 bits16 17 DAC1 conversion 16k 1_ bits O 15 18 Bit Mode Lower Conversion Memory Upper Conversion Memory DAC16 conversions DAC16 conversions DAC15 conversions DAC15 conversions DAC14 conversions DAC14 conversions DAC13 conversions DAC13 conversions DAC12 conversions DAC12 conversions DAC11 conversions DAC11 conversions DAC10 conversions DAC10 conversions DAC9 conversions DAC9 conversions DAC8 conversions DAC8 conversions DAC7 conversions DAC7 conversions DAC6 conversions DAC6 conversions DAC5 conversions DAC5 conversions DACA conversions DACA conversions DAC3 conversions DAC3 conversions DAC2 conversions DAC2 conversions DAC1 conversion 32k DAC1 conversion 32k 1 DAC1 conversion 2 DAC1 conversion 1 DAC1 conversion 64k DAC1 conversion 64k 1 DAC1 conversion 32k 2 DAC1 conversion 32k 1 16 Bit Mode Page 7 6 Hytec Electronics Ltd 8415 UTM G 8 1 1 5 Appli
20. n be derived either internally from the carrier card or from an external source via a transition card The source is selected using jumpers J1 J2 and the GND AGND link LNK1 where J1 External 12V connect 1 amp 2 Internal 12V connect 2 amp 3 J2 External 12V connect 1 amp 2 Internal 12V connect 2 amp 3 LNK1 GND AGND IN for internal 12V OUT for external 12V supplied from transition card DC DC converter Page 16 oz Hytec Electronics Ltd 8415 UTM G 17 1 1 APPENDIX A PCB JUMPERS Issue 1 PCB J1 External 12V connect 1 amp 2 Internal 12V connect 2 amp 3 J2 External 12V connect 1 amp 2 Internal 12V connect 2 amp 3 J3 Sets 16bit mode when IN This overrides the EN16 bit in the CSR Ext Factory set OUT J4 Not used Jumper for J3 located here for shipment LNK 1 Factory set IN links VME GND and AGND Page 17 Hytec Electronics Ltd APPENDIX B I O Connector PL2 50 way on 8415 DAC PCB 8415 UTM G 18 1 1 Pin Signal P N m AGND w Output 2 AGND N Outputl4 Output15 in y Output 1 26 AGND ND Un de SYN G2 m Output 3 AGND Go r2 r2 e wo AGND Output16 Output 4 32 ve o gt GND Output 5 AGND Output 6 33 34 XTrigger mm N oO 13 Output 7 14 AGND 39 15 AGND Output 8 Y G2 Go IE W eoo N N XTrigger N N XCIk 16 17 Output9 18 AGND AGND 40 41 4
21. or approx 20mS During this time the DAC output will be zeroed and the new reference and offset voltages applied During this process the output may glitch as shown in the following scope shots Two glitches can occur as shown in the scope shot below e Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help x 2 00 Vidiv 10 0 Vidiv 5 00 msidiv Normal 34v OmV offset 32 50 V offset 100 ks PILES EI Positive LeCroy AT First glitch will be negative 2 5V if going to 10V range or negative 5V if going to 5V File Vertical Timebase Trigger Di asure Math A Utilities Help 2 00 Vidiv 10 0 Vidiv 10 0 psidiv Stop 34V OmV offset 28 70 V offset 200MS 20 GS s Edge Positive m ES Xi 4879995us AX 000ns 1 ES t X2 4979995 us 1 AX LeCroy 8 4 2010 11 33 49 AM The second glitch will be 5V if going to 10V range or 2 5V if going from to 5V le Vertical Timebase Trigger Display Cursors Measure Math Analysis Utilities Help 1 44 mV X 4859995us AX 0 00ns T Ea UI X2 48 598995 us 1 AX LeCroy B 2 00 Viiv 10 0 V div 10 0 usiciv Normal 188v Om offset 34 30 Voffset Hof CESTO 1 80 mV BLY Page 15 6 Hytec Electronics Ltd 8415 UTM G 16 1 1 When going from 5V to 0 10V then only first glitch to 2 5V When going from 0 10V to 5V only second glitch at 2 5V When going from 10V to 0 5V then only first glitch to 5V When going from 0 5V
22. pdate rate Power quiescent Isolation DAC device Integral non linearity Offset error Offset drift Gain error Gain drift Output slew rate Single width Industry Pack 1 8ins x 3 9 ins 0 to 45 deg C ambient 16 18 bits 18 bits straight binary Code format 20h 10v 20000h OV and 3FFEOh 10V 18 bits straight binary Code format 40h 5v 20000h OV and 3FFCOh 5V 18 bits straight binary Code format 0000h OV and 3FFCOh 10V 18 bits straight binary Code format 0000h OV and 3FFCOh 5V 10mA FS Stable up to 10000pF Continuous No internal protection from external voltages provided 64KHz max 5V 350mA typical 12V 150mA typical 12V 100mA typical 100V via opto isolators if externally powered by HYTEC 8912 Texas Instruments DAC9881SB with serial interface 1LSBs typ 2LSBs max 32LSBs without calibration 2LSBs after firmware calibration at 25 deg C ambient Guaranteed for 10V range only 0 8 ppm per deg C typical 32LSBs without calibration 2LSBs after firmware calibration at 25 deg C ambient Guaranteed for 10V range only 10V range 2 ppm per deg C typical 5V range 4 ppm per deg C typical 0 10V range 2 ppm per deg C typical 0 5V range 0 8 ppm per deg C typical 1 6V us typ Page 5 Hytec Electronics Ltd 8415 UTM G 6 1 1 3 Operating Modes There are two operating modes 1 Registered the DAC outputs are controlled b
23. signal when set stops updating the DAC from memory EE Enables interrupt at end of programmed number of DAC updates from memory FE Enables interrupt when the upper conversion memory has been filled Memory Full HE Enables interrupt when the lower conversion memory has been filled Memory Half Full BS Busy status Flag showing unit is busy shifting data to DAC s or in process of changing range SSU Writing a 1 will set all DAC outputs to zero this bit is auto cleared on completion 1MB Enable 1Mb memory 32K values channel when logic 1 and 2Mb 64K values channel when logic O MH Set to 1 when the memory is inhibited from the IP Strobe line and ET is set CONT Sets continuous function generation cc Conversions complete Status bit set when the number of programmed updates has been completed Generates IRQO if set and EE is set to a logic 1 F Full status Set when DAC16 has been updated from the top of memory Generates IRQO if set and FE is set to a logic 1 HF Half full status Set when DAC16 has been updated from the top of the lower memory buffer Generates IRQO if set and HE is set to a logic 1 Page 8 6 Hytec Electronics Ltd 8415 UTM G 9 1 1 5 2 Memory Pointer Read write Address Byte 2hex Word lhex The Memory pointer is the number of updates held in the memory The current conversion address is given by the Memory pointer address offset by the DAC number and the Full status D15 D14
24. to 10V only second glitch at 5V When going from 10V to 0 10V then only first glitch to 5V When going from 0 10V to 10V only first glitch at 5V When going from 5V to 0 5V then only first glitch to 2 5V When going from 0 5V to 5V only first glitch at 2 5V When going between 0 5V and 0 10V no glitches occur 10 RANGE RESOLUTION AND INSTALLATION CONSIDERATIONS The following table shows the resolution per range Range Resolution 10V 76 312576uV 5V 38 165608uV 10V 38 156288uV 5V 19 078144uV Due to the high resolution and linearity of the DAC system design problems such as grounding and contact resistance become very important For this 18bit converter with a 20V full scale range 1LSB is 76 312576uV With a load current of 5mA series wiring and connector resistance of only 60mohms will cause an output error of 2LSBs To put this in contexts the resistance of 23 wire is about 0 067ohms meter Neglecting contact resistance less than 1 meter of wire will produce an error greater than 2LSBs in the analogue output voltage 11 EPICS and ASYN Software Driver Plus Linux Windows API EPICS and ASYN software drivers are in avalable for the DAC8415 16 channel DAC Industry Pack For downloads go to www hytec electronics co uk Download aspx A Linux Windowa API is available consult Hytec for details 12 SELECTION OF THE 12 VOLT POWER SUPPLY The DAC 8415 12 volt power supply ca
25. y the contents of the DAC registers 2 Memory the DAC outputs are updated for the programmed number of samples at the programmed clock rate from the RAM memory All the outputs are updated serially but change together there will be slight changes due to differences in the slew rate of the amplifiers about 1uS at the end of an internal update cycle The outputs may be updated at a rate of up to 64K Hz The two methods to update the 8415 DACs are detailed below 3 1 USING REGISTER TO UPDATE DACs For this mode set EX 0 and ARM 1 in the CSR In 18bit mode there are two registers per DAC channel giving a torla of 32 registers These can be loaded one at a time the module can then be ARMed and the data from the registers will be serially loaded from one DAC to the next until all the data has been passed to the DACs At this point the DAC outputs are automatically updated giving 16 simultaneous outputs Then ARM bit is cleared In this mode the output sample clock is not used as the output is set when ARM is set All the outputs change together 3 2USING MEMORY TO UPDATE DACs To select this mode set the following bits EX 1 ARM 1 in the CSR Trigger using software trigger ST or external hardware trigger In this method the memory is first loaded with the required data and the number of memory locations used is entered in to the Number of Updates NOC register The Control and Status Register CSR is then set

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