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ST ST10R165 User Manual

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1. m m sia m Segment x Address l l I 3 weg ES AE IN BUS PO L MCTC Wait States 1 15 124 254 MCT02063 SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 PROGRAMMABLE BUS CHARACTERISTICS Cont d Programmable Memory Tri State Time The ST10R165 allows the user to adjust the time between two subsequent external accesses to ac count for the tri state time of the external device The tri state time defines whenthe external device has released the bus after deactivation of the read command RD The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers by in troducing a waitstate after the previous bus cycle see figure above During this memory tri state Figure 7 8 Memory Tri State Time time wait state the CPU is not idle so CPU oper ations will only be slowed down if a subsequent external instruction or data fetch operation is re quired during the next instruction cycle The memory tri state time waitstate requires one CPU clock 50 ns at fcpu 20 MHz and is con trolled via the MTTOx bits of the BUSCON regis ters A waitstate will be inserted if bit MTTCx is 0 default after reset Note External bus cycles in multiplexed bus modes implicitly add one tri state time wait state in addition to the p
2. 213 254 13 System Reset ST10R165 Notes 214 254 SGS THOMSON a8 Viuexos serROMYGS wr SGS THOMSON STi0R165 User Manual YZ MICROELECTRONICS Chapter 14 POWER REDUCTION MODES Two different power reduction modes with differ ent levels of power reduction have been imple mented in the ST10R165 which may be entered under software control In Idle mode the CPU is stopped while the pe ripherals continue their operation Idle mode can be terminated by any reset or interrupt request In Power Down mode both the CPU and the pe ripherals are stopped Power Down mode can only be terminated by a hardware reset Note All external bus actions are completed be fore Idle or Power Down mode is entered However Idle or Power Down mode is not entered if READY is enabled but has not been activated driven low during the last bus access 14 1 IDLE MODE The power consumption of the ST10R165 micro controller can be decreased by entering Idle mode In this mode all peripherals including the watchdog timer continue to operate normally only the CPU operation is halted Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed To prevent unin tentional entry into Idle mode the IDLE instruction has been implemented as a protected 32 bit in struction March 1995 Idle mode is terminated by interrupt requests from any enabled
3. 26 254 selected by the specified PEC channel number is accessed independent of the current DPP register contents and also the locations referred to by these pointers are accessed independent of the current DPP register contents If a PEC channel is not used the corresponding pointer locations area available and can be used for word or byte data storage For more details about the use of the source and destination pointers for PEC data transfers see section Interrupt and Trap Functions Yy 00 FCFE H 77 00 FCEOY fa OO FDDEY Internal RAM 00 F 6004 OO FSFEy MCAQ2266 SGS THOMSON YA MICROELECTRONICS INTERNAL RAM AND SFR AREA Cont d Special Function Registers The functions of the CPU the bus interface the IO ports and the on chip peripherals of the ST10R165 are controlled via a number of Special Function Registers SFRs These SFRs are ar ranged within two areas of 512 Byte size each The first register block the SFR area is located in the 512 Bytes above the internal RAM 00 FFFFh 00 FEOOh the second register block the Extended SFR ESFR area is located in the 512 Bytes below the internal RAM 00 F1FFh 00 F000h Special function registers can be addressed via in direct and long 16 bit addressing modes Using an 8 bit offset together with an implicit base address allows to address word SFRs and their respective low bytes However this does not work for the re spective high by
4. I MCTO2066 1 The data drivers from the previous bus cycle should be disabled when the RD signal becomes active 126 254 SGS THOMSON YA MICROELECTRONICS 7 4 READY CONTROLLED BUS CYCLES For situations where the programmable wait states are not enough or where the response ac cess time of a peripheral is not constant the ST10R165 provides external bus cycles that are terminated via a READY input signal synchro nous or asynchronous In this case the ST10R165 first inserts a programmable number of waitstates 0 7 and then monitors the READY line to determine the actual end of the current bus cycle The external device drives READY low in order to indicate that data have been latched write cycle or are available read cycle The READY function is enabled via the RDYENx bits in the BUSCON registers When this function is selected RDYENx 1 only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates 0 7 while the MSB of bit field MCTC selects the READY operation Figure 7 10 READY Controlled Bus Cycles Bus Cycle 7 External Bus Interface ST10R165 MCTC 3 0 Synchronous READY ie the READY signal must meet setup and hold times MCTC 3 1 Asynchronous READY ie the READY signal is synchronized internally The synchronous READY provides the fastest bus cycles but requires setup and hold times to be met The CLKOUT signal
5. 2 verbe y ee le oss SOTBIC F19Ch CEh 15 14 18 12 11 10 9 8 m cope p Xe LS CURE RETE ey tmr The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control register SOCON Note In contrary to the error interrupt request flag SOEIR the error status flags SOFE SOPE SOOE are not reset automatically upon en try into the error interrupt service routine but must be cleared by software Reset Value 00h 7 6 5 4 3 2 1 0 SOTIR SOTIE ILVL GLVL rw Reset Value 00h 7 6 so so TBIR TBIE ILVL GLVL rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields ky 3 SON MICROELECTRONICS 179 254 9 Asynchronous Synchronous Serial Interface ST10R165 ASCO INTERRUPT CONTROL Cont d Using the ASCO Interrupts For normal operation ie besides the error inter rupt the ASCO provides three interrupt requests to control data exchange via this serial channel SOTBIR is activated when data is moved from SOTBUF to the transmit shift register SOTIR is activated before the last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has been transmitted SORIR is activated when the received frame is moved to SORBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two inter
6. rea Data Page 0 00 0000j System Segment 0 64 KByte 2 Memory Organization ST10R165 e System Stack programmable size e General Purpose Register Banks GPRs e Source and destination pointers for the Peripher al Event Controller PEC e Variable and other data storage or e Code storage OO FFFFy O0 FEOO 4 Internal RAM O0 F600 y Reserved 00 F200 y 77 r rea 00 F 000 RAM SFR Area 4 KByte MCA02233 Note The upper 256 bytes of SFR area ESFR area and internal RAM are bit addressable see shaded blocks in the figure above SGS THOMSON YA MICROELECTRONICS 23 254 2 Memory Organization ST10R165 INTERNAL RAM AND SFR AREA Cont d Code accesses are always made on even byte ad dresses The highest possible code storage loca tion in the internal RAM is either OO FDFER for sin gle word instructions or 00 FDFCh for double word instructions The respective location must contain a branch instruction unconditional because se quential boundary crossing from internal RAM to the SFR area is not supported and causes errone ous results Any word and byte data in the internal RAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address The highest possible word data storage location in the internal RAM is 00 FDFEh For PEC data transfers the internal RAM can
7. SSCON Register with SSCEN 0 SSCCON FFB2h D9h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC ssc ssc ssc ssc ssc ssc ssc SSC EN 0 MS AREN BEN PEN REN TEN PO PH HB SSCBM rw rw m rw rw rw rw rw rw rw rw rw Bit Function Programming Mode SSCEN 0 SSC Data Width Selection 0 Reserved Do not use this combination 1 15 Transfer Data Width is 2 16 bit lt SSCBM gt 1 SSCHB SSC Heading Control Bit 0 Transmit Receive LSB First 1 Transmit Receive MSB First SSCPH SSC Clock Phase Control Bit 0 Shift transmit data on the leading clock edge latch on trailing edge T4 Latch receive data on leading clock edge shift on trailing edge SSCPO SSC Clock Polarity Control Bit 0 Idle clock line is low leading clock edge is low to high transition 15 Idle clock line is high leading clock edge is high to low transition SSCTEN SSC Transmit Error Enable Bit 0 Ignore transmit errors T Check transmit errors SSCREN SSC Receive Error Enable Bit 0 Ignore receive errors des Check receive errors SSCPEN SSC Phase Error Enable Bit 0 Ignore phase errors 1 Check phase errors SSCBEN SSC Baudrate Error Enable Bit 0 Ignore baudrate errors 15 Check baudrate errors SSCAREN SSC Automatic Reset Enable Bit 0 No additional action upon a baudrate error The SSC is automatically reset upon a baudrate error SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clo
8. T5CLR 1 Timer 5 Capture Mode Enable T5SC 0 T5SC 1 For the effects of bits TXUD and TxUDE refer to the direction table see T6 section SGS THOMSON YA MICROELECTRONICS Timer 5 Mode Control Basic Operating Mode Gated Timer with Gate active low Gated Timer with Gate active high Timer Counter 5 stops Timer Counter 5 runs Timer 5 External Up Down Enable Positive transition rising edge on CAPIN Negative transition falling edge on CAPIN Any transition rising or falling edge on CAPIN Timer 5 not cleared on a capture Timer 5 is cleared on a capture Capture into register CAPREL Disabled Capture into register CAPREL Enabled 161 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT2 Cont d Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6 The description and the table apply according ly Timer T5 in Timer Mode or Gated Timer Mode When the auxiliary timer T5 is programmed to tim er mode or gated timer mode its operation is the same as described for the core timer T6 The de scriptions figures and tables apply accordingly with one exception e There is no output toggle latch and no alternate output pin for T5 Timer T5 in Counter Mode Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in register T5CON to 001b In counter mo
9. e PORTO goes into high impedance floating e PORT if used for the bus interface drives the address used last e Port 4 the activated pins drives the segment ad dress used last e Port 6 drives the CS signal corresponding to the address see above if enabled e ALE remains inactive low e RD WR remain inactive high 7 7 EXTERNAL BUS ARBITRATION In high performance systems it may be efficient to share external resources like memory banks or peripheral devices among more than one control ler The ST10R165 supports this approach with the possibility to arbitrate the access to its external bus ie to the external devices SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 This bus arbitration allows an external master to request the ST10R165 s bus via the HOLD input The ST10R165 acknowledges this request viathe HLDA output and will float its bus lines in this case The CS outputs may provide internal pullup devices The new master may now access the pe ripheral devices or memory banks via the same in terface lines as the ST10R165 During this time the ST10R165 can keep on executing as long as it does not need access to the external bus All ac tions that just require internal resources like in struction or data memory and on chip peripherals may be executed in parallel When the ST10R165 needs access to its external bus while it is occupied by another bus master it demands it via the BRE
10. for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right op eration can be estimated up to a quantity of one half of the LSB ofthe result In conjunction with the V flag the C flag allows evaluating the rounding error with a finer resolution see table below For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit oper ations with two operands the V flag represents the logical ORing of the two specified bits Shift Right Rounding Error Evaluation C V l 0 0 z No rounding error LSB 1 2 LSB gt 1 2 LSB 0 1 0 lt Rounding error 1 0 Rounding error 1 1 Rounding error 45 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d e Z Flag The Z flag is normally set to 1 if the re sult of an ALU operation equals zero otherwise it is cleared For the addition and substraction with carry the Z flag is only set to 1 if the Z flag already contains a 1 and the result of the current ALU operation additionally equals zero This mechanism is pro vided for the support of multiple precision calcula tions For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bit operations with two operands the Z flag repre sents the logical NORing of the two specified bits For the prioritize ALU operati
11. the data width can be chosen from 2 to 16 bits transfer may start with the LSB or the MSB the shift clock may be idle low or idle high data bits may be shifted with the leading or trail ing edge of the clock signal the baudrate may be set from 152 Bd upto 5 MBd 20 MHz CPU clock the shift clock can be generated master or re ceived slave This allows to adapt the SSC to a wide range of applications where serial data transfer is re quired The Data Width Selection allows to transfer frames of any length from 2 bit characters up to 16 bit characters Starting with the LSB SS CHB 0 allows to communicate eg with ASCO devices in synchronous mode ST10 family or 8051 like serial interfaces Starting with the MSB SSCHB 1 allows to operate compatible with the SPI interface Regardless which data width is selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in regis ters SSCTB and SSCRB with the LSB of the transfer data in bit O of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of SSCTB are ignored the unselected bits of SSCRB will be not valid and should be ignored by the receiver serv ice routine The Clock Control allows to adapt transmit and receive behaviour of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out
12. BUS PO DKO l Dota KX Address YX 1 Dato wr ui A nfl l N LLL I l l l l l MCTO2234 118 254 S7 SGS THOMSON YA MICROELECTRONICS EXTERNAL BUS MODES Cont d External Data Bus Width The EBC can operate on 8 bit or 16 bit wide exter nal memory peripherals A 16 bit data bus uses PORTO while an 8 bit data bus only uses POL the lower byte of PORTO This saves on address latches bus transceivers bus routing and memo ry cost on the expense of transfer time The EBC can control word accesses on an 8 bit data bus as well as byte accesses on a 16 bit data bus Word accesses on an 8 bit data bus are auto matically split into two subsequent byte accesses where the low byte is accessed first then the high byte The assembly of bytes to words and the dis assembly of words into bytes is handled by the EBC and is transparent to the CPU and the pro grammer Byte accesses on a 16 bit data bus require that the upper and lower half of the memory can be ac cessed individually In this case the upper byte is selected with the BHE signal while the lower byte is selected with the AO signal So the two bytes of the memory can be enabled independent from each other or together when accessing words When writing bytes to an external 16 bit device which has a single CS input but two WR enable inputs for the two bytes the EBC can directly generate these two write con
13. Data Input Output Registers Note E ESFR located in the ESFR space March 1995 Direction Control Registers Open Drain Control Registers 85 254 This is advanced information from SGS THOMSON Details are subject to change without notice 5 Parallel Ports ST10R165 In the ST10R165 certain ports provide Open Drain Control which allows to switch the output driver of a port pin from a push pull configuration to an open drain configuration In push pull mode a port output driver has an upper and a lower transistor thus it can actively drive the line either to a high or a low level In open drain mode the upper transis tor is always switched off and the output driver can only actively drive the line to a low level When writing a 1 to the port latch the lower transistor is switched off and the output enters a high imped ance state The high level must then be provided by an external pullup device With this feature it is possible to connect several port pins together to a Wired AND configuration saving external glue logic and or additional software overhead for ena bling disabling output signals This feature is implemented for ports P2 P3 and P6 see respective sections and is controlled through the respective Open Drain Control Regis ters ODPx These registers allow the individual bit wise selection of the open drain mode for each port line If the respective control bit ODPx y is 0 default afte
14. General Purpose Timer Units ST10R165 The timer input frequencies resolution and peri ods which result from the selected prescaler op tion when using a 20 MHz CPU clock are listed in the table below This table also applies to the Gat ed Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits Figure 8 3 Block Diagram of Core Timer T3 in Timer Mode Interrupt v Reaueet TxOTL fee 0 TxOUT TxOE MCB02028 GPT1 Timer Input Frequencies Resolution and Periods fopu 20MHz Prescalerfactor s 16 22 Timer Input Selection T21 T31I TAI Timer Input Selection T21 T31 TA O 128 512 1024 128 256 512 1024 Input Frequency 2 5 1 25 E CE 5 156 25 78 125 39 06 19 53 MHz MHz kHz kHz kHz kHz kHz kHz SGS THOMSON YA MICROELECTRONICS 143 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 010b or 011b Bit T3M 0 T3CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the ex ternal input pin T3IN Timer T3 External Input which is an alternate function of P3 6 To enable this
15. In asynchronous mode 8 or 9 bit data frames are transmitted or received preceded by a start bit and terminated by one or two stop bits For multi processor communication a mechanism to distin guish address from data bytes has been included 8 bit data plus wake up bit mode In synchronous mode the ASCO transmits or re ceives bytes 8 bits synchronously to a shift clock which is generated by the ASCO The SSC trans mits or receives characters of 2 16 bits length synchronously to a shift clock which can be gener ated by the SSC master mode or by an external master slave mode The SSC can start shifting with the LSB or with the MSB while the ASCO al ways shifts the LSB first A loop back option is available for testing purpos es SGS THOMSON YA MICROELECTRONICS THE ON CHIP PERIPHERAL BLOCKS Cont d A number of optional hardware error detection ca pabilities has been included to increase the relia bility of data transfers A parity bit can automatical ly be generated on transmission or be checked on reception Framing error detection allows to rec ognize data frames with missing stop bits An overrun error will be generated if the last charac ter received has not been read out of the receive buffer register at the time the reception of a new character is complete General Purpose Timer GPT Unit The GPT units represent a very flexible multifunc tional timer counter structure which may be used for man
16. TIMER BLOCK GPT2 Cont d Count Direction Control The count direction of the core timer can be con trolled either by software or by the external input pin T6EUD Timer T6 External Up Down Control Input which is the alternate input function of port pin P5 10 These options are selected by bits T6UD and T6UDE in control register T6CON When the up down control is done by software bit T6UDE 0 the count direction can be altered by setting or clearing bit TeUD When T6UDE 1 pin T6EUD is selected to be the controlling source of the count direction However bit T6UD can still be used to reverse the actual count direction as shown in the table below If T6 UD 0 and pin T6EUD shows a low level the timer is counting up With a high level at T6EUD the timer is count ing down If TEUDz 1 a high level at pin T6EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is run ning or not GPT2 Core Timer T6 Count Direction Control 8 General Purpose Timer Units ST10R165 Timer 6 Output Toggle Latch An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON T6OTL can also be set or reset by software Bit T6OE Alternate Output Function Enable in regis ter T6CON enables the state of T6OTL to be an al ternate function of the external output pin TOEOUT P3 1 For that purpose a 1 must be written i
17. mizing the remaining RAM for user data The CPU disposes of an actual register context consisting of up to 16 wordwide and or bytewide GPRs which are physically located within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at a time The number of register banks is only restricted by the available internal RAM space Foreasy parameter passing a register bank may overlap others A system stack of upto 1024 words is provided as a storage for temporary data The system stack is also located within the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the de tection of a stack overflow or underflow Hardware detection of the selected memory space is placed at the internal memory decoders and al lows the user to specify any address directly or in directly and obtain the desired data without using temporary registers or special instructions 15 254 1 Architectural Overview ST10R165 THE ON CHIP SYSTEM RESOURCES Cont d For Special Function Registers 1024 Bytes of the address space are reserved The standard Special Function Register area SFR uses 512 bytes while the Extended Special Function Regis ter area ESFR uses the other 512 bytes E SFRs are wordwide registers which are use
18. ooooh L umo a a a I sose FeBsn san Soral Channel 0 Baud Rate Generator Reload Register ooon Ce ee c NN D SORBUF FEB2h E Serial Channel 0 Receive Buffer Register XXXXh read only SORIC b FF6Eh Serial Channel 0 Receive Interrupt Control Register 0000h SOTBIC b F19Ch E Serial Channel 0 Transmit Buffer Interrupt Control Register 0000h SOTBUF FEBOh Serial Channel 0 Transmit Buffer Register 0000h write only m LN SSCRB FOB2h E m SSC Receive Buffer read only XXXXh FE46h 23h GPT2 Timer 5 Register 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h 240 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 SPECIAL FUNCTION REGISTERS ORDERED BY NAME Cont d o vs mecow rra aah GPT Tier 6 Cenol Rager conn mec errem Ban GPTeTmereimerupt Convoi Regier ooon fworcon ream bm Watchdog Timer Gomor Reaser ooox xoc e Fiet con X Peiphera 0 Iterupt Cool Regier 00h enc v Frene cm X Peipheral 1 erupt Gono Reaser 0000 eac v Frene com XfeieazmerwComnRegsor 00h xesc write cr x Peipheral 9 erupt ConRegse 00h zeros o Feren se Constant Vale o s Regier ead ony ooon Note 1 The system configuration is selected during reset 2 Bit WDTR indicates a watchdog timer triggered reset 241 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 16 3 REGISTERS ORDERED BY ADDRESS The following table lists a
19. rupt handlers This provides advantages for the servicing software For single transfers it is sufficient to use the transmitter interrupt SOTIR which indicates that the previously loaded data has been transmitted except for the last bit of an asynchronous frame Figure 9 6 ASCO Interrupt Generation For multiple back to back transfers it is neces sary to load the following data at least until the time the last bit of the previous frame is being transmitted In asynchronous mode this leaves just one bit time for the handler to respond to the transmitter interrupt request in synchronous mode it is not possible at all Using the transmit buffer interrupt SOTBIR to re load transmit data allows the time to transmit a complete frame for the service routine as SOTBUF may be reloaded while the previous data is still being transmitted As shown in the figure below SOTBIR is an early trigger for the reload routine while SOTIR indi cates the completed transmission Software using handshake therefore should rely on SOTIR at the end of a data block to make sure that all data has really been transmitted 180 254 SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ MICROELECTRONICS Chapter 10 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE The High Speed Synchronous Serial Interface SSC provides flexible high speed serial communi cation between the ST10R165 and other micro controllers micropro
20. using a 16 bit demultiplexed bus In that case most of the in structions can be processed within just one ma chine cycle which is also the general minimum execution time All external memory accesses are performed by the ST10R165 s on chip External Bus Controller EBC which works in parallel with the CPU This section summarizes the execution times in a very condensed way A detailled description of the execution times for the various instructions and the specific exceptions can be found in the ST10 Family Programming Manual The table below shows the minimum execution times required to process a ST10R165 instruction fetched from the internal RAM or from external Minimum Execution Times Memory Area Internal RAM 16 bit Demux Bus 16 bit Mux Bus 8 bit Demux Bus 8 bit Mux Bus 40 254 memory These execution times apply to most of the ST10R165 instructions except some of the branches the multiplication and the division in structions and a special move instruction The numbers in the table are in units of ns refer to a CPU clock of 20 MHz and assume no waitstates Execution from the internal RAM provides flexibili ty in terms of loadable and modifiable code on the account of execution time Execution from external memory strongly de pends on the selected bus mode and the program ming of the bus cycles waitstates The operand and instruction accesses listed be low can extend the execution time of an
21. 32 512 010b 011b 101b 110b Fe ewrer orrmm Ses 5Po x erorm mraum ses SPo oos se oo BFen ooFaom seesro Reserved Do rouse hs combination T Reserved Do rotuse tis combination 111b 1024 00 FDFEh 00 F600h Note No circular stack SP 11 SP 0 ky 3 SON MICROELECTRONICS 225 254 15 System Programming ST10R165 STACK OPERATIONS Cont d Figure 15 1 Physical Stack Address Generation FBFEh 11111011 13111 1110 FB80h 1111 1011 1 000 0000 FB80h 1111 1011 1000 0000 After PUSH FBFEh 1111 1011 1111 1110 FBFEh 1 1 1 1 1011 1111 1110 Phys A FB7Eh 1 1 13 1 1011 0111 1110 64 words The following example demonstrates the circular stack mechanism which is also an effect of this vir tual stack mapping First register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size With the fol lowing instruction register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 0F802h Set SP before last entry of physical stack of 256 words SP F802h Physical stack address FAO2h PUSH R1 SP F800h Physical stack address FAO00h PUSH R2 SP F7FEh Physical stack address FBFEh 226 254 SP Stack Size 1111 1012 1111 1110 a 1111 1010 0000 0000 1111
22. 9 Asynchronous Synchronous Serial Interface ST10R165 ASCO Mode Control 8 bit data synchronous operation 8 bit data async operation Reserved Do not use this combination 7 bit data parity async operation 9 bit data async operation 8 bit data wake up bit async operation Reserved Do not use this combination 8 bit data parity async operation Number of Stop Bits Selection operation One stop bit Two stop bits Receiver Enable Bit Receiver disabled Receiver enabled Reset by hardware after reception of byte in synchronous mode Parity Check Enable Bit async operation Ignore parity Check parity Framing Check Enable Bit async operation Ignore framing errors Check framing errors Overrun Check Enable Bit Ignore overrun errors Check overrun errors Parity Error Flag Set by hardware on a parity error SOPEN 1 Must be reset by software Framing Error Flag Set by hardware on a framing error SOFEN 1 Must be reset by software Overrun Error Flag Set by hardware on an overrun error SOOEN 1 Must be reset by software Parity Selection Bit Even parity parity bit set on odd number of 1 s in data Odd parity parity bit set on even number of 1 s in data Baudrate Selection Bit Divide clock by reload value constant depending on mode Additionally reduce serial clock to 2 3rd LoopBack Mode Enable Bit Standard transmit receive mode Loopback mode enabled Baudrate Generator Run Bit 0 Ba
23. Execution of the EINIT instruction disables the ac tion of the DISWDT instruction disables write ac cesses to register SYSCON see note and caus es the RSTOUT pin to go high This signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware Note All configurations regarding register SY SCON enable CLKOUT stacksize etc must be selected before the execution of Note Traps incl NMI may occur even though EINIT the interrupt system is still disabled 210 254 y SGS SON YA MICROELECTRONICS APPLICATION SPECIFIC INITIALIZATION ROUTINE Cont d System Startup Configuration Although most of the programmable features of the ST10R165 are either selected during the ini tialization phase or repeatedly during program ex ecution there are some features that must be se lected earlier because they are used for the first access of the program execution eg external bus configuration These selections are made during reset via the pins of PORTO which are read during the internal reset sequence During reset internal pullup devic es are active on the PORTO lines so their input level is high if the respective pin is left open or is low if the respective pin is connected to an exter nal pulldown device The coding of the selections as shown below allows in many cases to use the default option ie high level The value on the upper byte of
24. PORT 0 Cont d 5 1 1 Alternate Functions of PORTO When an external bus is enabled PORTO is used as data bus or address data bus Note that an external 8 bit demultiplexed bus only uses POL while POH is free for IO provided that no other bus mode is enabled PORTO is also used to select the system startup configuration During reset PORTO is configured to input and each line is held high through an in ternal pullup device Each line can then be individ ually pulled to a low level see DC level specifica tions in the respective Data Sheets through an external pulldown device A default configuration is selected when the respective PORTO lines are at a high level Through pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pullup devices are designed such that an external pulldown resistors see Data Sheet specification can be used to apply a correct low level These external pulldown resistors can re main connected to the PORTO pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORTO this might be the case for example if the Figure 5 3 PORTO IO and Alternate Functions Alternate Function a General Purpose 8 bit Input Output Demux Bus SGS THOMSON YA MICROELECTRONICS Demux Bus 5 Parallel Ports ST10R165 external resistor is too strong With
25. RPOH see table below CS Signal Generation During external accesses the EBC can generate a programmable number of CS lines on Port 6 which allow to directly select external peripherals esse Chip Seecttines we s e mim SS SSS C The CSx outputs are associated with the BUS CONXx registers and are driven active low for any access within the address area defined for the re spective BUSCON register For any access out side this defined address area the respective CSx signal will go inactive high Note No CSx signal will be generated for an ac cess to any internal address area even if this area is covered by the respective AD DRSELx register The chip select signals allow to be operated in four different modes which are selected via bits CS WENx and CSRENx in the respective BUSCONx register CSWENx CSRENx Chip Select Mode poc The Address Chip Select Default after Reset Read Write Chip Select 120 254 SGS THOMSON YA MICROELECTRONICS EXTERNAL BUS MODES Cont d Address Chip Select signals remain active for the whole external bus cycle An address chip se lect becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a different address area No spikes will be generated on the chip select lines Read or Write Chip Select signals remain active only as long as the associated control signal RD
26. SGS THOMSON YA MICROELECTRONICS Internal Control Logic Only on hardware reset BUSCONO 211 254 13 System Reset ST10R165 APPLICATION SPECIFIC INITIALIZATION ROUTINE Cont d Emulation Mode Pin POL O EMU selects the Emulation Mode when low during reset This mode allows the ac cess to integrated XBUS peripherals via the exter nal bus interface pins in application specific ver sions of the ST10R165 This mode is used for special emulator purposes and is of no use in basic ST10R165 devices so in this case POL O should be held high Default Emulation Mode is off Adapt Mode Pin POL 1 ADP selects the Adapt Mode when low during reset In this mode the ST10R165 goes into a passive state which is similar to its state during reset The pins of the ST10R165 float to tristate or are deactivated via internal pullup pull down devices as described for the reset state In addition also the RSTOUT pin floats to tristate rather than be driven low and the on chip oscilla tor is switched off This mode allows to switch a ST10R165 that is mounted to a board virtually off so an emulator may control the board s circuitry even though the 212 254 ky 3 original ST10R165 remains in its place The origi nal ST10R165 also may resume to control the board after a reset sequence with POL 1 high Default Adapt Mode is off Note When XTAL1 is fed by an external clock generator while XTAL2 is left open
27. SYNCHRONOUS OPERATION Cont d Synchronous transmission begins within 4 state times after data has been loaded into SOTBUF provided that SOR is set and SOREN O half du plex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR be ing set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The data bits are transmitted synchro nous with the shift clock After the bit time for the 8th data bit both pins TXDO and RXDO will go high the transmit interrupt request flag SOTIR is set and serial data transmission stops Pin TXDO P3 10 must be configured for alternate data output ie P3 102 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must also be configured for output P3 112 1 and DP3 11 1 during transmission 176 254 ky 3 Synchronous reception is initiated by setting bit SOREN 1 If bit SOR 1 the data applied at pin RXDO are clocked into the receive shift register synchronous to the clock which is output at pin TXDO After the 8th bit has been shifted in the content of the receive shift register is transferred to the receive data buffer SORBUF the receive in terrupt request flag SORIR is set the recei
28. Ti loaa z gt rw TAIC FF64h B2h SFR Reset Value 00h i5 14 13 12 11 10 9 8 7 6 r eat RUE E MEE TAIR T4IE ILVL GLVL rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields s SGS THOMSON 189 254 YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 8 2 TIMER BLOCK GPT2 From a programmers point of view the GPT2 block is represented by a set of SFRs as summa rized below Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded Timer block GPT2 supports high precision event control with a maximum resolution of 200 ns 20 MHz CPU clock It includes the two timers T5 and T6 and the 16 bit capture reload register CAPREL Timer T6 is referred to as the core timer and T5 is referred to as the auxiliary timer of GPT2 Each timer has an alternate input function pin as sociated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control input pin An overflow underflow of T6 is indicated by the output toggle bit TGOTL whose state may be out put on an alternate function port pin In addition T6 may be reloaded with the contents of CAPREL The toggle bit also supports the concatenation of T6 wit
29. Up Down 166 254 T6OUT P3 1 TsOE res Interrupt TelR Request VR02045H SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT2 Cont d GPT2 Capture Reload Register CAPREL in Capture And Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR the two functions can be en abled simultaneously by setting both bits This feature can be used to generate an output fre quency that is a multiple of the input frequency This combined mode can be used to detect con secutive external events which may occur aperi odically but where a finer resolution that means more ticks within the time between two external events is required For this purpose the time between the external events is measured using timer T5 and the CAPREL register Timer T5 runs in timer mode counting up with a frequency of eg fcpi 32 The external events are applied to pin CAPIN When an external event occurs the timer T5 contents are latched into register CAPREL and timer T5 is 8 General Purpose Timer Units ST10R165 cleared T5CLR 1 Thus register CAPREL al ways contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down with a frequency of eg fcpu 4 uses the value in register CAPREL to perform a reload on underflow This means the value in register CAPREL represents the time be
30. When writing to SSCCON make sure that re served locations receive zeros The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic see block diagram Transmission and reception of serial data is synchronized and takes place atthe same time ie the same number of transmitted bits is also received Transmit data is written into the Transmit Buffer SSCTB It is Transmission and reception enabled Access to status flags and M S control moved to the shift register as soon as this is emp ty An SSC master SSCMS 1 immediately be gins transmitting while an SSC slave SSC MS 0 will wait for an active shift clock When the transfer starts the busy flag SSCBSY is set and a transmit interrupt request SSCTIR will be gener ated to indicate that SSCTB may be reloaded again When the programmed number of bits 2 16 has been transferred the contents of the shift register are moved to the Receive Buffer SS CRB and a receive interrupt request SSCRIR will be generated If no further transfer is to take place SSCTB is empty SSCBSY will be cleared atthe same time Software should not modify SS CBSY as this flag is hardware controlled Note Only one SSC etc can be master at a giv en time 184 254 SGS SON IT MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165 The transfer of serial data bits can be pro grammed in many respects
31. monitored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 25 us and 420 ms can be monitored 20 MHz The default Watchdog Timer interval af ter reset is 6 55 ms 20 MHz 19 254 1 Architectural Overview ST10R165 1 4 PROTECTED BITS The ST10R165 provides a special mechanism to protect bits which can be modified by the on chip hard ware from being changed unintentionally by software accesses to related bits see also chapter The Central Processing Unit The following bits are protected Register Pme wes ASCO transmit buffer interrupt request flags soon smew T asco ewer orane teg Y 33 protected bits 20 254 S7 SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual Y The memory space of the ST10R165 is config ured in a Von Neumann architecture This means that code and data are accessed within the same linear address space All of the physically separated memory areas including internal RAM the internal Special Function Register Areas SFRs and ESFRs the address areas for inte Figure 2 1 Memory Areas and Address FF FFFFh Segment Data Page 1023 255 FF 0000h Segment 254 FE 0000h 03 0000h Segment 2 02 0000h Segment 1 01 0000h Data Page 3 Segment Data Page 0 00 0000h Address Space 16 MByte March 19
32. pending on the selected clock phase the first clock edge generated by the master may be al ready used to clock in the first data bit So the slave s first data bit must already be valid at this time Note On the SSC always atransmission and a reception takes place at the same time re gardless whether valid data has been trans mitted or received This is different eg from asynchronous reception on ASCO The initialization of the SCLK pin on the master requires some attention in order to avoid unde sired clock transitions which may disturb the other receivers The state of the internal alternate output lines is 1 as long as the SSC is disabled This al ternate output signal is ANDed with the respective port line output latch Enabling the SSC with an idle low clock SSCPO 0 will drive the alternate data output and via the AND the port pin SCLK immediately low To avoid this use the following sequence select the clock idle level SSCPO x load the port output latch with the desired clock idle level P3 13 x switch the pin to output DP3 13 1 enable the SSC SSCEN 1 if SSCPO 0 enable alternate data output P3 13 1 188 254 The same mechanism as for selecting a slave for transmission separate select lines or special commands may also be used to move the role of the master to another device in the network In this case the previous master and the future master
33. vides the best performance for passing data be tween multiple tasks Note The system stack allows to store words on ly Bytes must either be converted to words orthe respective other byte must be disre garded Register SP can only be loaded with even byte addresses The LSB of SP is always 0 Detection of stack overflow underflow is support ed by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP 224 254 ky 3 reaches either boundary specified in these regis ters The contents of the stack pointer are compared to the contents of the overflow register whenever the SP is DECREMENTED either by a CALL PUSH or SUB instruction An overflow trap will be entered when the SP value is less than the value in the stack overflow register The contents of the stack pointer are compared to the contents of the underflow register whenever the SP is INCREMENTED either by a RET POP or ADD instruction An underflow trap will be en tered when the SP value is greater than the value in the stack underflow register Note When a value is MOVED into the stack pointer NO check against the overflow un derflow registers is performed In many cases the user will place a software reset instruction SRST into the stack underflow and overflow trap service routines This is an easy ap proach which does n
34. 1 must be written into port data latch P3 3 and pin T3OUT P3 3 must be configured as output by setting direction control bit DP3 3 to 1 If T3OE 1 pin T3OUT then outputs the state of T3OTL If T3OE O pin T3OUT can be used as general purpose IO pin In addition TSOTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the re load function of the auxiliary timers T2 and T4 For this purpose the state of T3OTL does not have to be available at pin TSOUT because an internal connection is provided for this option Pin TxEUD Bit TXUDE Bit TXUD Count Direction Count Up pc px ce Lor 2 45 YE zal o0 1 p Count 5 50 0 00 Low poo ox mE 6 Hes M MEE GEN NET ANI Note The direction control works the same for core timer T3 and for auxiliary timers T2 and T4 Therefore the pins and bits are named Tx 142 254 SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT1 Cont d Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 000b In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable prescaler which is selected by bit field T3l The in put frequency frs for timer T3 and its resolution rz are scaled linearly with lower clock frequencies fceu aS can be seen from the following formula fopu 8 g T3l fts r s 8
35. 106 254 S7 SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 5 7 PORT 6 If this 8 bit port is used for general purpose IO the line can be switched into push pull or open drain direction of each line can be configured via the mode via the open drain control register ODP6 corresponding direction register DP6 Each port P6 FFCCh E6h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i E r T Y mpm dr ET I i a T E Em ua Da zu ak cm ta e Wet ez E 3 gt s rw rw rw rw rw rw rw rw DP6 FFCEh E7h SFR Reset Value 00h 15 14 13 12 11 10 9 7 0 8 6 5 4 3 2 1 r p pom pmo om qmm quem ct oes oes near oes alnes ores Ll aues aed cedo cdm cim E owes iue ce ocn rw rw rw rw rw rw rw rw Port direction register DP6 bit y DP6 y 0 Port line P6 y is an input high impedance DP6 y 1 Port line P6 y is an output ODP6 F1CEh E7h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p ee ee NS ee eT DE x ODP6 ODP6 ODP6 ODP6 ODP6 ODP6 ODP6 ODP6 7 6 5 4 3 2 1 0 7 rw rw rw rw rw rw rw rw Port 6 Open Drain control register bit y ODP6 y 0 Port line P6 y output driver in push pull mode ODP6 y 1 Port line P6 y output driver in open drain mode sy SGS THOMSON 107 254 YA MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 6 Cont d 5 7 1 Alternate Functions of Port 6 A programmable number of chip select signals CS4 CS0 derived from t
36. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 or 2 fom se oe ee ee oe em es ee e t5 t2 8 T rw E rw rw rw rw rw rw rw rw rw rw rw rw rw rw Port direction register DP3 bit y DP3 y 0 Port line P3 y is an input high impedance DP3 y 1 Port line P3 y is an output ODP3 F1C6h E3h ESFR Reset Value 0000h 15 13 12 10 9 8 7 6 5 4 3 2 1 0 ne Peters assa apr ear rorem or 10 9 8 7 6 4 0 E rw 2 rw rw rw rw rw rw rw rw rw rw rw rw Port 3 Open Drain control register bit y ODP3 y 0 Port line P3 y output driver in push pull mode ODP3 y 1 Port line P3 y output driver in open drain mode STA SGS THOMSON AG MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 3 Cont d 5 4 1 Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines the two serial interfaces and the control lines BHE and The table below summarizes the alternate func tions of Port 3 CLKOUT Port3Pin Alternate Function T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST MTSR TxDO RxDO BHE WRH SCLK Alternate Function General Purpose Input Ou tput 98 254 Timer 6 Toggle Output GPT2 Capture Input Timer 3 Toggle Output Timer 3 External Up Down Control Input Timer 4 Count Input Timer 3 Count Input Timer 2 Count Input SSC Master Receive Slave Transmit SSC Master Transmit Slave Receive ASCO Transmit Data Output ASCO Receive Data
37. 5 Choosing the Baudrate forthe BSL 0 00 eee 202 6 254 SGS THOMSON YA MICROELECTRONICS Table of Contents 13 System Reset es zur ee eae ee oe oe ERES 205 13 1 The ST10R165 s Pins after Reset te ee 207 13 2 Heset Output Pin aed ated actos vet sey soo eq ec EIE ended Erbe 208 13 3 Watchdog Timer Operation after Reset 0 0 0 liliis 208 13 4 Reset Values for the ST10R165 Registers llle llle ee ee 208 13 5 The Internal RAM after Reset iislsleelseeeee eee 209 13 6 Ports and External Bus Configuration during Reset 0 0202 eee aa 209 13 7 Application Specific Initialization Routine lille 210 14 Power Reduction Modes 215 144 ddle Mode xs mss REESE Ie eRx aa MORTE bu 215 14 2 Power Down Mode 0 eee hh hn 217 14 3 Status of Output Pins during Idle and Power Down Mode 0005 218 15 System Programming eleeelsse 221 15 1 Instructions Provided as Subsets of Instructions llli llle 221 15 2 Multiplication and Division lslileeee RR RII II 222 15 3 BCD Galc lations veces 2e hod ihrer ee efisueeeckesthnbeif seeXeiberbeent i 223 15 4 Stack Operations s d voee SERSLEHRO EE eels e udo vea dH PEERS 224 15 5 Register Banking 0 0 cee ce te hh 228 15 6 Procedure Call Entry and Exit 0 000 000 ce eee 228 15 7 gt Table Searching coz dit erp Seb ood a ete
38. ADDRESSING MECHANISM The standard mechanism to access data locations uses one of the four data page pointers DPPx which selects a 16 KByte data page and a 14 bit offset within this data page The four DPPs allow immediate access to up to 64 KByte of data In ap plications with big data arrays especially in HLL applications using large memory models this may require frequent reloading of the DPPs even for single accesses The EXTP extend page instruction allows to Switch to an arbitrary data page for 1 4 instruc tions without having to change the current DPPs EXAMPLE EXTP R15 1 The override page number is stored in R15 MOV RO R14 The 14 bit page offset is stored jin R14 MOV R1 R13 This instruction uses the standard DPP scheme The EXTS extend segment instruction allows to switch to a 64 KByte segment oriented data ac cess scheme for 1 4 instructions without having to change the current DPPs In this case all 16 bits of the operand address are used as segment off set with the segment taken from the EXTS in struction This greatly simplifies address calcula tion with continuous data like huge arrays in C EXAMPLE EXTS 15 1 The override seg is 15 OF 0000h 0F FFFFh MOV RO R14 SGS THOMSON YA MICROELECTRONICS 15 System Programming ST10R165 Ihe 16 bit segment offset is Stored in R14 MOV R1 R13 This instruction uses the
39. Al RSTOUT Reset WDTREL MCB02052 195 254 This is advanced information from SGS THOMSON Details are subject to change without notice 11 Watchdog Timer ST10R165 Figure 11 2 SFRs and Port Pins associated with the Watchdog Timer Reset Indication Pin Data Registers g RSTOUT Control Registers Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register The operation of the Watchdog Timer is controlled WDTCON FFAEh D7h SFR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 WDT WDT p I rw by its bitaddressable Watchdog Timer Control Register WDTCON This register specifies the reload value for the high byte of the timer se lects the input clock prescaling factor and pro vides a flag that indicates a watchdog timer over flow Reset Value 000Xh 0 Watchdog Timer Input Frequency Selection 0 Input frequency is fopy 2 1 Input frequency is fopy 128 Watchdog Timer Reset Indication Flag Set by the watchdog timer on an overflow Cleared by a hardware reset or by the SRVWDT instruction WDTREL Watchdog Timer Reload Value for the high byte Note The reset value will be 0002h if the reset was triggered by the watchdog timer overflow It will be 0000h otherwise 196 254 SGS THOMSON A3 vie xors SerROMYGS After any software reset ext
40. Although these internally in jected instructions will not be noticed in reality they are introduced here to ease the explanation of the pipeline in the following Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not Since passing through one pipeline stage takes atleast one machine cycle any isolated in struction takes at least four machine cycles to be completed Pipelining however allows parallel ie simultaneous processing of up to four instruc tions Thus most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset see figure below Instruction pipelining increases the average in struction throughput considered over a certain pe riod of time In the following any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing 33 254 3 Central Processing Unit ST10R165 INSTRUCTION PIPELINING Contd Standard Branch Instruction Processing Instruction pipelining helps to speed sequential program processing In the case that a branch is taken the instruction which has already been fetched providently is mostly not the instruction which must be decoded next Thus at least one additional machine cycle is normally required to fet
41. Cont d The Context Pointer CP This non bit addressable register is used to select the current register context This means that the CP register value determines the address of the first General Purpose Register GPR within the current register bank of up to 16 wordwide and or bytewide GPRs Note It isthe users responsibility that the physical GPR address specified via CP register plus short GPR address must always be an inter nal RAM location If this condition is not met unexpected results may occur Do not set CP below 00 F600h or above 00 FD FEh CP FE10h 08h SFR 15 14 11 10 r r Modifiable portion of register CP 3 Central Processing Unit ST10R165 Be careful using the upper GPRs with CP above 00 FDEOh The CP register can be updated via any instruc tion which is capable of modifying an SFR Note Due to the internal instruction pipeline a new CP value is not yet usable for GPR ad dress calculations of the instruction immedi ately following the instruction updating the CP register The Switch Context instruction SCXT allows to save the content of register CP on the stack and updating it with a new value in just one machine cycle Reset Value FCOOh 7 6 5 4 3 2 1 0 13 12 9 8 r r Specifies the word base address of the current register bank When writing a value to register CP with bits CP 11 CP 9 000 bits CP 11 CP 10 are set to 11 by hardware in all oth
42. Control Register DP3 Port 3 Direction Control Register SSCBR SSC Baud Rate Generator Reload Register SSCTB SSC Transmit Buffer Register write only SSCTIC SSC Transmit Interrupt Control Register March 1995 Control Registers Interrupt Control P3 Port 3 Data Register SSCCON SSC Control Register SSCRB SSC Receive Buffer Register read only SSCRIC SSC Receive Interrupt Control Register SSCEIC SSC Error Interrupt Control Register 181 254 This is advanced information from SGS THOMSON Details are subject to change without notice 10 High Speed Synchronous Serial Interface ST10R165 The operating mode of the serial channel SSC is during operation SSC enabled by SSCEN 1 it controlled by its bit addressable control register provides access to a set of status flags SSCCON This register serves for two purposes Register SSCCON is shown below in each of the during programming SSC disabled by SS two modes CEN 0 it provides access to a set of control bits Figure 10 2 Synchronous Serial Channel SSC Block Diagram Baud Rate Clock Slave clock Generator Control Master Clock Receive Int Request Transmit Int Request SSC Control Block Error Int Request Status Control Pin Control 16 Bit Shift Register Transmit Buffer Receive Buffer Register SSCTB Register SSCRB Internal Bus MCBO1957 182 254 S7 SGS THOMSON YA MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165
43. For all instructions which implicitly access the system stack the SP register is either decremented or in cremented as specified For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address provided that the branch is taken 3rd gt EXECUTE In this stage an operation is performed on the pre viously fetched operands in the ALU Additionally the condition flags in the PSW register are updat ed as specified by the instruction All explicit writes to the SFR memory space and all auto increment or auto decrement writes to GPRs used as indi rect address pointers are performed during the ex ecute stage of an instruction too 4th WRITE BACK In this stage all external operands and the remain ing operands within the internal RAM space are written back Figure 3 2 Sequential Instruction Pipelining L D 1 Machine SGS THOMSON YA MICROELECTRONICS 3 Central Processing Unit ST10R165 A particularity ofthe ST10R165 are the injected in structions These injected instructions are gener ated internally by the machine to provide the time needed to process instructions which cannot be processed within one machine cycle They are au tomatically injected into the decode stage of the pipeline and then they pass through the remain ing stages like every standard instruction Pro gram interrupts are performed by means of inject ed instructions too
44. Input P3 8 x DP3 8 0 Serial Data Output 10 3 BAUD RATE GENERATION The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capabili ty allowing baud rate generation independent from the timers The baud rate generator is clocked with the CPU clock divided by 2 10 MHz 20 MHz CPU clock The timer is counting downwards and can be start ed or stopped through the global enable bit SS CEN in register SSCCON Register SSCBR is the dual function Baud Rate Generator Reload regis ter Reading SSCBR while the SSC is enabled returns the content of the timer Reading SSCBR while the SSC is disabled returns the pro grammed reload value In this mode the desired reload value can be written to SSCBR Note Never write to SSCBR while the SSC is en abled Slave Mode Port Latch P3 13 x DP3 13 0 d P3 8 1 DP3 8 1 SGS THOMSON YA MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165 BAUD RATE GENERATION Cont d The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baudrate E fcpu SSC 2 lt SSCBR gt 1 fcpu BR See l 2 Baudratessc Baud Rate Reserved Use a reload value gt 0 5 MBaud 3 3 MBaud 2 5 MBaud 2 0 MBaud 1 0 MBaud 100 KBaud 10 KBaud 1 0 KBaud 152 6 Baud Note The content of SSCBR must be gt 0 SGS T
45. It is therefore recommended to use the bit field in structions BFLDL and BFLDH to write to any number of bits in either byte of an SFR without dis turbing the non addressed byte and the unselect ed bits Reserved Bits Some of the bits which are contained in the ST10R165 s SFRs are marked as Reserved User software should never write 1 sto reserved bits These bits are currently not implemented and may be used in future products to invoke new functions In this case the active state for these functions will be 1 and the inactive state will be 0 Therefore writing only 0 s to reserved loca tions provides portability of the current software to future devices Read accesses to reserved bits re turn O s Parallel Ports The ST10R165 provides up to 77 IO lines which are organized into six input output ports and one input port All port lines are bit addressable and all input output lines are individually bit wise pro grammable as inputs or outputs via direction reg isters The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of three IO ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins are configured as inputs All port lines have programmable alternate input or output functions associated with them PORTO and PORT1 may be used as add
46. P1H 1 A9 P1H 0 A8 P1L 7 A7 P1L 6 A6 P1L 5 A5 P1L 4 A4 P1L 5 A3 P1L 2 A2 P1L 1 A1 P11 0 A0 POH 7 AD15 POH 6 AD14 P0H 5 AD13 POH 4 AD12 POH 3 AD11 POH 2 AD10 POH 1 AD9 POH 0 AD8 Vss Vbo VR02052B 253 254 18 Device Specification ST10R165 Information furnished is believed to be accurate and reliable However SGS THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of SGS THOMSON Microelectronics Specifi cations mentioned in this publication are subject to change without notice This publication supersedes and replaces all information pre viously supplied SGS THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS THOMSON Microelectronics 1995 SGS THOMSON Microelectronics All rights reserved Purchase of C Components by SGS THOMSON Microelectronics conveys a license under the Philips I2C Patent Rights to use these components in an C system is granted provided that the system conforms to the IC Standard Specification as defined by Philips SGS THOMSON Microelectronics Group of Companies Australia Brazil France China Germany Hong Kong Italy Japan Korea Malaysia Ma
47. PORTO POH is latched into register RPOH upon reset the value on the lower byte POL directly influences the BUSCONO register bus mode or the internal control logic of the ST10R165 The pins that control the operation of the internal control logic and the reserved pins are evaluated Figure 13 3 PORTO Configuration during Reset 13 System Reset ST10R165 only during a hardware triggered reset sequence The pins that influence the configuration of the ST10R165 are evaluated during any reset se quence ie also during software and watchdog timer triggered resets The configuration via POH is latched in register RPOH for subsequent evaluation by software Register RPOH is described in chapter The Exter nal Bus Interface Note The reserved pins marked R must re main high during reset in order to ensure proper operation of the ST10R165 The load on those pins must be small enough for the internal pullup device to keep their level high or external pullup devices must en sure the high level The pins marked X should be left open for ST10R165 devices that do not use them The following describes the different selections that are offered for reset configuration The default modes refer to pins at high level ie without exter nal pulldown devices connected Please also con sider the note above on reserved pins L2 LA H 7 4 k L 4 Port 4 Logic Port 6 Logic Reserved for Derivatives SYSCON
48. T30E MCBO2035 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL 150 254 SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT1 Cont d e Using this single transition mode for both auxil iary timers allows to perform very flexible pulse width modulation PWM One of the auxiliary tim ers is programmed to reload the core timer on a positive transition of T3OTL the other is pro grammed for a reload on a negative transition of TSOTL With this combination the core timer is al ternately reloaded from the two auxiliary timers The figure below shows an example for the gener ation of a PWM signal using the alternate reload 8 General Purpose Timer Units ST10R165 mechanism T2 defines the high time of the PWM signal reloaded on positive transitions and T4 defines the low time of the PWM signal reloaded on negative transitions The PWM signal can be output on TSOUT with TSOE 1 P3 321 and DP3 3 1 With this method the high and low time of the PWM signal can be varied in a wide range Note The output toggle latch T3OTL is accessible via software and may be changed if re quired to modify the PWM signal However this will NOT trigger the reloading of T3 Figure 8 9 GPT1 Timer Reload Configuration for PWM Generation Reload Register T2 Interrupt Request T3OUT P3 3 Interrupt Request Interrupt Request MCB02037 Note Lines only affected by over
49. also be triggered intentionally eg to em ulate additional instructions by generating an Ille gal Opcode trap The ST10R165 distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the trap is either completed or cancelled ie it has no effect on the system state before the trap handling rou tine is entered Hardware traps are non maskable and always have priority over every other CPU activity If sev eral hardware trap conditions are detected within the same instruction cycle the highest priority trap is serviced see table in section Interrupt System Structure PSW CSP in segmentation mode and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level ie level 15 disabling all interrupts The CSP is set to code segment zero if segmen tation is enabled A trap service routine must be terminated with the RETI instruction SON MICROELECTRONICS TRAP FUNCTIONS Cont d The eight hardware trap functions of the ST10R165 are divided into two classes Class A traps are DA e external Non Maskable Interrupt NMI e Stack Overflow e Stack Underflow trap These traps share the same trap priority but have an individual vector address Class B traps are e Unde
50. also support data addressing beyond the limits of the current DPPs except ATOMIC whichis advantageous for bigger memory models in high level languages Refer to chapter System Programming for examples Protected Instructions Some instructions of the ST10R165 which are critical for the functionality of the controller are implemented as so called Protected Instructions These protected instructions use the maximum instruction format of 32 bits for decoding while the regular instructions only use a part of it eg the lower 8 bits with the other bits providing additional information like involved registers Decoding all 32 bits of a protected doubleword instruction increases the security in cases of data distortion during instruction fetching Critical operations like a software reset are therefore only executed if the complete instruction is decoded without an error This enhances the safety and reliability of a microcontroller system 250 254 S7 SGS THOMSON YA MICROELECTRONICS SL asc hes The device specification describes the electrical parameters of the device It lists DC characteris tics like input output or supply voltages or cur rents and AC characteristics like timing charac teristics and requirements Other than the architecture the instruction set or the basic functions of the ST10R165 core and its peripherals these DC and AC characteristics are subject to changes due to device improvements or specific derivatives
51. an instruction within the current execution flow Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00 0000h through 00 01FCh will be branched to Executing a TRAP instruction causes a similar ef fect as if an interrupt at the same vector had oc curred PSW CSP in segmentation mode and IP are pushed on the internal system stack and a jump is taken to the specified vector location When segmentation is enabled and a trap is exe cuted the CSP forthe trap service routine is set to code segment 0 No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not modi fied by the TRAP instruction so the service 80 254 ky 3 routine is executed on the same priority lev el from which it was invoked Therefore the service routine entered by the TRAP in struction can be interrupted by other traps or higher priority interrupts other than when triggered by a hardware trap Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a pro gram notidentified at assembly time A hardware trap may
52. and is not af fected by the alternate output function The re spective port latch should hold a 1 because its output is ANDed with the alternate output data If an alternate input function of a pin is used the direction of the pin must be programmed for input DPx y 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also setthe direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch On most of the port lines the user software is re sponsible for setting the proper direction when us ing an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the al ternate function There are port lines however where the direction of the port line is switched au tomatically For instance in the multiplexed exter nal bus modes of PORTO the direction must be Switched several times for an instruction fetch in order to output the addresses and to input the da ta Obviously this cannot be done through instruc tions In these cases the direction of the port line is switched automatically by
53. at pin CAPIN interrupt request flag CRIR in register CRIC is set T5IC FF66h B3h SFR 15 14 18 12 11 10 9 8 L I I gd I 1 L T6IC FF68h B4h SFR 13 12 11 10 9 8 15 14 pom om om pmo qe 9pm mpm NR mA v CRIC FF6Ah B5h 15 14 18 12 11 DC HOMES a TARE Ope 4 LE ee 3b eS Rb rer 6 TSIR T5IE ILVL GLVL a rw crear 6 T6IR T6IE ILVL GLVL rw J 6 CRIR CRIE ILVL GLVL i rw Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector T5INT T6INT or CRINT or trigger a PEC serv ice if the respective interrupt enable bit T5IE or T6IE in register TxIC CRIE in register CRIC is set There is an interrupt control register for each of the two timers and for the CAPREL register Reset Value 00h Note Please refer to the general Interrupt Control Register description for an explanation of the control fields 168 254 ky 3 SON MICROELECTRONICS MICROELECTRONICS Chapter 9 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE The Asynchronous Synchronous Serial Interface ASCO provides serial communication between the ST10R165 and other microcontrollers microproc essors or external peripherals The ASCO supports full duplex asynchronous communication up to 625 KBaud and half duplex synchronous communication up to 2 5 MBaud 20 MHz CPU clock In synchronous mode data are transmitted or received synchronous to a shift clock which is generated by the ST1
54. bit addressable RAM loca tions provide this feature e The read modify write approach may be critical with hardware effected bits In these cases the hardware may change specific bits while the read modify write operation is in progress where the writeback would overwrite the new bit value gen erated by the hardware The solution is either the implemented hardware protection see below or realized through special programming see Par ticular Pipeline Effects Protected bits are not changed during the read modify write sequence ie when hardware sets eg an interrupt request flag between the read and the write of the read modify write sequence The hardware protection logic guarantees that only the intended bit s is are affected by the write back operation Note If a conflict occurs between a bit manipula tion generated by hardware and an intend ed software access the software access has priority and determines the final value of the respective bit A summary of the protected bits implemented in the ST10R165 can be found at the end of chapter Architectural Overview 39 254 3 Central Processing Unit ST10R165 3 3 INSTRUCTION STATE TIMES Basically the time to execute an instruction de pends on where the instruction is fetched from and where possible operands are read from or written to The fastest processing mode of the ST10R165 is to execute a program fetched from fast external memory no wait states
55. bus interface EA 0 On the ST10R165 which is a romless device EA must be kept to 0 during reset The Non Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal eg a power fail signal It also serves to validate the PWRDN instruction that switches the ST10R165 into Power Down mode 111 254 This is advanced information from SGS THOMSON Details are subject to change without notice 6 Dedicated Pins ST10R165 The Reset Input RSTIN allows to put the ST10R165 into the well defined reset condition either at power up or external events like a hardware failure or manual reset The input voltage threshold of the RSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input The Reset Output RSTOUT provides a special reset signal for external circuitry RSTOUT is activated at the beginning of the reset sequence triggered via RSTIN a watchdog timer overflow or by the SRST instruction RSTOUT remains active low until the EINIT instruction is executed This allows to initialize the controller before the external circuitry is activated 112 254 The Oscillator Input XTAL1 and Output XTAL2 connect the internal clock oscillator to the external crystal An external clock signal may be fed to the input XTAL1 leaving XTAL2 open The Flash Programming Voltage input VPP provides the programming voltage that is required to erase an
56. case of a task scheduler that switches between independ ent tasks the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered CPU Interrupt Status IEN ILVL The Interrupt Enable bit allows to globally enable IEN 1 or disable IEN 0 interrupts The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is updated by hardware upon entry into an interrupt service routine but it can also be modified via soft ware to prevent other interrupts from being ac knowledged In case an interrupt level 15 has been assigned to the CPU it has the highest pos sible priority and thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details please refer to chapter Interrupt and Trap Func tions After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the ini tial CPU activity SON MICROELECTRONICS CPU SPECIAL FUNCTION REGISTERS Cont d The Instruction Pointer IP This register determines the 16 bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the ST10R165 s address space and thus it cannot directly be ac IP as 15 14 13 12 11 10 9 8 3 Central Processing Unit S
57. control registers through instructions which operate on word data types their upper 8 bits 15 8 will return zeros when read and will discard written data The layout of the Interrupt Control registers shown below applies to each xxlC register where xx stands for the mnemonic for the respective source 63 254 4 Interrupt and Trap Functions ST10R165 INTERRUPT SYSTEM STRUCTURE Cont d XxlC yyyyh zzh 15 14 13 12 11 10 Group Level SFR area Reset Value 00h Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority Interrupt Priority Level Defines the priority level for the arbitration of requests Fh Highest priority level Oh Lowest priority level Interrupt Enable Control Bit individually enables disables a specific source 0 Interrupt request is disabled 1 Interrupt Request is enabled Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs It is cleared automatically upon en try into the interrupt service routine or upon a PEC service In the case of PEC service the Interrupt Request flag remains set if the COUNT field in register PECCx of the selected PEC channel dec rements to zero This allows a normal CPU inter rupt to respond to a complete
58. ed Important timing characteristics of the external bus interface waitstates ALE length and Read Write Delay have been made programmable to allow the user the adaption of a wide range of dif ferent types of memories and or peripherals Ac cess to very slow memories or peripherals is sup ported via a particular Ready function For applications which require less than 64 KBytes of address space a non segmented mem ory model can be selected where all locations can be addressed by 16 bits and thus Port 4 is not needed as an output for the upper address bits A23 A19 A17 A16 as is the case when using the segmented memory model The on chip XBUS is an internal representation of the external bus and allows to access integrat ed application specific peripherals modules in the same way as external components It provides a defined interface for these customized peripher als Clock Generator The on chip clock generator provides the ST10R165 with its basic clock signal that controls all activities of the controller hardware The clock generator either directly feeds the external clock signal to the controller hardware or divides the ex ternal clock frequency by 2 depending on the de vice type This internal clock signal is also re ferred to as CPU clock Two separated clock sig nals are generated for the CPU itself and the pe ripheral part of the chip While the CPU clock is stopped during waitstates or during the
59. ferent priority levels level 0 cannot be arbitrated Interrupt requests that are programmed to priority levels 15 or 14 ie ILVL 111Xb will be serviced by the PEC unless the COUNT field of the asso ciated PECC register contains zero In this case the request will be serviced by normal interrupt processing instead Interrupt requests that are programmed to priority levels 13 through 1 will al ways be serviced by normal interrupt processing Note Priority level 0000b is the default level of the CPU Therefore a request on level 0 will never be serviced because it can never in terrupt the CPU However an enabled inter rupt request on level 0000b will terminate the ST10R165 s Idle mode and reactivate the CPU Figure 4 1 Priority Levels and PEC Channels Interrupt Control Register PEC Control SGS THOMSON YA MICROELECTRONICS 4 interrupt and Trap Functions ST10R165 For interrupt requests which are to be serviced by the PEC the associated PEC channel number is derived from the respective ILVL LSB and GLVL see figure below So programming a source to priority level 15 ILVL 1111b selects the PEC channel group 7 4 programming a source to pri ority level 14 ILVL 1110b selects the PEC chan nel group 3 0 The actual PEC channel number is then determined by the group priority field GLVL Simultaneous requests for PEC channels are pri oritized according to the PEC channel number where channel 0 has
60. function may either be combined with the pin s main function or may be used instead of it ie if the main pin function is not required Interrupt signals may be connected to TAIN T2IN the timer input pins CAPIN the capture input of GPT2 For each of these pins either a positive a nega tive or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is per formed in the control register of the peripheral de vice associated with the respective port pin The peripheral must be programmed to a specific op erating mode to allow generation of an interrupt by the external signal The priority of the interrupt re quest is determined by the interrupt control regis ter of the respective peripheral interrupt source and the interrupt vector of this source will be used to service the external interrupt request Note In order to use any of the listed pins as ex ternal interrupt input it must be switched to input mode via its direction control bit DPx y in the respective port direction control regis ter DPx Pins T2lN or TAIN can be used as external inter rupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control regis ters T2CON or TACON to 101b The active edge of the external input signal is determined by bit fields T2l
61. hard ware during each single cycle of a multiply or di vide instruction MDC FFOEh 87h 15 14 1 SFR 11 1 Multiply Divide Register In Use 3 12 0 9 8 7 6 5 4 3 2 1 3 Central Processing Unit ST10R165 When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared to be prepared for the new calcu lation After completion of the new division or mul tiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register which might be of interest for the user The remaining portions of the MDC register are re served for dedicated use by the hardware and should never be modified by the user in another way as described above Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed A detailed description of how to use the MDC reg ister for programming multiply and divide algo rithms can be found in chapter System Program ming Reset Value 0000h 0 0 Cleared when register MDL is read via software 1 Set when register MDL or MDH is written via software or when a multiply or divide instruction is executed Internal Machine Status The multiply divide unit uses these
62. idle mode the peripheral clock keeps running Both clocks are switched off when the power down mode is entered SGS THOMSON YA MICROELECTRONICS 1 3 THE ON CHIP PERIPHERAL BLOCKS The ST10R165 family clearly separates peripher als from the core This structure permits the maxi mum number of operations to be performed in par allel and allows peripherals to be added or re moved from family members without modifications to the core Each functional block processes data independently and communicates information over common buses Peripherals are controlled by data written to the respective Special Function Registers SFRs These SFRs are located either within the standard SFR area 00 FEOO0h 00 FFFFh or within the extended ESFR area 00 F000h 00 F1FFh These built in peripherals either allow the CPU to interface with the external world or provide func tions on chip that otherwise were to be added ex ternally in the respective system The ST10R165 peripherals are e Two General Purpose Timer Blocks GPT1 and GPT2 e Two Serial Interfaces ASCO and SSC e A Watchdog Timer e Seven IO ports with a total of 77 IO lines Each peripheral also contains a set of Special Function Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each pe ripheral
63. ie for forwarding op erand read and write values resolves most of the possible conflicts eg multiple usage of buses in a time optimized way and thus avoids that the pipeline becomes noticeable for the user in most cases However there are some very rare cases where the circumstance that the ST10R165 is a pipelined machine requires attention by the pro grammer In these cases the delays caused by pipeline conflicts can be used for other instruc tions in order to optimize performance a Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register is mostly not capable of using a new CP value which is to be updated by an immediately preceding instruction Thus to make sure that the new CP value is used at least one instruction must be inserted between a CP changing and a subsequent GPR using in struction as shown in the following example In SCXT CP 4 OFCOOh Select a new context Ip must not be an instruction using 7a GPR Tonio MOV RO datax write to GPR 0 in the new context a Data Page Pointer Updating An instruction which calculates a physical oper and address via a particular DPPn n 0 to 3 reg ister is mostly not capable of using a new DPPn 36 254 register value whichis to be updated by an imme diately preceding instruction Thus to make sure that the new DPPn register value is used at least one instruction must be inserted between a DP
64. instruc tion Internal RAM operand reads via indirect address ing modes Internal SFR operand reads immediately after writing External operand reads External operand writes Testing Branch Conditions immediately after PSW writes SGS THOMSON YA MICROELECTRONICS 3 4 CPU SPECIAL FUNCTION REGISTERS The core CPU requires a set of Special Function Registers SFRs to maintain the system state in formation to supply the ALU with register ad dressable constants and to control system and bus configuration multiply and divide ALU opera tions code memory segmentation data memory paging and accesses to the General Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can simply be con trolled by means of any instruction which is capa ble of addressing the SFR memory space a lot of flexibility has been gained without the need to create a set of system specific instructions Note however that there are user access restric tions for some of the CPU core SFRs to ensure proper processor operations The instruction SGS THOMSON YA MICROELECTRONICS 3 Central Processing Unit ST10R165 pointer IP and code segment pointer CSP cannot be accessed directly at all They can only be changed indirectly via branch instructions The PSW SP and MDC registers can be modified not only explicitly by th
65. instruction cycle the source request with the highest current priority will be determined by the interrupt system This request will then be serviced if its priority is higher than the current CPU priority in register PSW Interrupt System Register Description Interrupt processing is controlled globally by regis ter PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additional ly the different interrupt sources are controlled in dividually by their specific interrupt control regis ters IC Thus the acceptance of requests by the CPU is determined by both the individual inter rupt control registers and the PSW PEC services ky 3 4 Interrupt and Trap Functions ST10R165 SON MICROELECTRONICS are controlled by the respective PECCx register and the source and destination pointers which specify the task of the respective PEC service channel Interrupt Control Registers All interrupt control registers are organized identi cally The lower 8 bits of an interrupt control regis ter contain the complete interrupt status informa tion of the associated source which is required during one round of prioritization the upper 8 bits of the respective register are reserved All inter rupt control registers are bit addressable and all bits can be read or written via software This al lows each interrupt source to be programmed or modified with just one instruction When access ing interrupt
66. interrupt source whose individual In terrupt Enable flag was set before the Idle mode was entered regardless of bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority level of the requesting source is high er than the current CPU priority and the interrupt System is globally enabled After the RETI Return from Interrupt instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction Otherwise if the interrupt request can not be serviced because of a too low priority or a globally disabled interrupt system the CPU imme diately resumes normal program execution with the instruction following the IDLE instruction For a request which was programmed for PEC service a PEC data transfer is performed if the pri ority level of this request is higher than the current CPU priority and the interrupt system is globally enabled After the PEC data transfer has been completed the CPU remains in Idle mode Other wise if the PEC request cannot be serviced be cause of atoo low priority or a globally disabled in terrupt system the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction 215 254 This is advanced information from SGS THOMSON Details are subject to change without notice 14 Power Reduction Modes ST10R165 ID
67. is 8000h or 80h Multiplica tion Division In Progress 0 There is no multiplication division in progress 1 A multiplication division has been interrupted User General Purpose Flag May be used by the application software Interrupt and EBC Control Fields HLDEN ILVL IEN Define the response tointerrupt requests and enable external bus arbitration Described in section Interrupt and Trap Functions 44 254 SGS THOMSON YA MICROELECTRONICS CPU SPECIAL FUNCTION REGISTERS Cont d ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status due to the last recently performed ALU operation They are set by most of the instructions due to specific rules which de pend on the ALU or data movement operation per formed by an instruction After execution of an instruction which explicitly updates the PSW register the condition flags can not be interpreted as described in the following because any explicit write to the PSW register su persedes the condition flag values which are im plicitly generated by the CPU Explicitly reading the PSW register supplies a read value which rep resents the state of the PSW register after execu tion of the immediately preceding instruction Note After reset all of the ALU status bits are cleared N Flag For most of the ALU operations the N flag is set to 1 if the most significant bit of the re sult conta
68. is found in other microcon trollers Through the use of Compare and Incre ment or Decrement instructions the user can make comparisons to any value This allows loop counters to cover any range This is particularly advantageous in table searching Saving of system state is automatically performed on the internal system stack avoiding the use of in structions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and re quire the same execution time as branch instruc tions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and high level lan guages SGS THOMSON YA MICROELECTRONICS 1 Architectural Overview ST10R165 BASIC CPU CONCEPTS AND OPTIMIZATION Cont d Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined de sign an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and oper ands while reducing pipeline holds These con cepts however do not preclude the use of com plex instructions which are required by microcon troller users The following goals were used to de sign the instruction set 1 Provide powerful instructions to perform opera tions
69. lowest and channel 7 has highest priority Note All sources that request PEC service must be programmed to different PEC channels Otherwise an incorrect PEC channel may be activated MCA02005 65 254 4 Interrupt and Trap Functions ST10R165 INTERRUPT SYSTEM STRUCTURE Cont d The table below shows in a few examples which action is executed with a given programming of an in terrupt control register Priority Level Type of Service ILVL GLVL COUNT 00h COUNT 00h 1 1 1 1111 CPU interrupt PEC service level 15 group priority 3 channel 7 1111 CPU interrupt PEC service level 15 group priority 2 channel 6 1110 CPU interrupt PEC service level 14 group priority 2 channel 2 1101 CPU interrupt CPU interrupt level 13 group priority 2 level 13 group priority 2 0001 CPU interrupt CPU interrupt level 1 group priority 3 level 1 group priority 3 0001 CPU interrupt CPU interrupt level 1 group priority 0 level 1 group priority 0 Note All requests on levels 13 1 cannot initiate sically represents the arithmetic status of the PEC transfers They are always serviced by CPU the upper byte of the PSW controls the inter an interrupt service routine No PECC regis rupt system of the ST10R165 and the arbitration sd E DIR and no COUNT field is mechanism for the external bus interface checked 1 0 0 10 11 XX Note Pipeline effects have to be considered when enabling disabling interrupt requests I
70. memory accesses are performed by a particular on chip External Bus Controller EBC which is automatically invoked by the CPU whenever a code or data address refers to the external ad dress space If possible the CPU continues oper ating while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous ac cess has been completed the CPU will be held by the EBC until the request can be satisfied The EBC is described in a dedicated chapter MDH MDL Mul Div HW JE Bit Mask Gen R15 Internal General Instr Ptr ROM Instr Reg Purpose not ipeli 16 Bit Implemented on the ST10R165 Registers Barrel Shift RO a aa BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Code Seg Ptr Data Pg Ptrs VR02045B March 1995 This is advanced information from SGS THOMSON Details are subject to change without notice 31 254 3 Central Processing Unit ST10R165 The on chip peripheral units of the ST10R165 work nearly independently of the CPU with a sep arate clock generator Data and control informa tion is interchanged between the CPU and these peripherals via Special Function Registers SFRs Whenever peripherals need a non deter ministic CPU
71. memory peripheral data become valid Read cycles Input data is latched and the com mand signal is now deactivated This causes the accessed device to remove its data from the data bus which is then tri stated again Write cycles The command signal is now deacti vated If a subsequent external bus cycle is re quired the EBC places the respective address on the address bus The data remain valid on the bus until the next external bus cycle is started pa Bus Cycle Address P1 Segment P4 ALE WR 116 254 MCTO2061 SGS THOMSON YA MICROELECTRONICS EXTERNAL BUS MODES Cont d Switching between the Bus Modes The EBC allows to switch between different bus modes dynamically ie subsequent external bus cycles may be executed in different ways Certain address areas may use multiplexed or demulti plexed buses or use READY control or predefined waitstates A change of the external bus characteristics can be initiated in two different ways Reprogramming the BUSCON and or ADDR SEL registers allows to either change the bus mode for a given address window or change the size of an address window that uses a certain bus mode Reprogramming allows to use a great number of different address windows more than BUSCONSs are available on the expense of the overhead for changing the registers and keeping appropriate tables Switching between predefined address win dows automatically sel
72. of the standard device Therefore these characteristics are not contained in this manual but rather provided in a separate March 1995 ST10R165 User Manual Chapter 18 DEVICE SPECIFICATION Data Sheet which can be updated more fre quently Please referto the current version of the ST10R165 Data Sheet for all electrical parameters Note In any case the specific characteristics of a device should be verified before a new de sign is started This ensures that the used information is up to date The following figure shows the pin diagram of the ST10R165 It shows the location of the different supply and IO pins A detailed description of all the pins is also found in the Data Sheet 251 254 This is advanced information from SGS THOMSON Details are subject to change without notice 18 Device Specification ST10R165 Figure 18 1 Pin Description of the ST10R165 TQFP 100 Package N N N N N N O Pe 7 BREQ Ll P6 6 HLDA L1 P6 5 HOLD 1 P5 12 T6IN O P5 11 T5EUD C P5 10 TGEUD P2 15 EX7 P2 14 EX6 1 P2 13 EX5 P2 12 EX4 T P2 11 EX3 P2 10 EX2 T P2 9 EX1IN P2 8 EXOIN P6 4 CS4 CS3 Ll P6 2 CS2 CS1 Ll P6 3 Ll P6 1 gt o eo oO oO c oe oO X oO Oo o ol o X o o oO n2 o oO eo Co Qo Co Co 3 co O co ol Qo co P1H 6 A14 P1H 5 A13 P1H 4 A12 P1H 3 A11 P1H 2 A10 Vss Vop P1H 1 A9 P3 1 TEOUT P1H 0 A8 P3 2 CAPIN P1L 7 A7 P3 3 TGOUT
73. possible interrupt response and in many cases is sufficient to service the respective peripheral re controlled by a dedicated PEC Channel Counter Control register PECCx and a pair of pointers for source SRCPx and destination DSTPx of the data transfer The PECC registers control the action that is per quest eg serial channels etc Each channel is formed by the respective PEC channel PECCx FECyh 6zh see table SFR Reset Value 0000h 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw PEC Transfer Count Counts PEC transfers and influences the channel s action see table below Byte Word Transfer Selection 0 Transfer a Word 1 Transfer a Byte Increment Control Modification of SRCPx or DSTPx 0 0 Pointers are not modified 0 1 Increment DSTPx by 1 or 2 BWT 1 0 Increment SRCPx by 1 or 2 BWT 1 1 Reserved Do not use this combination changed to 10 by hardware PEC Control Register Addresses 68 254 SGS THOMSON YA MICROELECTRONICS OPERATION OF THE PEC CHANNELS Cont d Byte Word Transfer bit BWT controls if a byte or a word is moved during a PEC service cycle This selection controls the transferred data size and the increment step for the modified pointer Increment Control Field INC specifies if one of the PEC pointers is incremented after the PEC transfer It is not possible to increment both point ers however If the pointers are not modified INC 00 the respec
74. register TFR and the CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate unimplemented in structions The trap service routine can examine the faulting instruction to decode operands for un implemented opcodes based on the stacked IP In order to resume processing the stacked IP value must be incremented by the size of the undefined instruction which is determined by the user be fore a RETI instruction is executed Protection Fault Trap Whenever one of the special protected instruc tions is executed where the opcode of that instruc tion is not repeated twice in the second word of the instruction and the byte following the opcode is not the complement of the opcode the PRTFLT flag in register TFR is set and the CPU enters the protec tion fault trap routine The protected instructions SGS THOMSON YA MICROELECTRONICS 4 interrupt and Trap Functions ST10R165 include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed onto the sys tem stack for the protection fault trap is the ad dress of the instruction that caused the trap Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine The IP value pushed onto the system stack i
75. return location that is saved on the stack is not the next instruction in the instruction flow but rather the multiply or divide instruction it self as this instruction has been interrupted and will be completed after returning from the service routine SGS THOMSON YA MICROELECTRONICS 4 Interrupt and Trap Functions ST10R165 SAVING THE STATUS DURING INTERRUPT SERVICE Cont d Figure 4 3 Task Status saved on the System Stack High Addresses Low Addresses a System Stack before Interrupt Entry The interrupt request flag of the source that is be ing serviced is cleared The IP is loaded with the vector associated with the requesting source the CSP is cleared in case of segmentation and the first instruction of the service routine is fetched from the respective vector location which is ex pected to branch to the service routine itself The data page pointers and the context pointer are not affected When the interrupt service routine is left RETI is executed the status information is popped from the system stack in the reverse order taking into account the value of bit SGTDIS Context Switching An interrupt service routine usually saves all the registers it uses on the stack and restores them before returning The more registers a routine us es the more time is wasted with saving and re SGS THOMSON YA MICROELECTRONICS b System Stack after Interrupt Entry Unsegmented Status of Interr
76. rw rw rw rw rw L l s P1h FFO6h 83h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E t R rw rw rw rw rw rw rw rw P1X y Port data register P1H or P1L bit y DP1L F104h 82h ESFR Reset Value 00h 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 tv ue rrr rm Dee E90 aS Gt E ee alga Cx DP1L DP1L DP1L DP1L DP1L DP1L DP1L DP1L 7 6 DP1H F106h 83h ESFR Reset Value 00h 15 14 13 12 11 10 7 8 5 4 3 0 9 8 Fora pope o4 mo quomm qaum DP1H 7 bs ode Ve gx x ome E me Se ee eee mx 2 1 rw rw rw rw rw rw rw rw Port direction register DP1H or DP1L bit y DP1X y 0 Port line P1X y is an input high impedance DP1X y 1 Port line P1X y is an output s SGS THOMSON 125A YA MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 1 Cont d 5 2 1 Alternate Functions of PORT1 When a demultiplexed external bus is enabled PORT is used as address bus Note that demultiplexed bus modes use PORT1 as a 16 bit port Otherwise all 16 port lines can be used for general purpose IO During external accesses in demultiplexed bus modes PORT1 outputs the 16 bit intra segment address as an alternate output function During external accesses in multiplexed bus modes when no BUSCON register selects a de multiplexed bus mode PORT1 is not used and is available for general purpose IO Figure 5 5 PORT1 IO and Alternate Functions Alternate Function 3 P1H 7 P1H 6 P1H 5 P1H 4
77. searching or dered tables and non ordered tables respectively MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc SGT LOO lest whether target has not been found Note The last entry in the table must be greater than the largest possible target MOV RO i4 BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc NET LOO Test whether target is not found AND the end of table j has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000h SGS THOMSON YA MICROELECTRONICS 15 System Programming ST10R165 15 8 PERIPHERAL CONTROL AND INTERFACE All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory or by explicitly addressing the SFRs associated with the specific peripherals After resetting the ST10R165 all peripherals ex cept the watchdog timer are disabled and initial ized to default values A desired configuration of a specific peripheral is programmed using MOV in structions of either constants or memory values to specific SFRs Specific control flags may also be altered via bit instructions Once in operation the peripheral operates auton omously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine Information may also be p
78. sequence 233 254 15 System Programming ST10R165 Notes 234 254 S7 SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual A MICROELECTRONICS Chapter 16 REGISTER SET This section summarizes all registers which are Elements implemented in the ST10R165 and explains the REG NAME Name of this register description format which is used in the chapters T describing the function and layout of the SFRs A16 A8 Long 16 bit address Short 8 bit ad For easy reference the registers are ordered ac dress cording to two different keys except for GPRs E SFR Register space SFR or ESFR e Ordered by address to check which register a EN Register contents after reset given address references 0 1 defined value X undefined U e Ordered by register name to find the location of unchanged undefined after power a specific register up Register Description Format hwbit Bits that are set cleared by hard In the respective chapters the function and the ware are marked with a shaded ac layout of the SFRs is described in a specific for cess box mat which provides a number of details about the described special function register The example below shows how to interpret these details A word register looks like this REG NAME A16h A8h E SFR Reset Value h 15 14 11 13 12 10 9 8 7 6 5 4 3 2 1 0 write read only only Ww r rw rw rw bit field name Explanation of bit field name Descriptio
79. standard DPP scheme Note Instructions EXTP and EXTS inhibit inter rupts the same way as ATOMIC Short Addressing in the Extended SFR ESFR Space The short addressing modes of the ST10R165 REG or BITOFF implicitly access the SFR space The additional ESFR space would have to be accessed via long addressing modes MEM or Rw The EXTR extend register instruction al lows to redirect accesses in short addressing modes to the ESFR space for 1 4 instructions so the additional registers can be accessed this way too The EXTPR and EXTSR instructions combine the DPP override mechanism with the redirection to the ESFR space using a single instruction Note Instructions EXTR EXTPR and EXTSR in hibit interrupts the same way as ATOMIC The switching to the ESFR area and data page overriding is checked by the develop ment tools or handled automatically Nested Locked Sequences Each of the described extension instruction and the ATOMIC instruction starts an internal exten sion counter counting the effected instructions When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new in struction This allows to construct locked sequenc es longer than 4 instructions Note eInterrupt latencies may be increased when using locked code sequences e PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked
80. supports capture and re load operation with extended functionality Each block has alternate input output functions and specific interrupts associated with it 8 1 TIMER BLOCK GPT1 From a programmer s point of view the GPT1 block is composed of a set of SFRs as summa rized below Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded Figure 8 1 SFRs and Port Pins Associated with Timer Block GPT1 Ports amp Direction Control Alternate Functions Data Registers T2IN P3 7 TSIN P3 6 T4IN P3 5 T30UT P3 3 ODP3 T2EUD P5 15 T3EUD P3 4 T4EUD P5 14 Port 3 Open Drain Control Register Port 3 Direction Control Register Port 3 Data Register GPT1 Timer 2 Control Register GPT1 Timer 3 Control Register GPT1 Timer 4 Control Register March 1995 Control Registers Interrupt Control GPT1 Timer 2 Register GPT1 Timer 3 Register GPT1 Timer 4 Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Interrupt Control Register 139 254 This is advanced information from SGS THOMSON Details are subject to change without notice 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d All three timers of block GPT1 T2 T3 T4 can run in 3 basic modes which are timer gated timer and counter mode and all timers can either count up or down Each timer has an alternate input function pin on Port 3 ass
81. the end of reset the selected bus configura tion will be written to the BUSCONO register The configuration of the high byte of PORTO will be copied into the special register RPOH This read only register holds the selection for the number of chip selects and segment addresses Software can read this register in order to react according to the selected configuration if required When the reset is terminated the internal pullup devices are switched off and PORTO will be switched to the appropriate operating mode During external accesses in multiplexed bus modes PORTO first outputs the 16 bit intra seg ment address as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data In 8 bit data bus mode two memory cycles are re quired for word accesses the first for the low byte and the second for the high byte of the word Dur ing write cycles PORTO outputs the data byte or word after outputting the address During external accesses in demultiplexed bus modes PORTO reads the incoming instruction or data word or outputs the data byte or word 16 bit MUX Bus 89 254 5 Parallel Ports ST10R165 PORT 0 Cont d When an external bus mode is enabled the direc tion of the port pin and the loading of data into the port output latch are controlled by the bus control ler hardware The input of the port output latch is disconnected from the internal bus and is swi
82. the result of nor malized floating point numbers through the over flow V flag in the PSW This flag is set when a one is shifted out of the carry bit during shift right operations The overflow flag and the carry flag are then used to round the floating point result based on the desired rounding algorithm 15 10 TRAP INTERRUPT ENTRY AND EXIT Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level Traps are entered regardless of the current CPU priority When either a trap or inter rupt routine is entered the state of the machine is preserved on the system stack and a branch to the appropriate trap interrupt vector is made All trap and interrupt routines require the use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches back to the location where the trap or in terrupt occurred 232 254 15 11 UNSEPARABLE SEQUENCES The instructions of the ST10R165 are very effi cient most instructions execute in one machine cycle and even the multiplication and division are interruptable in order to minimize the response la tency to interrupt requests internal and external In many microcontroller applications this is vital Some special occasions however require certain code sequences eg semaphore handling to be uninterruptable to function properly This ca
83. which currently require sequences of instructions and are frequently used Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines 2 Avoid complex encoding schemes by placing operands in consistent fields for each instruc tion Also avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplify ing the development of compilers and assem blers 3 Provide most frequently used instructions with one word instruction formats All other instruc tions are placed into two word formats This allows all instructions to be placed on word boundaries which alleviates the need for com plex alignment hardware It also has the benefit of increasing the range for relative branching instructions The high performance offered by the hardware im plementation of the CPU can efficiently be utilized by a programmer via the highly functional SGS THOMSON YA MICROELECTRONICS ST10R165 instruction set which includes the fol lowing instruction classes Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instruct
84. will only run if T6 R 1 and the gate is active It will stop if either T6R 0 or the gate is inactive Note A transition of the gate signal at pin T6IN does not cause an interrupt request Figure 8 14 Block Diagram of Core Timer T6 in Gated Timer Mode SGS THOMSON YA MICROELECTRONICS Interrupt Request MCB02028 159 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT2 Cont d Timer 6 in Counter Mode Counter mode for the core timer T6 is selected by setting bit field T6M in register T CON to 001b In counter mode timer T6 is clocked by a transition at the external input pin T6IN which is an alternate function of P5 12 The event causing an increment or decrement of the timer can be a positive a neg ative or both a positive and a negative transition at this pin Bit field T6l in control register TOCON selects the triggering transition see table below The maximum input frequency which is allowed in counter mode is fopy 4 2 5 MHz 9 fce 220 MHz To ensure that a transition of the count input signal which is applied to T6IN is correctly recognized its level should be held high or low for at least 4 fco cycles before it changes Figure 8 15 Block Diagram of Core Timer T6 in Counter Mode Interrupt tar Regue TxOTL feo D TxOUT TxOE MCB02030 GPT2 Core Timer T6 Counter Mode Input Edge Selection T6l Triggering Edge for Counter Increment Decrement ooo O Non
85. 0R165 In asynchronous mode 8 or 9 bit data transfer pari ty generation and the number of stop bits can be selected Parity framing and overrun error detec tion is provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communica tion a mechanism to distinguish address from data bytes is included Testing is supported by a loop back option A 13 bit baud rate generator provides the ASCO with a separate serial clock signal The operating mode of the serial channel ASCO is controlled by its bitaddressable control register SOCON This register contains control bits for mode and error check selection and status flags for error identification Figure 9 1 SFRs and Port Pins associated with ASCO Ports amp Direction Control Alternate Functions Data Registers RXDO P3 11 TXDO P3 10 Port 3 Open Drain Control Register Port 3 Direction Control Register ASCO Baud Rate Generator Reload Register ASCO Transmit Buffer Register write only ASCO Transmit Interrupt Control Register SOTBIC ASCO Transmit Buffer Interrupt Control Reg March 1995 Control Registers Interrupt Control Port 3 Data Register ASCO Control Register ASCO Receive Buffer Register read only ASCO Receive Interrupt Control Register ASCO Error Interrupt Control Register 169 254 This is advanced information from SGS THOMSON Details are subject to change without notice
86. 1 Alternate Functions of Port3 1 0 0 eee ees 98 bib POM AS uci etes tete eso dE ath ate et Ae EY ense PIN E MPH qe 102 5 5 1 Alternate Functions of Port 4 1 0 2 ee eee 102 5 6 FP OM Denes eco tme det Ed tm bob o th e eua Ba deg scio d ba aaah 084 105 5 6 1 Alternate Functions of Portb liliis 105 bi 3 Potts Big du eee oe ideals honed dnt ae aad da ett ede ey tgee as Oed ote ut 107 5 7 1 Alternate Functions of Port 6 1 0 0 et tens 108 6 Dedicated Pins 5c ll ces dette ees ee Sh tet eee eas 111 s SGS THOMSON 10 1 0 54 YA MICROELECTRONICS Table of Contents 7 External Bus Interface llels esses 113 Z4 Single Ghip Mode e usebibee erri ooh ated d Ex Bees art oo ed brune teww is 114 7 2 External Bus Modes eiric tasetten a E E at te ara a 114 7 3 Programmable Bus Characteristics llli eese 122 7 4 READY Controlled Bus Cycles 0 0000 ce res 127 7 5 Controlling the External Bus Controller llli elei 128 1 6 EBC Idle State onm e REP SS UE X MORS a Ree e 135 7 External Bus Arbitration llli rh 135 T The XBUS Interface eoe eet a a eee eee ee A aed RUNE B NEA 138 8 General Purpose Timer Units ssee 139 81 TimerBlock GPT1 ssusseleeeeelee tees 139 8 1 GPT1 Gore Timer Takei iu fa che Oat ew a ee ee She ee Sy es Mens 141 8 1 2 GPT1 Auxiliary Timers T2 and T4 0 2 2 0 ee ee 146 8 1 3 Interrupt Control f
87. 1000 0000 0000 4 After PUSH H 11111018 1111 1110 A H z 1111 1012 1111 1110 f E 111101141 1111 1110 2 256 words The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack this circular stack mechanism only requires to move that por tion of stack data which is really to be re used ie the upper part of the defined stack area instead of the whole stack area Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled as the stack pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 words STKSZ 000b to 100b it does not work with op tion STKSZ 111b which uses the com plete internal RAM for system stack SGS THOMSON YA MICROELECTRONICS STACK OPERATIONS Cont d When a boundary is reached the stack underflow or overflow trap is entered where the user moves a predetermined portion of the internal stack to or from the external stack The amount of data trans ferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately one quarter to one tenth the size of
88. 95 MICROELECTRONICS Chapter 2 MEMORY ORGANIZATION grated XBUS peripherals and external memory are mapped into one common address space The ST10R165 provides a total addressable memory space of 16 MBytes This address space is arranged as 256 segments of 64 KBytes each and each segment is again subdivided into four data pages of 16 KBytes each see figure below RAM SFR 00 FFFFh Area 00 FO00h Data Page 3 External 00 C000h Memory Data Page 2 00 8000h Data Page 1 Internal ROM Area 00 4000h Data Page 0 00 0000h System Segment 64 KByte VR02045A 21 254 This is advanced information from SGS THOMSON Details are subject to change without notice 2 Memory Organization ST10R165 Space Most internal memory areas are mapped into seg ment 0 the system segment The upper 4 KByte of segment 0 00 F000h 00 FFFFh hold the In ternal RAM and Special Function Register Areas SFR and ESFR Code and data may be stored in any part ofthe in ternal memory areas except for the SFR blocks which may be used for control data but not for in structions Note The ST10R165 is a Romless device pro gram ROM must be in external memory Bytes are stored at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte ad dress Double words code only are stored in as cendi
89. A trap service routine however any class B trap occur ring will not be serviced until the class A trap serv ice routine is exited with a RETI instruction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost In the case where e g an Undefined Opcode trap class B occurs simultaneously with an NMI trap class A both the NMI and the UNDOPC flag is set the IP of the instruction with the undefined op code is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and imme diately pushed again because of the pending UN DOPC trap 82 254 External NMI Trap Whenever a high to low transition on the dedicat ed external NMI pin Non Maskable Interrupt is detected the NMI flag in register TFR is set and the CPU will enter the NMI trap routine The IP val ue pushed on the system stack is the address of the instruction following the one after which nor mal processing was interrupted by the NMI trap Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in regis ter TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an
90. BOR BX OR BMOV BMOVN explicitly set or clear specific bits The instructions BFLDL and BFLDH allow to manipulate up to 8 bits of a specific byte at one time The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is tak en The instructions JB and JNB also conditional jump instructions that refer to flags evaluate the specified bit to determine if the jump is to be taken Note Bit operations on undefined bit locations will always read a bit value of 0 while the write access will not affect the respective bit loca tion All instructions that manipulate single bits or bit groups internally use a read modify write se quence that accesses the whole word which con tains the specified bit s This method has several consequences e Bits can only be modified within the internal ad dress areas ie internal RAM and SFRs External locations cannot be used with bit instructions The upper 256 bytes of the SFR area the ESFR area and the internal RAM are bit addressable see chapter Memory Organization ie those register bits located within the respective sections SGS THOMSON YA MICROELECTRONICS 3 Central Processing Unit ST10R165 can be directly manipulated using bit instructions The other SFRs must be accessed byte word wise Note All GPRs are bit addressable independent of the allocation of the register bank via the context pointer CP Even GPRs which are allocated to not
91. CD calculations are performed by converting BCD data to binary data performing the desired calculations using standard data types and converting the result back to BCD data Due to the enhanced perfomance of division in structions binary data is quickly converted to BCD data through division by 10d Conversion from BCD data to binary data is enhanced by multiple bit shift instructions This provides similar perform ance compared to instructions directly supporting BCD data types while no additional hardware is required 223 254 15 System Programming ST10R165 15 4 STACK OPERATIONS The ST10R165 supports two types of stacks The system stack is used implicitly by the controller and is located in the internal RAM The user stack provides stack access to the user in either the in ternal or external memory Both stack types grow from high memory addresses to low memory ad dresses Internal System Stack A system stack is provided to store return vectors segment pointers and processor status for proce dures and interrupt routines A system register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped The internal system stack can also be used to temporarily store data or pass it between subrou tines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking scheme pro
92. CLKOUT and P3 12 BHE WRH Write DP3 x Direction Latch Read DP3 x Enable Write P3 x Alternate I n t e r n a Output Port Output Latch SGS THOMSON YA MICROELECTRONICS Alternate Function Data P3 12 BHE P3 15 CLKOUT Output Buffer MCB02075 101 254 5 Parallel Ports ST10R165 5 5 PORT 4 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP4 5 5 1 Alternate Functions of Port 4 During external bus cycles that use segmentation ie an address space above 64 KByte a number of Port 4 pins may output the segment address lines The number of pins that is used for segment address output determines the external address space which is directly accessible The other pins of Port 4 if any may be used for general purpose IO If segment address lines are selected the al P4 FFC8h E4h SFR 15 14 18 12 11 10 9 8 Poo qv moque mpm momo c qom RR ot aie uu Lom lal cae lee Gd ow su x cael x Port data register P4 bit y ternate function of Port 4 may be necessary to ac cess eg external memory directly after reset For this reason Port 4 will be switched to its alternate function automatically The number of segment address lines is selected via PORTO during reset The selected value can be read from bitfield SALSEL in register RPOH read only eg in order to check the configu
93. DDRSEL4 allow to define four independ ent address windows while all external accesses outside these windows are controlled via register BUSCONO Figure 7 1 SFRs and Port Pins Associated with the External Bus Interface Ports amp Direction Control Alternate Functions Address Registers PORTO PORT1 ALE RD WR WRL BHE WRH POL POH PORTO Data Registers P1L P1H PORT1 Data Registers Port 3 Direction Control Register Port 3 Data Register Port 4 Data Register Port 6 Open Drain Control Register Port 6 Direction Control Register Port 6 Data Register March 1995 Mode Registers Control Registers ADDRSELx Address Range Select Register 1 4 BUSCONx SYSCON RPOH Bus Mode Control Register 0 4 System Control Register Perbhotosinjiemn guration Register 113 254 This is advanced information from SGS THOMSON Details are subject to change without notice 7 External Bus Interface ST10R165 7 1 SINGLE CHIP MODE Single chip mode is entered when pin EA is high during reset In this case register BUSCONO is cleared except bit ALECTLO and bits BTYPO 1 0 POL 7 6 which also resets bit BUSACTO of BUSCONO register so no external bus is enabled In single chip mode the ST10R165 operates only with and out of internal resources No external bus is configured and no external peripherals and or memory can be accessed Also no port lines are occupied for the bus interface The ST10R165 be ing a Romless device
94. E 2 cycle will be aborted fopy Note After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled SGS SON 197 254 ky 26S THOMSON 11 Watchdog Timer ST10R165 The table below marks the possible ranges for the Note For safety reasons the user is advised to watchdog time which can be achieved using a rewrite WDTCON each time before the CPU clock of 20 MHz Some numbers are round watchdog timer is serviced ed to 3 significant digits Reload value Prescaler for fcpy in WDTREL 2 WDTIN 0 128 WDTIN 1 Fr 198 254 S7 SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ The built in bootstrap loader of the ST10R165 provides a mechanism to load the startup pro gram which is executed after reset via the serial interface In this case no external ROM memory or an internal ROM is required for the initialization code starting at location 00 0000h The bootstrap loader moves code data into the internal RAM but itis also possible to transfer data via the serial in terface into an external RAM using a second level loader routine External ROM memory is not nec essary However it may be used to provide lookup tables or may provide core code ie a set Figure 12 1 Bootstrap Loader Sequence Int Boot ROM BSL routine MICROELECTRONICS Chapter 12 BOOTSTRAP LOADER of general purpose subroutines eg for IO opera tions number crunching sy
95. EADY signal or by bus arbitration HOLD mode 75 254 4 Interrupt and Trap Functions ST10R165 INTERRUPT RESPONSE TIMES Cont d 4 5 1 PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the PEC data transfer being started The basic PEC response time for the ST10R165 is 2 instruction cycles In the figure below the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round dur ing cycle 2 In cycle 3 a PEC transfer instruction is injected into the decode stage of the pipeline suspending instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 com pletes the injected PEC transfer and resumes the execution of instruction N 1 All instructions that entered the pipeline after set ting of the interrupt request flag N 1 N 2 will be executed after the PEC data transfer Note When instruction N reads any of the PEC control registers PECC7 PECCO while a PEC request wins the current round of prior itization this round is repeated and the PEC data transfer is started one cycle later The minimum PEC response time is 3 states 150 ns 20 MHz CPU clock This requires program execution with the fastest bus configuration 16 bit demultiplexed no wait states no external op erand read requests and setting the interrupt re quest flag du
96. EGISTERS Cont d System Clock Output Enable CLKEN The system clock output function is enabled by setting bit CLKEN in register SYSCON to 1 If en abled port pin P3 15 takes on its alternate func tion as CLKOUT output pin The clock output is a 50 96 duty cycle clock whose frequency equals the CPU operating frequency foUT fcpu Note The output driver of port pin P3 15 is switched on automatically when the CLK OUT function is enabled The port direction bit is disregarded After reset the clock output function is disa bled CLKEN 0 Segmentation Disable Enable Control SGT DIS Bit SGTDIS allows to select either the segmented or non segmented memory mode In non segmented memory mode SGTDIS 1 it is assumed that the code address space is re stricted to 64 KBytes segment 0 and thus 16 bits are sufficient to represent all code addresses For implicit stack operations CALL or RET the CSP register is totally ignored and only the IP is saved to and restored from the stack SGS THOMSON YA MICROELECTRONICS 3 Central Processing Unit ST10R165 In segmented memory mode SGTDIS 0 it is assumed that the whole address space is availa ble for instructions For implicit stack operations CALL or RET the CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls if the CSP register is pushed onto the system sta
97. Fh of the internal RAM So up to 16 instructions may be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40h ie the first load ed instruction The bootstrap loading sequence is now terminated the ST10R165 remains in BSL mode however Most probably the initially loaded routine will load additional code or data as an av erage application is likely to require substantially more than 16 instructions This second receive loop may directly use the pre initialized interface ASCO to receive data and store it to arbitrary user defined locations This second level of loaded code may be the final application code It may also be another more so phisticated loader routine that adds a transmis sion protocol to enhance the integrity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go through several iterations or may directly executethefinal application Inall cases the ST10R165 will still run in BSL mode ie with the watchdog timer disabled and limited access to the memory space between 00 0000h 00 7FFFh All code fetches from this area 00 0000h 00 7FFFh or01 0000h 01 7FFFh if mappedto segment1 are re directed to the special Boot ROM Data fetches access will return undefined data on the ST10R165 which is a ROMless device 202 254 12 4 EX
98. GPT2 Cont d 8 2 1 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by its bitaddressable control register TECON Timer 6 Run Bit timer stops Setting T6R to 1 will start the timer In gated timer mode the timer will only run if T6R 1 and the gate is active high or low as pro grammed The timer can be started or stopped by software through bit T6R Timer T6 Run Bit If T R 0 the T6CON na is SFR 14 11 Timer 6 Input mi SEHR Depends on the Operating Mode see respective sections Timer 6 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 1XX Reserved Do not use this combination Reset Value 0000h Timer 6 Run Bit T6R 0 Timer Counter 6 stops T6R 1 Timer Counter 6 runs T6UD Timer 6 Up Down Control T6UDE Timer 6 External Up Down Enable T6OE Alternate Output Function Enable T6OE 0 Alternate Output Function Disabled T6OE 1 Alternate Output Function Enabled T6OTL Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software Timer 6 Reload Mode Enable T6SR 0 Reload from register CAPREL Disabled T6SR 1 Reload from register CAPREL Enabled For the effects of bits TEUD and T6UDE refer to the direction table below 156 254 SGS THOMSON YA MICROELECTRONICS
99. HOMSON YA MICROELECTRONICS lt SSCBR gt represents the content of the reload register taken as unsigned 16 bit integer The maximum baud rate that can be achieved when using a CPU clock of 20 MHz is 5 MBaud The table below lists some possible baud rates to gether with the required reload values and the re sulting bit times assuming a CPU clock of 20 MHZ 191 254 10 High Speed Synchronous Serial Interface ST10R165 10 4 ERROR DETECTION MECHANISMS The SSC is able to detect four different error con ditions Receive Error and Phase Error are detect ed in all modes while Transmit Error and Baudrate Error only apply to slave mode When an error is detected the respective error flag is set When the corresponding Error Enable Bit is set also an error interrupt request will be generated by setting SSCEIR see figure below The error in terrupt handler may then check the error flags to determine the cause of the error interrupt The er ror flags are not reset automatically like SSCEIR but rather must be cleared by software after serv icing This allows to service some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled errorflag s to prevent repeated interrupt requests A Receive Error Master or Slave mode is de tected when a new data frame is completely re ceived but the previous data was not read out of the rec
100. ITING BOOTSTRAP LOADER MODE In order to execute a program in normal mode the BSL mode must be terminated first The ST10R165 exits BSL mode upon a software reset ignores the level on POL 4 or a hardware reset POL 4 must be high then After a reset the ST10R165 will start executing from location 00 0000h of the external memory space 12 5 CHOOSING THE BAUDRATE FOR THE BSL The calculation of the serial baudrate for ASCO from the length of the first zero byte that is re ceived allows to feed the bootstrap loader of the ST10R165 with a wide range of baudrates How ever the upper and lower limits have to be kept in order to insure proper data transfer a CPU e 32 SOBRL 1 The ST10R165 uses timer T6 to measure the length of the initial zero byte The quantization un certainty of this measurement implies the first de viation from the real baudrate the next deviation is implied by the computation of the SOBRL reload value from the timer contents The formula below shows the association cPU PHost AIO SOBRL I9 72 T6 SGS THOMSON YA MICROELECTRONICS 12 Bootstrap Loader ST10R165 CHOOSING THE BAUDRATE FOR THE BSL Cont d For a correct data transfer from the host to the ST10R165 the maximum deviation between the internal initialized baudrate for ASCO and the real baudrate of the host should be below 2 5 The deviation Fg in percent between host baudrate and ST10R165 baudrate can be cal
101. Input Byte High Enable Write High Output SSC Shift Clock Input Output No pin assigned System Clock Output CLKOUT SCLK BHE RxDO TxDO MTSR MRST T2IN TSIN TAIN TSEUD TSOUT CAPIN T6OUT SGS THOMSON YA MICROELECTRONICS PORT 3 Cont d The port structure of the Port 3 pins depends on their alternate function see figures below When the on chip peripheral associated with a Port 3 pin is configured to use the alternate input function it reads the input latch which represents the state of the pin via the line labeled Alternate Data Input Port 3 pins with alternate input func tions are T2lN T3IN T4IN T3EUD and CAPIN When the on chip peripheral associated with a Port 3 pin is configured to use the alternate output function its Alternate Data Output line is ANDed with the port output latch line When using these alternate functions the user must set the direction of the port line to output DP3 y 1 and must set the port output latch P3 y 1 Otherwise the pin is in its high impedance state when configured as input or the pin is stuck at 0 when the port out SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 put latch is cleared When the alternate output functions are not used the Alternate Data Out put lineis in its inactive state which is a high level 1 Port 3 pins with alternate output functions are T6OUT T3OUT TxDO and CLKOUT When the on chip perip
102. LE MODE Cont d Figure 14 1 Transitions between Idle mode and active mode CPU Interru ot Rea uest Denied PEC Request Idle mode can also be terminated by a Non Mask able Interrupt ie a high to low transition on the NMI pin After Idle mode has been terminated by an interrupt or NMI request the interrupt system performs a round of prioritization to determine the highest priority request In the case of an NMI re quest the NMI trap will always be entered Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority The CPU will not go back into Idle mode when a CPU interrupt request is detected even when the interrupt was not serviced because of ahigher CPU priority or a globally disabled in terrupt system IEN 0 The CPU will only go back into Idle mode when the interrupt system is 216 254 denied Executed PEC Request globally enabled IENZ 1 and a PEC service on a priority level higher than the current CPU level is requested and executed Note An interrupt request which is individually en abled and assigned to priority level 0 will ter minate Idle mode The associated interrupt vector will not be accessed however The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the watch dog timer overflows To prevent th
103. M PROGRAMMING controllers can be built in macros thus providing the same names Directly Substitutable Instructions are instruc tions known from other microcontrollers that can be replaced by the following instructions of the ST10R165 Modification of System Flags is performed us ing bit set or bit clear instructions BSET BCLR All bit and word instructions can access the PSW register so no instructions like CLEAR CARRY or ENABLE INTERRUPTS are required External Memory Data Access does not require special instructions to load data pointers or explic itly load and store external data The ST10R165 provides a Von Neumann memory architecture and its on chip hardware automatically detects ac cesses to internal RAM GPRs and SFRs Substituted Instruction ST10R165 Instruction Function CLR Rn AND Rn 0h Clear register CPLB B BMOVN Bit Bit Complement bit it DEC Rn SUB Rn 1h Decrement register INC Rn ADD Rn 1h Increment register SWAPB Rn ROR Rn 8h Swap bytes within word March 1995 221 254 This is advanced information from SGS THOMSON Details are subject to change without notice 15 System Programming ST10R165 15 2 MULTIPLICATION AND DIVISION Multiplication and division of words and double words is provided through multiple cycle instruc tions implementing a Booth algorithm Each in struction implicitly uses the 32 bit register MD MDL lower 16 bits MDH upper 16 bits The MDRIU flag
104. MC O1958 193 254 10 High Speed Synchronous Serial Interface ST10R165 10 5 SSC INTERRUPT CONTROL Three bit addressable interrupt control registers are provided for serial channel SSC Register SS CTIC controls the transmit interrupt SSCRIC con trols the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each in terrupt source also has its own dedicated interrupt vector SCTINT is the transmit interrupt vector SCRINT is the receive interrupt vector and SCEINT is the error interrupt vector SSCTIC FF72h B9h SFR 15 14 18 12 11 10 9 8 Se SES v ORO ee ee REB fxpe T EM SSCRIC FF74h BAh 15 14 13 12 SSCEIC FF76h BBh 15 14 13 12 FeWES XP wb I 8 6 The cause of an error interrupt request receive phase baudrate transmit error can be identified by the error status flags in control register SSC CON Note In contrary tothe error interrupt request flag SSCEIR the error status flags SSCxE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software Reset Value 00h 7 6 5 4 3 2 1 0 n SSC SSC TIR TIE ILVL GLVL Reset Value 00h 7 6 5 4 3 2 1 0 Note Please refer to the general Interrupt Control Register description for an explanation of the control fields 194 254 ky 3 SON MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ Chapter 11 MICROELECTRONICS T
105. Multiply or Divide Register In Use in register MDC is set whenever either half of this register is written to or when a multiply divide in struction is started It is cleared whenever the MDL register is read Because an interrupt can be acknowledged before the contents of register MD are saved this flag is required to alert interrupt routines which require the use of the multiply di vide hardware so they can preserve register MD This register however only needs to be saved when an interrupt routine requires use of the MD register and a previous task has not saved the cur rent result This flag is easily tested by the Jump on Bit instructions Multiplication or division is simply performed by specifying the correct signed or unsigned ver sion of the multiply or divide instruction The result is then stored in register MD The overflow flag V is setif the result from a multiply or divide instruc tion is greater than 16 bits This flag can be used to determine whether both word halves must be transferred from register MD The high portion of register MD MDH must be moved into the regis ter file or memory first in order to ensure that the MDRIU flag reflects the correct state The following instruction sequence performs an unsigned 16 by 16 bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only required for interrupted multiply
106. OF INTERRUPT AND PEC SERVICE REQUESTS Cont d Software controlled Interrupt Classes Example Interpretation PEC service on up to 8 channels Interrupt Class 1 Interrupt Class 2 Interrupt Class 3 EF E ps ia p E pu T NF LL E esee 4 4 SAVING THE STATUS DURING INTERRUPT SERVICE Before an interrupt request that has been arbitrat ed is actually serviced the status of the current task is automatically saved on the system stack The CPU status PSW is saved along with the lo cation where the execution of the interrupted task is to be resumed after returning from the service routine This return location is specified through the Instruction Pointer IP and in case of a seg mented memory model the Code Segment Point er CSP Bit SGTDIS in register SYSCON con trols how the return location is stored The system stack receives the PSW first followed by the IP unsegmented or followed by CSP and then IP segmented mode This optimizes the us 72 254 8 sources on 2 levels 10 sources on 3 levels 6 sources on 2 levels age of the system stack if segmentation is disa bled The CPU priority field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced so the CPU now executes on the new level If a multiplication or division was in progress at the time the interrupt request was acknowl edged bit MULIP in register PSW is set to 1 In this case the
107. ON YA MICROELECTRONICS SFR Reset Value 0000h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so S0 S0 rw rw rw rw rw rw rw rw modes receive buffer overrun error detection can be selected through bit SOOEN When enabled the overrun error status flag SOOE and the error interrupt request flag SOEIR will be set when the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive buffer is overwritten The Loop Back option selected by bit SOLB al lows to simultaneously receive the data currently being transmitted This may be used to test serial communication routines at an early stage without having to provide an external network In loop back mode the alternate input output functions of the Port 3 pins are not necessary Note Serial data transmission or reception is only possible when the Baud Rate Generator Run Bit SOR is set to 1 Otherwise the se rial interface is idle Do not program the mode control field SOM in register SOCON to one of the reserved combinations to avoid unpredictable behav iour of the serial interface 171 254 9 Asynchronous Synchronous Serial Interface ST10R165 9 1 ASYNCHRONOUS OPERATION Asynchronous mode supports full duplex commu rate Data is transmitted on pin TXDO P3 10 and nication where both transmitter and receiver use received on pin RXDO P3 11 These signals are the same data frame format an
108. P1H 3 P1H 2 P1H 1 P1H 0 P1L 7 P1L 6 P1L 5 P1L 4 P1L 3 P1L 2 P1L 1 P1L 0 General Purpose Input Out put When an external bus mode is enabled the direc tion of the port pin and the loading of data into the port output latch are controlled by the bus control ler hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Out put via amultiplexer The alternate data is the 16 bit intrasegment address While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredict able results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active 8 16 bit Demux Bus 92 254 Ep SGS THOMSON l MICROELECTRONICS PORT 1 Cont d The figure below shows the structure of a PORT1 pin Figure 5 6 Block Diagram of a PORT1 Pin Write DP1H y DP1L y Direction Latch Read DP1H y DP1Ly Write PTH y P1L y I n t e r n qa Port Output Latch Read PIH y P1L y Alternate Function Enable Alternate Data Output ky 3 k SON MICROELECTRONICS 5 Parallel Ports ST10R165 Output Buffer Input Latch MCBD2232 93 254 5 Parallel Ports ST10R165 5 3 PORT 2 In the ST10R165 Port 2 is an 8 bit port If Port 2 is 5 3 1 Alternate Functions of Port 2 used for general purpose IO the direc
109. P1L 6 A6 P3 4 T3EUD ST10R165 P1L 5 A5 P3 5 T4IN P1L 4 A4 P3 6 T3IN P1L 3 A3 P3 7 T2IN P1L 2 A2 P3 8 MRST P1L 1 A1 P3 9 MTSR P1L 0 A0 P3 10 TxDO POH 7 AD15 P3 11 RxDO POH 6 AD14 P3 12 BHE WRH POH 5 AD13 P3 13 SCLK POH 4 AD12 P3 15 CLKOUT POH 3 AD11 P4 0 A16 POH 2 AD10 P4 1 A17 POH 1 AD9 P4 2 A18 POH 0 AD8 P5 13 T5in P5 14 T4EUD P5 15 T2EUD ONoOoaRWD AR A A AB A ol A O A POL O ADO H POL 1 AD1 O POL 2 AD2 O POL 3 AD3 O POL 4 ADA C POL 5 AD5 O POL 6 AD6 C POL 7 AD7 O VR02052A 252 254 SGS THOMSON YA MICROELECTRONICS 18 Device Specification ST10R165 Figure 18 2 Pin Description of the ST10R165 PQFP100 Package P5 11 TSEUD P5 12 T6IN P5 13 TSIN P5 14 T4EUD P5 15 T2EUD Vss XTAL1 XTAL2 Vbo P3 0 P3 1 T6OUT P3 2 CAPIN P3 3 T3OUT P3 4 T3EUD P3 5 TAIN P3 6 T3IN P3 7 T2IN P3 8 MRST P3 9 MTSR P3 10 TxDO P3 11 RxDO P3 12 BHE WRH P3 13 SCLK P3 15 CLKOUT P4 0 A16 P4 1 A17 P4 2 A18 P4 3 A19 Vas Vop tA P4 4 A20 Cj P4 5 A21 Cj P4 6 422 Cj P4 7 A23 Cj ky 3 SON MICROELECTRONICS BREQ HLDA HOLD CS4 1 P2 8 EXOIN 1 P amp 7 3 P6 6 3 P6 5 CS2 CST CSO 1 P6 4 Ly P6 5 CS3 m P6 2 L3 P6 1 L3 P6 0 ST10R165 un a d ca w0 e 20L 0 ADO rj POL 1 AD1 gt 0L 2 AD2 r4 gt 0L 3 AD3 rj 0L 4 AD4 rj gt 0L 5 AD5 r4 0L 6 AD6 Cy 20L7 AD7 c Vop Vss P1H 7 A15 P1H 6 A14 P1H 5 A13 P1H 4 A12 P1H 3 A11 P1H 2 A10 Vss Vpp
110. Pn changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode as shown in the following ex ample IS MOV DPPO 4 select data page 4 via DPPO Ina must not be an instruction using DPPO In MOV DPP0 0000h R1 move contents of R1 to address location 01 0000h in data page 4 supposed segmentation is enabled a Explicit Stack Pointer Updating None of the RET RETI RETS RETP or POP in structions is capable of correctly using a new SP register value whichis to be updated by an imme diately preceding instruction Thus in order to use the new SP register value without erroneously performed stack accesses at least one instruction must be inserted between an explicitly SP writing and any subsequent of the just mentioned implic itly SP using instructions as shown in the follow ing example Ij MOV SP 0FA40h Select a new top of stack Ine must not be an instruction popping operands from the system stack ENT POP RO pop word value from new top of stack into RO SGS THOMSON YA MICROELECTRONICS INSTRUCTION PIPELINING Contd a External Memory Access Sequences The effect described here will only become notice able when watching the external memory access sequences on the external bus eg by means of a Logic Analyzer Different pipeline stages can si multaneously put a request on the External Bus Controller EBC The sequence of instruc
111. Q output The external bus arbitration is enabled by setting bit HLDEN in register PSW to 1 This bit may be cleared during the execution of program sequenc es where the external resources are required but cannot be shared with other bus masters In this case the ST10R165 will not answer to HOLD re quests from other external masters The pins HOLD HLDA and BREQ keep their alter nate function bus arbitration even after the arbi tration mechanism has been switched off by clear ing HLDEN All three pins are used for bus arbitration after bit HLDEN was set once 135 254 7 External Bus Interface ST10R165 EXTERNAL BUS ARBITRATION Cont d Entering the Hold State Access to the ST10R165 s external bus is re quested by driving its HOLD input low After syn chronizing this signal the ST10R165 will complete a current external bus cycle if any is active re lease the external bus and grant access to it by driving the HLDA output low During hold state the ST10R165 treats the external bus interface as fol lows e Address and data bus es float to tri state e ALE is pulled low by an internal pulldown device e Command lines are pulled high by internal pullup devices RD WR WRL BHE WRH e CSx outputs are pulled high push pull mode or float to tri state open drain mode Should the ST10R165 require access to its exter nal bus during hold mode it activates its bus re quest output BREQ to notify t
112. ROELECTRONICS 5 Parallel Ports ST10R165 PORT 4 Cont d Figure 5 13 Block Diagram of a Port 4 Pin Direction Lateh Alternate Function Enable Alternate I n i e r n a Port Output Latch Buffer a co MCB02075 104 254 SGS THOMSON AJ Viexors SerROMYGS 5 Parallel Ports ST10R165 5 6 PORT 5 This 6 bit input port can only read data There is no output latch and no direction register Data written to P5 will be lost P5 FFA2h D1h SFR Reset Value XX h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r g P5 y Port data register P5 bit y Read only 5 6 1 Alternate Functions of Port 5 Each line of Port 5 serves as external timer control line for GPT1 and GPT2 The table below summarizes the alternate functions of Port 5 Alternate Function Timer 6 external Up Down Control Input Timer 5 external Up Down Control Input Timer 6 Count Input Timer 5 Count Input Timer 4 external Up Down Control Input Timer 2 external Up Down Control Input sy SGS THOMSON ees IF MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 5 Cont d Figure 5 14 Port 5 IO and Alternate Functions Alternate Function General Purpose Input Port 5 pins have a special port structure see figure below because it is an input only port Figure 5 15 Block Diagram of a Port 5 Pin Read Port P5 y Read uh Buffer 0723 O 5 MCB02228
113. RWDCx MTTCx BTYPx Memory Cycle Time Control Number of memory cycle time wait states 0000 15 waitstates Number 15 lt MCTC 1111 No waitstates Read Write Delay Control for BUSCONx 0 With read write delay activate command 1 TCL after falling edge of ALE 1 No read write delay activate command with falling edge of ALE Memory Tristate Time Control 0 1 waitstate 1 No waitstate External Bus Configuration 0 0 8 bit Demultiplexed Bus 0 1 8 bit Multiplexed Bus 1 0 16 bit Demultiplexed Bus 1 1 16 bit Multiplexed Bus Note For BUSCONO BTYP is defined via PORTO during reset ALE Lengthening Control 0 Normal ALE signal 1 Lengthened ALE signal Bus Active Control 0 External bus disabled 1 External bus enabled within the respective address window see ADDRSEL READY Input Enable 0 External bus cycle is controlled by bit field MCTC only 1 External bus cycle is controlled by the READY input signal Read Chip Select Enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command Write Chip Select Enable 0 The CS signal is independent of the write command WR WRL WRH 1 The CS signal is generated for the duration of the write command 131 254 SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 CONTROLLING THE EXTERNAL BU
114. Reserved Do not use this combination 111b 1024 00 FDFEh 00 F600h Note No circular stack 24 254 SGS THOMSON YA MICROELECTRONICS INTERNAL RAM AND SFR AREA Cont d General Purpose Registers The General Purpose Registers GPRs use a block of 16 consecutive words within the internal RAM The Context Pointer CP register deter mines the base address of the currently active register bank This register bank may consist of up to 16 word GPRs RO R1 R15 and or of up to 16 byte GPRs RLO RHO RL7 RH7 The six teen byte GPRs are mapped onto the first eight word GPRs see table below In contrast to the system stack a register bank grows from lower towards higher address loca tions and occupies a maximum space of 32 bytes The GPRs are accessed via short 2 4 or 8 bit addressing modes using the Context Pointer CP register as base address independent of the cur rent DPP register contents Additionally each bit 2 Memory Organization ST10R165 in the currently active register bank can be ac cessed individually The ST10R165 supports fast register bank con text switching Multiple register banks can physi cally exist within the internal RAM at the same time Only the register bank selected by the Con text Pointer register CP is active at a given time however Selecting a new active register bank is simply done by updating the CP register A partic ular Switch Context SCXT inst
115. Rs are marked with the letter E in column Physical Address LEN Aa CR External Interrupt 0 Control Register 0000h External Interrupt 1 Control Register 0000h P 8 bits not directly writeable P1L Direction Control Register 00h 238 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 SPECIAL FUNCTION REGISTERS ORDERED BY NAME Cont d Physical 8 Bit Description Reset Address Address p Value pem Brom em PiMDvecion Conver Reaser fom fore e From rw Pot2Direston Convoi Regs ooon es ef Eroon Ean FetsDresonCowdFegse ooon eer rem om CPU Data Page Pointer t Regier osiy oom ees Feon oon GPU Data Page Pointer Regier Go srs oo ores Fe06n um CPU Data Page Pointer Register 10 bis oo wow Fe0cn om CPU Muti Die Reiter Hih Word o000n_ omes errem sm Constant vate re Regier reas ony FFF pow e Eron em Poro Hian Register Uppernal of PORTO om pw rom em Pon High Register Uppernal of PORTH om m2 erm em Fereme em p rem em Fetreme e p oferon rm Pont negeren o ps6 Fram om Pons Register eadoniy oon ps ef Frccn rm Pone regseress o 239 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 SPECIAL FUNCTION REGISTERS ORDERED BY NAME Cont d LAN 3 ie per ooa o N FFion 88h CPU Program Status Word sd CPU Program Status Word sd Program Status Word
116. S CONTROLLER Cont d ADDRSEL1 FE18h 0Ch SFR Reset Value 0000h 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 rw b ADDRSEL2 FE1Ah ODh SFR Reset Value 0000h 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw ADDRSEL3 FE1Ch OEh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw ADDRSEL4 FE1Eh OFh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See table below Range Start Address Defines the upper bits of the start address A23 of the respective address area See table be low Note There is no register ADDRSELO as register BUSCONO controls all external accesses outside the four address windows of BUSCONA BUSCON 1 within the complete address space 132 254 S7 SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 CONTROLLING THE EXTERNAL BUS CONTROLLER Cont d Definition of Address Areas parameters in register BUSCONx are used to con The four register pairs BUSCON4 AD trol external accesses The range start address of DRSEL4 BUSCON1 ADDRSEL1 allow to define Such a window defines the upper address bits 4 separate address areas within the address which are not used within the address window of space of the ST10R165 Within each of these ad the specified size see table below For a given dress areas external accesses can be controlled wind
117. SCONO After initializ ing the active registers they are selected and evaluated automatically by interpreting the physi cal address No additional switching or selecting is necessary during run time except when more than the four address windows plus the default is to be used Switching from demultiplexed to multiplexed bus mode represents a special case The bus cy cle is started by activating ALE and driving the ad dress to Port 4 and PORT1 as usual if another BUSCON register selects a demultiplexed bus However in the multiplexed bus modes the ad dress is also required on PORTO In this special case the address on PORTO is delayed by one CPU clock cycle which delays the complete mul tiplexed bus cycle and extends the corresponding ALE signal see figure below This extra time is required to allow the previously selected device via demultiplexed bus to release the data bus which would be available in a demul tiplexed bus cycle 117 254 7 External Bus Interface ST10R165 EXTERNAL BUS MODES Cont d Figure 7 4 Switching from demultiplexed to Multiplexed Bus Mode Demultiplexed Multiplexed Bus Cycle idle State l Bus Cycle Address P1 Segment P4 NE Address 73 E NS EET y ALE IL l p ias BUS PO sh a esce l am X QDoto lnsir gt L _ Qata nsir l l l l l I EN l l N f l l l l l l l l ee aise ay N E ee a a E
118. SOCON An even parity bit will be set if the modulo 2 sum of the 8 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 9 bit data and wake up mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong par Figure 9 3 Asynchronous 8 bit Data Frames ity bitis received The parity bit itself will be stored in bit SORBUF 8 In wake up mode received frames are only trans ferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred This feature may be used to control communica tion in multi processor system When the master processor wants to transmit a block of data to one of several slaves itfirst sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte and a 0 for a data byte so no slave will be in terrupted by a data byte An address byte will in terrupt all slaves operating in 8 bit data wake up bit mode so each slave can examine the 8 LSBs of the received character the address The addressed slave will switch to 9 bit data mode eg by clearing bit SOM 0 which enables it to also re ceive the data bytes that will be coming having the wake up bit cleared T
119. SORIR if one or more of the fol lowing conditions are met e ftheframing error detection enable bit SOFEN is set and any of the expected stop bits is not high the framing error flag SOFE is set indicat ing that the error interrupt request is due to a framing error Asynchronous mode only If the parity error detection enable bit SOPEN is set in the modes where a parity bit is received and the parity check on the received data bits proves false the parity error flag SOPE is set indicating that the error interrupt request is due to a parity error Asynchronous mode only e fthe overrun error detection enable bit SOOEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete the overrun error flag SOOE is set indicating that the error interrupt request is due to an overrun error Asynchronous and synchronous mode SGS THOMSON YA MICROELECTRONICS 9 4 ASCO BAUD RATE GENERATION The serial channel ASCO has its own dedicated 13 bit baud rate generator with 13 bit reload capa bility allowing baud rate generation independent from the timers The baud rate generator is clocked with the CPU clock divided by 2 10 MHz 20 MHz CPU clock The timer is counting downwards and can be start ed or stopped through the Baud Rate Generator Run Bit SOR in register SOCON Each underflow of the timer provides one clock pulse to the s
120. ST10R165 16 BIT MCU USER MANUAL MARCH 1995 INTRODUCTION The rapidly growing area of embedded control applications is representing one of the most time critical operating environments for today s microcontrollers Complex control algorithms have to be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined maximum response time Embedded control applications therefore require microcontrollers which m Offer a high level of system integration m eliminate the need for additional peripheral devices and the associated software overhead m provide system security and fail safe mechanisms With the increasing complexity of embedded control applications a significant increase in CPU performance and peripheral functionality over conventional 8 bit controllers is required from microcontrollers for high end embedded control systems The ST10 family of 16 bit microcontrollers achieves this high performance goal The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli interrupts Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent This also minimizes the need for communication via the external bus interface The high flexibility of this architecture allows to serve the diverse and varying needs of di
121. T10R165 cessed by the programmer The IP can however be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch op erations Reset Value 0000h 7 6 5 4 3 2 1 0 Specifies the intra segment offset from where the current instruction is to be fetched IP refers to the current segment lt SEGNR gt The Code Segment Pointer CSP This non bit addressable register selects the code segment being used at run time to access instruc tions The lower 8 bits of register CSP select one of up to 256 segments of 64 Kbytes each while the upper 8 bits are reserved for future use Code memory addresses are generated by direct ly extending the 16 bit contents of the IP register by the contents of the CSP register as shown in the figure below In case of the segmented memory mode the se lected number of segment address bits 7 0 3 0 or 1 0 of register CSP is output on the segment address pins A23 A19 A17 A16 of Port 4 for all CSP FEO8h 04h SFR 15 14 11 1 Segment Number Specifies the code segment from where the current instruction is to be fetched SEGNR is ignored external code accesses For non segmented memory mode or Single Chip Mode the content of this register is not significant because all code ac cesses are automatically restricted to segment 0 Note The CSP register can only be read but no
122. THOMSON YA MICROELECTRONICS 69 254 4 Interrupt and Trap Functions ST10R165 OPERATION OF THE PEC CHANNELS Cont d Continuous transfers are selected by the value FFhin bit field COUNT In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again When COUNT is decremented from 01h to 00h af ter a transfer the request flag is not cleared which generates another request from the same source When COUNT already contains the value 00h the respective PEC channel remains idle and the as sociated interrupt service routine is activated in stead This allows to choose if alevel 15 or 14 re quest is to be serviced by the PEC or by the inter rupt service routine Note PEC transfers are only executed if their pri ority level is higher than the CPU level ie only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are ena bled and programmed for PEC service should use different channels Otherwise only one transfer will be performed for all si multaneous requests When COUNT is dec remented to 00h and the CPU is to be interrupted an incorrect interrupt vector will be generated The source and destination pointers specifiy the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the 8 PEC channels These pointers do not reside in specific SFRs but are mapp
123. TRONICS 55 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d The Multiply Divide High Register MDH This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the high order 16 bits of the 32 bit re sult For long divisions the MDH register must be loaded with the high order 16 bits of the 32 bit div idend before the division is started After any divi sion register MDH represents the 16 bit remain der Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 When a multiplication or division is interrupted be fore its completion and when a new multiply or di vide operation is to be performed within the inter MDH FEOCh 06h SFR 15 14 18 12 11 10 9 8 rupt service routine register MDH must be saved along with registers MDL and MDC to avoid erro neous results A detailed description of how to use the MDH reg ister for programming multiply and divide algo rithms can be found in chapter System Program ming The Multiply Divide Low Register MDL This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication thi
124. This manual also provides tables ordering the instruc Arithmetic Instructions Addition of two words or bytes Addition with Carry of two words or bytes Subtraction of two words or bytes Subtraction with Carry of two words or bytes 16 16 bit signed or unsigned multiplication 16 16 bit signed or unsigned division 32 16 bit signed or unsigned division 1 s complement of a word or byte 2 s complement negation of a word or byte Logical Instructions Bitwise ANDing of two words or bytes Bitwise ORing of two words or bytes Bitwise XORing of two words or bytes Compare and Loop Control Instructions Comparison of two words or bytes Comparison of two words with post increment by either 1 or 2 Comparison of two words with post decrement by either 1 or 2 March 1995 tions according to various criteria to allow quick references Summary of Instruction Classes Grouping the various instruction into classes aids in identifying similar instructions eg SHR ROR and variations of certain instructions eg ADD ADDB This provides an easy access to the pos sibilities and the power of the instructions of the ST10R165 Note The used mnemonics refer to the detailled description ADD ADDB ADDC ADDCB SUB SUBB SUBC SUBCB MUL MULU DIV DIVU DIVL DIVLU CPL CPLB NEG NEGB AND ANDB OR ORB XOR XORB CMP CMPB CMPI1 CMPI2 CMPD1 CMPD2 247 254 This is advanc
125. Timer Counter If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer TSOTL 4 16 bit auxiliary timer The count directions of the two concatenated tim ers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer gated timer or counter mode in this case Figure 8 7 Concatenation of Core Timer T3 and an Auxiliary Timer Tyl i e Spr on ee t 1 TyR Up Down Edge Select Interrupt m Request fer TyOUT TyOE Int t X eo Auxiliary Timer Tx erue MCB02034 TxR Txl TSOUT P3 3 X 2 4 y 3 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL SGS THOMSON YA MICROELECTRONICS 149 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 100b In reload mode the core timer T3 is reloaded with the contents of an auxil iary timer register triggered by one of two different signals The trigger signal is selected the same way as the clock source for counter mode see ta ble above ie a transition of the auxiliary timer s input or the output toggle l
126. WRL pin BHE acts as WRH CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO Internal ROM Enable Set according to pin EA during reset 0 Internal ROM disabled accesses to the ROM area use the external bus 1 Internal ROM enabled This bit is not relevant on the ST10R165 since it does not include internal ROM It should be kept at 0 SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored Internal ROM mapping This bit is not relevant on the ST10R165 since it does not include internal ROM It should be kept at 0 STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction Bit SGTDIS controls the correct stack operation push pop of CSP or not during traps and inter rupts Bits marked with must be kept at 0 129 254 SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 CONTROLLING THE EXTERNAL BUS CONTROLLER Cont d The layout of the five BUSCON registers is i
127. YTDIS 1 It may be disabled if byte access to 16 bit memo ry is not required and the BHE signal is not used Bus Mode Transfer Rate Speed factor for System Requirements Free IO Lines byte word dword access 8 bit Multiplexed Very low 1 5 3 6 Low 8 bit latch byte bus P1H P1L 8 bi 8 bit Demultipl Low 1 2 4 Very low no latch byte bus 16 bit Multiplexed High 1 5 1 5 3 High 16 bit latch word bus P1H P1L 16 bit Demultipl Very high 1 1 2 SGS THOMSON YA MICROELECTRONICS Low no latch word bus 119 254 7 External Bus Interface ST10R165 EXTERNAL BUS MODES Cont d Segment Address Generation During external accesses the EBC generates a programmable number of address lines on Port 4 which extend the 16 bit address output on PORTO or PORT1 and so increase the accessible address space The number of segment address lines is selected during reset and coded in bit field SALSEL in register RPOH see table below Note The total accessible address space may be increased by accessing several banks which are distinguished by individual chip select signals SALSEL Segment Address Lines Directly accessible Address Space Two A17 A16 256 KByte Default without pull downs Eight A23 A16 16 MByte Maximum foo 8s Four A19 A16 1 MByte or memory banks without requiring an external de coder The number of CS lines is selected during reset and coded in bit field CSSEL in register
128. a a dade eee LS 231 15 8 Peripheral Control and Interface lille 231 15 9 Floating Point Support 0 0 0 0 06 ce eran 232 15 10 Trap Interrupt Entry and Exit 0 0 ce eh 232 15 11 Unseparable Instruction Sequences 0 0 cee tet ee eee 232 15 12 Overriding the DPP Addressing Mechanism 00 000 c cece eee eae 233 16 Register Sel corser diovan arrin eG RIREY ee ee wie reese wes 235 16 1 CPU General Purpose Registers GPRS 0 0000 cece eee 236 16 2 Special Function Registers ordered by Name 0 00 e eee eee nee 238 16 3 Registers ordered by Address liliis 242 16 4 Special Notes slsssssselseleeeeee ls han 246 17 Instruction Set Summary L Ll 247 18 Device Specification 22 10 20 99 annan weed xxu eee vs 251 s SGS THOMSON 1L 1 1 779 YA MICROELECTRONICS Table of Contents Notes 8 254 yz 56 THOMSON n THOMSON wr SGS THOMSON STi0R165 User Manual YZ The architecture of the ST10R165 combines the advantages of both RISC and CISC processors in a very well balanced way The sum ofthe features which are combined result in a high performance microcontroller which is the right choice not only for today s applications but also for future engi neering challenges The ST10R165 not only inte Figure 1 1 ST10R165 Functional Block Diagram MICROELECTRONICS Chapter 1 ARCHITECTURAL OVERVIEW grates a powerful CPU cor
129. a new value provided for register bank switching SCXT 248 254 S7 SGS THOMSON YA MICROELECTRONICS 17 Instruction Set Summary ST10R165 Jump Instructions Conditional jumping to an either absolutely indirectly or relatively addressed target instruction within the current code segment Unconditional jumping to an absolutely addressed target instruction within any code segment Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit with a post inversion of the tested bit in case of jump taken semaphore support Call Instructions Conditional calling of an either absolutely or indirectly addressed subroutine within the current code segment Unconditional calling of a relatively addressed subroutine within the current code segment Unconditional calling of an absolutely addressed subroutine within any code segment Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack Unconditional branching to the interrupt or trap vector jump table in code segment 0 Return Instructions Returning from a subroutine within the current code segment Returning from a subroutine within any code s
130. a page base address together with the 14 bit page offset forms the physical 24 20 18 bit address In case of non segmented memory mode only the two least significant bits of the implicitly selected DPP register are used to generate the physical address Thus extreme care should be taken when changing the content of a DPP register if a Figure 3 6 Addressing via the Data Page Pointers Data Pages DPP Registers i Pra A 4 ge A non segmented memory model is selected be cause otherwise unexpected results could occur In case of the segmented memory mode the se lected number of segment address bits 9 2 5 2 or 3 2 of the respective DPP register is output on the segment address pins A23 A19 A17 A16 of Port 4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a new DPP value is not yet usable for the op erand address calculation of the instruction immediately following the instruction updat ing the DPP register 16 bit Data Address 15 14 DPP3 1 1 DPP2 1 0 DPP1 0 1 DPP0 0 0 14 bit Intra Page Address concatenated with content of DPPx After reset or with segmentation disabled the DPP registers select data pages 3 0 All of the internal memory is accessible in these cases 50 254 SGS THOMSON YA MICROELECTRONICS CPU SPECIAL FUNCTION REGISTERS
131. able the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined by the master or slave operation of the individual device Note The shift direction shown in the figure ap plies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration select one device for master operation SSC MS 1 all others must be programmed for slave operation SSCMS 0 Initialization includes the operating mode of the device s SSC and also the function of the respective port lines see Port Control Device 2 MCA01963 SGS THOMSON YA MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165 FULL DUPLEX OPERATION Cont d The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line ie enables the driver of its MRST pin All the other slaves have to program there MRST pins to input So only one slave can put its data onto the master s receive line Only receiving of data from the master is pos sible The master selects the slave device from which it expects data either by separate select lines or by sending a special comma
132. ack When initializating the stack pointer SP and the context pointer CP it must be ensured that these registers are initialized before any GPR or stack operation is performed This includes interrupt processing which is disabled upon completion of the internal reset and should remain disabled until the SP is initialized In addition the stack overflow STKOV and the stack underflow STKUN registers should be ini tialized After reset the CP SP and STKUN reg isters all contain the same reset value 00 FCOOh while the STKOV register contains 00 FAOOh With the default reset initialization 256 words of system stack are available where the system stack selected by the SP grows downwards from 00 FBFEh while the register bank selected by the CP grows upwards from 00 FCOOh Based on the application the user may wish to in itialize portions of the internal memory before nor mal program operation Once the register bank has been selected by programming the CP regis ter the desired portions of the internal memory can easily be initialized via indirect addressing At the end ofthe initialization the interrupt system may be globally enabled by setting bit IEN in reg ister PSW Care must be taken not to enable the interrupt system before the initialization is com plete The software initialization routine should be termi nated with the EINIT instruction This instruction has been implemented as a protected instruction
133. action an on chip Interrupt Control ler compares all pending peripheral service re quests against each other and prioritizes one of them If the priority of the current CPU operation is lower than the priority of the selected peripheral request an interrupt will occur Basically there are two types of interrupt process ing e Standard interrupt processing forces the CPU to save the current program status and the return address on the stack before branching to the inter rupt vector jump table e PEC interrupt processing steals just one ma chine cycle from the current CPU activity to per form a single data transfer via the on chip Periph eral Event Controller PEC System errors detected during program execution hardware traps or an external non maskable in terrupt are also processed as standard interrupts with a very high priority In contrast to other on chip peripherals there is a closer conjunction between the watchdog timer and the CPU If enabled the watchdog timer ex pects to be serviced by the CPU within a program mable period of time otherwise it will reset the chip Thus the watchdog timer is able to prevent the CPU from going totally astray when executing erroneous code After reset the watchdog timer starts counting automatically but it can be disa bled via software if desired 32 254 Beside its normal operation there are the following particular CPU states e Reset state Any reset hardware s
134. al registers by executing the SCXT switch con text instruction This mechanism does not provide a method to recursively call a subroutine Saving and Restoring of Registers To provide local registers the contents of the registers which are required for use by the subroutine can be pushed onto the stack and the previous values be popped before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive procedures This method however requires two machine cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Use of the System Stack for Local Registers It is possible to use the SP and CP to set up local subroutine register frames This allows subrou tines to dynamically allocate local variables as needed within two machine cycles A local frame is allocated by simply subtracting the number of required local registers from the SP and then moving the value of the new SP to the CP 229 254 15 System Programming ST10R165 PROCEDURE CALL ENTRY AND EXIT Cont d This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP see example below Each local register is then accessed as if it was a normal register Upon exit from the subrou t
135. and T4 are pro grammed to timer mode or gated timer mode their operation is the same as described for the core 8 General Purpose Timer Units ST10R165 timer T3 The descriptions figures and tables ap ply accordingly with one exception e There is no output toggle latch and no alternate output pin for T2 and T4 Timers T2 and TA in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to 001b In counter mode timers T2 and T4 can be clocked either by a transition at the respective external inputpin TxIN or by atran sition of timer T3 s output toggle latch T3OTL Figure 8 6 Block Diagram of an Auxiliary Timer in Counter Mode Auxiliary Timer Tx Timer Tx xk gt ed SGS THOMSON YA MICROELECTRONICS X224 MCBO2221 147 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d The event causing an increment or decrement of a timer can be a positive a negative or both a pos itive and a negative transition at either the respec tive input pin or at the toggle latch T3OTL Bit field Txl in the respective control register Tx CON selects the triggering transition see table below For counter operation pin TxIN must be config ured as input ie the respective direction control bit must be 0 The maximum input frequency which is allowed in counter mode is fopyg 1 25 MHz fpu 20 MHz To ensure th
136. are controlled via register SYSCON The properties of a bus cycle like chip select mode us age of READY length of ALE external bus mode read write delay and waitstates are controlled via registers BUSCONA BUSCONO Four of these registers BUSCON4 BUSCON1 have an ad dress select register ADDRSEL4 ADDRSEL1 associated with them which allows to specify up to four address areas and the individual bus char acteristics within these areas All accesses that are not covered by these four areas are then con trolled via BUSCONO This allows to use memory components or peripherals with different interfac es within the same system while optimizing ac cesses to each of them SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 CONTROLLING THE EXTERNAL BUS CONTROLLER Cont d SYSCON FF12h 89h SFR Reset Value OXXOh 15 14 13 11 10 0 12 9 8 7 6 5 4 3 2 1 SGT BYT CLK WR VISI XPER rw rw rw rw rw rw XPER SHARE XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disbled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins WRCFG Write Configuration Control Set according to pin POH O during reset 0 Pins WR and BHE retain their normal function 1 Pin WR acts as
137. are used as exter nal address data bus hold the address data which was output during the last external memory ac cess before entry into Idle mode under the follow ing conditions POH outputs the high byte of the last address if a multiplexed bus mode with 8 bit data bus is used otherwise POH is floating POL is always floating in Idle mode 218 254 PORT outputs the lower 16 bits of the last ad dress if a demultiplexed bus mode is used other wise the output pins of PORT1 represent the port latch data Port 4 outputs the segment address for the last ac cess on those pins that were selected during re set otherwise the output pins of Port 4 represent the port latch data During Power Down mode the oscillator and the clocks to the CPU and to the peripherals are turned off Like in Idle mode all port pins which are configured as general purpose output pins output the last data value which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is deter mined by the last action of the peripheral before the clocks were switched off SGS THOMSON YA MICROELECTRONICS 14 Power Reduction Modes ST10R165 STATUS OF OUTPUT PINS DURING IDLE AND POWER DOWN MODE Cont d The table below summarizes the state of all ST10R165 output pins during Idle and Power Down mode ST10R165 Output Pin s Idle Mode Power Down Mode A8 2 Port La
138. at a transition of the count input signal which is applied to TxIN is correctly recognized its level should be held for at least 8 fopy cycles before it changes GPT1 Auxiliary Timer Counter Mode Input Edge Selection Positive transition rising edge on TxIN Negative transition falling edge on TxIN Any transition rising or falling edge on TxIN Positive transition rising edge of output toggle latch T3OTL Negative transition falling edge of output toggle latch T3OTL Any transition rising or falling edge of output toggle latch T3OTL Note Only state transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 148 254 SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT1 Cont d Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary tim er Depending on which transition of T3OTL is se lected to clock the auxiliary timer this concatena tion forms a 32 bit or a 33 bit timer counter e 32 bit Timer Counter If both a positive and a negative transition of T3OTL is used to clock the auxiliary timer this timer is clocked on every over flow underflow of the core timer T3 Thus the two timers form a 32 bit timer 8 General Purpose Timer Units ST10R165 e 33 bit
139. atch T3OTL may trigger the reload Note When programmed for reload mode the re spective auxiliary timer T2 or T4 stops in dependent of its run flag T2R or TAR Upon a trigger signal T3 is loaded with the con tents of the respective timer register T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a T3OTL transition is selected for the trigger signal also the interrupt request flag Figure 8 8 GPT1 Auxiliary Timer in Reload Mode Source Edge eree 3 jj TxIN P3 7 P3 5 Core Timer T3 Up Down x 2 4 TSIR will be set upon a trigger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 The reload mode triggered by T3OTL can be used in a number of different configurations Depending on the selected active transition the following func tions can be performed e f both a positive and a negative transition of TSOTL is selected to trigger a reload the core tim er will be reloaded with the contents of the auxilia ry timer each time it overflows or underflows This is the standard reload mode reload on overflow underflow e f either a positive or a negative transition of TSOTL is selected to trigger a reload the core tim er will be reloaded with the contents of the auxilia ry timer on every second overflow or underflow Reload Register Tx Interrupt Request Interrupt Request T30UT d P3 3
140. ate as long as no demulti plexed bus is selected via one of the BUSCON registers In demultiplexed bus modes PORT1 drives the 16 bit intra segment address while PORTO or POL according to the selected data bus width drives the output data For a 16 bit data bus BHE is automatically ena bled for an 8 bit data bus BHE is disabled via bit BYTDIS in register SYSCON Default 16 bit data bus with multiplexed address es Note ST10R165 being a ROMless device pin EA must be connected to ground external start Chip Select Lines Pins POH 2 and POH 1 CSSEL define the number of active chip select signals during reset This allows to control which pins of Port 6 drive ex ternal CS signals and which are used for general purpose IO The two bits are latched in register RPOH Default All 5 chip selectlines active CS4 CS0 Note The selected number of CS signals cannot be changed via software after reset Segment Address Lines Pins POH 4 and POH 3 SALSEL define the number of active segment address lines during re set This allows to control which pins of Port 4 ky 3 SON MICROELECTRONICS 13 System Reset ST10R165 drive address lines and which are used for general purpose IO The two bits are latched in register RPOH Depending on the system architecture the required address space is chosen and accessible right from the start so the initialization routine can directly access all locations without prior pro
141. auxiliary timer register and the associated interrupt request flag TxIR will be set Note The direction control bits DP3 7 for T2IN and DP3 5 for T4IN must be set to 0 and the level of the capture trigger signal should be held high or low for at least 8 fce cycles before it changes to ensure correct edge detection Figure 8 10 GPT1 Auxiliary Timer in Capture Mode Edge Selact Capture Regisler Tx TxIN Interrupt P3 7 P3 5 rr Request Input p 13 Interrupt Clock Core Timer T3 T3IR Request Up Down NE TS0TL ero P3 3 x 2 4 T30E MCB02038 152 254 SGS THOMSON YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d 8 1 3 Interrupt Control for GPT1 Timers TxIC will be set This will cause an interrupt to the When a timer overflows from FFFFh to 0000h respective timer interrupt vector T2INT T3INT or when counting up or when it underflows from T4INT or trigger a PEC service if the respective 0000h to FFFFh when counting down its inter interrupt enable bit T2IE T3IE or TA4IE in register rupt request flag T2IR T3IR or T4IR in register TxIC is set There is an interrupt control register for each of the three timers T2IC FF60h BOh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 S g rw rw rw T3IC FF62h Bth SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 T3IR T3IE ILVL GLVL i Zh tibet elds a Vds m
142. be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The upper 256 Byte of the internal RAM 00 FDOOh through 00 FDFFh and the GPRs of the current bank are provided for single bit stor age and thus they are bit addressable System Stack The system stack may be defined within the inter nal RAM The size of the system stack is control led by bitfield STKSZ in register SYSCON see ta ble below For all system stack operations the on chip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only word access es are supported to the system stack A stack overflow STKOV and a stack underflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be used not only for protection against data destruction but also al low to implement a circular stack with hardware supported systemstack flushing and filling except for the 2KByte stack option The technique of implementing this circular stack is described in chapter System Programming lt STKSZ gt Stack Size Words Internal RAM Addresses Words 000b 2 010b OO FBFERh 00 FAOOh Default after Reset 00 FBFEh 00 FB80h 001b O0 FBFEh 00 FBOOh 00 FBFEh 00 FBCOh 100b 00 FBFEh 00 F800h 101b Pe Reserved Do not use this combination 110b
143. bit timers counters for measuring long time periods with high resolution Various reload or capture functions can be select ed to reload timers or capture a timer s contents triggered by an external signal or a selectable transition of toggle latch TXOTL The maximum resolution of the timers in module GPT1 is 400 ns 20 MHz CPU clock With its maximum resolution of 200 ns 20 MHz CPU clock the GPT2 timers provide precise event con trol and time measurement Watchdog Timer The Watchdog Timer represents one of the fail safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time The Watchdog Timer is always enabled after a re set of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed Thus the chip s start up procedure is always monitored The soft ware has to be designed to service the Watchdog Timer before it overflows If due to hardware or software related failures the software fails to do so the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware compo nents to reset The Watchdog Timer is a 16 bit timer clocked with the CPU clock divided either by 2 or by 128 The high byte of the Watchdog Timer register can be set to a prespecified reload value stored in WDTREL in order to allow further variation of the
144. bits to control internal operations Never modify these bits without saving and restoring register MDC SGS THOMSON YA MICROELECTRONICS 57 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d The Constant Zeros Register ZEROS All bits of this bit addressable register are fixed to 0 by hardware This register can be read only Register ZEROS can be used as a register ad dressable constant of all zeros ie for bit manipu lation or mask generation It can be accessed via any instruction which is capable of addressing a SFR ZEROS FF1Ch 8Eh SFR 15 14 13 12 r r r r ONES FF1Eh 8Fh 15 14 13 12 r r r r 11 r SFR 11 r 58 254 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r The Constant Ones Register ONES All bits of this bit addressable register are fixed to 1 by hardware This register can be read only Register ONES can be used as a register ad dressable constant of all ones ie for bit manipula tion or mask generation It can be accessed via any instruction which is capable of addressing an SFR Reset Value 0000h Reset Value FFFFh SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual Y MICROELECTRONICS Chapter 4 INTERRUPT AND TRAP FUNCTIONS The architecture of the ST10R165 supports sever al mechanisms for fast and flexible response to service reques
145. by ST10R165 s integrated periph erals or the External Bus Controller Using port as General Purpose I O lines All port lines are bit addressable and all input out put lines are individually bit wise programmable as inputs or outputs via direction registers except Port 5 The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of three MICROELECTRONICS Chapter 5 PARALLEL PORTS IO ports 2 3 6 can be configured pin by pin for push pull operation or open drain operation via control registers The logic level of a pin is clocked into the input latch once per state time regardless whether the port is configured for input or output A write operation to a port pin configured as an in put causes the value to be written into the port out put latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Writing to a pin configured as an output DPx y2 1 causes the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and writes it backto the output latch thus also modify ing the level at the pin Figure 5 1 SFRs and Pins associated with the Parallel Ports
146. cessors or external peripher als The SSC supports full duplex and half duplex synchronous communication up to 5 MBaud 20 MHz CPU clock The serial clock signal can be generated by the SSC itself master mode or be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows com munication with SPl compatible devices Trans mission and reception of data is double buffered A 16 bit baud rate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configured in a very flexible way so it can be used with other synchronous serial interfaces eg the ASCO in synchronous mode serve for mas ter slave or multimaster interconnections or oper ate compatible with the popular SPI interface So it can be used to communicate with shift registers IO expansion peripherals eg EEPROMs etc or other controllers networking The SSC sup ports half duplex and full duplex communication Data is transmitted or received on pins MTSR P3 9 Master Transmit Slave Receive and MRST P3 8 Master Receive Slave Transmit The clock signal is output or input on pin SCLK P3 13 These pins are alternate functions of Port 3 pins Figure 10 1 SFRs and Port Pins associated with the SSC Ports amp Direction Control Alternate Functions Data Registers SCLK P3 13 MTSR P3 9 MRST P3 8 ODP3 Port 3 Open Drain
147. ch the branch target instruction This extra ma chine cycle is provided by means of an injected in struction see figure below If a conditional branch is not taken there is no de viation from the sequential program flow and thus no extra time is required In this case the instruc tion after the branch instruction will enter the de code stage of the pipeline at the beginning of the next machine cycle after decode of the conditional branch instruction Figure 3 3 Standard Branch Instruction Pipelining 1 Machin Cycle DECODE 34 254 ky eo J ome TARGET lrancET ITARGET 2 ITARGET 3 ITARGET 2 ITARGET 1 ITARGET 1 ITARGET SON MICROELECTRONICS INSTRUCTION PIPELINING Contd Cache Jump Instruction Processing The ST10R165 incorporates a jump cache to opti mize conditional jumps which are processed re peatedly within a loop Whenever a jump on cache is taken the extra time to fetch the branch target instruction can be saved and thus the correspond ing cache jump instruction in most cases takes only one machine cycle This performance is achieved by the following mechanism Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time and provided that the jump condition is met the jump target instruction is fetched as usu al causing a time delay of one machine cycle In contrast to standard branch instructions however the target instruction
148. ck in addition to the IP register before an interrupt service routine is entered and it is repopped when the interrupt service routine is left again System Stack Size STKSZ This bitfield defines the size of the physical system stack which is located in the internal RAM of the ST10R165 An area of 32 512 words or all of the internal RAM may be dedicated to the system stack A circular stack mechanism allows to use a bigger virtual stack than this dedicated RAM ar ea These techniques as well as the encoding of bit field STKSZ are described in more detail in chap ter System Programming 43 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d The Processor Status Word PSW This bit addressable register reflects the current state of the microcontroller Two groups of bits represent the current ALU status and the current CPU interrupt status A separate bit USRO within register PSW is provided as a general purpose user flag PSW FF10h 88h SFR Reset Value 0000h 15 14 13 12 11 0 10 9 8 7 6 5 4 3 2 1 HLD MUL ILVL EN IP V C rw rw rw Bit Function S O Negative Result M o rmn pe Tesut oan ALU opetan rep OOOO Set when the result of an ALU operation produces a carry bit Set when the result of an ALU operation produces an overflow Zero Flag Set when the result of an ALU operation is zero End of Table Flag Set when the source operand of an instruction
149. ck received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 0 Transmission and reception disabled Access to control bits 183 254 SGS THOMSON YA MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165 SSCON Register with SSCEN 1 SSCCON FFB2h D9h 15 14 13 12 SSC SSC SSC EN 1 MS BSY rw rw ny SFR 11 SSC BE rw 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC tw tw tw F 7 t Reset Value 0000h Bit o Function Operating Mode SSCEN 1 SSCBC SSC Bit Count Field Shift counter is updated with every shifted bit Do not write to SSCTE SSC Transmit Error Flag 1 Transfer starts with the slave s transmit buffer not being updated SSCRE SSC Receive Error Flag uulllldr CERNI SSCPE SSC Phase Error Flag ulllldr CR SSC Baudrate Error Flag 1 More than factor 2 or 0 5 between Slave s actual and expected baudrate SSCBSY SSC Busy Flag Set while a transfer is in progress Do not write to SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK Master Mode Generate shift clock and output it via SCLK SSC Enable Bit 1 Notes The target of an access to SSCCON control bits or flags is determined by the state of SSCEN prior to the access ie writing CO57h to SSCCON in programming mode SS CEN 0 will initialize the SSC SSCEN was 0 and then turn it on SSCEN 1
150. contain values from FOO00h to FFFEh The Stack Underflow Trap entered when SP STKUN may be used in two different ways e Fatal error indication treats the stack underflow as a system error through the associated trap service routine e Automatic system stack refilling allows to use the system stack as a Stack Cache for a bigger STKUN FE16h OBh SFR 15 14 18 12 11 10 9 8 3 Central Processing Unit ST10R165 external user stack In this case register STKUN should be initialized to a value which represents the desired highest Bottom of Stack address More details about the stack underflow trap serv ice routine and virtual stack management are giv en in chapter System Programming Scope of Stack Limit Control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit ie CALL or RET instructions This control mechanism is not triggered ie no stack trap is generated when the stack pointer SP is directly updated via MOV instructions the limits of the stack area STKOV STKUN are changed so that SP is outside of the new limits Reset Value FCOOh 7 6 5 4 3 2 1 0 r r r r rw r Modifiable portion of register STKUN Specifies the upper limit of the internal system stack SGS THOMSON YA MICROELEC
151. culated via the formula below PContr PHost PContr F 100 Fg 2 5 B Note Function Fg does not consider the toler ances of oscillators and other devices sup porting the serial communication This baudrate deviation is a nonlinear function de pending on the CPU clock and the baudrate of the host The maxima of the function Fg increase with the host baudrate due tothe smaller baudrate prescaler factors and the implied higher quantiza tion error see figure below The minimum baudrate Blow in the figure above is determined by the maximum count ca pacity of timer T6 when measuring the zero byte ie it depends on the CPU clock Using the maxi mum T6 count 216 in the formula the minimum baudrate for fopy 20 MHz is 687 Baud The low est standard baudrate in this case would be 1200 Baud Baudrates below B oy would cause T6 to overflow In this case ASCO cannot be initialized properly The maximum baudrate Byjg in the figure above is the highest baudrate where the devia tion still does not exceed the limit ie all baudrates between B y and Byigh are below the deviation limit The maximum standard baudrate that fulfills this requirement is 19200 Baud Higher baudrates however may be used as long as the actual deviation does not exceed the limit A certain baudrate marked in the figure may eg violate the deviation limit while an even higher baudrate marked II in the figure stays very well be
152. d for controlling and monitoring functions of the dif ferent on chip units Unused E SFR addresses are reserved for future members of the ST10R165 family with enhanced functionality External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip upto 16 MBytes of external RAM and or ROM can be connected to the microcontroller via its external bus interface The integrated External Bus Con troller EBC allows to access external memory and or peripheral resources in a very flexible way For up to five address areas the bus mode multi plexed demultiplexed the data bus width 8 bit 16 bit and even the length of a bus cycle wait states signal delays can be selected independ ently This allows to access a variety of memory and peripheral components directly and with max imum efficiency The EBC can control external ac cesses in one of the following four different exter nal access modes e 16 18 20 24 bit Addresses 16 bit Data de multiplexed e 16 18 20 24 bit Addresses 8 bit Data demul tiplexed e 16 18 20 24 bit Addresses 16 bit Data Multi plexed e 16 18 20 24 bit Addresses 8 bit Data Multi plexed The demultiplexed bus modes use PORT1 for ad dresses and PORTO for data input output The multiplexed bus modes use PORTO for both ad 16 254 dresses and data input output All modes use Port 4 for the upper address lines A16 if select
153. d serviced or reprogrammed mean while When the system reset was caused by a watchdog timer overflow the WDTR Watchdog Timer Reset Indication flag in register WDTCON will be setto 1 This indicates the cause of the in ternal reset to the software initialization routine WDTR is reset to 0 by an external hardware reset or by servicing the watchdog timer After the inter nal reset has completed the operation of the watchdog timer can be disabled by the DISWDT Disable Watchdog Timer instruction This in struction has been implemented as a protected in struction For further security its execution is only enabled in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has been executed Thereafter the DISWDT instruction will have no effect 208 254 13 4 RESET VALUES FOR THE ST10R165 REGISTERS During the reset sequence the registers of the ST10R165 are preset with a default value Most SFRs including system registers and peripheral control and data registers are cleared to zero so all peripherals and the interrupt system are off or idle after reset A few exceptions to this rule pro vide a first pre initialization which is either fixed or controlled by input pins DPP1 0001h points to data page 1 DPP2 0002h points to data page 2 DPP3 0003h points to data page 3 CP FCOOh STKUN FCOOh STKOV FAO00h SP FCOOh WDTCON 0002h if reset was triggered by a
154. d PEC block trans fer Note Modifying the Interrupt Request flag via soft ware causes the same effects as if it had been set or cleared by hardware Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of si 64 254 multaneous requests The priority increases with the numerical value of ILVL so 0000b is the lowest and 1111b is the highest priority level When more than one interrupt request on a specific level becomes active at the same time the values in the respective bit fields GLVL are used for sec ond level arbitration to select one request for being serviced Again the group priority increases with the numerical value of GLVL so 00b is the lowest and 11b is the highest group priority Note All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect inter rupt vector will be generated SGS THOMSON YA MICROELECTRONICS INTERRUPT SYSTEM STRUCTURE Cont d Upon entry into the interrupt service routine the priority level of the source that won the arbitration and who s priority level is higher than the current CPU level is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack The interrupt system of the ST10R165 allows nesting of up to 15 interrupt service routines of dif
155. d by the CPU an interrupt service can only be inter rupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vec tor location 3 Multiple Register Banks This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM A single one machine cycle instruction allows to switch register banks from one task to another 4 Interruptable Multiple Cycle Instructions Reduced interrupt latency is provided by allow ing multiple cycle instructions multiply divide to be interruptable 14 254 ky 3 With an interrupt response time within a range from just 250 ns to 500 ns in case of maximum speed program execution the ST10R165 is ca pable of reacting very fast on non deterministic events Its fast external interrupt inputs are sampled every 50 ns and allow to recognize even very short ex ternal signals The ST10R165 also provides an excellent mecha nism to identify and to process exceptions or error conditions that arise during run time Hardware Traps Hardware traps cause an immediate non maskable system reaction which is similiar to a standard interrupt service branching to a dedicat ed vector table location The occurrence of a hardware trap is additionally signified by an indi vidual bit in the trap flag register TFR Except for another higher prioritized trap service being in pr
156. d out of external memo ry instructions N 1 and N require external oper and read accesses instructions N 3 through N write back external operands and the interrupt SGS THOMSON YA MICROELECTRONICS 4 interrupt and Trap Functions ST10R165 vector also points to an external location In this case the interrupt response time is the time to per form 9 word bus accesses because instruction 11 cannot be fetched via the external bus until all write fetch and read requests of preceding in structions in the pipeline are terminated e When instructions N N 1 and N 2 are executed out of external memory and the interrupt vector also points to an external location but all oper ands for instructions N 3 through N are in internal memory then the interrupt response time is the time to perform 3 word bus accesses After an interrupt service routine has been termi nated by executing the RETI instruction and if fur ther interrupts are pending the next interrupt serv ice routine will not be entered until at least two in struction cycles have been executed of the pro gram that was interrupted In most cases two in structions will be executed during this time Only one instruction will typically be executed if the first instruction following the RETI instruction is a branch instruction without cache hit or if it is exe cuted out of the internal RAM Note A bus access in this context also includes delays caused by an external R
157. d program the on chip Flash memory areas Onthe ST10R165 the VPP pin is reserved and should not be connected The Power Supply pins Vp and Vss provide the power supply for the digital logic of the ST10R165 Note All Vpp pins and all VSS pins must be con nected to the power supply and ground re spectively SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ MICROELECTRONICS Chapter 7 EXTERNAL BUS INTERFACE Although the ST10R165 provides a powerful set of on chip peripherals and on chip RAM areas these internal units only cover a small fraction of its address space of up to 16 MByte The external bus interface allows to access external peripher als and additional volatile and non volatile memo ry The external bus interface provides a number of configurations so it can be taylored to fit per fectly into a given application system Accesses to external memory or peripherals are executed by the integrated External Bus Control ler EBC The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers The BUSCONXx registers specify the external bus cycles in terms of address mux demux data 16 bit 8 bit chip selects and length waitstates READY control ALE RW de lay These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUS CON4 A
158. d the same baud alternate functions of Port 3 pins Figure 9 2 Asynchronous Mode of Serial Channel ASCO Reload Register Baud Rate Timer SOPE SOM SOSTP SOFE 4 SOOE Clock SORIR Receive Int Request Serial Port Control SOTIR Ty Int RXDO P3 11 pes 20 See sor gt Request Transmit Shift F 3 e TXDO P3 10 Receive Buffer Reg Transmit Buffer Reg SORBUF SOTBUF Internal Bus MCB02219 172 054 S7 SGS THOMSON YA MICROELECTRONICS 9 Asynchronous Synchronous Serial Interface ST10R165 ASYNCHRONOUS OPERATION Cont d Asynchronous Data Frames 8 bit data frames either consist of 8 data bits D7 D0 S0M 001b or of 7 data bits D6 DO plus an automatically generated parity bit SOM 011b Parity may be odd or even de pending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 7 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 8 bit data mode The parity error flag SOPE will be set along with the er ror interrupt request flag if a wrong parity bit is re ceived The parity bit itself will be stored in bit SORBUF 7 9 bit data frames either consist of 9 data bits D8 D0 SOM 100b of 8 data bits D7 DO plus an automatically generated parity bit SOM 111b or of 8 data bits D7 DO plus wake up bit SOM 101b Parity may be odd or even depending on bit SOODD in register
159. d via its bitaddressable control register T3CON T3CON FF42h A1h SFR Reset Value 0000h 15 14 11 1 13 12 0 9 8 7 6 5 4 3 2 1 0 T3 T3 rw rw rw rw rw rw Timer 3 Input Selection Depends on the operating mode see respective sections Timer 3 Mode Control Basic Operating Mode Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high Reserved Do not use this combination Timer 3 Run Bit T3R 0 Timer Counter 3 stops T3R 1 Timer Counter 3 runs Timer 3 Up Down Control T3UDE Timer 3 External Up Down Enable T30E Alternate Output Function Enable I T30E 0 Alternate Output Function Disabled T30E 1 Alternate Output Function Enabled T30TL Timer 3 Output Toggle Latch Toggles on each overflow underflow of T3 Can be set or reset by software For the effects of bits TZ3UD and T3UDE refer to the direction table below Timer 3 Run Bit The timer can be started or stopped by software In gated timer mode the timer will only run if through bit T3R Timer T3 Run Bit If T3R 0 the T3R 1 and the gate is active high or low as pro timer stops Setting T3R to 1 will start the timer grammed s SGS THOMSON 10 1 1 1 1477 YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d Count Direction Control The count direction of the core timer can be con tr
160. de layed by one CPU clock This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slow est possible bus cycle the other ALECTLx are 0 after reset Lengthened Multiplexed Bus Cycle P4 XC Dee L1 C ND 111 MI em NS B A m BS sid em J ES d pu E l l T MCT02235 123 254 7 External Bus Interface ST10R165 PROGRAMMABLE BUS CHARACTERISTICS Cont d Programmable Memory Cycle Time The ST10R165 allows the user to adjust the con troller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controllers signals do not change The external bus cycles of the ST10R165 can be extended for a memory or peripheral which can not keep pace with the controllers maximum Figure 7 7 Memory Cycle Time speed by introducing wait states during the ac cess see figure above During these memory cy cle time wait states the CPU is idle if this access is required for the execution of the current instruc tion The memory cycle time wait states can be pro grammed in increments of one CPU clock 50 ns at f py 20 MHz within a range from 0 to 15 de fault after reset via the MCTC fields of the BUS CON registers 15 lt MCTC gt waitstates will be in serted A aaa Bus Cycle
161. de timer T5 can be clocked either by a transition at the external input pin T5IN or by a transition of timer T6 s output toggle latch T6OTL Figure 8 16 Block Diagram of Auxiliary Timer T5 in Counter Mode Auxiliary Timer Tx 162 254 Interrupt Request MCB02271 SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT2 Cont d The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at either the in put pin or at the toggle latch T6OTL Bit field T5I in control register T5CON selects the triggering transition see table below Note Only state transitions of TGOTL which are caused by the overflows underflows of T6 will trigger the counter function of T5 Modi fications of TEOTL via software will NOT trigger the counter function of T5 The maximum input frequency which is allowed in counter mode is fopy 4 2 5 MHz 9 fopy 20 MHz To ensure that a transition of the count input signal which is applied to T5IN is correctly recognized its level should be held high or low for at least 4 fopy cycles before it changes 8 General Purpose Timer Units ST10R165 Timer Concatenation Using the toggle bit TGOTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer Depend ing on which transition of T6OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bi
162. denti cal Registers BUSCON4 BUSCON1 which con trol the selected address windows are completely under software control while register BUSCONO which eg is also used for the very first code ac BUSCONO Fi Pi SFR 14 11 cess after reset is partly controlled by hardware ie it is initialized via PORTO during the reset se quence This hardware control allows to define an appropriate external bus for systems where no in ternal program memory is provided Reset Value 0XX0h 1 0 aa CSR RDY BUS ALE MTT RWD BUSCON1 ee ie SFR Reset Value 0000h 1 0 14 11 csw CSR RDY BUS ALE MTT RWD EN1 EN1 EN1 ACT1 CTL1 BTYP1 ci C1 MCTC1 BUSCON2 Aon pss SFR 14 11 Reset Value 0000h 1 0 CSW CSR RDY BUS ALE MTT RWD EN2 EN2 EN2 ACT2 CTL2 BTYP2 c2 c2 MCTC2 BUSCON3 don pim SFR Reset Value 0000h 1 0 14 11 CSW CSR RDY BUS ALE MTT RWD EN3 EN3 EN3 ACT3 CTL3 BTYP3 c3 c3 MCTC3 BUSCONA m iid SFR 14 11 Reset Value 0000h 1 0 CSW CSR RDY BUS ALE MTT RWD EN4 EN4 EN4 ACTA CTL4 BTYP4 C4 C4 MCTC4 Note BUSACTO is initialized with 0 if pin EA is high during reset If pin EA is low during reset bit BUSACTO is set ALECTLO is set 1 lected via PORTO 130 254 and bit field BTYP is loaded with the bus configuration se SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 CONTROLLING THE EXTERNAL BUS CONTROLLER Cont d
163. divide instructions BSET SAVED 1ndicate th PUSH MDH Save previous MD contents PUSH MDL P On System stack save operation 222 254 ky 3 START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU JMPR cc_NV COPYL Test for only 16 bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 MDL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers wer saved POP MDL Restore registers POP MDH POP MDC DONE BCLR SAVED Multiplication is completed program continues The above save sequence and the restore se quence after COPYL are only required if the cur rent routine could have interrupted a previous rou tine which contained a MUL or DIV instruction Register MDC is also saved because it is possible that a previous routine s Multiply or Divide instruc tion was interrupted while in progress In this case the information about how to restart the instruction is contained in this register Register MDC must be cleared to be correctly initialized for a subse quent multiplication or division The old MDC con tents must be popped from the stack before the RETI instruction is executed For a division the user must first move the divi dend into the MD register If a 16 16 bit division is specified only the low portion of register MD must be loaded The result is also stored into register MD The low portion MDL contains the integer result of the division whi
164. e Counter T6 is disabled Positive transition rising edge on T6IN Negative transition falling edge on T6IN Any transition rising or falling edge on T6IN Reserved Do not use this combination 160 254 SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT2 Cont d 8 2 2 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer gated timer or counter mode with the same op tions forthe timer frequencies and the count signal as the core timer T6 In addition to these 3 count ing modes the auxiliary timer can be concatenat ed with the core timer Note The auxiliary timer has no output toggle latch and no alternate output function T5CON FF46h A3h 14 SFR 11 rw T5I Timer 5 Input Selection 8 General Purpose Timer Units ST10R165 The individual configuration for timer T5 is deter mined by its bitaddressable control register T5CON Note that functions which are present in both timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers Reset Value 0000h 15 13 12 10 9 8 7 6 5 4 3 2 1 0 T5 T5 rw rw rw rw rw rw rw Depends on the Operating Mode see respective sections T5M 00 01 10 11 Timer 5 Run Bit T5R 0 T5R 1 Timer 5 Up Down Control Timer Mode Counter Mode Register CAPREL Input Selection 00 Capture disabled 01 10 11 Timer 5 Clear Bit T5CLR 0
165. e defines the time for a data driver to float e Read Write Delay Time defines when a com mand is activated after the falling edge of ALE e READY Control defines if a bus cycle is termi nated internally or externally Note Internal accesses are executed with maxi mum speed and therefore are not program mable External acceses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software H pe 122 254 MCTO2225 SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 PROGRAMMABLE BUS CHARACTERISTICS Cont d ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers When bit ALECTL is set to 1 external bus cycles access ing the respective address window will have their ALE signal prolonged by half a CPU clock 25 ns at fcpu 20 MHz Also the address hold time af Figure 7 6 ALE Length Control Normal Multiplexed Bus eee Segment l I fost ne ong ne BUS PO i 4 I y p IL SGS THOMSON YA MICROELECTRONICS 4 l 4 ter the falling edge of ALE on a multiplexed bus will be prolonged by half a CPU clock so the data transfer within a bus cycle refers to the same CLK OUT edges as usual ie the data transfer is
166. e and a set of peripher al units into one chip but also connects the units in avery efficient way One of the four buses used concurrently on the ST10R165 is the XBUS an in ternal representation of the external bus interface This bus provides a standardized method of inte grating application specific peripherals to produce derivates of the standard ST10R165 XBUS Module anges March 1995 ssc 9 GPT2 9 254 This is advanced information from SGS THOMSON Details are subject to change without notice 1 Architectural Overview ST10R165 1 1 BASIC CPU CONCEPTS ANDOPTIMIZATION The main core of the CPU consists of a 4 stage in struction pipeline a 16 bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware has been spent fora separate multiply and divide unit a bit mask generator and a barrel shifter To meet the demand for greater performance and flexibility a number of areas has been optimized in the processor core Functional blocks in the CPU core are controlled by signals from the in struction decode logic These are summarized be low and described in detail in the following sec tions Figure 1 2 CPU Block Diagram 1 High Instruction Bandwidth Fast Execution 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 3 Extended Bit Processing and Peripheral Con trol 4 High Performance Branch Call and Loop Processing 5 Consistent and Optimized Instruction F
167. e determined by the following formulas fcPu B an RE ADD Gun T EEO Async 32 16 lt SOBRS gt lt SOBRL gt 1 cPU BRL zm 82 16 lt S0BRS gt Biss 1 lt SOBRL gt represents the content of the reload register taken as unsigned 13 bit integer lt SOBRS gt represents the value of bit SOBRS ie 0 or 1 taken as integer The maximum baud rate that can be achieved for the asynchronous modes when using a CPU clock of 20 MHz is 625 KBaud The table below lists var ious commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate Baud Rate SOBRS 0 fcpy 20 MHz 43 3 1 4 1 0 1 4 1 0 0 2 19 2 KBaud 41 7 14 9600 Baud 0 2 1 4 96 4800 Baud 40 2 96 0 6 2400 Baud 40 2 96 0 2 0103h 0104h 40 4 96 0 2 96 1200 Baud 40 2 0 4 96 0207h 0208h 0 1 0 2 96 600 Baud 0 1 0 0 96 75 Baud 41 7 96 0410h 0411h 40 1 96 0 1 1FFFh 40 0 0 0 Synchronous Mode Baud Rates For synchronous operation the baud rate genera tor provides a clock with 4 times the rate of the es tablished baud rate The baud rate for synchro nous operation of serial channel ASCO can be de termined by the following formula fopu Sync 8 4 SOBRS lt SOBRL gt 1 fcpu SOBRL c 8 4 lt SOBRS gt Bgync lt SOBRL gt represents the content of the reload r
168. e programmer but also im plicitly by the CPU during normal instruction processing Note that any explicit write request via software to an SFR supersedes a simultane ous modification by hardware of the same regis ter Note Any write operation to a single byte of an SFR clears the non addressed complemen tary byte within the specified SFR Non implemented reserved SFR bits can not be modified and will always supply a read value of 0 41 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d The System Configuration Register SYSCON This bit addressable register provides general system configuration and control functions The reset value for register SYSCON depends on the state of the PORTO pins during reset SYSCON FF12h 89h SFR Reset Value OXX0h 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 SGT BYT CLK WR VISI XPER rw rw rw rw rw rw XBUS Peripheral Share Mode Control XPER SHARE 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode Visible Mode Control VISIBLE 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins Write Configuration Control Set according to pin POH O during reset WRCFG 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH System Clock Output E
169. e watchdog timer from overflowing during Idle mode it must be pro grammed to a reasonable time interval before Idle mode is entered SGS THOMSON YA MICROELECTRONICS 14 2 POWER DOWN MODE To further reduce the power consumption the mi crocontroller can be switched to Power Down mode Clocking of all internal blocks is stopped the contents of the internal RAM however are preserved through the voltage supplied via the Voc pins The watchdog timer is stopped in Power Down mode This mode can only be terminated by an external hardware reset ie by asserting a low level on the RSTIN pin This reset will initialize all SFRs and ports to their default state but will not change the contents of the internal RAM There are two levels of protection against uninten tionally entering Power Down mode First the PWRDN Power Down instruction which is used to enter this mode has been implemented as a protected 32 bit instruction Second this instruc tion is effective only if the NMI Non Maskable In terrupt pin is externally pulled low while the PWRDN instruction is executed The microcon troller will enter Power Down mode after the PWRDN instruction has completed SGS THOMSON YA MICROELECTRONICS 14 Power Reduction Modes ST10R165 This feature can be used in conjunction with_an external power failure signal which pulls the NMI pin low when a power failure is imminent The mi crocontroller will enter the NMI trap routin
170. e which can save the internal state into RAM After the in ternal state has been saved the trap routine may set a flag or write a certain bit pattern into specific RAM locations and then execute the PWRDN in struction If the NMI pin is still low at this time Power Down mode will be entered otherwise pro gram execution continues During power down the voltage at the Vcc pins can be lowered to 2 5 V while the contents of the internal RAM will still be preserved The initialization routine executed upon reset can check the identification flag or bit pattern with in RAM to determine whether the controller was initially switched on or whether it was properly re started from Power Down mode 217 254 14 Power Reduction Modes ST10R165 14 3 STATUS OF OUTPUT PINS DURING IDLE AND POWER DOWN MODE During Idle mode the CPU clocks are turned off while all peripherals continue their operation in the normal way Therefore all ports pins which are configured as general purpose output pins output the last data value which was written to their port output latches If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function eg WR or to a defined state which is based on the last bus ac cess eg BHE Port pins which
171. ects the bus mode that is associated with the respective window Prede fined address windows allow to use different bus modes without any overhead but restrict their number to the number of BUSCONSs However as BUSCONO controls all address areas which are not covered by the other BUSCONS this allows to have gaps between these windows which use the bus mode of BUSCONO PORT will output the intra segment address when any of the BUSCON registers selects a de multiplexed bus mode even if the current bus cy cle uses a multiplexed bus mode This allows to have an external address decoder connected to PORT only while using it for all kinds of bus cy cles SGS THOMSON YA MICROELECTRONICS 7 External Bus Interface ST10R165 Note Never change the configuration for an ad dress area that currently supplies the in struction stream Due to the internal pipelining it is very difficult to determine the first instruction fetch that will use the new configuration Only change the configura tion for address areas that are not currently accessed This applies to BUSCON regis ters as well as to ADDRSEL registers The usage of the BUSCON ADDRSEL registers is controlled via the issued addresses When an ac cess code fetch or data is initiated the respec tive generated physical address defines if the ac cess is made internally uses one of the address windows defined by ADDRSEL4 1 or uses the default configuration in BU
172. ed information from SGS THOMSON Details are subject to change without notice 17 Instruction Set Summary ST10R165 Boolean Bit Manipulation Instructions Manipulation of a maskable bit field in either the high or the low byte of a word BFLDH BFLDL Setting a single bit to 1 BSET Clearing a single bit to 0 BCLR Movement of a single bit BMOV Movement of a negated bit BMOVN ANDing of two bits BAND ORing of two bits BOR XORing of two bits BXOR Comparison of two bits BCMP Shift and Rotate Instructions Shifting right of a word SHR Shifting left of a word SHL Rotating right of a word ROR Rotating left of a word ROL Arithmetic shifting right of a word sign bit shifting ASHR Prioritize Instruction Determination of the number of shift cycles required to normalize a word operand floating point support PRIOR Data Movement Instructions Standard data movement of a word or byte MOV MOVB Data movement of a byte to a word location with either sign or zero byte extension MOVBS MOVBZ Note The data movement instructions can be used with a big number of different addressing modes in cluding indirect addressing and automatic pointer in decrementing System Stack Instructions Pushing of a word onto the system stack PUSH Popping of a word from the system stack POP Saving of a word on the system stack and then updating the old word with
173. ed into the internal RAM of the ST10R165 just below the bit addressable area see figure below PEC data transfers do not use the data page pointers DPP3 DPP0 The PEC source and des tination pointers are used as 16 bit intra segment addresses within segment 0 so that data can be transferred between any two locations within the first four data pages 3 0 The pointer locations for inactive PEC channels may be used for general data storage Only the re quired pointers occupy RAM locations Note If word data transfer is selected for a specif ic PEC channel ie BWT 0 the respec tive source and destination pointers must both contain a valid word address which points to an even byte boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used Figure 4 2 Mapping of PEC Pointers into the Internal RAM RAM Address 00 FCFEh 00 FCFCh 00 FCFAh 00 FCF8h 00 FCF6h 00 FCF4h 00 FCF2h 00 FCFOh 70 254 RAM Address 00 FCEEh 00 FCECh 00 FCEAh 00 FCE8h 00 FCE6h 00 FCE4h 00 FCE2h 00 FCEOh SGS THOMSON YA MICROELECTRONICS 4 3 PRIORITIZATION OF INTERRUPT AND PEC SERVICE REQUESTS Interrupt and PEC service requests from all sourc es can be enabled so they are arbitrated and serviced if chosen or they may be disabled so their requests are disregarded and not serviced Enabling and disabling interrupt requests may be done via three mechanisms Cont
174. egister taken as unsigned 13 bit integers lt SOBRS gt represents the value of bit SOBRS ie 0 or 1 taken as integer The maximum baud rate that can be achieved in synchronous mode when using a CPU clock of 20 MHz is 2 5 MBaud SOBRS 1 fcpy 20 MHz Reload Value 0014h 0015h 002Ah 002Bh 0055h 0056h 00ACh 00ADh 015Ah 015Bh 02B5h 02B6h 15B2h 15B3h Note The deviation errors given in the table above are rounded Using a baudrate crystal resulting in a CPU clock of eg 18 432 MHz provides correct baudrates without deviation errors 178 254 SGS THOMSON YA MICROELECTRONICS 9 Asynchronous Synchronous Serial Interface ST10R165 9 5 ASCO INTERRUPT CONTROL Four bit addressable interrupt control registers are provided for serial channel ASCO Register SOTIC controls the transmit interrupt SOTBIC controls the transmit buffer interrupt SORIC controls the receive interrupt and SOEIC controls the error in terrupt of serial channel ASCO Each interrupt source also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SOTBINT is the transmit interrupt vector SORINT is the re ceive interrupt vector and SOEINT is the error in terrupt vector SOTIC FF6Ch B6h 15 14 18 12 11 10 9 8 Se SECUS up Ceoupe CODED e Vp expe ou Tec SORIC FF6Eh B7h 15 14 13 12 11 10 9 Se veES pesi ps Ip Eee pers SOEIC FF70h B8h 15 14 13 12 11 10 9 pep
175. egment Returning from a subroutine within the current code segment plus an additional popping of a selectable register from the system stack Returning from an interrupt service routine JMPA JMPS JB JBC CALLA CALLR CALLS PCALL TRAP RET RETS RETP RETI SGS THOMSON YA MICROELECTRONICS JMPI JMPR JNB JNBS CALLI 249 254 17 Instruction Set Summary ST10R165 System Control Instructions Resetting the ST10R165 via software SRST Entering the Idle mode IDLE Entering the Power Down mode PWRDN Servicing the Watchdog Timer SRVWDT Disabling the Watchdog Timer DISWDT Signifying the end of the initialization routine pulls pin RSTOUT high and disables the effect of any later execution of a DISWDT instruction EINIT Miscellaneous Null operation which requires 2 bytes of storage and the minimum time for execution NOP Definition of an unseparable instruction sequence ATOMIC Switch reg bitoff and bitaddr addressing modes to the Extended SFR space EXTR Override the DPP addressing scheme using a specific data page instead of the DPPs and optionally switch to ESFR space EXTP EXTPR Override the DPP addressing scheme using a specific segment instead of the DPPs and optionally switch to ESFR space EXTS EXTSR Note The ATOMIC and EXT instructions provide support for uninterruptable code sequences eg for semaphore operations They
176. eive buffer register SSCRB This condition sets the error flag SSCRE and when enabled via SSCREN the error interrupt requestflag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost 192 254 ky 3 A Phase Error Master or Slave mode is detect ed when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the CPU clock changes be tween one sample before and two samples after the latching edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error inter rupt request flag SSCEIR A Baud Rate Error Slave mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 ie it either is more than double or less than half the ex pected baud rate This condition sets the error flag SSCBE and when enabled via SSCBEN the er ror interrupt request flag SSCEIR Using this error detection capability requires that the slave s baud rate generator is programmed to the same baud rate as the master device This feature allows to detect false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit SS CAREN 1 an automatic reset of the SSC will be performed in case of this error This is done to reinitialize the SSC if too few or too many clock pulses
177. eld IL VL in register PSW This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt re quests Trap Trap Vector Trap Trap Reset Functions Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps Non Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS NMITRAP STOTRAP STUTRAP 00 0000h 00 0000h 00 0000h 00 0008h 00 0010h 00 0018h 00 0028h 00 0028h 00 0028h 00 0028h 00 0028h mend O o mor Software Traps TRAP Instruction 62 254 Any Any 00 0000h 00h 7Fh 00 01FCh in steps of 4h Current CPU Priority SGS THOMSON YA MICROELECTRONICS INTERRUPT SYSTEM STRUCTURE Cont d Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sourc es which require PEC or interrupt processing is selected according to its interrupt priority This pri ority of interrupts and PEC requests is program mable in two levels Each requesting source can be assigned to a specific priority A second level group priority allows to specify an internal order for simultaneous requests from a group of differ ent sources on the same priority level At the end of each
178. elong to different memory areas is no problem Howev er when executing code the different memory ar eas must be switched explicitly via branch instruc tions Sequential boundary crossing is not sup ported and leads to erroneous results Note Changing from the external memory area to the internal RAM SFR area takes place within segment 0 SGS THOMSON YA MICROELECTRONICS CROSSING MEMORY BOUNDARIES Cont d Segments are contiguous blocks of 64 KByte each They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched ex plicitly The instructions JMPS CALLS and RETS will do this In larger sequential programs make sure that the highest used code location of a segment con tains an unconditional branch instruction to the respective following segment to prevent the prefetcher from trying to leave the current seg ment SGS THOMSON YA MICROELECTRONICS 2 Memory Organization ST10R165 Data Pages are contiguous blocks of 16 KByte each They are referenced via the data page pointers DPP3 0 and via an explicit data page number for data accesses overriding the stand ard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register that is used for the current access is se lected via the two upper b
179. en provid ed which allow the modification of multiple bits from one operand in a single instruction High Performance Branch Call and Loop Processing Due to the high percentage of branching in con troller applications branch instructions have been optimized to require one extra machine cycle only when a branch is taken This is implemented by precalculating the target address while decoding 12 254 the instruction To decrease loop execution over head three enhancements have been provided e The first solution provides single cycle branch execution after the first iteration of a loop Thus only one machine cycle is lost during the execu tion of the entire loop In loops which fall through upon completion no machine cycles are lost when exiting the loop No special instructions are re quired to perform loops and loops are automati cally detected during execution of branch instruc tions e The second loop enhancement allows the detec tion of the end of a table and avoids the use of two compare instructions embedded in loops One simply places the lowest negative number at the end ofthe specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if ei ther condition has been met The terminating con dition can then be tested e The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which
180. er channels In addition the PEC uses a dedicated area of RAM which contains the source and desti nation addresses The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the vector location related to the cor responding source PEC services are very well suited for example to move register contents to from a memory table The ST10R165 has 8 PEC channels each of which offers such fast interrupt driven data transfer capabilities SGS THOMSON YA MICROELECTRONICS 1 Architectural Overview ST10R165 Memory Areas The memory space of the ST10R165 is configured in a Von Neumann architecture which means that code memory data memory registers and IO ports are organized within the same linear ad dress space which covers up to 16 MBytes The entire memory space can be accessed bytewise or wordwise Particular portions of the on chip memory have additionally been made directly bit addressable A2KByte 16 bit wide internal RAM provides fast access to General Purpose Registers GPRs user data variables and system stack The internal RAM may also be used for code A unique decoding scheme provides flexible user register banks in the internal memory while opti
181. er cases all bits of bit field cp receive the written value ky 3 SON MICROELECTRONICS 51 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d Figure 3 7 Register Bank Selection via Register CP Internal RAM il Several addressing modes use register CP implic itly for address calculations The addressing modes mentioned below are described in chapter Instruction Set Summary Short 4 Bit GPR Addresses mnemonic Rw or Rb specify an address relative to the memory lo cation specified by the contents of the CP register ie the base of the current register bank Depending on whether a relative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is either multiplied by two or not be fore it is added to the content of register CP see figure below Thus both byte and word GPR ac cesses are possible in this way GPRs used as indirect address pointers are al ways accessed wordwise For some instructions 52 254 ky 3 only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses The respective physi cal address calculation is identical to that for the short 4 bit GPR addresses Short 8 Bit Register Addresses mnemonic reg or bitoff within a range from FOh to FFh interpret the four least significant bits as short 4 bit GPR address while the four most significant bits are ig nored The r
182. erial channel The timer is reloaded with the value stored in its 13 bit reload register each time it un derflows The resulting clock is again divided ac cording to the operating mode and controlled by the Baudrate Selection Bit SOBRS If SOBRS 1 the clock signal is additionally divided to 2 3rd of its frequency see formulas and table So the baud rate of ASCO is determined by the CPU clock the reload value the value of SOBRS and the operating mode asynchronous or synchro nous Register SOBG is the dual function Baud Rate Generator Reload register Reading SOBG returns the content of the timer bits 15 13 return zero while writing to SOBG always updates the reload register bits 15 13 are insiginificant An auto reload of the timer with the content of the reload register is performed each time SOBG is written to However if SOR 0 at the time the write operation to SOBG is performed the timer will not be reloaded until the first instruction cycle after SOR 1 177 254 9 Asynchronous Synchronous Serial Interface ST10R165 ASCO BAUD RATE GENERATION Cont d Asynchronous Mode Baud Rates For asynchronous operation the baud rate gener ator provides a clock with 16 times the rate of the established baud rate Every received bit is sam pled at the 7th 8th and 9th cycle of this clock The baud rate for asynchronous operation of serial channel ASCO and the required reload value for a given baudrate can b
183. ernal hardware reset see note or watchdog timer reset the watchdog timer is enabled and starts counting up from 0000h with the frequency fcpy 2 The input fre quency may be switched to fcpy 128 by setting bit WDTIN The watchdog timer can be disabled via the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT When the watchdog timer is not disabled via in struction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reach es FFFFh the watchdog timer will overflow and cause an internal reset This reset will pull the ex ternal reset indication pin RSTOUT low It differs from a software or external hardware reset in that bit WDTR Watchdog Timer Reset Indication Flag of register WDTCON will be set A hardware reset or the SRVWDT instruction will clear this bit Bit WDTR can be examined by software in order to determine the cause of the reset A watchdog reset will also complete a running ex ternal bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active low after the pro 11 Watchdog Timer ST10R165 To pr
184. ernal memory peripheral for read cycles Af ter a period of time which is determined by the ac cess time of the memory peripheral data become valid Read cycles Input data is latched and the com mand signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again Write cycles The command signal is now deacti vated The data remain valid on the bus until the next external bus cycle is started E Bus Cycle r Segment P4 ALE BUS PO RD BUS PO SGS THOMSON YA MICROELECTRONICS MCTO2060 115 254 7 External Bus Interface ST10R165 EXTERNAL BUS MODES Cont d Demultiplexed Bus Modes In the demultiplexed bus modes the 16 bit intra segment address is permanently output on PORT1 while the data uses PORTO 16 bit data or POL 8 bit data The upper address lines are permanently output on Port 4 if selected via SALSEL during reset No address latches are required The EBC initiates an external access by placing an address on the address bus After a program mable period of time the EBC activates the re spective command signal RD WR WRL WRH Data is driven onto the data bus either by the EBC Figure 7 3 Demultiplexed Bus Cycle for write cycles or by the external memory pe ripheral for read cycles After a period of time which is determined by the access time of the
185. espective physical GPR address cal culation is identical to that for the short 4 bit GPR addresses For single bit accesses on a GPR the GPR s word address is calculated as just de scribed but the position of the bit within the word is specified by a separate additional 4 bit value SON MICROELECTRONICS CPU SPECIAL FUNCTION REGISTERS Cont d 3 Central Processing Unit ST10R165 Figure 3 8 Implicit CP Use by Short GPR Addressing Modes Specified by reg or bitoff Vj 1111 4 Bit GPR Address Z Y Conlext Pointer Y Control i l For byte GPR accesses The Stack Pointer SP This non bit addressable register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Since the least significant bit of register SP is tied to 0 and bits 15 through 12 are tied to 1 by hard ware the SP register can only contain values from FOOOh to FFFEh This allows to access a physical SP FE12h 09h SFR 15 14 13 12 11 10 9 8 SGS THOMSON YA MICROELECTRONICS I For word GPR accesses Internal Must be within the internal RAM area MCA02005 stack within the internal RAM of the ST10R165 A virtual stack usually bigger can be realized via software This mechanism is
186. event the watchdog timer from overflowing it must be serviced periodically by the user soft ware The watchdog timer is serviced with the in struction SRVWDT which is a protected 32 bit in struction Servicing the watchdog timer clears the low byte and reloads the high byte of the watch dog time register WDT with the preset value in bit field WDTREL which is the high byte of register WDTCON Servicing the watchdog timer will also reset bit WDTR After being serviced the watch dog timer continues counting up from the value lt WDTREL gt 29 Instruction SRVWDT has been encoded in such a way that the chance of uninten tionally servicing the watchdog timer eg by fetch ing and executing a bit pattern from a wrong loca tion is minimized When instruction SRVWDT does not match the format for protected instruc tions the Protection Fault Trap will be entered rather than the instruction be executed The time period for an overflow of the watchdog timer is programmable in two ways e the input frequency to the watchdog timer can be selected via bit WDTIN in register WDTCON to be either fc pi 2 or fc pi j 128 e the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON The period Pwpr between servicing the watchdog timer and the next overflow can therefore be de termined by the following formula 1 lt WDTIN gt 6 516 _ 98 grammed waitstates Otherwise the external bus Pwpr 2 tere DIES
187. f this bus cycle either does not use READY at all or if READY is sampled active low after the programmed waitstates When READY is sampled inactive high after the pro grammed waitstates the running external bus cy cle is aborted Then the internal reset sequence is started Note A watchdog reset disregards the configura tion of POL 5 POL 0 The watchdog reset cannot occur while the ST10R165 is in bootstrap loader mode SGS THOMSON YA MICROELECTRONICS 13 1 THE ST10R165 S PINS AFTER RESET After the reset sequence the different groups of pins of the ST10R165 are activated in different ways depending on their function Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORTO so either external accesses can Figure 13 2 Reset Input and Output Signals Internal reset condition Internal reset condition 13 System Reset ST10R165 takes place or the external control signals are in active The general purpose IO pins remain in in put mode high impedance until reprogrammed via software see figure below The RSTOUT pin remains active low until the end of the initializa tion routine see description Initialization Initialization When the internal reset condition is prolongued by RSTIN the activation of the output signals is delayed until the end of the internal reset condition Current bus cycle is completed or aborted S
188. fferent application areas such as automotive industrial control or data communications The core of the 16 bit family has been developped with a modular family concept in mind All family members execute an efficient control optimized instruction set additional instructions for members of the second generation This allows an easy and quick implementation of new family members with different internal memory sizes and technologies different sets of on chip peripherals and or different numbers of IO pins 2 254 The XBUS concept opens a straight forward path for the integration of application specific peripheral modules in addition to the standard on chip peripherals in order to build application specific derivatives As programs for embedded control applications become larger high level languages are favoured by programmers because high level language programs are easier to write to debug and to maintain The ST10F166 with 32 K bytes of Flash memory was the first generation of this 16 bit controller family The ST10R165 is one of the new members of the second generation of this family This second generation is even more powerful due to additional instructions for HLL support an increased address space increased internal RAM andhighly efficient management of various resources on the external bus Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost s
189. fined Opcode e Protection Fault e Illegal Word Operand Access TFR FFACh D6h SFR 14 STK OF rw 11 15 13 12 STK UF rw rw 10 9 8 7 6 5 4 3 2 1 0 UND PRT ILL ILL ILL OPC FLT OPA INA BUS rw rw rw rw rw 4 Interrupt and Trap Functions ST10R165 e llegal Instruction Access e llegal External Bus Access Trap These traps share the same trap priority and the same vector address The bit addressable Trap Flag Register TFR al lows a trap service routine to identify the kind of trap which caused the exception Each trap func tion is indicated by a separate request flag When a hardware trap occurs the corresponding re quest flag in register TFR is set to 1 Reset Value 0000h Illegal External Bus Access Flag ILLBUS An external access has been attempted with no external bus defined ILLINA Illegal Instruction Access Flag A branch to an odd address has been attempted ILLOPA Illegal Word Operand Access Flag A word operand access read or write to an odd address has been attempted Protection Fault Flag PRTFLT i A protected instruction with an illegal format has been detected UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid ST10R165 opcode Stack Underflow Flag STKUF The current stack pointer value exceeds the content of register STKUN Stack Overflow Flag STKOF The current stack pointer value falls below the content of regis
190. flow a SRST instruction or when the reset input signal RSTIN is latched low hard ware reset The internal reset condition is active at least for the duration of the reset sequence and then until the RSTIN input is inactive When this internal reset condition is removed reset se quence complete and RSTIN inactive the reset configuration is latched from PORTO and pins ALE RD and WR are driven to their inactive lev els After the internal reset condition is removed the microcontroller will start program execution from memory location 00 0000h in code segment zero This start location will typically hold a branch in struction to the start of a software initialization rou tine for the application specific configuration of pe ripherals and CPU Special Function Registers External Hardware External Reset Sources Generated Warm reset Automatic Power on reset 205 254 This is advanced information from SGS THOMSON Details are subject to change without notice 13 System Reset ST10R165 Hardware Reset A hardware reset is triggered when the reset input signal RSTIN is latched low To ensure the recog nition of the RSTIN signal latching it must be held low for at least 2 CPU clock cycles However also shorter RSTIN pulses may trigger a hardware reset if they coincide with the latch s sample point RSTIN may go high during the reset se quence After the reset sequence has been com pleted the RSTIN i
191. from the respective external memory area 38 254 a Updating the Stack Pointer An instruction that changes the contents of the stack pointer SP MOV ADD SUB may not be followed directly by an instruction that implicitly uses the SP ie a POP or RETURN instruction To ensure proper operation an instruction should be inserted that does not use the stack pointer a Timing Instruction pipelining reduces the average instruc tion processing time in a wide scale from four to one machine cycles mostly However there are some rare cases where a particular pipeline situ ation causes the processing time for a single in struction to be extended either by a half or by one machine cycle Although this additional time rep resents only a tiny part of the total program execu tion time it might be of interest to avoid these pipeline caused time delays in time critical pro gram modules Besides a general execution time description the following section provides some hints on how to optimize time critical program parts with regard to such pipeline caused timing particularities SGS THOMSON YA MICROELECTRONICS 3 2 BIT HANDLING AND BIT PROTECTION The ST10R165 provides several mechanisms to manipulate bits These mechanisms either manip ulate software flags within the internal RAM con trol on chip peripherals via control bits in their re spective SFRs or control IO functions via port pins The instructions BSET BCLR BAND
192. from binary multiples of the CPU clock Peripheral Interfaces The on chip peripherals generally have two differ ent types of interfaces an interface to the CPU and an interface to external hardware Communi cation between CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interrupt re quests are generated by the peripherals based on specific events which occur during their operation eg operation complete error etc For interfacing with external hardware specific pins of the parallel ports are used when an input SGS THOMSON YA MICROELECTRONICS 1 Architectural Overview ST10R165 or output function has been selected for a periph eral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose IO pin Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock fcpy The on chip oscil lator derives the CPU clock from the crystal or from the external clock signal The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue thei
193. gram ming The required pins of Port 4 are automatically switched to address output mode Even if not all segment address lines are enabled on Port 4 the ST10R165 internally uses its com plete 24 bit addressing mechanism This allows to restrict the width of the effective address bus while still deriving CS signals from the complete addresses Default 2 bit segment address A17 A16 allow ing access to 256 KByte Note The selected number of segment address lines cannot be changed via software after reset BHE Pin Configuration Pin POH O defines the write configuration control bit WRCFG of SYSCON register If POH O is pulled down during reset the bit WRCFG is set to T and the pin BHE is configured as WRH Write High Byte while pin WR is configured as WRL Write Low Byte Default pins WR and BHE retain their normal functions Configuration of Integrated XBUS Peripherals The PORTO pins that are reserved for the configu ration of specific derivatives X are provided for customer specific peripherals that have been inte grated into application specific versions of the ST10R165 and are connected via the XBUS In basic ST10R165 devices these pins are disre garded However for reasons of compatibility and upgradability it is recommended to keep those pins high during reset which are not used in the re spective devices These bits are latched in regis ter RPOH Default Inactive state depends on peripheral
194. h auxiliary timer T5 Triggered by an exter nal signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can count up or down and the current timer value can be read or modified by the CPU in the non bitaddressable SFRs T5 and T6 Figure 8 11 SFRs and Port Pins Associated with Timer Block GPT2 Ports amp Direction Control Alternate Functions Data Registers T5IN P5 13 T5EUD P5 11 T6IN P5 12 TGEUD P5 10 CAPIN P3 2 T6OUT P3 1 ODP3 Port 3 Open Drain Control Register Port 3 Direction Control Register Port 3 Data Register Port 5 Data Register GPT2 Timer 5 Control Register GPT2 Timer 6 Control Register 154 254 Control Registers Interrupt Control GPT2Timer5Register T7 GPT2 Timer 6 Register GPT2 Capture Reload Register C EOT Re funt Control Register GPT2 Suc 6 Ifiterrupt Control Register GPT2 CAPREL Interrupt Control Register SGS THOMSON YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT2 Cont d Figure 8 12 GPT2 Block Diagram TSEUD CPU lock 7 n 2 9 u o F3 7 Interrupt T5N GPT2 Timer T5 Recusst Clear y Capture ie a Interrupt Request GPT2 CAPREL Reload Interrupt Request Mode GPT2 Timer T6 TBOTL reour CPU Clock Control to CAPCOM TeEUD Timers U D MCTO2142 v5 SGS THOMSON 188 254 YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 TIMER BLOCK
195. hardware if the alter nate function of such a pin is enabled To determine the appropriate level of the port out put latches check how the alternate data output is combined with the respective port latch output SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose IO lines When using port pins for general purpose output the initial output value should be written to the port latch prior to enabling the output drivers in order to avoid undesired transitions on the out put pins This applies to single pins as well as to pin groups see examples below SINGLE_BIT BSET P4 7 Initial output level is high BSET DP4 7 Switch on the output driver BIT GROUP BFLDHP4 24h 24h Initial output level is high BFLDHDP4 24h 24h Switch on the output drivers Note When using several BSET pairs to control more pins of one port these pairs must be separated by instructions which do not ref erence the respective port see Particular Pipeline Effects in chapter The Central P
196. have been detected SON MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165 ERROR DETECTION MECHANISMS Cont d A Transmit Error Slave mode is detected when a transfer was initiated by the master shift clock gets active but the transmit buffer SSCTB of the slave was not updated since the last transfer This condition sets the error flag SSCTE and when en abled via SSCTEN the error interrupt request flag SSCEIR If a transfer starts while the transmit buff er is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to the corruption of the data on the transmit receive line in half duplex mode open Figure 10 6 SSC Error Interrupt Control Register SSCCON Transmit Receive Baudrate SGS THOMSON YA MICROELECTRONICS drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones ie their transmit buffers must be loaded with FFFFh prior to any transfer Note A slave with push pull output drivers which is not selected for transmission will normal ly have its output drivers switched Howev er in order to avoid possible conflicts or misinterpretations it is recommended to al ways load the slave s transmit buffer prior to any transfer Register SSCEIR SSCEIE Error Interrupt SSCEINT
197. he arbitration circuit ry BREQ is activated only during hold mode It will be inactive during normal operation Figure 7 11 External Bus Arbitration Releasing the Bus 2 Signals a l l l l Other MCT02238 Note The ST10R165 will complete the currently running bus cycle before granting bus access as indicat ed by the broken lines This may delay hold acknowledge compared to this figure The figure above shows the first possibility for BREQ to get active 136 254 SGS THOMSON YA MICROELECTRONICS EXTERNAL BUS ARBITRATION Cont d Exiting the Hold State The external bus master returns the access rights to the ST10R165 by driving the HOLD input high After synchronizing this signal the ST10R165 will drive the HLDA output high actively drive the con trol signals and resume executing external bus cy cles if required Depending on the arbitration logic the external bus can be returned to the ST10R165 under two circumstances 7 External Bus Interface ST10R165 e The external master does no more require ac cess tothe shared resources and gives up its own access rights or e The ST10R165 needs access to the shared re sources and demands this by activating its BREQ output The arbitration logic may then deactivate the other master s HLDA and so free the external bus for the ST10R165 depending on the priority of the different masters Figure 7 12 External Bus Arb
198. he bus control registers BUSCONA BUSCONO can be output on 5 pins of Port 6 The other 3 pins may be used for bus ar bitration to accomodate additional masters in a ST10R165 system The number of chip select signals is selected via Port 6 Pin Altern Function CSSEL 10 G en purpose IO purpose IO purpose IO purpose IO purpose IO HOLDExternal hold request input HLDAHold acknowledge output BREQBus request output Figure 5 16 Port 6 IO and Alternate Functions Alternate Function General Purpose Input O utput 108 254 PORTO during reset The selected value can be read from bitfield CSSEL in register RPOH read only eg in order to check the configuration during run time The table below summarizes the alternate func tions of Port 6 depending on the number of select ed chip select lines coded via bitfield CSSEL Altern Function Altern Function Altern Function CSSEL 01 CSSEL 00 CSSEL 11 Chip select CSO Chip select CS1 Gen purpose IO Gen purpose IO Gen purpose IO Chip select CSO Chip select CSO Chip select CS1 Chip select CS2 Gen purpose IO Gen purpose IO Chip select CS1 Chip select Chip select CS3 Chip select CS4 SGS THOMSON YA MICROELECTRONICS PORT 6 Cont d The chip select lines of Port 6 additionally have an internal weak pullup device This device is switched on under the following conditions ealways during reset eif the Port 6 line
199. he slaves that were not being addressed remain in 8 bit data wake up bit mode ignoring the following data bytes DO D1 D2 D3 D4 D5 D7 LSB Parity Figure 9 4 Asynchronous 9 bit Data Frames SGS THOMSON YA MICROELECTRONICS Do D1 D2 D3 D4 D5 D7 9th LSB Bit 2nd top Stop Bit Data Bit D8 e Parity e Wake up Bit 173 254 9 Asynchronous Synchronous Serial Interface ST10R165 ASYNCHRONOUS OPERATION Cont d Asynchronous transmission begins at the next overflow of the divide by 16 counter see figure above provided that SOR is set and data has been loaded into SOTBUF The transmitted data frame consists of three basic elements the start bit the data field 8 or 9 bits LSB first including a parity bit if selected the delimiter 1 or 2 stop bits Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The transmit interrupt request flag SOTIR will be set before the last bit of a frame is transmitted ie before the first or the second stop bit is shifted out of the transmit shift register The transmitter output pin TXDO P3 10
200. heral associated with a Port 3 pin is configured to use both the alternate input and output function the descriptions above apply to the respective current operating mode The direction must be set accordingly Port 3 pins with alternate input output functions are MTSR MRST RxDO and SCLK Note Enabling the CLKOUT function automatical ly enables the P3 15 output driver Setting bit DP3 15 1 is not required 99 254 5 Parallel Ports ST10R165 PORT 3 Cont d Figure 5 10 Block Diagram of a Port3 Pin with Alternate Input or Alternate Output Function Write ODP3 y Open Drain Latch Read ODP3 y Direction Latch Read DP3 y I n t e F n a l Alternate Data Output i la oc am Output Buffer Clock MCB02229 yz 13 11 0 100 254 S7 SGS THOMSON YA MICROELECTRONICS PORT 3 Cont d Pin P3 12 BHE WRH is one more pin with an al ternate output function However its structure is slightly different see figure below because after reset the BHE or WRH function must be used de pending on the system startup configuration In these cases there is no possibility to program any 5 Parallel Ports ST10R165 port latches before Thus the appropriate alternate function is selected automatically If BHE WRH is not used in the system this pin can be used for general purpose IO by disabling the alternate function BYTDIS 1 WRCFG 0 Figure 5 11 Block Diagram of Pins P3 15
201. i Signal circuit_2 SGS THOMSON YA MICROELECTRONICS 12 2 MEMORY CONFIGURATION AFTER RESET The configuration ie the accessibility of the ST10R165 s memory areas after reset in Boot strap Loader mode differs from the standard case Pin EA is not evaluated when BSL mode is select ed and accesses to the address range 00 0000h 00 7FFFh are partly re directed while the ST10R165 is in BSL mode see table below All code fetches are made from the special Boot ROM while data accesses will return undefined values on the ST10R165 external 12 Bootstrap Loader ST10R165 Note When the BSL mode is active the address range 00 0000h 00 7FFFh is reserved for the special Boot ROM External memory in this address range cannot be accessed un less the Boot ROM area is moved to the segment 1 bit ROMS1 of SYSCON register set to 1 access to Depends on reset config EA PO bus enabled BSL mode active Yes POL 4 0 No POL 4 1 must be low must be low Code fetch from address Boot ROM access External memory range 00 0000h 00 7FFFh Data fetch from address range Undefined value External memory 00 0000h 00 7FFFh ky 3 SON MICROELECTRONICS 201 254 12 Bootstrap Loader ST10R165 12 3 LOADING THE STARTUP CODE After sending the identification byte the BSL en ters a loop to receive 32 bytes via ASCO These bytes are stored sequentially into locations 00 FA40h through 00 FA5
202. icitly used whenever data accesses to any memory location are made via indirect or direct long 16 bit addressing modes except for override accesses via EXTended in structions and PEC data transfers After reset the Data Page Pointers are initialized in a way that all indirect or direct long 16 bit addresses result in identical 18 bit addresses This allows to access data pages 3 0 within segment 0 as shownin the figure below If the user does not want to use any data paging no further action is required Reset Value 0000h 7 6 5 4 3 2 1 0 DPPOPN DPP1 FEO02h 01h SFR 15 14 1 11 10 9 8 3 12 rw Reset Value 0001h 7 6 5 4 3 2 1 0 DPP1PN rw Reset Value 0002h 7 6 5 4 3 2 1 0 DPP2PN DPP2 FE04h 02h SFR 15 14 13 12 11 10 9 8 DPP3 FEO6h 03h SFR 15 14 11 10 9 8 Reset Value 0003h 7 6 5 4 3 2 1 0 13 12 Data Page Number of DPPx DPPxPN SGS THOMSON YA MICROELECTRONICS Specifies the data page selected via DPPx Only the least significant two bits of DPPx are sig nificant when segmentation is disabled 49 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit ad dress with the contents of the DDP register select ed by the upper two bits of the 16 bit address The content of the selected DPP register specifies one of the 1024 possible data pages This dat
203. implicit decrement of the SP is made through a PUSH or CALL instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decre mented by a subtract instruction the IP value pushed represents the address of the instruction after the instruction following the subtract instruc tion For recovery from stack overflow it must be en sured that there is enough excess space on the stack for saving the current system state PSW IP in segmented mode also CSP twice Other wise a system reset should be generated Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine Again which IP value will be pushed onto the system stack depends on SGS THOMSON YA MICROELECTRONICS TRAP FUNCTIONS Cont d which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruc tion the pushed IP value represents the address of the instruction after the instruction following the add instruction Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid ST10R165 opcode the UNDOPC flag is set in
204. ine first the old CP must be restored by popping it from the stack and then the number of used local registers must be added to the SP to restore the allocated local space back to the system stack Note The system stack is growing downwards while the register bank is growing upwards The software to provide the local register bank for the example above is very compact Figure 15 2 Local Registers After entering the subroutine SUB SP 10 Free 5 words in the current system Stack SCXT CP SP Set th new register bank pointer Before exiting the subroutine POP CP Restore the old register bank ADD SP 10 Release the 5 word of the current System stack Old Stack Area Newly Allocated Register Bank Old CP Contents o BEEN 230 254 SGS THOMSON YA MICROELECTRONICS 15 7 TABLE SEARCHING A number of features have been included to de crease the execution time required to search ta bles First branch delays are eliminated by the branch target cache after the first iteration of the loop Second in non sequentially searched ta bles the enhanced performance of the ALU al lows more complicated hash algorithms to be processed to obtain better table distribution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease the number of overhead instructions executed in the loop The two examples below illustrate
205. ins a 1 otherwise it is cleared In the case of integer operations the N flag can be inter preted as the sign bit of the result negative N2 1 positive N 0 Negative numbers are always represented as the 2 s complement of the corre sponding positive number The range of signed numbers extends from 8000h to 7FFFh for the word data type or from 80h to 7Fh for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical XORing of the two specified bits e C Flag After an addition the C flag indicates that a carry from the most significant bit of the speci fied word or byte data type has been generated After asubtraction or a comparison the C flag indi cates a borrow which represents the logical nega tion of a carry for the addition This means that the C flag is set to 1 if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these opera tions cannot cause a carry anyhow For shift and rotate operations the C flag repre ky 3 SON MICROELECTRONICS 3 Ce
206. interrupt request if appropri ate Start bits that follow this frame will not be rec ognized Note In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be ac tivated and no data will be transferred SON MICROELECTRONICS 9 Asynchronous Synchronous Serial Interface ST10R165 9 2 SYNCHRONOUS OPERATION Synchronous mode supports half duplex commu nication basically for simple IO expansion via shift registers Data is transmitted and received via pin RXDO P3 11 while pin TXDO P3 10 outputs the shift clock These signals are alternate functions of Port 3 pins Synchronous mode is selected with S0M 000b 8 data bits are transmitted or received synchro nous to a shift clock generated by the internal baud rate generator The shift clock is only active as long as data bits are transmitted or received Figure 9 5 Synchronous Mode of Serial Channel ASCO Reload Register SOM OOUB Clock Receive Int Request Request TXDO P3 10 Serial Port Control Transmit Int gs Shift Clock Error Int Receive DP He Request MUX Receive Shift Transmit Shift RXDO P3 11 Register Register 1 Transmit Receive Buffer Reg Transmit Buffer Reg SORBUF SOTBUF Internal Bus MCB02220 THOMSON 173 253 SGS YA MICROELECTRONICS 9 Asynchronous Synchronous Serial Interface ST10R165
207. ions Miscellaneous Instructions Possible operand types are bits bytes and words Specific instruction support the conversion exten sion of bytes to words A variety of direct indirect or immediate addressing modes are provided to specify the required operands Programmable Multiple Priority System Interrupt The following enhancements have been included to allow processing of a large number of interrupt Sources 1 Peripheral Event Controller PEC This proc essor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven byte or word data transfers between any two locations in segment 0 with an optional incre ment of either the PEC source or the destina tion pointer Just one cycle is stolen from the current CPU activity to perform a PEC service 13 254 1 Architectural Overview ST10R165 BASIC CPU CONCEPTS AND OPTIMIZATION Cont d 2 Multiple Priority Interrupt Controller This con troller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the abil ity to prevent similar priority tasks from inter rupting each other For each of the possible interrupt sources there is a separate control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority bitfield Once having been accepte
208. irst bit of the transmit data will be placed onto the MTSR line on the next clock from the baudrate generator transmission only starts if SS CEN 1 Depending on the selected clock phase also a clock pulse will be generated on the SCLK line With the opposite clock edge the mas ter at the same time latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Since the clock line is connected to all slaves their shift reg isters will be shifted synchronously with the mas ter s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift reg ister holds the data of the selected slave In the master and all slaves the content of the shift regis ter is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set 187 254 10 High Speed Synchronous Serial Interface ST10R165 FULL DUPLEX OPERATION Cont d A slave device will immediately output the select ed first bit MSB or LSB of the transfer data at pin MRST when the content of the transmit buffer is copied into the slave s shift register It will not wait for the next clock from the baudrate generator as the master does The reason for this is that de
209. is used as a chip select output and the ST10R165 is in Hold mode invoked through HOLD and the respective pin driver is in push pull mode ODP6 x 0 This feature is implemented to drive the chip se lect lines high during reset in order to avoid multi ple chip selection and to allow another master to access the external memory via the same chip se lect lines Wired AND while the ST10R165 is in Hold mode With ODP6 x 1 open drain output selected the internal pullup device will not be active during 5 Parallel Ports ST10R165 Hold mode external pullup devices must be used in this case aes When entering Hold mode the CS lines are active ly driven high for one clock phase then the output level is controlled by the pullup devices if activat ed After reset the CS function must be used if select ed so In this case there is no possibility to pro gram any port latches before Thus the alternate function CS is selected automatically in this case Note The open drain output option can only be selected via software earliest during the ini tialization routine atleast signal CSO will be in push pull output driver mode directly after reset Figure 5 17 Block Diagram of Port 6 Pins with an alternate output function Write ODP6 y Open Drain Latch Read ODP6 y Write DP6 y d V p 1 MUX 0 Alternate Function Enable Direction Latch Read DP6 y Alternate Data Outp
210. it and 16 bit Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16 bit ALU In addition for byte op erations signals are provided from bits six and seven ofthe ALU result to correctly set the condi tion flags Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from pre viously calculated portions of the desired opera tion Most internal execution blocks have been op timized to perform operations on either 8 bit or 16 bit quantities Once the pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per ma chine cycle Thus these operations use two cou pled 16 bit registers MDL and MDH and require four and nine machine cycles respectively to per form a 16 bit by 16 bit or 32 bit by 16 bit calcula tion plus one machine cycle to setup and adjust the operands and the result Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast inter rupt response Instructions have also been provid ed to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements 11 254 1 Archi
211. it cannot operate in single chip mode Hence the EA pin must be forced at 0 during reset 7 2 EXTERNAL BUS MODES When the external bus interface is enabled bit BUSACTx 1 and configured bitfield BTYP the ST10R165 uses a subset of its port lines together with some control lines to build the external bus The bus configuration BTYP for the address win dows BUSCON4 BUSCON1 is selected via software typically during the initialization of the system The bus configuration BTYP for the default ad dress range BUSCONO is selected via PORTO during reset provided that pin EA is low during re set Afterwards BUSCONO may be modified via software just like the other BUSCON registers The 16 MByte address space of the ST10R165 is divided into 256 segments of 64 KByte each The 16 bit intra segment address is output on PORTO for multiplexed bus modes or on PORT1 for de multiplexed bus modes When segmentation is disabled only one 64 KByte segment can be used and accessed Otherwise additional address lines may be output on Port 4 and or several chip se lect lines may be used to select different memory banks or peripherals These functions are select ed during reset via bitfields SALSEL and CSSEL of register RPOH respectively Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmen tation disabled BTYP Encoding External Data Bus Width Ex
212. itration Regaining the Bus CSx Other Signals MCTO2236 Note The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain sequence Even if BREQ is activated earlier the regain sequence is initiated by HOLD going high BREQ and HOLD are connected via an external arbitration circuitry Please note that HOLD may also be de activated without the ST10R165 requesting the bus SGS THOMSON YA MICROELECTRONICS 137 254 7 External Bus Interface ST10R165 7 8 THE XBUS INTERFACE The ST10R165 provides an on chip interface the XBUS interface which allows to connect integrat ed customer application specific peripherals to the standard controller core The XBUS is an internal representation of the external bus interface ie it is operated in the same way The current XBUS interface is prepared to support up to 3 X Peripherals For each peripheral on the XBUS X Peripheral there is a separate address window controlled by an XBCON and an XADRS register As an inter face to a peripheral in many cases is represented by just a few registers the XADRS registers select smaller address windows than the standard AD 138 254 DRSEL registers As the register pairs control in tegrated peripherals rather than externally con nected ones they are fixed by mask programming rather than being user programmable X Peripheral accesses provide the same choices as external accesses so these peripherals ma
213. its of the 16 bit data address Subsequent 16 bit data addresses that cross the 16 KByte data page boundaries there fore will use different data page pointers while the physical locations need not be subsequent within memory 29 254 2 Memory Organization ST10R165 Notes 30 284 IL fay SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual JA MICROELECTRONICS Chapter 3 CENTRAL PROCESSING UNIT Basic tasks of the CPU are to fetch and decode in structions to supply operands for the arithmetic and logic unit ALU to perform operations on these operands in the ALU and to store the previ ously calculated results As the CPU is the main engine of the ST10R165 controller it is also af fected by certain actions of the peripheral subsys tem Since a four stage pipeline is implemented in the ST10R165 up to four instructions can be proc essed in parallel Most instructions of the ST10R165 are executed in one machine cycle ie 100 ns 20 MHz CPU clock due to this parallel ism This chapter describes how the pipeline works for sequential and branch instructions in general and which hardware provisions have been made to speed the execution of jump in Figure 3 1 CPU Block Diagram structions in particular The general instruction timing is described including standard and excep tional timing While internal memory accesses are normally per formed by the CPU itself external peripheral or
214. l Configuration Precautions and Hints e The external bus interface is enabled as long as at least one of the BUSCON registers has its BUS ACT bit set e PORT will output the intra segment address as long as at least one of the BUSCON registers se 134 254 ky 3 1 0 8 bit segment address A23 A16 1 1 2 bit segment address A17 A16 Default without pulldowns Chip Select Line Selection Number of active CS outputs 11 5 CS lines CS4 C S0 Default without pulldowns Segment Address Line Selection Number of active segment address outputs 0 0 4 bit segment address A19 A16 These pins are reserved for XBUS peripherals integrated into application specific versions of the ST10R165 Leave these pins open on standard ST10R165 controllers lects a demultiplexed external bus even for multi plexed bus cycles e The address areas defined via registers AD DRSELx may not overlap each other The opera tion of the EBC will be unpredictable in such a case e The address areas defined via registers AD DRSELx may overlap internal address areas In ternal accesses will be executed in this case e For any access to an internal address area the EBC will remain inactive see EBC Idle State SON MICROELECTRONICS 7 6 EBC IDLE STATE When the external bus interface is enabled but no external access is currently executed the EBC is idle During this idle state the external interface appears in the following way
215. le the high portion MDH contains the remainder SON MICROELECTRONICS MULTIPLICATION AND DIVISION Cont d The following instruction sequence performs a 32 by 16 bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds the divisor JMPR cc V ERROR Test for divide overflow MOV R3 MDH Move remainder to R3 MOV R4 MDL Move integer result to R4 Clears MDRIU Whenever a multiply or divide instruction is inter rupted while in progress the address of the inter rupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set When the interrupt routine is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIPz 1 the multiply divide instruction is re read SGS THOMSON YA MICROELECTRONICS 15 System Programming ST10R165 from the location popped from the stack return address and will be completed after the RETI in struction has been executed Note The MULIP flagis part of the context of the interrupted task When the interrupting routine does not return to the interrupted task eg scheduler switches to another task the MULIP flag must be set or cleared according to the context of the task that is switched to 15 3 BCD CALCULATIONS No direct support for BCD calculations is provided in the ST10R165 B
216. ll SFRs which are imple Extended SFR Space ESFRs are marked with mented in the ST10R165 ordered by their physical the letter E in column Physical Address address Bit addressable SFRs are marked with the letter b in column Name SFRs within the pee uem ame mem tme ee oe A 9 03 sscem rosne um ssc Basate Regeer nth nm ef rrooe eon rot Drecten Corra measer fo ew e Erone sm Prt Droen Correios Ton DPIM Fioshe een PiHDiedonOowoRegser 00 aron of erone um p Son Sarun Coton mee mew m owe reme em Pons Opn an Cont megas eo pppo FEoon oon CPU Data Page Pointer 0 Register 10 bits o E M om om 0000h CPU Data Page Pointer 1 Register 10 bits 0001h CPU Data Page Pointer 2 Register 10 bits 0002h CPU Data Page Pointer 3 Register 10 bits 0003h CPU Code Segment Pointer Register 0000h 8 bits not directly writeable CPU Multiply Divide Register High Word 0000h CPU Multiply Divide Register Low Word 0000h 242 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 REGISTERS ORDERED BY ADDRESS Cont d nm Em ihe nr ess S Ein ow GPU onea Poner Reger Few sc 19 xml rem t eri convenes ape fon wor reae sm Wacraoo Timer Register eado ooon SOTBUF FEBOh SUME Serial Channel 0 Transmit Buffer ae 0000h write only SORBUF FEB2h Serial Channel 0 Receive Buffer Register XXXXh read only osa res
217. low it This depends on the host interface Figure 12 3 Baudrate deviation between host and ST10R165 SGS THOMSON YA MICROELECTRONICS 203 254 12 Bootstrap Loader ST10R165 Notes 204 254 S7 SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ The internal system reset function provides initial ization of the ST10R165 into a defined default state and is invoked either by asserting a hard ware reset signal on pin RSTIN Hardware Reset Input upon the execution of the SRST instruction Software Reset or by an overflow of the watch dog timer Whenever one of these conditions occurs the mi crocontroller is reset into its predefined default state through an internal reset procedure When a reset is initiated pending internal hold states are cancelled and the current internal access cycle if any is completed An external bus cycle is abort ed except for a watchdog reset see description After that the bus pin drivers and the IO pin drivers are switched off tristate RSTOUT is activated depending on the reset source The internal reset procedure requires 516 CPU clock cycles 25 8 us 20 MHz CPU clock in or Figure 13 1 External Reset Circuitry RSTOUT ST10R165 A 1 H A A J D o o e March 1995 MICROELECTRONICS Chapter 13 SYSTEM RESET der to perform a complete reset sequence This 516 cycle reset sequence is started upon a watch dog timer over
218. lta Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U S A 254 254 SGS THOMSON YA MICROELECTRONICS
219. m SA Seva Channel 0 Baud Rate Generator load Regier 0000n Ecos recon som PEC Chanel o Convo egiser foon Pon FFo2n em Por 0 gh Register Upper tetor PORTO fon Pm e Froon ean Por 1 Hon Register Upper rator PORTH fon 243 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 REGISTERS ORDERED BY ADDRESS Cont d no LEE fiie enm e es rro sem GUPesamSmwswWod von svscon e Frin eon CPU System Contguraton reger 0X zemos e Frin een Consan Value o s Reiter eado ooon omes e Frien orn Consan vawe T s Reiter ead ony FFF 244 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 REGISTERS ORDERED BY ADDRESS Cont d Physical 8 Bit T Reset P5 b FFA2h Port 5 Register read only XXXXh TFR b i DP3 b FFceh E3 Port 3 Direction Control Register 0000h a of Fron ta Ponanegiter bis Om Pe reco en Pore Regs em Xm Note 1 The system configuration is selected during reset 2 Bit WDTR indicates a watchdog timer triggered reset 245 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 16 4 SPECIAL NOTES PEC Pointer Registers The source and destination pointers for the pe ripheral event controller are mapped to a special area within the internal RAM Pointers that are not occupied by the PEC may therefore be used like normal RAM During Power Down mode or any warm reset the PEC p
220. mini are used within this document ALE Address Latch Enable ALU Arithmetic and Logic Unit 4 254 SGS THOMSON TT E vie sors SerROMYGS ASC CAN CISC CMOS CPU EBC ESFR Flash GPR GPT HLL lO PEC PLA RAM RISC ROM SFR SSC XBUS Asynchronous synchronous Serial Controller Controller Area Network License Bosch Complex Instruction Set Computing Complementary Metal Oxide Silicon Central Processing Unit External Bus Controller Extended Special Function Register Non volatile memory that may be electrically erased General Purpose Register General Purpose Timer unit High Level Language Input Output Peripheral Event Controller Programmable Logic Array Random Access Memory Reduced Instruction Set Computing Read Only Memory Special Function Register Synchronous Serial Controller Internal representation of the External Bus Table of Contents 1 Architectural Overview 0000 cece eee ee eee 9 1 1 Basic CPU Concepts and Optimization 0 0 0 cee ee 10 1 2 The On chip System Resources sssusa 0c cee eee 15 1 3 The On chip Peripheral Blocks 0 000 cee cece ee eee 17 1 4 Protected Bis uiui bette hd Ge Mee teres te eoe to alee ee e 20 2 Memory Organization rl eee tee NER I xxu RE EE 21 2 1 Internal RAM and SFR Area 26 n 23 2 2 External Memory Space 0 0060 ee ern 28 2 3 Cro
221. mptied the bottom of stack is reloaded from the external memory and the internal point ers are adjusted accordingly Linear Stack The ST10R165 also offers a linear stack option STKSZ 111b where the system stack may use the complete internal RAM area This allows to provide a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The RAM area that may effectively be consumed by the system stackis defined via the STKUN and STKOV point ers The underflow and overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable bits of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 F000h up to 00 FFFEh the physical sys tem stack must be located within the internal RAM and therefore may only use the address range 00 F600h to 00 FDFEn It is the user s responsibil ity to restrict the system stack to the internal RAM range Note Avoid stack accesses within address range 00 F000h to 00 F5FEh ESFR space and reserved area and within address range 00 FEOO0h and 00 FFFEh SFR space Oth erwise unpredictable results will occur 227 254 15 System Programming ST10R165 STACK OPERATIONS Cont d User Stacks User stacks provide the ability to create task spe cific data stacks and to off load data from the s
222. must be configured for alternate data output ie P3 10 1 and DP3 10 1 Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXDO provided that bits SOR and SOREN are set The receive data input pin RXDO is sampled at 16 times the 174 254 ky 3 rate of the selected baud rate A majority decision of the 7th 8th and 9th sample determines the ef fective bit value This avoids erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at pin RXDO If the start bit proves valid the receive circuit continues sam pling and shifts the incoming data frame into the receive shift register When the last stop bit has been received the con tent of the receive shift register is transferred to the receive data buffer register SORBUF Simulta neously the receive interrupt request flag SORIR is set after the 9th sample in the last stop bit time slot as programmed regardless whether valid stop bits have been received or not The receive circuit then waits for the next start bit 1 to 0 tran sition at the receive data input pin The receiver input pin RXDO P3 11 must be con figured for input ie DP3 112 0 Asynchronous reception is stopped by clearing bit SOREN A currently received frame is completed including the generation of the receive interrupt re quest and an error
223. must be enabled and_may be used by the peripheral logic to control the READY timing in this case The asynchronous READY is less restrictive but requires additional waitstates caused by the inter nal synchronization As the asynchronous READY is sampled earlier see figure above programmed waitstates may be necessary to provide proper bus cycles see also notes on normally ready peripherals below Bus Cycle with active READY tera 1 WS 2 WS extended via READY 1 WS 2 WS ar fX A r SREADY AREADY Evaluation sampling of the READY input SGS THOMSON YA MICROELECTRONICS MCT02237 127 254 7 External Bus Interface ST10R165 READY CONTROLLED BUS CYCLES Cont d A READY signal especially asynchronous READY that has been activated by an external device may be deactivated in response to the trail ing rising edge of the respective command RD or WR Note When the READY function is enabled for a specific address window each bus cycle within this window must be terminated with an active READY signal Otherwise the controller hangs until the next reset A time out function is only provided by the watch dog timer Combining the READY function with prede fined waitstates is advantageous in two cases Memory components with a fixed access time and peripherals operating with READY may be grouped into the same address window The ex ter
224. n be provided by inhibiting interrupts during the respec tive code sequence by disabling and enabling them before and after the sequence The neces sary overhead may be reduced by means of the ATOMIC instruction which allows to lock 1 4 in structions to an unseparable code sequence dur ing which the interrupt system standard interrupts and PEC requests and Class A Traps NMI stack overflow underflow are disabled A Class B Trap illegal opcode illegal bus access etc however will interrupt the atomic sequence since it indicates a severe hardware problem The inter rupt inhibit caused by an ATOMIC instruction gets active immediately ie no other instruction will en ter the pipeline except the one that follows the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense eg MUL is one instruc tion Any instruction type can be used within an unseparable code sequence EXAMPLE ATOMIC 3 The following 3 instructions are locked No NOP required MOV RO 1234h INSTRUCTION Instruction 1 no other instr enters the pipeline MOV R1 5678h Instruction 2 MUL RO R1 Instruction 3 MUL regarded as one instruction MOV R2 MDL This instruction is out of the Scope of the ATOMIC instruction sequence SGS THOMSON YA MICROELECTRONICS 15 12 OVERRIDING THE DPP
225. n of the functions controlled by this bit field A byte register looks like this REG NAME A16h A8h E SFR Reset Value h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Romo quomo am ee epa ap e ap a e e rw rw rw March 1995 235 254 This is advanced information from SGS THOMSON Details are subject to change without notice 16 Register Set ST10R165 16 1 CPU GENERAL PURPOSE REGISTERS GPRS The GPRs form the register bank that the CPU Pointer CP Due to the addressing mechanism works with This register bank may be located an GPR banks can only reside within the internal ywhere within the internal RAM via the Context RAM All GPRs are bit addressable Physical 8 Bit me Reset Ro o o e CP 0 FOh CPU General Purpose Word Register RO UUUUh CP 2 CPU General Purpose Word Register R1 UUUUh R2 CP 4 Foh CPU General Purpose Word Register R2 ms m s rs CPU General Purpose Word Regstrn UUUUR m omes ra GPU General Purpose Word Register uuuun ms GP 10 Fen CPU General Purpose Woro Regserrs f UUUUR me oP 12 Fon OPU General Purpose Word Register UUUUh Coe Fen Fehn FBh CPU General Purpose Word Register R11 UUUUh FCh CPU General Purpose Word Register R12 UUUUh R13 CP 26 FDh CPU General Purpose Word Register R13 UUUUh Ra CP 28 CPU General Purpose Word Register R14 UUUUh R15 CP 30 CPU General Purpose W
226. nable CLKOUT CLKEN 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal Disable Enable Control for Pin BHE Set according to data bus width BYTDIS 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO Internal ROM Enable Set according to pin EA during reset 0 Internal ROM disabled accesses to the ROM area use the external bus 1 Internal ROM enabled This bit is not relevant on the ST10R165 since it does not include internal ROM It should be kept to 0 Segmentation Disable Enable Control SGTDIS 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000h 00 7F FFh 1 Internal ROM area mapped to segment 1 01 0000h 01 7FFFh This bit is not relevant on the ST10R165 since it does not include internal ROM It should be kept to 0 System Stack Size STKSZ M TES Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction The function of bits XPER SHARE VISIBLE WRCFG BYTDIS ROMEN and ROMS is de scribed in more detail in chapter The External Bus Controller 42 254 SGS THOMSON YA MICROELECTRONICS CPU SPECIAL FUNCTION R
227. nal waitstate control logic in this case would activate READY either upon the memory s chip select or with the peripheral s READY output Af ter the predefined number of waitstates the ST10R165 will check its READY line to determine the end of the bus cycle For a memory access it will be low already see example a in the figure above for a peripheral access it may be delayed see example b in the figure above As memories tend to be faster than peripherals there should be no impact on system performance When using the READY function with normally ready peripherals it may lead to erroneous bus cycles if the READY line is sampled too early These peripherals pull their READY output low 128 254 while they are idle When they are accessed they deactivate READY until the bus cycle is complete then drive it low again If however the peripheral deactivates READY after the first sample point of the ST10R165 the controller samples an active READY and terminates the current bus cycle which of course is too early By inserting prede fined waitstates the first READY sample point can be shifted to a time where the peripheral has safely controlled the READY line eg after 2 wait states in the figure above 7 5 CONTROLLING THE EXTERNAL BUS CONTROLLER A set of registers controls the functions of the EBC General features like the usage of interface pins WR BHE segmentation and internal ROM mapping
228. nd ready to be loaded with the next transmit data If SSCTB has been reloaded by the time the cur rent transmission is finished the data is immedi ately transferred to the shift register and the next transmission will start without any additional de lay On the data line there is no gap between the two successive frames Eg two byte transfers would look the same as one word transfer This Figure 10 5 SSC Half Duplex Configuration Master Device 1 Shift Register feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer It is just a matter of software how long atotal data frame length can be This op tion can also be used eg to interface to byte wide and word wide devices on the same serial bus Note Of course this can only happen in multiples of the selected basic data width since it would require disabling enabling of the SSC to reprogram the basic data width on the fly Device 2 Common Transmit Receive Device 3 MCAQ1 965 189 254 SGS THOMSON YA MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165 HALF DUPLEX OPERATION Cont d Port Control The SSC uses three pins of Port 3 to communi cate with the external world Pin P3 13 SCLK serves as the clock line while pins P3 8 MRST Master Receive Slave Transmit and P3 9 MTSR Master Transmit Slave Receive serve as the serial data input output lines The operati
229. nd to this slave The selected slave then switches its MRST line to output until it gets a deselection signal or command The slaves use open drain output on MRST This forms a Wired AND connection The receive line needs an external pullup in this case Corrup tion of the data on the receive line sent by the se lected slave is avoided when all slaves which are not selected for transmission to the master only send ones 1 Since this high level is not actively driven onto the line but only held through the pul lup device the selected slave can pull this line ac tively to a low level when transmitting a zero bit The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave ky 3 SON MICROELECTRONICS After performing all necessary initializations of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer will start After a transfer the alternate data line will al ways remain at the logic level of the last transmit ted data bit When the serial interfaces are enabled the mas ter device can initiate the first data transfer by writ ing the transmit data into register SSCTB This value is copied into the shift register which is as sumed to be empty at this time and the selected f
230. ng allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKOV should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry into an interrupt service routine Then six additional stack word locations are re quired to push IP PSW and CSP for both the in terrupt service routine and the hardware trap serv ice routine More details about the stack overflow trap service routine and virtual stack management are given in chapter System Programming Reset Value FA00h r r r r 7 6 5 4 3 2 1 0 WwW r r Modifiable portion of register STKOV Specifies the lower limit of the internal system stack 54 254 SGS THOMSON YA MICROELECTRONICS CPU SPECIAL FUNCTION REGISTERS Cont d The Stack Underflow Pointer STKUN This non bit addressable register is compared against the SP register after each datapop opera tion from the system stack eg POP and RET in structions and after each addition to the SP regis ter If the content of the SP register is greater than the content of the STKUN register a stack under flow hardware trap will occur Since the least significant bit of register STKUN is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKUN register can only
231. ng memory locations as two subsequent words Single bits are always stored in the speci fied bit position at a word address Bit position 0 is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit ofthe byte at the next odd byte address Bit ad dressing is supported for a part of the Special Function Registers a part ofthe internal RAM and for the General Purpose Registers Figure 2 2 Storage of Words Byte and Bits in a Byte Organized Memory External Memory 00 CO00R X x B M Data Page 2 X X 00 8000h Data Page 1l 00 4000h Data Page 0 00 0000h System Segment 0 64 KByte 00 FFFFh SFR Area 00 FE00h 00 FDOOh 00 F600h Reserved 00 F200h 00 F100h 00 F000h System Segment 0 4 KByte VR02045C Note Byte units forming a single word or a double word must always be stored within the same physical internal external ROM RAM and organizational page segment memory area 22 254 SGS THOMSON YA MICROELECTRONICS 2 1 INTERNAL RAM AND SFR AREA The RAM SFR area is located within data page 3 and provides access to 2 KByte of on chip RAM organized as 1K 16 and to two 512 Byte blocks of Special Function Registers SFRs The internal RAM serves for several purposes Figure 2 3 Internal RAM Area and SFR Areas ar Data Page 3 Data Page 2 00 8000 y Data Page Internal ROM 00 40004
232. nly required for initialization and mode se lection Registers that need to be accessed fre quently are allocated to the standard SFR area wherever possible Note The development tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or exces sive EXTR instructions 27 254 2 Memory Organization ST10R165 2 2 EXTERNAL MEMORY SPACE The ST10R165 is capable of using an address space of up to 16 MByte Only parts of this ad dress space are occupied by internal memory are as All addresses which are not used for on chip RAM or for registers may reference external mem ory locations This external memory is accessed via the ST10R165 s external bus interface Four memory bank sizes are supported Non segmented mode 64KByte with A15 A0 on PORTO or PORT1 2 bit segmented mode 256 KByte with A17 A16 on Port 4 and A15 A0 on PORTO or PORT1 4 bit segmented mode 1 MByte with A19 A16 on Port 4 and A15 A0 on PORTO or PORT1 8 bit segmented mode 16 MByte with A23 A16 on Port 4 and A15 A0 on PORTO or PORT1 Each bank can be directly addressed via the ad dress bus while the programmable chip select signals can be used to select various memory banks The ST10R165 also supports four different bus types Multiplexed 16 bit Bus with address and data on PORTO Default after Reset Multiplexed 8 bit Bus with addres
233. nput is sampled When the re set input signal is active at that time the internal re set condition is prolonged until RSTIN gets inac tive The input RSTIN provides an internal pullup de vice equalling a resistor of 50 KO to 150 KQ the minimum reset time must be determined by the lowest value Simply connecting an external ca pacitor is sufficient for an automatic power on re set see a in figure above RSTIN may also be connected to the output of other logic gates see b in figure above Note Driving RSTIN low for 2 CPU clock cycles is only sufficient for a hardware triggered warm reset A power on reset requires an active time of two reset sequences 1036 CPU clock cycles after a stable clock signal is available about 10 50 ms to allow the on chip oscillator to stabilize 206 254 Software Reset The reset sequence can be triggered at any time via the protected instruction SRST Software Re set This instruction can be executed deliberately within a program eg to leave bootstrap loader mode or upon a hardware trap that reveals a sys tem failure A software reset disregards the configuration of POL 5 POL 0 Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during pro gram execution is will overflow and trigger the re set sequence Other than hardware and software reset the watchdog reset completes a running ex ternal_bus cycle i
234. nterrupt Control Functions in the PSW us ees z regsier ene The Processor Status Word PSW is functionally SAADI TNS sen RIRES SIN eat divided into 2 parts the lower byte of the PSW ba 66 254 IL wy SGS THOMSON YA MICROELECTRONICS INTERRUPT SYSTEM STRUCTURE Cont d PSW FF10h 88h SFR 15 14 18 12 11 4 Interrupt and Trap Functions ST10R165 Reset Value 0000h 0 rw 10 9 8 7 6 5 4 3 2 1 HLD MUL rw rw CPU status flags Described in section The Central Processing Unit Define the current status of the CPU ALU multiplication unit HOLD Enable Enables External Bus Arbitration 0 Busarbitration disabled P6 7 P6 5 may be used for general purpose IO 1 Bus arbitration enabled P6 7 P6 5 serve as BREQ HLDA HOLD resp CPU Priority Level Defines the current priority level for the CPU Fh Highest priority level Oh Lowest priority level Interrupt Enable Control Bit globally enables disables interrupt requests 0 Interrupt requests are disabled 1 Interrupt requests are enabled CPU Priority ILVL defines the current level forthe operation ofthe CPU This bit field reflects the pri ority level of the routine that is currently executed Upon the entry into an interrupt service routine this bit field is updated with the priority level of the re quest that is being serviced The PSW is saved on the system stack before The CPU level deter mines the minimum interru
235. nterrupt input signal When Cl is pro grammed to 01b a positive external transition will set the interrupt request flag Cl 10b selects a negative transition to setthe interrupt request flag and with Cl 11b both a positive and a negative transition will set the request flag When the inter rupt enable bit CRIE is set aninterrupt request for vector CRINT or a PEC request will be generated Note The non maskable interrupt input pin NMI and the reset input RSTIN provide another possibility for the CPU to react on an exter nal input signal NMI and RSTIN are dedi cated input pins which cause hardware traps P3 5 T4IN Auxiliary timer T4 input pin T4CON P3 2 CAPIN GPT2 capture input pin T5CON 78 254 SGS THOMSON YA MICROELECTRONICS EXTERNAL INTERRUPTS Cont d Fast External Interrupts The input pins that may be used for external inter rupts are sampled every 400 ns 20 MHz CPU clock ie external events are scanned and detect ed in timeframes of 400 ns The ST10R165 pro vides 8 interrupt inputs that are sampled every 50 ns 20 MHz CPU clock so external events are captured faster than with standard interrupt inputs EXICON F1COh EOh 1 14 CCxIC See Table SFR EXIxES External Interrupt x Edge Selection Field x 7 0 0 0 Fast external interrupts disabled standard mode 0 1 Interrupt on positive edge rising 1 0 Interrupt on negative edge falling 1 1 Interrupt on any edge rising o
236. nto port data latch P3 1 and pin TGOUT P3 1 must be configured as output by setting direction control bit DP3 1 to 1 If TEOE 1 pin TOUT then outputs the state of TGOTL If TGOE O pin TGOUT can be used as general purpose IO pin In addition T6OTL can be used in conjunction with the timer over underflows as an input for the counter function of the auxiliary timer T5 For this purpose the state of TGOTL does not have to be available at pin TGOUT because an internal con nection is provided for this option Lx o9 f o ew SSS x o9 o3 09m 0 o 3 o eo coon SSS 3 3 emm Note The direction control works the same for core timer T6 and for auxiliary timer T5 Therefore the pins and bits are named Tx 157 254 SGS THOMSON YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT2 Cont d Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bit field T6M in register TECON to 000b In this mode T6 is clocked with the internal system clock divided by a programmable prescaler which is selected by bit field T6l The input frequency frg for timer T6 and its resolution r4 are scaled linear ly with lower clock frequencies fopy as can be seen from the following formula fopu 4 9 lt T6l gt fre rte us __ fceu MHz 4 9 lt T6l gt The timer input frequencies resolution and peri ods which result from the selected prescale
237. ntral Processing Unit ST10R165 sents the value of the bit shifted out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an oper and For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit oper ations with two operands the C flag represents the logical ANDing of the two specified bits e V Flag For addition subtraction and 2 s comple mentation the V flag is always set to 1 if the re sult overflows the maximum range of signed num bers which are representable by either 16 bits for word operations 8000h to 7FFFh or by 8 bits for byte operations 90h to 7Fh other wise the V flag is cleared Note that the result of an integer addition integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result cannot be represented in a word data type otherwise it is cleared Note that a divi sion by zero will always cause an overflow In con trast to the result of a division the result of a mul tiplication is valid regardless of whether the V flag is set to 1 or not Since logical ALU operations cannot produce an invalid result the V flag is cleared by these opera tions The V flag is also used as Sticky Bit
238. o allow recovery from software or hardware fail ure the ST10R165 provides a Watchdog Timer If the software fails to service this timer before an overflow occurs an internal reset sequence will be initiated This internal reset will also pull the RSTOUT pin low which also resets the peripheral hardware which might be the cause for the mal function When the watchdog timer is enabled and the software has been designed to service it regu larly before it overflows the watchdog timer will supervise the program execution as it only will overflow if the program does not progress proper ly The watchdog timer will also time out if a soft ware error was due to hardware related failures Figure 11 1 Watchdog Timer Block Diagram WDT Low Byte WDT Control March 1995 WATCHDOG TIMER This prevents the controller from malfunctioning for longer than a user specified time The watchdog timer provides two registers a read only timer register that contains the current count and a control register for initialization The watchdog timer is a 16 bit up counter which can be clocked with the CPU clock fcpy either divided by 2 or divided by 128 This 16 bit timer is realized as two concatenated 8 bit timers see fig ure below The upper 8 bits of the watchdog timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset on each service access
239. ociated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count di rection Up Down may be programmed via soft ware or may be dynamically altered by a signal at an external control input pin Each overflow under flow of core timer T3 may be indicated on an alter nate output function pin The auxiliary timers T2 Figure 8 2 GPT1 Block Diagram and T4 may additionally be concatenated with the core timer or used as capture or reload registers forthe core timer The current contents of each timer can be read or modified by the CPU by accessing the corre sponding timer registers T2 T3 or T4 which are located in the non bitaddressable SFR space When any of the timer registers is written to by the CPU inthe state immediately before a timer incre ment decrement reload or capture is to be per formed the CPU write operation has priority in or der to guarantee correct results T2EUD H u D Interrupt GPT1 Timer T2 Request CPU Clock 2 nz3 10 T2 T2IN Mode Control CPU Clock Vo n 3 10 Mode iu J Control T3EUD T4 TAIN Mode CPU Clock Control cK 12 nz3 10 140 254 Toggle FF J sour Interrupt Request Interrupt Request MCTO2141 SGS THOMSON YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d 8 1 1 GPT1 Core Timer T3 The core timer T3 is configured and controlle
240. of a cache jump instruction Figure 3 4 Cache Jump Instruction Pipelining 1 Machine Injection Cycle 1st loop iteration ky 3 SON MICROELECTRONICS 3 Central Processing Unit ST10R165 JMPA JMPR JB JBC JNB JNBS is additional ly stored in the cache after having been fetched After each repeatedly following execution of the same cache jump instruction the jump target in struction is not fetched from progam memory but taken from the cache and immediatly injected into the decode stage of the pipeline see figure be low A time saving jump on cacheis always taken after the second and any further occurrence of the same cache jump instruction unless an instruc tion which has the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard in terrupt has been processed during the period of time between two following occurrences of the same cache jump instruction Injection of cached Target Instruction Repeated loop iteration J 35 254 3 Central Processing Unit ST10R165 INSTRUCTION PIPELINING Cont d Particular Pipeline Effects Since up to four different instructions are proc essed simultaneously additional hardware has been spent in the ST10R165 to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of perform ance This extra hardware
241. of in structions Atrap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction Hardware traps always have highest priority and cause im mediate system reaction The software trap func tion is invoked by the TRAP instruction which generates a software interrupt for a specified in terrupt vector For all types of traps the current program status is saved on the system stack External Interrupt Processing Although the ST10R165 does not provide dedicat ed interrupt pins it allows to connect external in terrupt sources and provides several mechanisms to react on external events including standard in puts non maskable interrupts and fast external in terrupts These interrupt functions are alternate port functions except for the non maskable inter rupt and the reset input 59 84 This is advanced information from SGS THOMSON Details are subject to change without notice 4 Interrupt and Trap Functions ST10R165 4 1 INTERRUPT SYSTEM STRUCTURE The ST10R165 provides 28 separate interrupt nodes that may be assigned to 16 priority levels In order to support modular and consistent soft ware design techniques each source of an inter rupt or PEC request is supplied with a separate in terrupt control register and interrupt vector The control register contains the interr
242. oftware watchdog forces the CPU into a predefined active state e IDLE state The clock signal to the CPU itself is switched off while the clocks for the on chip pe ripherals keep running e POWER DOWN state All of the on chip clocks are switched off A transition into an active CPU state is forced by an interrupt if being IDLE or by a reset if being in POWER DOWN mode The IDLE POWER DOWN and RESET states can be entered by particular ST10R165 system control instructions A setof Special Function Registers is dedicated to the functions of the CPU core General System Configuration SYSCON RPOH e CPU Status Indication and Control PSW e Code Access Control IP CSP e Data Paging Control DPPO DPP1 DPP2 DPP3 e GPRs Access Control CP e System Stack Access Control SP STKUN STKOV e Multiply and Divide Support MDL MDH MDC e ALU Constants Support ZEROS ONES SGS THOMSON YA MICROELECTRONICS 3 1 INSTRUCTION PIPELINING The instruction pipeline of the ST10R165 parti tiones instruction processing into four stages of which each one has its individual task 1st gt FETCH In this stage the instruction selected by the In struction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal RAM or external memory 2nd DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched
243. ogress ahardware trap will interrupt any current program execution In turn hardware trap servic es can normally not be interrupted by standard or PEC interrupts Software interrupts are supported by means of the TRAP instruction in combination with an individu al trap interrupt number SON MICROELECTRONICS 1 2 THE ON CHIP SYSTEM RESOURCES The ST10R165 controllers provide a number of powerful system resources designed around the CPU The combination of CPU and these resourc es results in the high performance of the members of this controller family Peripheral Event Controller PEC and Inter rupt Control The Peripheral Event Controller allows to respond to an interrupt request with a single data transfer word or byte which only consumes one instruc tion cycle and does not require to save and restore the machine status Each interrupt source is prior itized every machine cycle in the interrupt control block If PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored inthe PSW regis ter is tested to determine whether a higher priority interrupt is currently being serviced When an in terrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transf
244. ointers are preserved The PEC and its registers are described in chapter Interrupt and Trap Functions GPR Access in the ESFR Area The locations OO FOO0h 00 FO1Eh within the ESFR area are reserved and allow to access the current register bank via short register addressing modes The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces see example below 246 254 ky 3 MOV R5 DP3 GPR access via SFR area EXTR 1 MOV R5 ODP3 GPR access via ESFR area Writing Bytes to SFRs All special function registers may be accessed wordwise or bytewise some of them even bit wise Reading bytes from word SFRs is a non critical operation However when writing bytes to word SFRs the complementary byte of the respec tive SFR is cleared with the write operation SON MICROELECTRONICS SGS THOMSON MICROELECTRONICS ST10R165 User Manual Chapter 17 STA INSTRUCTION SET SUMMARY This chapter briefly summarizes the ST10R165 s instructions ordered by instruction classes This provides a basic understanding of the ST10R165 s instruction set the power and versa tility of the instructions and their general usage A detailed description of each single instruction including its operand data type condition flag set tings addressing modes length number of bytes and object code format is provided in the ST10 Programming Manual for the ST10 Family
245. olled either by software or by the external input pin T3EUD Timer T3 External Up Down Control Input which is the alternate input function of port pin P3 4 These options are selected by bits T3UD and T3UDE in control register T3CON When the up down control is done by software bit T3UDE 0 the count direction can be altered by setting or clearing bit T3UD When T3UDE 1 pin TSEUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as shown in the table below If T3UD 0 and pin T3EUD shows a low level the timer is counting up With a high level at T3EUD the timer is count ing down If T3UD 1 a high level at pin T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is run ning or not When pin T3EUD P3 4 is used as external count direction control input it must be configured as in put ie its corresponding direction control bit DP3 4 must be set to 0 GPT1 Core Timer T3 Count Direction Control Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit TSOTL in control register T3CON T3OTL can also be set or reset by software Bit T3OE Alternate Output Function Enable in regis ter T3CON enables the state of T3OTL to be an al ternate function of the external output pin T3OUT P3 3 For that purpose a
246. olled from peripherals through read accesses to SFRs or bit operations including branch tests on specific control bits in SFRs To ensure proper allocation of peripherals among multiple tasks a portion of the internal memory has been made bit addressable to allow user sem aphores Instructions have also been provided to lock out tasks via software by setting or clearing user specific bits and conditionally branching based on these specific bits It is recommended that bit fields in control SFRs are updated using the BFLDH and BFLDL instruc tions or a MOV instruction to avoid undesired in termediate modes of operation which can occur when BCLR BSET or AND OR instruction se quences are used 231 254 15 System Programming ST10R165 15 9 FLOATING POINT SUPPORT All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and logic instructions allow easy masking and ex tracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the CPU core First the PRI OR instruction aids in normalizing floating point numbers by indicating the position of the first set bit in a GPR This result can the be used to rotate the floating point result accordingly The second feature aids in properly rounding
247. ome effective only after the instruction following the modifying instruction As bit instruc tions BSET BCLR use internal read modify write sequences accessing the whole port in structions modifying the port direction should be followed by an instruction that does not access the same port see example below WRONG BSET DP3 13 change direction of P3 13 to output BSET P3 5 7P3 13 is still input reads pin P3 13 RIGHT BSET DP3 13 the rd mod wr change direction of P3 13 to output NOP any instruction not accessing port 3 BSET P3 5 P3 13 is now output the rd mod wr reads the P3 13 output latch 37 254 3 Central Processing Unit ST10R165 INSTRUCTION PIPELINING Contd a Changing the System Configuration The instruction following an instruction that chang es the system configuration via register SYSCON eg segmentation stack size cannot use the new resources eg stack In these cases an in struction that does not access these resources should be inserted BUSCON ADDRSEL The instruction following an instruction that chang es the properties of an external address area can not access operands within the new area In these cases an instruction that does not access this ad dress area should be inserted Code accesses to the new address area should be made after an ab solute branch to this area Note As a rule instructions that change external bus properties should not be executed
248. on of these pins depends on the selected operating mode master or slave In order to enable the al ternate output functions of these pins instead of the general purpose IO operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output lines are ANDed When an alternate data output line is not used function disabled it is held at a high level allowing IO operations via the port latch The di rection of the port lines depends on the operating mode The SSC will automatically use the correct alternate input or output line of the ports when switching modes The direction of the pins how ever must be programmed by the user as shown in the tables Using the open drain output feature helps to avoid bus contention problems and re duces the need for hardwired hand shaking or slave select lines In this case itis not always nec essary to switch the direction of a port pin The ta ble below summarizes the required values for the different modes and pins Note In the table below an x means that the ac tual value is irrelevant in the respective mode however it is recommended to set these bits to 1 so they are already in the correct state when switching between mas ter and slave mode P3 13 SCLK P3 8 MRST Serial Data In put 190 254 Master Mode Serial Clock P3 13 2 1 DP3 13 1 Serial Clock Output Input P3 9 MTSR Serial Data P3 9 1 DP3 9 1 Serial Data Output
249. on the Z flag indi cates if the second operand was zero or not e E Flag The E flag can be altered by instruc tions which perform ALU or data movement oper ations The E flag is cleared by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set de pending on the value of the source operand to sig nify whether the end of a search table is reached or not If the value of the source operand of an in struction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000h for the word data type or 80h for the byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an interrupt serv ice routine when a multiply or divide ALU opera tion was interrupted before completion Depend ing on the state of the MULIP bit the hardware de 46 254 ky 3 cides whether a multiplication or division must be continued or not after the end of an interrupt serv ice The MULIP bit is overwritten with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This nor mally means that the MULIP flag is cleared again after that Note The MULIP flag is a part of the task environ ment When the interrupting service routine does not return to the interrupted multiply divide instruction ie in
250. ootstrap Loader for flexible system initialization 77 IO Lines With Individual Bit Addressability m ri stated in input mode m Push pull or open drain output mode Different Temperature Ranges m Oto 70 C 40 to 85 C Multifunctional CMOS Process m Low Power CMOS Technology including power saving Idle and Power Down modes m 100 Pin Plastic Quad Flat Pack PQFP Package a EIAJ standard 0 65 mm 25 6 mil lead spacing surface mount technology 3 254 FEATURES Complete Development Support A variety of software and hardware development tools for the SGS THOMSON family of 16 bit microcontrollers is available from experienced international tool suppliers The high quality and reliability of these tools is already proven in many applications and by many users The tool environment for the SGS THOMSON 16 bit microcontrollers includes the following tools m Compilers C MODULA2 FORTH Macro Assemblers Linkers Locaters Library Managers Format Converters Architectural Simulators HLL debuggers Real Time operating systems VHDL chip models In Circuit Emulators based on bondout or standard chips Plug In emulators m Emulation and Clip Over adapters production Sockets m Logic Analyzer disassemblers m Evaluation Boards with monitor programs m industrial boards also for CAN FUZZY PROFIBUS FORTH applications m Network driver software CAN PROFIBUS Abbreviations The following acronyms and ter
251. operation pin T3IN P3 6 must be configured as input ie direction control bit DP3 6 must contain 0 If T3M 0 0 the timer is enabled when TS3IN shows alow level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high lev el in order to enable the timer In addition the tim er can be turned on or off by software using bit T3R The timer will only run if T3R 1 and the gate is active It will stop if either T3R 0 or the gate is inactive Note A transition of the gate signal at pin T3IN does not cause an interrupt request Figure 8 4 Block Diagram of Core Timer T3 in Gated Timer Mode 144 254 Interrupt te egos Fs D TxOUT TxOE MCBO2029 TxOTL SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT1 Cont d Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 001b In counter mode timer T3 is clocked by atransition at the external input pin T3IN which is an alternate function of P3 6 The event causing an increment or decrement of the timer can be a positive a neg ative or both a positive and a negative transition at this pin Bit field T3I in control register T3CON selects the triggering transition see table below 8 General Purpose Timer Units ST10R165 For counter operation pin T3IN P3 6 must be con figured as input ie direction control bit DP3 6 must be 0 The maxim
252. or GPT1 Timers iliis eee 153 9 2 Timer Block GBPI2 uz nlieeesmmt hr teet ox ante Lr mee trn ge ae es 154 8 21 GPT2 Gore Timer T6 unl Lee eue daw en PES rrr xe 156 8 2 2 GPT2 Auxiliary TimMer Si uu bres eee kl eee tbe deh tad kb CUR US 161 8 2 3 Interrupt Control for GPT2 Timers and CAPREL 2 0 000 eee eee 168 9 Asynchronous Synchronous Serial Interface 169 9 1 Asynchronous Operation 0 00 00 e eee 172 9 2 Synchronous Operation 4 wa anen erdei eile hewn eee base Du eed fae users 175 9 3 Hardware Error Detection Capabilities a nuaa aaae 177 9 4 ASCO Baud Rate Generation liiis eh 177 9 5 ASCO Interrupt Control lllllsleseeleee hr 179 10 High Speed Synchronous Serial Interface 181 10 1 Full Duplex Operation 0 0 0 0 00 eee ee eee 186 10 2 Half Duplex Operation liiis hn 188 10 3 Baud Rate Generation 000 ccc sn 190 10 4 Error Detection Mechanisms 00 00 cee nh 192 10 5 SSG lnterrupt Control eo ngs ted eori Uthin eneniue dr usseptUepi adp etse 194 TT Watchdog Timer caso pierre died ee YI urs 195 12 Bootstrap Loader ss sss sive teas eet RRREYVATREIITILxe YT 199 12 1 Entering the Bootstrap Loader 0 cece ess 200 12 2 Memory Configuration after Reset llli 201 12 3 Loading the Startup Code saa aeaaea eee 202 12 4 Exiting Bootstrap Loader Mode 1 0 ee es 202 12
253. or T4l When these fields are pro grammed to X01b interrupt request flags T2IR or T4IR in registers T2IC or T4IC will be set on a pos Pins to be used as External Interrupt Inputs PortPin Original Function Control Register P3 7 T2IN Auxiliary timer T2 input pin T2CON itive external transition at pins T2IN or T4IN re spectively When T2l or T4l are programmed to X10b then a negative external transition will set the corresponding request flag When T2l or TAI are programmed to X11b both a positive and a negative transition will set the request flag In all three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or T4IN When the interrupt enable bits T2IE or T4IE are set a PEC request or an interrupt request for vec tor T2INT or T4INT will be generated Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5ECON is cleared to 0 signal transitions on pin CAPIN will only set the interrupt request flag CRIR in reg ister CRIC and the capture function of register CAPREL is not activated So register CAPREL can still be used as reload register for GPT2 timer T5 while pin CAPIN serves as external interrupt input Bit field Cl in register T5CON selects the effective transition of the external i
254. or WR is active This also includes the program mable read write delay Read chip select is only activated for read cycles write chip select is only activated for write cycles read write chip select is activated for both read and write cycles write cy cles are assumed if any of the signals WRH or WRL gets active These modes save external glue logic when accessing external devices like latches or drivers that only provide a single enable input CSO provides an address chip select directly after reset except for single chip mode when the first instruction is fetched Internal pullup devices hold the selected CS lines high during reset After the end of a reset se quence the pullup devices are switched off and the pin drivers control the pin levels on the select ed CS lines Not selected CS lines will enter the high impedance state and are available for gener al purpose IO ky 3 SON MICROELECTRONICS 7 External Bus Interface ST10R165 The pullup_devices are also active during bus hold while HLDA is active and the respective pin is switched to push pull mode Open drain outputs will float during bus hold In this case external pul lup devices are required or the new bus master is responsible for driving appropriate levels on the CS lines Segment Address versus Chip Select The external bus interface of the ST10R165 sup ports many configurations for the external memo ry By increasing the number of segment addre
255. ord Register R15 UUUUh 236 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 CPU GENERAL PURPOSE REGISTERS Cont d The first 8 GPRs R7 RO may also be accessed tive GPR bytewise Other than with SFRs writing to a GPR The respective halves of the byte accessible reg byte does not affect the other byte of the respec isters receive special names Physical 8 Bit Description Reset Address Address P Value FOh CPU General Purpose Byte Register RLO CPU General Purpose Byte Register RhO CPU General Purpose Byte Register RL1 F3h CPU General Purpose Byte Register RH1 CPU General Purpose Byte Register RL3 CPU General Purpose Byte Register RH3 CPU General Purpose Byte Register RL4 Byte Byte Byte CPU General Purpose Byte Register RH4 Byte Byte Byte FAh CPU General Purpose Byte Register RL5 FBh CPU General Purpose Byte Register RH5 FDh CPU General Purpose Byte Register RH6 FEh CPU General Purpose Byte Register RL7 FFh CP 14 FFh CPU General Purpose Byte Register RH7 CPU General Purpose Byte Register RL6 237 254 SGS THOMSON YA MICROELECTRONICS 16 Register Set ST10R165 16 2 SPECIAL FUNCTION REGISTERS ORDERED BY NAME The following table lists all SFRs which are imple b in column Name SFRs within the Extended mented in the ST10R165 in alphabetical order SFR Space ESFRs are marked with the letter Bit addressable SF
256. ormats 6 Programmable Multiple Priority Interrupt Struc ture ROM not Implemented on the ST10R165 10 254 Instr Ptr Instr Reg MDH MDL Mul Div HW Bit Mask Gen 16 Bit Barrel Shift BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Code Seg Ptr Data Pg Ptrs General Purpose egisters PTT TI Internal STA SGS THOMSON MICROELECTRONICS VR02045B 1 Architectural Overview ST10R165 BASIC CPU CONCEPTS AND OPTIMIZATION Cont d High Instruction Bandwidth Fast Execution Based on the hardware provisions most of the ST10R165 s instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock For example shift and rotate in structions are always processed within one ma chine cycle independent of the number of bits to be shifted Branch multiply and divide instructions normally take more than one machine cycle These instruc tions however have also been optimized For ex ample branch instructions only require an addi tional machine cycle when a branch is taken and most branches taken in loops require no additional machine cycles at all due to the Jump Cache A 32 bit 16 bit division takes 1us a 16 bit 16 bit multiplication takes 0 5 us at 20 MHz CPU clock The instruction c
257. ot require special program ming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the inter nal memory thus allowing a greater portion of the internal RAM to be used for program data or reg ister banking This approach assumes no error but requires a set of control routines see below SON MICROELECTRONICS STACK OPERATIONS Cont d Circular virtual Stack This basic technique allows data to be pushed un til the overflow boundary of the internal stack is reached At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of re turn or pop instructions the upper boundary since the stack empties upward to higher memory loca tions is reached The entries that have been pre viously saved in external memory must now be re stored This is called stack filling Because pro cedure call instructions do not continue to nest in finitely and call and return instructions alternate flushing and filling normally occurs very infre quently If this is not true for a given program envi ronment this techni
258. ow size only those upper address bits of the by one of the four different bus modes independ Start address are used marked R which are not ent of each other and of the bus mode specified in implicitly used for addresses inside the window register BUSCONO Each ADDRSELx registerina The lower bits of the start address marked x way cuts out an address window within which the 8 disregarded Bit field RGSZ Resulting Window Size Relevant Bits R of Start Address A23 A12 4 KByte 8 KByte 16 KByte 32 KByte 64 KByte 128 KByte 256 KByte 512 KByte 1 MByte 2 MByte 4 MByte 8 MByte Reserved 2232027 20320203 02200 x DIDDII DIDI X X DDD XX X IDDI x xxx IDD DDD x x xXXXDDUDIID x x xx X X X IDII x x xx xxx X III xxx x xxx X X ODD xxx x xxx XXX OD x lt x x xX XK KK KK OX mg s SGS THOMSON 889 254 YA MICROELECTRONICS 7 External Bus Interface ST10R165 CONTROLLING THE EXTERNAL BUS CONTROLLER Cont d RPOh F108h 84h 15 14 13 12 11 b ow dee web we ab ee WRCFG Write Configuration Control Reset Value XXh 4 3 2 1 7 5 0 x x gt mm mmm T 0 Pins WR and BHE retain their normal function 1 Pins WR acts as WRL pin BHE acts as WRH 0 0 3 CS lines CS2 CS0 0 1 2 CS lines CS1 CS0 10 No CS lines at all 0 1 No segment address lines at all SALSEL Note RPOH cannot be changed via software but rather allows to check the current configura tion XBUS Periphera
259. pe field BTYP in register BUSCONO is initialized according to POL 7 and POL 6 e bit BUSACTO in register BUSCONO is set to 1 e bit ALECTLO in register BUSCONO is set to 1 BUS SGS THOMSON YA MICROELECTRONICS 13 System Reset ST10R165 e bit ROMEN in register SYSCON will be cleared to 0 e bit BYTDIS in register SYSCON is set according to the data bus width BYTDIS POL 7 The other bits of register BUSCONO and the other BUSCON registers are cleared This default initial ization selects the slowest possible external ac cesses using the configured bus type The Ready function is disabled at the end of the internal sys tem reset When the internal reset has completed the config uration of PORTO PORT1 Port 4 Port 6 and of the BHE signal High Byte Enable alternate func tion of P3 12 depends on the bus type which was selected during reset When any of the external bus modes was selected during reset PORTO and PORT1 will operate in the selected bus mode Port 4 will output the selected number of segment address lines all zero after reset and Port 6 will drive the selected number of CS lines CSO will be 0 while the other active CS lines will be 1 When no memory accesses above 64 K are to be performed segmentation may be disa bled When the on chip bootstrap loader was activated during reset pin TxDO alternate function of P3 10 will be switched to output mode after the recep
260. previous slave will have to toggle their operating mode SSCMS and the direction of their port pins see description above 10 2 HALF DUPLEX OPERATION In a half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and re ceive pins are connected to the one data ex change line serial data may be moved between arbitrary stations Similar to full duplex mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enable its trans mit pin driver the non transmitting devices use open drain out put and only send ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave This allows to detect any cor ruptions on the common data exchange line where the received data is not equal to the trans mitted data SGS THOMSON YA MICROELECTRONICS 10 High Speed Synchronous Serial Interface ST10R165 HALF DUPLEX OPERATION Cont d Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer SSCTB is empty a
261. pt priority level that will be serviced Any request on the same or a lower level will not be acknowledged The current CPU priority level may be changed via software to control which interrupt request sourc es will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC services do not influence the ILVL field in the PSW Hardware traps switch the CPU level to maximum priority ie 15 so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed SGS THOMSON YA MICROELECTRONICS Note The TRAP instruction does not change the CPU level thus software invoked trap serv ice routines may be interrupted by higher re quests Interrupt Enable bit IEN globally enables or disa bles PEC operation and the acceptance of inter rupts by the CPU When IEN is cleared no inter rupt requests are accepted by the CPU When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bits in their associated control registers are globally en abled Note Traps are non maskable and are therefore not affected by the IEN bit 67 254 4 Interrupt and Trap Functions ST10R165 4 2 OPERATION OF THE PEC CHANNELS The ST10R165 s Peripheral Event Controller PEC provides 8 PEC service channels which move a single byte or word between two locations in segment 0 data pages 3 0 This is the fastest
262. pts The External Interrupt Nodes and the Software Nodes use naming conventions that are compatible with the respective ST10F167 interrupt nodes SGS THOMSON YA MICROELECTRONICS 4 Interrupt and Trap Functions ST10R165 INTERRUPT SYSTEM STRUCTURE Cont d Service Request Flag Flag Vector Location Number Note Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction The respective vector location results from multiplying the trap number by 4 4 bytes per entry 61 254 SGS THOMSON YA MICROELECTRONICS 4 Interrupt and Trap Functions ST10R165 INTERRUPT SYSTEM STRUCTURE Cont d The table below lists the vector locations for hard ware traps and the corresponding status flags in register TFR It also lists the priorities of trap serv ice for cases where more than one trap condition might be detected within the same instruction Af ter any reset hardware reset software reset in struction SRST or reset by watchdog timer over flow program execution starts at the reset vector at location 00 0000h Reset conditions have prior ity over every other system activity and therefore have the highest priority trap priority IIl Software traps may be performed from any vector location between 00 0000h and 00 01FCh A serv ice routine entered via a software TRAP instruc tion is always executed on the current CPU priority level which is indicated in bit fi
263. que should not be used be cause of the overhead of flushing and filling The basic mechanism is the transformation of the addresses of a virtual stack area controlled via registers SP STKOV and STKUN to a defined 15 System Programming ST10R165 physical stack area within the internal RAM via hardware This virtual stack area covers all possi ble locations that SP can point to ie 00 F000h through 00 FFFEh STKOV and STKUN accept the same 4 KByte address range The size of the physical stack area within the inter nal RAM that effectively is used for standard stack operations is defined via bitfield STKSZ in register SYSCON see below The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of the stack pointer register SP see table with the complementary most signifi cant bits of the upper limit of the physical stack area 00 FBFEh This transformation is done via hardware see figure below The reset values STKOV FAOOh STKUN FCOOh SP FCOOh STKSZ 000b map the virtual stack area directly to the physical stack area and allow to use internal system stack with out any changes provided that the 256 word area is not exceeded lt STKSZ gt Stack Size Internal RAM Addresses Words Significant Bits of Words of Physical Stack Stack Pointer SP 000b 256 00 FBFEh 00 FA00h Default after Reset SP 8 SP 0 001b O0 FBFER 00 F BOOh SP 7 SP 0 256 64
264. r T5 are not af fected by a capture If T5CLR 1 timer T5 is cleared after the current timer value has been latched into register CAPREL Note Bit T5SC only controls whether a capture is performed or not If T5SC 0 the input pin CAPIN can still be usedto clear timer T5 or as an external interrupt input This interrupt is controlled by the CAPREL interrupt con trol register CHIC Figure 8 18 GPT2 Register CAPREL in Capture Mode Up Down d Auxiliary Timer T5 Edge Select CAPREL Register SGS THOMSON YA MICROELECTRONICS Interrupt TSIR Request Interrupt CRIR Request MCB02044 165 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT2 Cont d GPT2 Capture Reload Register CAPREL in Re load Mode This 16 bit register can be used as a reload regis ter for the core timer T6 This mode is selected by setting bit T6SR 1 in register TeCON The event causing a reload in this mode is an overflow or un derflow of the core timer T6 When timer T6 overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down the value stored in register CAPREL is loaded into timer T6 This will not set the interrupt request flag CRIR as sociated with the CAPREL register However in terrupt request flag T6IR will be set indicating the overflow underflow of T6 Figure 8 19 GPT2 Register CAPREL in Reload Mode CAPREL Register Core Timer T6
265. r falling Note The fast external interrupt inputs are sam pled every 50 ns The interrupt request arbi tration and processing however is executed every 200 ns both 20 MHz CPU clock SGS THOMSON YA MICROELECTRONICS ESFR 4 interrupt and Trap Functions ST10R165 The pins of Port 2 EXOIN EX7IN on P2 8 P2 15 can individually be programmed to this fast inter rupt mode where also the trigger transition rising falling or both can be selected The External In terrupt Control register EXICON controls this fea ture for all 8 pins Reset Value 0000h 5 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Reset Value 00h 7 6 5 4 3 2 1 0 CCx CC rw rw rw rw Note Please refer to the general interrupt control register description for an explanation of the control fields 79 254 4 Interrupt and Trap Functions ST10R165 4 7 TRAP FUNCTIONS Traps interrupt the current execution similar to standard interrupts However trap functions offer the possibility to bypass the interrupt system s pri oritization process in cases where immediate sys tem reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level The ST10R165 provides two different kinds of trapping mechanisms Hardware traps are trig gered by events that occur during program execu tion eg illegal access or undefined opcode soft ware traps are initiated via
266. r op tion when using a 20 MHz CPU clock are listed in the table below This table also applies to the Gat ed Timer Mode of T6 and to the auxiliary timer T5 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits Figure 8 13 Block Diagram of Core Timer T6 in Timer Mode Interrupt s Rogues TxOTL FD TxOUT TxOE MCB02028 GPT2 Timer Input Frequencies Resolution and Periods fcpy 20MHz Timer Input Selection T51l Tel pue s Pus qme se Input Frequency 2 5 1 25 Lu e 5 156 25 78 125 39 06 ud MHz MHz kHz kHz kHz kHz kHz 158 254 SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT2 Cont d Timer 6 in Gated Timer Mode Gated timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to 010b or 011b Bit T6M 0 TGCON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the ex ternal input pin T6IN Timer T6 External Input which is an alternate function of P5 12 8 General Purpose Timer Units ST10R165 If T6M 0 0 the timer is enabled when T6IN shows a low level A high level at this pin stops the timer If T6M 0 1 pin T6IN must have a high lev el in orderto enable the timer In addition the tim er can be turned on or off by software using bit T6R The timer
267. r operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priori ty Further details on peripheral timing are includ ed in the specific sections about each peripheral Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space The following addressing mechanisms al low to access the SFRs eindirect or direct addressing with 16 bit mem addresses it must be guaranteed that the used data page pointer DPPO DPP3 selects data page 3 e accesses viathe Peripheral Event Controller PEC use the SRCPx and DSTPx pointers in stead of the data page pointers e short 8 bit reg addresses to the standard SFR area do not use the data page pointers but di rectly access the registers within this 512 Byte ar ea e short 8 bit reg addresses to the extended ESFR area require switching to the 512 Byte ex tended SFR area This is done via the EXTension instructions EXTR EXTP R EXTS R 17 254 1 Architectural Overview ST10R165 THE ON CHIP PERIPHERAL BLOCKS Cont d Byte write operations to word wide SFRs via in direct or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non ad dressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte
268. r reset the output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx reg isters are located in the ESFR space Each port line has one programmable alternate in put or output function associated with it Each port line has one programmable alternate input or output function associated with it PORTO and PORT1 may be used as the address and data lines when accessing external memory Port 4 outputs the additional segment address bits A23 19 17 A16 in systems where more than 64 KBytes of memory are to be accessed directly Port 6 provides the optional chip select outputs and the bus arbitration lines Port 2 is used for fast external interrupt inputs Port 3 includes alternate input output functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT Port 5 is used for timer control signals Figure 5 2 Output Drivers in Push Pull Mode and in Open Drain Mode Push Pull Output Driver 86 254 External Pullup Open Drain Output Driver MCA01975 SGS THOMSON YA MICROELECTRONICS Alternate Input or Output function of Port If an alternate output function of a pin is to be used the direction of this pin must be pro grammed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin re mains in the high impedance state
269. ration during run time The table below summarizes the alternate func tions of Port 4 depending on the number of select ed segment address lines coded via bitfield SAL SEL Reset Value 00h 7 6 5 4 3 2 1 0 n as no rw r Ww rw rw rw rw rw rw DP4 FFCAh E5h SFR 15 14 13 12 11 10 9 8 ro r py teres Se rk pe Tu de uad Lee ogee TV ae ee war obo ehe Port direction register DP4 bit y T 6 5 4 3 2 1 rw rw rw rw rw rw rw rw Reset Value 00h 0 DPA y 0 Port line P4 y is an input high impedance DP4 y 1 Port line P4 y is an output 102 254 SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 4 Cont d Port 4 Pin Std Function Altern Function Altern Function Altern Function SALSEL 01 64 KB SALSEL 11 256KB SALSEL 00 1MB SALSEL 10 16 MB n purpose IO purpose IO purpose IO purpose IO purpose IO purpose IO purpose IO purpose IO g Address A16 Address A17 purpose IO purpose IO purpose IO purpose IO purpose IO purpose IO Figure 5 12 Port 4 I O and Alternate Functions g Address A16 Address A17 Address A18 Address A19 purpose IO purpose IO purpose IO purpose IO Address A16 Address A17 Address A18 Address A19 Address A20 Address A21 Address A22 Address A23 Alternate Function 3 General Purpose Input Output 103 254 SGS THOMSON YA MIC
270. ress and data lines when accessing external memory while Port 4 outputs the additional segment address bits A23 19 17 A16 in systems where segmentation is used to access more than 64 KBytes of memo ry Port 6 provides optional bus arbitration signals 18 254 BREQ HLDA HOLD and chip select signals Port 2 accepts the fast external interrupt inputs Port 3 includes alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT Port 5 is used for timer control signals All port lines that are not used for these alternate functions may be used as general purpose IO lines Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral com ponents is provided by two serial interfaces with different functionality an Asynchronous Synchro nous Serial Channel ASCO and a High Speed Synchronous Serial Channel SSC They support full duplex asynchronous communi cation at up to 625 KBaud and half duplex syn chronous communication at up to 5 MBaud 2 5 MBaud on the ASCO 20 MHz CPU clock The SSC may be configured so it interfaces with serial ly linked peripheral components Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tun ing For transmission reception and error han dling 3 separate interrupt vectors are provided on channel SSC 4 vectors are provided on channel ASCO
271. ring the last state of an instruction cy cle When the interrupt request flag is set during the first state of an instruction cycle the minimum PEC response time under these conditions is 4 state times 200 ns 20 MHz CPU clock Figure 4 5 Pipeline Diagram for PEC Response Time Pipeline Stage Cycle 1 Cycle 2 Cycle 3 DECODE EXECUTE WRITEBACK i i j i j 0 f F 1 f PEC Response Time 76 254 SGS THOMSON YA MICROELECTRONICS INTERRUPT RESPONSE TIMES Cont d The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer including N e When internal hold conditions between instruc tion pairs N 2 N 1 or N 1 N occur the minimum PEC response time may be extended by 1 state time for each of these conditions eIn case instruction N reads the PSW and instruc tion N 1 has an effect on the condition flags the PEC response time may additionally be extended by 2 state times Any reference to external locations increases the PEC response time due to pipeline related access priorities The following conditions have to be con sidered e Instruction fetch from an external location e Operand read from an external location e Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflic
272. rmined by their bitaddressable control reg isters T2CON and T4CON which are both organ ized identically Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers Reset Value 0000h T4CON FF44h A2h SFR 15 14 11 1 13 12 0 9 8 7 6 5 4 3 2 1 0 T2 UDE T2UD T2R T2M Tal rw rw rw rw rw Reset Value 0000h Txi Timer x Input Selection Depends on the Operating Mode see respective sections 13 12 0 9 8 7 6 5 4 3 2 1 0 T4 UDE T4UD T4R TAM TAI i rw rw rw rw rw TxM Timer x Mode Control Basic Operating Mode Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high Reload Mode Capture Mode Reserved Do not use this combination Timer x Run Bit TxR 0 Timer Counter x stops TxR 1 Timer Counter x runs Timer x Up Down Control Timer x External Up Down Enable Wu For the effects of bits TXUD and TxUDE refer to the direction table see T3 section 146 254 SGS THOMSON YA MICROELECTRONICS TIMER BLOCK GPT1 Cont d Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3 The description and the table apply according ly Timers T2 and T4 in Timer Mode or Gated Tim er Mode When the auxiliary timers T2
273. rocessing Unit Each of these ports and the alternate input and output functions are described in detail in the fol lowing subsections 87 254 5 Parallel Ports ST10R165 5 1 PORT 0 The two 8 bit ports POH and POL represent the If this port is used for general purpose IO the di higher and lower part of PORTO respectively rection of each line can be configured via the cor Both halves of PORTO can be written eg via a responding direction registers DPOH and DPOL PEC transfer without affecting the other half POL FFOOh 80h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POL 7 POL 6 POL 5 POL 4 POL 3 POL 2 POL 1 POL O rw rw rw rw rw rw rw rw POh FF02h 81h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOS uu neg ux kaum rw rw rw rw rw rw rw rw POX y Port data register POH or POL bit y DPOL F100h 80h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOL DPOL DPOL DPOL DPOL DPOL DPOL DPOL 7 6 5 4 3 2 1 0 l l l bu l l l ues rw rw rw rw rw rw rw rw DPOh F102h 81h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOH DPOH DPOH DPOH 7 6 4 0 5 rw rw rw rw rw rw rw rw Port direction register DPOH or DPOL bit y DPOX y 0 Port line POX y is an input high impedance DPOX y 1 Port line POX y is an output 88 294 IL wy SGS THOMSON YA MICROELECTRONICS
274. rogrammable MTTC waitstate pe pus Cycle Segment X Address l l l BUS PO SGS THOMSON YA MICROELECTRONICS I MITC Wait State MCTO2065 125 254 7 External Bus Interface ST10R165 PROGRAMMABLE BUS CHARACTERISTICS Cont d Read Write Signal Delay The ST10R165 allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the time between the fall ing edge of ALE and the falling edge of the com mand Without read write delay the falling edges of ALE and command s are coincident except for propagation delays With the delay enabled the command s become active half a CPU clock 25 ns at fcpy 20 MHz after the falling edge of ALE Figure 7 9 Read Write Delay Segment ALE BUS PO BUS PO Read Write Delay Bus Cycle The read write delay does not extend the memory cycle time and does not slow down the controller in general In multiplexed bus modes however the data drivers of an external device may conflict with the ST10R165 s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write de lay The read write delay is controlled via the RWDCx bits in the BUSCON registers The command s will be delayed if bit RWDCx is 0 default after re set Address l l WR rN N f l
275. rol Bits allow to switch each individual source ON or OFF so it may generate a re quest or not The control bits xxIE are located in the respective interrupt control registers All inter rupt requests may be enabled or disabled general ly via bit IEN in register PSW This control bit is the main switch that selects if requests from any source are accepted or not For a specific request to be arbitrated the respec tive source s enable bit and the global enable bit must both be set The Priority Level automatically selects a certain group of interrupt requests that will be acknowl edged disclosing all other requests The priority level of the source that won the arbitration is com pared against the CPU s current level and the source is only serviced if its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or a lower level An interrupt source that is assigned to level 0 will be disabled and never be serviced The ATOMIC and EXTend instructions auto matically disable all interrupt requests for the du ration of the following 1 4 instructions This is useful eg for semaphore handling and does not require to re enable the interrupt system after the ky 3 4 Interrupt and Trap Functions ST10R165 SON MICROELECTRONICS unseparable instruction sequence see chapter System Programming Interrupt Class Management An interr
276. rresponding baudrate factor with respect to the current CPU clock and initializes the serial interface ASCO accordingly Using this baudrate an identification byte is re turned to the host that provides the loaded data This identification byte is B5h for the ST10R165 When the ST10R165 has entered BSL mode the following configuration is automatically set values that deviate from the normal reset values are marked Watchdog Timer Register SYSCON Disabled OEO0h Context Pointer CP FAO0h Register STKUN FA40h Stack Pointer SP FA40h Register STKOV FAOCh 0 lt gt C Register SOCON 8011h Register BUSCONO acc to startup config Register SOBG acc to 00 byte P3 10 TXDO T DP3 10 T Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TXDO is configured as output so the ST10R165 can return the identification byte The hardware that activates the BSL during re set may be a simple pull down resistor on POL 4 for systems that use this feature upon every hardware reset You may want to use a switcha ble solution via jumper or an external signal for Systems that only temporarily use the bootstrap loader Figure 12 2 Hardware Provisions to Activate the BSL Hora SKO circuit 1 200 254 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H 1 external
277. ruction performs register bank switching and an automatic saving of the previous context The number of implement ed register banks arbitrary sizes is only limited by the size of the available internal RAM Details on using switching and overlapping regis ter banks are described in chapter System Pro gramming Mapping of General Purpose Registers to RAM Addresses Byte Registers Word Register Internal RAM Address CP 1Eh CP 1Ch CP 1Ah CP 18h CP 16h CP 14h CP 12h CP 10h CP 4 OEh CP OCh CP 0Ah CP 4 08h CP 4 06h CP 04h CP 4 02h CP 4 00h SGS THOMSON YA MICROELECTRONICS 25 254 2 Memory Organization ST10R165 INTERNAL RAM AND SFR AREA Cont d PEC Source and Destination Pointers The 16 word locations in the internal RAM from 00 FCEOh to OO FCFEh just below the bit ad dressable section are provided as source and destination address pointers for data transfers on the eight PEC channels Each channel uses a pair of pointers stored in two subsequent word loca tions with the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher word address x 7 0 Whenever a PEC data transfer is performed the pair of source and destination pointers which is Figure 2 4 Location of the PEC Pointers OO FCFE OO FCFC PEC Source and Destination Pointers OO FCE2 OO FCEO
278. ry area each bank pointer is then assigned Thus upon entry into a new task the appropriate bank pointer is used as the operand for the SCXT switch context instruction Upon exit from a task a simple POP instruction to the context pointer CP restores the previous task s register bank 15 6 PROCEDURE CALL ENTRY AND EXIT To support modular programming a procedure mechanism is provided to allow coding of fre quently used portions of code into subroutines The CALL and RET instructions store and restore the value of the instruction pointer IP on the sys tem stack before and after a subroutine is execut ed Procedures may be called conditionally with in structions CALLA or CALLI or be called uncondi tionally using instructions CALLR or CALLS Note Any data pushed onto the system stack dur ing execution of the subroutine must be popped before the RET instruction is exe cuted SGS THOMSON YA MICROELECTRONICS PROCEDURE CALL ENTRY AND EXIT Cont d Passing Parameters on the System Stack Parameters may be passed via the system stack through PUSH instructions before the subroutine is called and POP instructions during execution of the subroutine Base plus offset indirect address ing also permits access to parameters without popping these parameters from the stack during execution of the subroutine Indirect addressing provides a mechanism of accessing data refer enced by data pointers which are passed to the
279. s and data on PORTO POL Demultiplexed 16 bit Bus with address on PORT1 and data on PORTO Demultiplexed 8 bit Bus with address on PORT1 and data on POL Memory model and bus mode are selected during reset by pin EA and PORTO pins For further de tails about the external bus configuration and con 28 254 trol please refer to chapter The External Bus In terface External word and byte data can only be accessed via indirect or long 16 bit addressing modes using one of the four DPP registers There is no short addressing mode for external operands Any word data access is made to an even byte address For PEC data transfers the external memory in segment 0 can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single bit storage and therefore it is not bit addressable 2 3 CROSSING MEMORY BOUNDARIES The address space of the ST10R165 is implicitly divided into equally sized blocks of different gran ularity and into logical memory areas Crossing the boundaries between these blocks code or da ta or areas requires special attention to ensure that the controller executes the desired opera tions Memory Areas are partitions of the address space that represent different kinds of memory if provided at all These memory areas are the in ternal RAM SFR area and the external memory Accessing subsequent data locations that b
280. s each The Address Latch Enable signal ALE controls external address latches that provide a stable address in multiplexed bus modes During reset and Hold mode an internal pull down ensaves an inactive Low level on ALE output March 1995 MICROELECTRONICS Chapter 6 DEDICATED PINS The External Read Strobe RD controls the output drivers of external memory or peripherals when the ST10R165 reads data from these external devices During reset and during Hold mode an internal pullup ensures an inactive high level on the RD output The External Write Strobe WR WRL controls the data transfer from the ST10R165 to an external memory or peripheral device This pin may either provide a general WR signal activated for both byte and word write accesses or specifically control the low byte of an external 16 bit device WRL together with the signal WRH alternate function of P3 12 BHE During reset and during Hold mode an internal pullup ensures an inactive high level on the WR WRL output The Ready Input READY receives a control signal from an external memory or peripheral device that is used to terminate an external bus cycle provided that this function is enabled for the current bus cycle READY may be used as synchronous READY or may be evaluated asynchronously The External Access Enable Pin EA determines if the ST10R165 after reset starts fetching code from the internal ROM area EA 1 or via the external
281. s non bit addressable register represents the low order 16 bits of the 32 bit re sult For long divisions the MDL register must be loaded with the low order 16 bits of the 32 bit divi dend before the division is started After any divi sion register MDL represents the 16 bit quotient Reset Value 0000h 7 6 5 4 3 2 1 0 MDL FEOEh 07h SFR 15 14 13 12 11 10 9 8 Reset Value 0000h 7 6 5 4 3 2 1 0 56 254 SGS THOMSON YA MICROELECTRONICS CPU SPECIAL FUNCTION REGISTERS Cont d Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted be fore its completion and when a new multiply or di vide operation is to be performed within the inter rupt service routine register MDL must be saved along with registers MDH and MDC to avoid erro neous results A detailed description of how to use the MDL reg ister for programming multiply and divide algo rithms can be found in chapter System Program ming The Multiply Divide Control Register MDC This bit addressable 16 bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or di vide operation Register MDC is updated by
282. s the address of the instruction following the one which caused the trap Illegal Instruction Access Trap Whenever a branch is made to an odd byte ad dress the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is the illegal odd target address of the branch instruction Illegal External Bus Access Trap Whenever the CPU requests an external instruc tion fetch data read or data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap However the ST10R165 being a romless mi crocontroller an external bus must be defined and such a trap should never occur 83 254 4 Interrupt and Trap Functions ST10R165 Notes 84 254 O or SGS THOMSON n MICROELECTRONICS qr SGS THOMSON ST10R165 User Manual SZA In order to accept or generate single external con trol signals or parallel data the ST10R165 pro vides up to 77 parallel IO lines organized into sev en 8 bit IO ports PORTO made of POH and POL PORT1 made of P1H and P1L Port 2 Port 4 Port 6 one 15 bit IO port Port 3 and one 6 bit input port Port 5 These port lines may be used for general purpose Input Output controlled via software or may be used implicitly
283. ss lines the ST10R165 can address a linear address space of 256 KByte 1 MByte or 16 MByte This al lows to implement a large sequential memory ar ea and also allows to access a great number of external devices using an external decoder By increasing the number of CS lines the ST10R165 can access memory banks or peripherals without external glue logic These two features may be combined to optimize the overall system perform ance Enabling 4 segment address lines and 5 chip select lines eg allows to access five memory banks of 1 MByte each So the available address space is 5 MByte without glue logic Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmen tation disabled 121 254 7 External Bus Interface ST10R165 7 38PROGRAMMABLE BUSCHARACTERISTICS Important timing characteristics of the external bus interface have been made user programma ble to allow to adapt it to a wide range of different external bus and memory configurations with dif ferent types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE Control defines the ALE signal length and the address hold time after its falling edge Memory Cycle Time extendable with 1 15 waitstates defines the allowable access time e Memory Tri State Time extendable with 1 wait Figure 7 5 Programmable External Bus Cycle stat
284. ssing Memory Boundaries 0 00 c eee en 28 3 Central Processing Unit 000 ce eee ee ee 31 3 4 Instruction Pipelining sree 0a Coa eee ied bate ee o REGN ed PAGS 33 3 2 Bit Handling and Bit Protection llle eh 39 3 3 Instruction State Times 0 00 00 a a e a i eae 40 3 4 CPU Special Function Registers aaa ccc eee ees 41 4Interrupt and Trap Functions 00000 e eee eee 59 4 1 Interrupt System Structure 2 00 00 cc en 60 4 2 Operation of the PEC Channels 00 00 cece eee tenes 68 4 3 Prioritization of Interrupt and PEC Service Requests 0 000 cee ee eee 71 4 4 Saving the Status during Interrupt Service 0 0 0 liess 72 4 5 Interrupt Response Times 0 0 0 0 ee ete 74 4 5 1 PEC Response TimeS 000 e eee enn 76 46 External Interrupts 0 0 ce eee 78 47 gt Trap FUNCUONS cec eee iat EOM ep De eter reg 80 5 Parallel POIIS cu sees eeee eee yee eee ee ve a ee ne 85 bil e PON Ongea ose Ae he A ane etait aL RR Lote SR be SUI AER ERIGI a 88 5 1 1 Alternate Functions of PORTO ssssssseeseese ee 89 5 2 FIP OM M eroe aa Ne see UL aie ioehbet ob edet et fuste Ne eo et ident Solent ast tole ats 91 5 2 1 Alternate Functions of PORT1 0 000 cece s 92 SS SPOLL2 noi oce eU Bep pel pi lees m Bes befters i IRA EROR a alan Dor edie 94 5 3 1 Alternate Functions of Port2 1 0 ees 94 S M oic PEL 97 5 4
285. stem initialization etc The Bootstrap Loader may be used to load the complete application software into ROMless sys tems it may load temporary software into com plete systems for testing or calibration it may also be used to load a programming routine for exter nal EPROM or Flash memories The BSL mechanism may be used for standard system startup as well as only for special occa sions like system maintenance firmware update or end of line programming or testing 32 bytes user software 1 BSL initialization time gt 2ms fCPU 20 MHz 2 Zero byte 1 start bit eight 0 data bits 1 stop bit sent by host 3 Identification byte sent by ST10R165 4 32 bytes of code data sent by host 5 Internal Boot ROM March 1995 199 254 This is advanced information from SGS THOMSON Details are subject to change without notice 12 Bootstrap Loader ST10R165 12 1 ENTERING THE BOOTSTRAP LOADER The ST10R165 enters BSL mode if pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated inde pendent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM no part of the memory area is required for this After entering BSL mode and the respective initial ization the ST10R165 scans the RXDO line to re ceive a zero byte ie one start bit eight 0 data bits and one stop bit From the duration of this zero byte it calculates the co
286. subroutine In addition two instructions have been implement ed to allow one parameter to be passed on the System stack without additional software over head The PCALL push and call instruction first pushes the reg operand and the IP contents onto the sys tem stack and then passes control to the subrou tine specified by the caddr operand When exiting from the subroutine the RETP re turn and pop instruction first pops the IP and then the reg operand from the system stack and re turns tothe calling program Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of the CALLS call inter segment subrou tine instruction This instruction preserves both the CSP code segment pointer and IP on the System stack Upon return from the subroutine a RETS return from inter segment subroutine instruction must be used to restore both the CSP and IP This en ky 3 SON MICROELECTRONICS 15 System Programming ST10R165 sures that the next instruction after the CALLS in struction is fetched from the correct segment Note Itis possible to use CALLS within the same segment but still two words of the stack are used to store both the IP and CSP Providing Local Registers for Subroutines For subroutines which require local storage the following methods are provided Alternate Bank of Registers Upon entry into a subroutine it is possible to specify a new set of lo c
287. supported by regis ters STKOV and STKUN see respective descrip tions below The SP register can be updated via any instruc tion which is capable of modifying an SFR Note Due to the internal instruction pipeline a POP or RETURN instruction must not im mediately follow an instruction updating the SP register Reset Value FCOOh 53 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d The Stack Overflow Pointer STKOV This non bit addressable register is compared against the SP register after each operation which pushes data onto the system stack eg PUSH and CALL instructions or interrupts and af ter each substraction from the SP register If the content of the SP register is less than the content of the STKOV register a stack overflow hardware trap will occur Since the least significant bit of register STKOV is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKOV register can only contain values from FOOOh to FFFEh The Stack Overflow Trap entered when SP STKOV may be used in two different ways e Fatal error indication treats the stack overflow as a system error through the associated trap service routine Under these circumstances data STKOV FE14h 0Ah SFR 15 14 18 12 11 10 9 8 in the bottom of the stack may have been overwrit ten by the status information stacked upon servic ing the stack overflow trap e Automatic system stack flushi
288. t are completed before entering the service routine The actual execution time for these instructions eg waitstates therefore influences the interrupt response time In the figure below the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round dur ing cycle 2 In cycle 3a TRAP instruction is inject ed into the decode stage of the pipeline replacing instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected TRAP instruction save PSW IP and CSP if seg mented mode and fetches the first instruction I1 from the respective vector location All instructions that entered the pipeline after set ting of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine The minimum interrupt response time is 5 states 250 ns 20 MHz CPU clock This requires pro gram execution with the fastest bus configuration 16 bit demultiplexed no wait states no external operand read requests and setting the interrupt re quest flag during the last state of an instruction cy cle When the interrupt request flag is set during the first state of an instruction cycle the minimum interrupt response time under these conditions is 6 state times 300 ns 20 MHz CPU clock The interrupt response time is increased by all de lays of the instructions in the pipeline that are exe cu
289. t written by data operations It is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP instruction the CSP register is automatically set to ze ro Reset Value 0000h 7 6 5 4 3 2 1 0 18 12 0 9 8 when segmentation is disabled SGS THOMSON YA MICROELECTRONICS 47 254 3 Central Processing Unit ST10R165 CPU SPECIAL FUNCTION REGISTERS Cont d Figure 3 5 Addressing via the Code Segment Pointer Code Segment 255 ps 294 FE 0000h 4 H 15 CSP Register E 01 0000h 24 20 18 bit Physical Code Address 00 0000h i H H H a a A i Note When segmentation is disabled the IP value is used directly as the 16 bit address 48 254 S7 SGS THOMSON YA MICROELECTRONICS CPU SPECIAL FUNCTION REGISTERS Cont d The Data Page Pointers DPPO DPP1 DPP2 DPP3 These four non bit addressable registers select up to four different data pages being active simulta neously at run time The lower 10 bits of each DPP register select one of the 1024 possible 16 Kbyte data pages while the upper 6 bits are re served for future use The DPP registers allow to access the entire memory space in pages of 16 Kbytes each DPPO FEOO0h 00h SFR 15 14 1 11 10 9 8 3 12 3 Central Processing Unit ST10R165 The DPP registers are impl
290. t timer counter e 32 bit Timer Counter If both a positive and a negative transition of TGOTL is used to clock the auxiliary timer this timer is clocked on every over flow underflow of the core timer T6 Thus the two timers form a 32 bit timer e 33 bit Timer Counter If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T6 This configuration forms a 33 bit timer 16 bit core timer T6OTL 16 bit auxiliary timer GPT2 Auxiliary Timer Counter Mode Input Edge Selection Triggering Edge for Counter Increment Decrement Any transition rising or falling edge on T5IN Positive transition rising edge of output toggle latch T6OTL Negative transition falling edge of output toggle latch T6OTL Any transition rising or falling edge of output toggle latch T6OTL SGS THOMSON YA MICROELECTRONICS 163 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT2 Cont d The count directions of the two concatenated tim T6 can operate in timer gated timer or counter ers are not required to be the same This offers a mode in this case wide variety of different configurations Figure 8 17 Concatenation of Core Timer T6 and Auxiliary Timer T5 s Interrupt Core Timer Ty Request Up Down MCBO2034 eo Auxiliary Timer Tx me L E T6EOUT P3 1 x 5 y 6 Note Line only affected by over
291. tch Data Port Latch Data Last value 4 Last value 4 Other Port Output Pins Port Latch Data Alternate Function Port Latch Data Alternate Function Note 1 High if EINIT was executed before entering Idle or Power Down mode Low otherwise 2 For multiplexed buses with 8 bit data bus 3 For demultiplexed buses 4 The CS signal that corresponds to the last address remains active low all other enabled CS signals remain inactive high sy SGS THOMSON 219291 YA MICROELECTRONICS 14 Power Reduction Modes ST10R165 Notes 220 254 S7 SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ To aid in software development a number of fea tures has been incorporated into the instruction set of the ST10R165 including constructs for modularity loops and context switching In many cases commonly used instruction sequences have been simplified while providing greater flexi bility The following programming features help to fully utilize this instruction set 15 1 INSTRUCTIONS PROVIDED AS SUBSETS OF INSTRUCTIONS In many cases instructions found in other micro controllers are provided as subsets of more pow erful instructions in the ST10R165 This allows the same functionality to be provided while decreas ing the hardware required and decreasing decode complexity In order to aid assembly program ming these instructions familiar from other micro MICROELECTRONICS Chapter 15 SYSTE
292. tched to the line labeled Alternate Data Out put via a multiplexer The alternate data can be the 16 bit intrasegment address or the 8 16 bit data information The incoming data on PORTO is Figure 5 4 Block Diagram of a PORTO Pin Write DPOH y DPOL y Direction Latch Alternate Direction read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the exter nal bus modes are disabled the contents of the di rection register last written by the user becomes active The figure below shows the structure of a PORTO pin Read DPOH y DPOL y Write POH y POL y Port Output Latch Read POH y POL y I n t e r n q 90 254 Alternate Function Enable Alternate Data Output Output Buffer MCB02251 SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 5 2 PORT 1 The two 8 bit ports P1H and P1L represent the If this port is used for general purpose IO the di higher and lower part of PORT1 respectively rection of each line can be configured via the cor Both halves of PORT1 can be written eg via a responding direction registers DP1H and DP1L PEC transfer without affecting the other half P1L FF04h 82h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1L 7 P1L 6 P1L 5 P1L 4 P1L 3 P1L 2 P1L 1 P1L 0 7 rw rw rw
293. tectural Overview ST10R165 BASIC CPU CONCEPTS AND OPTIMIZATION Cont d A set of consistent flags is automatically updated in the PSW after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also pre served automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also com puted in the central ALU A 16 bitbarrel shifter provides multiple bit shifts in a single cycle Rotates and arithmetic shifts are also supported Extended Bit Processing and Peripheral Con trol A large number of instructions has been dedicated to bit processing These instructions provide effi cient control and testing of peripherals while en hancing data manipulation Unlike other microcon trollers these instructions provide direct access to two operands in the bit addressable space without requiring to move them into temporary flags The same logical instructions available for words and bytes are also supported for bits This allows the user to compare and modify a control bit for a peripheral in one instruction Multiple bit shift in structions have been included to avoid long in struction streams of single bit shift operations These are also performed in a single machine cy cle In addition bit field instructions have be
294. ted before entering the service routine includ ing N Figure 4 4 Pipeline Diagram for Interrupt Response Time Pipeline Stage D Ne ve DECODE EXECUTE WRITEBACK N 2 N 3 Interrupt Response Time TRAP ED p 4 a a 5 a 5 i 4 5 a 4 4 J 74 254 SGS THOMSON YA MICROELECTRONICS INTERRUPT RESPONSE TIMES Cont d e When internal hold conditions between instruc tion pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW or the SP the mini mum interrupt response time may be extended by 1 state time for each of these conditions eIn case instruction N reads the PSW and instruc tion N 1 has an effect on the condition flags the interrupt response time may additionally be ex tended by 2 state times Any reference to external locations increases the interrupt response time due to pipeline related ac cess priorities The following conditions have to be considered e Instruction fetch from an external location e Operand read from an external location e Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays e The worst case interrupt response time including external accesses will occur when instructions N N 1 and N 2 are execute
295. ter STKOV Non Maskable Interrupt Flag A negative transition falling edge has been detected on pin NMI Note The trap service routine must clear the respective trap flag otherwise a new trap will be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware 81 254 SGS THOMSON YA MICROELECTRONICS 4 Interrupt and Trap Functions ST10R165 TRAP FUNCTIONS Cont d The reset functions hardware software watch dog may be regarded as a type of trap Reset functions have the highest system priority trap priority III Class A traps have the second highest priority trap priority Il on the 3rd rank are class B traps so a class A trap can interrupt a class B trap If more than one class A trap occur at a time they are prioritized internally with the NMI trap on the highest and the stack underflow trap on the lowest priority All class B traps have the same trap priority trap priority I When several class B traps get active at a time the corresponding flags in the TFR register are set and the trap service routine is entered Since all class B traps have the same vector the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine A class A trap occurring during the execution of a class B trap service routine will be serviced imme diately During the execution of a class
296. ternal Address Bus Mode foo 8 bit Data Demultiplexed Addresses 8 bit Data Multiplexed Addresses 16 bit Data Demultiplexed Addresses 16 bit Data Multiplexed Addresses 114 254 SGS THOMSON YA MICROELECTRONICS EXTERNAL BUS MODES Cont d Multiplexed Bus Modes In the multiplexed bus modes the 16 bit intra seg ment address as well as the data use PORTO The address is time multiplexed with the data and has to be latched externally The width of the required latch depends on the selected data bus width ie an 8 bit data bus requires a byte latch the ad dress bits A15 A8 on POH do not change while POL multiplexes address and data a 16 bit data bus requires a word latch the least significant ad dress line AO is not relevant for word accesses The upper address lines An A16 are perma nently output on Port 4 if segmentation is ena bled and do not require latches The EBC initiates an external access by generat ing the Address Latch Enable signal ALE and then placing an address on the bus The falling edge of ALE triggers an external latch to capture Figure 7 2 Multiplexed Bus Cycle 7 External Bus Interface ST10R165 the address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates the respective command signal RD WR WRL WRH Data is driven onto the bus either by the EBC for write cycles or by the ext
297. tes Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The upper half of each register block is bit ad dressable so the respective control status bits can directly be modified or checked using bit ad dressing When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing an Extend Register EXTR instruction is required before to switch the short addressing mechanism from the standard SFR area to the Extended SFR area This is not required for 16 bit and indirect address es The GPRs R15 RO are duplicated ie they are accessible within both register blocks via short 2 4 or 8 bit addresses without switching Example EXTR 4 Switch to ESFR area for the next 4 instructions SGS THOMSON YA MICROELECTRONICS 2 Memory Organization ST10R165 MOV ODP2 datal6 ODP2 uses 8 bit reg addressing BFLDL DP6 mask data8 Bit addressing for bit fields BSET DP1H 7 Bit addressing for single bits MOV T8REL R1 I8REL uses 16 bit address R1 is duplicated and also accessible via the ESFR mode EXTR is not required for this access The scope of the EXTR 4 instruction ends here MOV T8REL R1 I8REL uses 16 bit address R1 is duplicated j and does not require switching In order to minimize the use of the EXTR instruc tions the ESFR area mostly holds registers which are mai
298. the internal stack Once the transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the exe cution time required by the trap routines affects user programs The following procedure initializes the controller for usage of the circular stack mechanism e Specify the size of the physical system stack area within the internal RAM bitfield STKSZ in register SYSCON e Define two pointers which specify the upper and lower boundary of the external stack These val ues are then tested in the stack underflow and overflow trap routines when moving data e Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six words for the reserved space to store two inter rupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated space After exiting from the trap procedure the SGS THOMSON YA MICROELECTRONICS 15 System Programming ST10R165 internal stack will wrap around to the top of the in ternal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack is e
299. this clock signal may also be used to drive the emulator device However if a crystal is used the emulator device s oscillator can use this crystal only if atleast XTAL2 ofthe original device is dis connected from the circuitry the output XTAL2 will still be active in Adapt Mode Bootstrap Loader Mode Pin POL 4 BSL activates the on chip bootstrap loader when low during reset The bootstrap load er allows to move the start code into the internal RAM of the ST10R165 via the serial interface ASCO The ST10R165 will remain in bootstrap loader mode until a hardware reset with POL 4 high or a software reset Default The ST10R165 starts fetching code from location 00 0000h the bootstrap loader is off SON MICROELECTRONICS APPLICATION SPECIFIC INITIALIZATION ROUTINE Cont d External Bus Type Pins POL 7 and POL 6 BUSTYP select the exter nal bus type during reset This allows to configure the external bus interface of the ST10R165 even for the first code fetch after reset The two bits are copied into bit field BTYP of register BUSCONO POL 7 controls the data bus width while POL 6 controls the address output multiplexed or demul tiplexed This bit field may be changed via soft ware after reset if required PORTO and PORT are automatically switched to the selected bus mode In multiplexed bus modes PORTO drives both the 16 bit intra segment ad dress and the output data while PORT1 remains in high impedance st
300. tion of each All Port 2 lines P2 15 P2 8 can serve as Fast line can be configured via the corresponding di External Interrupt inputs EX7IN EXOIN rection register DP2 Each port line can be switched into push pull or open drain mode via the open drain control register ODP2 P2 FFCOh EOh SFR Reset Value 00 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t yb x Na Sp x cq 1 p tgp d Poss pasa rasa rea Per vas za we kee Lehes Sp UE M T semen DENN at rw rw rw rw rw rw rw rw E P2 y Port data register P2 bit y DP2 FFC2h E1h SFR Reset Value 00 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 TOY I7 TV NEG T Te CREER eee DP2 rw rw rw rw rw rw rw rw s i Port direction register DP2 bit y DP2 y 0 Port line P2 y is an input high impedance DP2 y 1 Port line P2 y is an output ODP2 F1C2h E1h ESFR Reset Value 00 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP2 ODP2 ODP2 ODP2 14 10 9 8 rw rw rw rw rw rw rw rw E x i i i Port 2 Open Drain control register bit y ODP2 y 0 Port line P2 y output driver in push pull mode ODP2 y 1 Port line P2 y output driver in open drain mode 94 254 o GI SGS THOMSON MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 2 Cont d The table below summarizes the alternate functions of Port 2 Fast External Interrupt 0 Input Fast External Interrupt 1 Input Fast External Interrupt 2 Input Fast External Interrupt 3 Inp
301. tion of the zero byte All other pins remain in the high impedance state until they are changed by software or peripheral operation 209 254 13 System Reset ST10R165 13 7 APPLICATION SPECIFIC INITIALIZATION ROUTINE After the internal reset condition is removed the ST10R165 fetches the first instruction from loca tion 00 0000h which is the first vector in the trap interrupt vector table the reset vector 4 words lo cations 00 0000h through 00 0007h are provided in this table to start the initialization after reset As a rule this location holds a branch instruction to the actual initialization routine that may be located anywhere in the address space Note When the Bootstrap Loader Mode was acti vated during a hardware reset the ST10R165 does not fetch instructions from location 00 0000h but rather expects data via serial interface ASCO After reset it may be desirable to reconfigure the external bus characteristics because the SY SCON register is initialized during reset to the slowest possible memory configuration To decrease the number of instructions required to initialize the ST10R165 each peripheral is pro grammed to a default configuration upon reset but is disabled from operation These default con figurations can be found in the descriptions of the individual peripherals During the software design phase portions of the internal memory space must be assigned to regis ter banks and system st
302. tions processed by the CPU may diverge from the se quence of the corresponding external memory ac cesses performed by the EBC due to the prede fined priority of external memory accesses 1st Write Data 2nd Fetch Code 3rd Read Data a Controlling Interrupts Software modifications implicit or explicit of the PSW are done in the execute phase of the respec tive instructions In order to maintain fast interrupt responses however the current interrupt prioriti zation round does not consider these changes ie an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions Time criti cal instruction sequences therefore should not be gin directly after the instruction disabling inter rupts as shown in the following example INT OFF BCLR IEN globally disable interrupts Igi non critical instruction CRIT 1ST In begin of uninterruptable critical Sequence SGS THOMSON YA MICROELECTRONICS 3 Central Processing Unit ST10R165 CRIT LAST lux end of uninterruptable critical Sequence INT ON BSET IEN globally r nable interrupts Note The described delay of 1 instruction also ap plies for enabling the interrupts system ie no interrupt requests are acknowledged un til the instruction following the enabling in struction a Initialization of Port Pins Modifications of the direction of port pins input or output bec
303. tive channel will always move data from the same source to the same des tination Note The reserved combination 11 is changed to 10 by hardware However it is not recom mended to use this combination The PEC Transfer Count Field COUNT controls the action of a respective PEC channel where the 4 Interrupt and Trap Functions ST10R165 content of bit field COUNT at the time the request is activated selects the action COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all The table below summarizes how the COUNT field itself the interrupt requests flag IR and the PEC channel action depends on the previous con tent of COUNT The PEC transfer counter allows to service a specified number of requests by the respective PEC channel and then when COUNT reaches 00h activate the interrupt service routine which is associated with the priority level After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced COUNT COUNT Bis PEC Action of PEC Channel and Comments FFh FFh Move a Byte Word Continuous transfer mode ie COUNT is not modified FEh 02h FDh 01h E Move a Byte Word and decrement COUNT 01h 00h T Move a Byte Word Leave request flag set which triggers another request 00h 00h an No action Activate interrupt service routine rather than PEC channel Note After PEC Service SGS
304. to identify exception conditions during runtime m HLL support for semaphore operations and efficient data access Integrated On chip Memory m 2 KByte internal RAM for variables register banks system stack and code External Bus Interface m Multiplexed or configurations m Segmentation capability and chip select signal generation m 8 bit or 16 bit data bus m Programmable Bus configuration for five programmable address areas non multiplexed bus 16 Priority Level Interrupt System m 28 interrupt nodes with separate interrupt vectors m 300 500 ns typical maximum interrupt latency in case of internal program execution m Fast external interrupts SGS THOMSON YA MICROELECTRONICS 8 Channel Peripheral Event Controller PEC m Interrupt driven single cycle data transfer m Transfer count option standard CPU interrupt after a programmable number of PEC transfers m Eliminates overhead of saving and restoring System state for interrupt requests Intelligent On chip Peripheral Subsystems m 2 Multifunctional General Purpose Timer Units GPT1 three 16 bit timers counters 400 ns maximum resolution GPT2 two 16 bit timers counters 200 ns maximum resolution m Asynchronous Synchronous Serial Channel USART with baud rate generator parity framing and overrun error detection m High Speed Synchronous Serial Channel programmable data length and shift direction m Watchdog Timer with programmable time intervals m B
305. transmit data while the other clock edge is used to latch in receive data Bit SS CPH selects the leading edge or the trailing edge for each function Bit SSCPO selects the level of the clock line in the idle state So for an idle high clock the leading edge is a falling one a 1 to 0 transition The figure below is a summary Figure 10 3 Serial Clock Phase and Polarity Options Pins MTSR MRST First Bit iL Shift Data SGS THOMSON YA MICROELECTRONICS Serial Clock Transmit Data MCAC1 960 185 254 10 High Speed Synchronous Serial Interface ST10R165 10 1 FULL DUPLEX OPERATION The different devices are connected through three lines The definition of these lines is always deter mined by the master The line connected to the master s data output pin MTSR is the transmit line the receive line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master opera tion generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode DP3 13 0 The output of the master s shift reg ister is connected to the external transmit line which in turn is connected to the slaves shift reg ister input The output of the slaves shift register is connected to the external receive line in order to Figure 10 4 SSC Full Duplex Configuration Device 1 Shift Register 186 254 en
306. trol signals This saves the external combination of the WR signal with AO or BHE In this case pin WR serves as WRL write low byte and pin BHE serves as WRH 7 External Bus Interface ST10R165 write high byte Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE The respective byte will be written on both data bus halves When reading bytes from an external 16 bit de vice whole words may be read andthe ST10R165 automatically selects the byte to be input and dis cards the other However care must be taken when reading devices that change state when be ing read like FIFOs interrupt status registers etc In this case individual bytes should be selected using BHE and AO Note PORT1 gets available for general purpose IO when none of the BUSCON registers se lects a demultiplexed bus mode Disable Enable Control for Pin BHE BYTDIS Bit BYTDIS of SYSCON register is provided for controlling the active low Byte High Enable BHE pin The function of the BHE pin is enabled if the BYTDIS bit contains a 0 Otherwise itis disabled and the pin can be used as standard IO pin The BHE pin is implicitly used by the External Bus Controller to select one of two byte organized memory chips which are connected to the ST10R165 via a word wide external data bus Af ter reset the BHE function is automatically ena bled BYTDIS 0 if a 16 bit data bus is selected during reset otherwise itis disabled B
307. ts contribute to the delay ky 3 SON MICROELECTRONICS 4 Interrupt and Trap Functions ST10R165 A few examples illustrate these delays e The worst case interrupt response time including external accesses will occur when instructions N and N 1 are executed out of external memory in structions N 1 and N require external operand read accesses and instructions N 3 N 2 and N 1 write back external operands In this case the PEC response time is the time to perform 7 word bus accesses e When instructions N and N 1 are executed out of external memory but all operands for instruc tions N 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 word bus access plus 2 state times Once a request for PEC service has been ac knowledged by the CPU the execution of the next instruction is delayed by 2 state times plus the ad ditional time it might take to fetch the source oper and from external memory and to write the desti nation operand over the external bus in an exter nal program environment Note A bus access in this context also includes delays caused by an external READY signal or by bus arbitration HOLD mode 77 254 4 Interrupt and Trap Functions ST10R165 4 6 EXTERNAL INTERRUPTS Although the ST10R165 has no dedicated INTR input pins it provides many possibilities to react on external asynchronous events by using a number of IO lines for interrupt input The interrupt
308. ts that can be generated from vari ous sources internal or external to the microcon troller These mechanisms include Normal Interrupt Processing The CPU temporarily suspends the current pro gram execution and branches to an interrupt serv ice routine in order to service an interrupt request ing device The current program status IP PSW in segmentation mode also CSP is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the or der in which multiple interrupt requests are to be handled Interrupt Processing via the Peripheral Event Controller PEC A faster alternative to normal software controlled interrupt processing is servicing an interrupt re questing device with the ST10R165 s integrated Peripheral Event Controller PEC Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two loca tions in segment 0 data pages O0 through 3 through one of eight programmable PEC Service Channels During a PEC transfer the normal pro gram execution of the CPU is halted for just 1 in struction cycle No internal program status infor March 1995 mation needs to be saved The same prioritization scheme is used for PEC service as for normal in terrupt processing PEC transfers share the 2 highest priority levels Trap Functions Trap functions are activated in response to special conditions that occur during the execution
309. tween two underflows of timer T6 now measured in timer T6 increments Since timer T6 runs 8 times faster than timer T5 it will underflow 8 times within the time between two external events Thus the underflow signal of timer T6 generates 8 ticks Upon each underflow the in terrupt request flag T6IR will be set and bit TEOTL will be toggled The state of TEOTL may be output on pin TOUT This signal has 8 times more tran sitions than the signal which is applied to pin CAP IN The underflow signal of timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units which gives the user the possibil ity to set compare events based on a finer resolu tion than that of the external events Figure 8 20 GPT2 Register CAPREL in Capture And Reload Mode Up Down Auxiliary Timer T5 7 eH isr Interrupt TSIR Request Core Timer T6 ome mecs Up Down SGS THOMSON YA MICROELECTRONICS Interrupt os j Request T60TL ero T60E Interrupt tae Request VR02045G 167 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT2 Cont d 8 2 3 Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down its inter rupt request flag T5IR or T6IR in register TxIC will be set Whenever a transition according to the selection in bit field Cl is detected
310. udrate generator disabled ASCO inactive 1 Baudrate generator enabled 170 254 SGS THOMSON YA MICROELECTRONICS 9 Asynchronous Synchronous Serial Interface ST10R165 SOCON FFBOh D8h 15 rw A transmission is started by writing to the write only Transmit Buffer register SOTBUF via an in struction or a PEC data transfer Only the number of data bits which is determined by the selected operating mode will actually be transmitted ie bits written to positions 9 through 15 of register SOTBUF are always insignificant After a transmis sion has been completed the transmit buffer reg ister is cleared to 0000h Data transmission is double buffered so a new character may be written to the transmit buffer register before the transmission of the previous character is complete This allows to send charac ters back to back without gaps Data reception is enabled by the Receiver Enable Bit SOREN After reception of a character has been completed the received data and if provid ed by the selected operating mode the received parity bit can be read from the read only Receive Buffer register SORBUF Bits in the upper half of SORBUF which are not valid in the selected oper ating mode will be read as zeros Data reception is double buffered so that recep tion of a second character may already begin be fore the previously received character has been read out of the receive buffer register In all SGS THOMS
311. um input frequency which is allowed in counter mode is fopy 1 25 MHz fcey 20 MHz To ensure that a transition of the count input signal which is applied to T3IN is cor rectly recognized its level should be held high or low for at least 8 f py cycles before it changes Figure 8 5 Block Diagram of Core Timer T3 in Counter Mode Interrupt Request MCBO2030 GPT1 Core Timer T3 Counter Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 is disabled Positive transition rising edge on T3IN Negative transition falling edge on T3IN Any transition rising or falling edge on T3IN Reserved Do not use this combination 145 254 SGS THOMSON YA MICROELECTRONICS 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d 8 1 2 GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured for timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 3 counting modes the auxiliary timers can be con catenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer T2CON FF40h AOh SFR 15 14 11 1 Note The auxiliary timers have no output toggle latch and no alternate output function The individual configuration for timers T2 and T4 is dete
312. underflows of T3 but NOT by software modifications of T3OTL Note Although it is possible it should be avoided to select the same reload trigger event for both auxiliary timers In this case both reload registers would try to load the core timer at the same time If this combination is selected T2 is disregarded and the contents of T4 is reloaded SGS THOMSON YA MICROELECTRONICS 151 254 8 General Purpose Timer Units ST10R165 TIMER BLOCK GPT1 Cont d Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to 101b In capture mode the contents of the core timer are latched into an aux iliary timer register in response to a signal transi tion at the respective auxiliary timer s external in put pin TxIN The capture trigger signal can be a positive a negative or both a positive and a neg ative transition The two least significant bits of bit field Txl are used to select the active transition see table in the counter mode section while the most significant bit TxI 2 is irrelevant for capture mode It is recom mended to keep this bit cleared Txl 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Upon a trigger selected transition at the corre sponding input pin TxIN the contents of the core timer are loaded into the
313. underflows of T6 but NOT by software modifications of T6OTL 164 254 SGS THOMSON AJ vie xors SerROMYGS TIMER BLOCK GPT2 Cont d GPT2 Capture Reload Register CAPREL in Capture Mode This 16 bit register can be used as a capture reg ister for the auxiliary timer T5 This mode is select ed by setting bit T5SC 1 in control register T5CON The source for a capture trigger is the ex ternal input pin CAPIN which is an alternate input function of port pin P3 2 Either a positive a nega tive or both a positive and a negative transition at this pin can be selected to trigger the capture func tion The active edge is controlled by bit field CI in register T5CON The same coding is used as in the two least significant bits of bit field T5l see ta ble in counter mode section The maximum input frequency for the capture trig ger signal at CAPIN is fopy 4 2 5 MHz fopy 20 MHz To ensure that a transition of the capture 8 General Purpose Timer Units ST10R165 trigger signal is correctly recognized its level should be held for at least 4 fopy cycles before it changes When a selected transition at the external input pin CAPIN is detected the contents of the auxilia ry timer T5 are latched into register CAPREL and interrupt request flag CRIR is set With the same event timer T5 can be cleared to 0000H This op tion is controlled by bit TBCLR in register TECON If TBCLR O the contents of time
314. upt class covers a set of interrupt sources with the same importance ie the same priority from the system s viewpoint Interrupts of the same class must not interrupt each other The ST10R165 supports this function with two fea tures Classes with up to 4 members can be established by using the same interrupt priority ILVL and as signing a dedicated group level GLVL to each member This functionality is built in and handled automatically by the interrupt controller Classes with more than 4 members can be estab lished by using a number of adjacent interrupt pri orities ILVL and the respective group levels 4 per ILVL Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class All requests from the same or any lower level are blocked now ie no request of this class will be accepted The example below establishes 3 interrupt class es which cover 2 or 3 interrupt priorities depend ing on the number of members in a class A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8 which is the highest priority ILVL in class 2 Class 1 requests or PEC requests are still serviced in this case The 24 interrupt sources excluding PEC re quests are so assigned to 3 classes of priority rather than to 7 different levels as the hardware support would do 71 254 4 Interrupt and Trap Functions ST10R165 PRIORITIZATION
315. upt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is ac tivated by one specific event depending on the selected operating mode of the respective device The only exceptions are the two serial channels of the ST10R165 where an error interrupt request can be generated by different kinds of error How ever specific status flags which identify the type of error are implemented in the serial channels con trol registers The ST10R165 provides a vectored interrupt sys tem In this system specific vector locations in the memory space are reserved for the reset trap and interrupt service functions Whenever a re quest occurs the CPU branches to the location that is associated with the respective interrupt source This allows direct identification of the source that caused the request The only excep tions are the class B hardware traps which all share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the in struction which is a seven bit trap number The reserved vector locations build a jump table in the low end of the ST10R165 s address space segment 0 The jump table is made up of the ap propriate jump instructions that transfer control to the interrupt or trap service routines
316. upted Task Pst b System Stack after Interrupt Entry Segmented MCA02226 storing The ST10R165 allows to switch the com plete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New_Bank pushes the content of the context pointer CP on the sys tem stack and loads CP with the immediate value New Bank which selects a new register bank The service routine may now use its own regis ters This register bank is preserved when the service routine terminates ie its contents are available on the next call Before returning RETI the previous CP is simply POPped from the system stack which returns the registers to the original bank Note The first instruction following the SCXT in struction must not use a GPR Resources that are used by the interrupting pro gram must eventually be saved and restored eg the DPPs and the registers of the MUL DIV unit 73 254 4 Interrupt and Trap Functions ST10R165 4 5 INTERRUPT RESPONSE TIMES The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction 11 being fetched from the interrupt vector location The ba sic interrupt response time for the ST10R165 is 3 instruction cycles All instructions in the pipeline including instruction N during which the interrupt request flag is se
317. ut Fast External Interrupt 4 Input Fast External Interrupt 5 Input Fast External Interrupt 6 Input Fast External Interrupt 7 Input Figure 5 7 Port 2 IO and Alternate Functions Alternate Function General Purpose Fast External Input Ou tput Interrupt Input 95 254 SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 2 Cont d The pins of Port 2 combine internal bus data and alternate data output before the port latch input Figure 5 8 Block Diagram of a Port 2 Pin Write ODP2 y Open Drain Latch Read ODP2 y Write DP2 y Direction Latch Read DP2 y I n t e i n a l oc om Output Buffer Clock MCB02230 96 284 IL fay SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 5 4 PORT 3 If this 15 bit port is used for general purpose IO pins P3 15 P3 14 and P3 12 do not support open the direction of each line can be configured via the drain mode corresponding direction register DP3 Most port pue to pin limitations register bit P3 14 is not con lines can be switched into push pull or open drain nected to an output pin mode via the open drain control register ODP3 P3 FFC4h E2h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw P3 y Port data register P3 bit y Note Register bit P3 14 is not connected to an IO pin DP3 FFC6h E3h SFR Reset Value 0000h 15 14
318. ut Write P6 y Port Output D Output Latch Buffer Clock Input Latch MCB01982 109 254 SGS THOMSON YA MICROELECTRONICS 5 Parallel Ports ST10R165 PORT 6 Cont d The bus arbitration signals HOLD HLDA and tomatically to the appropriate direction Note that BREQ are selected with bit HLDEN in register the pin drivers for HLDA and BREQ are automati PSW When the bus arbitration signals are ena cally enabled while the pin driver for HOLD is au bled via HLDEN also these pins are switched au tomatically disabled Figure 5 18 Block Diagram of Pin P6 5 HOLD Write ODP6 y Open Drain Latch Read ODP6 y Write DP6 y Direction Latch Read DP6 y I n t e r n a l o c o Output Buffer Clock d MCB01983 Input 110 254 S7 SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ Most of the input output or control signals of the functional the ST10R165 are realized as alternate functions of pins of the parallel ports There is however a number of signals that use separate pins including the oscillator special control signals and of course the power supply The table below summarizes the 23 dedicated pins of the ST10R165 Ping rmon R amp Enteral Read Svobe RSTIN Reset Input RSTOUT Reset Output XTAL1 XTAL2 Oscillator Input Output Vpp Reserved for Flash Programming Voltage Digital Power Supply and Ground 6 pin
319. ver en able bit SOREN is reset and serial data reception stops Pin TXDO P3 10 must be configured for alternate data output ie P3 102 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must be configured as alternate data input DP3 11 0 Synchronous reception is stopped by clearing bit SOREN A currently received byte is completed in cluding the generation of the receive interrupt re quest and an error interrupt request if appropri ate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission If a previously received byte has not been read out of the receive buffer register atthe time the recep tion of the next byte is complete both the error in terrupt request flag SOEIR and the overrun error status flag SOOE will be set provided the overrun check has been enabled by bit SOOEN SON MICROELECTRONICS 9 Asynchronous Synchronous Serial Interface ST10R165 9 3 HARDWARE ERROR DETECTION CAPABILITIES To improve the safety of serial data exchange the serial channel ASCO provides an error interrupt re quest flag which indicates the presence of an er ror and three selectable error status flags in reg ister SOCON which indicate which error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR will be set simultaneously with the receive inter rupt request flag
320. watchdog timer overflow 0000h otherwise SORBUF XXh undefined SSCRB XXXXh undefined SYSCON 0XXOh set according to reset configuration BUSCONO 0XXOh set according to reset configuration XXh reset levels of POH FFFFh fixed value RPOH ONES SGS THOMSON YA MICROELECTRONICS 13 5 THEINTERNAL RAM AFTER RESET The contents of the internal RAM are not affected by a system reset However after a power on re set the contents of the internal RAM are unde fined This implies that the GPRs R15 R0 and the PEC source and destination pointers SRCP7 SRCPO DSTP7 DSTPO which are mapped into the internal RAM are also unchanged after a warm reset software reset or watchdog re set but are undefined after a power on reset 13 6 PORTS AND EXTERNAL CONFIGURATION DURING RESET During the internal reset sequence all of the ST10R165 s port pins are configured as inputs by clearing the associated direction registers and their pin drivers are switched to the high imped ance state This ensures that the ST10R165 and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pulldown and pins RD and WR are held high through internal pullups Also the pins select ed for CS output will be pulled high The registers SYSCON and BUSCONO are initial ized according to the configuration selected via PORTO Pin EA must be held at 0 level ethe Bus Ty
321. which may 60 254 be located anywhere within the address space The entries to the jump table are located at the lowest addresses in code segment 0 of the ad dress space Each entry occupies 2 words except for the reset vector and the hardware trap vectors which occupy 4 or 8 words The table below lists all sources that are capable of requesting interrupt or PEC service in the ST10R165 the associated interrupt vectors their locations and the associated trap numbers It also lists the mnemonics of the affected Interrupt Re quest flags and their corresponding Interrupt Ena ble flags The mnemonics are composed of a part that specifies the respective source followed by a part that specifies their function IR2Interrupt Re quest flag E Interrupt Enable flag Note The four X Peripheral nodes in the table are prepared to accept interrupt requests from integrated XBUS peripherals Those of these nodes where no X Peripherals are connected may be used to generate soft ware controlled interrupt requests by setting the respective XPnIR bit as with the Soft ware Nodes In addition the ST10R165 includes three Software Nodes associated with three Software Interrupt Control Registers CC291C F184h C2h CC301C F18Ch C6h and CC31IC F194h CAh These nodes offer the same features as the other interrupt nodes except that their interrupt request flags are not set by hardware but are available for generating software inter ru
322. witches asynchronously with RSTIN synchronously upon software or watchdog reset The reset condition ends here The ST10R165 starts program execution Execution of the EINIT instruction 1 2 3 4 Activation of the IO pins is controlled by software 5 6 The shaded area designates the internal reset sequence which starts after synchronization of RSTIN SGS THOMSON YA MICROELECTRONICS 207 254 13 System Reset ST10R165 13 2 RESET OUTPUT PIN The RSTOUT pin is dedicated to generate a reset signal for the system components besides the controller itself RSTOUT will be driven active low at the begin of any reset sequence triggered by hardware the SRST instruction or a watchdog timer overflow RSTOUT stays active low be yond the end of the internal reset sequence until the protected EINIT End of Initialization instruc tion is executed see figure above This allows to completely configure the controller including its on chip peripheral units before releasing the reset signal for the external peripherals of the system 13 3 WATCHDOG TIMER OPERATION AFTER RESET The watchdog timer starts running after the inter nal reset has completed It will be clocked with the internal system clock divided by 2 10 MHz fcpu 20 MHz and its default reload value is 00h so a watchdog timer overflow will occur 131072 CPU clock cycles 6 55 ms fcpy 20 MHz after completion of the internal reset unless it is disable
323. y be bytewide or wordwide with or without a sepa rate address bus Interrupt nodes and configura tion pins on PORTO are provided for X Peripher als to be integrated Note If you plan to develop a peripheral of your own to be integrated into a ST10R165 de vice to create a customer specific version please ask for the specification of the XBUS interface and for further support SGS THOMSON YA MICROELECTRONICS wr SGS THOMSON STi0R165 User Manual YZ MICROELECTRONICS Chapter 8 GENERAL PURPOSE TIMER UNITS The General Purpose Timer Units GPT1 and GPT2 represent very flexible multifunctional timer structures which may be used for timing event counting pulse width measurement pulse gener ation frequency multiplication and other purpos es They incorporate five 16 bit timers that are grouped into the two timer blocks GPT1 and GPT2 Block GPT1 contains 3 timers counters with a maximum resolution of 400 ns 20 MHz CPU clock while block GPT2 contains 2 timers counters with a maximum resolution of 200 ns 20 MHz CPU clock and a 16 bit Capture Reload register CAPREL Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may op tionally be configured as reload or capture regis ters for the core timer In the GPT2 block the ad ditional CAPREL register
324. y different time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multi plication The five 16 bit timers are organized in two sepa rate modules GPT1 and GPT2 Each timer in each module may operate independently in a number of different modes or may be concatenat ed with another timer of the same module Each timer can be configured individually for one of three basic modes of operation which are Tim er Gated Timer and Counter Mode In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler while Counter Mode allows a timer to be clocked in reference to external events via Tx IN Pulse width or duty cycle measurement is support ed in Gated Timer Mode where the operation of a timer is controlled by the gate level on its external input pin TxIN The count direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal TxEUD to facilitate eg position tracking The core timers T3 and T6 have output toggle latches TxOTL which change their state on each timer over flow underflow The state of these latches may be output on port pins TxOUT or SGS THOMSON YA MICROELECTRONICS 1 Architectural Overview ST10R165 may be used internally to concatenate the core timers with the respective auxiliary timers resulting in 32 33
325. ycle time has been dramatically reduced through the use of instruction pipelining This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel The following four stage pipeline pro vides the optimum balancing for the CPU core FETCH In this stage an instruction is fetched from the internal ROM or RAM or from the external memory based on the current IP value DECODE In this stage the previously fetched in struction is decoded and the required operands are fetched EXECUTE Inthis stage the specified operation is performed on the previously fetched operands WRITE BACK Inthis stage the result is written to the specified location If this technique were not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed SGS THOMSON YA MICROELECTRONICS Instruction Decoder Instruction decoding is primarily generated from PLA outputs based on the selected opcode No microcode is used and each pipeline stage re ceives control signals staged in control registers from the decode stage PLAs Pipeline holds are primarily caused by wait states for external memo ry accesses and cause the holding of signals in the control registers Multiple cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals High Function 8 b
326. ys tem stack The user may push both bytes and words onto a user stack but is responsible for us ing the appropriate instructions when popping data from the specific user stack No hardware de tection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one byte or word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack point er Rb Rw or Rw Rw Post increment Index Register Indirect Addressing Used to pop one byte or word from a user stack This mode is available to most instructions but only GPRs RO R3 can be specified as the user stack pointer Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one byte or word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack point er 228 254 15 5 REGISTER BANKING Register banking provides the user with an ex tremely fast method to switch user context A sin gle machine cycle instruction saves the old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated during coding based on the needs of each task Once the internal memory has been partitioned into a register bank space internal stack space and a global internal memo
327. ystem performance while minimizing the part count These efforts are supported by the XBUS This XBUS is an internal representation of the external bus interface that opens and simplifies the integration of peripherals by standardizing the required interface More standard and application specific derivatives are planned and in development The ST10R165 with its reduced peripheral set has been designed for embedded control applications where price performance characteristics of this ST10 gives a real advantage in price sensitive markets like computer peripherals amp telecom High Performance 16 Bit CPU With Four Stage Pipeline m 100 ns minimum instruction cycle time with most instructions executed in 1 cycle m 500 ns multiplication 16 bit 16 bit 1 us division 32 bit 16 bit m Multiple high bandwidth internal data buses SGS THOMSON YA MICROELECTRONICS FEATURES m Register based design with multiple variable register banks m Single cycle context switching support m 16 MBytes linear address space for code and data von Neumann architecture m System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency m Bit byte and word data types m Flexible and efficient addressing modes for high code density m Enhanced boolean bit manipulation with direct addressability of 4 Kbits for peripheral control and user defined flags m Hardware traps

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