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SIS3305 5 GS/s, 2.5 GS/s, 1.25 GS/s 10

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2. Slruck de 55353205 vi Z Hund WA fz dug E err ee Ed dE E EE bb SS GS Ws 1 bares dud rr rl if Alt ud Pete ee aal Hn Ax SN NW N Ki Ki ka NM modo od EEE I SIS3305 5 GS s 10 b dd dd des da KANN grat Ban EZE k fe re eee i i D 1 tbs el t E en 3 uw wi Ki 5 R M E m Ki bbe 8 a 8 FEFEFE RR ey ee a feet ee x hy Te Ty The ET Mee e ht LR a L P LR R1 1 KKK M d df bk oet US SS Thy
3. Page 88 of 97 Still Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 10 Getting started 10 1 SIS3305 base program The runtime version of the SIS3305 base program in combination with a SIS3150 USB to VME or a SISII00 e 310x PCI Express to VME interface provides access to all implemented SIS3305 features without the need for coding in the first step under Windows Feel free to inquire about the possibility for a loaner in case you are working with another VME master An example screen shot of the SIS3305 base program a signal acquired in ring buffer synchronous mode of operation W 5153350 ADC Test 27 August 2008 im 81 x Panel View 5153350 Configuration Information Test Menues 8183350 ADC Test Menue 418183350 ADC Temperature Information ADC Sample Clock Temperature Celsius Operation Mode Iv Display Raw Signals Frequency Synthesizer Clock Mode FT MultiE vent Mode 2 Ringbuffer Synchronous Mode Display Histogram 100 00 57 00 52 00 Celsius Display FFT 75 00 50 00 25 00 0 00 54 00 52 00 Frequency Synthesizer Parameter a N Frequence 25 MHz x M 2 Power N Ch 4 Nof Events i o 12550 Fahrenheit Close 4 d 72 Rinabuffer sample length en vd 20 M Divider Frequence in MHz Za 1000 Address Threshold 4 O NDivider 500 00 50 00 47 00 20 00 Threshold Trigger
4. SS P P Hy a x rater jL Ad A TMT Ms t P F til KNKKKKKKM TRANT T i TT gg ay ly Se OTT kkk k1 i K 3 VK KN SN Ki a d t IC SU te AULA RIA ee Wenger sr us EEF ee Eg ee AA eee n Pr xS E RR KEE he a a ii in Bio h LA amp KK a ggg NS Ki Ki Ki Te un d F ESSE m l a BA SESS KA E a d 5 E d E LRL
5. 55 actual samipi O actual sample address register 55 qb ruo d qe eegener EE DO TOD Meu ADC JOB delay beu s etu IO ADC serial interface eese OD Aurora Protocol Status 2 Aurora Protocol Data Status 57 broddeast E A velis EE E A E EET E E Direct Memory Event Coumnter 55 Direct Memory Max Nof Events 92 Direct Memory Stop Pretrigger Block Length 51 EEprom Control cceeeeeeeeeeeeeee DO end address threshold sss O2 event Con gurapon 4O External Trigger In Counter 32 firmware revision e AU Individual Channel Select Set Veto 58 interrupt configuration eessseesssssss 21 22 UN TEMP dp IN cc H 0 171 T key UU SS LEMO Trigger Out 56161 teet onto d module Id sess 20 OCW Me COMO 000100101010100 ringbuffer pretrigger delay 51 Sample Memory Start Address 49 Sample Extended Block Length 50 sampling status D4 WA FO s E MNT OO TDC 16815 619 e PNIS SIS Documentation TDC Sparb5toD CNA OC 0 0000020207 35
6. D D D d d dP 5 Se bn Du bn ye Ab oi cus S RS S UR Pun nuni AS dE at Dow A S m mS URS TT KAUL se wl A printout of the silk screen of the component side of the PCB is shown below SIS Documentation 7 Board layout Page 79 of 97 SIS Documentation SIS3305 Saree innovative 5 GS s 10 bit Digitizer systeme 8 Front panel The SIS3305 is a single width 4TE 6U VME module A sketch of the SIS3305 front panel without handles is shown below SIS3305 1 SIS GmbH www struck de VETO CON Page 80 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 8 1 Front Panel LED s The 5153305 has 6 front panel LEDs to visualise part of the modules status The access LED is a good way to check first time communication addressing with the module Function Access to SIS3305 VME slave port Red P Power Gren R Ready on board logic configured User to be set cleared under program control User to be set cleared under program control OT Data sampling ADC data transfer to Memory acitve User to be set cleared under program control OT Data sample logic enabled see Control Register The three USER Leds U1 U2 U3 are flashing with 4 Hz to indicate the over
7. Daa U21_Tx Lock flag 28 Data U2l error counter bit 7 to 4 or 27 DataU2lemorcouterbit3 24 Data_U21_error counter bitO 15 Data Hl Lane upflg 14 Daa U11 Lane up flag O B Z7 Data UllTxlockfhg 12 A 4 Z Data Ull error counter bit 7 to 4 or OlJDL jJDataUllemorcouterbit3 8 Jg Data Ull errorcounterbitO0 6 Lea Pret UII Soft eror latch Data Ull Sot eo ach 0 o Daa Ull Hard error flag Note Data Ux1 Lane up flag 1 Data Uxl Lane up flag 0 Page 43 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 14 Key addresses 0x400 0x43C write only Write access with Broadcast functionality to a key address KA with arbitrary data invokes a respective action 4 14 1 Key address general reset 0x400 write only define SIS3305 KEY RESET 0x400 WELLE only D32 y A write with arbitrary data to this register key address resets the SIS3305 to it s power up state 4 14 2 Key address Arm sample logic 0x410 write only define S1IS3305 KEY ARM 0x410 write Only D32 7y A write with arbitrary data to this register key address will arm the sample logic 4 14 3 Key address Disarm sampe logic 0x414 write only define SIS3305 KEY DISARM 0x414 write only D32 A write with arbitrary data to this register key address will disarm
8. nnns 24 4x SRS O OntFOT R68 E 25 EBprom 152430 Onewire Control Eeer 27 AA Broadcast setip EE EE 29 AS LEMO 1 185868 Out Select register 0X40 Tead WEITE 31 JO EXPO et In OU E 32 EL E ART 33 4 7 1 TDC Write Cmd Read Status register 0x50 read WrIte sass 33 4 7 2 TDC Read Cmd Read Data register 0x54 read write essere 33 4 7 3 TDC Statt Stop Enable register 0x58 read WrItge npa etis appare ob Eege TE xa DRE UPS e Ee 33 4 7 4 XILINX JTAG TESI 116815 61 9 ommo aa 36 4 7 5 ATANA JTTA DATA RR E 36 4 8 Temperature and Temperature Supervisor register 0x70 readiwrten 37 4 0 ADC Serial Interface SPI register 0x74 readiwrte esses 30 4 10 0 chl ch4 ADC2 ch5 8 FPGA Data Transfer Control register OxCO OxC4A 40 4 11 ADCI chl ch4 ADC2 ch5 8 FPGA Data Transfer Status register OxC8 OSCH 41 4 12 Aurora Protocol Status register OxDO read write ssa 42 4 13 Aurora Data Status register OxD4 readivwtei enne nennen nnns 43 4 14 Key addresses 0x400 0x43C write online 44 4 14 1 Key address general reset 0x400 write ob 44 4 14 2 Key address Arm sample logic 0x410 write Only sss 44 4 14 3 Key address Disarm sampe logic 0x414 write of
9. Timestamp Clear with Sample Enable bit Timestamp Clear with Timestamp Clear with Sample Enable bit O0 Sample Enabled and first TDC Event external Trigger Sample Enabled Page 47 of 97 Wie Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer ADC Event sampling with next external Trigger ADC Event sampling with ADC Event sampling with next external Trigger bit Ready for ADC Events after Sample Enabled 1 Ready for ADC Events after Sample Enabled and first TDC Event external Trigger Enable internal Trigger Gate asynchronous Mode Enable internal Trigger Gate bit internal individual trigger gate Enable global Trigger Gate synchronous Mode bit 0 No global trigger 1 global trigger all channels are trigger with global trigger gate external trigger if enabled or KeyTrigger ADC Event Saving Modes 4 channel Event FIFO Mode Save ADC values of 4 channels in one Data Block asynchronous Mode 1 x 5Gsps synchronous Mode 5Gsps 2 5Gsps 1 25Gsps 1 2 channel Event FIFO Mode Save ADC values of 2 channels in one Data Block asynchronous Mode 2 x 2 5Gsps 4 1 channel Event FIFO Mode WE Save ADC values of 1 channel in one Data Block asynchronous Mode 4 x 1 25Gsps 4 channel Event Direct Memory Start Mode synchronous Mode 5Gsps 2 5Gsps 1 25Gsps 4 channel Event Direct Memory Stop Wrap Mode synchronous Mode 5Gsps 2 5Gsps 1 25Gsps
10. 11 3 Connector types The table below lists the connectors used on the SIS3305 Part Number CONIOB Piggy Back Chl Ch4 CON20B Piggy Back Ch5 Ch8 CON100 JTAG MOLEX 87831 1420 CON 120 Trigger_In LEMO EPY 00 250 NTN CON 123 Count_In LEMO EPY 00 250 NTN TT mm ENO ITT CON901D CLK_OUT JYEBAO SMA8400A 1 9000 P1 P2 VME BUS HARTING 02 01 160 2101 Page 92 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer 11 4 Rowd and z Pin Assignments The SIS3305 is prepared for the use with VME64x backplanes A foreseen feature is geographical addressing The prepared pins on the d and z rows of the P1 and P2 connectors are listed below Position 071 0 1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VPC D GAP SSES Wild Innovative systeme P22 DO GND VPC D Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 93 of 97 gile Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 11 5 Firmware upgrade The firmware of the SIS3305 can be upgraded over JT AG The upgrade options are VME on units that have intact firmware and the JTAG connector CON100 Refer to the section 9 1 also Page 94 of 97 SIS Documentation 12 Index channel Event FIFO Mode channel Event FIFO Mode annel Event Dir
11. The 8 bit ADC Event Header programmable ID is used to program an Event Header ID The example software writes a part of the selected SIS3305 VME base address and the ADC group number to this register Bis 71 0 1 ADC chip 2 channel 5 8 Page 46 of 97 Wie Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer The 4 bit ADC Event Header programmable information is used to add additional information to the ADC event header The Struck example software writes the selected ADC chip channel mode to this register ADC Event Header ADC chip channel mode software defined programmable information OA channel 4 x 1 25Gsps pe channel 2 x 2 5Gsps Ce channel 1 x 5Gsps reserved Enable Direct Memory Stop Arm for Trigger after PreTriggerDelay bit Enable Direct Memory Stop Arm for Trigger after PreDelay bit Arms the logic for an external trigger immediately after the sampling is started in Event Direct Memory Stop Wrap Mode Arms the logic for an external trigger after the sampling 1s started and PreTrigger samples are stored in Event Direct Memory Stop Wrap Mode Disable Direct Memory Header bit Disable Direct Memory PCR 0 Direct Memory Event Data Buffer has a Header Disable Timestamp Clear bit Disable Timestamp Clear bit Timestamp Clear with Enable Timestamp clear function see Timestamp Clear with Sample Enable bit Disable Timestamp clear function
12. Threshold value OFF Threshold value ON Enable default after Reset 0x0 A valid gate output is generated on the conditions e GT is set GT the Gate output signal will be set if the actual ADC value goes above the programmable threshold value ON and OFF and it is valid until the actual ADC value goes below the threshold value OFF 4 22 2 Threshold Trigger Gate LT 90 1510 2516 13026 31 Bit Threshold value OFF Threshold value ON Enable default after Reset 0x0 A valid gate output is generated on the condition e LTisset LT the Gate output signal will be set if the actual ADC value goes below the programmable threshold value ON and OFF and it is valid until the actual ADC value goes above the threshold value OFF Page 53 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 23 Sampling Status 0x2040 0x3040 define 305_ SAMPLING STATUS REG ADC 1 4 0x2040 define S1S3305 SAMPLING STATUS REG ADCb5 8 0x3040 This register holds the sampling status and an event builder FSM Finite State Machine error counter The Finite State Machine FSM error counter 15 reserved for internal use reserved M reserved Event Builder FSM Mode Error Counter bit 7 Event Builder FSM Mode Error Counter bit 0 HEN 6 Direct Memory Wrap Flag D Sampling Enable BUSY Page 54 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS
13. 1 1 60 tri 2586111182 0 X USB 83 LED eeeeeeeeeeeeeeeseeeeeeeeeeeeeeeeseeeeeeeseeeeeeeeeeeeeeeeseeeeeeeseeeeeeeeee 1 8 VEC 1000000000 0 83 9 62 VES E 61 5 85 veto delay length SE EE 62 1 01100 ee sessssseossossesseoseossossessesseoseos 86 VISUS C EEN 90 000 01 interrupt E M T I 12 VME addressing eee 1 e e e e G 13 VME base address 88 VME64X ENN 7 93 watchdog SE 88 1 0055 00010011111100 90 XILINX eeeeeeeeseeeeeeeseeeeeeeseeeeeeeseeeeeeeeeseeeeeeeseeeeeeeseeeeeeeseeeeeeeeee 83 Page 97 of 97
14. C T end Page 70 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 6 1 1 TDC FIFO Event Data format TDC Fifo Event external Trigger In Event ID 8 Header 4 x 32 bit words 31 28 7 24 23 16 15 Event ID Event Cnt Event Header ID Timestamp 47 32 Timestamp 31 0 Counter 40MHz 31 0 TDC Cnt Temperature 9 0 TDC value 17 0 Event Cnt 4 bit TDC Event Counter counts the External Triggers in the ADC FPGA Event Header ID programmable by the Event configuration registers Timestamp could be cleared with Sampling enable or with first TDC Event Incremented with Clock 12 2 5Ghz gt 208 33MHz Latched with the TDC Event External Trigger Counter 40MHz cleared with Sampling enable or with external Clear Incremented with external Count max 80MHz Latched with the TDC Event External Trigger TDC Cnt 4 bit TDC Event Counter counts the received TDC data messages caused by the External Trigger in the VME FPGA Temperature value of the temperature sensor see Temperature register TDC value value of the TDC measurement Example HEADER EVENT 1D TDC 82820000 decac 0 32d40368 meaning 82820000 Event ID 8 82820000 Event Cnt 22 82820000 82 indicates Base Address 0x41000000 ADC chip 1 Page 71 of 97 Seabed Innovative systeme SIS3305 5 GS s 10 bit Digitizer SIS Documentation 6 1 2 A
15. Channel 1 Trigger Gate cal Channel 1 2 Sample Logic Page 65 of 97 Seale innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 5 5 1 3 1 channel Event FIFO Mode In 1 channel Event FIFO Mode the logic saves the ADC values of 1 channels in one Data Block This mode is used to save 1 25Gsps Events which are triggered internally channel trigger channel 4 trigger Channel 4 Veto Channel 4 Channel 3 Veto Sample Logic ADC FPGA Veto Channel 2 Veto Logic Channel 1 Veto Channel 3 Sample Logic Channel 4 Trigger Gate Channel 2 Sample Logic ADC FPGA Channel 3 Trigger Gate Trigger Gate Logic Channel 2 Trigger Gate Channel 1 Channel 1 Trigger Gate Sample Logic Page 66 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Seale innovative systeme 5 5 2 4 channel Event Direct Memory Start Mode The logic saves the ADC values of 4 channels to memory in one data block with a header in 4 channel Event Direct Memory Start Mode An external trigger starts the sampling and the logic writes N samples to the Memory with an information header If the sample logic is enabled In Multi Event Mode the logic is ready for a new trigger after the event is written programmable Event Length up to e 4x 201 326 592 1 25Gsps e 2x 402 653 184 2 5Gsps e 1x 805 306 368 SGsps programmable Number of Events Multi Event programmable Ringbuffer Delay for the ADC data 6 to 6
16. 0 0 0 l Not possible IJ Bay Stopped Clock source bit setting table Page 23 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer Clock Source Clock Source Clock Source Bitl RB o 0 Internal 2 5 GHz O 1 External Clock d 0 Noclcck No clock Enable Trigger In TDC Measurement Logic Enable Trigger In TDC Measurement Logic bit 0 Disables the TDC Measurement Logic in the VME FPGA Enables the TDC Measurement Logic in the VME FPGA 4 1 Veto Length register 0x14 read write define S1IS3305_VETO_LENGTH 0x14 This registers defines the veto length setting It is used if the External LEMO Veto Delay Length logic is enabled in the control register Refer to sections 4 1 1 and 5 4 1 for an illustration of the External LEMO Veto Delay Length logic Function 32 bit Veto Length value Veto Length Veto Length value 1 20ns The power up default value is 0 4 2 Veto Delay register 0x18 read write define 5153305 _ DELAY LENGTH 0x18 This registers defines the veto delay setting It is used if the External LEMO Veto Delay Length logic is enabled in the control register Refer to sections 4 1 1 and 5 4 1 for an illustration of the External LEMO Veto Delay Length logic Function 32 bit Veto Delay value Veto Delay Veto Delay value 1 20ns The power up default value is 0 Page 24 of 97 SIS Documentation SIS3305 innovative GS s 10
17. 44 4 14 4 Key address 17188676 nnne 44 4 14 5 Key address Enable sample logic eese eene nennen enne nennen nennen 44 Page 3 of 97 SIS Documentation SIS3305 03 5 GS s 10 bit Digitizer 4 14 6 Key address Set Volo E 44 4147 106 7 1101007063 6 Clear E 44 4 14 8 Key address ADC Clock Synchronization seen nnne nnne 45 4 14 9 Key address Reset ADC FPCGA Toagtc nennen ennt teens 45 4 14 10 Key address Trigger Out E 45 4 15 Event configuration registers 0x2000 0x3000 readiwrte i 416 4 16 Sample Memory Start Address registers 0x2004 Ox lt 3004 sss 49 4 17 Sample Extended Block Length registers 0x2008 0x3008 sees 50 4 18 Direct Memory Stop Pretrigger Block Length registers Ox200C UNO 51 4 19 Ringbuffer Pretrigger Delay 16818161 rera rust 51 4 20 Direct Memory Max Nof Events registers 0x2018 OX3018 sss 51 4 21 End Address Threshold registers oe etr teretes oen Pob sabe NEES 52 4 22 Trigger Gate Threshold regISterS sass 53 4221 Threshold IESE GALE OT a eh a 53 4 222 Threshold Triepet Gate E EE 53 4 23 Sampling Status 0x2040
18. 15a 184 209 315 2305 320 S01 sic 30d 327 3af 23 Saf 3bl 3b0 3b4 3ae 0 Gg 4e 54 18e 1a0 197 lab 32e 336 EE 2d 305 3b2 3b4 3b4 gt l trigger 0x26C on 2 position ADC4 44 47 46 Ab 16a 1 Ze 174 LOG SiG 322 okt 328 3b1 23 3b3 23 56 fe e 60 1b6 lc Leo 1d2 345 34d 34a 301 3b6 3I 3b4 3b6 4d cmi 52 59 192 la6 96 laf 352 335 337 30 302 3b4 Elek 3b4 64 6a 6 6 FS Ide LE 1e9 lfa OO 264 Oe 562 3b6 2325 3b6 3b6 58 re 56 62 1b8 Led 1c4 Toe 348 350 34d 3353 3b3 2325 353 3b4 14 la 84 205 216 207 221 307 372 3651 348 Eley 359 3b6 6 3 Page 77 of 97 SIS3305 5 GS s 10 bit Digitizer Wie Innovative systeme SIS Documentation 6 1 5 ADC Direct Memory Event Data format external Trigger ADC Direct Memory Event Event ID OxC for ADC Direct Memory Start Mode Event ID OxD for ADC Direct Memory Wrap Stop Mode Header 16 x 32 bit words 31 28 27 24 23 16 15 Event ID Event Header Info Event Header ID Timestamp 47 32 Timestamp 31 0 Counter 40MHz 31 0 Length 31 0 in Data blocks 16x32 bit words Wrap flag 0000000 Wrap stop offset 23 0 in Data blocks 001 0000 Event Counter 000000 000000 redundant second block Event ID Event Header Info Event Header ID Timestamp 47 32 Timestamp
19. 31 0 Coun ter 4A0MHz 31 0 Length 31 0 in Data blocks 0000000 Wrap flag Wrap stop offset 23 0 in Data blocks 0x0000 Event Counter 0000 00 000000 1 Data Block 16 x 32 bit words Note Sample N 1 25 Gsps N 2 5 Gsps N 5 Gsps sample 1 1 1 9 0 sample2 3 5 sample 3 5 9 sample 4 7 13 sample 5 9 17 sample 6 11 21 sample 7 13 25 sample 8 15 29 sample 9 17 33 sample 10 19 37 sample 11 21 41 sample 12 23 45 sample 1 2 3 9 0 sample 2 4 7 sample 3 6 11 Sample 4 8 15 sample 5 10 19 sample 6 12 23 sample 7 14 27 sample 1 sample 9 18 35 sample 10 20 39 sample 11 22 43 sample 12 24 47 sample 1 1 2 9 0 sample 2 3 6 sample 3 5 10 sample 4 7 14 sample 5 9 18 sample 6 11 22 sample 7 13 26 sample 8 15 30 sample 9 17 34 sample 10 19 38 sample 11 21 42 sample 12 23 46 Sample 1 2 4 9 0 sample 2 4 8 sample 3 6 12 sample 4 8 16 sample 5 10 20 sample 6 12 24 sample 7 14 28 sample 8 16 32 sample 9 18 36 sample 10 20 40 sample 11 22 44 sample 12 24 48 Page 78 of 97 0 B0 w rr n o ay a o 4 act R e Un Tray ii W 1 07 Tm KS 200177 L
20. 3d fl TOLL 24 292 2db 2da 0 26 41 10e Lie 262 268 21 zad e00004 42 47 48 4f lzc iad 13d 15b 210 209 27a 28c 2e7 2e5 2e0 2e0 Af 9e LOC 17a 297 29d 2e4 2e2 Da 64 18a 199 2a6 23 2e4 2e3 6a 73 laa 1b6 2bl 26 206 202 7a 05 9 1d6 2bd 2bf 2e4 2el Event ID 4 Event Info 1 9 indicates ADC chip 2 gt channel 5 bit 0 of e0 indicates Trigger GT bit 3 and on 6 position of ADC2 0x26d 3eldaba 4a 93 Sr 2 15 d 162 180 28c 299 290 2al 2e4 206 21 2e2 99 indicates Trigger GT bit 3 and on 6 position 0x26d 5e 69 192 110 237 2ae 2e 21 0 6e 78 LO 1bd 2 28 2695 2e2 99000 4 7e 5953 8a gi 1800 dec lue 6 Zor 208 COU 2609 2eb 265 267 2e2 1 55 207 211 291 ZOL 2e4 2e0 62 ce 8 2 206 2d4 2e4 206 db ea 2 244 209 2da 2e2 2dd 8 106 2421 259 2da 2db 2e0 2de Page 75 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer 6 1 4 ADC 5 Gsps FIFO Event Data format ADC Fifo Event Event ID 7 5 Gsps internal external trigger 2 5 Gsps external trigger 1 25 Gsps external trigger Header 4 x 32 bit words 31 28 27 24 23 16 15 innovative Struck systeme Event ID Event Header Info Event Header ID Timestamp 47 32 Timestamp 31 0 Counter 40MHz 31 0 ADC 4 Trigger Index ADC 3 ADC 2 Trigge
21. 5 GS s 10 bit Digitizer 4 5 LEMO Trigger Out Select register 0x40 read write define SIS3305 TRIGGER OUT SELECT REG 0x40 read write D32 The selected conditions are ored to the LEMO Trigger Out connector 9 Select Trigger In if LEMO IN is enabled o 8 Select Trigger In direc 6 Select Trigger ADC2ch7 O Select Trigger ADC1 chl Page 31 of 97 Salaa Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 6 External Trigger In Counter define SIS3305_EXTERNAL TRIGGER COUNTER Ox4C I reid only D32 This 32 bit Counter will be cleared if the Sample Logic or the TDC Measurement Logic is disabled It will be incremented with each External Trigger In Signal if the Sample Logic and the TDC Measurement Logic are enabled The TDC Measurement Logic writes the lower 4 counter bits with the TDC Stop values to the ADC FPGAs Page 32 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Wie Innovative systeme 4 7 TDC registers The SIS3305 is equipped with a ACAM TDC GPX chip Four TDC registers are implemented to control the TDC GPX define SIS3305 TDC WRITE CMD REG 0x50 read write D32 define SIS3305 TDC READ CMD REG 0x54 read write D32 define 8183305 TDC START STOP ENABLE REG 0x58 read write D32 define SIS3305_TDC_FSM_REG4_VALUE_REG Ox5C read write D32 Programming refer to sis3305_configuration_readout_lib c int SIS3305_TDC_Even
22. N Bee eneral block diagram of one ADC 59 hical addressi 93 eographical addreseng esses 611107 5137160 1 Oe Doe e 0100000110000000 83 PX EE cci Page 95 of 97 SIS Documentation H USB 06060600606000060060000060006000000060000060006000006000600000006000000000000000000909 input 12008679356 NI 110000010101100 Th DLO et EN e w feet TN bat ce ae UOT EE DUR Te E e IRQ Direct Memory End Address Thresbold e 22 IRO MOC eene e TAG E EE O O ADC Clock Synchronization 45 arm sample logic A Ad disarm sample logic 44 Enable sample logiC 44 FAL T2 A resol NRI E 1 1 1 12121212 2 an Reset ADC FPGA Logic 45 OE 1 oS e YS rigger Out Eeer key address 14 30 44 e Page 96 of 97 SIS3305 5 GS s 10 bit Digitizer innovative systeme live insertion e Hl ID zig a M T 07 ETO Nandi ea aaa Memory Overrun Veto Loge 03 mode O EE operating CHERCHE Over termperature NG 81 Ole ae eee one eee o power consumption Hl PROM 0 53 RE E OO COMTO actual next event Start address register
23. TDC Write Cmd MEET 33 34 temperatur O eegene 37 temperature supervisor ccceeeeeeeceeeeeeeeeeeeeeeees 37 EE 53 Trigger Gate Threshold ss 53 1750 0810 E T aa 24 VOLO a E 24 VME PA 14 EE 85 ROS 12 21 SE 12 21 S sample logic PIE Eccc 60 ri 60 sc Eege 86 Silo S Ea icio PT 89 SD EE 6 5153305 base program 89 BOWAO I0 19 o eeng 90 oa bl 15 39 2100 0 00 ME a 67 Status Direct Memory Event Flags 23 SE 0 NEN cm 68 S11 13 88 SV P 13 88 dp 13 88 57 5115551 88 T RE CCL AY 0 0 0010100202 EE 58 see e 83 LE 11 TOC A 33 RS E 36 83 jupe ee ee H 83 SIS3305 5 GS s 10 bit Digitizer Salaa Innovative systeme T h 1 1 P 1 F ecnnica roperties 631011665 dee T 1 1 84 5 ei RRUIIUEZ 18 TA BEE termperature 3 8l TMS EE 36 83 tri Tri BREET 84 tri gger Control eher errereen 10 1 1 10 tri gger generation
24. default after Reset 0x0 4 19 Ringbuffer Pretrigger Delay register define SIS3305_RINGBUFFER_PRE_DELAY_ADC12 0x2010 define SIS3305_RINGBUFFER_PRE_DELAY_ADC34 0x2014 fdefine SIS3305_RINGBUFFER_PRE_DELAY_ADC56 0x3010 define SIS3305_RINGBUFFER_PRE_DELAY_ADC78 0x3014 These registers define the number of pre trigger delay for each channel The maximum Ringbuffer pretrigger delay value is 1023 Bit 31 26 25 16 10 Function reserved ADC 1 3 5 7 Zeenen aaee 2 4 6 8 Pretrigger Delay value Pretrigger Delay value Ringbuffer Number of delayed samples Pretrigger Delay value 1 25 Gsps 2 5 Gsps 2000 5 9 8 HB HH Ox31f 1023 x 6 2 6138 1023 x 12 2 12276 1023 x 24 24552 4 20 Direct Memory Max Nof Events registers 0x2018 0x3018 fdefine 3305 MAX NOF EVENTS ADC 1 4 0x2018 Page 51 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer define SIS3305_MAX_NOF_EVENTS_ADC5_8 Ox3018 The Sample Logic stops as soon as the Event counter reaches the value of the Direct_Memory_Max_Nof_Events register in Event Direct Memory Mode The Event sample logic runs continuous with Max Nof Events 0 Bit 31 16 15 0 The power up default value is 0 4 21 End Address Threshold registers define SIS3305_END_ADDRESS_THRESHOLD_ADC1_4 0220320 fdefine SIS3305_END_ADDRESS_THRESHOLD_ADC5_8 0x301C These registers define the End Address Threshold values for each A
25. 0 53040 666666666666666 666666666000 54 4 24 Actual Sample address regster nennen 55 4 25 Direct Memory Eege Eeer 55 4 26 Direct Memory Actual Next Event Start address register sass 55 2 27 601173153100016 Value registers sese eege EE 56 4 28 Aurora Protocol Data Status register 0x2058 0x3058 readiwrte 57 4 29 Individual Channel Select Set Veto register 0x2070 0x3070 read write sess 58 4 30 ADC Input tap delay registers 0x2400 UA 58 D PRS CES Ol OTTO eege 59 5 1 General block diagram of one ADC channel IA 59 0 2 JBiiable Sample E 60 x MEN uuu SU mmm 60 Jo yy 61 5 4 1 External Veto 1061517161015111 eegener 62 5 4 2 Memory Overrun Veto LOGIC E 63 e Fe MER SE OVINE e 64 5 5 1 Er gl lal e 64 5 5 2 4 channel Event Direct Memory Start Mode 67 5 5 3 4 channel Event Direct Memory Stop Mode 68 OMEN IR Enn DANTUR 69 6 1 Exent Dau EE EE 70 6 1 1 TDC PIO e Data dg 71 6 1 2 ADC 1 25 Gsps FIFO Event Data format internal Trigger eese 72 6 1 3 ADC 2 5 Gsps FIFO Event Data format internal Trigger sss 74 6 1 4 ADC 5 Gsps FIFO FE yet EIERE EELER 76 6 1 5 ADC Dire
26. 1 2 closed 50 Ohm Termination enabled JP123A Position 3 4 closed 50 Ohm Termination disabled JP123A 9 5 JP124C 50 Ohm Termination NIM VETO IN 50 Ohm termination of the Veto signal 1s enabled or disabled with the jumper JP124C Position 1 2 closed 50 Ohm Termination enabled JP124A Position 3 4 closed 50 Ohm Termination disabled JP124A Page 85 of 97 SIS Documentation SIS3305 ERI innovative 5 GS s 10 bit Digitizer systeme 9 6 J601 JTAG chain The JTAG chain on the SIS3305 can be configured to comprise the serial PROM only short JTAG chain or to comprise the serial PROM and the Virtex FPGA long chain The configuration 1s selected with the 6 pin array J601 as sketched below e e e Long Chain 1 3 and 2 4 closed J601 ENS na an In the Impact software you will see all 5 Xilinx devices as shown below z ISE iMPACT Boundary Scan E File Edit View Operations Output Debug Window Help DPR CONSE em ew Emus 8 i Right click device to select operations 7 0 Gel Boundary Scan SlaveSerial Loe es te 25 tg Direct SPI SystemACE TBI E Create PROM File PROM File Formatter xcf32p sig3305 prom 2 sig3350 prom 2 xcf32p xc4vtx20 5 SH 5 SH bypass bypass bypass TOG Short Chain 3 5 and 4 6 closed factory default Page 86 of 97 SIS Documentation SIS3305 ERI innovative
27. 5 GS s 10 bit Digitizer Trigger Mode and internal Trigger ADC 5 channel 5 Threshold GT 0x262 610 sample Block Length 4 programmed 3 gt 4 x 12 samples 48 samples HEADER_EVENT_ID_1_25G_ADC1 220000 30 33 ca el 24c Bae 313 320 920000 the 9 a0004 80004 a0004 0 78 3e 44 4e 5 CER Ob Th 90 29 39 ITO 210 1 EE Lit 141 1635 187 lab 29a 2ae 2cl 203 262 11 2fe 30a 280 S24 oz 320 26 320 326 32d 32c aa 22e 310 342 gile Innovative systeme Event ID 0 Event Info 0 9 indicates ADC chip 2 gt channel 5 bit 0 of a indicates Trigger GT bit 3 and on 2 position 0x266 4 indicates 4 x 128 bit blocks gt 48 samples HEADER EVENT ID 1 25G ADC1 920000 2e 2e 6f 82 ldo TEY 2556 301 e0004 e0004 0 2e 30 33 34 37 3a 3f 46 50 bO cb e9 108 127 14b 16c 190 97 26d 286 2a0 2b5 2c8 2d9 252 236 219 30a 313 31b 321 324 328 32a 32e 32f a indicates Trigger GT bit 3 and on 6 position Ox26d HEADER EVENT ID l1 25G ADCIl 920000 2e cal 2 b2 219 237 30c 314 c0004 abd547 0 c0004 8 31 SS 38 3b 40 49 51 56 6e CE ec 108 12a 14c 170 192 ipo 7 ZOO 20d 29f 209 209 2dg Zea 2f7 3la SKS 323 2298 Ded 32d 83 520 OD a indicates Trigger GT bit 3 and on 4 position Ox26e 50 1b3 2e8 32T T 1 f9 304 32a Page 73 of 97 SIS Documentation SIS3305 innovative 5 GS s 10 bit Digitizer 0
28. 5 GS s 10 bit Digitizer systeme J601 In the Impact software you will see the two serial Xilinx PROMs as shown below f ISE iMPACT Boundary Scan En File Edit View Operations Output Debug Window Help umi 88 8 8 6 8 3 Flows Ee al Right click device to select operations 8 S38 Boundary Scan Gel SlaveSerial Gel Direct SPI sl SystemACE TBI zi Create PROM File PROM File Formatter xofiz SIS 2208 promi 2 xct32p sijg3350 prom 2 TDG Page 87 of 97 SIS Documentation SIS3305 Seil innovative Systeme 5 GS s 10 bit Digitizer 2 9 7 SW1 SW2 VME Base Address Rotary switches The two rotary switches of SW and SW2 are used to set the base address The function may depend on the setting of switches 1 4 of SW80 also refer to the VME addressing section 3 9 8 SW80 Dip switch Reset Behavior Slave Addressing Watchdog Disable The 8 switches of SW80 are in charge of system controller function reset behaviour and slave addressing as listed in the table below Factory default settings are illustrated on the left hand side of the table Function EN A32 Slave Addressing EN A16 reserved for future slave use EN GEO reserved for future slave use EN RES reserved for future slave use Not used Not used Watchdog enable Connect VME SYSRESET to FPGA reset
29. Data 1 O0 J Temperature Data Bit 0 LSB The power up default value reads 0x80F00nnn The default temperature threshold setting at power up or after a Key Reset command is 90 60 C The Temperature Supervisor Threshold Flag will be set if the value of the Temperature Data is higher than 0 C and higher than the Temperature Threshold value It will be cleared with a power on reset or with clear the Enable Temperature Supervisor bit If the Temperature Supervisor Threshold Flag is set then the Supervisor logic sets the both ADC chips to standby mode under that condition it is no longer possible to write read to from the ADC chips via the SPI interface the logic of the ADC FPGAs are set to the reset state and the ADC clock is turned off The three USER Leds U1 U2 U3 are flashing with 4 Hz to indicate the over temperature state U2 1s inverted to U1 U3 Page 37 of 97 Still Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer The operating temperature ranges from 35 C to 85 C and is covered by the table below Note The Celsius temperature reading is obtained by casting the read data to signed short and dividing the obtained value by 4 0 after float conversion Page 38 of 97 Seabee innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 9 ADC Serial Interface SPI register 0x74 read write define SIS3305_ADC_SERIAL INTERFACE REG 0x74 read write D
30. Key address registers Offset Size in BLT Access j Function TA Pe 0x00000400 4 KA General Reset 25 d 2 Jcd JC C QOG 0x00000410 4 KA Arm Sample Loge 0x00000414 4 KA Disam DisbleSampelogio 0500000418 4 KA Trigger 17 ADC Clock Synchronisation Reset ADC FPGA Logic DDR2 Memory Aurora Interface 0x00000420 0x00000424 0x00000430 0x00000434 JL KA p o KA o KA NENNEN NENNEN 44 KA Te Kalte 0x0000043C 4 KA TriggerOutpulse Page 15 of 97 SIS Documentation SIS3305 innovative LL ARI MD en 3 1 3 ADC group 1 registers Event information ADC group 1 channel 1 4 0x02000 Event configuration register ADC1 chl ch4 0x02004 sample Memory Start address register ADC1 chl ch4 0x02008 Sample Extended Block Length register ADCI ch1 ch4 0x0200C R W Direct Memory Pretrigger Block Length register Bul REN NENNEN 0x02010 Ringbuffer Pretrigger Delay ADCI chl1 ch2 0x02014 Ringbuffer Pretrigger Delay ADC1 ch3 ch4 0x02018 Direct Memory Max Nof Events register ADC1 chl ch4 0x0201C End Address Threshold 0x02020 0x02024 0x02028 0x0202C 0x02030 0x02034 0x02038 0x0203C R W Trigger Gate GT Threshold register ADCI chl RW Trigger Gate LT Threshold register ADC1 ch1 R W Trigger Gate GT
31. Status Enable External Veto Delay Length Logic 8 Set Invert External LEMO Direct Veto In ss Invert External LEMO Direct Veto In 6 Set Enable External LEMO Count In ss Enable External LEMO Count In 0 Switch on user LED Status User 1 LED I LED on O LED OM denotes power up default setting if enabled see LEMO Trigger Out Select register Page 18 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Seabed Innovative systeme If Led Application Mode 0 Led On if Status User 1 LED 1 Status User 2 LED 1 Status User 3 LED 1 Led On if Status User LED 1 Data sampling ADC data transfer to Memory acitve us Data sample logic enabled 4 1 1 Enable for the External LEMO Inputs The logic of the four LEMO inputs 1s illustrated in the diagram below External LEMO Trigger In External Trigger In AND enable Control Reg bit 7 23 E LEM xterna O Count In External Count In AND enable Control Reg bit 6 22 Reg bit 6 22 External LEMO Reset In External Reset In AND enable Control Regio Reg bit 5 21 Note 1 The external inputs are disabled at power up Note 2 The external trigger input is routed to the TDC independent of the status of the enable bit Note 3 The Veto input is not present on cards with Optical Link Medium option Page 19 of 97 SIS Documentation SIS3305 innovative 4 2 Module Id and Firmware Revision Register 0x4 read
32. Threshold register ADCI 2 RW Trigger Gate LT Threshold register ADC1 ch2 R W Trigger Gate GT Threshold register ADC1 3 R W Trigger Gate LT Threshold register ADC1 3 R W Trigger Gate GT Threshold register ADCI ch4 RW Trigger Gate LT Threshold register ADC1 ch4 R Sampling Status ADCI ch1 ch4 1 Actual Sample address register ADC1 ch1 ch4 R Direct Memory Event Counter ADCI chl ch4 Direct Memory Actual Event Start address register ADCI chl ch4 1 Actual Sample Value ADC1 ch1 ch2 1 Actual Sample Value ADCI ch3 ch4 22222222 0x02040 0x02044 0x02048 0x0204C 0x02050 0x02054 0x02058 0x0205C Aurora Protocol Data Status register ADCI Internal Status register ADC1 0x02060 Aurora Protocol TX Live counter ADC1 00 0x02074 0x02078 0x02D7C W W W W Individual Channel Select Set Veto register ADC1 ch1 ch4 reserved reserved reserved 0x02400 Input Tap Delay register ADC1 ch1 ch4 00 Page 16 of 97 SIS Documentation SIS3305 innovative 3 1 4 ADC group 2 registers Event information ADC group 2 channel 5 8 0x03000 Event configuration register ADC2 ch5 ch8 0x03004 Sample Memory Start address register ADC2 ch5 ch8 0x03008 Sample Extended Block Length register ADC2 ch5 ch8 Ox0300C R W _ Direct Memory Pretrigger Block Length register 0x03010 Ringbuffer Pretrigger Delay ADC2 ch5 ch6 0x03014 Ringbuffer Pretrigger Delay ADC2 ch7 ch8 0x03018 D
33. Veto AND mmm 0 External Veto Delay Length Control Reg bit 11 27 Edge Level Control Reg bit 10 26 0 level sensitive l 1 edge sensitive Enable Veto Delay Length Ldgic Control Reg bit 9 25 Gate Mode Control Reg bit 12 28 Do _ Key Set Veto SET Key Veto Logic Key Veto Q Key Clear Veto CLR Enable Control Reg bit 13 29 i Delay and Length Logic Logic External programmed Veto 0 Veto MUX 1 Gate j Memory Overrun Veto Logic atte innovative systeme Channel 1 2 3 4 Veto ADC2 Veto is set if Wr ptr Rd ptr gt of Memory Size Page 61 of 97 SIS Documentation SIS3305 Sable innovative 5 GS s 10 bit Digitizer systeme 5 4 1 External Veto Delay Length Logic The effect of the Invert bits 22 27 Edge sensitivity bits 10 26 and Gate mode bits 12 28 control bits 1s illustrated below ov NIM Level Veto In 0 7 V 1 Logic Level Veto In 0 4 HO Level Mode retriggerable Edge sensitivity 0 Invert Veto In 0 Edge 0 Gate Gate Mode 0 L 1 x 20 ns Invert Veto In 0 Edge 0 Gate Mode 1 L 1 x 20 ns Invert Veto In 7 1 Edge Gate Mode 0 L NIM pulse width L 1 x 20 ns Invert
34. Veto In 1 Edge 0 Gate Mode 1 L 1 x 20 ns L gt NIM pulse width Edge Mode not retriggerable Edge sensitivity 1 leading edge Mode Invert Veto In Edge 1 Gate Mode 0 trailing edge Mode Invert Veto In 7 1 Edge 1 Gate Mode 0 Invert Veto In 0 4 D 0 x 20 ns L 1 x 20 ns Edge 1 Gate Mode 1 leading edge Mode trailing edge Mode Invert Veto In 1 D 1 x 20 ns L 1 x 20 ns Edge 1 Gate Mode 1 Page 62 of 97 SIS Documentation SIS3305 dni innovative 5 GS s 10 bit Digitizer systeme 5 4 2 Memory Overrun Veto Logic The Memory Overrun Veto Flag will be set if the Write Pointer Sample Address the Read Pointer is greater than 4 of the Memory size Page 63 of 97 Still Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 5 5 Event Saving Modes Different Event Saving Modes are implemented to save Events e Event FIFO Mode e Event Direct Memory Start Mode e Event Direct Memory Stop Mode Note refer to the example code in sis3305_adc_tests c where you can find the full setup in the routines int RunTest_SIS 3305_Test_Event_Aguisition void int RunTest SIS3305 Test Direct Memory Start Mode Aquisition void int RunTest SIS3305 Test Direct Memory Stop Mode Aquisition void 5 5 1 Event FIFO Mode The Event FIFO Mode is implemented for events with a maximum size of 3072 samples for each channel Three
35. bit Digitizer CS 4 3 EEprom 93C56 Control Register define SIS3305 EEPROM CONTROL REG 0x28 read write D32 Provides access to the 2kbit onboard eeprom The EEprom is organized as 128 words 1 Read EEprom Busy 30 reserved TM TT 29 reserved MTT 28 EEprom Command WRITE DISABLE OT 27 Eprom Command WRITE ENABLE TTT 26 EEprom Command ERASE 0T 25 EEprom Command WRITE TT 24 EEprom Command READ 0 23 ewemed N TT 22 EEprom Address 666 MTT GI EEprom Addressbt5 20 EEprmAddresbit 9 BEprom Address 3 MN 18 EEprmAddesbi2 MTT 17 EEprmAddesbi 0T 16 EEprom Address 6150 TOT 9 EEprom Write databit9 EEprom Read data bit9 SSS S EEprom Write data bit8 EEprom Read databt 6 EEprmWrtedaabit EEprom Read data bit6 0 EEprmWrtedaabit EEprom Read data bit0 The power up default value reads 0x0 Programming see in sis3305_configuration_readout_lib c read access int ee_93c56_read_word unsigned int moduleAdr unsigned char adr unsigned short data int ee_93c56_read_block unsigned int moduleAdr unsigned char startAdr unsigned short data unsigned char len Page 25 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer write access int ee_93c56_write_word unsigned int moduleAdr unsigned char adr unsigned short data
36. define SIS3305_MODID 0x4 read only D32 7 This register reflects the module identification of the SIS3305 and its minor and major firmware revision levels The major revision level will be used to distinguish between substantial design differences and experiment specific designs while the minor revision level will be used to mark user specific adaptations 3 5 9 Major Revision Bit 8 Major Revision 81 0 6 Minor Revision Bit6 jMimrRevsionBitO 4 2 1 Major revision numbers Find below a table with major revision numbers used to date Application user Page 20 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 3 Interrupt configuration register 0x8 define SIS3305 IRQ CONFIG 0x8 read write D32 This read write register controls the VME interrupt behaviour of the SIS3305 ADC Eight interrupt sources are foreseen for the time being two of them are associated with an interrupt condition the other condition is reserved for future use The interrupter type is DOS 4 3 1 IRQ mode In RORA release on register access mode the interrupt will be pending until the IRQ source is cleared by specific access to the corresponding disable VME IRQ source bit After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again In ROAK release on acknowledge mode the interrupt condition will be cleared and the IRQ s
37. if disabled O _3__ Enable IRQ source 3 Status enable source 3 read as 1 if enabled 0 if disabled Ju 2 _ Enable IRQ source 2 2222 Status enable source 2 read as 1 if enabled 0 if disabled 0 1 _ Enable IRQ source I _ Status enable source 1 read as 1 if enabled 0 if disabled 0 O0 Enable IRQ source O 22 Status enable source 0 read as 1 if enabled 0 if disabled 0 The power up default value reads 0x 00000000 IRQ source 3 reached Address Threshold level sensitive IRQ source 2 reached Address Threshold edge sensitive IRQ source 1 Direct Memory Stopped Flag level sensitive IRQ source 0 Direct Memory Stopped Flag edge sensitive Page 22 of 97 SIS Documentation SIS3305 innovative 4 5 Acquisition control register 0x10 read write define SIS3305 ACQUISITION CONTROL 0x10 read write D32 The acquisition control register is in charge of most of the settings related to the actual configuration of the digitization process Like the control register it is implemented in a J K fashion 9 Seresrwed9 Sumsreered SCSCSC S S S S S S Set reserved t reserved SO 6 Sersrwed Sumsrsrwed 0 SeresrwdO Sumsrsrwed O The power up default value reads 0x0 Direct Memory Event Mode Flag table Direct Memory Direct Memory Clock Source Busy Flag Stopped Flag IA NeBuy
38. int ee_93c56_write_block unsigned int moduleAdr unsigned char startAdr unsigned short data unsigned char len erase to OxFFFF access int ee 93cb56 erase word unsigned int moduleAdr unsigned char adr int ee 93c56 erase block unsigned int moduleAdr unsigned char startAdr unsigned char len lf write and erase accesses need to write enable the device first int ee 93c56 write enable unsigned int moduleAdr int ee 93c56 write disable unsigned int moduleAdr The EEprom information and the offsets as used by the SIS3305 base software are listed in the table below 16 bit ADC mode ADC channel 1 ADC channel 8 address offset 0 IOBTapDeay IOBTap Delay 8 le Phase adjust Phase adjust 16 4channel Gainadjust Gainadjust camel offset adjust offset Gain adjust 32 2 channel A C Gain adjust Gain adjust 40 fachan AE offset adjust set Gainadjust M Heu NEIN 56 2 channel B D Offset adjust Offset Gain adjust OTT po 64 1 channel A _ Gain adjust Gain adjust 72 I channel A Offset adjust Offset Gain adjust 80 1 channel B Gain adjust 1 Lan adjust 88 1 channel B Offset adjust Offset Gain adjust 96 l channel C Gain adjust Loan ning 104 l channel C _ Offset adjust Offset Gain adjust 112 l channel D _ Gain adjust Gain adjust 120 l channel D Of
39. like define SIS3305 CONTROL STATUS 0x0 read write D32 refers to the SIS3305 h header file 4 1 Control Status Register 0x0 write read define SIS3305 CONTROL STATUS 0x0 read write D32 The control register is implemented as a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time The same register represents the status register on read access GI Clear Control LEMO Trigger MN TT 30 Clearreserved 4 MTT 29 Clear Enable Memory Overrun Veo C o O 28 Clear Gate Mode External Veto In Delay Length Logic C Ju 27 Clear Invert External Veto In Delay Length Logic 5 J0 26 Clear Edge sensitive External Veto Delay Length Loge 9 0 TT 25 Clear Enable External LEMO Veto Delay Length Logic 0 TT 24 Clear Invert External LEMO Direct Veton Ji 23 Clear Enable External LEMO Trigger O0 TT 22 Clear Enable External LEMO Count n 0T 21 Clear Enable External LEMO Reset n 09 0T 20 Clear Enable External LEMO Direct Veton Ju 19 Clear Led Application Mode 18 Swichoffuer3LED MTT 17 Switch offuser 2LED MTT H6 SwichoffuerTLED 0 9 Set Enable External LEMO Veto Delay Length Logic
40. synchronous Mode external trigger gate all channels record data at the same time asynchronous Mode internal trigger gate each channel group records data individually Page 48 of 97 Seale innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 16 Sample Memory Start Address registers 0x2004 0x3004 define 305_ SAMPLE START ADDRESS ADC1 4 0x2004 define S1953305 SAMPLE START ADDRESS AIDCH 8 0x3004 These registers define the memory start address The value is given in 512 bit blocks 16 32 bit words 23 0 Function reserved Sample Memory Start Address 512 bit blocks 32 bit word address x 16 The power up default value is 0 Explanation sample memory start address The contents of the sample memory start address register is assigned as memory data storage address with the arm command key address arm sample logic or with the enable command key address enable sample logic Page 49 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 17 Sample Extended Block Length registers 0x2008 0x3008 define 8 305 SAMPLE LENGTH ADC1 4 0x2008 define 5 305 SAMPLE LENGTH ADC5 8 0x3008 This register set defines the number of sample blocks of each ADC Event or the number of extended sample blocks depending on the Trigger Gate mode The size of one sample block for each ADC channel is 128 bit 1 e 4 x 32 bit word 12 samples The m
41. the sample logic 4 14 4 Key address Trigger define SIS3305 KEY TRIGGER 0x418 write only D32 A write with arbitrary data to this register key address will generate a trigger 4 14 5 Key address Enable sample logic define SIS3305 KEY ENABLE Ox41C write only D32 A write with arbitrary data to this register key address will enable the sample logic 4 14 6 Key address Set Veto define SIS3305 KEY SET VETO 0x420 write only D32 A write with arbitrary data to this register key address will set the Veto function 4 14 7 Key address Clear Veto define SIS3305 KEY CLR VETO 0x424 write only D32 A write with arbitrary data to this register key address will clear the Veto function Page 44 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 14 8 Key address ADC Clock Synchronization define SIS3305 ADC SYNCH PULSE 0x430 write only D32 A write with arbitrary data to this register key address makes the ADC out clock signals go low and resets the ISERDES Logic in the FPGA for the ADC data The ADC out clock signals restart after TDR pipeline delay a certain number of input clock cycles which is programmed via the SPI in the SYNCH register This command is necessary to synchronize the four ADC channels within the ADC chips 4 14 9 Key address Reset ADC FPGA Logic define SIS3305 ADC FPGA RESET 0x434 write only D32 A write with arbitrary data to t
42. 1 OX2 i 512 bit block ET 128 bit block ES 32 bit f 0x2 i 128 bit block ES 32 bit 0x3 Ox7F FFFF 512 bit block 0x80 0000 512 bit block 0x80 0001 512 bit block 0x80 0002 512 bit block 0 essen 512 bit block 128 bit block 32 bit ees OxFFF FFFC 128 bit block 32 bit Le OxFFF FFFD 128 bit block EN 32 bit l OxFFF FFFE 128 bit block ODD iL OxFFF FFFF Page 69 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 61 Event Data formats ADC and TDC events are stored to memory tagged with an event ID The event ID 1s used to distinguish between the different event types Event ID table Event Type 0x0 1 25 Gsps ADC 1 FIFO Event Data Format internal trigger 1 25 Gsps ADC 2 FIFO Event Data Format internal trigger 0x2 1 25 Gsps ADC 3 FIFO Event Data Format internal trigger 0x3 1 25 Gsps ADC 4 FIFO Event Data Format internal trigger 2 5 Gsps ADC 1 2 FIFO Event Data Format internal trigger C NE 2 5 Gsps ADC 3 4 FIFO Event Data Format internal trigger 0x6 reserved e Gsps ADC 1 2 3 4 FIFO Event Format Data SGsps internal trigger or 1 25 2 5 5Gsps global 5 trigger E 9 FIFO Event Data Format reserved a C e OD ADC Dieet Memory Wrap Stop Mode Ent Deta Formet obale
43. 138 for each channel ADC Input signal Delayed ADC signal Ringbuffer Delay Pre Post External Trigger Start Event X with N samples Memory Event 1 Event 2 Event 3 Header sample memory start address Page 67 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 5 5 3 4 channel Event Direct Memory Stop Mode The logic saves the ADC values of 4 channels to memory in one data block with a header in 4 channel Event Direct Memory Stop Mode The sampling of the ADC data starts immediately with sample logic is enabled The logic writes immediately to memory in a wrap around mode if the sample logic is enabled The Sample ADC Data Start Address is the programmed Sample Memory Start Address Header Length The Sample Address will be incremented up to the programmable Sample Block Length and start then again from the Sample ADC Data Start Address Stop Mode is recommended if the required Pre Trigger Length is greater than the maximum of the Ringbuffer Delay programmable Event Length up to e 4x 201 326 592 1 25Gsps e 2x 402 653 184 2 5Gsps e 1x 805 306 368 SGsps programmable Number of Events Multi Event programmable Ringbuffer Delay to delay of the ADC data 6 to 6138 for each channel programmable Direct Memory Pretrigger Delay ADC Input signal Delayed ADC signal Ringbuffer Delay L Pre Post R
44. 30 unused StatusIRQ source 6 reserved 0 29 unused Status IRQ source 5 reserved JI 28 unused Status IRQ source 4 reserve 0 Status IRQ source 3 End Address Threshold Flag level sensitive 0 26 unused Status IRQ source 2 End Address Threshold Flag edge sensitive O 25 unused Status IRQ source 1 Direct Memory Stopped Flag level sensitive 24 unused Status IRQ source 0 Direct Memory Stopped edge sensitive 0 23 Disable Clear IRQ source7 Statusflagsource7 0 _22 Disable Clear IRQ source6 Statusflagsource6 21 Disable Clear IRQ source5 Statusflagsouce 3 0 20 Disable Clear IRQ source 4 Status flagsource4 Cd 19 Disable Clear IRQ source 3___ Status flag source 3 0 _18 Disable Clear IRQ source Status flag source 0 17 Disable Clear IRQ source 1 Status flag source bd 16 Disable Clear IRQ source 0 Statusflagsouce UH 15 unused StausVMEIRQ O 14 unsd Statusintemal IRQ 13 funused 0 O 12 umelle 11 unused JI 10 funused 0 OO 9 unused 0 OO 8 unused 0 7 _ Enable IRQ source 7 Status enable source 7 read as 1 if enabled 0 if disabled Ju 6 Enable IRQ source 6 Status enable source 6 read as 1 if enabled 0 if disabled 0 5 Enable IRQ source 5 Statusenablesource 5 read as 1 if enabled 0 if disabled 0 4 _ Enable IRQ source 4 Status enable source 4 read as 1 if enabled 0
45. 313 RW 0x00000020 R W TDC test register only SIS internal use 0x00000024 R W TDC test register only SIS internal use 0x00000028 R W EEprom 93056 control register 0x0000002C R W EEprom DS2430 onewire control register 0x00000030 CBLT Broadcast Setup register 0x00000034 0x00000038 0x0000003C 4 OOOO R W reserved Keel TDC Write Cmd register TDC Status register TDC Read Cmd register TDC Read value register TDC Start Stop Enable register TDC FSM Reg4 value used for TDC Master Reset register 0x00000050 0x00000054 0x00000058 R W R W R W R W R W R W R W R W R W R W R W R W 0x0000005C R W Page 14 of 97 SIS Documentation SIS3305 innovative GS s 10 bit Digitizer YT 0x00000060 RW XILINX JTAG_TEST JTAG_DATA_IN 0x00000070 RW Temperature and Temperature Supervisor Register 0x00000074 Wonly ADC Serial Interface SPI register 0200000000 RW 61001 chi ch4 FPGA Data Transfer Control register 202000000064 R W ADC2 ch5 ch8 FPGA Data Transfer Control register 0200000008 Ronly ADCI chl ch4 FPGA Data Transfer Status register 0200000000 Ronly ADC2 ch5 ch8 FPGA Data Transfer Status register 0x00000000 Ronly Aurora Protocol Status 0x00000004 Ko Aurora Data Status a 3 1 2
46. 32 Several parameters of the 10 bit 5 GS s ADC 2 EV10AQ190 chip like gain 1 GHz full bandwidth offset phase calibration e g can be configured with the SPI serial Peripheral Interface The SPI register is the interface between the 5183305 VME FPGA and the ADC SPIs Please refer to the documentation of the EV10AQ190 ADC chip for details Write Read Logic BUSY Flag pe Set ADC Standby Logic Busy Flag PEN Force ADC Standby Flag ADC Select Bit 23 Write Cmd 22 Address Din 21 AddressBitS j 20 Address Bit4 S 19 Address Bit3 le 18 AddesBit2 le 17 AddesBit le 16 AddressBitO Write Data Bit 14 Read Data Bit 14 Write Data Bit Read Data Bit 1 0 Write Data Bit 0 LSB Read Data Bit 0 LSB The power up default value is 0 Programming see in 153305 configuration readout lib c int SIS3305_ADC_SPI_Setup unsigned int module addr struct SISSS205 ADC SPI Contig 7 5121 8533 05 ADC SPI configuration Struct Page 39 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 10 ADC1 ch1 ch4 ADC2 ch5 8 FPGA Data Transfer Control register 0xCO 0xC4 define S1S3305 DATA TRANSFER ADC1 4 CTRL REG O0xCO read write D32 define SIS3305 DATA TRANSFER ADC5 8 CTRL REG OxC4 read write D32 With a write to this these register s the fast data transfer logic 5GBit serial interface between the ADC FPGA and VME FPGA will execu
47. 5 2 Enable Sample Logic The schematic of the sample logic 15 shown below External Trigger In Key Enable Sample Logic Key Trigger SET Key ArmS le Logi ey Arm Sample Logic S SET Sample Logic Enabled p Clear Key Reset Key Disable Sample Logic Br Clear 5 3 Triggering The schematic of the trigger logic of the ADC1 channel 1 4 is shown below e 5 2 7 Key Address Trigger External Trigger In AND Enable global Trigger Gate Event configuration register bit 5 Channel 1 2 3 4 Trigger Gate Enable internal Trigger Gate Event configuration register bit 6 Individual Channel 1 2 3 4 Trigger Gate Te d Page 60 of 97 SIS Documentation 5 4 Veto The schematic of the Veto logic of the ADCI channel 1 4 is shown below Veto Select Veto Channel 1 2 3 4 SIS3305 5 GS s 10 bit Digitizer Individual Channel Select Set Veto register bit 4 5 6 7 Set Veto Channel 1 2 3 4 Individual Channel Select Set Veto register bit 0 1 2 3 The schematic of the global veto logic is shown below Invert Direct Veto In Control Reg bit 8 24 External LEMO Veto In Enable Control Reg bit 4 20 0 Straigth MUX 1 Invert Invert Veto In Delay Length logic 1 Invert MI 0 Straigth AND External Direct Veto Logic External direct
48. 5 base sis3150usb_winusb Dateiardner 27 08 2010 18 26 M E d tel Cjsis3305 base sis3150usb cvpress Dateiardner 27 08 2010 18 26 E Neuen Ordner erstellen Csis3305 base sissi x Dateiordner 22 02 2011 17 30 E Ordner im web verdffentlichen 153305 base sis3150usb winusb is for operation with the SIS3150USB to VME interface and the standard Windows USB driver installed 51853305 base sis3150usb cypress is for operation with the SIS3150USB to VME interface under a Cypress USB driver installation and sis3305_base sis310x for all SIS1100 e 310x PCI Express to VME interfaces 10 2 Software examples The 5153305 software win directory has the structure shown below PF 5 Datei Bearbeiten Ansicht Favoriten Extras 3 zur ck e 3 ky CR Suchen TE Ordner HE Adresse E U sisdvd03061 11sis33051s0ftwaretwin Mame Grate T Ge ndert am Datei und Ordneraufgaben Y VisualC 2008 applications Dateiordner 27 08 2010 18 25 sis3305_ header Dateiordner 27 08 2010 18 25 Andere Orte Y tsis 3305 library Dateiordner 27 08 2010 125 ysis_vme_master lib Dateiordner 27 08 2010 18 25 Details y cvi affline Dateiordner 27 08 2010 18 26 Dateiordner 27 8 2010 18 26 The SIS3305 h file can be found in the s1s3305 header directory and the s153305 library directory contains library elements for SIS3305 operation The VisualC 2008 applications folder holds code for firmware upgrade over VME The source code and th
49. 6 1 3 ADC 2 5 Gsps FIFO Event Data format internal Trigger ADC Fifo Event 2 5 Gsps internal Trigger Event ID 4 for Channel 1 2 Event ID 5 for Channel 3 4 Header 4 x 32 bit words 31 28 27 24 23 16 15 Event ID Event Header Info Event Header ID Timestamp 47 32 Timestamp 31 0 Counter 40MHz 31 0 ADC2 4 ADC 1 3 Length 15 0 in Data blocks Trigger Index Trigger Index 1 Data Block 8 x 32 bit words sample 1 9 0 sample 3 sample 5 sample 7 sample 9 sample 11 sample 13 sample 15 sample 17 sample 19 sample 21 sample 23 sample 2 9 0 sample 4 sample 6 sample 8 sample 10 sample 12 sample 14 sample 16 sample 18 sample 20 sample 22 sample 24 Page 74 of 97 SIS Documentation Examples Trigger Mode and internal Trigger ADC 5 6 channel 5 Threshold GT 0x262 610 SIS3305 5 GS s 10 bit Digitizer gile 1111073176 systeme Sample Block Length 4 programmed 3 gt 4 x 24 samples 96 samples HEADER EVENT ID 2 5G ADCIZ2 41920000 35 34 37 38 ad a6 9b b2 Lei 203 1f1 20e zo045 Zod 201 2ce 41920000 the 9 e00004 HEADER EVENT ID 2 5G ADCIZ2 41920000 3d 41 42 48 114 134 123 141 278 27 2e1 4 2df 1 990004 3deac70 35 29 3b Sc be 05 go eb 216 236 226 23e 2da 2da 2da 207 38
50. 821010781018 66 6666 11 4 MET SSE SE RD ees 04 IB 05 DIO Page 5 of 7 SIS Documentation SIS3305 518 90 innovative systeme 5 GS s 10 bit Digitizer 1 Introduction The SIS3305 is our first digitizer card with GS s sampling speed It s resolution of 10 bit in combination with the high channel count in 1 25 GS s mode of operation makes it perfectly suited for many mid channel count applications in Particle Physics Synchrotron Radiation accelerator controls and related applications Two digitizer chips from e2v Technologies with 4 ADC cores each are used on the SIS3305 The flexible architecture of the digitizers with an analog cross bar on chip clock logic and adjustable gain and offset allow for interleaved operation at 2 5 GS s and 5 GS s Applications comprise but are not limited to e MCP readout e Fast detector readout e Accelerator machine controls SIS3305 with veto input option As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals html 1 1 Related documents A list of available firmware designs can be retrieved from http www struck de sis3305firm html Page 6 of 97 Seabed Innovative systeme SIS
51. DC 1 25 Gsps FIFO Event Data format internal Trigger ADC Fifo Event 1 25 Gsps internal Trigger Event ID 0 for Channel 1 Event ID 1 for Channel 2 Event ID 2 for Channel 3 Event ID 3 for Channel 4 Header 4 x 32 bit words 31 28 27 24 23 16 15 Event Header ID Event ID Event Header Info Timestamp 47 32 Timestamp 31 0 Counter 40MHz 31 0 Trigger Index Length 15 0 in Data blocks 1 Data Block 4 x 32 bit words sample 1 9 0 sample 2 sample 3 2 Data Block sample 4 sample 5 sample 6 sample 13 9 0 sample 14 sample 15 sample 16 sample 17 sample 18 sample 19 sample 20 sample 21 sample 22 sample 23 sample 24 Event Cnt 4 bit TDC Event Counter It counts the External Trigger In pulses Event Header Info programmable by the Event configuration registers Event Header ID programmable by the Event configuration registers Timestamp see TDC FIFO Event Counter 40M Hz see TDC FIFO Event Trigger Index 4 bit value it indicates the point in time of the internal trigger inside a 6 sample group marked yellow The point in time of a 6 sample eroup depends on the Ringbuffer Predelay Bit 3 indicates trigger condition GT else LT Bit 2 0 indicates trigger position inside the 6 sample group 1 to 6 Page 72 of 97 SIS Documentation SIS3305 Examples
52. DC channel group The value of the Actual Next Sample address counter will be compared with the value of the End Address Threshold register The value 1s given in 512 bit Blocks 1 e 32 bit word address x 16 Function reserved Sample Memory End Address Threshold in 512 bit Blocks 32 bit word address x 16 The power up default value is 0 Page 52 of 97 Seabed Innovative systeme SIS3305 5 GS s 10 bit Digitizer SIS Documentation 4 22 Trigger Gate Threshold registers define SIS3305_TRIGGER_GATE_GT_THRESHOLDS_ADC1 0x2020 define S1S3305 TRIGGER GATE LT THRESHOLDS ADCI1 0x2024 fdefine S1S3305 TRIGGER GATE GT THRESHOLDS ADC2 0x2028 fdefine S1S3305 TRIGGER GATE LT THRESHOLDS ADC2 xZ0Z2C define S13S3305 TRIGGER GATE GT THRESHOLDS ADC3 0x20350 define SIS3305 TRIGGER GATE LT THRESHOLDS ADC3 0x2034 fdefine S13S3305 TRIGGER GATE GT THRESHOLDS 4 0x2039 fdefine S13S3305 TRIGGER GATE LT THRESHOLDS 4 0x203C define S13S3305 TRIGGER GATE GT THRESHOLDS ADC5 0x3020 define S13S3305 TRIGGER GATE LT THRESHOLDS ADC5 0x3024 define S1S3305 TRIGGER GATE GT THRESHOLDS ADCO 0x3028 define S183305 TRIGGER GATE LT THRESHOLDS 6 0x 302C define SIS3305 TRIGGER GATE GT THRESHOLDS ADC 7 0xo050 fdefine SIS3305 TRIGGER GATE LT THRESHOLDS ADC 7 0x3034 define S1S3305 TRIGGER GATE GT THRESHOLDS ADCB8 0x3038 define S1IS3305 TRIGGER GATE LT THRESHOLDS ADCH 02230307 4 22 1 Threshold Trigger Gate GT Bit 31 3026 2516 150 90
53. Documentation SIS3305 5 GS s 10 bit Digitizer 2 Technical Properties Features 2 1 Benefits High speed digitization with good resolution Low noise fixed gain input stage High channel density Fast readout Minimal event to event deadtime Availability of turnkey systems with ready to run software 2 2 Key functionality Find below a list of key features of the SIS3305 digitizer 8 4 2 channels with 1 25 GS s 2 5 GS s or 5 GS s sampling speed 10 bit resolution 2 GByte memory ACAM GPX TDC external internal clock multi event mode read on the fly actual sample value pre post trigger option readout in parallel to acquisition trigger generation sparsification differential clock output two SMA connectors differential clock input two SMA connectors 4 channel input piggy back A32 D32 BLT32 MBLT64 2e SSTVME VME64x Connectors operation in standard crate supported VME64x Front panel VME64x extractor handles 5 12 and 12 V VME standard voltages Optical 4 Gigabit link connection option or Veto input option 2 3 Input Stage Options At this point in time the following input stage piggies are available Coupling Bandwidth SIS3305 PAD SMA DC J 1V 41V 1 8 GHz SIS3305 DAD LEMO 1 V 1V 400 MHz LEMO Feel free to inquire about custom input stage developments Page 7 of 97 SIS Documentation SIS3305 innovative LLL S GS s 10 bit Digitizer D 2 4 Module design A simplified b
54. Event FIFO Modes are implemented e 4 channel Event FIFO Mode asynchronous mode 5 Gsps or synchronous mode 5Gsps 2 5Gsps 1 25Gsps e 2 channel Event FIFO Mode synchronous Mode 2 5Gsps e l channel Event FIFO Mode synchronous Mode 1 25Gsps Page 64 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 5 5 1 1 4 channel Event FIFO Mode In 4 channel Event FIFO Mode the logic saves the ADC values of 4 channels in one Data Block This mode is used to save 5Gsps Events which are triggered externally global trigger synchronous or triggered internally or of channel 1 to 4 triggers asynchronous This mode is also used to save 1 25Gsps 2 5Gsps Events which are triggered externally global trigger synchronous Channel 1 Veto ADC FPGA Veto Logic Channel 1 2 3 4 Sample Logic Channel 4 Trigger Gate Channel 3 Trigger Gate ADC FPGA Trigger Gate or Logic Channel 2 Trigger Gate Channel 1 Trigger Gate 5 5 1 2 2 channel Event FIFO Mode In 2 channel Event FIFO Mode the logic saves the ADC values of 2 channels in one Data Block This mode is used to save 2 5Gsps Events which are triggered internally Cor of channel 1 to 2 triggers and or of channel 3 to 4 triggers Channel 3 Veto ADC FPGA Veto Logic Channel 3 4 Sample Logic Channel 1 Veto Channel 4 Trigger Gate ADC FPGA Channel 3 Trigger Gate SR Trigger Gate Logic Channel 2 Trigger Gate
55. ILA 0 gibale Air gagne yuan g HH EE ET E d KK E ee E ae KANKKKKKKKKKKNK KK d NUR BORSA m AA RV DS CW RR RR EW CNN EK EW NET RTT d ERSAT EE Pg EEF Bang dd 7 E i PUR TU be Se Se Se D Du Se oe TT Te T Tes Ta ta Se gy De yy Fay D D Ser Fig EE Vixwnnxannneanh L
56. Seabee Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer SIS3305 5 GS s 2 5 GS s 1 25 GS s 10 bit VME Digitizer User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 4 49 0 40 60 87 305 20 email info struck de http www struck de Version sis3305 M 0x1009 1 v120 doc as of 06 06 2011 Page 1 of 97 Seale innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer Revision Table Modification Generation EV10EQ190 block diagram Ox1005 firmware Veto length logic Mention bandwidth in SPI section Change in SW80 default setting 1 10 08 03 11 0 1 007 firmware modified Veto Delay Length logic add Direct Memory Start Mode add Direct Memory Wrap Stop Mode 1 20 06 06 11 0x1008 0x1009 firmware add ADC FPGA Individual Select Set Veto logic add Memory Overrun Veto logic Page 2 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer Table of contents AOS 0 1 1 1 E 000000 3 MANO e 6 1 1 Related E 6 2 100111161 EE 7 2 1 BCU UU ais det 000 E AE E 7 SEELEN 7 2 9 DOD E O 7 E BVOC E A E I IA O E 8 2 4 1 EE OE E O a E O O 9 2 4 2 EV10EQ190 Digitizer ADC Chm sss 9 2 4 3 OT A ere 10 2 4 4 CE 10 2 4 5 Trigger control pre post start stop and gate mode 10 2 4 6 Internal Trie ger Pell
57. Trigger Source Threshold Peaking Gap Pulse 3 E 0 bonu Length Length Key Trigger v Internal Trigger Iess H ADCA disable C MES Lemo In Key Timestamp Clear Invert Lemo In NIM ADC3T disable xa 1 LVDS In Event Time s ADC2 disable F i 1 FIR GT rising E 2 RAW SIGNALS 54 8 53 8 52 8 51 8 50 8 43 8 B 116 Number of Events Timestamp sec ADC4 1 3 774211582 Number of Events Timestamp sec ADC3 4 1 3 774211692 Number of Events Timestamp sec ADC2 4 1 3 774211692 Number of Events Timestamp sec ADCI 1 11 758703720 an 0 i XZoom lt i A EL 80 X Min Scale i E 1 X Mas Scale E show ADC 1 S Zooming Fitting IV X Autoscale Y Autoscale Auto Delete Raw Graph ijm X 2 d start 5153350 Test 5153350 ADC Test 27 ef 09 55 Page 89 of 97 SIS Documentation SIS3305 ERI innovative 5 GS s 10 bit Digitizer systeme Three different precompiled versions of the SIS3305 base program can be found on the DVD as shown below ae E Fa ay pem LL LL EE IT tg x9 Il BAI I x2 Es Datei Bearbeiten Ansicht Favoriten Extras 7 Zur ck e gt T Si JO Suchen Ki Ordner Hab Adresse C U sisdvd03061 1 sis3305 software win ci Mame Grote T Ge ndert am Datei und Ordneraufgaben si30
58. With version 1006 and lower write to addr 0x200c 0x300c With version 1007 and higher write to addr 0x2058 0x3058 with datum 0x5555aaaa 31 0 Q gn _ _ ee 23 0 gt O ASO 9 Prot_Soft_Error_Latch bil 8 Pro Hard Eror Latchbit 79 0 6 Prtgtclklocked O ProHardemorflg Note After power up and the links locked the reading will be 0x03780358 after a clear error latch bit cycle the reading should be 0x00780058 Page 57 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 29 Individual Channel Select Set Veto register 0x2070 0x3070 read write define SIS3305_INDIVIDUAL_SELECT_SET_VETO_ADC1_4 OxZ070 7 FOV Doz wy define SIS3305_INDIVIDUAL_SELECT_SET_VETO_ADC5_8 0569070 7 uw D32 y These two registers are used to include exclude channels from the external veto and to veto channels directly Refer to the illustration in section 5 4 also Eed 9 reserved 8 Select Veto TDC Event 6 Select Veto ADC Channel 3 Set Veto ADC Channel 2 6 0 Set Veto ADC Channel 1 5 Note the power up value is 0x0 4 30 ADC Input tap delay registers 0x2400 0x3400 define SIS3305_ADC_INPUT_TAP_DELAY_ADC1_4 0x2400 define SIS3305_ADC_INPUT_TAP_DELAY_ADC5_8 0x3400 The input tap delay registers are used to adjust the ADC FPGA data strobe timing Bt piu 11 0 9 Js e Jan Func
59. ata read access int ee_ds2430_read_byte unsigned int moduleAdr unsigned char adr unsigned char data int ee ds2430 read block unsigned int moduleAdr unsigned char startAdr unsigned char data unsigned char len write access int ee ds2430 write byte unsigned int moduleAdr unsigned char adr unsigned char data int ee ds2430 write block unsigned int moduleAdr unsigned char startAdr unsigned char data unsigned char len erase to OxFFFF access int ee ds2430 erase byte unsigned int moduleAdr unsigned char adr int ee ds2430 erase block unsigned int moduleAdr unsigned char startAdr unsigned char len Struck definition of the DS2430 contents _8 bit address offset O Struck Serial Number lower byte Struck Serial Number upper byte 2 User Serial Number lower byte 3 User Serial Number upper byte 4 TDC HSDiv value High speed divider PLL E free Page 28 of 97 Wie Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 4 Broadcast setup register define SIS3305 CBLT BROADCAST 0x30 read write D32 7 This read write register defines whether the SIS3305 will participate in a Broadcast The configuration of this register and the registers of other participating modules is essential for proper Broadcast behaviour Bit Function Broadcast address bit 31 Broadcast address bit 30 Broadcast address bit 29 Broadcast add
60. aximum number of Sample Extended Block Length depends on the ADC Event Saving Mode Valid for ADC Event Saving Modes 0 1 and 4 Event FIFO Mode Bit 7 0 Function sample Extended Block Length default after Reset 0x0 Note the maximum ADC Event size for one ADC channel is 3072 samples The logic stops the ADC event sampling after 3072 samples in gate mode Valid for ADC Event Saving Modes 6 and 7 Event Direct Memory Mode Bit 31 24 23 0 Function Sample Extended Block Length default after Reset 0x0 Sample Extended Number of Number of samples Block Length 128 bit blocks 1 25 Gsps 2 5 Gsps 5 Gsps n N 1 x 12 N 1 x 24 N 1 x 48 3072 6144 12288 Valid for ADC Event Saving Modes 6 and 7 Direct Memory Mode Oxft ffff 16 777 216 201 326 592 402 653 184 805 306 368 Page 50 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 18 Direct Memory Stop Pretrigger Block Length registers Ox200C 0x300C define SIS3305_SAMPLE_PRE_TRIGGER_LENGTH_ADC1_4 0 20 00 define SIS3305_SAMPLE_PRE_TRIGGER_LENGTH_ADC5_8 Ox300C These registers define the pretrigger number of sample blocks of each Event in Direct Memory Stop Wrap Mode ADC Event Saving Mode 7 The size of one sample block for each ADC channel is 128 bit 4 x 32 bit word 12 samples Valid for ADC Event Saving Mode 7 Direct Memory Stop Wrap Mode 230 Pretrigger Block Length
61. ct Memory Event Data format external TrIgSEr sss sess 78 7 OA EE 79 Or Geert an E Mm 80 8 1 Font Prine E KC 81 Se 10011671717 5 EE 81 SI PR ELED E 82 9 e ee E E 83 9 1 3 7 E 83 9 2 10120 50 Ohm Termination NIM TRIGGER IN 84 9 3 JP122A 50 Ohm Termination NIM COUNT IN 84 9 4 JP123A 50 Ohm Termination NIM RESET 00 666 85 9 5 JP124C 50 Ohm Termination NIM VETO IN 85 E 1 E THIS 86 9 7 SW1 SW2 VME Base Address Rotary switches assesses 88 9 8 SW80 Dip switch Reset Behavior Slave Addressing Watchdog Disable 666666666666666 6660666 88 MO UTM SCI EE T m 89 10 1 gt 5153305090886 PRO ST AM E 89 10 2 SOIWar EX ADDIE a 90 Page 4 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Salaa Innovative systeme 5 57 RET TEE 9 DL DR Seet e E 9 I2 Operam condi 0 ETE TOT 91 ES wt 91 9 6666666660660 66666666666666 Non Hot swap live insertion 11 2 2 ER NE iiid RR 92 03 0 606 6 666666666666666 Row d and z Pin 881
62. e 10 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Wie Innovative systeme 2 5 TDC The TDC on the SIS3305 is used to measure the time between the external start signal and it s ADC FPGA clock synchronized stop signal for the two ADC groups The TDC information Stop 1 and Stop 2 values is used in the process of ADC data timing rearrangement External LEMO Trigger In NIM Control Data 10 LVPECL VME L Fanout FPGA Trg In ADC Clock 2 5 GHz Trg In Synch Trg ADC2 Stop2 TDC value ADC 6 Clock 4 EG p 625 MHz Trg In Synch Trg ADC1 Stop1 TDC val ADc1 LARC 4 EA op value The TDC Measurement logic is implemented in the VME FPGA If the Sample Logic and the TDC Measurement logic are enabled Acquisition register bit 4 1 and the TDC is configured then it handles the timing measurement of the TDC The stop values in steps of 27ps are written to the corresponding ADC FPGA to get the timing information relative to the internal timestamp for each TDC measurement Start to Stop1 2 The maximal trigger in rate is limited to 500kHz ADC Clock 2 5 GHz ADC1 Clock 625 MHz ADC1 FPGA Clock 625 MHz 3 208 33MHz ADC2 Clock 625 MHz ADC2 FPGA Clock 625 MHz 3 208 33MHz Trigger In TDC Start TDC Stop 1 ADC1 FPGA Timestamp Clear Store l 1 l TDC Stop 2 ADC1 FPGA Timestamp Clear Store 1 l i Stop1 TDC value x 2 ps Stop2 TDC va
63. e Value registers define S1IS83305 ACTUAL SAMPLE VALUE ADC12 define 1 3305 ACTUAL SAMPLE VALUE ADC34 define S1S83305 ACTUAL SAMPLE VALUE ADC56 define SIS3305 ACTUAL SAMPLE VALUE ADC78 Read on the fly of the actual converted ADC values 0x2050 0x2054 0x3050 0x3054 Sigil Innovative read read read read systeme ny Py a ae The read only registers are updated with every ADC clock unless a concurrent VME read access 1S pending The register contents is refreshed and can be read any time 1 e they are updated independent of the unarmed armed sampling state as long as a sampling clock 1s distributed on the ADC board internal clock or active clocking external clock Bit 3126 2516 J I50 9 0 Function ADC 1 3 5 7 ADC 2 4 6 8 10 bit data 10 bit data Page 56 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 28 Aurora Protocol Data Status register 0x2058 0x3058 read write define SIS3305 FPGA AURORA STATUS ADC1 4 0x2058 read write D32 define SIS3305 FPGA AURORA STATUS ADC5 8 0x3058 read write D32 define 8183305 FPGA AURORA STATUS KEY CLEAR ADC1 4 0x200C wr D32 define SI1S3305 FPGA AURORA STATUS KEY CLEAR ADC5 8 0x300C wr D32 These registers hold the ADC FPGA Status of the Aurora Protocol and Data Links between the ADC FPGAs U11 and U21 and the VME FPGA Note Clear Error_Latch bits
64. e distribution kits for National Instruments Labwindows CVI can be found n the CVI directory for SIS3150USB and SIS1100 e 310x interfaces as above The sis3305 adc test c file has routines like int RunTest SIS3305 Test Direct Memory Stop Mode Aquisition void With step by step commented setup Page 90 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 11 Appendix 11 1 Power consumption The SIS3305 uses standard VME voltages only 12 5 A 11 2 Operating conditions 11 2 1 Cooling Although the SIS3305 is mainly a 2 5 and 3 3 V low power design massive power 1s consumed by the Analog to Digital converter chips FPGAs and linear regulators however Hence forced air flow is required for the operation of the board The board may be operated in a non condensing environment at an ambient temperature between 10 and 25 Celsius A power up warm up time of some 10 minutes is recommended to ensure equilibrium on board temperature conditions Note an over temperature protection mechanism is implemented to avoid damage to the ADC and FPGA chips refer to section 4 8 11 2 2 Non Hot swap live insertion Please note that the VME standard does not support hot swap by default and that the SIS3305 is not hot pluggable The VME crate has to be powered down for 5153305 module insertion and removal Page 91 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer
65. e than one unit shipped in one batch a set of addresses like 0x41000000 0x42000000 0x43000000 may be used also e The 16 jumper allows for a future changed addressing scheme with different resource allocation Page 13 of 97 SIS Documentation SIS3305 innovative 3 1 Address Map Overview The SIS3305 resources and their locations are listed in the tables below Note Write access to a key address KA with arbitrary data invokes the respective action Function 0x000000 0x0000FC W R VME FPGA registers 0x000400 0x00043C Wonly VME FPGA key addresses with Broadcast functionality 0x002000 Ox002FFC R W ADCI chi chd FPGA registers 0x003000 0003552 R W ADC2 ch5 ch8 FPGA registers 0x008000 OxOOBFFC R W ADCIchl ch4 Memory Data FIFO 0x00C000 OxOOFFFC R W ADC2 ch5 ch8 Memory Data FIFO Lor 0x800000 OxBFFFFC R W ADCIchl ch4 Memory Data FIFO 02000000 OxFFFFFC R W ADC 2ch ch8 Memory Data FIFO 3 1 1 VME FPGA registers Offset Size in BLT Access Function Bytes 000000000 4 WR Control Status Register Q K register 1 000000004 4 Ronly Module Id and Firmware Revision register 000000008 4 RW Interrupt configuration register 000000006 A RW Interrupt control register SSS MN 000000016 1 RAW Acquisition controllstatus register J K registe 0x00000014 4 RW Vet Length register 0891
66. ect Memory Start Mode 67 annel Event Direct Memory Stop Mode 68 annel Event FIFO Mode 65 HOS 06060600600060060060060000600060000060006000006000600000006000000006000000060000060060000060060000009099 93 56 EEN 90 9 _ 0 We ur EE AGAM EE s 5 eege ee EE EE A EE 4 284 ne OMG MIO Aspects of Operation 0 ETT eiaeaen a fata feuds ee hs heen ce eens ec d Et ase address 00000 0 EE roadcast Stee EENG 6030 Eer master EE IS de tee EE oo E Oo O O l calibration NERO RET AOO EE external I external oe ie internal e L MAXIMUM BEEN CJ SIS3305 5 GS s 10 bit Digitizer fa innovative systeme ini 10 clock source LO 23 24 40 CORU a a S a A fi 1 83 O IA 0 EDOLITIS NI O E EE e WD O LL A duty Eeer E E OS e2v ele eege eegene 65817 1 1 1 1 1 1 1 100111 ee enable sample 1015102 O0 enable sample Joe OO it OF COUMICT o 1 1 1 1 ER event data e E Event FIFO eener O Een E DN e EE OF External Veto Delay Length Logic 02 FIR EE NN CHE cT I EM bast EWE ae 74 OIA
67. et EE 10 pe 11 Geet 12 7 ONE PA PRU 13 3 1 P rudis WIAD OOO LE E E E E o 14 3 1 1 E EE 14 3 1 2 EE 15 3 1 3 AIC erOUp TWO ISI DESI ra sree cee ara O 16 3 1 4 APEC ROUND 2 0 OIG ET OT 17 EES 18 4 1 Control Status Register OxO wnteiread nnne nennen enne 18 4 1 Enable for the External LEMO Inpnuts eem enn en eren nenne 19 4 2 Module Id and Firmware Revision Register 0x4 read esses 20 4 2 1 Major revision 111110035678 sss e 20 4 3 Interrupt configuration register 0X8 6666666666666666 6666660660660 21 4 3 1 MM EE 21 4 4 Interrupt control register OUKC 22 4 5 Acquisition control register 0x10 read WrIte 23 4 1 Veto Length register 0x14 readiwrteit nnns 24 4 2 Veto Delay register 0x18 read write
68. fset adjust Offset Gain adjust Page 26 of 97 Nile Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer EEprom DS2430 Onewire Control Register define SIS3305 ONE WIRE CONTROL REG 0x2C read write D32 7 Provides access to the 256 bit onboard EEprom The EEprom is organized as 32 words 8bit Read EEprom Busy 30 reserved 0 29 reserved 0 0 28 reserved 0 27 reserved 0 26 reserved 0 25 reserved 0 O0 24 reserved 0 23 reserved 000 O0 22 reserved 0 21 reserved 0 20 19 reserved Il 18 esoe 7 esoe 16 reserved 0 15 reserved 0 14 reserved 0 O0 13 reserved 0 O0 12 served 0 11 esoe 10 Onewire Command RESET BUS OQ 9 Onewire Command WRITE BYTE 0 8 Onewire Command READ BYTE 0 6 EEprom Write data bit6 EEprom Read data bit6 0 _ EEprom Write data bitO EEprom Read data bit0 The Device Presence bit can be found in EEprom Read data bit 0 after executing a RESET BUS command A value of 0 indicates that at least 1 device is present on the Onewire bus The power up default value reads 0x0 Page 27 of 97 atl Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer Programming refer to sis3305_configuration_readout_lib c bus reset presence bit int ee_ds2430_reset unsigned int moduleAdr int ee_ds2430_read_rom unsigned int moduleAdr unsigned char d
69. gister is used in the firmware upgrade process over VME A TCK is generated upon a write cycle to the register O OTD 4 7 5 XILINX JTAG_DATA_IN register define SIS3305 XILINX JTAG DATA IN 0x60 read only D32 This register 1s used in the firmware upgrade process over VME It is at the same address as the JTAG TEST register and is used in read access It operates as a shift register for TDO The contents of the register is shifted to the right by one bit with every positive edge of TCK and the status of TDO is transferred to Bit 30 Bit 31 reflects the current value of TDO during a read access Page 36 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Seale Innovative systeme 4 8 Temperature and Temperature Supervisor register 0x70 read write define SIS3305 INTERNAL TEMPERATURE REG 0x70 read write D32 The 8183305 is equipped with a serial 10 bit Analog Devices 07314 temperature sensor The temperature reading is stored in twos complement format Refer to the AD7314 data sheet for more detailed information Bit write Enable Temperature Supervisor Enable Temperature Supervisor 28 Temperature Supervisor Threshold Flag 27 NM 26 T_T Temperature Threshold Bit 1 Temperature Threshold Bit Temperature Threshold Bit 0 LSB Temperature Threshold Bit 0 LSB 1 0 o ooo _ _ _ _ 9 Temperature Data Bit 9 MSB d 5 Temperature
70. his register key address reset the ADC FPGA logic including the DDR2 memory controller Used for test purposes only 4 14 10 Key address Trigger Out Pulse define S183305 ADCEXTERNAL TRIGGER OUT PULSE 0x43C weite only D22 A write with arbitrary data to this register key address generates a pulse on the External Trigger Out if enabled see LEMO Trigger Out Select register bit 15 Page 45 of 97 Wie Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 15 Event configuration registers 0x2000 0x3000 read write define SIS3305_EVENT_CONFIG_ADC1_4 0x2000 define S1 3305 EVENT CONFIG ADC5 8 0x3000 This register is implemented for each channel group Function ADC Event Header programmable ID bit 7 ADC Event Header programmable ID bit 0 ADC Event Header programmable Info bit 3 ADC Event Header programmable Info bit 0 Unused read 0 Enable Direct Memory Stop Arm for Trigger after PreTriggerDelay bit Unused Enable Direct Memory TDC Measurement bit Disable Direct Memory Header bit 9 Enable Timestamp Clear with Sample Enable bit 8 Enable ADC Event sampling with next external Trigger TDC else with Enable Unused read 0 6 Enable internal Trigger Gate asynchronous Mode Enable global Trigger Gate synchronous Mode ADC Gate Mode else Trigger Mode Unused read 0 ADC Event Saving Mode bit 2 ADC Event Saving Mode bit 1 0 ADC Event Saving Mode bit 0
71. ingfuffer Ringbuffer Sample Logic Enabled Write to Memory If offset address Sample Length then offset address Next Event address else offset address 0 i wrap stop offset address 1 Header Direct Memory Pretrigger Length i External Trigger i i Stop SS Event X with N samples Pre Post Direct Memory Stop Direct Memory Stop ST N 1 0 1 2 51 1 wrap stop offset address 1 sample Memory ST N 1 a Event 1 Event 2 sam ple memory start address wrap stop offset address ST Page 68 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 6 ADC memory The two four channel groups have a one GByte memory space each It can be accessed by VME via the fast data transfer logic and it s FIFOs The ADC sampling logic stores Events to memory in 512 bit blocks The smallest event size is 128 bit Therefore the last 512 bit block 15 filled by the logic with OxFFFFFFFF as needed after the sample logic is disabled 1G x 8bit 256M x 32bit 64M x 128bit 16M x 512bit Memory 512 bit buffer Block Address 32 bit Address 0 0 ecco 512 bit block j 128 bit block scht nee 0x0 OX1 wees 512 bit block SS 128 bit block 32 bit p 0x
72. irect Memory Max Nof Events register ADC2 ch5 ch8 0x0301C End Address Threshold Wen 0x03020 Trigger Gate GT Threshold register ADC2 ch5 0x03024 0x03028 R W Trigger Gate LT Threshold register ADC2 5 R W Trigger Gate GT Threshold register ADC2 ch 2 2 0x0302C Trigger Gate LT Threshold register ADC2 6 0x03030 Trigger Gate GT Threshold register ADC2 ch7 0x03034 0x03038 0x0 2036 R W Trigger Gate LT Threshold register ADC2 ch R W Trigger Gate GT Threshold register ADC2 8 RW Trigger Gate LT Threshold register ADC2 8 1 Sampling Status ADC2 ch5 ch8 R Next Sample address register ADC2 ch5 ch8 R Direct Memory Event Counter ADC2 ch5 ch8 Direct Memory Actual Event Start address register ADC2 ch5 ch8 R Actual Sample Value ADC2 ch5 ch6 R Actual Sample Value ADC2 ch7 ch8 R Aurora Protocol Status register ADC2 Internal Status register ADC2 222 0x03040 023 03 0 4 4 0x03048 0x0304C 0x03050 0x03054 0x03058 Dx0305 0x03060 Aurora Protocol TX Live counter ADC2 Dx03070 0x03074 0x03078 0x0307C W W Individual Channel Select Set Veto register ADC2 ch5 ch8 reserved reserved W reserved 0x03400 Input Tap Delay register ADC2 ch5 ch8 mn Page 17 of 97 SIS Documentation SIS3305 innovative 4 Register Description The function of the individual registers is described in detail in this section The first line after the subsection header in Courier font
73. is a 2mm 1 e metric 14 pin header that allows you to reprogram the firmware of the SIS3305 with a JTAG programmer The pin out is shown in the schematic below It is compatible with the cable that comes with the XILINX HW USB platform cable Za LA fe o Ec ir P A e Ik E iii C21 Eh x ages s 1 255 55 Km Ch The schematic for CON100 is shown below CONI00 JTAG STECKER 2mm MOLEX 87831 1 MOLEX 87831 1420 Note The 5153305 has to be powered for reprogramming over JT AG Page 83 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Wie Innovative systeme 9 2 JP120A 50 Ohm Termination NIM TRIGGER IN 50 Ohm termination of the trigger input signal 15 enabled or disabled with the jumper JP120A you can enable or disable the Position 1 2 closed 50 Ohm termination enabled JP120A Position 3 4 closed 50 Ohm termination disabled JP120A 9 3 JP122A 50 Ohm Termination NIM COUNT IN 50 Ohm termination of the count input signal is enabled or disabled with the jumper JP122A Position 1 2 closed 50 Ohm Termination enabled JP122A Position 3 4 closed 50 Ohm Termination disabled JP122A Page 84 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Wie Innovative systeme 9 4 JP123A 50 Ohm Termination NIM RESET IN 50 Ohm termination of the reset signal is enabled or disabled with the jumper JP123A Position
74. l 2 ac Se a7 9a bs 220 292 23e 2062 230 b 247 S76 UJ 381 38a Sit Sob 4 304 04 5 GS s 10 bit Digitizer SIS3305 Trigger Mode and internal Trigger 5 Gsps ADC 1 4 channel 1 Threshold GT 0x262 610 Salaa Innovative systeme Sample Block Length 4 programmed 3 gt 4 x 48 samples 192 samples 34 32 35 33 8a ga 90 9c 22 242 23b 24a 37a 303 380 384 cdcd indicates Trigger GT bit 3 and on 5 position ADC1 3 and 4 position ADC2 4 c4b50e 34 34 34 ES a3 bO a8 b8 25 267 25 270 38a 38f 38e 390 33 35 33 34 be ce c4 d4 23 28a 284 293 394 398 399 39a 0 36 2 Sis 2 dc eb e2 13 2797 296 2a8 26 39e 3a0 3a0 3a3 cdcd0004 37 8 38 3b ER a 39 aC rtc ILE LOE 132 106 12a 114 13a 200 2e0 ecd ec 207 7 207 213 3a4 3aa 3a4 3aa 3al 32 3a8 3ac e 40 3e 42 143 15 14e 10 21 306 S02 od 3ae 300 3ae 3b1 gt 1 trigger 0x267 on 4 position ADC2 2 34 36 35 bb CH El CE 214 285 280 Pot DT 396 394 39a abbb indicates Trigger GT bit 3 and on 2 position ADC4 and 3 position ADC1 3 2 e488ca 35 36 27 36 d9 e6 de ee 29a 2a8 2a3 22 DOC 39d 39d 3al 36 38 ER 38 f9 107 100 110 200 2009 204 27 3a4 3a7 3a5 3a6 0 33 3b ES Sd lla 120 123 15 4 2db 268 2e4 281 3aa 3ab 33 33 abbb0004 41 45 40 46 3e 45 42 49 13e 165 l5l Lye 148 16e
75. lock diagram of the 85183305 can be found below The module is a dual four channel digitizer group design with control interface section as illustrated in the simplified block diagram below ACAM TDC GPX FPGA 4G Link em mmm Virtesd edium VME Interface Veto In or 4G Option VO Control FPGA 4 Channel Virtex5 ADC ADC Interface Clock Distribution FPGA 4 Channel Virtex5 ADC ADC Interface Page8of97 00000000 SIS Documentation SIS3305 5 GS s 10 bit Digitizer Seabee innovative systeme 2 4 1 Four channel group The structure of both four channel groups is identical The ADC chip itself has four ADC cores and is connected to its peripherals as illustrated 1n the simplified scheme below PRE AMP PRE AMP ADC FPGA PRE AMP PRE AMP Analog Piggy Back 2 4 2 EV10EQ190 Digitizer ADC Chip The EV10EQ190 chip from e2v Technologies is used as ADC chip on the 85183305 It s architecture is illustrated below LVDS Buffers LVDS Buffers LVDS Buffers LVDS Buffers Selection 2 5 GHz clock x SDA Offset ea 080 8982 Ww Peripheral Interface Analog MUX Cross Point Switch Page 9 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 2 4 3 Memory handling The 5153305 has FPGA block memory and DDR2 memory resource
76. lue x 2 ps Write Stop values into ADC FPGAs l Page 11 of 97 Sigil Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 2 6 VME Interrupts Eight interrupt sources are forseen refer to sections 4 3 and 4 4 for details on the actual implementation RORA or ROAK interrupter mode can be used Page 12 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 3 VME Addressing As the SIS3305 VME FADC has two times one GByte of memory two times two GByte in V2 A32 addressing was implemented as the only option for the time being The module occupies an address space of 0300 FFFF Bytes 1 e 16 Mbyte The base address is defined by the selected addressing mode which is selected by jumper array SW80 and SW and SW2 in non geographical mode The table below summarises the possible base address settings RAR EN AIO EN GEO EN RES 2 2 SW LL pem TIN o Netimplemenui in this design Notimpiemented in this design Shorthand SWI SW2 Setting of rotary switch SW1 or SW2 respective Notes e This concept allows the use of the SIS3305 in standard VME as well as in VME64x environments i e the user does not need to use a VME64x backplane e The factory default setting is EN A32 closed SW1 4 5 2 1 1 e the module will react to A32 addressing under address 0x41000000 With mor
77. ource disabled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again K 3 RORAROAKMode RORA LROAK O Do I1 VME IRQ Enable 0 IRQ disabled 1 IRQ enable MO 10 VMEmQlewlBt2 MO 9 VMElQlewlBt ln VMElQlewlBto LT IRO Vector Bit 7 placed on D7 during VME IRQ ACK cycle SS 6 IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle O0 5 IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle ln 4 IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle O 3 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle 0O0 2 IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle O 1 IRQ Vector Bit I placed on DI during VME IRQ ACK cycle MT 0 IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle O The power up default value reads 0x 00000000 Page 21 of 97 SIS Documentation SIS3305 innovative GS s 10 bit Digitizer E 4 4 Interrupt control register 0xC define SIS3305 IRQ CONTROL OxC read write D32 This register controls the VME interrupt behaviour of the SIS3305 ADC Eight interrupt sources are foreseen for the time being two of them are associated with an interrupt condition the others are reserved for future use 31 Update IRQ Pulse Status IRQ source 7 reserved o i OSO
78. r Index Trigger Index ADC 1 Trigger Index Length 15 0 in Data blocks 1 Data Block 16 x 32 bit words Note Sample N 1 25 Gsps N 2 5 Gsps N 5 Gsps sample 1 1 1 9 0 sample 2 3 5 sample 3 5 9 sample 4 7 13 sample 5 9 17 sample 6 11 21 sample 7 13 25 sample 8 15 29 sample 9 17 33 sample 10 19 37 sample 11 21 41 sample 12 23 45 sample 1 2 3 9 0 sample 2 4 7 sample 3 6 11 Sample 4 8 15 sample 5 10 19 sample 6 12 23 sample 7 14 27 sample 8 16 31 sample 9 18 35 sample 10 20 39 sample 11 22 43 sample 12 24 47 sample 1 1 2 9 0 sample 2 3 6 sample 3 5 10 sample 4 7 14 sample 5 9 18 sample 6 11 22 sample 7 13 26 sample 8 15 30 sample 9 17 34 sample 10 19 38 sample 11 21 42 sample 12 23 46 Sample 1 2 4 9 0 sample 2 4 8 sample 3 6 12 sample 4 8 16 sample 5 10 20 sample 6 12 24 sample 7 14 28 sample 10 20 40 sample 8 16 32 sample 11 22 44 sample 9 18 36 sample 12 24 48 Page 76 of 97 SIS Documentation Examples HEADER EVENT ID 5G ADCI234 72820000 34 33 34 32 35 34 33 33 66 76 6d 7f 6a Tb 70 85 lel 20b 1f5 21a led 214 111 226 35b 36 2603 2 261 372 366 375 cdcd0004 HEADER EVENT ID 5G ADCI234 72820000 34 SN 30 ER 33 34 32 32 89 a
79. ress bit 28 24 Broadcast address bit 24 23 esoe 22 reserved 21 reserved 20 served 19 reserved 18 reserved H7 reserved 16 reserved 15 reserved 14 reserved o 13 reserved 12 reserved 1 reserved 10 0 8 0 1 0 5 Enable Broadcast Master 4 EnableBroadcast eee Enable Broadcast TC Page 29 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer Broadcast functionality is implemented for all Key address cycles Modules which are supposed to participate in a broadcast have to get the same broadcast address The broadcast address is defined by the upper 8 bits of the broadcast setup register One module has to be configured as broadcast master the enable broadcast bit has to be set for all modules as illustrated below im bel 0 0 0 kel O im D Broadcast enable Broadcast enable Broadcast enable VME Crate Broadcast setup example broadcast address 0x30000000 Broadcast Setup Register 0x30000030 Broadcast Master Broadcast enable 0x30000010 Broadcast enable 0x30000010 Broadcast enable 0x30000010 Broadcast enable All 4 modules will participate in a key reset A32 D32 write to address 0x30000400 Note Do not use a broadcast address that is an existing VME address of a VME card in the crate Page 30 of 97 Seabee Innovative systeme SIS Documentation SIS3305
80. s The stream of digitized data from the ADC cores is recorded to the block memory of the FPGA continuously Trigger handling data processing data formatting and storage to external DDR2 memory can be implemented in a flexible fashion in different firmware flavors 2 4 4 Clock sources The 5153305 features following clock modes e Internal fixed clock e External differential clock 2 4 4 1 Internal clock The internal clock is generated from an on board tunable quartz the factory default configuration is 2 5 GHz 2 4 4 2 External clock A PECL symmetric differential clock can be supplied to the module through two SMA connectors Typically this clock is coming from the clock output of another SIS3305 to operate two cards synchronously Min sym clock Max sym clock 400 MHz 2500 MHz The duty cycle has to meet the criteria specified in the table below 2 4 5 Trigger control pre post start stop and gate mode The modes of operation start stop and gate in combination with the Ringbuffer delay and Pre Trigger Sample Length allow for the flexible implementation of acquisition schemes with and without pre and post trigger samples 2 4 6 Internal Trigger generation A set of 16 registers allows to set individual thresholds for the 8 channels with the two trigger conditions greater than GT and lower than LT Schmitt trigger like operation 1s supported via different values for the trigger on and trigger off conditions Pag
81. s 10 bit Digitizer 4 24 Actual Sample address register define SIS3305_ACTUAL_SAMPLE_ADDRESS_ADC1_4 0x2044 define 305 ACTUAL SAMPLE ADDRESS ADC5 8 0x3044 These two read only registers hold the actual sampling address for the given ADC channel group The value 1s given in 512 bit Blocks 32 bit word address x 16 23 0 Function reserved Actual Sample Memory Address in 512 bit Blocks 32 bit word address x 16 4 25 Direct Memory Event Counter define SIS3305_DIRECT_MEMORY_EVENT_COUNTER_ADC1_4 0x2048 define 1 3305 DIRECT MEMORY EVENT COUNTER ADC5 8 0x3048 These two read only registers hold the actual number of events in Direct Memory mode for the given ADC channel group The Event Counter will be cleared with Sample enable and will be incremented with each saved Event Bit 31 16 Function reserved Event Counter 4 26 Direct Memory Actual Next Event Start address register define 13 83305 DIRECT MEMORY ACTUAL EVENT START ADDRESS ADC1 4 0x204C define 1 3305 DIRECT MEMORY ACTUAL EVENT START ADDRESS ADC5 8 0x304C These two read only registers hold the actual Next Event Start address in Direct Memory mode for the given ADC channel group The value 1s given in 512 bit Blocks 32 bit word address x 16 Function reserved Actual Next Event Start Memory Address in 512 bit Blocks 32 bit word address x 16 Page 55 of 97 SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 27 Actual Sampl
82. t_Mode_Setup unsigned int module addr unsigned int uint_HSDiv 4 7 1 TDC Write Cmd Read Status register 0x50 read write 31 TDC Write Address bit3 0 30 TDCWrieAddrssbit2 TO 29 TDC Write Address bit1 0 28 TDC Write Address bit0 O o 27 TDC Write Data bit 27 0 26 TDC Write 808688626 0 5 TDCIRQFlaEg 4 DCPs 3 J Je TDCFIFO2LodFlg 2 AJ A TDCFIFOlLlodFlag 0 TDCWriedaabitO TDCFIFOl Empty Flag o o The power up default value reads 0x0 4 7 2 TDC Read Cmd Read Data register 0x54 read write Page 33 of 97 Wie Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer Read TDC Read Data bit 27 TDC Read Data bit 26 2 TDC Read Data bit 1 0 Reserved TDC Read Data bit 0 The power up default value reads 0x0 Page 34 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 7 3 TDC Start Stop Enable register 0x58 read write 25 O B Ca TDC Stop2 Enable TDC Stop1 Enable 0 TDC Start Enable Note Data are ored with TDC FSM data To be used in test mode only TDC test in software Loop Page 35 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 7 4 XILINX JTAG TEST register define SIS3305 XILINX JTAG TEST 0x60 write only D32 This re
83. te the written Command A Reset Transfer FSM command stops the fast data transfer logic and resets the FIFOs ADCI chl ch4 Memory Data FIFO ADC2 ch5 ch8 Memory Data FIFO A Start Read Transfer command resets the FIFOs ADCI chl ch4 Memory Data FIFO ADC2 ch5 ch8 Memory Data FIFO and starts the fast data transfer Read The logic transfers the memory data from the written Start Address to the VME FPGA data FIFO controlled by the FIFO Halffull flag A Start Write Transfer command resets the FIFOs ADCI chl ch4 Memory Data FIFO ADC2 ch5 ch8 Memory Data FIFO and starts the fast data transfer Write The logic transfers the VME FPGA Data FIFO data to memory at the written Start Address controlled by the FIFO Empty flag only possible if ADC Memory Write via VME Test is enabled Event Configuration registers bit 15 Memory Start 512 bit Block Address default after Reset 0x0 Command bit table Command Command function Bitl BitO DL JResetTransfer FSM 1 O0 Start Read Transfer Start Write Transfer Page 40 of 97 Seabed Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 11 ADC1 ch1 ch4 ADC2 ch5 8 FPGA Data Transfer Status register OxC8 OxCC define SIS3305 DATA TRANSFER ADC1 4 STATUS REG 0xC8 read D32 define S1IS3305 DATA TRANSFER ADC5 8 STATUS REG OxCC read D32 This set of two registers holds the status of the VME ADC FPGA data transfer Func
84. temperature state U2 1s inverted to U1 U3 8 2 Channel LED s L1 L8 The 8 card edge surface mounted LEDs L1 L8 can be seen through the corresponding holes in the front panel They visualize the trigger status of the corresponding channel The on duration is stretched for better visibility of short pulses Page 81 of 97 Seale innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 8 3 PCBLEDs Surface mounted red LEDs are used to signal power status trigger status and FPGA debug information the use of the debug LEDs is firmware design dependent A table with the SMD LEDs 15 given below Function Front panel trigger LED L1 Front panel trigger LED L2 Front panel trigger LED L3 Front panel trigger LED L4 Front panel trigger LED L5 Page 82 of 97 SIS Documentation SIS3305 dni innovative 5 GS s 10 bit Digitizer systeme 9 Jumpers Connectors The following subsections list the configuration jumpers and connectors of the 5183305 9 1 CON100 JTAG The 5153305 on board logic can load its firmware from a serial PROMS via the JTAG port on connector CONIOO or over VME A list of firmware designs can be found under http www struck de sis3305firm htm Hardware like the XILINX HW USB JTAG in connection with the appropriate software will be required for in field JTAG firmware upgrades The JTAG chain configuration is selected with the register XX is used to choose VME or CON100 as JTAG source CON100
85. tion Data Transfer Logic busy Data Transfer Direction Write Flag 0 Memory gt VME FPGA 1 VME FPGA Memory FIFO read VME FIFO Data valid Flag FIFO read VME FIFO Data AlmostFull Flag max nof pending read requests no pending read requests 25 In ER ee BS 0 Data Transfer internal 512 block Address counter bit 0 Page 41 of 97 Seale innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 12 Aurora Protocol Status register 0xDO read write define SIS3305 VME FPGA AURORA PROT STATUS OxDO read write D32 This register holds the VME FPGA Status of the Aurora Protocol Link between the VME FPGA and the ADC FPGAs U11 and U21 read 31 Prot_U21_error counter bit7 Eo LLL 24 Prot U21 errorcounterbitO0 15 J Prot Ull eror counter bit RE Prot Ull eror counterbitO 6 Lea Prot UII Soft error latch Prot UII Softeror lath o nm JJ JPro UllHaremorflg Page 42 of 97 Wie Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 4 13 Aurora Data Status register 0xD4 read write define SIS3305 VME FPGA AURORA DATA STATUS OxD4 fead write D32 85 This register holds the VME FPGA Status of the Aurora Data Link between the VME FPGA and the ADC FPGAs U11 and U21 read 31 Data_U21_Lane_up_flag 30 J J Data U21 Lane up flag O 29
86. tion None ADC4 ADC3 ADC2 ADC 1 None Tap delay value x 78ps Select Select Select Select Note The tap delays can be retrieved fom the 93C56 EEprom and have to be written to the two input tap delay registers prior to acquisition of data Page 58 of 97 Seale Innovative systeme SIS Documentation SIS3305 5 GS s 10 bit Digitizer 5 Aspects of Operation 5 1 General block diagram of one ADC channel 1 4 The schematic of the ADC channel 1 4 data flow and sample sample logic 1s shown below ADC Clk domain Memory CIk domain Copy to Memory TDC Event VME CTRL Fifo Rss 512 x events ch4 data Ringbuffer Event Buffer Delay Fifo 0 to 6138 clks 6K x samples cha data Ringbuffer Event Buffer Data Data 128 Event Buffer Delay Fifo ADC1 ch1 ch4 0 to 6138 clks 6K x samples Data Input Block data 10 Delay 0 Delay Fifo programmable 0 to 6138 clks 6K x samples cht data Ringbuffer Event Buffer Delay Fifo Formatter l Logic l Memory 1 GByte Sample Logic Control Block ch 1 4 ADC ch1 4 4 T Gat Trigger Block Laus Global Trigger External Trigger or Key Address Trigger Memory Address 2 0to 6138 clks 6K x samples Address Logic Ringbuffer ADC ch1 4 ch 1 4 Veto Veto Block Global Veto External Veto or programmable Veto Sample Logic Enabled Page 59 of 97 SIS Documentation SIS3305 innovative

SIS3305 5 GS/s, 2.5 GS/s, 1.25 GS/s 10

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