Reset and System Startup Configuration via PORT0 or
Contents
1. IRS PORTO sample Timing Short Hardware Reset Bidirectional Reset enabled Semiconductor Group 10 of 23 AP163703 12 99 Reset and System Startup Infineon ologia Reset and System Startup Note The characteristic that PORTO 1 0 is not transparent before it is latched as shown in figure 2 3 4 6 and 7 is only implemented in the actual devices The PORTO 1 0 characteristic of the older ones listed below differs in that point For these devices PORTO 1 0 is transparent for the same duration as PORTO 15 2 During software reset WDT reset bidirectional reset disabled PORTO 1 0 is not latched and therefore not transparent see figure 5 Device Step Device Step C161V K O AA C167 LM BB BC BD C163 L C167S 4RM AA AE C165 C167SR LM BA BB C167CR LM BB C167CR 16RM AA Table 4 Devices were PORTO 1 0 are transparent during Reset Note Latching of the PORTO configuration when Pin EA High is different for devices with flash on chip For devices without single chip mode reset RSTCON i e the devices not included Table5 when the level on pin EA is high during reset the configuration on POH 4 0 and POL 7 0 is not latched with the end of the internal reset condition but about 120 40 us later due to program Flash voltage ramp up This behavoiur should not present a problem in systems where the reset configuration is realized by external resi2. 1 PLL 2 3 4 5 CB DA DB FA OWE yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C167CR 4RM AA Vpp OWE 0 5 1 PLL 1 5 2 2 5 3 4 5 DA DB FA Vpp OWE no yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C167CR 16FM AC 1 PLL 4 C167CR 16RM AA 1 PLL 2 3 4 5 FA OWE no yes 0 5 1 PLL 1 5 2 2 5 3 4 5 Semiconductor Group 22 of 23 AP163703 12 99 puma Infineon nologies Reset and System Startup C167CS 32FM AA AB AD AE CA CB RD yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C167CS 4RM AA RD yes yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C167S 4RM AA Vpp no no no 1 PLL 2 3 4 5 FA Vpp yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C167SR LM AB 1 PLL 4 BA 1 PLL 2 3 4 5 FA Vpp no yes 0 5 1 PLL 1 5 2 2 5 3 4 5 1 The described options are implemented since the steps listed below The Oscillator Watchdog OWD can be disabled in different kinds No OWD implemented Vpp OWE_ A low level on pin Vpp OWE disables the OWD OWE Alow level on pin OWE disables the OWD RD A low level on pin RD at the end of any type of reset disables the OWD The level of RD is latched with the IRS See figure 2 7 Vpp A low level on pin Vpp disables the OWD 3 Besides other features the Power Management PM includes the Slow Down Divider SDD A separate cl
3. Microcontrollers ApNote AP163703 Reset and System Startup Configuration via PORTO or Register RSTCON Presents an overview about the different reset types power on reset long short hardware reset software reset WDT reset and the system startup configuration via PORTO or register RSTCON The calculation for the pull up down resistors at PORTO is also included Author Al MC AE Semiconductor Group 12 99 Rel 03 Edition 1999 12 Published by Infineon Technologies AG 81726 M nchen Germany Infineon Technologies AG 2006 Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to techn
4. 12 3 Calculation of the Pull up down Resistors at PORTO for Startup Configuration 15 3 1 Pull down Calculation Ra 15 3 2 Pullsup Calcilalloll 45x 3 EX x ba pene EX qx er Ee ques 16 4 Calculation of the Pull down Res at Pin RD for BSL Entry in Single Chip Mode 18 5 Appendix qc Ur 20 5 1 PORTO Configuration during Reset 20 5 2 Reset Clock Options and Steps 22 Note Some of the products mentioned in this Application Note are not officially announced yet AP163703 ApNote Revision History Actual Revision 12 99 Previous Revision 6 98 Page of Page of Subjects changes since last release actual Rev prev Rel Reset Note added New chapter Calculation of the Pull down Resistor at Pin BSL Entry in Single Chip Mode Appendix Reset Clock Options and Steps updated 12 7 1 24 E Le New chapter System Startup Configuration upon a Single Chip Mode EN Le Semiconductor Group 2 of 23 AP163703 12 99 Infineon ologia Reset and System Startup 1 Overview about the different Reset Sources During reset the device executes a special internal sequence in order to set internal signals and the Special Function Registers SFRs to their specified default values The contents of some Special Function Registers are controlled
5. 5 clock options RSTCON don t care POH 4 3 segm addr lines RSTCON don t care POH 4 3 POH 2 1 chip select lines RSTCON 9 POH 2 1 POH 0 WR configuration RSTCON don t care POH 0 4 POL 7 6 bus type RSTCON don t POL 5 2 BSL entry not possible POL 5 2 9 POL 1 adapt mode not possible 1 1 9 POL 0 emulation mode not possible 2 9 RD BSL entry RD 9 not possible 3 Startup configuration source default RSTCON PORTO PORTO pull ups during reset off on CS pull ups after reset ott RD WR pull ups after reset on 9 ALE pull down after reset on 9 Startup configuration source PORTO PORTO pull ups during reset on 65 pull ups after reset off if selected active high level is driven RD WR pull ups after reset off active high level is driven ALE pull down after reset off active low level is driven Oscillator watchdog disable RD 9 PORTO pull ups after reset off CS pull ups during reset on RD WR pull ups during reset on ALE pull down during reset on Table 6 EA Pin and System Startup Configuration Semiconductor Group 13 of 23 AP163703 12 99 puma Infineon nologies Reset and System Startup 1 Adapt mode entry only via pin EA Low In single chip mode it is not possible to activate adapt mode 2 Emulation mode entry only via pin EA Low In single chip mode it is not possible to activate emulation mode 3 Oscill
6. MHz CPU Clock the internal reset sequence is started 1024 TCL 25 6 us 20 MHz CPU Clock After the internal reset sequence has been completed the RSTIN input is sampled When the reset input is still active at that time the internal reset condition is prolonged until RSTIN gets inactive If the RSTIN signal is active for more then 1024 TCL then the behaviour of the PORTO latch mechanism is equal to a long hardware reset 1 2 Software Reset The reset sequence can be triggered at any time via the protected instruction SRST Software Reset This instruction can be executed deliberately within a program e g to leave bootstrap loader mode or upon a hardware trap that reveals a system failure A software reset takes 1024 TCL 25 6 us 920 MHz 1 8 Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence The watchdog timer reset releases automatically a software reset Other than a hardware reset the watchdog timer reset completes a running external bus cycle if this bus cycle either does not use READY at all or if READY is sampled active low after the programmed waitstates When READY is sampled inactive high after the programmed waitstates the running external bus cycle is aborted Then the internal reset sequence is started Note The watchdog timer reset cannot occur while the device is
7. at PORTO for Startup Configuration The specification in the Data Sheet includes the values of the PORTO configuration currents and 31 Pull down Calculation is the base for the calculation of the pull down resistors for PORTO startup configuration IPoLmin 100 pA That means that the port configuration current has to be greater or equal than 100 pA to get an input voltage lower or equal to The system current lsysL has a direct influence on the value of the needed pull down resistor The relation between the different parameters and the calculation with an example are shown below Note All currents flowing into the microcontroller are defined as positive and all currents flowing out of it are defined as negative Because of the internal pull up transistor the direction of Ipo and Ipoy is out of the device and therefore the sign in the current specification is negative IPoL gt 100A gt current Figure 8 System Environment and Pull down Resistor for Startup Current Specification in the Data Sheet Vcc 5V 10 45 lt lt 55 0 2 0 1 gt 0 8V lt lt 1 0V IPoLmin 100pA gt 100 Semiconductor Group 15 of 23 AP163703 12 99 Infineon ologia Reset and System Startup Pull down resistor calculation lt _ IPD IPoL ISYSL Examp
8. in bootstrap loader mode Semiconductor Group 4 of 23 AP163703 12 99 Infineon 5a gig Reset and System Startup 1 4 Bidirectional Reset The bidirectional reset is a new feature and implemented since the devices and steps listed below The steps in parentheses do only reflect a software or watchdog timer reset to RSTIN but not a short hardware reset as shown in figure 7 Device Step Device Step C161RI all C167CR LM CA CB C161CI SI all C167CR 4RM AB AC 161 all C167CR 16RM FA C161CS JC Jl all C167S 4RM BA BB C1610R all all C164CI 8EM all 16758 FA Table 2 Devices with implemented Bidirectional Reset Feature In bidirectional reset mode the device s line RSTIN normally an input may be driven active by the chip logic e g in order to support external equipment which is required for startup e g flash memory Internal Circuitry Reset sequence active BDRSTEN 1 Figure 1 Bidirectional Reset Operation Semiconductor Group 5 of 23 AP163703 12 99 Infineon nologies Reset and System Startup Bidirectional reset reflects internal reset sources software watchdog also to the RSTIN pin and converts short hardware reset pulses to a minimum duration of the internal reset sequence Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON SYSCON 3 and changes RSTIN from a pure input to an open drain IO line with an in
9. reset 4 TCL lt tgp lt 1024 TCL IRS Internal Reset Signal Sampling point of PORTO configuration bits is 7 TCL prescaler enabled or 10 TCL direct drive or PLL after the rising edge of RSTIN or after the end of the internal reset sequence TCL 1 1 2 1 TCL 25 ns 20 MHz CPU Clock Semiconductor Group 8 of 23 AP163703 12 99 Reset and System Startup 2048 TCL RSTIN PO 15 2 PO 1 0 tpotix Figure 2 PORTO sample Timing Power on Reset 4 1024 TCL P0 15 2 PO 1 0 om IRS Figure 3 PORTO sample Timing Long Hardware Reset Bidirectional Reset enabled or disabled RSTIN P0 12 2 P0 15 13 PO 1 0 Figure 4 PORTO sample Timing Short Hardware Reset Bidirectional Reset disabled Semiconductor Group 9 of 23 AP163703 12 99 echnologias PO 12 6 P0 15 13 PO 5 0 lt 1024 TCL transp a rent SW or WDT Reset Figure 5 PORTO sample Timing Software Reset or WDT Reset Bidirectional Reset disabled RSTIN P0 15 2 PO 1 0 1024 TCL s SW or WDT Reset IRS Figure 6 PORTO sample Timing Software Reset and WDT Reset Bidirectional Reset enabled RSTIN P0 15 2 PO 1 0 Figure 7 1024 TCL not transparent transparent ______________
10. the end of reset or via a fixed configuration value which is used when EA High single chip mode reset see section 2 3 for details 2 1 PORTO Configuration during Reset Table 3 shows PORTO configuration pins and which kind of reset sample event does sample which pin depending whether bidirectional reset is enabled on or disabled off Table 3 System Startup Configuration via PORTO Semiconductor Group 7 of 23 AP163703 12 99 Infineon nologies Reset and System Startup The PORTO startup configuration is sampled either with the end of the internal reset sequence or with the end of the external hardware reset If the external RSTIN signal is deactivated before the end of the internal reset sequence short hardware reset then an internal reset signal IRS of the device is used to latch the system startup configuration at PORTO else power on reset or long hardware reset PORTO is latched after the rising edge of RSTIN with signal IRS The sampling point of PORTO is 7 TCL prescaler enabled or 10 TCL direct drive or PLL after the rising edge of RSTIN as shown in the PORTO sample timing see figures below The duration of one internal reset sequence is 1024 TCL for initializing the internal Special Function Registers plus 10 TCL for the jump to address 00 0000 after the internal reset sequence The bidirecti
11. ator watchdog can be disabled for test purposes via pull down at pin RD 4 If system starts in single chip mode and external bus is enabled via software later then PORTO startup configuration is used for the external bus but it can be changed via software POH 2 1 CS signals selected via PORTO will be driven active high after reset 5 Internal CSx pull ups are active during reset 9 Only for SHWR For WDTR and SWR not possible POL 5 2 If the BSL entry is done via pin RD then the CPU clock is XTAL1 clock divided by two fcpu 056 2 This has to be considered for the appropriate communication baudrate with the external host 7 CS signals are driven active high after RSTCON is copied to RPOH If the system starts in single chip mode and CS will be used for external access then depending on the system demands external pull up resistors are necessary at the CS signals because after reset and before RSTCON is copied to RPOH the CS signals are in tristate and without defined level internal pull ups are disabled 9 Pull ups are active until bit BUSACTx in register BUSCONx is set then RD and WR are driven active high 9 Pull down is active until bit BUSACTx in register BUSCONx is set then ALE is driven active low Table 6 EA Pin and System Startup Configuration cont d Semiconductor Group 14 of 23 AP163703 12 99 Infineon ologia Reset and System Startup 3 Calculation of the Pull up down Resistors
12. during system startup configuration via PORTO or default value The system startup configuration at PORTO is sampled upon different reset events See table 1 Hardware Reset Power on Reset Short Hardware Reset Warm Reset Long Hardware Reset Power Down Wakeup Reset Software Reset Watchdog Timer Reset The reset source is also indicated by the reset source indication flags in register WDTCON Power on Reset PONR Power on tastin gt gt 1024 TCL Short Hardware Reset SHWR 4 TCL lt tas 1024 TCL Long Hardware Reset LHWR las gt 1024 TCL Watchdog Timer Reset WDTR WDT overflow Software Reset SWR SRST command Table 1 Reset Sources and Reset Conditions 11 Hardware Reset A hardware reset is triggered when the reset input signal RSTIN is sampled low To ensure the recognition of the RSTIN signal latching it must be held low for at least 2 CPU clock cycles 4 TCL 100 ns 20 MHz CPU Clock Also shorter RSTIN pulses may trigger a hardware reset if they coincide with the latch s sample point However for microcontrollers with an on chip PLL it is recommended to keep RSTIN low for ca 1 ms to guarantee that the PLL is locked After the reset sequence has been completed the RSTIN input is sampled again When the reset input signal is active low at that time the internal reset condition is prolonged until RSTIN gets inactive high The input RSTIN provides an internal pull up device equalling a resistor o
13. f 50 KQ to 250 KQ the minimum reset time must be determined by the lowest value Simply connecting an external capacitor is sufficient for an automatic power on reset a proper low level of RSTIN between power off and on has to be reached RSTIN may also be connected to the output of other logic gates Semiconductor Group 3 of 23 AP163703 12 99 Infineon nologies Reset and System Startup Three different kinds of external hardware resets have to be considered a Power on Reset A complete power on reset requires an active RSTIN time of two reset sequences 2 1024 TCL 51 2 us 20 MHz CPU Clock after a stable clock signal is available Depending on the oscillation frequency and the type of external oscillator circuit the on chip oscillator needs about 0 01 50 ms quartz crystal 2 50 ms ceramic resonator 0 01 0 5 ms to stabilize This means that the power on reset time is dominant by the oscillator start up time b Long Hardware Reset A long hardware reset requires an active RSTIN time longer than the duration of the internal reset sequence The duration of the internal reset sequence is 1024 TCL 1024 TCL 25 6 us 20 MHz CPU Clock The long hardware reset is also named power down wakeup reset c Short Hardware Reset The active RSTIN time of a short hardware reset is between 4 TCL and 1024 TCL If the RSTIN signal is active for at least 4 TCL clock cycles 100 ns 20
14. ical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or System Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered puma Infineon ivo dz oo be 5 Reset and System Startup Contents Page 1 Overview about the different Reset Sources 3 1 1 Hardware Reset 5 Pn dre p bres yd Exo ________ 3 1 2 Software Hesel isssk ex E ER EX 4 1 3 Watchdog Timer Reset 4 1 4 Bidirectional Reset e dd es ca 5 2 System Startup Configuration eee 7 2 1 PORTO Configuration during Reset 7 2 2 PORTO Sample Timing for the different Reset Types 8 2 3 System Startup Configuration upon a Single Chip Mode Reset
15. in all devices Please refer to the User s Manuals 2 The clock configuration bits are not fully decoded in all devices and steps Please use Appendix and the User s Manuals for detailed information Semiconductor Group 21 of 23 AP163703 12 99 Infineon nologies Reset and System Startup 5 2 Reset Clock Options and Steps C161RI AA BA BB 0 5 1 C161V K O AA FA 0 5 1 C1610R FA RD yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C161PI AA RD yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C161CS JC JI 32F AC BC CB RD yes yes no 0 5 1 PLL 1 5 2 2 5 3 4 5 C161SI CI 32F AA BA RD yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C161CS 32R AA RD yes yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C163 L AA AB AC Vpp OWE no 0 5 1 PLL 1 5 2 2 5 3 4 5 C163 16F AA AB BA Vpp OWE no no no 0 5 1 PLL 1 5 2 2 5 3 4 5 C163 16F x BB x BC x no 0 5 1 PLL 1 5 2 2 5 3 4 5 C164CI 8E BC CA RD yes yes no 0 5 1 PLL 1 5 2 2 5 3 4 5 C164CI 8R AB RD yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C164CH 8F AA RD yes yes yes 0 5 1 PLL 1 5 2 2 5 3 4 5 C165 BB 0 5 0 5 1 no C167 LM AD BA BB BC 0 5 C167CR LM AB 1 PLL 4 BA BB BE
16. le without system current lt _ 0 8 V 0 BD HR The recommended maximum value Rpp 8000 2 3 2 Pull up Calculation is the base for the calculation of the pull up resistors for PORTO startup configuration IPoHmax 10 Vin Vinmin AS already mentioned PORTO supplies internal pull up resistors which are only active during Reset or during Hold or Adapt mode For normal systems this internal pull up resistors are sufficient to reach the input high voltages at the PORTO pins This situation changes when the system current Isysy exceeds 10 pA Then additional external pull up resistors are mandatory For example system flash memory with a high leakage current can cause an increased Isysy The calculation and an example are shown below lt 10pA leakage Figure 9 System Environment and Pull up Resistor for Startup Semiconductor Group 16 of 23 AP163703 12 99 Infineon nologies Reset and System Startup Current Specification in the Data Sheet Vcc 5V 10 gt 45V lt lt 5 5 V ViHmin 0 2 Vcc 0 9 V gt 1 8 V lt ViHmin 20V 10 pA gt lt 10 VIHmin Pull up resistor calculation UE lsvsH PoH Rpu lt Example 45V 18V SYSH RPU lt 67 5 KQ The recommended maximum value Rey 67 5 Note The leakage current of some b
17. ock path can be selected for Slow Down operation bypassing the basic clock path used for standard operation The programmable Slow Down Divider divides the oscillator frequency by a factor of 1 32 In SDD mode the OWD has no effect 4 Prescaler option 0 5 Direct drive option 1 The PLL clock is not used for prescaler option fcpy fosc 0 5 and direct drive option fosc 1 0 5 In the first step of the C164CI 4RM or 8RM 32 64 Kbyte ROM version as an intermediate solution when pin EA High during reset the configuration is read from internal ROM address 00 003Eh instead of POH 7 0 and is copied into register RPOH In this case the status of PORTO during reset is not evaluated Register RSTCON is not implemented and during startup the content of ROM address 00 003Eh is used instead of the default configuration for single chip mode reset Semiconductor Group 23 of 23 AP163703 12 99
18. onal reset feature converts software reset WDT reset or short hardware reset to an externally visible hardware reset with a duration of 1024 TCL This feature is disabled after hardware reset and can be enabled via software 2 2 PORTO Sample Timing for the different Reset Types The different reset sources and timing relations at PORTO during and at the end of reset are shown below If a reset event occurs then PORTO is switched to input mode and the internal pull ups are active During that time it is possible that the desired input voltage levels at PORTO Vj and forced by the internal external pull ups and pull downs for the startup configuration are not reached Therefore PORTO is not transparent for 1024TCL power on reset for 2048 TCL to prevent unexpected behaviour to the system After that time a part of PORTO becomes transparent and at the end of reset these pins are sampled with the IRS signal Depending on the reset type some PORTO pins are not transparent e g POL 1 and POL O which control Adapt Mode and Emulation Mode Noise on these lines during reset would force the microcontroller to Adapt Mode or Emulation Mode Therefore both pins are not transparent until the sample point IRS at the end of the reset condition The PORTO sample timings shown below are based on the following conditions tpofix During tpofix PORTO has to be constant so the System Startup Configuration is latched correctly tsun Duration of a short hardware
19. or BSL Entry Semiconductor Group 18 of 23 AP163703 12 99 Infineon nologies Reset and System Startup Current Specification in the Data Sheet Vcc 5V 10 gt 45V lt Veco lt 5 5V Vimax 0 2Vec 0 1V gt 0 8V lt lt 1 0V IRWLmin 00 gt law gt 500pA Note Worst case for calculation is in that case Vi 5 5V Pull down resistor calculation lt ViLmax _ max IRD IRWL ISYSL Example without system current lt _ 10V Isys 0 A 90005 The recommended maximum value Rgp 2000 Q Semiconductor Group 19 of 23 AP163703 12 99 puma Infineon melomngies Reset and System Startup 5 Appendix 51 PORTO Configuration during Reset H7 H5 H2 L7 L6 L5 L4 L3 L2 L1 Lo ES EE E IE UE EN M EE E CLKCFG SALSEL CSSEL WRC BUSTYP SMOD ADP EMU External Host Mode EHM requires Emulation Mode iori Bootsirap Loader Siart fom intemal boot ROM _ GPU programming mode tor OTP santas dened by ER pin CPU Host Mode CHM CPU programming mode for OTP Semiconductor Group 20 of 23 AP163703 12 99 Infineon 5 a gig Reset and System Startup moe __ I I 11 256 KByte Default without pull downs E Maximum 01 64 KByte Minimum 1 This modes are implemented
20. stors on PORTO and where no other device is driving onto PORTO the data bus unless explicitly selected by the microcontroller under software control otherwise make sure that the reset configuration is maintained on PORTO until 200 us after the end of the internal reset condition and that PORTO is not switched to output or external bus accesses are performed during the first 120 us of program execution Semiconductor Group 11 of 23 AP163703 12 99 Infineon ologia Reset and System Startup 2 3 System Startup Configuration upon Single Chip Mode Reset For a single chip mode reset indicated by EA High the configuration via PORTO is replaced by the fixed configuration value 2 see User s Manual chapter System Startup Configuration upon a Single Chip Mode Reset In this case PORTO needs no external circuitry pull ups pull downs and also the internal configuration pull ups are not activated This fixed default configuration is activated after each long hardware reset LHWR or power on reset PONR The fixed default configuration selects a safe worst case configuration The initialization software can then modify these parameters via register RSTCON and select the intended configuration for a given application Table 6 includes the principle differences for the system startup configuration related to EA Low and EA High The column Configuration Source shows a comparison for devices with and witho
21. tegrated pull up resistor When an internal reset is triggered by the SRST instruction or by a watchdog timer overflow or a low level is applied to the RSTIN line an internal driver pulls it low for the duration of the internal reset sequence After that it is released and is then controlled by the external circuitry alone The bidirectional reset function is useful in applications where external devices require a defined reset signal but cannot be connected to the device s RSTOUT signal e g an external flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT The following behaviour differences must be observed when using the bidirectional reset feature in an application Bit BDRSTEN in register SYSCON cannot be changed after EINIT After a reset bit BDRSTEN is cleared bidirectional reset is disabled Bit WDTR will always be 0 even after a watchdog timer reset The PORTO configuration is treated like on a hardware reset Especially the bootstrap loader may be activated when POL 4 RD is low Pin RSTIN may only be connected to external reset devices with an open drain output driver Semiconductor Group 6 of 23 AP163703 12 99 Reset and System Startup 2 System Startup Configuration Some system features have to be selected before the first instruction of a program is executed These selections are made during reset via the pins of PORTO which are latched at
22. us hold devices exceeds the specified value of 110 HAI In that case all PORTO pins not configured to low level need a pull up resistor For calculation of the pull up value please refer to the specified leakage current of the bus hold device Semiconductor Group 17 of 23 AP163703 12 99 Infineon ologia Reset and System Startup 4 Calculation of the Pull down Resistor at Pin RD for BSL Entry in Single Chip Mode law is the base for the calculation of the pull down resistor at pin RD for BSL entry when single chip mode is selected The specification of Read Write active current min 500pA for pin RD Vout is also valid for ViN Vi That means that the read active current has to be greater or equal than 500 pA to get an input voltage Vy lower or equal to The system current lt has a direct influence on the value of the needed pull down resistor The relation between the different parameters and the calculation with an example are shown below Note All currents flowing into the microcontroller are defined as positive and all currents flowing out of it are defined as negative Because of the internal pull up transistor the direction of IRw i is out of the device and therefore the sign in the current specification is negative IRWL 2 500uA current Vin S max Figure 10 EN System Environment and Pull down Resistor at Pin RD f
23. ut register RSTCON The single chip mode reset via register RSTCON is a new feature and implemented since the devices listed below Device Step Device Step C164CI xXxRM C161CS 32RM AA C164xy 8FM C167CS 4RM AA Table 5 Devices with Single Chip Mode Reset RSTCON In the first step of the C164CI 4RM or 8RM 32 64 Kbyte ROM version as an intermediate solution when pin EA High during reset the configuration is read from internal ROM address 00 003Eh instead of POH 7 0 and is copied into register In this case the status of PORTO during reset is not evaluated Register RSTCON is not implemented and during startup the content of ROM address 00 003Eh is used instead of the default configuration for single chip mode reset Semiconductor Group 12 of 23 AP163703 12 99 Reset and System Startup Configuration Source Device with Device without RSTCON RSTCON POH 7 5 clock options default RSTCON POH 7 5 POH 4 3 segm addr lines default RSTCON don t care POH 4 3 POH 2 1 chip select lines default RSTCON don t care POH 2 1 4 POH 0 WR configuration default RSTCON POH O 4 POL 7 6 bus type default RSTCON don t care POL 5 2 BSL entry not possible POL 5 2 POL 1 adapt mode not possible 1 POL 1 POL 0 emulation mode not possible 2 POL 0 RD BSL entry RD not possible 3 POH 7
Download Pdf Manuals
Related Search