TI-DM3730-EM CORE BOARD User Manual
Contents
1. 2 12 EXPANSION FEATURE OP TIO NS 3 SYSTEM INTEGRATION e se se se se gegee tenent tenian tanta inta tasas aa tasses thia snas inia as Ge Be Ge tasas eta See ee ee 16 3 1 32 3 2 3 TI DM3730 EM CORE BOARD Reset SYS nRESWARM Reset output 17 3 3 INTERR UPIS Se RE De Ee n M su M t YY dE e E NOI 17 3 4 JTAG DEBUGGER INTER FACE 17 3 5 POWER MANAGEMENT cootra eed en ee tee d Y er ri rg eye LY 17 3 51 System Power Supplies us said pan testi rerba De Ge GR sig a A Ek Rek Ge ar aa 18 3 5 2 System Power Management iese ee esee tentent Re Ge ettet inet ee inito ete Ge ee Ge ee ee 18 2 E 88633449 http www esys ir 982158963982 info esys ir o EEE Embedded Designer in IRAN ardazesh Sabz EE an 3 5 3 Microcontroller iese se itt de de GYN DN e od ee ge dod 19 3 6 BOOT MODES ir ee ia Ge ee ge ed Ge Dee ade EE eg ve Ee Re ee EVE eu ed ee ee ee Ge ie 20 3 7 ES D CONSIDERATIO NS ee eterni cottidie eret etri FO GU ree Yd rW dyo 20 4 MEMORY amp VO MAPPING 2522 52522 ci sees sede a ee i iai a ia dee ara ara ara caa nra ara anna seek ede ee dd de ia sa od ao aud 21 5 CONNECTOR DESCRIP TION AND FUNCTION ese ese ese sese tnn tana ntn santa sta sta sta stata sanata 22 5 1 CONNEC TOR DESC RIPTIO NS rosario viene rii a e EV Ha o eN EKG REEF TET REY EE TRA 22 5 2 PIN DESCRIPTIO NS amp FUNCTIONS ees see ee ee ee ee ee LLA LLALL ee ee Ge ee ee ee ee SH 23 3 me E2. SYS nRESWARM External devices can drive MSTR nRST low to assert reset to the product TI DM3730 EM CORE BOARD uses SYS nRES WARM to indicate to other devices that the Torpedo SOM is in reset 3 2 1 Master Reset SYS nRESPWRON Reset Input TheMSTR nRST triggers a power on reset event to the OMAP35x processor and resets the entire CPU IMPORTANT NOTE MSTR nRST does not reset the TPS65930 the TPS65930 is only reset by removing power from the SOM IMPORTANT NOTE Any custom reset circuit design should guard the assertion of the reset lines during a low power state so as to prevent power up in a low or bad power condition Low Pulse on SYS nRESPWRON Signal A low pulse on the MSTR nRST signal asserted by an external source for example the reset button on the custom design application will bring SYS nRESPWRON low until the assertion source is de asserted There is no delay beyond the de assertion of the external 16 4982188633449 http www esys ir 9821889063987 info esys ir EE EE EEE 9821 Jaan u Jl5 ardazesh Sabz sufficient for all related 3 2 2 TI DM3730 EM CORE BOARD Reset SYS nRESWARM Reset output All hardware peripherals should connect their hardware reset pin to the SYS nRESWARM signal on the expansion connector Internally all Torpedo SOM peripheral hardware reset pins areconnected to the SYS_nRESWARM net 3 3 Interrupts The OMAP35x incorporates the ARM Cortex A8
3. 2 1 1 A 16 1 2 2 24 26 28 30 2 CEN so 10 2 4 Era IS 20 2 A 26 B EN 3 36 EN EU 50 52 54 0 2 34 6 4 44 46 48 0 2 4 60 5 5 5 5 5 Gwcps o emea So onn onn T ND ND ND 5 G G GPMC_nCS7 GPMC_nADV_ALE MCBSP3_FSX UART2_R X MSBSP3 DX UARI2 CT 4 5 EN 6 6 6 S S MCBSP3_DR UART2_RT MCBSP3_CLKX UART2 SYS cLKOUTVGPON IO 9 0 1 O 5 6 7 1 2 5 9 10 86 Embedded Designer in IRAN ul I O Voltage 1 1 1 1 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V Embedded Designer in IRAN de oig ud ardazesh Sabz J2 Connector Pin Description GPIO Signal Name I O Voltage Remark Ground GND GND AU DSS_D23 93 Q Z U Ground DSS_D22 92 T T i T v m T L 7 n 1 7 n 7 n 7 i Signal Name Remark No a woso m TT vaas es gen m nw s vm RS so lm uw D vase fis uw 0 pp quw pe pe Ed ha ow T rn 4 4 5 5 pe Lh gt D Ww N N SPN ole spn sa Nn w 1 tA 13 19 23 25 29 31 3 3 39 3 9 3 5 57 59 1 1 20 22 32 40 4 4 48 4 52 54 56 58 16 20 2 24 26 28 32 40 Lu Eaa as 52 54 a UN YE BARA RZ 8 Guangzhou Embedded Machine Technology Co Ltd CAM PCLK 97 Cms 9 CAM XCLKA CAM WEN CAM STROBE C
4. 50 o a a a
5. 4 2 OMAP35x Processor Block Diagram info a esys ir 9 http www esys ir Embedded Designer in IRAN ma an ardazesh Sabz OMAP Applications Processor CVBS Dual or Camera LCD Panel S Video serial and MPU Parallel IVA 2 2 Subsystem TMS320DM64x DSP Subsystem Imaging Video and ARM Cortex Audio Processor Parallel Camera AB Core ISP 32K 32K L1 TrustZone 48K L1D RAM meg 16K 16K L1 Capture 64K L2 2DI3D Dual Output 3 Layer Hard 32K L2 RAM Graphi Display Processor ka 16K L2 ROM raphics 1xGraphics 2xVideo mege Video Hardware Accelerator Temporal Dithering Pipeline Accelerators 3530 only SDTV OCIF Support 64 L3 Interconnect Network Hierarchial Performance and Power Driven 32 32 SDRAM GPMC Memory General Scheduler Purpose Rotation Memory Controller NAND System Controls PRCM Peripherals 3xUART 3xHigh Speed I2C 5xMcBSP 2x with Sidetone Audio Buffer 4xMcSPI 6xGPIO 2xSmartReflex Control Module SDRC NOR SDRAM Flash Memory SRAM Controller 3xHigh Speed MMC SDIO HDQ 1 Wire 2xMailboxes 12xGPTimers 2xWDT External 32K Sync Timer Peripherals Interfaces Emulation External and Debug SDTI ETM JTAG Stacked Memories Coresight DAP Figure 2 1 OMAP35x Processor Block Diagram NOTE The block diagram pictured above comes from TI s OMAP3530 25 Applications Processor Data Sheet 2 5 Clocks The OMAP35x requires an oscillator and
6. power supply network normally supply current is the half of the maximum value 3 Power Consumption Condition SOM53x work in maximum speed and the external power supply in maximum current speed 2 3 Mechanical data Primary Purpose OMA P35XSystem on Module PCB size 1 37 x 2 51 inch 34 8 x 63 75mm sum 3 picture2 1 TI DM3730 EM CORE BOARD PCB size diagram 2 4 Processor 2 4 1 OMAP35x Processor The TI DM3730 EM CORE BOARD uses TI s high performance OMAP35x Applications Processor This device features the Superscalar ARM Cortex A8 RISC core and provides many integrated on chip peripherals including 8 E 88633449 http www esys ir 88963982 info esys ir lS TM 9821 jaa Qrilo ardazesh Sabz 9821 88633449 88963982 Embedded Designer in IRAN ma an Superscalar ARM CortexTM A8 RISC core gt Vectored floating point unit 16 Kbytes data L1 cache 64 Kbyte RAM Vv Vv V WV 32Kbyte ROM Integrated LCD Controller 3 UART I2S codec interface 9 9 host interface Programmable timers Real time clock RTC 9 Low power modes See TI s OMAP35x TRM and Data Sheet available from TI s website 16 Kbytes instruction Ll cache One high speed USB 2 0 On the Go OTG interface and one high speed USB 2 0 Many general purpose I O GPIO signals for additional information the documents are 2
7. that can be configured as input or output Most of the OMAP35x processors can be configured as GPIO input or output of other and have different functions It is essential to review the final design including electrical and software all the signals to verify the necessary configuration external pull ups pull downs IMPORTANT NOTE Please pay special attention to the reference voltage of the OMAP35x used to power each signal in the table below especially when used as a GPIO Not all power rails coming out of the TPS65930 are on by default and may need to be enabled through software 5 1 Connector Descriptions Connector list No LED list Power LED Power List DEE v pt RTC ary VDD_AUX2 1 8V 100mA Output Controllable 1 8V power output http www esys ir Embedded Designer in IRAN He PN D eae ardazesh Sabz Test Point list T2 HFCLKOUT VDD AUX VDD CORE YDDIO 5 2Pin Descriptions amp Functions J1 Connector Pin Descriptions GPIO GPMC A10 GPMC_A9 1 8V 1 ux EN p 21 GPMC AI 1 8V 1 8V 1 8V i 1 8V 1 8V 1 8V 1 8V MEE MER ERR NEN EE MEE EN n GPMC DIO 1 8V GPMC Di1 1 8V GE DI EN EE 36 35 34 FEN IE EET UM H Ho 44 45 46 EU No 43 42 41 40 39 38 36 35 34 44 45 46 47 48 ardazesh Sabz 5 5 5 5 5 1 3 5 1 9
8. 1 Alternate SYS_BOOT 6 0 1000110 MMC1 USB 3 7 ESD Considerations The TI DM3730 EM CORE BOARD was designed to interface to a customer s peoard while remaining low cost and adaptable to many different applications The TI DM3730 EM CORE BOARD does not provide any onboard ESD protection circuitry this must be provided by the product it is used in 20 88633449 http www esys ir 9821 990963987 ifo esys ir I L Embedded Designer in IRAN ardazesh Sabz gt gt eae 4 Memory amp I O Mapping On the OMAP35x microcontroller all address mapping for the GPMC chip select signals is listed below Mapped Chip Selectl signals for the OMAP are available as outputs from the microcontroller and are assigned as follows nCS3 uP_nCS3 Available for use by an off board external nCS4 uP_nCS4 Available for use by an nCS5 uP_nCS5 Available for use by an off board external off board external NOTE Memory addresses for chip selects on the OMAP35x are configurable by software Therefore precise address locations cannot be provided 21 GE 7 lt 88633449 l http www esys ir 982188963987 info esys ir lS c L Embedded Designer in IRAN jee JAIS D e ardazesh Sabz 5 Connector description and function IMPORTANT NOTE The following pin descriptions and states are provided by the default pin usage the signal of defined in the connection table lots of
9. 30 PMIC see Section 5 Pin Descriptions amp Functionsl for more information If certain peripherals are not desired such as the LCD controller chip selects IRQs or UARTS then more GPIO pins become availab le 2 12 Expansion Feature Options The TI DM3730 EM CORE BOARD was designed for expansion and a variable feature set providing all the necessary control signals and bus signals to expand the user s design It is possible for a user to expand the TI DM3730 EM CORE BOARD s functionality even further by adding host bus or ISA bus devices Some features that are implemented on the OMAP35x but are not discussed herein include RTC pulse width modulation PWM Secure Digital MMC cards SDIO cards graphics accelerator DSP codecs Image Processing Unit lw ire interface and the debug module Embedded Designer in IRAN us ue 15 88963982 http www esys ir 88963982 info esys ir Embedded Designer in IRAN ardazesh Sabz 3 System Integration 3 1 Configuration OMAP35x TI DM3730 EM CORE BOARD was designed to meet multiple app licat ions for users with specific design and budget requirements As a result this TI DM3730 EM CORE BOARD supports a variety of embedded operating systems and hardware configurations Please contact PardazeshSabz Sales for additional hardware configurations to meet your application needs 3 2 Reset TI DM3730 EM CORE BOARD has a reset input SYS nRESPWRON and a reset output
10. AM D2 CAM D6 CAM D9 CAM_D10 CAM D11 AV S VIDEO Y 97 94 1l 167 126 100 101 102 103 104 105 106 107 108 109 110 wxoc J3 Connector Pin Descriptions 1 om 2 C2_DAT7 N o 139 138 137 136 135 134 133 132 130 131 178 181 180 Embedded Designer in IRAN os 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V 1 8V CVBS output S Video output Y channel S Video output C channel GPIO I O Voltage Remark z swmp po isv jew 6 3 X USB2 D4 ardazesh Sag B2 D3 USB2 D2 B2 DI B2 DO B2 NXT JSB2_STP USB2_CLK Guangzhou Embedded Machine Technology Co z c on z 2 E c on c Nn z 2 A PREDRIV RIGHT PREDRIV LEFT OIE Q Z Z Z oJ U Signal Name HS US B2_DIR S YS_DRM_M SECURE GPIO22 HS US B2_D0 MCSPI3_SIMO GPIO14 HS US B2_D1 MCSPI3_SOMI GPIO15 HS US B2_D2 MCSPI3_CS0 G PIO16 HSUSB2 D3 GPIO21 HSUSB2 D4 GPIO18 HS US B2_D5 GPIO19 HS US B2_D6 GPIO20 HS US B2_D7 MCSPI3_CLK GPIO17 ND 32 o 37 43 NH EN Embedded Designer in IRAN ows 1 8V IO output p A X IE ECRHSUS IR AY R Ltd 179 182 177 9 8 J 6 5 4 NIN NINIJIN o UN 29 28 237 26 25 24 ES m I O Voltage Remark L8V 0 4 d m iv 7
11. E N 7 LN 1982188633449 info esys ir http www esys ir 88963982 ym Embedded Designer in IRAN jee JAIS ul oe ardazesh Sabz 1 Introduction 1 1 Product Overview The SOM35x module based on TI s OMAP35x processor family is a compact product ready hardware and software solution that fast forwards embedded designs The SOM35x provides high performance and low power within tight space constraints for applications SOM35x support Linux 2 6 31 WinCE6 0 Android and other embedded operating system SOM35x provides a mass of software resources such as DVSDK OpenGL ES2 0 OGRE and etc The SOM35x is an off the shelf solution that reduces development risks associated with the complex design and manufacturing details of the OMAP3 processor that Speed Time to Market The compact SOM35x is an ideal off the shelf solution for applications that include medical devices barcode readers mobile Internet devices Image Capture Machine GPS and 3D Game machine The SOM35x allows for powerful versatility compact designs and long life products Picture 1 1 TI DM3730 EM CORE BOARD 1 2 Acronyms ADC Analog to Digital Converter BSP Board Support Package BTB Board to board DDR Double Data Rate RAM DMA Direct Memory Access 4 Co 88633449 http www esys ir 982158963982 info Pesys ir IS c Embedded Designer in IRAN a PJ n ardazesh Sabz ESD Electrostatic Discharge FIFO First In First Out GPIO General P
12. O J DNE ENE ONE EN DEE NEE a he N o o hsv 19 fisy mw _ he d o 27 YF HE http WWW CS Embedded Designer in IRAN VDD MMCI MMCI1 Power MMC1_CMD MMC1_CLK MMCI DATO MMC DATI MMCI_DATD 1 i 1 13 MMCI DAT3 15 MMCI DAT4 17 19 MMCI DATS MMC1_DAT6 21 MMCI DAT7 23 9 Em 5 7 EWN B 27 29 EWN 33 Ed 37 39 a E E C 5i T2 MMC1_CD T2 GPIOO MMC check USB OTG ID 21 29 31 33 35 37 39 41 43 45 47 49 51 HSUSBO ID HSUSBO DN HSUSBO DP VBUS HSUSBO T2 GPIO1 T2 GPIO2 T2 GPIOG T2 PWMO T2 GPIO7 T2 PWMI T2 GPIO15 T2 ADCINO T2 ADCIN2 VDD_AUX2 VDD_RTC Q Z U 5 Q Z U VDD_SOM VDD_SOM GPIO Signal Name No MCBSP1_CLKR GPIO156 MCBSP1_FSR GPIO157 MCBSP1_DX GPIO158 MCBSP1_DR GPIO159 MCBSP1_FSX GPIO161 MCBSP1_CLKX GPIO162 SYS BOOTS SYS_BOOT4 SYS_BOOT3 SYS_BOOT2 SYS_BOOT 1 SYS_BOOTO I2C3 SCL I2C3 SDA I2C2 SCL I2C2 SDA JTAG TDO JTAG nTRST JTAG TMS JTAG TDI JTAG TCK JTAG RTCK JTAG EMUO JTAG PMU T2 KPD RO T2 KPD R1 T2 KPD R2 T2 KPD R3 T2 KPD R4 T2 KPD R5 ae oo oc 2 4 6 8 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 1 1 1 6 Embedded Designer in IRAN ul er SOM Power Input SOM Power Input I O Voltage E a a a a oo oe a oo So oo o i gt li Bo
13. P3 GPMC 32x full signal output resource 6 Ed 88633449 http www esys ir 88963982 info esys ir o EEE 9821 Embedded Designer in IRAN A VR ul oe ardazesh Sabz Ix OMAP3 DSS bus full signal output 1x AV S Video 1x AV S Video output esses 1x Camera bus full signal output 2x SPI bus 1 route multiplex with 1 route HSUSB 3x 4 cable UART RX TX CTS RTS 2x MCBSP bus 1 route multiplex with 2 route UART 2x MMC bus full signal output 1x HSUSB OTG 2x HSUSB ULPI bus full signal output 2x I2C bus 1x OneWire bus 1x TI standard JTAG 1x stereo headphone output Dual Channel 1x Mono Channel microphone input 1x Mono Channel Audio output 6x extra GPIO Power Management IC derivation gt include 2 route PWM 2x ADC input 5x boot selection signal 5x Power management signal 2 route system Reset 1 route rouse 2 route external power control 6x6 matrix scanning keyboard 2 2 Operating conditions Power supply 3 3V 80mA L 1 3 3V 200mA L X2 3 3V 500mA 3 saw 1 660mWw 92 1650mW 3 Temperature Commerca o0 V WC ewe a 8c http Embedded Designer in IRAN dew UII NEE ardazesh Sabz 1 Power Consumption Condition SOM53x work in a low power consumption state and cut down all external power supply 2 Power Consumption Condition SOM53x work in high speed and all the external
14. crystal to enable proper internal timing A 26 000 MHz oscillator is used to generate many of the processor s internal clocks via a series of Phase Lock Loops PLLs and signal dividers To generate the core CPU clock the 26 000 MHz signal is run through a Digital PLL controlled by the PRCM registers Divisors are used to divide down the internal bus frequency to set the LCD memory controller camera interface etc The second required crystal runs at 32 768 kHz and is connected directly to the TPS65950 The 32 768 kHz clock is used for PMIC and CPU start up and as a reference clock for the Real 10 E 1982188633449 info esys ir http www esys ir 88963982 9 7 Embedded Designer in IRAN jee JAIS EEN ardazesh Sabz Time Clock RTC Module The CPU s microcontroller core clock speed is initialized by software on the Torpedo SOM The DDR SDRAM bus speed is set at 166 MHz in LogicLoader Other clock speeds such as core speed and specific serial baud rates can be supported and modified in software for specific user applications The TI DM3730 EM CORE BOARD provides an external bus clock uP_BUS_CLK This clock is driven by the GPMC_CLK pin OMA P35x_ Microcontroller TI DM3730 EM CORE Default Software Value in Signal Name BOARD Net Name X Loader CORE N A Up to 600 MHz SDRC_CLK N A 166 MHz GPMC_CLK uP_BUS_CLK Not configured IMPORTANT NOTE Please see TI s OMAP35x TRM for additional information about proces
15. esigner should keep in mind cost availability ESD protection and data rates The UARTA baud rate is set to a default 115 2 Kbits sec though it supports most common serial baud rates 2 9 2 UART2 Serial Port UART3 is an asynchronous 16C750 compatible UART This UART is a high speed serial interface that uses FIFO and is capable of sending and receiving serial data simultaneous ly The signals from the Torpedo SOM are 1 8V TTL level signals not RS232 level signals The UART 2 baud rate can also be set to most common serial baud rates 2 9 3 UART3 Serial port UART3 is an asynchronous 16C750 compatible UART This UART is a high speed serial interface that uses FIFO and is capable of sending and receiving serial data simultaneous ly The signals from the TI DM3730 EM CORE BOARD are 1 8V TTL level signals not RS232 level signals The UARTC baud rate can also be set to most common serial baud rates 13 88633449 http www esys ir 9821 88963982 info esys ir ardazesh Sabz 9821 2 9 4 MsSPI Embedded Designer in IRAN D P The Torpedo SOM provides three external SPI ports with multiple chip selects Additional SPI ports are available through different resistor populations Please see Table 5 1 for more information 2 9 5 I2C The TI DM3730 EM CORE BOARD supports two dedicated external I2C ports The clock and data signals for the I2C2 port have 4 7K ohm pull up resistors the clock and data signal
16. interrupt controller which provides many intersystem Most external GPIO signals can also be configured as interrupt inputs by configuring their pin control registers PardazeshSabz BSP s setup and process all onboard systern and external TI DM3730 EM CORE BOARD interrupt sources Refer to TI N OMAP35x TRM for further information on using interrupts 3 4JTAG Debugger Interface The JTAG connection on the OMAP35x allows recovery of corrupted flash memory real time application debug and DSP development There are several third party JTAG debuggers available for TI microcontrollers The following signals make up the JTAG interface to the OMAP35x processor TDI TMS TCK TDO nTRST RTCK EMUO and EMUI When laying out the 20 pin connector realize that it may not be numbered as a standard 20 pin 0 1 insulation displacement connector IDC through hole connector Each JTAG tool vendor may define the 20 pin IDC connector pin out differently 3 5 Power Manage ment http www esys ir 7 Embedded Designer in IRAN ul ec SYS_nRESPWRON signal source so the custom design must ensure that the assertion time is Embedded Designer in IRAN ardazesh Sabz o 00 3 5 1 System Power Supplies In order to ensure a flexible design the Torpedo SOM has the following power areas VDD SOM and VDD RTC All power areas are inputs to the TI DM3730 EM CORE BOARD The module also provides VIO 1V8 as a reference voltage It may be used to su
17. l Embedded Designer in IRAN He ib MEEN ardazesh Sabz TI DM3730 EM CORE BOARD User Manual 1 88633449 http www esys ir Se ee n 982138963982 info esys ir TTT Embedded Designer in IRAN ardazesh Sabz o l0 I Catalogue st yide UO 4 11 PRO DUC T OVERVIEW 12 ACRONYMS 13 TI DM3730 EM CORE BOARD BLOCKDIAGRAM eene eene nennen 6 2 ELECTRICAL SPECIFICATION cuta ee see ee ente erat ek ane FERRY DL ese Eg ek GN Gee gekos seen deeg Eed 6 2 1 2 2 2 3 MECHANIC AL DATA iiirciucicnic tini tr B ane kes KG KS e Fh ta Sk ER Fo Hon Le Ge denice RR EN Ed 8 2 4 PROCESSOR lll ne rd dud ein eren treten EE VERE EE Y Ee reve odd 8 2 4 1 OMAP35x Processor eese tarta Ee Pak Ee Be ae asas ene se se se ps ena enda aane Ke ERA an deban Be oaa ua 8 2 4 2 OMAP35x Processor Block Diagram essere tente ttn Ge ntt Ge Ge ee ee 9 2 5 LS belese AA AE VEER e ore EEN 2 6 MEMORY 2 6 1 Mobile DDR and NA ND 8 sss a nn EG ee Ge Ge 11 2 62 E ternal Memory sesse sees see see ses ee a ee ee ae n 12 2 7 AUBIO CODRC ssim t E se ee NEO ee ek aans 12 2 8 2 9 2 9 1 2 9 2 2 9 3 AE MEME SAAD oe N N N EE 14 2 95 ET EE EER ER HO ER EE AE IE 14 2 9 6 Reserved DC Addresses uil Be ee ee ee Bee Se Ge Ak ttai AE ee 14 2 10 TUSBEINTERFACE ii ee eee SEE ee ee ee cnet nere ee 14 PX MEC KEN EN EE OE ER EE EE EEN
18. pply up to 200 mA of power but it is recommended to use an external supply 1 VDD SOM The VDD SOM input is the main source of power for the TI DM3730 EM CORE BOARD This input expects a voltage within typical single lithium ion battery limits which generally operate from 2 7V to 4 2V If a lithium ion battery is not used as the main power source it is recommended to supply a fixed 3 3 V supply The TPS65930 power management controller takes the VDD SOM rail input and creates all onboard voltages If the design is required to maintain RAM contents in a critical power situation e g low battery loss of power the VDD SOM supply should be maintained above the minimum level at all costs we suggest using the Standby mode to prepare the system for a critical power condition In this way the DDR SDRAM is placed into self refresh and the processor is placed into the Standby state 2 VDD_RTC The VDD RTC power rail for power supply board TPS65930 Power management state machine and RTC circuit when VDD SOM is not present A lithium ion coin cell typically supplies power to this rail The TPS65930 overrides this input when VDD SOM is applied 3 5 2 System Power Manage ment Good power management design is important in any system development and embedded system design is no exception In embedded system design power management is typically one of the most complicated areas due to the dramatic effect it has on product cost performance u
19. rated LCD controller The signals from the OMAP35x LCD controller are organized by bit and color and can be interfaced through the expansion connec tors PardazeshSabz provide 4 3 inch resolution is 480x272 and 7 inch resolution is 800x480 TFT touch screen panel IMPORTANT NOTE Using the internal graphics controller will affect processor performance Selecting display resolutions and color bits per pixel will vary processor busload 2 9 Serial Interfaces The TI DM3730 EM CORE BOARD comes with the follow ing serial channels http www esys ir OM infensi OO M Embedded Designer in IRAN D P Embedded Designer in IRAN He PN ue ardazesh Sabz UARTI UART2 UART3 three SPI ports two MCBSP and two I2C ports If additional serial channels are required please contact PardazeshSabz Please see TI DM3730 EM User Manual for further information regarding serial communications 2 9 1 UARTI UART1 has been configured as the main SOM35x serial port based on the processor It is an asynchronous 16C750 compatible UART This UART provides a high speed serial interface that uses 64 byte First In First Out FIFO and is capable of sending and receiving serial data simultaneously The signals from the Torpedo SOM are 1 8V Transistor Transistor Logic TTL level signals not RS232 level signals The end product design must provide an external RS232 transceiver for RS232 applications When choosing an RS232 transceiver the d
20. red power supplies are active in this state 2 Suspend State Suspend is the hardware power down state for the SOM allowing for lower power consumption The Suspend state is designed to reduce power consumption while the OMAP35x is waiting for an event such as a keyboard input In BSPs All power supplies remain active and system context is retained An internal or external wakeup event can cause the processor to transition back to Run mode 3 Standby State Standby is the lowest power state for the SOM This state is entered in ParcazeshSabz BSPs through softw are commands The OMAP35x processor is put into the lowest power state and all Embedded Designer in IRAN D eae clocks are 19 a 88633449 http www esys ir 88963982 info esys ir Embedded Designer in IRAN jee JAIS ud ardazesh Sabz stopped The VDD_SOM power rail should be maintained if the low power DDR SDRAM contents wish to be retained Internal or external wakeup events can cause a return to the Run state 3 6 Boot Modes The OMAP35x provides the option of booting from multiple sources The boot mode is controlled by the SYS_BOOT pins of the processor SYS BOOTO and SYS BOOTS are available off board through the expansion connectors OMA P35x Processor Pins Boot Method Default SYS BOOT 6 0 21101111 USB UART3 MMCI1 NAND Alternate SYS_BOOT 6 0 1001111 NAND USB UART3 MMC 1 Alternate SYS_BOOT 6 0 1001110 XIPwait DOC USB UART3 MMC
21. s for the I2C3 port have 470 ohm pull up resistors Please see TI S OMAP35x TRM for further information 2 9 6 Reserved I2C Addresses The OMAP35x Torpedo SOM contains a product ID chip that connects to the I2C bus PardazeshSabz software uses this product ID chip to determine hardware version information As a result the 7 bit I2C addresses listed below are used by the product ID chip and must be avoided in custom designs function as 101 1000 101 1001 101 1010 101 1011 101 1100 101 1101 2 10 USB Interface The TI DM3730 EM CORE BOARD information on using the OTG 88633449 88963982 info esys ir supports one USB 2 0 OTG port which can a host or device client The port can operate at up to 480 Mbit sec For more 14 http www esys ir 9821 ardazesh Sabz interfaces please see T s OMAP35x TRM IMPORTANT NOTE In order to correctly implement USB on the SOM3530 B2 additional impedance matching circuitry may be required on the USB2_D and USB2_D signals before they can be used USB 2 0 requirements specify the signals must be routed as differential pairs with 90 ohm differential impedance Refer to the USB 2 0 Specification for detailed information 2 11 GPIO PardazsehSabz design ed the TI DM3730 EM CORE BOARD to be flexible and provide multiple options for analog and digital GPIO There are numerous digital GPIO pins on the Torpedo SOM that interface to the OMAP35x processor and TPS659
22. sability and overall customer satisfaction Many factors affect a power efficient hardware design power 18 88633449 http www esys ir 1982128963082 info esys ir o 9821 Jaan u Jl5 ardazesh Sabz supply selection efficiency clocking design IC and component selection etc On the OMAP35x there are many different software configurations that drastically affect power consumption microcontroller core clock frequency bus clock frequency peripheral clocks bus modes power management states peripheral power states and modes product user scenarios interrupt handling and display settings resolution backlight refresh bits per pixel etc These settings are typically initialized in the startup software routines and may be modified later in the operating system and application software T2 REGEN is an open drain output from the TPS65930 It can be used to control power for external power ICs or LDOs Please see the TPS65930 TRM for more information 3 5 3 Microcontroller The OMAP35x processor s power management scheme was designed for the cellular handset market which means the static and dynamic power consumption has very flexible controls allowing designers to tweak the processor to minimize end product power consumption 1 Run State The OMAP35x can enter Run mode from any state A Standby to Run transition occurs on any valid wakeup event such as the assertion or any enabled interrupt signal All regui
23. sor clocking 2 6 Memory 2 6 1 Mobile DDR and NAND The OMAP35x uses a 32 bit memory bus to interface to mobile DDR SDRAM and a 16 bit memory bus to interface to NAND At the time of publication it can be ordered in three density options B 128 MB Mobile DDR and 128 MB NAND Mm 256MB Mobile DDR and 256 MB NAND B 512MB Mobile DDR and 512 MB NAND In TI DM3730 EM CORE BOARD the default memory configuration is designated as 256MB Mobile DDR and 256MB NAND 11 4982188633449 http www esys ir 2199963982 info esys ir Sc LE 9821 ardazesh Sabz 2 6 2 External Memory It is possible to expand the system s non volatile storage capability by adding external flash ICs SD memory Compact Flash or NAND flash 2 7 Audio Codec The OMAP35x processor has multiple Multi channel Buffered Serial Port McBSP interfaces that support PCM and I2S formats Both PCM and I2S serial paths drive the built in TPS65950 audio codec From the TPS65950 the outputs are CODEC_OUTL and CODEC_OUTR these signals are available from the expansion connectors The codec in the TPS65950 performs up to full duplex codec functions and supports variable sample rates from 8 96k samples per second 2 8 Display Interface The OMAP35x has a built in LCD controller supporting STN color STN and TFT panels at a resolution of up to XGA 1024 x 768 x 24 bit color See T s OMAP35x TRM for further information on the integ
24. urpose Input Output GPMC General Purpose Memory Controller GPO General Purpose Output IC Integrated Circuit VO Input Output IRQ Interrupt Request LCD Liquid Crystal Display LDO Low Dropout Regulator McBSP Multi channel Buffered Serial port PCB Printed Circuit Board PCMCIA Personal Computer Memory Card International Association PC Cards PHY Physical Layer PLL Phase lock loop PWM Pulse Width Modulation RTC Real Time Clock SDIO Secure Digital Input Output SDRAM Synchronous Dynamic Random Access Memory SOM System on Module SSP Synchronous Serial Port SPI Standard Programming Interface STN Super Twisted Nematic LCD TFT Thin Film Transistor LCD TI Texas Instruments TSC Touch Screen Controller TTL Transistor Transistor Logic UART Universal Asynchronous Receive Transmit B EA ttp Www esys ir h 88633449 982138963982 info gesys ir O TTT Embedded Designer in IRAN lolo 01 n 1 3 TI DM3730 EM CORE BOARD Block diagram ardazesh Sabz TPS65930 OMAP3 Processor Picture 1 2 TI DM3730 EM CORE BOARD Block diagram 2 Electrical Specification 2 1 Hardware ARM Cortex A8 Core up to 720MHz NEON SIMD Co processor 430MHz TMS320C64x DSP POWERVR SG 2D 3D graphic Acceleration 128MByte 256M Byte 512M Byte DDR 256MByte 512MByte 1G Byte Nand Flash 1x Power LED 2x Programmable LED Processor TI OMAP3530 SOM 4x 0 5mm 60Pin B2B interface interface Te Eis 1x OMA
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