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Microprocessor Peripherals UPI- 41A 41AH 42 42AH User`s Manual

1. Opcode 0000 0000 No operation is performed Execution continues with the following instruction ORL A Rr Logical OR Accumulator With Register Mask Opcode 0100 1 ro r4 ro Data in the accumulator is logically with the mask contained in working register f lt A OR Rr 0 7 Example ORREG ORL A R4 ACC CONTENTS WITH MASK IN REG 4 45 LI UPI 41A 41AH 42 42AH USER S MANUAL intel ORLA Rr Logical OR Accumulator With Memory Mask Opcode 0100 000r Data in the accumulator is logically ORed with the mask contained in the data memory location referenced by register r bits 0 7 lt A OR Rr r 0 1 Example ORDM MOVE MOVE HEX TO REG 0 ORL A RO OR ACC CONTENTS WITH MASK LOCATION 63 Logical OR Accumulator With Immediate Mask Opcode 0100 0011 dz da 95 94 da do dy do This is a 2 cycle instruction Data in the accumulator is logically ORed with an immediately specified mask A A OR data Example ORID ORL A X ACC CONTENTS WITH MASK 301011000 ASCII VALUE OF X ORL Logical OR Port 1 2 With Immediate Mask Opcode 1000 10 py d dg dg d4 dg do dy do This is a 2 cycle instruction Data on port p is logically ORed with an immediately specified mask Pp l
2. Assume accumulator contains signed number isolate sign without changing value RLTC CLR C CLEAR CARRY TO ZERO RLCA ROTATE ACC LEFT SIGN 7 IS PLACED IN CARRY RRA ROTATE ACC RIGHT VALUE BITS 0 6 IS RESTORED CARRY UNCHANGED 7 18 ZERO Rotate Right Without Carry Opcode Example 0111 0111 The contents of the accumulator are rotated right one bit Bit 0 is rotated into the bit 7 position lt An D n 0 6 lt Ao Assume accumulator contains 10110001 RRNC RRA NEW ACC CONTENTS ARE 11011000 RRCA Rotate Right Through Carry 48 Opcode Example 0110 0111 The contents of the accumulator are rotated one bit Bit 0 replaces the carry bit the carry bit is rotated into the bit 7 position An Ay 1 n 0 6 A7 lt Ag Assume carry is not set and accumulator contains 10110001 RRTC RRCA CARRY IS SET AND ACC CONTAINS 01011000 intel UPI 41A 41AH 42 42AH USER S MANUAL SELRBO Select Register Bank 0 Opcode 1100 0101 PSW BIT 4 is set to zero References to working registers 0 7 address data memory locations 0 7 This is the recommended setting for normal program execution BS lt 0 SELRB1 Select Register Bank 1 Opcode Example 1101 0101 PSW bit 4 is set to one References to working registers 0 7 address data memory locations
3. The setting of the carry bit is complemented one is changed to zero and zero is changed to one lt NOT Example Set C to one current setting is unknown CTOI CLR C C IS CLEARED TO ZERO CPL C CIS SET TO ONE CPL F0 COMPLEMENT FLAG 0 Opcode 100110101 The setting of Flag 0 is complemented one is changed to zero and zero is changed to Fy lt NOT F0 CPLF1 Complement Flag 1 Opcode 1011 0101 The setting of the F Flag is complemented one is changed to zero and zero is changed to one lt NOT Fj 34 intel UPI 41A 41AH 42 42AH USER S MANUAL DAA Decimal Adjust Accumulator Opcode Example 0101 0111 The 8 bit accumulator value is adjusted to form two 4 bit Binary Coded Decimal BCD digits following the binary addition of BCD numbers The carry bit C is affected If the contents of bits 0 3 are greater than nine or if AC is one the accumulator is incremented by six The four high order bits are then checked If bits 4 7 exceed nine or if C is one these bits are increased by six If an overflow occurs C is set to one otherwise it is cleared to zero Assume accumulator contains 9AH DA ADJUSTED TO 01H with C set C AC ACC 0 0 9AH INITIAL CONTENTS 06H ADD SIX TO LOW DIGIT 0 0 60H ADD SIX TO HIGH DIGIT 1 0 01H RESULT DEC A Decrement Accumulator Opcode Example 0000 0111
4. The contents of the accumulator are decremented by one A 1 Decrement contents of data memory location 63 MOV RO 3FH MOVE HEX TO REG 0 MOV A RO MOVE CONTENTS OF LOCATION 63 ACC DEC A DECREMENT ACC MOV RO A MOVE CONTENTS OF ACC TO LOCATION 63 DEC Rr Decrement Register Opcode Example 1100 The contents of working register are decremented by one Rr lt Rr 1 0 7 DECR1 DEC R1 DECREMENT ADDRESS REG 1 DIS Disable IBF Interrupt Opcode Note 0001 0101 The input Buffer Full interrupt is disabled The interrupt sequence is not initiated by WR and CS however an IBF interrupt request is latched and remains pending until an EN I enable IBF interrupt instruction is executed The IBF flag is set and cleared independent of the IBF interrupt request so that handshaking protocol can continue normally 35 LI UPI 41A 41AH 42 42AH USER S MANUAL intel DIS TCNTI Disable Timer Counter Interrupt Opcode DJNZ Rr address 0011 0101 The timer counter interrupt is disabled Any pending timer interrupt request is cleared The interrupt sequence is not initiated by an overflow but the timer flag is set and time accumula tion continues Decrement Register and Test Opcode Note Example 1110 1 r2 r4 ro a7 ag 85 This is a 2 c
5. Figure 2 19 Recommended PORT Input Connections 24 in UPI 41A 41AH 42 42AH USER S MANUAL CHIP SELECT CONNECTION IF MORE THAN ONE EXPANDER IS USED cs P4 PORT 4 INPUTS UPI 41A 41AH 5 PORT 5 42 42AH 8243 PORT 6 P7 PORT 7 231318 25 BITS 0 1 BITS 2 3 PROG 00 00 READ 01 PORT 01 WRITE 10 ADDRESS 10 OR 11 11 AND 20 23 ADDRESS 4 BITS DATA 4 5 231318 26 Figure 2 20 8243 Expander Interface DATA BUS CONTROL CONTROL BUS PORT 1 UPI 41A 41AH 42 42AH PORT 2 PROG 231318 27 Figure 2 21 Multiple 8243 Expansion 25 UPI 41A 41AH 42 42AH USER S MANUAL intel CHAPTER 3 INSTRUCTION SET The UPI 41A 41AH 42 42AH Instruction Set is op code compatible with the MCS 48 set except for the elimination of external program and data memory in structions and the addition of the data bus buffer in structions It is very straightforward and efficient in its use of program memory All instructions are either 1 or 2 bytes in length over 70 are only 1 byte long and over half of the instructions execute in one machine cycle The remainder require only two cycles and in clude Branch Immediate and I O operations The UPI 41A 41AH 42 42AH Instruction Set effi ciently handles the single bit operations required in control applications Special instructions allow port bits to be set or cleared individually Also any accumul
6. INTERRUPTS The UPI 41A 41AH 42 42AH has the following in ternal interrupts Input Buffer Full IBF interrupt Timer Overflow interrupt The IBF interrupt forces a CALL to location 3 in pro gram memory a timer overflow interrupts forces a CALL to location 7 The IBF interrupt is enabled by the EN I instruction and disabled by the DIS I instruc tion The timer overflow interrupt is enabled and dis abled by the EN TNCTI and DIS TCNTI instructions respectively intel Figure 2 14 illustrates the internal interrupt logic An IBF interrupt request is generated whenever WR and CS are both low regardless of whether interrupts are enabled The interrupt request is cleared upon entering the IBF service routine only That is the DIS I instruc tion does not clear a pending IBF interrupt Interrupt Timing Latency When the IBF interrupt is enabled and an IBF inter rupt request occurs an interrupt sequence is intiated as soon as the currently executing instruction is complet ed The following sequence occurs A CALL to location 3 is forced The program counter and bits 4 7 of the Program Status Word are stored in the stack The stack pointer is incremented Mp cs INTERRUPT REQUEST IBF INTERRUPT REQUEST er ES INTERRUPT RECOGNIZED gt RESET IBF INTERRUPT ENI ENABLE INTERRUPT ENABLE DIS I gt RESET mmer L l OVERFLOW TIMER INTERRUPT RECOGNIZED EN
7. 13 UPI 41A 41AH 42 42AH USER S MANUAL Table 2 2 lists the internal conditions which are testable and indicates the condition which will cause a jump In all cases the destination address must be within the page of program memory 256 locations in which the jump instruction occurs OSCILLATOR AND TIMING CIRCUITS The UPI 41A 41AH 42 42AH s internal timing gen eration is controlled by a self contained oscillator and timing circuit A choice of crystal L C or external clock can be used to derive the basic oscillator frequen cy The resident timing circuit consists of an oscillator a state counter and a cycle counter as illustrated in Fig ure 2 9 Figure 2 10 shows instruction cycle timing Oscillator The on board oscillator is a series resonant circuit with a frequency range of 1 to 12 5 MHz depending on intel which UPI is used Refer to Table 1 1 Pins XTAL 1 and XTAL 2 are input and output respectively of a high gain amplifier stage A crystal or inductor and capacitor connected between XTAL 1 and XTAL 2 provide the feedback and proper phase shift for oscilla tion Recommended connections for crystal or L C are shown in Figure 2 11 State Counter The output of the oscillator is divided by 3 in the state counter to generate a signal which defines the state times of the machine Each instruction cycle consists of five states as illustrat ed in Figure 2 10 and Table 2 3 The overlap of address and executio
8. Repeat step 1 above UPI 41A 41AH 42 42AH USER S MANUAL WR UPI 41A 41AH 42 42AH OBB 1 WR UPI 41A 41AH AO 42 42AH DBB 2 DATA BUS WRUPI 41A 41AH 42 42AH 231318 42 Figure 5 11 Distributed Processor System 61 UPI 41A 41AH 42 42AH USER S MANUAL intel CHAPTER 6 APPLICATIONS ABSTRACTS The UPI 41A 41AH 42 42AH is designed to fill a wide variety of low to medium speed peripheral inter face applications where flexibility and easy implementa tion are important considerations The following exam ples illustrate some typical applications Keyboard Encoder Figure 6 1 illustrates a keyboard encoder configuration using the UPI and the 8243 I O expander to scan a 128 key matrix The encoder has switch matrix scan ning logic N key rollover logic ROM look up table FIFO character buffer and additional outputs for dis play functions control keys or other special functions PORT 1 and PORTs 4 7 provide the interface to the keyboard PORT 1 lines are set one at a time to select the various key matrix rows When a row is energized all 16 columns PORTs 4 7 inputs are sampled to determine if any switch in the row is closed The scanning software is code effi cient because the UPI instruction set includes individu al bit set clear operations and expander PORTs 4 7 can be directly addressed with single 2 byte instruc tions Also accumulator bits can be te
9. 0 2 2 MOV Rr data Move immediate to register 2 2 JT1 addr Jump on T4 1 2 2 MOV Rr Move immediate to JNT1 addr Jump on T4 0 2 2 data data memory 2 2 JFO addr Jump on Fo Flag 1 2 2 MOV PSW Move PSW to A 1 1 JF1 addr Jump on F4 Flag 1 2 2 MOVPSW A Move A to PSW 1 1 JTF addr Jump on Timer Flag 1 2 2 XCH A Rr Exchange A and registers 1 1 JNIBF addr Jump on IBF Flag 0 2 2 XCH A Rr Exchange A and JOBF addr Jump on OBF Flag 1 2 2 data memory 1 1 JBb addr Jump on Accumulator Bit 2 2 XCHD A Exchange digit of A Rr and register 1 1 29 LI UPI 41A 41AH 42 42AH USER S MANUAL intel ALPHABETIC LISTING ADDA Rr Add Register Contents to Accumulator Opcode 0110 1 fo ry The contents of register r are added to the accumulator Carry is affected lt A Rr 0 7 Example ADDREG ADD A R6 ADD REG 6 CONTENTS ACC ADDA Rr Add Data Memory Contents to Accumulator Opcode 0110 000r The contents of the standard data memory location address by register r bits 0 7 are added to the accumulator Carry is affected A Rr r 0 1 Example ADDM MOV RO 47 MOVE 47 DECIMAL TO REG 0 ADD A GRO ADD VALUE OF LOCATION 47 TO ACC ADD Add Immediate Data to Accumulator Opcode 0000 0011 dz da 95 94 da do dy do This is a 2 cycle instruction The specified data is added to the accumulator C
10. 0101 1 fo ry ro Data in the accumulator is logically ANDed with the mask contained in working register r A lt A AND Rr 0 7 ANDREG ANL A R3 ACC CONTENTS WITH MASK MASK IN REG 3 ANL A GRr Logical AND Accumulator With Memory Mask Opcode 0101 000r Data in the accumulator is logically ANDed with the mask contained in the data memory location referenced by register r bits 0 7 lt AND Rn r 0 1 Example MOV RO 0FFH MOV FF HEX TO REG 0 ANL 0AFH ACC CONTENTS WITH MASK IN LOCATION 63 31 LI UPI 41A 41AH 42 42AH USER S MANUAL intel ANL A data Logical AND Accumulator With Immediate Mask Opcode Example 0101 0011 dz da 95 94 da do dy do This is a 2 cycle instruction Data in the accumulator is logically ANDed with an immediate ly specified mask A lt AND data ANDID ANL A 0AFH AND ACC CONTENTS WITH MASK 10101111 ANL A X Y AND ACC CONTENTS WITH VALUE OF EXP 34 X Y ANL Logical AND PORT 1 2 With Immediate Mask Opcode Note Example 1001 10 py Po dz dg 95 94 da do dy do This is a 2 cycle instruction Data on the port p is logically ANDed with an immediately specified mask Pp lt Pp AND data p 1 2 Bits 0 1 of the opcode are used to represent PORT 1 and PORT 2 If
11. ALU and is often the destination for results as well Data to and from the I O ports and memory normally passes through the accumulator DBB STATUS REGISTER T 8 DBBOUT 2 2 dE MASTER 4 0 INTERFACE WR CONTROL Logic ARITHMETIC LOGIC UNIT CRYSTAL XTAL LC OR 9 PRON PROGRAM SUPPLY 5 SUPPLY 5 GROUND INTERNAL BUS DATA MEMORY x B 128 x B 256 RANDOM DECODE ACCESS MEMORY _ PERIPHERAL INTERFACE Poo Pay PORT 4 7 EXPANDER INTERFACE 1K 2KX 8 FROM ROM PROGRAM MENORY TESTO CONDITIONAL BRANCH LOGIC TESTI 10 BIT PROGRAM COUNTER 8 BIT TIMER EVENT COUNTER 231318 9 Figure 2 4 UPI 41A 41AH 42 42AH Block Diagram 10 intel PROGRAM MEMORY The UPI 41A 41AH 42 42AH microcomputer has 1024 2048 8 bit words of resident read only memory for program storage Each of these memory locations is directly addressable by a 10 bit program counter De pending on the type of application and the number of program changes anticipated three types of program memory are available 8041AH 8042AH with mask programmed ROM Memory 8741AH 8742AH with electrically programmable OTP EPROM Memory 8741A and 8742 with electrically programmable EPROM Memory A program memory map is illustrated in Figure 2 5 Memory is divided
12. intel CHAPTER 5 SYSTEM OPERATION BUS INTERFACE The UPI 41A 41AH 42 42AH Microcomputer func tions as a peripheral to a master processor by using the data bus buffer registers to handle data transfers The DBB configuration is illustrated in Figure 5 1 The UPI Microcomputer s 8 three state data lines 7 con nect directly to the master processor s data bus Data transfer to the master is controlled by 4 external inputs to the UPI Ag Address Input signifying command or data CS Chip Select RD Read strobe WR Write strobe CONTROL Bus STATUS REGISTER DATA BUS INPUT REGISTER DATA BUS OUTPUT REGISTER 231318 32 Figure 5 1 Data Bus Register Configuration The master processor addresses the UPI 41A 41AH 42 42AH Microcomputer as a standard peripheral de vice Table 5 1 shows the conditions for data transfer Table 5 1 Data Transfer Controls CS Ao RD WR Condition 0 0 0 1 Read DBBOUT Oo 1 0 1 Read STATUS 0 0 1 0 Write DBBIN data F4 0 0 1 1 0 Write DBBIN command set Fy 1 1 Disable 56 Reading the Register The sequence for reading the DBBOUT register is shown in Figure 5 2 This operation causes the 8 bit contents of the DBBOUT register to be placed on the system Data Bus The OBF flag is cleared automatical ly Reading STATUS The sequence for reading the UPI Microcomputer s 8 STAT
13. that is they alter PC bits 0 7 only If a conditional JUMP or indirect JUMP begins in lo cation 255 of a page it must reference a destination on the following page Program memory can be used to store constants as well as program instructions The UPI 41AH 42AH in struction set contains an instruction MOVP3 de signed specifically for efficient transfer of look up table information from page 3 of memory DATA MEMORY The UPI 41A has 64 8 bit words of Random Access Memory the UPI 41AH has 128 8 bit words of Ran dom Access Memory the UPI 42 has 128 8 bit words of RAM and the UPI 42AH has 256 8 bit words of RAM This memory contains two working register banks an 8 level program counter stack and a scratch pad memory as shown in Figure 2 6 The amount of scratch pad memory available is variable depending on the number of addresses nested in the stack and the number of working registers being used Addressing Data Memory The first eight locations in RAM are designated as working registers Ro These locations or registers can be addressed directly by specifying a register num ber in the instruction Since these locations are easily addressed they are generally used to store frequently 11 UPI 41A 41AH 42 42AH USER S MANUAL accessed intermediate results Other locations in data memory are addressed indirectly by using Ro or to specify the desired address 8042 8742 USER 224 8 874
14. 1 lines The lower 4 bits interface directly to the 8243 I O expander device and contain address and data information during PORT 4 7 access The upper 4 bits can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure Po4 as Output Buffer Full interrupt Pos as Input Buffer Full IBF interrupt Pog as DMA Request DRQ and P27 as DMA ACKnowledge 10 WRITE 1 0 write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER READ 1 read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register CHIP SELECT Chip select input used to select one UPI 41A 41AH 42 42AH microcomputer out of several connected to a common data bus COMMAND DATA SELECT Address input used by the master processor to indicate whether byte transfer is data 0 or command Ao 1 TEST 0 TEST 1 39 TEST INPUTS Input pins can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 T4 also functions as the event timer input under software control TESTO To is used during PROM programming and verification in the UPI 41 41 42 42 1 XTAL 2 INPUTS Inputs for a crystal LC or an external timing signal to determine the internal oscillator frequency SYNC 11 O
15. Complement A 1 1 REGISTERS DAA Decimal Adjust A 1 1 INC Rr Increment register 1 1 SWAP A Swap nibbles of A 1 1 INC eRr Increment data memory 1 1 RLA Rotate A left 1 1 DEC Rr Decrement register 1 1 RLCA Rotate A left through carry 1 1 SUBROUTINE RRA Rotate A right 1 1 CALL addr Jump to subroutine 2 2 RRCA Rotate A right RET Return 1 2 through carry 1 1 RETR Return and restore status 1 2 INPUT OUTPUT FLAGS IN A Pp Input port to A 1 2 CLR C Clear Carry 1 1 OUTL Pp A Output A to port 1 2 CPLC Complement Carry 1 1 ANL Pp data And immediate to port 2 2 CLR FO Clear Flag 0 1 1 ORL data Or immediate to port 2 2 CPL FO Complement Flag 0 1 1 IN A DBB Input DDB to A clear IBF 1 1 CLR F1 Clear F4 Flag 1 1 OUT DBB A Output Ato DBB Set OBF 1 1 CPL F1 Complement F Flag 1 1 MOV STS A A4 A7 to bits 4 7 of status 1 1 BRANCH MOVD A Pp Input Expander port to A 1 2 JMP addr Jump unconditional 2 2 MOVD Output A to Expander port 1 2 JMPP Jump indirect 1 2 ANLD Pp A And A to Expander port 1 2 DJNZ Rr Decrement register ORLD Or A to Expander port 1 2 addr and jump on non zero 2 2 DATA MOVES JC addr Jump on Carry 1 2 2 MOV A Rr Move register to A 1 1 JNC addr Jump on Carry 0 2 2 MOV A Rr Move data memory to A 1 1 JZ addr Jump on A zero 2 2 MOV A data Move immediate to A 2 2 JNZ addr Jump on A not zero 2 2 MOV Rr A Move A to register 1 1 JTO addr Jump 1 2 2 MOV Rr A Move A to data memory 1 1 JNTO addr Jump on
16. EXCHANGE BITS 0 3 OF ACC AND LOCATION 51 MOV RO A MOVE CONTENTS OF ACC TO LOCATION 51 Exchange Accumulator Register Contents Opcode 0010 1 ro r4 ro The contents of the accumulator and the contents of working register r are exchanged A lt gt Rr 0 7 Example Move PSW contents to Reg 7 without losing accumulator contents XCHAR7 XCH A R7 XCHANGE CONTENTS OF REG 7 AND ACC MOV A PSW MOVE PSW CONTENTS TO ACC XCH A R7 XCHANGE CONTENTS OF REG 7 AND ACC AGAIN A GRr Exchange Accumulator and Data Memory Contents Opcode 0010 000r The contents of the accumulator and the contents of the data memory location addressed by bits 0 7 of register r are exchanged Register r contents are unaffected lt gt Rn r 0 1 Example Decrement contents of location 52 DEC 52 MOV RO 52 MOVE 52 DEC TO ADDRESS REGO A RO XCHANGE CONTENTS OF ACC AND LOCATION 52 DECA DECREMENT ACC CONTENTS XCH A RO XCHANGE CONTENTS OF ACC AND LOCATION 52 AGAIN 51 LI UPI 41A 41AH 42 42AH USER S MANUAL intel XCHD A Rr Exchange Accumulator and Data Memory 4 bit Data Opcode 0011 00 This instruction exchanges bits 0 3 of accumulator with bits 0 3 of the data memory location addressed by bits 0 7 of register r Bits 4 7 of the accumulator bits 4 7 of the data memory location and the contents of r
17. Engineers ideal component for low speed peripheral control appli Training Courses cations intel UPI 41A 41AH 42 42AH USER S MANUAL CHAPTER 2 FUNCTIONAL DESCRIPTION The UPI microcomputer is an intelligent peripheral controller designed to operate in iAPX 86 88 MCS 85 MCS 80 MCS 51 and MCS 48 systems The UPI s ar chitecture illustrated in Figure 2 1 is based on a low cost single chip microcomputer with program memo ry data memory CPU I O event timer and clock os cillator in a single 40 pin package Special interface reg isters are included which enable the UPI to function as a peripheral to an 8 bit master processor This chapter provides a basic description of the UPI microcomputer and its system interface registers Un less otherwise noted the descriptions in this section ap ply to the 8741AH 8742AH with OTP EPROM mem ory the 8741A 8742 with UV erasable program mem ory and the 8041AH 8042AH These devices are so similar that they can be considered identical under most circumstances All functions described in this chapter apply to the UPI 41A 41AH 42 42AH PIN DESCRIPTION UPI 41A 41AH 42 42AH are packaged in 40 pin Dual In Line DIP packages The pin configuration for both devices is shown in Figure 2 2 Figure 2 3 illus trates the UPI Logic Symbol 1024 X 8 2048 PROGRAM MEMORY ROM EPROM 8 BIT CPU 8 BIT 8 BIT DATA BUS DATA BUS INPUT REGISTER OUTPUT REGISTE
18. IN A DBB instruction causes the contents to be trans ferred to the UPI accumulator and the IBF flag is cleared The OUT DBBAA instruction causes the contents of the accumulator to be transferred to the DBBOUT register The OBF flag is set The UPI s data bus buffer interface is applicable to a variety of microprocessors including the 8086 8088 8085AH 8080 and 8048 description of the interface to each of these proces sors follows cs B CREE e ce Lu C 231318 36 Figure 5 5 Writing Commands to DBBIN DESIGN EXAMPLES 8085AH Interface Figure 5 6 illustrates an 8085AH system using a UPI 41A 41AH 42 42AH The 8085AH system uses a multiplexed address and data bus During I O the 8 upper address lines 5 contain the same I O address as the lower 8 address data lines therefore I O address decoding is done using only the upper 8 lines to eliminate latching of the address An 8205 decoder provides address decoding for both the UPI and the 8237 Data is transferred using the two DMA handshaking lines of PORT 2 The 8237 per forms the actual bus transfer operation Using the UPI 41A 41AH 42 42AH s OBF master interrupt the UPI notifies the 8085AH upon transfer completion us ing the RST 5 5 interrupt input The IBF master inter rupt is not used in this example 8088 Interface Figure 5 7 illustrates a UPI 41A 41AH 42 42AH in terface to an 8088 minimum mode
19. LINE ARITHMETIC PROCESSING 41 41 42 42 UPI 41A 41AH SERIAL 42 42AH COMMUNICATION 231318 5 Figure 1 3 Interfaces and Protocols for Multiprocessor Systems intel Features for Peripheral Control The UPI 8 bit interval timer event counter can be used to generate complex timing sequences for control appli cations or it can count external events such as switch closures and position encoder pulses Software timing loops can be simplified or eliminated by the interval timer If enabled an interrupt to the CPU will occur when the timer overflows The UPI I O complement contains two TTL compati ble 8 bit bidirectional I O ports and two general pur pose test inputs Each of the 16 port lines can individu ally function as either input or output under software control Four of the port lines can also function as an interface for the 8243 I O expander which provides four additional 4 bit ports that are directly addressable by UPI software The 8243 expander allows low cost I O expansion for large control applications while maintaining easy and efficient software port addressing 16 LINES UPI 41A 41AH 42 42AH 121 0 LINES 231318 4 Figure 1 4 8243 I O Expander Interface On Chip Memory The 64 128 256 bytes data memory include dual working register banks and an 8 level program counter stack Switching between the register banks allows fast response to interrupts The
20. Timer To Port Fetch ncrement E Increment Read Port Fetch Increment Output 4 ANL Pp DATA Instruction Program Timer Immediate Program Counter Data Counter Fetch ncrement m Increment Read Port Fetch 2 Increment Output ORL Instruction Program Timer Immediate Program To Port Counter Data Counter Fetch ncrement Output Increment Read Instruction Program Counter Opcode Address Timer P2 Lower MOVD Pp A Fe ch ncrement Output Increment Output Data Instruction Program Counter Opcode Address Timer To P2 Lower DPp A Fetch ncrement Output Increment Output n Instruction Program Opcode Address Timer Data Fetch ncrement Output Increment Output Instruction Program Counter Opcode Address Timer Data Fetch ncrement Sample Increment Fetch Update J Conditional Instruction Program Counter Condition Timer Immediate Data Program Counter MOV STS A Fe ch ncrement _ Increment Update Instruction Program Counter Timer Status Register IN A Fe ch ncrement Increment x Instruction Program Counter Timer Fetch ncrement Increment Output DUTDBB A Instruction Program Counter Timer To Port STRT T Fetch ncrement _ NJ Start STRT CNT Instruction Program Counter Counter STOP TCNT Fe ch ncrement _ _ Stop Instruction Program Counter Counter ENI Fetch ncrement Enable Instruction Program Counter Interrupt pd Fetch ncrement Disable DISI S Instruction P
21. be programmed to recognize special com binations of characters such as commands then transfer only the decoded information to the master processor Matrix Printer Interface The matrix printer interface illustrated in Figure 6 2 is a typical application for the UPI The actual printer mechanism could be any of the numerous dot matrix types and similar configurations can be shown for drum spherical head daisy wheel or chain type print ers The bus structure shown represents a generalized 8 bit system bus configuration The UPI s three state inter UPI 41A 41AH 42 42AH USER S MANUAL face port and asynchronous data buffer registers allow it to connect directly to this type of system for efficient two way data transfer The UPI s two on board I O ports provide up to 16 input and output signals to control the printer mecha nism The timer event counter is used for generating a timing sequence to control print head position line feed carriage return and other sequences The on board program memory provides character generation for 5 x 7 7 x 9 or other dot matrix formats As an added feature a portion of the data memory can be used as a FIFO buffer so that the master processor can send a block of data at a high rate The UPI can then output characters from the buffer at a rate the printer can ac cept while the master processor returns to other tasks DRIVERS DATA BUS INTERFACE TO 8 BIT MASTER PROCESSOR CONTR
22. operation 1 should be written to P25 and before the EN FLAGS instruction A 0 written to P24 or P25 disables the pin intel A UPI 41A 41AH 42 42AH USER S MANUAL ENI Enable IBF Interrupt Opcode 0000 0101 The Input Buffer Full interrupt is enabled A low signal on WR and CS initiates the interrupt sequence TCNTI Enable Timer Counter Interrupt Opcode 0010 0101 The timer counter interrupt is enabled An overflow of this register initiates the interrupt sequence INA DBB Input Data Bus Buffer Contents to Accumulator Opcode 0010 0010 Data in the DBBIN register is transferred to the accumulator and the Input Buffer Full IBF flag is set to zero A DBB IBF lt 0 Example INDBB IN A DBB INPUT DBBIN CONTENTS TO ACCUMULATOR IN A Pp Input Port 1 2 Data to Accumulator Opcode 0000 10 py This is a 2 cycle instruction Data present on is transferred read to accumulator A Pp p 1 2 see ANL instruction Example INP 12 IN A P1 NPUT PORT 1 CONTENTS ACC MOV R6 A MOVE ACC CONTENTS TO REG 6 IN A P2 NPUT PORT 2 CONTENTS ACC MOV R7 A MOVE ACC CONTENTS TO REG 7 INC Increment Accumulator Opcode 0001 0111 The contents of the accumulator are incremented by 1 Example Increment contents of location 10 in data memory
23. range depending on which UPI is used Refer to Table 1 2 The signal must be connected to pins XTAL 1 and XTAL 2 by buffers with a suitable pull up resistor to guarantee that a logic 1 is above 3 8 volts The recommended connection is shown in Figure 2 12 fc XTAL 1 UP1 41A 41AH 42 42AH STANDARD TTL OR OPEN COLLECTOR 231318 16 Figure 2 12 Recommended Connection For External Clock Signal 16 intel INTERVAL TIMER EVENT COUNTER The UPI 41A 41AH 42 42AH has a resident 8 bit timer counter which has several software selectable modes of operation As an interval timer it can gener ate accurate delays from 80 microseconds to 20 48 mil liseconds without placing undue burden on the proces sor In the counter mode external events such as switch closures or tachometer pulses can be counted and used to direct program flow Timer Configuration Figure 2 13 illustrates the basic timer counter configu ration An 8 bit register is used to count pulses from either the internal clock and prescaler or from an exter nal source The counter is presettable and readable with two MOV instructions which transfer the contents of the accumulator to the counter and vice versa i e MOV T A and MOV A T The counter is stopped by a RESET or STOP TCNT instruction and remains stopped until restarted either as a timer START T in struction or as a counter START CNT instruction Once started the counter will increment
24. set the 1 flag in the status register RD I O READ signal used to transfer data from the DBBOUT register or status register to the system data bus e CS CHIP SELECT signal used to enable one 8041AH out of several connected to a common bus Ao Address input used to select either the 8 bit status register or DBBOUT register during an 1 READ Also the signal is used to set the flag in the status register during an I O WRITE The WR and RD signals are active low and are stan dard MCS 80 peripheral control signals used to syn chronize data transfer between the system bus and pe ripheral devices The CS and signals are decoded from the address bus of the master system In a system with few I O devices a linear addressing configuration can be used where Ao and A lines are connected directly to Ag and CS inputs see Figure 2 17 Data Read Table 2 4 illustrates the relative timing of a DBBOUT Read When CS Ao and RD are low the contents of the DBBOUT register is placed on the three state Data lines 7 and the OBF flag is cleared The master processor uses CS Ag WR and RD to control data transfer between the DBBOUT register and the master system The following operations are under master processor control 21 UPI 41A 41AH 42 42AH USER S MANUAL 8 BIT SYSTEM BUS cs RD Ao UPI 41A 41AH 42 42AH PERIPHERAL INTERFACE PORT 2 TEST1 ADDRESS BUS DATA BUS V 0 WR RESE
25. stack is used to store return addresses and processor status upon entering a subrou tine UPI 41A 41AH 42 42AH USER S MANUAL The UPI program memory is available in three types to allow flexibility in moving from design to prototype to production with the same PC layout The 8741 8742 device with EPROM memory is very economical for initial system design and development Its program memory can be electrically programmed using the Intel Universal PROM Programmer When changes are needed the entire program can be erased using UV lamp and reprogrammed in about 20 minutes This means the 8741 8742 can be used as a single chip breadboard for very complex interface and control problems After the 8741 8742 is programmed it can be tested in the actual production level PC board and the actual functional environment Changes required during system debugging can be made in the 8741 8742 program much more easily than they could be made in a random logic design The system configuration and PC layout can remain fixed during the development process and the turn around time be tween changes can be reduced to a minimum At any point during the development cycle the 8741 8742 EPROM part can be replaced with the low cost UPI 41AH 42AH respectively with factory mask programmed memory or OTP EPROM The transition from system development to mass production is made smoothly because the 8741 8742 8741AH and 8041AH 8742AH and 8042AH parts are c
26. system Two 8 bit latches are used to demultiplex the address and data bus The address bus is 20 lines wide For I O only the lower 16 address lines are used providing an address ing range of 64K UPI address selection is accom plished using an 8205 decoder The address line of the bus is connected to the corresponding UPI input for register selection Since the UPI is polled by the 8088 neither DMA nor master interrupt capabilities of the UPI are used in the figure 8086 Interface The UPI 41A 41AH 42 42AH can be used on an 8086 maximum mode system as shown in Figure 5 8 The address and data bus is demultiplexed using three 57 UPI 41A 41AH 42 42AH USER S MANUAL in 8085AH ADDRESS DATA UPI 41A 41AH 42 42AH 231318 37 Figure 5 6 8085AH UPI System ADDRESS BUS UPI 41A 41AH 42 42AH ADQ AD45 PORT 1 DATA BUS 231318 38 Figure 5 7 8088 UPI Minimum Mode System 58 UPI 41A 41AH 42 42AH USER S MANUAL 8086 READY RESET B 8288 ADo AD 16 8282 CONTROL 3 AODRESS 5 00 07 CS Ao WR UPI 41A 41AH 42 42AH PORT 2 PORT 1 TEST 1 231318 39 Figure 5 8 8086 UPI Maximum Mode Systems 8282 latches providing separate address and data buses The address bus is 20 lines wide and the data bus is 16 lines wide Multiplexed control lines are decoded by the 8288 The U
27. the UPI 42 The UPI C42 doubles the user programmable memory size adds Auto A20 Gate support includes Standby and Suspend power down modes and is available in a space saving 44 lead QFP pkg Device Package ROM OTP Comments 80042 5 4K ROM Device 82C42PC N P S Phoenix MultiKey 42 firmware PS 2 style mouse support 82C42PD N P S Phoenix MultiKey 42L firmware KBC and SCC for portable apps 82C42PE N P S Phoenix MultiKey 42G firmware Energy Efficient KBC solution 87C42 N P S 4K One Time Programmable Version UPI L42 The low voltage 3 3V version of the UPI C42 Device Package ROM OTP Comments 80L42 5 4K ROM Device 82L42PC N P S Phoenix MultiKey 42 firmware PS 2 style mouse support 82LA2PD N P S Phoenix MultiKey 42L firmware KBC and SCC for portable apps 87L42 N P S 4K One Time Programmable Version NOTES N 44 lead PLCC P 40 lead PDIP S 44 lead QFP D 40 lead CERDIP KBC Key Board Control SCC Scan Code Control Standby feature not supported on current B 1 stepping DEVELOPMENT SUPPORT The UPI microcomputer is fully supported by Intel 8048 UPI 41A 41AH 42 42AH Assembler with development tools like the UPP PROM program Universal PROM Programmer UPP Series mer already mentioned The combination of device fea tures and Intel development support make the UPI an UPI DEVELOPMENT SUPPORT Application
28. the main system processor Higher overall system throughput is achieved and soft ware complexity is greatly reduced The intelligent peripheral chips simplify master processor control tasks by performing many functions externally in peripheral hardware rather than internally in main processor soft ware Intelligent peripherals also provide system flexibility They contain on chip mode registers which are pro grammed by the master processor during system initial ization These control registers allow the peripheral to be configured into many different operation modes The user defined program for the peripheral is stored in main system memory and is transferred to the peripher al s registers whenever a mode change is required Of course this type of flexibility requires software over head in the master system which tends to limit the ben efit derived from the peripheral chip In the past intelligent peripherals were designed to handle very specialized tasks Separate chips were de signed for communication disciplines parallel I O keyboard encoding interval timing CRT control etc Yet in spite of the large number of devices available and the increased flexibility built into these chips there is still a large number of microcomputer peripheral control tasks which are not satisfied With the introduction of the Universal Peripheral In terface UPI microcomputer Intel has taken the intel ligent peripheral concept a step f
29. you are coding in binary rather than assembly language the mapping is as follows Bits pi Port ANDP2 ANL P2 OFOH AND PORT 2 CONTENTS WITH MASK F0 HEX CLEAR 20 23 ANLD Pp A Logical AND Port 4 7 With Accumulator Mask Opcode Note Example 32 100 1 1 1 p1 po This is a 2 cycle instruction Data on port p on the 8243 expander is logically ANDed with the digit mask contained in accumulator bits 0 3 Pp lt Pp AND A0 3 p 4 7 The mapping of Port p to opcode bits po is as follows P1 PO Port 0 0 4 0 1 5 1 0 6 1 1 7 ANDP4 ANLD P4 A PORT 4 CONTENTS WITH ACC BITS 0 3 intel CALL address Subroutine Call UPI 41A 41AH 42 42AH USER S MANUAL Opcode 1 0100 a7 ag 8584 81 This is a 2 cycle instruction The program counter and PSW bits 4 7 are saved in the stack The stack pointer PSW bits 0 2 is updated Program control is then passed to the location specified by address Execution continues at the instruction following the CALL upon return from the subroutine SP PC PSW4_7 SP lt SP 1 PCg_9 lt addrg_g PCo_7 lt addro_7 Example Add three groups of two numbers Put subtotals in locations 50 51 and total in location 52 MOV RO 50 MOVE 50 DEC TO ADDRESS REG 0 BEGADD M
30. 2 8041AH 8741AH 8741 WORKING REGISTERS 8x8 DIRECTLY ADDRESSABLE WHEN BANK 1 IS SELECTED ADDRESSED INDIRECTLY 8 LEVEL STACK THROUGH o R1 Ro OR Ry R USER RAM 16X8 BANK WORKING REGISTERS DIRECTLY ADDRESSABLE WHEN BANK iS SELECTED 231318 11 Figure 2 6 Data Memory Map Working Registers Dual banks of eight working registers are included in the UPI 41A 41AH 42 42AH data memory Loca tions 0 7 make up register bank 0 and locations 24 13 form register bank 1 A RESET signal automatically selects register bank 0 When bank 0 is selected refer ences to Ro R5 in UPI 41A 41AH 42 42AH instruc tions operate on locations 0 7 in data memory A lect register bank instruction is used to selected be tween the banks during program execution If the in struction SEL RBI Select Register Bank 1 is execut ed then program references to Ro R will operate locations 24 31 As stated previously registers O and 1 in the active register bank are used as indirect address registers for all locations in data memory Register bank 1 is normally reserved for handling inter rupt service routines thereby preserving the contents of the main program registers The SEL RB1 instruction can be issued at the beginning of an interrupt service routine Then upon return to the main program an RETR return amp restore status instruction will auto matically restore the previ
31. 24 31 This is the recommended setting for interrupt service routines since locations 0 7 are left intact The setting of PSW bit 4 in effect at the time of an interrupt is restored by the RETR instruction when the interrupt service routine is completed Assume an IBF interrupt has occurred control has passed to program memory location 3 and PSW bit 4 was zero before the interrupt LOC3 JMP INIT JUMP TO ROUTINE INIT INIT MOV R7 A MOV ACC CONTENTS TO LOCATION 7 SEL RB1 SELECT REG BANK 1 MOV R7 OFAH MOVE FA HEX TO LOCATION 31 SEL RBO SELECT REG BANK 0 MOV A R7 RESTORE ACC FROM LOCATION 7 RETR RETURN RESTORE PC AND PSW 49 LI UPI 41A 41AH 42 42AH USER S MANUAL intel STOP Stop Timer Event Counter Opcode Example 0110 0101 This instruction is used to stop both time accumulation and event counting Disable interrupt but jump to interrupt routine after eight overflows and stop timer Count overflows in register 7 START DIS TCNTI DISABLE TIMER INTERRUPT CLR CLEAR ACC TO ZERO MOV MOV ZERO TO TIMER MOV R7 A MOVE ZERO TO REG 7 STRT T TIMER MAIN JTF COUNT JUMP TO ROUTINE COUNT TF 1 AND CLEAR TIMER FLAG JMP MAIN CLOSE LOOP COUNT INC R7 INCREMENT REG 7 MOV 7 MOVE REG 7 CONTENTS TO ACC JB3 INT JUMP TO ROUTINE INT IF ACC BIT 3 IS SET REG 7 8 JMP MAIN OTHERWISE RETURN TO ROUTINE MAIN INT STOP TCNT TIMER
32. 4 bit ports PORTS 4 5 6 and 7 PORTS 1 and 2 PORTS 1 and 2 are each 8 bits wide and have the same I O characteristics Data written to these ports by an intel OUTL Pp A instruction is latched and remains un changed until it is rewritten Input data is sampled at the time the IN A Pp instruction is executed There fore input data must be present at the PORT until read by an INput instruction PORT 1 and 2 inputs are fully TTL compatible and outputs will drive one standard TTL load Circuit Configuration The PORT 1 and 2 lines have a special output structure shown in Figure 2 18 that allows each line to serve as an input an output or both even though outputs are statically latched Each line has a permanent high impedance pull up 50 which is sufficient to provide source current for a TTL high level yet can be pulled low by a standard TTL gate drive Whenever a 1 is written to a line a low impedance pull up 2500 is switched in momen tarily 500 ns to provide a fast transition from O to 1 When a 0 is written to the line a low impedance pull down 3000 is active to provide TTL current sinking capability To use a particular PORT pin as an input a logic 1 must first be written to that pin NOTE A RESET initializes all PORT pins to the high im pedance logic 1 state UPI 41A 41AH 42 42AH USER S MANUAL An external TTL device connected to the pin has suffi cient curren
33. AH 42 42AH The lower half of PORT 2 provides an interface to the 8243 as illustrated in Figure 2 20 The PROG pin is used as a strobe to clock address and data information via the PORT 2 interface The extra 16 I O lines are referred to in UPI software as PORTS 4 5 6 and 7 Each PORT can be directly addressed and can be ANDed and ORed with an immediate data mask Data can be moved directly to the accumulator from the ex pander PORTS or vice versa The 8243 I O ports PORTS 4 5 6 and 7 provide more drive capability than the UPI 41A 41AH 42 42AH bidirectional ports The 8243 output is capable of driving about 5 standard TTL loads intel Multiple 8243 s can be connected to the PORT 2 inter face In normal operation only one of the 8243 s would be active at the time an Input or Output command is executed The upper half of PORT 2 is used to provide chip select signals to the 8043 s Figure 2 21 shows how four 8243 s could be connected Software is needed to select and set the proper PORT 2 pin before an INPUT or OUTPUT command to PORTS 4 7 is executed In general the software overhead required is very minor compared to the added flexibility of having a large number of I O pins available INPUT PORT 1 2 UPI 41A 41AH 42 42AH INCORRECT UNLESS ALL LINES ON THE PORT ARE INPUTS 1K INPUT PORT 1 2 UPI 41A 41AH 42 42AH RECOMMENDED WHEN INPUTS AND OUTPUTS ARE MIXED ON A PORT 231318 24
34. CHAPTER 5 SYSTEM OPERATION 56 Bus Interface 56 Design Examples 57 General Handshaking Protocol 60 CHAPTER 6 APPLICATIONS 62 ADSUAGCIS dose RU ARRA 62 intel UPI 41A 41AH 42 42AH USER S MANUAL CHAPTER 1 INTRODUCTION Accompanying the introduction of microprocessors such as the 8088 8086 80186 and 80286 there has been a rapid proliferation of intelligent peripheral devices These special purpose peripherals extend CPU per formance and flexibility in a number of important ways Table 1 1 Intelligent Peripheral Devices 8255 GPIO Programmable Peripheral Interface 8251A USART Programmable Communication Interface 8253 TIMER Programmable Interval Timer 8257 DMA Programmable DMA Controller 8259 Programmable Interrupt Controller 82077AA Programmable Floppy Disk Controller 8273 SDLC Programmable Synchronous Data Link Controller 8274 Programmable Multiprotocol Serial Communications Controller 8275 8276 CRT Programmable CRT Controllers 8279 PKD Programmable Keyboard Display Controller 8291A 8292 8293 Programmable GPIB System Talker Listener Controller Intelligent devices like the 82077AA floppy disk con troller and 8273 synchronous data link controller see Table 1 1 can preprocess serial data and perform con trol tasks which off load
35. ERFLOW TO OVFLOW ROUTINE JFC 1 address Jump If Flag 0 is Set Opcode 1011 0110 a7 ag as ay This is a 2 cycle instruction Control passes to the specified address if flag 0 is set to one PCo_7 lt addr if Fo 1 Example JFOIS1 JFO TOTAL TO TOTAL ROUTINE IF Fp 1 38 intel UPI 41A 41AH 42 42AH USER S MANUAL JF1 address Jump If C D Flag F1 Is Set Opcode Example 0111 0110 a7 ag ay This is a 2 cycle instruction Control passes to the specified address if the flag F1 is set to one PCo_7 lt addr ifF 1 JF 1181 JF1 FILBUF JUMP TO FILBUF ROUTINEIFF 1 JMP address Direct Jump Within 1K Block Opcode Example 0 0 100 ay This is 2 cycle instruction Bits 0 10 of program counter are replaced with the directly specified address PCg 10 lt addr 8 10 PCo_7 addr 0 7 JMP SUBTOT JUMP TO SUBROUTINE SUBTOT JMP 5 6 JUMP TO INSTRUCTION SIX LOCATIONS BEFORE CURRENT LOCATION JMP 2FH JUMP TO ADDRESS 2F HEX JMPP 9A Indirect Jump Within Page Opcode Example 1011 0011 This is a 2 cycle instruction The contents of program memory location pointed to by accumulator are substituted for the page
36. G 6 MOV Rr A Move Accumulator Contents to Data Memory Opcode Example 1010 000r The contents of the accumulator are moved to the data memory location whose address is specified by bits 0 7 of register r Register r contents are unaffected Rr lt A r 0 1 Assume contains 11000111 MDMA MOV GR A MOVE CONTENTS OF ACC TO LOCATION 7 REG MOV Rr data Move Immediate Data to Data Memory Opcode Example 1011 000r dzdeds d4 da do dy do This is a 2 cycle instruction The 8 bit value specified by data is moved to the standard data memory location addressed by register r bit 0 7 Move the hexadecimal value AC3F to locations 62 63 MIDM MOV RO 62 MOVE 62 DEC TO ADDR REGO MOV MOVE AC HEX TO LOCATION 62 INC RO NCREMENT REG 63 MOV RO 3FH MOVE HEX TO LOCATION 63 43 LI UPI 41A 41AH 42 42AH USER S MANUAL intel MOV STS A Move Accumulator Contents to STS Register Opcode 1001 00 The contents of the accumulator moved into status register Only bits 4 7 are affected STS4_7 lt 4 7 Example Set ST4 ST to 1 MSTS MOV A 0FOH ACC MOV STS A MOVE TO STS MOVT A Move Accumulator Contents to Timer Counter Opcode 0110 0010 The contents of the accumulator are moved to the timer event counter regis
37. INCA MOV RO 10 MOV 40 DEC TO ADDRESS REGO MOV A GRO MOVE CONTENTS OF LOCATION ACC INCA NCREMENT ACC MOV RO A MOVE ACC CONTENTS LOCATION 10 37 LI UPI 41A 41AH 42 42AH USER S MANUAL intel Increment Register Opcode 0001 1 ro ry ro The contents of working register r are incremented by one lt Rr 1 0 7 Example INCRO INC RO NCREMENT ADDRESS REG 0 INC Rr Increment Data Memory Location Opcode 0001 000r The contents of the resident data memory location addressed by register r bits 0 7 are incremented by one Rr 1 0 1 Example INCDM R1 OFFH MOVE ONES TO REG 1 INC GRI INCREMENT LOCATION 63 JBb address Jump If Accumulator Bit is Set Opcode bo by bo 1 0010 85 84 82 This is a 2 cycle instruction Control passes to the specified address if accumulator bit b is set to one PCo 7 addr ifb 1 lt PC 2 ifb 0 Example JB4IS1 JB4 NEXT TO NEXT ROUTINE ACC BIT 4 1 JC address Jump If Carry Is Set Opcode 1111 0110 a7 ag a5 ay This is a 2 cycle instruction Control passes to the specified address if the carry bit is set to one PCo_7 addr ifC 1 lt PC 2 ifc 0 Example JC1 JC OV
38. JMP 7H JUMP TO LOCATION 7 TIMER INTERRUPT ROUTINE STRT CNT Start Event Counter Opcode Example 0100 0101 The TEST 1 pin is enabled as event counter input and the counter is started The event counter register is incremented with each high to low transition on the T pin Initialize and start event counter Assume overflow is desired with first T input STARTC EN TCNTI ENABLE COUNTER INTERRUPT MOV A ZOFFH MOVE FF HEX ONES TO ACC MOV MOVE ONES TO COUNTER STRT CNT NPUT AND START STRTT Start Timer Opcode Example 50 0101 0101 Timer accumulation is initiated in the timer register The register is incremented every 32 instruction cycles The prescaler which counts the 32 cycles is cleared but the timer register is not Initialize and start timer STARTT EN TCNTI NABLE TIMER INTERRUPT CLRA CLEAR ACC TO ZEROS MOV T A MOVE ZEROS TO TIMER STRT T TIMER intel UPI 41A 41AH 42 42AH USER S MANUAL SWAPA Swap Nibbles Within Accumulator Opcode 010010111 Bits 0 3 of the accumulator swapped with bits 4 7 of the accumulator A4 7 lt gt Ao 3 Example Pack bits 0 3 of locations 50 51 into location 50 PCKDIG MOV RO 50 MOVE 50 DEC TO REG 0 MOV R1 51 MOVE 51 DEC TO REG 1 XCHD A RO EXCHANGE BIT 0 3 OF ACC AND LOCATION 50 SWAP A SWAP BITS 0 3 AND 4 7 OF ACC XCHD
39. Microprocessor Peripherals UPI 41A 41AH 42 42AH User s Manual October 1993 Order Number 231318 006 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoev er including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata Other brands and names are the property of their respective owners TSince publication of documents referenced in this document registration of the Pentium OverDrive and iCOMP trademarks has been issued to Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 COPYRIGHT INTEL CORPORATION 1996 Microprocessor Peripherals UPI 41A 41AH 42 42AH User s Manual CONTENTS PAGE CHAPTER 1 INTRODUCTION 1 Interface Registers for Multiprocessor Configurations 3 Powerful 8 Bit Processor 3 Special Instructi
40. ND PROGRAMMING POWER DOWN MODES SINGLE STEP The UPI family has a single step mode which allows the user to manually step through his program one in struction at a time While stopped the address of the next instruction to be fetched is available on PORT 1 and the lower 2 bits of PORT 2 The single step feature simplifies program debugging by allowing the user to easily follow program execution Figure 4 1 illustrates a recommended circuit for single step operation while Figure 4 2 shows the timing rela tionship between the SYNC output and the SS input During single step operation PORT 1 and part of PORT 2 are used to output address information In order to retain the normal I O functions of PORTS 1 and 2 a separate latch can be used as shown in Figure 4 3 PRESET MOMENTARY PUSH TO STEP Ye 7474 PRESET TOSS INPUT ON UPI 41A 41AH 42 42AH FROM UPI 41A 41AH 42 42AH 9 7474 SYNC OUTPUT 231318 28 Figure 4 1 Single Step Circuit SYNC USED BY BUTTON 55 55 P10 17 PORT DATA X PCO 7 X P20 P21 X 8 9 X ACTIVE CYCLE STOP CYCLE activecycte 231318 29 Figure 4 2 Single Step Timing 53 UPI 41A 41AH 42 42AH USER S MANUAL UPI 41A 41AH 42 42AH OC OPEN COLLECTOR TTL LS LOW POWER SCHOTTKLY TTL ADDRESS DISPLAY LED P17 INPUT DATA 231318 30 Figure 4 3 Latching Port Data Timing The sequence of single step operation is
41. OL BUS DOT MATRIX PRINTER PRINT POSITION UPI 41A 41AH 42 42AH SOLENOIDS SOLENOID DRIVERS TOP OF FORM 2 amp PORT 2 PORT 1 PORT 2 CONTROL 231318 44 Figure 6 2 Matrix Printer Controller 63 UPI 41A 41AH 42 42AH USER S MANUAL The 8295 Printer Controller is an example of an UPI preprogrammed as a dot matrix printer interface Tape Cassette Controller Figure 6 3 illustrates a digital cassette interface which can be implemented with the UPI Two sections of the tape transport are controlled by the UPI digital data command logic and motor servo control The motor servo requires a speed reference in the form of a monostable pulse whose width is proportional to the desired speed The UPI monitors a prerecorded clock from the tape and uses its on board interval timer to generate the required speed reference pulses at each clock transition Recorded data from the tape is supplied serially by the data command logic and is converted to 8 bit words by the UPI then transferred to the master processor At 10 ips tape speed the UPI can easily handle the 8000 bps data rate To record data the UPI uses the two input lines to data command logic which control the flux direction in the recording head The UPI also monitors 4 status lines from the tape transport includ ing end of tape cassette inserted busy and write per mit All control signals can be han
42. OV A R1 MOVE CONTENTS OF REG 1 ACC ADD A R2 ADD REG 2 TO ACC CALL SUBTOT CALL SUBROUTINE SUBTOT ADD A R3 ADD REG 3 TO ACC ADD A R4 ADD REG 4 TO ACC CALL SUBTOT CALL SUBROUTINE ADD A R5 ADD REG 5 TO ACC ADD A R6 ADD REG 6 TO ACC CALL SUBTOT CALL SUBROUTINE SUBTOT MOV R0 A MOVE CONTENTS OF ACC TO LOCATION ADDRESSED BY REG 0 INC RO NCREMENT REG 0 RET RETURN TO MAIN PROGRAM CLRA Clear Accumulator Opcode 001010111 The contents of the accumulator are cleared to zero A lt 00H CLRC Clear Carry Bit Opcode 1001 0111 During normal program execution the carry bit can be set to one by the ADD ADDC RLC CPLC RRC and DAA instructions This instruction resets the carry bit to zero lt 0 1 Clear Flag 1 Opcode 1010 0101 The flag is Fi lt 0 cleared to zero 33 LI UPI 41A 41AH 42 42AH USER S MANUAL intel CLRFO Clear 0 Opcode 1000 0101 Fo flag is cleared to zero Fo lt 0 CPLA Complement Accumulator Opcode 0011 0111 The contents of accumulator are complemented This is strictly a one s complement Each one is changed to zero and vice versa NOT Example Assume accumulator contains 01101010 CPLA CPL A CONTENTS ARE COMPLE MENTED TO 10010101 CPLC Complement Carry Bit Opcode 101001411
43. PI s CS input is provided by linear selec tion Note that UPI is both I O mapped and memo ry mapped as a result of the linear addressing tech nique An address decoder may be used to limit the UPI 41A 41AH 42 42AH to a specific I O mapped address Address line 1 is connected to the UPI s Ao input This insures that the registers of the UPI will have even I O addresses Data will be transferred on Do Dj lines only This allows the I O registers to be accessed using byte manipulation instructions 8080 Interface Figure 5 9 illustrates the interface to an 8080A system In this example a crystal and capacitor are used for UPI 41A 41AH 42 42AH timing reference and pow er on RESET If the 2 MHz 8080A 2 phase clock were used instead of the crystal the UPI 41A 41AH 42 42AH would run at only 16 full speed The Ag and CS inputs are direct connections to the 8080 address bus In larger systems however either of these inputs may be decoded from the 16 address lines The RD and WR inputs to the UPI can be either the IOR and IOW or the MEMR and MEMR signals de pending on the I O mapping technique to be used The UPI can be addressed as an I O device using IN put and OUTput instructions in 8080 software 8048 Interface Figure 5 10 shows the UPI interface to an 8048 master processor The 8048 RD and WR outputs are directly compatible with the UPI Figure 5 11 shows a distributed process ing system with up to seven UPT s c
44. Power Down sequence The sequence typically occurs as follows 1 Imminent power supply failure is detected by user defined circuitry The signal must occur early enough to guarantee the 1 41 42 can save all necessary data before falls outside normal operating tolerance 2 A Power Failure signal is used to interrupt the processor via a timer overflow interrupt for in stance and call a Power Failure service routine 3 The Power Failure routine saves all important data and machine status in the RAM array The routine may also initiate transfer of a backup supply to the Vpp pin and indicate to external circuitry that the Power Failure routine is complete 4 A RESET signal is applied by external hardware to guarantee data will not be altered as the power sup ply falls out of limits RESET must be low until Voc reaches ground potential Recovery from the Power Down mode can occur as any other power on sequence An external 1 ufd capac itor on the RESET input will provide the necessary initialization pulse POWER SUPPLY PROCESSOR INTERRUPTED 1 POWER SUPPLY FAIL SIGNAL POWER 1 1 I RESET 1 1 DATA SAVE ROUTINE EXECUTED NORMAL SEQUENCE FOLLOWS ACCESS TO DATA RAM INHIBITED 231318 31 Figure 4 4 Power Down Sequence 55 UPI 41A 41AH 42 42AH USER S MANUAL
45. R SYSTEM INTERFACE 64x8 128x8 8 BIT 256 x 8 TIMER COUNTER DATA MEMORY 8 BIT STATUS 18 REGISTER 1 0 LINES PERIPHERAL INTERFACE AND 1 0 EXPANSION 231318 6 Figure 2 1 UPI 41A 41AH 42 42AH Single Chip Microcomputer UPI 41A 41AH 42 42AH USER S MANUAL in TEST 0 vece XTAL1 TEST1 XTAL2 P27 DACK RESET P26 DRQ 55 P25 5 24 P17 RD P16 Ao P15 WR Pia EVG 42 42AH on 00 12 D P11 D2 P10 D3 VOD 04 PROG 05 23 06 P22 07 P21 vss P20 231318 7 PORT 1 XTAL 1 RESET SINGLE STEP 8 PORT 2 DATA UPI 41A 41AH 1 TEST BUS BUFFER INTERFACE WRITE CONTROL SYNC CONTROL INTERFACE DATA TEST MODE CHIP SELECT 231318 8 Figure 2 3 Logic Symbol intel UPI 41A 41AH 42 42AH USER S MANUAL The following section summarizes the functions of each UPI pin NOTE that several pins have two or more functions which are described in separate paragraphs Table 2 1 Pin Description Symbol Pin No Type Name and Function Do D7 BUS 12 19 DATA BUS Three state bidirectional DATA BUS BUFFER lines used to interface the UPI 41A 41AH 42 42AH microcomputer to an 8 bit master system data bus 17 27 34 PORT 1 8 bit PORT 1 quasi bidirectional I O lines 2 27 21 24 35 38 1 0 PORT 2 8 bit PORT 2 quasi bidirectional
46. RTS 1 and 2 are configured to allow input on a given pin by first writing a 1 to the pin Four additional 4 bit ports are available through the 8243 I O expander device The 8243 interfaces to the 28 intel UPI 41A 41AH 42 42AH peripheral interface via four PORT 2 lines which form an expander bus The 8243 ports have their own AND and OR instructions like the on board ports as well as move instructions to transfer data in or out The expander AND or OR in structions however combine the contents of the accu mulator with the selected port rather than with imme diate data as is done with the on board ports INSTRUCTION SET DESCRIPTION The following section provides a detailed description of each UPI instruction and illustrates how the instruc tions are used For further information about programming the UPI consult the 8048 8041AH Assembly Language Manual Table 3 1 Symbols and Abbreviations Used Symbol Definition A Accumulator C Carry DBBIN Data Bus Buffer Input DBBOUT Data Bus Buffer Output Fo F4 FLAG 0 FLAG 1 C D flag Interrupt P Mnemonic for operation PC Program Counter Pp Port designator p 1 2 or 4 7 PSW Status Word Rr Register designator r 0 7 SP Stack Pointer STS Status register Timer Flag T4 TEST 0 TEST 1 Immediate data prefix Indirect address prefix Double parentheses show the effect of that i
47. S signal is monitored via PORT 2 as an enable to the UPI to send serial data A PORT 2 line is also used as a software generated interrupt to the mas ter processor The interrupt functions as a service re quest when the UPI has a byte of data to transfer or when it is ready to receive Alternatively the EN FLAGS instruction could be used to create the OBF and IBF interrupts on and The RS232C interface is implemented using the TEST pin as a receive input and a PORT 2 pin as a transmit output External packages Ao A1 are used to provide RS232C drive requirements The serial receive software is interrupt driven and uses the on chip timer to per form time critical serial control After a start bit is de tected the interval timer can be preset to generate an interrupt at the proper time for sampling the serial bit stream This eliminates the need for software timing UPI 41A 41AH 42 42AH USER S MANUAL loops and allows the processor to proceed to other tasks i e parallel I O operations between serial bit sam ples Software flags are used so the main program can determine when the interrupt driven receive program has a character assembled for it This type of configuration allows system designers flex ibility in designing custom I O interfaces for specific serial and parallel I O applications For instance a sec ond or third serial channel could be substituted in place of the parallel I O if required The UPI s da
48. T XTAL 1 XTAL 2 TEST O 231318 22 Figure 2 17 Interface to 8080 System Bus Table 2 4 Data Transfer Controls CS RD WR Ao 0 0 1 0 Read DBBOUT register 0 0 1 1 Read STATUS register 0 1 0 0 Write DBBIN data register 0 1 0 1 Write DBBIN command register 1 x x x Disable DBB Status Read Table 2 4 shows the logic sequence required for a STATUS register read When CS and RD are low with Ao high the contents of the 8 bit status register appears on Data lines Data Write Table 2 4 shows the sequence for writing information to the DBBIN register When CS and WR are low the contents of the system data bus is latched into DBBIN Also the IBF flag is set and an interrupt is generated if enabled 22 Command Write During any write Table 2 4 the state of the Ao input is latched into the status register in the 1 command data flag location This additional bit is used to signal whether DBBIN contents are command Ao 1 or data Ag 0 information INPUT OUTPUT INTERFACE The UPI 41A 41AH 42 42AH has 16 lines for input and output functions These I O lines are grouped as two 8 bit TTL compatible ports PORTS 1 and 2 The port lines can individually function as either inputs or outputs under software control In addition the lower 4 lines of PORT 2 can be used to interface to an 8243 I O expander device to increase I O capacity to 28 or more lines The additional lines are grouped as
49. TCNTI EXECUTED TIMER INTERRUPT ENABLE DIS TCNTI EXECUTED RESET gt INTERRUPT IN PROGRESS TIMER INTERRUPT REQUEST RETR EXECUTED 5 RESET 231318 19 Figure 2 14 Interrupt Logic 18 intel Location 3 in program memory should contain an un conditional jump to the beginning of the IBF interrupt service routine elsewhere in program memory At the end of the service routine an RETR Return and Re store Status instruction is used to return control to the main program This instruction will restore the pro gram counter and PSW bits 4 7 providing automatic restoration of the previously active register bank as well RETR also re enables interrupts A timer overflow interrupt is enabled by the EN TCNTI instruction and disabled by the DIS TCNTI instruction If enabled this interrupt occurs when the timer counter register overflows A CALL to location 7 is forced and the interrupt routine proceeds as de scribed above The interrupt service latency is the sum of current in struction time interrupt recognition time and the in ternal call to the interrupt vector address The worst case latency time for servicing an interrupt is 7 clock cycles Best case latency is 4 clock cycles Interrupt Timing Interrupt inputs may be enabled or disabled under pro gram control using EN I DIS I EN TCNTI and DIS TCNTI instructions Also a RESET input will disable interrupts An interrupt request must be removed
50. The Program Status Word PSW is actually a collec tion of flip flops located throughout the machine which are read or written as a whole The PSW can be loaded to or from the accumulator by the MOV A PSW or MOV PSW A instructions The ability to write directly to the PSW allows easy restoration of machine status after a power down sequence The upper 4 bits of the PSW bits 4 5 6 and 7 are stored in the PC Stack with every subroutine CALL or interrupt vector Restoring the bits on a return is op tional The bits are restored if an RETR instruction is executed but not if an RET is executed PSW bit definitions are as follows Bits 0 2 Stack Pointer Bits So S1 82 Bit 3 Not Used Bit 4 Working Register Bank 0 Bank 0 1 Bank 1 Bit 5 Flag 0 bit Fo This is a general purpose flag which can be cleared or complemented and tested with conditional jump instructions It may be used during data transfer to an external processor Bit 6 Auxiliary Carry AC The flag status is determined by an ADD instruc tion and is used by the Decimal Adjustment instruc tion DAA Bit 7 Carry CY The flag indicates that a previous operation resulted in overflow of the accumulator CONDITIONAL BRANCH LOGIC Conditional Branch Logic in the UPI 41AH 42AH al lows the status of various processor flags inputs and other hardware functions to directly affect program ex ecution The status is sampled in state 3 of the first cycle
51. US bits is shown in Figure 5 3 This operation causes the 8 bit STATUS register contents to be placed on the system Data Bus as shown i CEP 231318 33 Figure 5 2 DBBOUT Read 231318 34 BUS CONTENTS DURING STATUS READ ST STe STs ST Fy Fo IBF D7 06 05 D4 D2 D Figure 5 3 Status Read UPI 41A 41AH 42 42AH USER S MANUAL 23131835 Figure 5 4 Writing Data to DBBIN Write Data to DBBIN The sequence for writing data to the DBBIN register is shown in Figure 5 4 This operation causes the system Data Bus contents to be transferred to the DBBIN reg ister and the IBF flag is set Also the flag is cleared 0 and an interrupt request is generated When the IBF interrupt is enabled a jump to location 3 will occur The interrupt request is cleared upon entering the IBF service routine or by a system RESET input Writing Commands to DBBIN The sequence for writing commands to the DBBIN reg ister is shown in Figure 5 5 This sequence is identical to a data write except that the Ag input is latched in the flag 1 The IBF flag is set and an interrupt request is generated when the master writes a command to DBB Operations of Data Bus Registers The UPI 41A 41AH 42 42AH Microcomputer con trols the transfer of DBB data to its accumulator by executing INput and OUTput instructions An
52. UTPUT ACC CONTENTS PORT2 MOV A R6 MOVE REG 6 CONTENTS TO ACC OUTL P1 A OUTPUT ACC CONTENTS TO PORT 1 RET Return Without PSW Restore Opcode 1000 0011 This is a 2 cycle instruction The stack pointer PSW bits 0 2 is decremented The program counter is then restored from the stack PSW bits 4 7 are not restored SP lt SP 1 PC lt SP RETR Return With PSW Restore Opcode 1001 00411 This is a 2 cycle instruction The stack pointer is decremented The program counter and bits 4 7 of the PSW are then restored from the stack Note that RETR should be used to return from an interrupt but should not be used within the interrupt service routine as it signals the end of an interrupt routine SP lt SP 1 PC 8 PSW4_7 lt SP RLA Rotate Left Without Carry Opcode 1110 04411 The contents of the accumulator are rotated left one bit Bit 7 is rotated into the bit O position Ana 1 lt An n 0 6 lt Example Assume accumulator contains 10110001 RLNC RL A NEW ACC CONTENTS ARE 01100011 47 LI UPI 41A 41AH 42 42AH USER S MANUAL intel RLCA Rotate Left Through Carry Opcode Example 11110111 The contents of accumulator are rotated left one bit Bit 7 replaces carry bit carry bit is rotated into the bit 0 position Ant 1 lt An n 0 6 lt
53. UTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation EA EXTERNAL ACCESS External access input which allows emulation testing and PROM ROM verification PROG 25 PROGRAM Multifunction pin used as the program pulse input during PROM programming During I O expander access the PROG pin acts as an address data strobe to the 8243 RESET Input used to reset status flip flops and to set the program counter to zero RESET is also used during PROM programming and verification SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction 40 POWER 5V main power supply pin 26 POWER 5V during normal operation 25V for UPI 41A 21V for UPI 42 programming operation 12V for programming UPI 41AH 42AH Low power standby pin in ROM version 20 GROUND Circuit ground potential UPI 41A 41AH 42 42AH USER S MANUAL The following sections provide a detailed functional de scription of the UPI microcomputer Figure 2 4 illus trates the functional blocks within the UPI device CPU SECTION The CPU section of the UPI 41A 41AH 42 42AH microcomputer performs basic data manipulations and controls data flow throughout the single chip computer via the internal 8 bit data bus The CPU section i
54. accumulator Flags There are four user accessible flags Carry Auxiliary Carry Fi The Carry flag indicates overflow of accumulator while the Auxiliary Carry flag indicates overflow be tween BCD digits and is used during decimal adjust intel operations Both Carry and Auxiliary Carry are part of the Program Status Word PSW and are stored in the stack during subroutine calls The Fo and F flags are general purpose flags which can be cleared or comple mented by UPI instructions Fo is accessible via the Program Status Word and is stored in the stack with the Carry flags reflects the condition of the Ag line and caution must be used when setting or clearing it Register Operations The working registers can be accessed via the accumu lator as explained above or they can be loaded with immediate data constants from program memory In addition they can be incremented or decremented di rectly or they can be used as loop counters as explained in the section on branch instructions Additional Data Memory locations can be accessed with indirect instructions and Ry Branch Instructions The UPI 41A 41AH 42 42AH Instruction Set cludes 17 jump instructions The unconditional allows jumps anywhere in the 1K words of program memory All other jump instructions are limited to the current page 256 words of program memory Conditional jump instructions can test the following in put
55. an be implemented with or without UPI pro gram interference by enabling or disabling an internal UPI interrupt Internally data transfer between the DBB and the UPI accumulator is under software con 20 trol and is completely asynchronous to the external processor timing This allows the UPI software to han dle peripheral control tasks independent of the main processor while still maintaining a data interface with the master system Configuration Figure 2 16 illustrates the internal configuration of the DBB registers Data is stored in two 8 bit buffer regis ters DBBIN and DBBOUT DBBIN and DBBOUT may be accessed by the external processor using the WR line and the RD line respectively The data bus is a bidirectional three state bus which can be connected directly to an 8 bit microprocessor system Four con trol lines WR RD CS are used by the external processor to transfer data to and from the DBBIN and DBBOUT registers An 8 bit register containing status flags is used to indi cate the status of the DBB registers The eight status flags are defined as follows OBF Output Buffer Full This flag is automatically set when the UPI Micro computer loads the DBBOUT register and is cleared when the master processor reads the data register IBF Input Buffer Full This flag is set when the master processor writes a character to the DBBIN register and is cleared when the UPI INputs the data register contents to its ac
56. and P25 P24 is the Output Buffer Full interrupt request line to the host system P25 is the Input Buffer empty interrupt request line These interrupt outputs reflect the internal status of the OBF flag and the IBF inverted flag Note these outputs may be inhibited by writing a 0 to these pins Reenabling interrupts is done by writing a 1 to these port pins Interrupts are typically enabled after power on since the I O ports are set in a 1 condition The EN FLAG s effect is only cancelled by a device RESET DMA handshaking controls are available from two pins on PORT 2 of the UPI 41A 41AH 42 42AH mi crocomputer These lines P26 and P 7 are enabled by the EN DMA instruction becomes DMA request and P5 becomes DMA acknowledge DACK The UPI program initiates a DMA request by writing a 1 to The DMA controller transfers the data into the DBBIN data register using DACK which acts as a chip select The EN DMA instruction can only be can celled by a chip RESET RESET The RESET input provides a means for internal initiali zation of the processor An automatic initialization pulse can be generated at power on by simply connect ing a 1 pfd capacitor between the RESET input and ground as shown in Figure 2 15 It has an internal pull up resistor to charge the capacitor and a Schmitt trigger circuit to generate a clean transition A 2 stage synchronizer has been added to support reliable op
57. arry is affected lt A data Example ADDID ADD A ADDER ADD VALUE OF SYMBOL ADDER TO ACC ADDC Add Carry and Register Contents to Accumulator Opcode 0111 1 ro r4 ro The content of the carry bit is added to accumulator location 0 The contents of register are then added to the accumulator Carry is affected A C r 0 7 Example ADDRGC ADDC A R4 ADD CARRY AND REG 4 CONTENTS TO ACC 30 intel A UPI 41A 41AH 42 42AH USER S MANUAL ADDC A Rr Add Carry and Data Memory Contents to Accumulator Opcode 0111 000r The content of carry bit is added to accumulator location 0 Then contents of the standard data memory location addressed by register r bits 0 7 are added to the accumula tor Carry is affected A A Rr 0 1 Example MOV 1 40 MOV 40 DEC TO 1 ADDC A GRI ADD CARRY AND LOCATION 40 CONTENTS TO ACC ADDC A data Add Carry and Immediate Data to Accumulator Opcode 0001 0011 9796 95 94 dg do dy do This is a 2 cycle instruction The content of the carry bit is added to accumulator location 0 Then the specified data is added to the accumulator Carry is affected lt A Example ADDC A 255 ADD CARRY AND 225 DEC ACC ANLA Rr Logical AND Accumulator With Register Mask Opcode
58. as follows 1 The processor is requested to stop by applying a low level on SS The SS input should not be brought low while SYNC is high The UPI samples the SS pin in the middle of the SYNC pulse 2 The processor responds to the request by stopping during the instruction fetch portion of the next in struction If a double cycle instruction is in progress when the single step command is received both cy cles will be completed before stopping 3 The processor acknowledges it has entered the stopped state by raising SYNC high In this state which can be maintained indefinitely the 10 bit ad dress of the next instruction to be fetched is preset on PORT 1 and the lower 2 bits of PORT 2 4 SS is then raised high to bring the processor out of the stopped mode allowing it to fetch the next in struction The exit from stop is indicated by the proc essor bringing SYNC low 54 5 To stop the processor at the next instruction SS must be brought low again before the next SYNC pulse the circuit in Figure 4 1 uses the trailing edge of the previous pulse If SS is left high the processor re mains in the RUN mode Figure 4 1 shows a schematic for implementing single step A single D type flip flop with preset and clear is used to generate SS In the RUN mode SS is held high by keeping the flip flop preset preset has precedence over the clear input To enter single step preset is re moved allowing SYNC to bring SS low v
59. ator bit can be directly tested via conditional branch instruc tions Additional instructions are included to simplify loop counters table look up routines and N way branch routines The UPI 41A 41AH 42 42AH Microcomputer han dles arithmetic operations in both binary and BCD for efficient interface to peripherals such as keyboards and displays The instruction set can be divided into the following groups Data Moves Accumulator Operations Flags Register Operations Branch Instructions Control Timer Operations Subroutines Input Output Instructions Data Moves See Instruction Summary The 8 bit accumulator is the control point for all data transfers within the UPI 41A 41AH 42 42AH Data can be transferred between the 8 registers of each work ing register bank and the accumulator directly i e with a source or destination register specified by 3 bits in the instruction The remaining locations in the RAM array are addressed either by Ro or of the active register bank Transfers to and from RAM re quire one cycle Constants stored in Program Memory can be loaded directly into the accumulator or the eight working reg isters Data can also be transferred directly between the 26 accumulator and the on board timer counter the Status Register STS or the Program Status Word PSW Transfers to STS register alter bits 4 7 only Transfers to the PSW alter machine status ac cordin
60. be fore the RETR instruction is executed to return from the service routine otherwise the processor will re en ter the service routine immediately Thus the WR and CS inputs should not be held low longer than the dura tion of the interrupt service routine The interrupt system is single level Once an interrupt is detected all further interrupt requests are latched but are not acted upon until execution of an RETR instruc tion re enables the interrupt input logic This occurs at the beginning of the second cycle of the RETR instruc tion If an IBF interrupt and a timer overflow interrupt occur simultaneously the IBF interrupt will be recog nized first and the timer overflow interrupt will remain pending until the end of the interrupt service routine External Interrupts An external interrupt can be created using the UPI 41 41 42 42 timer counter in the event counter mode The counter is first preset to FFH and the EN TCNTI instruction is executed A timer over flow interrupt is generated by the first high to low tran UPI 41A 41AH 42 42AH USER S MANUAL sition of the TEST 1 input pin Also if an IBF interrupt occurs during servicing of the timer counter interrupt it will remain pending until the end of the service rou tine Host Interrupts And DMA If needed two external interrupts to the host system can be created using the EN FLAGS instruction This instruction allocates two I O lines on PORT 2
61. cle instruction Control passes to specified address if the TEST 1 signal is low Pin is sampled during SYNC PCo_7 lt addr ifT 0 JT1LOW JNT1 OBBH JUMP TO LOCATION BB HEX 0 JNZ address Jump If Accumulator Is Not Zero Opcode Example 1001 0110 a7 ag 82 ay This is a 2 cycle instruction Control passes to the specified address if the accumulator con tents are nonzero at the time this instruction is executed PCo_7 lt addr 0 JNZ OABH JUMP TO LOCATION AB HEX ACC VALUE IS NONZERO JOBF Address Jump If Output Buffer Full Flag Is Set Opcode Example 1000 0110 ag ag 82 This is a 2 cycle instruction Control passes to the specified address if the Output Buffer Full OBF flag is set 1 at the time this instruction is executed PCo 7 lt addr if OBF 1 JOBFHI JOBF OAAH JUMP TO LOCATION AA HEX OBF 1 JTF address Jump If Timer Flag is Set 40 Opcode Example 0001 0110 a7 ag as 82 ay This is a 2 cycle instruction Control passes to the specified address if the timer flag is set to one that is the timer counter register overflows to zero The timer flag is cleared upon execution of this instruction This overflow initiates an interrupt service seq
62. cumulator UPI 41A 41AH 42 42AH USER S MANUAL CONTROL BUS SYSTEM INTERFACE DATA UPI Bus Contents During Status Read ST STe STs ST4 Fy Fo IBF D7 D6 D5 D4 D3 D2 D1 DO STATUS REGISTER DATA BUS INPUT REGISTER DATA BUS BUS OUTPUT REGISTER 231318 21 Figure 2 16 Data Bus Buffer Configuration Fo This is a general purpose flag which can be cleared or toggled under UPI software control The flag is used to transfer UPI status information to the mas ter processor F4 Command Data This flag is set to the condition of the input line when the master processor writes a character to the data register The F flag can also be cleared or tog gled under UPI Microcomputer program control ST4 through ST7 These bits are user defined status bits They are de fined by the MOV STS A instruction SYSTEM INTERFACE Figure 2 17 illustrates how a UPI Microcomputer can be connected to a standard 8080 type bus system Data lines Do D7 form a three state bidirectional port which can be connected directly to the system data bus The UPI bus interface has sufficient drive capability 400 for small systems however a larger system may require buffers Four control signals are required to handle the data and status information transfer e WR I O WRITE signal used to transfer data from the system bus to the UPI DBBIN register and
63. dled by the UPI s two I O ports intel Figure 6 4 shows an I O interface design based on the UPI This configuration includes 12 parallel I O lines and a serial RS232C interface for full duplex data transfer up to 1200 baud This type of design can be used to interface a master processor to a broad spec trum of peripheral devices as well as to a serial commu nication channel Universal I O Interface PORT 1 is used strictly for I O in this example while PORT 2 lines provide five functions P23 P20 T O lines bidirectional Request to send RTS Clear to send CTS Interrupt to master P5 Serial data out The parallel I O lines make use of the bidirectional port structure of the UPI Any line can function as an input or output All port lines are automatically initial ized to 1 by a system RESET pulse and remain latched An external TTL signal connected to a port line will override the UPI s 50 internal pull up so that an INPUT instruction will correctly sample the TTL sig nal DATA ENCODE DECODE AND COMMAND UPI 41A 41AH 42 42AH 8 BIT MASTER PROCESSOR CONTROL DATA BUS CONTROL BUS 231318 45 Figure 6 3 Tape Transport Controller 64 intel Four PORT 2 lines function as general I O similar to PORT 1 Also the RTS signal is generated on PORT 2 under software control when the UPI has serial data to send The CT
64. e I O port data on PORTS 10 17 and PORTS 20 22 The I O port data may be demultiplexed using an ex ternal latch on the rising edge of SYNC The program counter contents may be demultiplexed similarly using the trailing edge of SYNC Reading and or writing the Data Bus Buffer registers is still allowed although only when Do D not being sampled for opcode data In practice since this sam pling time is not known externally reads or writes on the system bus are done during SYNC high time Ap proximately 600 ns are available for each read or write cycle POWER DOWN MODE UPI 41AH 42AH ONLY Extra circuitry is included in the UPI 41AH 42AH version to allow low power standby operation Power is removed from all system elements except the inter UPI 41A 41AH 42 42AH USER S MANUAL nal data RAM in the low power mode Thus the con tents of RAM can be maintained and the device draws only 10 to 15 of its normal power The Vcc pin serves as the 5V power supply pin for all of the UPI 41AH 42AH version s circuitry except the data RAM array The Vpp pin supplies only the RAM array In normal operation both and are connected to the same 5V power supply To enter the Power Down mode the RESET signal to the UPI is asserted This ensures the memory will not be inadvertently altered by the UPI during power down The Vcc pin is then grounded while Vpp is maintained at 5V Figure 4 4 illustrates a recommended
65. e which renders the EPROM Array unreadable when set UPI 41A 41AH 42 42AH USER S MANUAL All UPI s have the following main features 8 bit CPU 8 bit data bus interface registers The UPI family has the following differences intel Interval timer event counter Two 8 bit TTL compatible I O ports Resident clock oscillator circuits Table 1 2 UPI 41A UPI 42 UPI 41AH UPI 42AH 1K 8 EPROM 2K x 8 EPROM 1K x8 ROM 2K x8 ROM or 1 8 2K x8 OTP 64 x 8 RAM 128 x 8 RAM 128 x 8 RAM 256 x 8 RAM Set Security Feature Signature Row Feature 32 Bytes with 1 Test Code Checksum 2 Intel Signature 3 Security Byte 4 User Signature PROGRAMMING UPI 41A UPI 42 UPI 41AH UPI 42AH Vpp 25V 21V 12 5V 50 ms 50 mA 30 mA EA 21 5V 24 5V 18V 12 5V 21 5V 24 5V 18V 20 V 5 5V TPW 50 ms 50 ms 1ms PIN DESCRIPTION UPI 41A UPI 42 UPI 41AH UPI 42AH T1 T1 functions as a test input which can be directly tested using conditional branching instructions It functions as the event timer input under software control T1 functions as a test input that can be directly tested using conditional branching instructions It works as the event timer input under software control It is used during sync mode to reset the instruction state to 51 and synchronize the internal clock to phase 1 SS Single step input used with the sync output to step the program t
66. egister r are unaffected Ao 3 lt gt Rro 3 0 1 Example Assume program counter contents have been stacked in locations 22 23 XCHNIB MOV RO 23 MOVE 23 DEC TO REG 0 CLR A CLEAR ACC TO ZEROS XCHD A RO EXCHANGE BITS 0 3 OF ACC AND LOCATION 23 BITS 8 11 OF PC ARE ZEROED ADDRESS REFERS TO PAGE 0 XRL A Rr Logical XOR Accumulator With Register Mask Opcode 1101 1rer ro Data in the accumulator is EXCLUSIVE ORed with the mask contained in working register iB lt gt XOR r 0 7 Example XORREG XRL A R5 ACC CONTENTS WITH IN REG 5 XRL A Rr Logical XOR Accumulator With Memory Mask Opcode 1101 000r Data in accumulator is EXCLUSIVE ORed with the mask contained in data memory location address by register r bits 0 7 lt A XOR RD r 0 1 Example XORDM MOV 1 20 MOVE 20 HEX TO REG 1 XRL A GR1 ACC CONTENTS WITH MASK IN LOCATION 32 XRL A data Logical Accumulator With Immediate Mask Opcode 1101 0011 dz da 95 94 da do dy do This is a 2 cycle instruction Data in the accumulator is EXCLUSIVE ORed with an immedi ately specified mask A lt A data Example XORID XRL A ZHEXTEN XOR CONTENTS OF ACC WITH MASK EQUAL VALUE OF SYMBOL HEXTEN 52 intel UPI 41A 41AH 42 42AH USER S MANUAL CHAPTER 4 SINGLE STEP A
67. er whether it is operat ing with an internal or an external clock source In addition two instructions allow the timer interrupt to be enabled or disabled Subroutines Subroutines are entered by executing a call instruction Calls can be made to any address in the 1K word pro gram memory Two separate return instructions deter mine whether or not status i e the upper 4 bits of the PSW is restored upon return from a subroutine Input Output Instructions Two 8 bit data bus buffer registers DBBIN and DBBOUT and an 8 bit status register STS enable the UPI 41A universal peripheral interface to communi cate with the external microcomputer system Data can be INputted from the DBBIN register to the accumula tor Data can be OUTputted from the accumulator to the DBBOUT register The STS register contains four user definable bits ST4 517 plus four reserved status bits IBF Fo and 1 The user definable bits are set from the accu mulator The UPI 41A 41AH 42 42AH peripheral interface has two 8 bit static I O ports which can be loaded to and from the accumulator Outputs are statically latched but inputs to the ports are sampled at the time an IN instruction is executed In addition immediate data from program memory can be ANDed and ORed directly to PORTS 1 and 2 with the result remaining on the port This allows masks stored in program mem ory to be used to set or reset individual bits on the I O ports PO
68. era tion up to 12 5 MHz If automatic initialization is used RESET should be held low for at least 10 milliseconds to allow the power supply to stabilize If an external RESET signal is used RESET may be held low for a minimum of 8 instruc tion cycles Figure 2 15 illustrates a configuration using an external TTL gate to generate the RESET input This configuration can be used to derive the RESET signal from the 8224 clock generator in an 8080 system 19 UPI 41A 41AH 42 42AH USER S MANUAL oo rar UPI 41A 41AH 42 42AH UPI 41A 41AH 42 42AH EXTERNAL RESET SIGNAL RESET OPEN COLLECTOR 231318 20 Figure 2 15 External Reset Configuration The RESET input performs the following functions Disables Interrupts Clears Program Counter to Zero Clears Stack Pointer Clears Status Register and Flags Clears Timer and Timer Flag Stops Timer Selects Register Bank 0 Sets PORTS 1 and 2 to Input Mode DATA BUS BUFFER Two 8 bit data bus buffer registers DBBIN and DBBOUT serve as temporary buffers for commands and data flowing between it and the master processor Externally data is transmitted or received by the DBB registers upon execution of an INput or OUTput in struction by the master processor Four control signals are used Ao Address input signifying control or data 5 Chip Select RD Read Strobe WR Write Strobe Transfer c
69. ermines the stack pair to be used at a given time The stack pointer is initialized by a RESET signal to which corresponds to RAM locations 8 and 9 The first call or interrupt results in the program coun ter and PSW contents being transferred to RAM loca tions 8 and 9 in the format shown in Figure 2 7 The stack pointer is automatically incremented by 110 point to location is 10 and 11 in anticipation of another CALL Nesting of subroutines within subroutines can continue up to 8 levels without overflowing the stack If overflow does occur the deepest address stored locations 8 and 9 will be overwritten and lost since the stack pointer overflows from 07H to Likewise the stack pointer will underflow from 00H to 07H The end of a subroutine is signaled by a return instruc tion either RET or RETR Each instruction will auto matically decrement the Stack Pointer and transfer the contents of the proper RAM register pair to the Pro gram Counter PROGRAM STATUS WORD The 8 bit program status word illustrated in Figure 2 8 is used to store general information about program exe cution In addition to the 3 bit Stack Pointer discussed previously the PSW includes the following flags UPI 41A 41AH 42 42AH USER S MANUAL CY Carry AC Auxiliary Carry Fo Flag 0 BS Register Bank Select SAVED IN STACK STACK POINTER B LSB MSI 231318 12 Figure 2 8 Program Status Word
70. faces to the system bus just like any intelli gent peripheral device see Figure 1 1 The host proc essor and the UPI 41A 41AH 42 42AH form a loose ly coupled multi processor system that is communica tions between the two processors are direct Common resources are three addressable registers located physi cally on the UPI 41A 41AH 42 42AH These reg UPI 41A 41AH 42 42AH USER S MANUAL isters are the Data Bus Buffer Input DBBIN Data Bus Buffer Output DBBOUT and Status STATUS registers The host processor may read data from DBBOUT or write commands and data into DBBIN The status of DBBOUT and DBBIN plus user defined status is supplied in STATUS The host may read STATUS at any time An interrupt to the UPI proces sor is automatically generated if enabled when DBBIN is loaded Because the UPI contains a complete microcomputer with program memory data memory and CPU it can function as a Universal controller A designer can program the UPI to control printers tape transports or multiple serial communication channels The UPI can also handle off line arithmetic processing or any num ber of other low speed control tasks POWERFUL 8 BIT PROCESSOR The UPI contains a powerful 8 bit CPU with as fast as 1 2 psec cycle time and two single level interrupts Its instruction set includes over 90 instructions for easy software development Most instructions are single byte and single cycle and none are more than two b
71. gly and provide a means of restoring status after an interrupt or of altering the stack pointer if necessary Accumulator Operations Immediate data data memory or the working registers can be added with or without carry to the accumula tor These sources can also be ANDed ORed or exclu sive ORed to the accumulator Data may be moved to or from the accumulator and working registers or data memory The two values can also be exchanged in a single operation The lower 4 bits of the accumulator can be exchanged with the lower 4 bits of any of the internal RAM loca tions This operation along with an instruction which swaps the upper and lower 4 bit halves of the accumu lator provides easy handling of BCD numbers and other 4 bit quantities To facilitate BCD arithmetic a Decimal Adjust instruction is also included This instruction is used to correct the result of the binary addition of two 2 digit BCD numbers Performing a decimal adjust on the result in the accumulator produc es the desired BCD result The accumulator can be incremented decremented cleared or complemented and can be rotated left or right 1 bit at a time with or without carry A subtract operation can be easily implemented in UPI software using three single byte single cycle instruc tions A value can be subtracted from the accumulator by using the following instructions Complement the accumulator Add the value to the accumulator Complement the
72. hrough each instruction Single step input used with the sync output to step the program through each instruction This pin is used to put the device in sync mode by applying 12 5V to it Port 1 10 17 8 bit Quasi Bidirectional 1 0 Lines Port 1 P10 P17 8 bit Quasi Bidirectional I O Lines 10 17 access the Signature Row Security Bit NOTES For a complete description of the Security Feature refer to the UPI 41AH 42AH Datasheet For a complete description of the Signature Row refer to the UPI 41AH 42AH Datasheet intel HMOS processing has been applied to the UPI family to allow for additional performance and memory capa bility while reducing costs The UPI 41A 41AH 42 42AH are all pin and software compatible This allows growth in present designs to incorporate new features and add additional performance For new designs the additional memory and performance of the UPI 41A 41AH 42 42AH extends the UPI grow your own solution concept to more complex motor control tasks 80 column printers and process control applica tions as examples The 8243 device is an I O multiplexer which allows expansion of I O to over 100 lines if seven devices are used All three parts are fabricated with N channel MOS technology and require a single 5V supply for operation INTERFACE REGISTERS FOR MULTI PROCESSOR CONFIGURATIONS In the normal configuration the UPI 41A 41AH 42 42AH inter
73. ia the clear input Note that SYNC must be buffered since the SN7474 is equivalent to 3 TTL loads The processor is now in the stopped state The next instruction is initiated by stoppe state The next instruc tion is initiated by clocking 1 the flip flop This 1 will not appear on SS unless SYNC is high 1 clear must be removed from the flip flop In response to SS going high the processor begins an instruction fetch which brings SYNC low SS is then reset through the clear input and the processor again enters the stopped state intel EXTERNAL ACCESS The UPI family has an External Access mode EA which puts the processor into a test mode This mode allows the user to disable the internal program memory and execute from external memory External Access mode is useful in testing because it allows the user to test the processor s functions directly It is only useful for testing since this mode uses Dg PORTS 10 17 and PORTS 20 22 This mode is invoked by connecting the EA pin to 5V The 11 bit current program counter contents then come out on PORTS 10 17 and PORTS 20 22 after the SYNC output goes high PORT 10 is the least signifi cant bit The desired instruction opcode is placed on Do D7 before the start of state Sj During state 81 the opcode is sampled from Do D and subsequently exe cuted in place of the internal program memory con tents The program counter contents are multiplexed with th
74. into 256 location pages and three locations are reserved for special use PAGE 7 PAGE 6 5 PAGE 4 PAGE 3 PAGE 2 PAGE 1 LOCATION 7 TIMER INTERRUPT VECTORS PROGRAM HERE LOCATION 3 IBF INTERRUPT VECTORS PROGRAM HERE LOCATION 0 RESET VECTORS PROGRAM HERE PROGRAM MEMORY MAP 231318 10 ADDRESS Figure 2 5 Program Memory Map UPI 41A 41AH 42 42AH USER S MANUAL INTERRUPT VECTORS 1 Location 0 Following a RESET input to the processor the next instruction is automatically fetched from location 0 2 Location 3 An interrupt generated by an Input Buffer Full IBF condition when the IBF interrupt is enabled causes the next instruction to be fetched from loca tion 3 3 Location 7 A timer overflow interrupt when enabled will cause the next instruction to be fetched from loca tion 7 Following a system RESET program execution begins at location O Instructions in program memory are nor mally executed sequentially Program control can be transferred out of the main line of code by an input buffer full IBF interrupt or a timer interrupt or when a jump or call instruction is encountered An IBF inter rupt if enabled will automatically transfer control to location 3 while a timer interrupt will transfer control to location 7 All conditional JUMP instructions and the indirect JUMP instruction are limited in range to the current 256 location page
75. n cludes the following functional blocks shown in Figure 2 4 Arithmetic Logic Unit ALU Instruction Decoder Accumulator Flags Arithmetic Logic Units ALU The ALU is capable of performing the following opera tions ADD with or without carry AND OR and EXCLUSIVE OR Increment Decrement Bit complement Rotate left or right Swap BCD decimal adjust intel In a typical operation data from the accumulator is combined in the ALU with data from some other source on the UPI 41A 41AH 42 42AH internal bus such as a register or an I O port The result of an ALU operation can be transferred to the internal bus or back to the accumulator If an operation such as an ADD or ROTATE requires more than 8 bits the CARRY flag is used as an indica tor Likewise during decimal adjust and other BCD operations the AUXILIARY CARRY flag can be set and acted upon These flags are part of the Program Status Word PSW Instruction Decoder During an instruction fetch the operation code op code portion of each program instruction is stored and decoded by the instruction decoder The decoder gener ates outputs used along with various timing signals to control the functions performed in the ALU Also the instruction decoder controls the source and destination of ALU data Accumulator The accumulator is the single most important register in the processor It is the primary source of data to the
76. n operations illustrated in Figure 2 10 al lows fast instruction execution Table 2 2 Conditional Branch Instructions M Jump Condition Device Instruction Mnemonic Jump if Accumulator JZ addr All bits zero JNZ addr Any bit not zero Accumulator bit JBb addr Bit b 1 Carry flag JC addr Carry flag 1 JNC addr Carry flag 0 User flag JFO addr Fo flag 1 JF1 addr F4 flag 1 Timer flag JTF addr Timer flag 1 Test Input O JTO addr To 1 JNTO addr 0 Test Input 1 JT1 addr T4 1 JNT1 addr Ty Input Buffer flag JNIBF addr IBF flag 0 Output Buffer flag JOBF addr OBF flag 1 OSCILLATOR 3 25 SYNC STATE CYCLE COUNTER COUNTER 231318 13 Figure 2 9 Oscillator Configuration 14 SYNC ze _ 1 2 4 17 S INPUT INPUT INST DECODE EXECUTION INST OUTPUT ADDRESS OUTPUT ADDRESS 231318 14 Figure 2 10 Instruction Cycle Timing In UPI 41A 41AH 42 42AH USER S MANUAL Table 2 3 Instruction Timing Diagram 1 2 Instruction 51 52 53 54 55 1 52 53 54 55 Fetch ncrement Increment Read Port IN A Pp t ze Instruction Program Counter Timer Fetch ncrement Increment Output Instruction Program Counter
77. ng registers banks The UPI 41A 41AH 42 42AH provides two instruc tions for control of the external microcomputer system IBF and OBF flags can be routed to PORT 2 allowing interrupts of the external processor DMA handshaking signals can also be enabled using lines from PORT 2 The IBF interrupt can be enabled and disabled using two instructions Also the interrupt is automatically disabled following a RESET input or during an inter rupt service routine The working register bank switch instructions allow the programmer to immediately substitute a second 8 regis ter bank for the one in use This effectively provides either 16 working registers or the means for quickly saving the contents of the first 8 registers in response to an interrupt The user has the option of switching regis ter banks when an interrupt occurs However if the banks are switched the original bank will automatically be restored upon execution of a return and restore status RETR instruction at the end of the interrupt service routine Timer The 8 bit on board timer counter can be loaded or read via the accumulator while the counter is stopped or while counting The counter can be started as a timer with an internal clock source or as an event counter or timer with an 27 UPI 41A 41AH 42 42AH USER S MANUAL external clock applied to the TEST 1 pin The instruc tion executed determines which clock source is used A single instruction stops the count
78. o routine when timer reaches 64 that is when bit 6 is set assuming initializa tion to zero TIMCHK MOV A T MOVE TIMER CONTENTS JB6 EXIT JUMP TO EXIT IF ACC BIT 65 1 MOV PSW A Move Accumulator Contents to PSW Opcode Example 42 11010111 The contents of the accumulator are moved into program status word condition bits and the stack pointer are affected by this move PSW lt Move up stack pointer by two memory locations that is increment the pointer by one INCPTR MOV A PSW MOVE PSW CONTENTS ACC INCA NCREMENT ACC BY ONE MOV PSW A MOVE ACC CONTENTS TO PSW intel UPI 41A 41AH 42 42AH USER S MANUAL MOV Rr A Move Accumulator Contents to Register Opcode Example 1010 The contents of the accumulator are moved to register r Rr 0 7 MRA MOVE CONTENTS OF TO 0 MOV Rr data Move Immediate Data to Register Opcode Example 1011 1rer4ro dz dg 95 94 da do dy do This is a 2 cycle instruction The 8 bit value specified by data is moved to register Rr lt data 0 7 MIR4 4 tHE VALUE OF THE SYMBOL HEXTEN IS MOVED INTO REG 4 MIR5 MOV R5 PI R R tHE VAUE OF THE EXPRESSION PI R R 18 MOVED INTO REG 5 MIR6 MOV R6 OADH AD HEXIS MOVED INTO RE
79. om pletely pin compatible This feature allows extensive testing with the EPROM part even into initial ship ments to customers Yet the transition to low cost ROMs or OTP EPROM is simplified to the point of being merely a package substitution PREPROGRAMMED UPI s The 8242AH 8292 and 8294 are 8042AH s that are programmed by Intel and sold as standard peripherals Intel offers a complete line of factory programmed key board controllers These devices contain firmware de veloped by Phoenix Technologies Ltd and Award Soft ware Inc See Table 1 3 for a complete listing of Intels entire keyboard controller product line The 8292 is a GPIB controller part of a three chip GPIB system The 8294 is a Data Encryption Unit that implements the National Bureau of Standards data encryption algo rithm These parts illustrate the great flexibility offered by the UPI family LI UPI 41A 41AH 42 42AH USER S MANUAL intel Table 1 3 Keyboard Controller Family Product Selection Guide UPI 42 The industry standard for desktop Keyboard Control Device Package ROM OTP Comments 8042 N P 2K ROM Device 8242 N P Phoenix firmware version 2 5 8242PC Phoenix MultiKey 42 firmware PS 2 style mouse support 8242WA N P Award firmware version 3 57 8242WB N P Award firmware version 4 14 PS 2 style mouse support 8742 N P D 2K Available as OTP N P or EPROM D UPI C42 A low power CHMOS version of
80. on Set Features 4 Preprogrammed UPPS 5 Development Support 6 UPI Development Support 6 CHAPTER 2 FUNCTIONAL DESCRIPTION 7 Pin Description 7 CPU Section 10 Program Memory 11 Interrupt Vectors 11 Data Memory 11 Program Counter 12 Program Counter Stack 12 Program Status Word 13 Conditional Branch Logic 13 Oscillator and Timing Circuits 14 Interval Timer Event Counter 16 Test 17 Interrupts 18 Reset ENT SER 19 Data Bus Buffer 20 System Interface 21 Input Output Interface 22 Ports 2 22 Ports 4 5 and 7 23 CHAPTER 3 INSTRUCTION SET 26 Instruction Set Description 28 Alphabetic Listing 30 CHAPTER 4 SINGLE STEP AND PROGRAMMING POWER DOWN MODES eu ea eG Aten 53 Single Step 53 External Access 55 Power Down Mode UPI 41AH 42AH Only 55
81. one state in order to be registered 250 ns at 12 MHz The maximum count frequency is one count per three instruction cycles 267 kHz at 12 MHz There is no minimum frequency limit intel Timer Mode The STRT T instruction connects the internal clock to the counter input and enables the counter The input clock is derived from the SYNC signal of the internal oscillator and the divide by 32 prescaler The configu ration is illustrated in Figure 2 13 Note this instruction does not clear the timer register Various delays and timing sequences between 40 usec and 10 24 msec easily be generated with a minimum of software timing loops at 12 MHz Times longer than 10 24 msec can be accurately mea sured by accumulating multiple overflows in a register under software control For time resolution less than 40 psec an external clock can be applied to the TEST 1 counter input see Event Counter Mode The mini mum time resolution with an external clock is 3 75 psec 267 kHz at 12 MHz TEST 1 Event Counter Input The TEST 1 pin is multifunctional It is automatically initialized as a test input by a RESET signal and can be tested using UPI 41A conditional branch instructions In the second mode of operation illustrated in Figure 2 13 the TEST 1 pin is used as an input to the internal UPI 41A 41AH 42 42AH USER S MANUAL 8 bit event counter The Start Counter STRT CNT instruction controls an internal switch which connec
82. onnected to a single 8048 master processor In this configuration the 8048 uses PORT O as a data bus I O PORT 2 is used to select one of the seven 59 UPI 41A 41AH 42 42AH USER S MANUAL XTAL1 XTAL2 UPI 41A 41AH PERIPHERAL RD 42 42AH DEVICES WR TEST 0 a amp TEST 1 231318 40 Figure 5 9 8080A UPI Interface WR UPI 41A 41AH PERIPHERAL 42 42AH DEVICES cs CONTROL 5 2 Ao DATA BUS 8 231318 41 Figure 5 10 8048 UPI Interface UPI s when data transfer occurs The UPI s are pro grammed to handle isolated tasks and since they oper ate in parallel system throughput is increased GENERAL HANDSHAKING PROTOCOL 1 Master reads STATUS register RD CS Ao 0 0 1 in polling or in response to either an IBF or an OBF interrupt 2 If the UPI DBBIN register is empty IBF flag 0 Master writes a word to the DBBIN register WR 60 CS Ao 0 0 1 0 0 0 If Ag 1 write command word set If Ag 0 write data word Fi 0 3 If the UPI DBBOUT register is full OBF flag 1 Master reads a word from the DBBOUT register RD CS 0 0 0 4 UPI recognizes IBF via IBF interrupt or JNIBF Input data or command word is processed depend ing on F1 IBF is reset Repeat step 1 above 5 UPI recognizes OBF flag 0 via JOBF Next word is output to DBBOUT register OBF is set
83. ously selected bank During 12 intel interrupt processing registers in bank 0 can be accessed indirectly using and Ry If register bank 1 is not used registers 24 31 can still serve as additional scratch pad memory Program Counter Stack RAM locations 8 23 are used as an 8 level program counter stack When program control is temporarily passed from the main program to a subroutine or inter rupt service routine the 10 bit program counter and bits 4 7 of the program status word PSW are stored in two stack locations When control is returned to the main program via an RETR instruction the program counter and PSW bits 4 7 are restored Returning via an RET instruction does not restore the PSW bits however The program counter stack is addressed by three stack pointer bits in the PSW bits 0 2 Opera tion of the program counter stack and the program status word is explained in detail in the following sec tions The stack allows up to eight levels of subroutine nest ing that is a subroutine may call a second subroutine which may call a third etc up to eight levels Unused stack locations can be used as scratch pad memory Each unused level of subroutine nesting provides two additional RAM locations for general use The following sections provide a detailed description of the Program Counter Stack and the Program Status Word PROGRAM COUNTER The UPI 41A 41AH 42 42AH microcomputer has a 10 bit
84. portion of the program counter PC 0 7 PCo_7 lt Assume accumulator contains OFH JMPPAG JMPP A TO ADDRESS STORED IN LOCATION 15 IN CURRENT PAGE JNC address Jump If Carry Is Not Set Opcode Example 1110 0110 ag ag 82 ay This is a 2 cycle instruction Control passes to the specified address if the carry bit is not set that is equals zero 7 lt addr ifC 0 JC0 JNC NOVFLO JUMP TO NOVFLO ROUTINE 0 address Jump If Input Buffer Full Flag Is Low Opcode Example 1101 0110 a7 ag as ay This is a 2 cycle instruction Control passes to the specified address if the Input Buffer Full flag is low IBF 0 PCo_7 addr if IBF 0 LOC 3 JNIBF LOC 3 jUMP TO SELF IF IBF 0 OTHERWISE CONTINUE 39 LI UPI 41A 41AH 42 42AH USER S MANUAL intel JNTO address Jumpif TEST 0 is Low Opcode Example 0010 0110 ag a5 ag ay This is a 2 cycle instruction Control passes to the specified address if the TEST 0 signal is low Pin is sampled during SYNC PCo_7 lt addr ifTp 0 JTOLOW JNTO 60 JUMP TO LOCATION 60 DEC To 0 JNT1 address Jump If TEST 1 is Low Opcode Example 0100 0110 28786854284 ag 82 ay This is a 2 cy
85. program counter PC which can directly ad dress any of the 1024 2048 or 4096 locations in pro gram memory The program counter always contains the address of the next instruction to be executed and is normally incremented sequentially for each instruction to be executed when each instruction fetches occurs When control is temporarily passed from the main pro gram to a subroutine or an interrupt routine however the PC contents must be altered to point to the address of the desired routine The stack is used to save the current PC contents so that at the end of the routine main program execution can continue The program counter is initialized to zero by a RESET signal PROGRAM COUNTER STACK The Program Counter Stack is composed of 16 loca tions in Data Memory as illustrated in Figure 2 7 These RAM locations 8 through 23 are used to store the 10 bit program counter and 4 bits of the program status word intel An interrupt or Call to a subroutine causes the contents of the program counter to be stored in one of the 8 register pairs of the program counter stack DATA STACK MEMORY POINTER LOCATION 111 22 110 20 101 19 18 100 12 16 011 19 14 010 13 12 001 b 10 000 PSW 4 7 PC 8 9 9 PC 4 7 0 8 LSB Figure 2 7 Program Counter Stack A 3 bit Stack Pointer which is part of the Program Status Word PSW det
86. rogram Counter Interrupt EN DMA Fetch ncrement DMA Enabled Instruction Program Counter DRQ Cleared Fetch ncrement OBF IBF EN FLAGS instruction Program Counter Output Enabled 2 xtaut 1 UPI 41A 41AH 42 42 XTAL2 231318 48 231318 15 Figure 2 11 Recommended Crystal and L C Connections 15 UPI 41A 41AH 42 42AH USER S MANUAL Cycle Counter The output of the state counter is divided by 5 in the cycle counter to generate a signal which defines a ma chine cycle This signal is call SYNC and is available continuously on the SYNC output pin It can be used to synchronize external circuitry or as a general pur pose clock output It is also used for synchronizing sin gle step Frequency Reference The external crystal provides high speed and accurate timing generation A crystal frequency of 5 9904 MHz is useful for generation of standard communication fre quencies by the UPI 41A 41AH 42 42AH However if an accurate frequency reference and maximum proc essor speed are not required an inductor and capacitor may be used in place of the crystal as shown in Figure 2 11 A recommended range of inductance and capacitance combinations is given below L 130 uH corresponds to 3 MHz L 45 uH corresponds to 5 MHz An external clock signal can also be used as a frequency reference to the UPI 41A 41AH 42 42AH however the levels are not TTL compatible The signal must be in the 1 12 5 MHz frequency
87. s RO is shown as RO Contents of intel UPI 41A 41AH 42 42AH USER S MANUAL Table 3 2 Instruction Set Summary Mnemonic Description Bytes Cycle Mnemonic Description Bytes Cycle ACCUMULATOR DATA MOVES Continued ADD A Rr Add register to A 1 1 MOVPA 9A Moveto A from current ADD A eRr Add data memory to A 1 1 page 1 2 ADD A data Add immediate to 2 2 MOVP3 A Move to A from page 3 1 2 ADDC A Rr Add register to A with carry 1 1 ADDC A Rr to A TIMER COUNTER MOV A T Read Timer Counter 1 1 ADDE MOVT A Load Timer Counter 1 1 data with carry 2 2 4 STRT T Start Timer 1 1 ANL A Rr And register to A 1 1 STRT CNT Start Counter 1 1 ANL A Rr And data memory to A 1 1 2 STOP TCNT Stop Timer Counter 1 1 ANL A data And immediate to 2 2 EN TCNTI Enable Timer Counter 1 1 pean gat con 1 1 DISTCNTI Disable Timer Counter 1 1 ORL A Rr Or data memory to A 1 1 Interrupt ORLA Or immediate to 2 2 XRL A Rr Exclusive Or CONTROL register to A 1 1 EN DMA Enable DMA Handshake XRL A Rr Exclusive Or data Lines 1 1 memory to A 1 1 Enable IBF interrupt 1 1 XRLA data Exclusive Or DIS Disable IBF interrupt 1 1 immediate to A 2 2 EN FLAGS Enable Master Interrupts 1 1 INCA Increment A 1 1 SEL RBO Select register bank 0 1 1 DEC Decrement A 1 1 SEL RB1 Select register bank 1 1 1 CLRA Clear A 1 1 NOP No Operation 1 1 CPLA
88. s and maching flags TEST 0 input pin TEST input pin Input Buffer Full flag Output Buffer Full flag Timer flag Accumulator zero Accumulator bit Carry flag Fo flag F flag The conditions tested by these instructions are the instantaneous values at the time the conditional jump instruction is executed For instance the jump on accu mulator zero instruction tests the accumulator itself not an intermediate flag The decrement register and jump if not zero DJNZ instruction combines decrement and branch operations UPI 41A 41AH 42 42AH USER S MANUAL in a single instruction which is useful in implementing a loop counter This instruction can designate any of the 8 working registers as a counter and can effect a branch to any address within the current page of execution A special indirect jump instruction JMPP allows the program to be vectored to any one of several differ ent locations based on the contents of the accumulator The contents of the accumulator point to a location in program memory which contains the jump address As an example this instruction could be used to vector to any one of several routines based on an ASCII charac ter which has been loaded into the accumulator In this way ASCII inputs can be used to initiate various rou tines Control The UPI 41A 41AH 42 42AH Instruction Set has six instructions for control of the DMA interrupts and selection of worki
89. s is a 2 cycle instruction The 8 bit value spedified by data is loaded in the accumulator A data Example A OA3H MOV HEX TO ACC MOV A PSW Move PSW Contents to Accumulator Opcode 1100 01411 The contents of the program status word are moved to the accumulator lt PSW Example Jump to RBISET routine if bank switch PSW bit 4 is set BSCHK MOV A PSW MOV PSW CONTENTS TO ACC JB4 RB1 SET TO RBISET IF ACC 4 1 41 LI UPI 41A 41AH 42 42AH USER S MANUAL intel MOV Move Register Contents to Accumulator Opcode Example 1111 1 ro r4 ro Eight bits of data are moved from working register r into the accumulator A 0 7 MAR MOV A R3 MOVE CONTENTS OF REG 3 TO ACC MOV A Rr Move Data Memory Contents to Accumulator Opcode Example 1111 00 The contents of data memory location addressed bits 0 7 of register are moved to the accumulator Register r contents are unaffected lt Rn r 0 1 Assume R1 contains 00110110 MADM MOV A R1 MOVE CONTENTS OF DATA MEM LOCATION 54 TO ACC MOVA T Move Timer Counter Contents to Accumulator Opcode Example 0100 0010 The contents of the timer event counter register are moved to the accumulator The timer event counter is not stopped lt Jump t
90. sted in a single operation Scan time for 128 keys is about 10 ms Each matrix point has a unique binary code which is used to address ROM when a key closure is detected Page 3 of ROM contains a look up table with useable codes 1 ASCH EBCDIC etc which correspond to each key When a valid key closure is detected the ROM code corresponding to that key is stored in a FIFO buffer in data memory for transfer to the master processor To avoid stray noise and switch bounce a key closure must be detected on two consecutive scans before it is consid ered valid and loaded into the FIFO buffer The FIFO buffer allows multiple keys to be processed as they are depressed without regard to when they are released a condition known as N key rollover The basic features of this encoder are fairly standard and require only about 500 bytes of memory Since the UPI is programmable and has additional memory ca pacity it can handle a number of other functions For example special keys can be programmed to give an entry on closing as well as opening Also I O lines are PORT 4 PORT 5 8243 EXPANDER PORT 6 PORT 7 PORT2 PROG INTERFACE DATA BUS TO 8 BIT MASTER Ree CONTROL BUS UPI 41A 41AH 42 42AH KEYBOARD MATRIX 16 COLUMNS PORT 1 PORT 2 CONTROL 231318 43 Figure 6 1 Keyboard Encoder Configuration 62 intel available to control a 16 digit 7 segment display The UPI can also
91. t Pp OR data p 1 2 see OUTL instruction Example ORL P1 OFH PORT 1 CONTENTS WITH MASK FF HEX SET PORT 1 TO ALL ONES ORLD Pp A Logical OR Port 4 7 With Accumulator Mask Opcode 1000 11 p4 This is a 2 cycle instruction Data 8243 port p is logically ORed with the digit mask contained in accumulator bits 0 3 Pp Pp p 4 7 See MOVD instruction Example ORP7 P7 A PORT 7 CONTENTS WITH ACC BITS 0 3 OUT DBB A Output Accumulator Contents to Data Bus Buffer Opcode 0000 0010 Contents of accumulator are transferred to Data Bus Buffer Output register and Output Buffer Full OBF flag is set to one DBB A lt 1 Example OUTDBB OUT DBB A OUTPUT THE CONTENTS OF ACC TO DBBOUT 46 intel UPI 41A 41AH 42 42AH USER S MANUAL OUTL Pp A Output Accumulator Data to Port 1 and 2 Opcode 0011 10 py This is a 2 cycle instruction Data residing in accumulator is transferred written to port and latched Pp lt A P 1 2 Note Bits 0 1 of the opcode are used to represent PORT 1 and PORT 2 If you are coding in binary rather than assembly language the mapping is as follows Edad Port P1 Po 0 0 X 0 1 1 1 0 2 1 1 X Example OUTLP MOV A R7 MOVE REG 7 CONTENTS TO ACC OUTL P2 A O
92. t sinking capability to pull down the pin to the low state An IN A Pp instruction will sample the status of PORT pin and will input the proper logic level With no external input connected the IN A Pp instruction inputs the previous output status This structure allows input and output information on the same pin and also allows any mix of input and output lines on the same port However when inputs and outputs are mixed on one PORT a PORT write will cause the strong internal pull ups to turn on at all inputs If a switch or other low impedance device is connected to an input a PORT write 417 to an input could cause current limits on internal lines to be ex ceeded Figure 2 19 illustrates the recommended con nection when inputs and outputs are mixed on one PORT The bidirectional port structure in combination with the UPI 41A 41AH 42 42AH logical AND and OR instructions provide an efficient means for handling sin gle line inputs and outputs within an 8 bit processor PORTS 4 5 6 and 7 By using an 8243 I O expander 16 additional I O lines can be connected to the UPI 41AH 42AH and directly addressed as 4 bit I O ports using UPI 41AH ORL ANL INTERNAL BUS WRITE PULSE 231318 23 Figure 2 18 Quasi Bidirectional Port Structure 23 UPI 41A 41AH 42 42AH USER S MANUAL instructions This feature saves program space and de sign time and improves the bit handling capability of the UPI 41A 41
93. ta memory can buffer data and commands for up to 4 low speed channels 110 baud teletypewriter etc Application Notes The following application notes illustrate the various applications of the UPI family Other related publica tions including the Microcontroller Handbook are avail able through the Intel Literature Department PARALLEL CTS RTS PORT 1 AND 2 DBB INTERFACE TO 8 BIT MASTER PROCESSOR PROCESSOR PORT 2 UPI 41A 41AH 42 42AH RS232C SERIAL INTERFACE INTERRUPT OUTPUT MASTER TRANSMIT RECEIVE DATA DATA TEST 0 CONTROL 231318 46 Figure 6 4 Universal I O Interface 65
94. ter Example Initialize and start event counter INITEC CLR A CLEAR ACC TO ZEROS MOV T A MOVE ZEROS TO EVENT COUNTER STRT CNT COUNTER MOVD A Pp Move Port 4 7 Data to Accumulator Opcode 0000 11 py This is 2 cycle instruction Data on 8243 port p is moved read to accumulator bits 0 3 Accumulator bits 4 7 are zeroed Ao 3 lt Pp p 4 7 A4 7 0 Note Bits 0 1 of the opcode are used to represent PORTS 4 7 If you are coding in binary rather than assembly language the mapping is as follows ve Port Pi Po 0 0 4 0 1 5 1 0 6 1 1 7 Example INPPT5 MOVD 5 MOVE PORT 5 DATA TO ACC BITS 0 3 ZERO ACC BITS 4 7 MOVD Pp A Move Accumulator Data to Port 4 5 6 and 7 Opcode 0011 1 1 P4 This is a 2 cycle instruction Data in accumulator bits 0 3 is moved written to 8243 port p Accumulator bits 4 7 are unaffected See NOTE above regarding port mapping Example data in accumulator to ports 4 and 5 OUTP45 MOVD P4 A MOVE ACC BITS 0 3 TO PORT 4 SWAPA EXCHANGE ACC BITS 0 3 AND 4 7 MOVD P5 A MOVE ACC BITS 0 3 TO PORT 5 44 intel UPI 41A 41AH 42 42AH USER S MANUAL Move Current Page Data to Accumulator Opcode 101010011 This is 2 cycle instruction The contents of the program memory location addressed by accumulator are moved to
95. the accumulator Only bits 0 7 of the program counter are affected limiting the program memory reference to the current page The program counter is restored following this operation lt A Note This a 1 byte 2 cycle instruction If it appears in location 255 of a program memory page addresses a location in the following page Example MOV128 MOV 128 MOVE 128 DEC TO ACC MOVP A A CONTENTS OF 129TH LOCATION CURRENT PAGE ARE MOVED ACC Move Page Data to Accumulator Opcode 1110 0011 This is a 2 cycle instruction The contents of the program memory location within page 3 addressed by the accumulator are moved to the accumulator The program counter is restored following this operation lt A within page 3 Example Look up ASCII equivalent of hexadecimal code in table contained at the beginning of page 3 Note that ASCII characters are designated by a 7 bit code the eighth bit is always reset TABSCH MOV A OB8H MOVE B8 HEX TO ACC 10111000 ANL A 7FH LOGICAL AND ACC TO MASK 7 00111000 MOVP3 A A MOVE CONTENTS OF LOCATION 38 HEX IN PAGE 3 TO ACC ASCII 8 Access contents of location in page 3 labelled TAB1 Assume current program location is not in page 3 TABSCH MOV ISOLATE BITS 0 7 OF LABEL ADDRESS VALUE MOVP3 A A MOVE CONTENT OF PAGE 3 LOCATION LABELED TAB ACC NOP The NOP Instruction
96. to its maxi mum count FFH and overflow to zero continuing its count until stopped by a STOP TCNT instruction or RESET The increment from maximum count to zero overflow results in setting the Timer Flag TF and generating an interrupt request The state of the overflow flag is test able with the conditional jump instruction JTF The flag is reset by executing a JTF or by a RESET signal The timer interrupt request is stored in a latch and ORed with the input buffer full interrupt request The timer interrupt can be enabled or disabled independent of the IBF interrupt by the EN TCNTI and DIS TCTNI instructions If enabled the counter overflow will cause a subroutine call to location 7 where the tim er service routine is stored If the timer and Input Buff er Full interrupts occur simultaneously the IBF source will be recognized and the call will be to location 3 Since the timer interrupt is latched it will remain pend ing until the DBBIN register has been serviced and will immediately be recognized upon return from the serv ice routine A pending timer interrupt is reset by the initiation of a timer interrupt service routine Event Counter Mode The STRT CNT instruction connects the TEST 1 input pin to the counter input and enables the counter Note this instruction does not clear the counter The counter is incremented on high to low transitions of the TEST 1 input The TEST 1 input must remain high for a mini mum of
97. ts TEST 1 through an edge detector to the 8 bit internal counter Note that this instruction does not inhibit the testing of TEST 1 via conditional Jump instructions In the counter mode the TEST 1 input is sampled once per instruction cycle After a high level is detected the next occurrence of a low level at TEST 1 will cause the counter to increment by one The event counter functions can be stopped by the Stop Timer Counter STOP TCNT instruction When this instruction is executed the TEST 1 pin becomes a test input and functions as previously described TEST INPUTS There are two multifunction pins designated as Test Inputs TEST 0 and TEST 1 In the normal mode of operation status of each of these lines can be directly tested using the following conditional Jump instruc tions JTO Jump if TEST 0 1 JNTO Jump if TEST 0 0 e JTI Jump if TEST 1 1 JNT1 Jump if TEST 1 0 PRESCALER 32 EXTERNAL INPUT TEST 1 O COUNTER INTERNAL BUS COUNTER OSCILLATOR OVERFLOW FLAG 8 BIT INTERRUPT LOAD READ 231318 17 Figure 2 13 Timer Counter 17 UPI 41A 41AH 42 42AH USER S MANUAL The test imputs are TTL compatible An external logic signal connected to one of the test inputs will be sam pled at the time the appropriate conditional jump in struction is executed The path of program execution will be altered depending on the state of the external signal when sampled
98. uence if the timer overflow interrupt is enabled 7 lt addr if TF 1 JTF1 JTF TIMER JUMP TO TIMER ROUTINE 1 intel A UPI 41A 41AH 42 42AH USER S MANUAL JTO address Jump If TEST 0 Is High Opcode 0011 0110 a7 ag as ay This is a 2 cycle instruction Control passes to the specified address if the TEST 0 signal is high 1 Pin is sampled during SYNC PCo_7 lt addr 1 Example JTOHI JTO 53 JUMP TO LOCATION 53 DEC To 1 JT1 address Jump If TEST 1 Is High Opcode 0101 0110 a7 ag as ay This is a 2 cycle instruction Control passes to the specified address if the TEST 1 signal is high 1 Pin is sampled during SYNC PCo_7 lt addr ifT 1 Example JT1 COUNT JUMP TO COUNT ROUTINE 1 JZaddress Jump If Accumulator Is Zero Opcode 1100 0110 ag as ag 82 ay This is a 2 cycle instruction Control passes to the specified address if the accumulator con tains all zeros at the time this instruction is executed 7 lt addr 0 Example JZ JUMP TO LOCATION HEX ACC VALUE IS ZERO MOV Move Immediate Data to Accumulator Opcode 0010 0011 dz da 95 94 da do dy do Thi
99. urther by providing an intelligent controller that is fully user programmable It is a complete single chip microcomputer which can connect directly to a master processor data bus It has the same advantages of intelligence and flexibility which previous peripheral chips offered In addition UPIs are user programmable it has 1K 2K bytes of ROM or EPROM memory for program storage plus 64 128 256 bytes of RAM memory UPI 41A 41 42 42AH respectively for data storage or ini tialization from the master processor The UPI device allows a designer to fully specify his control algorithm in the peripheral chip without relying on the master processor Devices like printer controllers and key board scanners can be completely self contained rely ing on the master processor only for data transfer The UPI family currently consists of seven compo nents 8741A microcomputer with 1K EPROM memory 8741AH microcomputer with 1K OTP EPROM memory 8041AH microcomputer with 1K ROM memory 8742 microcomputer with 2K EPROM memory 8742AH microcomputer with 2K OTP EPROM memory 8042AH microcomputer with 2K ROM memory 8243 I O expander device The UPI 41A 41AH 42 42AH family of microcom puters are functionally equivalent except for the type and amount of program memory available with each In addition the UPI 41AH 42AH family has a Signa ture Row outside the EPROM Array The UPI 41AH 42AH family also has a Security Featur
100. ycle instruction Register r is decremented and tested for zero If the register contains all zeros program control falls through to the next instruction If the register con tents are not zero control jumps to the specified address within the current page Rr lt Rr 1 If R 0 then PCo_7 lt addr A 10 bit address specification does not cause an error if the DJNZ instruction and the jump target are on the same page If the DJNZ instruction begins in location 255 of a page it will jump to a target address on the following page Otherwise it is limited to a jump within the current page Increment values in data memory locations 50 54 MOV RO 50 MOVE 50 DEC TO ADDRESS REG 0 MOV R3 05 MOVE 5 DEC TO COUNTER REG 3 INCRT INC RO NCREMENT CONTENTS OF LOCATION ADDRESSED BY REGO INC RO NCREMENT ADDRESS IN REG 0 DJNZ R3 INCRT DECREMENT REG 3 JUMP INCRT IF REG 3 NONZERO NEXT NEXT ROUTINE EXECUTED R3 IS ZERO EN Enable DMA Handshake Lines Opcode 1110 0101 DMA handshaking is enabled using P26 as DMA request P27 as DMA acknowl edge DACK The lines forces CS and Ag low internally and clears ENFLAGS Enable Master Interrupts Opcode 36 1111 0101 The Output Buffer Full OBF and the Input Buffer Full IBF flags IBF is inverted are routed to and For proper
101. ytes long The instruction set is optimized for bit manipulation and I O operations Special instructions are included to allow binary or BCD arithmetic operations table look up routines loop counters and N way branch routines UPI 41A 41AH 42 42AH DATA CONTROL BUS BUS ADDRESS BUS MATRIX PRINTER 231318 1 Figure 1 1 Interfacing Peripherals To Microcomputer Systems UPI 41A 41AH 42 42AH USER S MANUAL 8741A XXXX 8741AH 8041AH 8742AH 8042AH m bu 231318 47 231318 2 231318 3 Electrically 8741AH 8742AH 8041AH 8042AH D8742 Programmable Electrically Programmed Electrically Light Erasable Programmed ROM Programmable EPROM OTP EPROM Light Erasable EPROM Figure 1 2 Pin Compatible ROM EPROM Versions SPECIAL INSTRUCTION SET 5 22 Adjus FEATURES Swap 4 bit Nibbles of A For Loop Counters Exchange lower nibbles of A and Register Decrement Register and Jump if not zero Rotate A left or right with or without Carry For Bit Manipulation For Lookup Tables AND to A immediate data or Register Load A from Page of ROM Address in A OR to A immediate data or Register Load A from Current Page of ROM XOR to A immediate data or Register Address in A AND to Output Ports Accumulator OR to Output Ports Accumulator Jump Conditionally on any bit in A PERIPHERAL CONTROL UPI 41A 41AH 42 42AH 8 BIT MICROCOMPUTER SYSTEM OFF

Microprocessor Peripherals UPI- 41A 41AH 42 42AH User`s Manual

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