78Q8430 Driver Manual for ST 5100/OS-20 with NexGen
Contents
1. 4 9 STETHER_Send Prototype ST_ErrorCode_t STETHER_Send NGifnet netp NGbuf bufp Description This function sends new message buffer data to the device It copies data from system memory to the 78Q8430 data buffers and then triggers a 78Q8430 transmit event Parameters netp network interface type NGethifnet_tsc Returns ST NO ERROR if no errors are encountered ST ERROR NO MEMORY if no TX FDs are available from the driver core STETHER_Send tscReadReg_BUS16 hk tscWriteReg_BUS16 Figure 11 STETHER_Send Call Graph 18 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 4 10 STETHER_Start Prototype void STETHER_Start NGifnet netp Description Driver initialization occurs in this function lt copies the first available outgoing packet to the 7808430 It then starts TX and un queues any TX request that it might have processed Parameters netp network interface type NGethifnet_tsc Returns none STETHER_ Stat Gi STETHER_Send gt gt tscReadReg_BUS16 oe tscWriteReg_BUS16 Figure 12 STETHER_ Start Call Graph Rev 1 0 19 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 5 STi5100 IPSTB Platform Example The STi5100 IPSTB demonstrates the 78Q8430 Ethernet driver capability in an2. 3 3 3 DEV FUNCTIONS STRUCT The DEV_FUNCTIONS STRUCT structure is defined in the TSC Ethernet source module commem h Figure 2 shows the call graph for the DEV FUNCTIONS STRUCT structure 3 3 4 DEVICE CONTROL_STRUCT The DEVICE CONTROL_STRUCT structure is defined in the TSC Ethernet source module commem h STETHER_ functions refer to this control block as PDEV_CTRL See the TSC Ethernet source module tscport c for its usage Figure 3 shows the call graph for the DEVICE CONTROL_STRUCT structure Rev 1 0 9 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 10 UM_8430_005 misc_ ctrl MISC_CTRL A k arc_ctrl ARC_CTRL a a wake _pm_ ctrl i WAKE _PM_CTRL a e E ipchk_ OT K IPCHK_ CTRL a h i i Bin intr_ctrl A PHY_INTR_CTRL 4 5 A Lo tx_stp m TX_STP Aa NI sm intr_ctrl INTR_CTRL a a sa po x RX_CTRL Aa RE Ob tx_qsr _ NAL TX_QSR a Be E DEVICE _CONTROL_STRUCT PHY_DIAG pi S gt phy diag lt ABS TX_CTRL i TE S can DEI a F E MAC_CTRL mac_ctrl sa PHY_STATUS w ohy_status i o a RMON Leg H 2 ka mm rmon 7 PHY_MDIX zg phy mdix i ARC_ENTRY a arc entry pen eg i a PHY_CTRL gt eee f phy_ctrl m DMA_CTRL pe GE dma cht Figure 3 DEVICE CONTROL_STRUCT Call Graph Rev 1 0 UM_8430 005 78Q8430 Driver Manual
3. 24 SEMICONDUCTOR CORP Simplifying System Integration 78Q8430 Driver Manual for ST 5100 OS 20 with NexGen TCP IP Stack March 2008 Rev 1 0 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 2008 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Pentium is a registered trademark of Intel Corporation Windows is a registered trademark of Microsoft Corporation All other trademarks are the property of their respective owners Teridian Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Accordingly the reader is cautioned to verify that this document is current by comparing it to the latest version on http www teridian com or by checking with your sales representative Teridian Semiconductor Corp 6440 Oak Canyon Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www teridian com 2 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP
4. Tsc_Interrupt tsc interrupt Int_Level interrupt level Use16Bit use 16 bit bus width Trans_Len transfer packet length Returns none 4 4 STETHER Config ARC Prototype void STETHER_Config_ ARC NGifnet netp Description This function configures the ARC table with the contents of the preset arc_entry array found in DEVICE CONTROL_STRUCT The ARC address has the same format as a standard 6 byte MAC address It implements all the available default rules 14 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack Parameters netp network interface type NGethifnet_tsc Returns none tscArcCtrIPromiscuousMode tscConfigARC tscArcWrite tscArcCtrIMulticastPkt tscWriteReg_Bus16 STETHER_Config_ARC tscArcCtrlOnNowPkt tscReadReg_Bus16 tscArcCtriPausePkt EC tscArcCtrlWrite lt CI tscArcCalcRMR tscArcCtriMagicPkt tscArcCtrlBroadcastPkt tsc TaskLock tsc TaskUnlock Figure 6 STETHER_Config_ARC Call Graph 4 5 STETHER HandleCompletedTXBuffers Prototype INT4 STETHER_HandleCompletedTXBuffers NGifnet netp Description This routine handles TX and error interrupts derived from tsclsr and tscDpr which in turn are the result of STETHER_Send calls for data transmission It extracts and records
5. 25 GE ene a INIGIMANOM ME 25 ADDPENGOIX A e d a 26 Appendix B Rele se e 27 Release Package Contenido da na ao 27 Solhware Build ang Installation aci oia as 27 Changes fom Previous E 27 ise Eiere 21 Rev 1 0 3 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 Figures Figure NG TSE STRUGT Call Graph iio 8 Figure 2 NET CONTROL_STRUCT and DEV_FUNCTIONS STRUCT Call Graphie 9 Figure 3 DEVICE CONTROL STRUCT Call Graphie 10 Figure 4 STETHER_CopyData Call Graph iii 13 Figure 5 STE THER Glose Gall Graph eee bielle 14 Figure 6 STETHER_Config_ ARC Call Graphie 15 Figure 7 STETHER_HandleCompletedTXBuffers Call Graph kakaa kakaa kakaa aaa 16 Figure STEIHER InterruptrlandierCali Graph daa solaio aaa 16 Figure 9 STETHER_Open Call Graph First LEvel iii 17 FIgure 1 0 5 TE THER Receive e UE e perenni aerea 18 Foue 116 3 TE THER Send Call rappin a e doii 18 Figure 12 gt TETHER Stat RE en o a 19 Figure 13 IPSTB Plattorm Block Diagra EE 20 Tables Table 1 Teridian Source File free 7 Table 2 ST OS 20 Configuration Source File Tree 7 Table 3 NEXGEN TCP IP Files for Hardware ChecKSUmM kakaa kakaa aaa kaaa 8 Table 4 Device Driver Configuration Options ii 11 Table S Driver Default Values for Important 78Q8430 Registers and Parameters 11 4 Rev 1 0 UM_843
6. H target net tap jei_ soc 138 198 185 138 tckdiv 8 board_runtime_ init HH david target net tap jei_soc 138 198 185 133 tckdiv 4 board_runtime_ init target usb tap hti_usb usb tckdiv 4 board_runtime_ init major target net tap jei_ soc 138 198 185 143 tckdiv 4 board_runtime_ init hl target jei108 tap jei_ soc 167 4 204 108 tckdiv 4 board_runtime_ init target jei112 tap jei_soc 167 4 204 112 tckdiv 4 board_runtime_ init target jei62 tap jei_soc 167 4 204 62 tckdiv 4 board_runtime_init target jei96 tap jei_soc 167 4 204 96 tckdiv 4 board_runtime_init target jei99 tap jei_soc 167 4 204 99 tckdiv 4 board_runtime_init target jei110 tap jei_ soc 167 4 204 110 tckdiv 4 board_runtime_ init target jei111 tap jei_ soc 167 4 204 111 tckdiv 4 board_runtime_ init target tp5100 tap jei_soc 192 168 1 30 tckdiv 4 board_runtime_ init Rev 1 0 21 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 5 1 4 STi5100 IPSTB Configuration The STi5100 configuration parameters are contained in the C jostba5 config board mb390_mem cfg file ST5100 FMI Bus Cycle Settings The FMI Bus cycle settings in the file are shown below He Bank 2 32MBytes Stem1 Configured as 16 bit peripheral He Parameters weuseoeconfig 0 waitpolarity 0 latchpoint 1 datadrivedelay 0 HH busreleasetime 2 csactive 3 oeactive 1 beactive 2 portsize 16 HH devicetype 1 HH cyclenotphaseread 1 accessti
7. IP Stack Table of Contents d Introduction nelle least 5 2 System Requirements Leila ici 6 2 1 Hardware Heouirements kaaa kaaa aaa kakaa naa 6 2 2 Software Requirements aaa aaa kaaa kaaa kaaa kakaa kaaa kaaa 6 3 Device Driver Structure ela ili a 7 Osi Device DEVerFiles asio esile ij elie A A O A fo laici 7 1 2 Pile Directory Structure srl 7 852 75 1W0S20 Header FIleS ses sob of ol dl tallo decia dans 8 E Data SUCESO 8 Beet NG FSC STRUC Tracara loan radio 8 2332 NETSEONIROE STRUCI WEE 9 333 DEV FUNCTONS che 9 3 3 4 DEVICE _CONTROL_ SA ei 9 3 4 Device Driver Options Ee 11 4 ST IPSTB NexGen 7808430 Ethernet API uuu ate ee 13 4 1 STETHER CopyDala E RE 13 4 2 OTE THER ClOSC arica oli cold 14 45 STETHER CONliG is A oasi 14 44 Se HER COMING ARO Dista A e oi ran 14 4 5 STETHER HandleCompletedTXBuffers 1 15 40 S TETHER InterrupiHlandler O EE 16 Gal cS VE WHER ODEN israeliana 17 40 O ME VME e A a ODI Od cid 18 49 SE MeN SENO Chit EE 18 io o A A 19 5 STI5IOC IPSTB Platform Example cella 20 9 1 SU 20 es EOS GE ENVIONMEN pela a aaa 20 5 1 2 MPEG Video Server PC Environment 21 5 1 3 ST Microconnect Target Contfguraton kakaa 21 Dil STI8100IPSTB Configuration ee e Ee EE Eed ecient 22 32 BUld STISTOJIPSTE CO ee ee e 23 IZ L calon Ol SOUICe EE EE Ee 23 522 Te WE e E EE 23 5 9 RUN Ane STS T00 PSTB BE xain ple ll Lellis 24 6 Related Documentaliona sa nile
8. SystemRoot system32 STEP 2 Modify the system variable ST20ROOT as follows ST20ROOT C STM ST20R2 0 5 STEP 3 Reboot the PC 20 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 5 1 2 MPEG Video Server PC Environment Use the following procedure to set up the video server PC STEP1 Set up the ST TSVOD server for unicast video streaming G 08430 ST_IPSTB_SW PBox servers TS_VOD_ Server STEP 2 Set up the ST Multicast server for multicast video streaming G Q8430 ST_IPSTB_SW IPBox servers Multicast STEP 3 Set the video server PC IP address to 192 168 1 110 STEP 4 Start the appropriate server before requesting a video stream 5 1 3 ST Microconnect Target Configuration The ST Microconnect Target Configuration IP addresses via Ethernet are as follows Host PC 192 168 1 100 ST Microconnect 192 168 1 30 Video Server PC 192 168 1 110 The target configuration parameters are contained in the C ipstbaS config platform targets cfg file The target configuration portion of this file is as follows Sample targets cfg file HH Format of ST20 targets line HH target Ipt1 tap jpi_ppi Ipt1 board_runtime_init target jei target tap jei_soc jei target name board_runtime_init HH E g target myjei tap jei_soc myjei tckdiv board_runtime_ init H target myjei2 tap jei_soc 10 1 1 1 tckdiv board_runtime_ init HH HH End of sample targets cfg HH Ic
9. for ST5100 OS 20 with NexGen TCP IP Stack 3 4 Device Driver Options Table 4 lists the configuration options for the device driver Table 5 lists the software default values for several important 78Q8430 registers and parameters used by the driver The file Commen h contains these default values To change the default values make the changes in Commem h and recompile the driver A discussion of these values and how they are chosen follows the table Table 4 Device Driver Configuration Options Option Name Settings Gesetten SSS DRIVER_MODE INTERRUPT_MODE 1 Choice of polling mode or interrupt driven POLLING MODE 2 Polling mode is used only for diagnostics TSC_CPU TSCCPU ST5100 3 Selects target CPU platform for the driver Table 5 Driver Default Values for Important 7808430 Registers and Parameters Driver Variable 78Q8430 Register Register Field Default Name Address eae MEM_LEAK_OPT_VALUE NA EAR_INT_DELAY_CNT IDCR 0x180 x1FFF _INT_DELAY_ 0 WM_INT_FREE_BLOCK WMVR 0x190 Interrupt WM_HR_FREE_BLOCK WM_PAUSE_FREE_BLOCK 1 MEM LEAK OPT VALUE memory leak detection optimal value The driver uses the MEM LEAK OPT VALUE parameter to detect a memory leak condition Several conditions must be considered when deciding what this value should be Theoretically subtracting the number of memory blocks used by the QUEs Nq from the total number of memory blocks available should equal the number of free blocks In p
10. internet streaming video application This section describes how to set up the platform build the driver and NexGen software and run an example which plays and stops an MPEG2 movie Figure 13 shows the components and connections for the STi5100 IPSTB platform Refer to the 78Q8430 STEM Demo Board User Manual for additional information on the hardware setup Cable Hol 00H Switch Hub ST20 ICE Ribbon Cable Development PC L TV pr_ m_ m Video Audio Cable gt Cat 5 Gable STi5100 Evaluation Platform with 7808430 STEM Demo Board Video Server Figure 13 IPSTB Platform Block Diagram 5 1 Setup The path names in talics given in the following steps are for illustrative purposes If the software has been installed in different directories than those given below replace the path in the example with the appropriate path for your installation 5 1 1 Host PC Environment Changes to the PC environment are needed when using the STi5100 platform or when changing between the STi5100 and STi5514 platforms The STi5514 platform uses the old ST20R 1 9 6 tool set while the STi5100 platform uses the newer ST20R2 0 5 tool set Use the following procedure to modify the environment STEP 1 Modify the Windows Environment to use the ST20R2 0 5 tool set Append C STM ST20R2 0 5 bin to the front of the system variable Path As an example the new path might be C STMST20R2 0 5 bin C S7TMST20R1 9 6 bin
11. the status for the completed transmissions if statistics collection is active On exit it checks for any additional pending transmissions and if found invokes STETHER_ Send to fulfill the TX request Parameters netp network interface type NGethifnet_tsc Returns Number of TX packets processed Rev 1 0 15 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 STETHER_HandleCompletedT XBuffers a a STETHER Send p tscReadReg_BUS16 tscWriteReg_BUS16 Figure 7 STETHER_HandleCompletedTXBuffers Call Graph 4 6 STETHER_InterruptHandler Prototype void STETHER_InterruptHandler NGifnet netp Description This function is the interrupt handler wrapper It handles TX RX and error interrupts derived from tsclsr and tscDpr The function begins by isolating the interrupt source and then clearing the interrupt s If statistics are being collected it updates the interrupt related portion Based on its interrogation of the interrupt source it may call STETHER_HandleCompletedTxBuffers Parameters netp network interface type NGethifnet_tsc Returns none tscDelay tsc_PhyRead sk tscReadReg_BUS16 tscWriteReg_BUS16 Sa tscReadReg16 TL tsc TaskLock ad tscSwReset pe tscMacCtrlWrite gt tscTaskUnlock Figure 8 STETHER_InterruptHandler Call Graph STETHER_InterruptHa
12. 0 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 1 Introduction The Teridian Semiconductor Corporation TSC 78Q8430 is a single chip 10 100 Ethernet MAC and PHY controller supporting multi media offload The device is optimized to enhance throughput and offload network protocol tasks from the host processor for demanding multi media applications found in Set Top Boxes IP video and Broadband Media Appliances This document describes the 78Q8430 software device driver for ST OS 20 The document is based on the following driver software version gt SW Revision TSC8430B_V1 01 03 07 2008 A 7808430 Demo Board D8430T3B_ STEM is available to support development of embedded applications in conjunction with an ST STi5100 IPSTB development platform and ST ST20R2 0 5 SW tools The 78Q8430 ST OS 20 device driver includes the operating system OS and platform independent files and the OS and platform CPU board dependent files The ST OS 20 device driver uses a specific configuration of the OS and platform which is dependent on the generic Teridian Ethernet device driver This driver runs on the STi5100 IPSTB hardware platform with the NexGen TCP IP protocol stack for IP video streaming demo application software Rev 1 0 9 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 2 System Requirements 2 1 Hardware Requirements The following list describes the minimum hardware requirements for a 78Q843
13. 0 ST OS 20 based development platform e 78Q8430 demo board D8430T3B STEM e Software development PC with the following minimum requirements Pentium 4 CPU with 256 MB RAM and 40 GB hard drive running either Windows 2000 or Windows XP e IP Server PC with the following minimum requirements Pentium 4 CPU with 256 MB RAM and 40 GB hard drive 10 100 ports for 78Q8430 demo board connection running either Windows 2000 or Windows XP e 10 100 HUB or switch e STi5100 evaluation platform The STi5100 communicates with the 78Q8430 registers at base memory address 0x43038000 e ST Microconnect JTAG emulator This device loads the IPSTB software into the STi5100 evaluation platform 2 2 Software Requirements The following list describes the minimum software requirements for embedded applications programming on a 78Q8430 ST OS 20 based development platform e 120 Toolset STi5100 BSP Version 2 0 5 Patch 1 e IPBox contains web server htdocs and video_server folders e PSTB application Ipstba3_esp 5100 6 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 3 Device Driver Structure This 78Q8430 ST OS 20 device driver software is a customized version of the generic Teridian Ethernet device driver software It is configured with wrapper code for the NexGen TCP IP protocol stack and other protocols RTSP RTP to stream the MPEG 2 transport stream The wrapper code connects the generic
14. ANK2_DATA1 0x89111100 9 cycle Read CSE1 CSE2 OEE1 OEE2 1 poke d STI5100_FMI_BANK2_DATA2 0x89111100 9 cycle Write CSE1 CSE2 OEE1 OEE2 1 poke d STI5100_FMI_BANK2_DATAO 0x04100691 LATCHPT 1 BUSRELEASE 1 CS OE active R amp W poke d STI5100_FMI_BANK2_DATA1 0x88020202 7 cycle Read CSE1 OEE1 1 CSE2 OEE2 2 poke d STI5100_FMI_BANK2_DATA2 0x88020202 7 cycle Write CSE1 OEE1 1 CSE2 OEE2 2 poke d STI5100_FMI_BANK2_DATA3 0x00000000 22 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack ST5100 FMI Clock Rate Settings The FMI clock rate settings in the file are shown below TTPMOD TSC modified settings sdram refresh bank 5 flash runs 1 2 bus clk sdram runs bus clk poke d STI5100_FMI_GEN_CFG 0x00000000 poke d STI5100_FMI_ FLASH CLK SEL 0x00000001 1 2 ST bus clock 50 4MHz poke d STI5100_FMI_FLASH CLK SEL 0x00000002 1 3 ST bus clock 36MHz poke d STI5100_FMI_ FLASH CLK SEL 0x00000000 1 1 ST bus clock 100 8MHz poke d STI5100_FMI_CLK_ ENABLE 0x00000001 5 2 Build STi5100 IPSTB Code 5 2 1 Location of Source Files The relevant TSC and NexGen source files required to build and run the STi5100 video streaming application example are listed below The NexGen files include modifications to support the hardware checksum TSC Source Files e Directory path C jostbad src nexgen_drv o ether_tsc 8q8430 c Wrapper file which include T
15. TCP IP Stack Appendix B Release Notes Release Notes for the 78Q8430 ST OS 20 Driver Version 1 01 date 03 07 2008 The driver includes the following default settings e Strip CRC is on e Append CRC in Tx packet is on the NexGen stack is customized for this e Jumbo packet support is off Release Package Contents The software release includes the following components e 78Q8430 Software User Guide for ST OS 20 this document e 7808430 ST OS 20 Driver source code 78Q8430_Drv_V1 01 zip The readme file has how to instructions to compile and build the 7808430 device drivers e ST Video Demo software integrated with the 78Q8430 driver ipstba5 zip e Video server with demo videos IPbox zip Contains the video server installation files and videos Software Build and Installation Make configuration changes as needed in the tscport h and commem h files In the ST video demo these files are in C ipstba5 include Follow the procedures in Section 5 2 2 to build and install the STi5100 IPSTB software Changes from Previous Release None first release Known Problems None Rev 1 0 21 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 Revision History Revision Date Deseripion O 3 28 2008 First publication 28 Rev 1 0
16. device driver API to the NexGen TCP IP stack 3 1 Device Driver Files 3 1 1 File Partitions The device driver software includes 4 groups of files e OS and platform independent files o tsccore c o commem h o comregs h e TSC OS and platform dependent files o tscport c o tscport h o optional wrapper files ether_tsc78q8430 c ether_tsc78q8430 h Target OS and platform dependent files o targets cfg o mb390_mem cfg e Modified TCP IP protocol stack files o Ipncs c o tcpncs c o udpncs c 3 1 2 File Directory Structure Table 1 Table 2 and Table 3 list the directory and file structure for the 7808430 driver software and a brief description of each file Table 1 Teridian Source File Tree Directory Path FileName File Description ff Cipstbas src nexgen_drv CaipstbaSiinclude Table 2 ST OS 20 Configuration Source File Tree Directory Path FileName File Description C ipstba5 config platform targets cfg IPSTB Target configuration mb390_mem cfg FMI bus configuration for 7808430 registers and SRAM 7 Rev 1 0 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 Table 3 NEXGEN TCP IP Files for Hardware Checksum Directory Path FileName File Description C ipstba5 src nexgen_drv ipncs c ip c Add IP checksum HW SW option udpncs c udp c Add UDP checksum HW SW option tcpncs c tcp c Add TCP checksum HW SW option 3 2 ST OS 20 Header Files The 78Q8430 device driv
17. er software requires the following ST OS 20 header files to be included include lt task h gt include lt stdio h gt include lt stdlib h gt include lt message h gt include lt string h gt include lt heap h gt include lt cache h gt include lt debug h gt include lt interrup h gt include lt ostime h gt include lt c1timer h gt include lt time h gt include lt semaphor h gt include lt debug h gt include stddefs h include commem h include comregs h 3 3 Data Structures The 78Q8430 device driver for ST OS 20 interfaces to the NexGen TCP IP stack with the structures described below 3 3 1 NG TSC STRUCT NG TSC _ STRUCT and DEVICE CONTROL_STRUCT structures are defined in the TSC Ethernet source module commem h Figure 1 shows the call graph for the NG_ TSC STRUCT structure DEVICE_CONTROL_STRUCT A NG TSC STRUCT Figure 1 NG_TSC_STRUCT Call Graph 8 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 3 3 2 NET CONTROL_STRUCT The NET CONTROL_STRUCT structure is defined in the TSC Ethernet source module commem h Figure 2 shows the call graph for the NET CONTROL_STRUCT structure DEVICE CONTROL_STRUCT A device_struct x NET_CONTROL_STRUCT inext_ctrl A 5 lt d ptscLoad device_functions AS DEV FUNCTIONS STRUCT Figure 2 NET CONTROL_STRUCT and DEV_FUNCTIONS STRUCT Call Graph
18. eridian source files o tsccore c Core code o tscport c OS and H W dependent code o tsctest c Test application code e Directory path C jpstbad include o ether_tsc 8q8430 h Wrapper file which include Teridian header files o tscport h OS and H W dependent headers o commem h Common memory data structure declaration o comregs h Register declaration NexGen Files with Hardware Checksum e Directory path C jostbad src nexgen_drv o Ipncs c Enable HW checksum usage in IP files o Uudpncs c Enable HW checksum usage in UDP files o tcpncs c Enable HW checksum usage in TCP files 5 2 2 Build the Software Use the following procedure to build the software STEP 1 Use Windows File Manager to open a window STEP 2 Select the directory C ipstba5 STEP 3 Double click to execute the ipstb_setup link A blue DOS window will appear displaying Using 5100ref root c ipstba5 c iostbaS src ref_ipstb gt STEP 4 Make the new Ethernet device driver and NexGen code create nexgen_drv lib Change to directory C ipstba5 src nexgen_drv gmake clean gmake Rev 1 0 23 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 STEP 5 Make the new code for a complete IPSTB image create ref_ipstb Iku Change to directory C ipstba5 src ref_ipstb gmake clean gmake 5 3 Run the STi5100 IPSTB Example Use the following procedure to execute the IPSTB ref_ipstb Iku application to request an MPEG2 movie from the serve
19. meread 1d cse1timeread 2 HH cse2timeread 0 oee1timeread 0 oee2timeread O bee1timeread 0 HH bee2timeread 0 HH cyclenotphasewrite 1 accesstimewrite 1d cse1timewrite 2 HH cse2timewrite 2 oee1timewrite 0 oee2timewrite O bee1timewrite 0 HH bee2timewrite 0 HH strobeonfalling O burstsize O datalatency O dataholddelay O HH burstmode 0 poke d STI5100_FMI_BANK2_DATAO poke d STI5100_FMI_BANK2_DATA1 poke d STI5100_FMI_BANK2_DATA2 poke d STI5100_FMI_BANK2_DATA3 0x001016D1 BE not active during rd 0x9d200000 0x9d220000 0x00000000 Na a LEE ST IPSTB original settings poke d STI5100_ FMI BANK2 _DATAO 0x041086e9 poke d STI5100_ FMI BANK2 _DATA1 0x0e024400 poke d STI5100_ FMI BANK2 _DATA2 0x0e024400 poke d STI5100_ FMI BANK2_DATA3 0x00000000 TTPMOD TSC modified settings Won t work with 7 cycles poke d STI5100_FMI_BANK2_DATA1 0x87111100 7 cycle Read CSE1 CSE2 0EE1 0EE2 1 poke d STI5100_FMI_BANK2_DATA2 0x87111100 7 cycle Write CSE1 CSE2 OEE1 OEE2 1 The following timings work poke d STI5100_FMI_BANK2_DATA1 0x8C111100 12 cycle Read CSE1 CSE2 0EE1 0EE2 1 poke d STI5100_FMI_BANK2_DATA2 0x8C111100 12 cycle Write CSE1 CSE2 OEE1 OEE2 1 poke d STIS100_FMI_BANK2_DATA1 0x8A111100 10 cycle Read CSE1 CSE2 0EE1 0EE2 1 poke d STI5100_ FMI BANK2_DATA2 0x8A111100 10 cycle Write CSE1 CSE2 OEE1 OEE2 1 poke d STIS100_FMI_B
20. miconductor products or to check the availability of the 78Q8430 contact us at 6440 Oak Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email lan support teridian com For a complete list of worldwide sales offices go to http www teridian com Rev 1 0 25 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430_005 Appendix A Acronyms API Fast Ethernet FTP HTTP IP MAC PC PHY RAM RMON ROM RTCP RTP RTSP STB TCP TCP IP TELNET TSC UDP URL 26 Application Program Interface 100Mbps Ethernet LAN as defined by IEEE 802 3u File Transfer Protocol RFC4823 Hyper Text Transport Protocol RFC2854 Internet Protocol RFC1112 also RFC0894 Media Access Control IEEE 802 3 Personal Computer Physical Random Access Memory Remote monitoring MIBS belong to SNMP protocol family Read Only Memory Real time Transport Control Protocol RFC4571 Real time Transport Protocol RFC4598 Real Time Streaming Protocol RFC2326 Set Top Box IP Cable Terrestrial Satellite Transport Control Protocol RFC3168 also RFCO793 TCP over IP protocols which is the core protocol for internet communications Network Virtual Terminal Protocol for terminal emulation RFC0855 TERIDIAN Semiconductor Corporation User Datagram Protocol RFC0768 Uniform Resource Locator RFC1738 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen
21. ndler 16 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 4 7 STETHER Open Prototype int STETHER_Open NGifnet netp Description Driver initialization begins with this function It initializes the default configuration in the device control structure It calls tscDevicelnit to set up the hardware with the default configuration Parameters netp network interface type NGethifnet_tsc Returns NULL if OK err Error code in case of error STETHER_CopyData tscDisablelntr tscWriteReg_ BUS16 tscEnablelntr esst STETHER_InterruptHandler ee STETHER_Config ARC STETHER_Open tscStructInit tscReadReg_BUS16 tscDevicelnit tscPhyStatus Figure 9 STETHER_Open Call Graph First Level Rev 1 0 17 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 4 8 STETHER_Receive Prototype void STETHER_Receive NGifnet netp Description This routine checks for valid RX frames and copies their data from the 7808430 buffers into the system buffers Parameters netp network interface type NGethifnet_tsc Returns none STETHER_Receive m tscReadReg BUS16 oe tscWriteReg_BUS16 Figure 10 STETHER_Receive Call Graph
22. ption Copies data from the 78Q8430 to NexGen buffers in a task The function does a serialized call to STETHER_ receive Parameters netp network interface type NGethifnet_tsc Returns none mt at A STETHER Receive tscReadReg_BUS16 STETHER_CopyData A tscWriteReg BUS16 Figure 4 STETHER_CopyData Call Graph Rev 1 0 13 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 4 2 STETHER Close Prototype int STETHER_Close NGifnet netp Description Driver cleanup and Ethernet controller shutdown are handled by this function It stops the driver deletes the task and serialization unloads the driver and de queues and frees any pending buffers Parameters netp network interface type NGethifnet_tsc Returns NG_EOK if OK NG EALREADY Error if interface is not up tscStop tscWriteReg_BUS16 STETHER_Close ei A tscUnload _ tscDelay Figure 5 STETHER Close Call Graph 4 3 STETHER_Config Prototype void STETHER_ Config U32 Eth_BaseAddr U8 Addr_Shift U8 Tsc_Interrupt U8 Int_Level U8 Use16Bit U8 Trans_Len Description This routine configures the 78Q8430 interface It records the input parameters in globally available variables for use by the driver Parameters Eth _BaseAddr 78Q8430 base address Addr_ Shift address shift
23. r STEP 1 From the Windows Start menu select and execute st20dev the ST20R2 0 5 tool set STEP 2 Select File Open Workspace gt C lipstbad ref_ipstb stw STEP 3 Make sure the ST Microconnect and STi5100 box are powered up STEP 4 Select Build Start Debug Go STEP 5 Select Debug Go A second DOS window will appear displaying the Testtool prompt Testtool gt STEP 6 Request an MPEG2 movie from the server by entering the following command PlayManager_Play rtsp 192 168 1 110 554 song vidpid 34 amp audpid 33 amp Bitrate 1400 STEP 7 Stop the movie using the following command PlayManager_Stop The text file C jostba5 Play_Commands txt contains ready made commands with correct parameters to play various MPEG2 streams Refer to the ST IPSTB user guide for more information on the PlayManager and IPSTB software 24 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 6 Related Documentation The following 78Q8430 documents are available from Teridian Semiconductor Corporation 78Q8430 Preliminary Data Sheet 78Q8430 Layout Guidelines 78Q8430 Software Driver Development Guidelines 7808430 Driver Manual for ST 5100 OS 20 with NexGen TCP IP Stack 78Q8430 STEM Demo Board User Manual 78Q8430 Driver Manual for ARM920T Linux 78Q8430 Embest Evaluation Board User Manual 7 Contact Information For more information about Teridian Se
24. ractice this may not be exactly true due to the fact that a dynamic QUE may hold one memory block in reserve Additionally one or more memory blocks may be allocated or de allocated between the time the number of free blocks are read and the time it takes to complete the calculation Given that there are 127 total memory blocks available and Nf is the number of currently free memory blocks the number of unaccounted memory blocks Na can be found from the following equation Na 127 Nq Nf If Na is greater than MEM LEAK OPT_VALUE it is an indication that there are some memory leaks and the driver issues a software reset 2 EAR INT DELAY CNT delay in the interrupt if early interrupt is used The early receive interrupt has a delay timer feature This feature is intended to leverage the deep receive buffer to decrease interrupt handling overhead in the host Normally the early receive interrupt is triggered as soon as any data for a received frame is placed into the receive QUE The receive interrupt delay timer delays this interrupt for a programmable amount of time to allow the receive QUE to accumulate more data In this way under conditions of heavy load several frames can be serviced by a single receive interrupt The interrupt timer is linked to the PHY speed such that the timer value is measured in byte times or in other words a single tick on the interrupt delay timer is equal to the amount of time it would take the PHY to
25. receive a single byte The timer does not require that an actual byte be received so the interrupt delay feature will not cause small frames to be left in the QUE while waiting for more data Anytime data is Rev 1 0 11 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack UM_8430 005 added to the receive QUE and the interrupt delay timer is enabled the timer is started if it is not already running If the interrupt delay timer is already running when data is added to the receive QUE the running timer is not affected When a BLOCK is removed from the receive QUE the interrupt delay timer is reset This means that the driver must completely empty the receive QUE each time it services the delay timer interrupt or risk stranding data in the QUE 3 WM_INT_FREE BLOCK Watermark interrupt value The watermark values are set based on the minimum number of free memory blocks that must be available to avoid the specified action In the case of the interrupt watermark the specified action is an interrupt The value of the interrupt watermark should be set low enough that it is not triggered under ordinary circumstances as this would increase the interrupt service load of the system The interrupt water mark should also be set high enough that the interrupt is triggered while there is still enough free memory to keep the system moving long enough to take action and avoid data loss due to a lack of memory 4 WM_HR_FREE_BLOCK Headroom Waterma
26. rk The Headroom watermark specifies the number of free memory BLOCKS below which the MAC receiver is halted This effectively reserves some blocks of memory for MAC transmit The default value for the Headroom watermark is 0x04 This allows the MAC transmit to have at least 4 blocks of memory to send a packet 5 WM PAUSE FREE BLOCK Free blocks before sending pause The PAUSE watermark specifies the minimum number of free memory BLOCKS that triggers the automatic transmission of the PAUSE frame 12 Rev 1 0 UM_8430 005 78Q8430 Driver Manual for ST5100 OS 20 with NexGen TCP IP Stack 4 STIPSTB NexGen 78Q8430 Ethernet API This section shows an example of the specific integration of the 78Q8430 device driver in the STi5100 IPSTB reference design The simple NexGen interface code contained in the ether_tsc78q8430 c and ether_tsc78q8430 h files connects the device driver to the NexGen TCP IP protocol stack The API described below is defined in the TSC driver source modules tscport h and tscport c The API consists of the following functions e STETHER_CopyData e STETHER_Config e STETHER_Config_ARC e STETHER HandleCompletedTXBuffers e STETHER_InterruptHandler e STETHER_Open e STETHER_Receive e STETHER_Send e STETHER_ Start Note The STi5100 communicates with the 78Q8430 registers at base memory address 0x43038000 4 1 STETHER_CopyData Prototype void STETHER_CopyData NGifnet netp Descri
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