TPA3122D2N Datasheet
Contents
1. 1 kHz 48 dB Vcc 12 V RL 40 f 1 kHz 4 Output Power at 1 THD N Po Voc 24 V RL 8 Q f 1 kHz 8 Output Power at 10 Voc 12 V RL 4 Q f 1 kHz 5 THD N Voc 24 V RL 8 Q f 1 kHz 10 THD N Total harmonic distortion 4 O f 1 kHz Po 1 W 0 1 noise Ri 8 Q f 1 kHz Po 1 W 0 06 85 uV Vn Output integrated noise floor 20 Hz to 22 kHz A weighted filter Gain 20 dB 240 dB Crosstalk Po 1 W f 1kHz Gain 20 dB 60 dB SNR Signal to noise ratio Max Output at THD N lt 1 f 1 kHz Gain 20 dB 99 dB Thermal trip point 150 C Thermal hysteresis 30 G fosc Oscillator frequency 10 V x Vec 230 250 270 kHz mute delay time from mute input switches high until outputs muted 120 msec unmute delay time from mute input switches low until outputs unmuted 120 msec 4 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 3 TEXAS INSTRUMENTS TPA3122D2 www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 FUNCTIONAL BLOCK DIAGRAM lt gt BSL AVCC PVCCL REGULATOR 4 52. BSN and BSP Capacitors The half H bridge output stages use only NMOS transistors Therefore they require bootstrap capacitors for the high side of each output to turn on correctly A 220 nF ceramic capacitor rated for at least 25 V must be connected from each output to its corresponding bootstrap input Specifically one 220 nF capacitor must be connected from LOUT to BSL and one 220 nF capacitor must be connected from ROUT to BSR The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power supply for the high side N channel power MOSFET gate drive circuitry During each high side switching cycle the bootstrap capacitors hold the gate to source voltage high enough to keep the high side MOSFETs turned on VCLAMP Capacitor To ensure that the maximum gate to source voltage for the NMOS output transistors is not exceeded one internal regulator clamps the gate voltage One 1 uF capacitor must be connected from VCLAMP pin 11 for PWP and pin 9 for DIP package to ground and must be rated for at least 16 V The voltages at the VCLAMP terminal may vary with Vcc and may not be used for powering any other circuitry Vgyp Capacitor Selection The scaled supply reference Vpyp nominally provides an AVcc 8 internal bias for the preamplifier stages The external capacitor for this reference is a critical component and serves several important functions During start up or recovery from shutdo
3. GAINO GAIN1 Vi Vcc 24 125 SD Vj 0 Vcc 30 V 1 lit Low level input current MUTE 0 V Voc 30 V 1 GAINO 0 V Vcc 24 V 1 TA Operating free air temperature 40 85 C Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 Submit Documentation Feedback 35 TEXAS TPA3122D2 INSTRUMENTS www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 DC CHARACTERISTICS 25 C Voc 24 V R 40 unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT Class D output offset voltage Vos measured differentially 1 BIN Bypass output voltage No load 8 V loci Quiescent supply current SD 2 V MUTE 0 V No load 23 37 mA lcc a Quiescent supply current in mute mode MUTE 2 V No load 23 mA lcc a 2 supply current in shutdown SD 0 8 V No load 0 39 1 mA DS on Drain source on state resistance 200 mQ Gain0 0 8 V 18 20 22 Gain1 0 8 V Gain0 2 V 24 26 28 G Gain dB Gain0 0 8 V 30 32 34 Gain1 2 V Gain0 2 V 34 36 38 Mute Attenuation Vi 1Vrms 82 AC CHARACTERISTICS 25 C Voc 24V R 40 unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ksvn Supply ripple rejection ripple 200 22
4. E LOUT VCLAMP EE LS AVDD ci AVDD PGNDL LIN C AAN 17 5 verre rs gt AVDD 2 DETECT AGND SD CONTROL n 5 VCLAMP THERMAL MUTE MUTE CONTROL NC LTE OSC RAMP BYPASS BYPASS GAIN1 AV CONTROL GAINO SC DETECT BSR PVCCR M HS ROUT gt vaar H LS e PGNDR AVDD ni AVDD lt gt D ANN AVDD 2 Copyright 2007 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link s TPA3122D2 35 TEXAS TPA3122D2 INSTRUMENTS www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY SE FREQUENCY SE 10 10 Gain 20 dB Gain 20 dB Rt 4 SE Rt 4 SE 12V Voc 18 o 1 o 1 z a a 0 1 0 1 0 01 0 01 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz Gani f Frequency Hz CODD Figure 1 Figure 2 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY SE FREQUENCY SE 10 Gain 20 dB Gain 20 dB RL 40 SE Rt 8 Q SE Voc 24 V Voc 24 V o o 1 2 I I z a a I Po 1W 0 01 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz G003 f Frequency Hz enor Figure 3 Figure 4 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION
5. for Pkg Type RoHS The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tis terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise con
6. A MAX A MIN MS 001 VARIATION 0 020 MIN 0 015 0 38 MAX 00 5 08 Cau x ge Plane L Seating Plane 125 3 18 MIN gt 4 0 010 0 25 NOM u 0 430 10 92 MAX 7 0 51 0 2 1 0 015 0 38 0 010 0 25 4 14 18 20 Pin vendor option A 4040049 E 12 2002 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice Falls within JEDEC 5 001 except 18 and 20 pin minimum body length Dim The 20 pin end lead shoulder width is a vendor option either half or full width bp o gt 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality contr
7. NOISE vs vs OUTPUT POWER SE OUTPUT POWER SE 10 10 Gain 20 dB Gain 20 dB RL 4 Q SE RL 8 Q SE 5 1 1 2 I I z a a E 0 1 0 1 0 01 0 01 0 01 0 1 1 10 40 0 01 0 1 1 10 40 Po Output Power W GE Po Output Power W Us Figure 5 Figure 6 6 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 9 TEXAS INSTRUMENTS www ti com CROSSTALK vs FREQUENCY SE 0 Gain 20 dB 0 25 W 20 4 Q SE Vcc 18V Crosstalk dB 20 100 1k 10k 20k f Frequency Hz E Figure 7 GAIN PHASE vs FREQUENCY SE 400 lt 200 m I 72 1 o S a 9 0 Gain 20dB 22uH 0 125W 0 68 pF t RL 4Q SE 470 uF Vcc 24 V 1 200 100 1 10 100 f Frequency Hz 9 OUTPUT POWER 5 SUPPLY VOLTAGE SE Gain 20 dB 4Q SE Po Output Power W THD N 1 0 10 12 14 16 18 20 PVcc Supply Voltage V m NOTE Dashed line Thermally limited Figure 11 Copyright 2007 Texas Instruments Incorporated Gain dBr A Crosstalk dB Po Output Power W TPA3122D2 SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS con
8. e Signal generator e Power resistor s e Linear regulated power supply e Filter components e EVM or other complete audio circuit Figure 30 shows the block diagrams of basic measurement systems for class AB and class D amplifiers A sine wave is normally used as the input signal because it consists of the fundamental frequency only no other harmonics are present An analyzer is then connected to the APA output to measure the voltage output The analyzer must be capable of measuring the entire audio bandwidth A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins A System Two audio measurement system AP II Reference 1 by Audio Precision includes the signal generator and analyzer in one package The generator output and amplifier input must be ac coupled However the EVMs already have the ac coupling capacitors CiN so no additional coupling is required The generator output impedance should be low to avoid attenuating the test signal and is important because the input resistance of APAs is not high Conversely the analyzer input impedance should be high The output resistance Rour of the APA is normally in the hundreds of milliohms and can be ignored for all but the power related calculations Figure 30 a shows a class AB amplifier system It takes an analog signal input and produces an analog signal output This amplifier circuit can be directly connected to the
9. 35 TEXAS INSTRUMENTS www ti com TPA3122D2 SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 15 W STEREO CLASS D AUDIO POWER AMPLIFIER FEATURES e 10 W ch into an 4 O Load From a 17 V Supply e 15 W ch into an 8 O Load From a 28 V Supply Operates from 10 V to 30 V Efficient Class D Operation Four Selectable Fixed Gain Settings e Internal Oscillator No External Components Required Single Ended Analog Inputs Thermal and Short Circuit Protection with Auto Recovery Feature e 20 pin DIP Package APPLICATIONS e Televisions DESCRIPTION The TPA3122D2 is a 15 W per channel efficient Class D audio power amplifier for driving stereo single ended speakers or mono bridge tied load The TPA3122D2 can drive stereo speakers as low as 40 The efficiency of the TPA3122D2 eliminates the need for an external heat sink when playing music The gain of the amplifier is controlled by two gain select pins The gain selections are 20 26 32 and 36 dB SIMPLIFIED APPLICATION CIRCUIT 1 uF Left Channel Eb 3 Right Channel j 1 1 BYPASS AGND 10 30 v P Shutdown Control Mute Control gt TPA3122D2 0 22 uF 22H 470 L C 0 68 0 68 gt lt SZ C 22uH 470 0 22 uF QM 10 v to 30v 4 1 uF 4 Step Gain Control Please be aware that an important notice concerning avail
10. high outputs switch at 5096 duty cycle low outputs enabled TTL logic levels with compliance to AVCC BSL 18 Bootstrap I O for left channel PVCCL 1 Power supply for left channel H bridge not internally connected to PVCCR or AVCC LOUT 19 Class D H bridge positive output for left channel PGNDL 20 Power ground for left channel H bridge VCLAMP 9 Internally generated voltage supply for bootstrap capacitors BSR 13 VO Bootstrap I O for right channel ROUT 12 Class D H bridge negative output for right channel PGNDR 11 Power ground for right channel H bridge PVCCR 10 Power supply for right channel H bridge not connected to PVCCL or AVCC AGND 8 Analog ground for digital analog cells in core AGND 7 Analog Ground for analog cells in core BYPASS 6 o 2 inputs Nominally equal to AVCC 8 Also controls start up time via AVCC 16 17 High voltage analog power supply Not internally connected to PVCCR or PVCCL 2 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 TEXAS INSTRUMENTS ABSOLUTE MAXIMUM RATINGS www ti com over operating free air temperature range unless otherwise noted TPA3122D2 SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 VALUE UNIT Voc Supply voltage AVCC PVCC 0 3 to 36 V Vi Logic input voltage SD MUTE GAINO GAIN1 0 3 to Voc 0 3 0 3 to Vcc 0 3 V ViN Analog input
11. capacitors should be grounded to power ground For an example layout see the TPA3122D2 Evaluation Module TPA3122D2bEVM User Manual SLOU214 Both the EVM user manual and the thermal pad application note are available on the TI Web site at http www ti com 22uH rn e J Shutdown Control Mute Control Left Input Right Input 1 0uF AJ LEFT OUT 4 7K 1 0uF 122 PDIP ou I 1 0uF 470uF 470uF 0 1uF 10uF t 4 lt Figure 28 SE 4 Application Schematic 14 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 9 TEXAS INSTRUMENTS TPA3122D2 www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 vec A Shutdown Control 4 0 1 Mute Control 0 PVCCL PGNDL 1 0uF EV 19 Plus Input 50 LOUT Ee Minus Input 1 0uF 1 0uF n acz zeg v o 0 22uF TPA3122 PDIP O 1uF 11 1 0 470uF 470uF e 7 Figure 29 BTL 8 O Application Schematic 0 1uF 10uF BASIC MEASUREMENT SYSTEM This application note focuses on methods that use the basic equipment listed below e Audio analyzer or spectrum analyzer Digital multimeter DMM e Oscilloscope Twisted pair wires
12. driving a load through an output ac coupling capacitor and the other end of the load is tied to ground SE inputs and outputs are considered to be unbalanced meaning one end is tied to ground and the other to an amplifier input output The generator should have unbalanced outputs and the signal should be referenced to the generator ground for best results Unbalanced or balanced outputs can be used when floating but they may create a ground loop that will effect the measurement accuracy The analyzer should have balanced inputs to cancel out any common mode noise in the measurement Twisted Pair Wire Twisted Pair Wire Figure 31 SE Input SE Output Measurement Circuit The following general rules should be followed when connecting to APAs with SE inputs and outputs Use an unbalanced source to supply the input signal Use an analyzer with balanced inputs e Use twisted pair wire for all connections e Use shielding when the system environment is noisy e Ensure the cables from the power supply to the APA and from the APA to the load can handle the large currents see Table 4 Copyright 2007 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link s TPA3122D2 35 TEXAS TPA3122D2 INSTRUMENTS www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 DIFFERENTIAL INPUT AND BTL OUTPUT TPA3122D2 Mono Configuration Many of the class D APAs and many class AB APAs have dif
13. is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically desi
14. or other analyzer input This is not true of the class D amplifier system shown in Figure 30 b which requires low pass filters in most cases in order to measure the audio output waveforms This is because it takes an analog input signal and converts it into a pulse width modulated PWM output signal that is not accurately processed by some analyzers Copyright 2007 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link s TPA3122D2 TPA3122D2 SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 Power Supply Signal Generator Power Supply e Signal Class D APA Crit R Generator d L b Traditional Class D Figure 30 Audio Measurement Systems Ji TEXAS INSTRUMENTS www ti com Analyzer 20 Hz 20 kHz Analyzer 20 Hz 20 kHz 16 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 35 TEXAS INSTRUMENTS TPA3122D2 www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 SE Input and SE Output TPA3122D2 Stereo Configuration The SE input and output configuration is used with class AB amplifiers A block diagram of a fully SE measurement circuit is shown in Figure 31 SE inputs normally have one input pin per channel In some cases two pins are present one is the signal and the other is ground SE outputs have one pin
15. shifts in the actual resistance of the input resistors 10 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 9 TEXAS INSTRUMENTS TPA3122D2 www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 For design purposes the input network discussed in the next section should be designed assuming an input impedance of 8 which is the absolute minimum input impedance of the TPA3122D2 At the higher gain settings the input impedance could increase as high as 72 kO Table 1 Gain Setting AMPLIFIER GAIN dB INPUT IMPEDANCE GAIN1 GAINO TYPICAL TYPICAL 0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9 INPUT RESISTANCE Changing the gain setting can vary the input resistance of the amplifier from its smallest value 10 20 to the largest value 60 20 As a result if a single capacitor is used in the input high pass filter the 3 dB or cutoff frequency may change when changing gain steps In IN put Signal The 3 dB frequency can be calculated using Equation 1 Use the Z values given in Table 1 27 Z C 1 INPUT CAPACITOR C In the typical application an input capacitor is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation In this case C and the input impedance of the amplifier Zi form a high pass filter with the corner fre
16. voltage RIN LIN 0 3 to 7 V Continuous total power dissipation See Dissipation Rating Table TA Operating free air temperature range 40 to 85 C Ty Operating junction temperature range 40 to 150 C Tstg Storage temperature range 65 to 150 C R Load resistance Minimum value 3 2 kV Human body model all pins 2 kV ESD Electrostatic Discharge 3 Charged device model all pins 500 V 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability DISSIPATION RATINGS PACKAGE TA lt 25 DERATING FACTOR TA 70 85 20 pin DIP 1 87 W 15 mW C 1 20 W 0 97 W 1 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at www ti com RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Voc Supply voltage PVCC AVCC 10 30 V High level input voltage SD MUTE GAINO GAIN1 2 V Vi Low level input voltage SD MUTE GAINO GAIN1 0 8 V SD Vi Voc Vec 30 V 125 High level input current MUTE Voc Voc 30 V 125
17. 12V 1 0 0 8 0 6 0 4 0 2 0 0 0 2 4 6 8 10 12 14 Po Total Output Power W Figure 15 G015 POWER SUPPLY REJECTION RATIO vs FREQUENCY SE Gain 20 dB RL 40 SE Vcc 12 V Vripple 200 20 100 1k f Frequency Hz Figure 17 Submit Documentation Feedback 10k 20k 9017 INSTRUMENTS www ti com EFFICIENCY vs OUTPUT POWER SE 100 80 al I 60 2 40 20 0 Output Power W Gon Figure 14 SUPPLY CURRENT vs TOTAL OUTPUT POWER SE Gain 20 dB Ri 8 Q SE lt 1 5 gt 8 V2 1 o 2 0 2 4 6 8 10 12 14 Po Total Output Power W 16 TOTAL HARMONIC DISTORTION NOISE vs FREQUENCY BTL 10 Gain 20 dB 8 Q BTL 1 Vcc 24 V 5 1 Z 04 T 0 01 0 001 20 100 1k 10k 20k f Frequency Hz GS Figure 18 Copyright O 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 TEXAS INSTRUMENTS www ti com TPA3122D2 SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS continued TOTAL HARMONIC DISTORTION NOISE vs OUTPUT POWER BTL Gain 20 dB 8 Q BTL Ds 2 0
18. 41 a 0 01 0 001 0 01 04 1 Po Output Power W 0019 Figure 19 OUTPUT POWER vs SUPPLY VOLTAGE BTL 70 Gain 20 dB 60 8Q BTL 50 2 5 40 THD N 10 amp 30 S THD N 1 20 n 10 0 10 12 14 16 18 20 22 24 26 28 30 PVcc Supply Voltage V G021 Figure 21 SUPPLY CURRENT vs TOTAL OUTPUT POWER BTL Gain 20 dB RL 80 BTL 5 5 gt 8 2 42 9 0 4 8 12 16 20 24 28 Po Total Output Power W 023 Figure 23 Copyright 2007 Texas Instruments Incorporated Product Folder Link s Gain dBr A GAIN PHASE vs FREQUENCY BTL 30 Phase 20 200 Gain ee 10 1 0 5 400 9 40 500 Gain 20dB 33 pH 4 20 0 125W 1 uF 600 R 8 Q BTL i Vcc 24 V 30 700 20 100 1k 10k 200k f Frequency Hz GU Figure 20 EFFICIENCY vs OUTPUT POWER BTL I e 5 ul Gain 20 dB Ri 8 Q BTL 0 4 8 12 16 20 24 28 Po Output Power W ao Figure 22 POWER SUPPLY REJECTION RATIO VS FREQUENCY BTL Gain 20 dB Ri 8 Q BTL Vcc 24 V Vripple 200 m ra 20 100 10k 20k f Frequency Hz Good
19. Figure 24 Submit Documentation Feedback 9 12202 35 TEXAS TPA3122D2 INSTRUMENTS www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 APPLICATION INFORMATION CLASS D OPERATION This section focuses on the class D operation of the TPA3122D2 Traditional Class D Modulation Scheme The TPA3122D2 operates in AD mode There are two main configurations that may be used For stereo operation the TPA3122D2 should be configured in a single ended SE half bridge amplifier For mono applications TPA3122D2 may be used as a bridge tied load BTL amplifier The traditional class D modulation scheme which is used in the TPA3122D2 BTL configuration has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage Vcc Therefore the differential pre filtered output varies between positive and negative Vcc where filtered 50 duty cycle yields 0 V across the load The traditional class D modulation scheme with voltage and current waveforms is shown in Figure 25 12V Differential Voltage ov Across Load Figure 25 Traditional Class D Modulation Scheme s Output Voltage and Current Waveforms into an Inductive Load With No Input Supply Pumping One issue encountered in single ended SE class D amplifier designs is supply pumping Power supply pumping is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class D amp
20. OUT Litter Citer Figure 26 BTL Filter Configuration Figure 27 SE Filter Configuration 12 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 9 TEXAS INSTRUMENTS TPA3122D2 www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 Power Supply Decoupling Cs The TPA3122D2 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion THD is as low as possible Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads For higher frequency transients spikes or digital hash on the line a good low equivalent series resistance ESR ceramic capacitor typically 0 1 uF to 1 uF placed as close as possible to the device Vec lead works best For filtering lower frequency noise signals a larger aluminum electrolytic capacitor of 220 uF or greater placed near the audio power amplifier is recommended The 220 uF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs The PVCC terminals provide the power to the output transistors so a 220 uF or larger capacitor should be placed on each PVCC terminal A 10 uF capacitor on the AVCC terminal is adequate
21. ability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright O 2007 Texas Instruments Incorporated TPA3122D2 vy TEXAS INSTRUMENTS www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam NG a during storage or handling to prevent electrostatic damage to the MOS gates N DIP PACKAGE TOP VIEW PVCCL 201 PGNDL SD 19 LOUT MUTE BSL LIN AVCC RIN AVCC BYPASS GAINO AGND GAIN1 AGND BSR VCLAMP ROUT PVCCR PGNDR TERMINAL FUNCTIONS TERMINAL NAME ys Vo DESCRIPTION SD 2 signal for IC low disabled high operational TTL logic levels with compliance to RIN 5 Audio input for right channel LIN 4 Audio input for left channel GAINO 15 Gain select least significant bit TTL logic levels with compliance to AVCC GAIN1 14 Gain select most significant bit TTL logic levels with compliance to AVCC MUTE 3 Mute signal for quick disable enable of outputs
22. d com Video amp Imaging www ti com video and ZigBee Solutions www ti com lprf Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2009 Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Texas Instruments TPA3122D2N
23. e left floating For power conservation the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level Copyright 2007 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TPA3122D2 TEXAS INSTRUMENTS www ti com TPA3122D2 SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 USING LOW ESR CAPACITORS Low ESR capacitors are recommended throughout this application section A real as opposed to ideal capacitor can be modeled simply as a resistor in series with an ideal capacitor The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor SHORT CIRCUIT PROTECTION The TPA3122D2 has short circuit protection circuitry on the outputs that prevents damage to the device during output to output shorts and output to GND shorts When a short circuit is detected on the outputs the part immediately disables the output drive This is an unlatched fault Normal operation is restored when the fault is removed THERMAL PROTECTION Thermal protection on the TPA3122D2 prevents damage to the device when the internal die temperature exceeds 150 C There is a 15 C tolerance on this trip point from device to device Once the die temperature exceeds the thermal set point the device enters into the shutdown state and the output
24. ferential inputs and bridge tied load BTL outputs Differential inputs have two input pins per channel and amplify the difference in voltage between the pins Differential inputs reduce the common mode noise and distortion of the input circuit BTL is a term commonly used in audio to describe differential outputs BTL outputs have two output pins providing voltages that are 180 degrees out of phase The load is connected between these pins This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor A block diagram of the measurement circuit is shown in Figure 32 The differential input is a balanced input meaning the positive and negative pins have the same impedance to ground Similarly the SE output equates to a balanced output Evaluation Module Generator Audio Power Amplifier Analyzer I I I I I I I m Lr I amp Y Y YN 1 i R Lit b j XI i E f I 1 Twisted Pair Wire Twisted Pair Wire Figure 32 Differential Input BTL Output Measurement Circuit The generator should have balanced outputs and the signal should be balanced for best results An unbalanced output can be used but it may create a ground loop that affects the measurement accuracy The analyzer must also have balanced inputs for the system to be fully balanced thereby cancelling out a
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26. is important to ensure that boards are cleaned properly Single Ended Output Capacitor C In single ended SE applications the DC blocking capacitor forms a high pass filter with speaker impedance The frequency response rolls of with decreasing frequency at a rate of 20dB decade The cutoff frequency is determined by fc 1 2xnC Z Table 2 shows some common component values and the associated cutoff frequencies Table 2 Common Filter Responses Cse DC Blocking Capacitor uF Speaker Impedance f 60 Hz f 40 Hz f 20 Hz 4 680 1000 2200 8 330 470 1000 Output Filter and Frequency Response For the best frequency response a flat passband output filter second order Butterworth may be used The output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins There are several possible configurations depending on the speaker impedance and whether the output configuration is Single Ended SE or Bridge Tied Load BTL Table 3 list several possible arrangements Table 3 Recommended Filter Output Components Output Configuration Speaker Impedance Filter Inductor uH Filter Capacitor nF 4 22 680 Single Ended SE 8 47 390 4 4 10 1500 Bridge Tied Load 8 22 680 LOUT Litter LOUT ROUT Lfitter Critter C ter d R
27. lifier This phenomenon is most evident at low audio frequencies and when both channels are operating at the same frequency and phase At low levels power supply pumping results in distortion in the audio output due to fluctuations in supply voltage At higher levels pumping can cause the overvoltage protection to operate which temporarily shuts down the audio output Several things can be done to relieve power supply pumping The lowest impact is to operate the two inputs out of phase 180 and reverse the speaker connections Because most audio is highly correlated this causes the supply pumping to be out of phase and not as severe If this is not enough the amount of bulk capacitance on the supply must be increased Also improvement is realized by hooking other supplies to this node thereby sinking some of the excess current Power supply pumping should be tested by operating the amplifier at low frequencies and high output levels Gain setting via GAINO and GAIN1 inputs The gain of the TPA3122D2 is set by two input terminals GAINO and GAIN1 The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier This causes the input impedance Zi to be dependent on the gain setting The actual gain settings are controlled by ratios of resistors so the gain variation from part to part is small However the input impedance from part to part at the same gain may shift by 20 due to
28. ny common mode noise in the circuit and providing the most accurate measurement The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs e Use balanced source to supply the input signal Use an analyzer with balanced inputs e Use twisted pair wire for all connections Use shielding when the system environment is noisy e Ensure that the cables from the power supply to the APA and from the APA to the load can handle the large currents see Table 4 Table 4 shows the recommended wire size for the power supply and load cables of the APA system The real concern is the dc or ac power loss that occurs as the current flows through the cable These recommendations are based on 12 inch long wire with 20 2 sine wave signal at 25 Table 4 Recommended Minimum Wire Size for Power Cables DC POWER LOSS AC POWER LOSS Pour W AWG Size MW MW 10 4 18 22 16 40 18 42 2 4 18 22 3 2 8 3 7 8 5 1 8 22 28 2 8 2 1 8 1 0 75 8 22 28 1 5 6 1 1 6 6 2 18 Submit Documentation Feedback Copyright 2007 Texas Instruments Incorporated Product Folder Link s TPA3122D2 K TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 10 Apr 2008 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty TPA3122D2N ACTIVE PDIP N 20 20 Pb Free CU NIPDAU
29. ol techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice
30. quency determined in Equation 2 3 dB fc 2 The value of C is important as it directly affects the bass low frequency performance of the circuit Consider the example where Z is 20 and the specification calls for a flat bass response down to 20 Hz Equation 2 is reconfigured as Equation 3 1 2n Z f 3 In this example C is 0 4 uF so one would likely choose a value of 0 47 uF as this value is commonly used If the gain is known and is constant use Z from Table 1 to calculate A further consideration for this capacitor is the leakage path from the input source through the input network and the feedback network to the load This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom especially Copyright 2007 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link s TPA3122D2 35 TEXAS TPA3122D2 INSTRUMENTS www ti com SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 in high gain applications For this reason a low leakage tantalum or ceramic capacitor is the best choice When polarized capacitors are used the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2 V which is likely higher than the source dc level Note that it is important to confirm the capacitor polarity in the application Additionally lead free solder can create dc offset voltages and it
31. s are disabled This is not a latched fault The thermal fault is cleared once the temperature of the die is reduced by 30 C The device begins normal operation at this point with no external system interaction PRINTED CIRCUIT BOARD PCB LAYOUT Because the TPA3122D2 is a class D amplifier that switches at a high frequency the layout of the printed circuit board PCB should be optimized according to the following guidelines for the best possible performance e Decoupling capacitors The high frequency decoupling capacitors should be placed as close to the PVCC pins 1 and 10 and AVCC pins 16 and 17 terminals as possible The VBYP pin 6 capacitor and VCLAMP pin 9 capacitor should also be placed as close to the device as possible Large 220 uF or greater bulk power supply decoupling capacitors should be placed near the TPA3122D2 on the PVCCL and PVCCR terminals e Grounding The AVCC pins 16 and 17 decoupling capacitor and VBYP pin 6 capacitor should each be grounded to analog ground AGND pins 7 and 8 The PVCOx decoupling capacitors VCLAMP capacitors should each be grounded to power ground PGND pins 11 and 20 Analog ground and power ground should be connected at the thermal pad which should be used as a central ground connection or star ground for the TPA3122D2 e Output filter The EMI filter L1 L2 C9 and C16 should be placed as close to the output terminals as possible for the best EMI performance The
32. sidered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by to Customer on an annual basis Addendum Page 1 MECHANICAL DATA N R PDIP T PLASTIC DUAL IN LINE PACKAGE 16 PINS SHOWN PINS DIM
33. tinued CROSSTALK vs FREQUENCY SE 0 Gain 20 dB Po 0 125 W 20 8 Q SE Vcc 18V 40 Left to Right 60 80 Right to Left 5 71 100 20 100 1k 10k 20k f Frequency Hz uos Figure 8 GAIN PHASE vs FREQUENCY SE 30 200 59 1 100 20 0 P 15 Phase 9 5 100 1 10 Gain 20dB 47 uH 5 E Po 0425W 0 22 pF 200 RL 8Q SE 470 uF Vcc 18V 0 300 20 100 1 10 200k f Frequency Hz ET Figure 10 OUTPUT POWER vs SUPPLY VOLTAGE SE 18 16 Gain 20 dB 8 Q SE 14 12 THD N 10 10 8 6 THD N 1 4 2 0 10 12 14 16 18 20 22 24 26 28 30 PVcc Supply Voltage V 5012 12 Submit Documentation Feedback 7 Product Folder Link s 12202 TPA3122D2 SLOS527A DECEMBER 2007 REVISED DECEMBER 2007 Supply Current A Efficiency PSRR dB 35 TEXAS TYPICAL CHARACTERISTICS continued EFFICIENCY vs OUTPUT POWER SE 100 80 60 40 20 Gain 20 dB RI 24 Q SE Vcc 12V Po Output Power W Figure 13 SUPPLY CURRENT vs TOTAL OUTPUT POWE 1 4 Gain 20 dB R SE 1 2 4 Q SE Vcc
34. wn mode determines the rate at which the amplifier starts up The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal This noise could result in degraded PSRR and THD The circuit is designed for Cgsp value of 1 uF for best pop performance The inputs caps should be the same value A ceramic or tantalum low ESR capacitor is recommended SHUTDOWN OPERATION The TPA3122D2 employs a shutdown mode of operation designed to reduce supply current lcc to the absolute minimum level during periods of non use for power conservation The SHUTDOWN input terminal should be held high see specification table for trip point during normal operation when the amplifier is in use Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low current state Never leave SHUTDOWN unconnected because amplifier operation would be unpredictable For the best power up pop performance place the amplifier in the shutdown or mute mode prior to applying the power supply voltage MUTE Operation The MUTE pin is an input for controlling the output state of the TPA3122D2 A logic high on this terminal causes the outputs to run at a constant 5096 duty cycle A logic low on this pin enables the outputs This terminal may be used as a quick disable enable of outputs when changing channels on a television or switching between different audio sources The MUTE terminal should never b
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