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ZWIR4501

1. PAN Coordinator Device Beacon Transmission Beacon Tracking MCU ZMD44102 ZMD44102 MCU Auto BeaconTrack BeaconTx Beacon gt IRQ Beacon _ gt D macBcTrStatus Beacon gt R RxFIFO MHR MSDU LQI gt Check beacon T_Beaconinterval x 24Td_Beaconinterval gt 4 A T_BeaconInterval T_BeaconScanStart c Rxldle t zg macControl TxRxOff i x T_Beaconinterval I Prepare a 4 IRQ AutoBcTx e next beacon SS WriteTxF rame R Auto BeaconTx Beacon gt T_Beacon ScanDuration T_Beacon a ScanDuration c Number of consecutive o missed beacons equals n macMaxLostBeacons Auto T BeaconTx i Bea con gt s C k T_Beacon R ScanDuration T_BeaconInterval Ka x 24Td_Beaconinterval A C t i x T_Beaconinterval gt gt gt X IRQ Beacon L Synchronization loss Prepare E t RQ AutoBcTx e macBcTrStatus SyncLoss gt Ge indication nextbeacon WriteTxF rame gt RxIdle macControl TxRxOff lt I d e _macControl BcTrOn B c T_Beacon T ScanDuration r a c k lt xX IRQ gt R IRQreason Beacon gt x macBcTrStatus Beacon gt gt Check beacon RxFIFO MHR MSDU LQI d macControl TxRxOff Figure 4 34 MSC Beaconing Syn
2. PAN Coordinator Device MCU ZMD44102 ZMD44102 MCU macTxConfig EnSlottMode CSMA GoToRx p SE T _L BeaconTrack macControl AutoBcTxOn _ recone Beacon gt IRQ Beacon gt _ macBcTrStatus Beacon gt gt Check beacon RxFIFO MHR MSDU LQI gt J Rxldle macControl TxRxOff R k macTxConfig EnSlottMode CSMA X A l macRxConfig WaitResponseEnable gt Configuration e c dje AutoAckEn FifoStoreLQI t A l AckSpuNb j a I P e Vv e _ WriteTxFrame gt T_BeaconInterval T_BeaconInterval _l __macControl TxOn 24Td_Beaconintefval T_BeaconScanStart gt Sent data request T_Beaconinterval X T x Perform CSMA command x f Cmad data request ES IRQ Tx _ gt Receive data request T td IRA mx macTxStatus Success _ gt command lt l macRxStatus DataAck T_Wait e prepare Ack RxFIFO MHR MSDU LQI DT Ach ForAck gt set frame pending bit I T j mhrAckFc1Tx frame pending gt x 4 Ack Receive Ack with the frame pending bit set gt kX frame pending bit set r x IRQ x gt in the MHR frame WriteTxFrame wl R A macRxStatus FramePend control section macControl TxOn RxActive c _ ti a S T_MaxFi Send pending data e ae ee Pees T gt lt Perform CSMA Response x Wait for the pending data 4 IRQ Tx Data en ee RO macTxSta
3. Rx Tx MCU ZMD44102 ZMD44102 MCU RPCC channel gt RPCC channel Werer d macRxConfig AutoAckEnable d Configure mhrAckFc1Tx mhrAckFc2Tx gt FifoStoreLQl AckSquNbChEn IT macRxConfig default gt e o Configure J macTxConfig default g A macTxConfig default gt and start Rx D macControl RxOn d msduLengthTx t mhrFc1Tx ack request data mhrFx2Tx e mhrSquNbTx mhrDst Tx gt Write frame mhrSrc Tx e TxFIFO MSDU _ lt macControl TxOn SS R GG x m Transmission A T gt failing due to A x X perform CSMA busy channel t i IRQ gt v IRQreason Tx __ N Idle gt Read Tx status macTxStatus CAfail_CHbusy gt __ macControl TxOn gt T X perform CSMA gt Transmit x again L bt Data Ack requested RQ IRQ _ Read Rx 4 RQreason Rx t IRQreason Tx gt N ae status ng i macRxStatus DataAck R macTxStatus Success gt _ Read 7 XT Ack T_Wait X x receive fame 4 RxF IFO MHR MSDU LQI T ForAck A CH c Update MHR x ti Waiting for the lt mhrAckFc1Tx pend gt v for the Ack ACK frame A C k as IRQ X gt IRA lt lt IRQreason Tx CH IRQreason Rx gt gt meaa I lt Seed Rx status status C e macTxStatus Succes
4. Device macBcTrStatus Scan Ier Scan TRIER S Sc JE g Sc Sync Align Align Beacon interval uncertainty window initial corrected beacon interval beacon interval T BeaconScanStart T_BeaconScanStart worst case timining 5 S deviation Coordinator Device lost beacon macBcTrStatus Sc Tied e Scan Teese Scan Weg E Sc Align Sync Align Beacon interval uncertainty window corrected initial corrected beacon interval beacon interval beacon interval T_BeaconScanStart worstcasetimining J 7_BeaconScanStart___ deviation 5 Figure 4 25 Beacon Tracking Timing Correction Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 57 of 124 ZMmMoor eene E RED 4 12 3 Superframe Timing Correction There is also symbol time drift within the superframe between a beacon tracking device and a coordinator The minimum symbol time accuracy according to the IEEE standard is 40 ppm therefore the worst case symbol time deviation between a coordinator and a device is 40 ppm 40 ppm 80 ppm The ZWIR4501 aligns its beacon tracking interval to the beacon interval of the coordinator Once a beacon tracking device has its beacon interval aligned Align bit set in the macBcTrStatus register it will automatically correct its superframe time base The correction interval is adjusted in the SFalignOrder register The correction interval should not be
5. maclinitialCW Initial size of the CSMA CA contention window Reference IEEE 802 15 4 Section 7 5 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 114 of 124 ZMmMor eene E BAD The maclnitialCW sets the initial contention window size used by the CSMA CA algorithm The default value is 2 In order to be 802 15 4 compliant it should not be changed Register Maximum Number of CSMA CA Backoffs 2 0 mnemonic macMaxCSMABackOffs address OxBC access R W C code based constant address definition CSMA_MAX_CSMA_BACKOFFS macMaxCSMABackOffs Maximum number of backoffs done by CSMA CA Reference IEEE 802 15 4 Section 7 5 The macMaxCSMABackOffs sets the maximum number of backoffs done by the CSMA CA algorithm Note that the range defined by the 802 15 4 standard is 0 to 5 however the HW MAC allows values up to 7 Register Battery Life Extension Window Length 3 0 mnemonic macBattLifeExtPeriods address OxBD access R W C code based constant address definition CSMA_BATT_LIFE_EXT_PRDS Addr Register Description eset OxBD macBattLifeExtPeriods Length of the backoff and transaction start window in 0x06 back off periods in the Battery Life Extension mode Reference IEEE 802 15 4 Section 7 5 This register defines the number of backoff periods after the beacon IFS in which the backoff countdown or a transaction start can take place if the Battery Life Extension mode is
6. MHz For IEEE 802 15 4 Phase noise dBc Hz 10 to 100 kHz offset Check with local authorities for frequency regulations Contact ZMD support for non IEEE 802 15 4 compliant frequency applications Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 13 of 124 ZMmMoor eene E RED 3 Application Circuit and External Components The ZWIR4501 requires few external components which allows for a small module form factor and low bill of material BoM costs Figure 3 1 shows an example of an application circuit and its required components Additionally a separate microcontroller is required along with its support components The standard microcontroller interfaces are described in paragraph 3 5 on page 18 Note Please refer to ZWIR4501 application notes 7 for reference design details before using the application circuit example for a product design ree 50 OHM TRACE PLL Loop Filter If Y2 ts SX5159 crystal then C60 and C61 are 43 pF 2 SEPARATE Y2 XTAL CIRCUIT FROM LOOP FILTER AS FAR AS POSSIBLE BEST WITH ONE ON BOTTOM ONE ON TOP 3 LOCATE ALL POWERS SUPPLY CAPACITORS CLOSE TO U4 1 If Y2 is CS5032H crystal then C60 and C61 are 18 pF 4 LOOP FILTER COMPONENTS SHOULD BE PLACED WITH HIGHEST PRIORITY NOTES EZE A RFTEST A64 E a e E d Al ATEST4 8 ATEST3 1 ATEST2 ATEST1 Figure 3 1 Application Circu
7. SrcPanlid SrcPanid Figure 4 17 MAC Header Address Field Composition Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 43 of 124 ZMmMoor eene E RED 4 11 3 Receive Mode Rx The Rx mode can be entered by either the macControl command RxOn an autonomous turnaround coming from Tx or AutoBcTx mode entry B Figure 4 18 or from Tx mode in order to receive an acknowledgment entry A Figure 4 18 or automatically from BeaconTrack or AutoBeaconTx mode in order to resume a paused Wait For Frame Response cycle entry D Figure 4 18 The macControl command RxOn can be issued in Idle or Rxldle mode After the receiver has powered up the acquisition phase starts The macRxStatus is Acquire If a frame has been detected it is received and stored into the RxFIFO macRxStatus Rx As explained in section 4 5 a copy of the MHR and CRC is also stored in the register bank At the end of the reception the CRC sequence and the frame filter are checked If the CRC checksum is invalid or does not pass the frame filter rules the frame is removed from the RxFIFO and the acquisition is resumed Reception of a correct frame is indicated by an interrupt and the appropriate IRQreason More detailed information can be derived from the macRxStatus register For correct frames the status is Data or DataAck if the received frame requests acknowledgment After a correct frame there are three ways to pr
8. EdThreshold Energy detection channel busy idle threshold value Refer to section 4 7 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 79 of 124 Lm eene WIS Register AGC Level 7 0 mnemonic AgcLvl address OxOE access R C code based constant address definition AGC_LVL Register Description I AgcLvl Automatic Gain Control Level The automatic gain control level is the variable part of the gain of the programmable gain amplifier PGA The measured AgcLvl value is above a certain dynamic range an indirect proportional input signal level After a successfully received packet it can be used to estimate the LQI see section 4 6 and RSSI see section 4 7 If the ContRx bit is set in the macRxConfig register the AgcLvl of the last received frame cannot be read from this register The AgcLvl is stored only until the receiver is switched on again Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 80 of 124 eene E RED 5 4 MAC Operating Control Register MAC Control Commands 4 0 mnemonic macControl address 0xA0 access R W C code based constant address definition MAC_CTRL mnemonic macControlT address 0xA1 access R W C code based constant address definition MAC_CTRL_T Addr Register Connend Description Reset USA macControl macControl is ready for next command Ox1F Set by hardware indicating the acceptance macCo
9. 1 5 Pin Description Table 1 1 provides a description of the respective pins Pin Name Pin Type Pin Description ATEST2 Analog I O Analog test pin 2 no connection ATEST1 Analog I O Analog test pin 1 no connection AVDD AVDD Analog power supply typical 2 4 V AVSS Ground Analog ground AVDD AVDD RF power supply typical 2 4 V AVSS Ground RF ground RFIO RF IO RF receiver input and transmitter output AVSS Ground RF ground RFO RF output RF transmitter output AVDD AVDD Analog PLL power supply typical 2 4 V XTAL1 Analog input 24 MHz crystal oscillator input O OIN OD oO R w hy j k ajo Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 8 of 124 Pin Name The Analog Mixed Signal Company Pin Type ZWIR4501 Pin Description XTAL2 Analog output 24 MHz crystal oscillator output LPF_CP Analog output Loop filter charge pump node LPF_VCO Analog input Loop filter VCO tune node AVDD AVDD Analog PLL VCO power supply typical 2 4 V RFTEST RF test pin ground RFTESTPWR AVDD RF test power supply typical 2 4 V DVDD 2 4 DVDD Digital PLL power supply typical 2 4 V RSN CMOS input Chip reset active low DVDD 2 4 DVDD Digital core 2 4V power supply core and pre driver DVDD_3 3 DVDD_3 3 Digital IO 3 3V power supply post driver GPD CM
10. 54 MAC Operating Control dees dere hae einen NENNEN 81 5 5 MAC FIFO ReGISIOR y iiccdcasccscanancedcvcsvedsdavancas du ENEE duvaueducvenatddsveanedsduwontssduvauedscenen 83 560 MAC TX Control EE 85 57 MACRX CONTON EE 91 5 8 MAC Ack Control 94 5 9 MAC Scan Control 97 5 10 MAC Beacon Controls sssini a a a A a AEN 99 5 10 1 MAC Beacon Generation Control 99 5 10 2 MAC Beacon Tracking Control 101 5 11 MAC Timer Control and Values sosennnneeneeeseensnrtnrtestnnrtnnrtesttrrntnnnnnsstertnnn nn nentenen ennnen 106 9 12 MAC Frame Filter Control 2 3 23 iettetcieeseleeieedeeusialt dee 109 5 13 MAC Superframe and GTS Control 111 5 14 MAG CSMA Control eege das cessecivensad avi cacad lances sacuvecscdcvtensidivenesadcedsauasddedencated 114 e NL WER TEE 116 5 16 CLKO Configuration cece eeene ee eeenne ee eeene eee eeeeaeeeeeeaeeeseeaeeeseeneeeseeieeeeeeiieeeeeneaas 118 5 17 Recommended Startup Register Getp nn nnstnnne nnne n 119 6 Transmitter RF Spectrum Test Modes cscsscssccecsnseeeseeesseseseseesesecesnesnseeseessnesanseensnneans 120 7 Mechanical Specifications cccceceeneeesceeeeeeecceeeeeeceeseesesceeeesenceeseseeeaeseseseensnseeeenenseesenes 121 8 BT Vu E 122 9 Document Revision HIStory cccssecceceeeeesceeeseeseseeeeneeeeseeseseeeenseeeeeeesescaeseseeeeeseeesseeseseeeeneeees 122 10 LiSt Of Abbreviations sssaaa RAAE AAKA AENEA eebe Ee 123 E 123 Copyright 2009 ZMD AG Z
11. Current network time of a FFD 15 8 in symbols macTotalTimeFFD3 Current network time of a FFD 23 16 in symbols If the device is a FFD and automatic beacon generation is active then these registers will monitor the current network time between two beacons The beginning of the beacon interval is assigned to the value T_BeaconInterval 1 and the end to 0 The unit is in symbols If the device does not use beacon generation e unslotted mode this timer must be initiated by the macControl command TotalTimerStart Register Current RFD Network Time 23 0 mnemonic macTotalTimeRFD address OxE6 OxE8 access R C code based constant address definition MAC_TOT_TIME_RFD_1 through MAC_TOT_TIME_RFD_3 macTotalTimeRFD1 Current network time of a RFD 7 0 in RTC units macTotalTimeRFD2 Current network time of a RFD 15 8 in RTC units macTotalTimeRFD3 Current network time of a RFD 23 16 in RTC units One RTC unit is 2 32 768 kHz in EU and 1 32 768 kHz US mode If the device is an RFD and a beacon tracking has been activated then these registers will monitor the current network time between two beacons The timer is restarted after each tracked beacon The initial value is the current network time at the end of the tracked beacon minus an error estimate derived by the HW MAC from the previous beacon interval The error estimate is used to correct the timing deviation caused by frequency offset between the crysta
12. Given a total coordinator device timing deviation DEV of 120ppm and a beacon order BO the initial T_BeaconScanStart time is T BeaconScanStart 960 2 DEV T BeaconScanStart 960 2 120e 6 During the initial beacon interval the macBcTrStatus shows the status Track and Sync where Sync means that the HW MAC has successfully synchronized to a beacon but the beacon interval is not corrected yet After the 2 tracked beacon the beacon interval timing correction is active as indicated by the additional Align status bit in the macBcTrStatus register At this time the beacon arrival uncertainty window should be reduced by setting T BeaconScanStart to 5 This will reduce the beacon tracking power consumption Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 56 of 124 ZMmMor eene AWIRASO1 Whenever a beacon frame is lost the beacon interval timing correction requires the addition of one beacon interval in order to realign with the coordinator s beacon interval During this time the macBcTrStatus Align bit is cleared and only the Sync indicator bit is set The T BeaconScanStart must be reset to the worst case timing deviation In general after each tracked beacon the firmware should check the Align bit in the macBcTrStatus register If the bit is set the T BeaconScanStart should be set to 5 otherwise it should be set to the worst case timing deviation Coordinator beacon interval
13. MAC As defined by 1 EU mode US ode Notes The ZWIR4501 Rx synchronization algorithm which starts after PLL and analog Rx power up does not require the complete preamble for proper synchronization Therefore the frame could start earlier than the start of Rx synchronization which leads to a negative time in EU mode Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 12 of 124 The Analog Mixed Signal Company ZWIR4501 2 The RTC requires 730 ms stabilization time after a power up Please refer to chapter 4 Integrated HW MAC for further information 2 6 RF Parameter Summary Parameter Min Nominal output power Pout Typ Max Unit Transmitter Output power at 50 O Low out power modes dBm LP1 dBm LP2 dBm LP3 Chip rate kbit s channel 0 kbit s channels 1 to 10 Error vector magnitude EVM As defined by 1 r dBm Sensitivity At packet error rate PER lt 1 1 EU mode dBm At packet error rate PER lt 1 1 US mode Maximum usable input power dBm Input referred IP3 dBm Input referred IP2 dBm Adjacent channel rejection dB As defined by 1 Alternate channel rejection Frequency range dB MHz As defined by 1 Crystal reference frequency MHz Loop bandwidth kHz Frequency resolution Hz Channel spacing
14. MAC automatically returns to the automatic beacon transmission mode to transmit a beacon frame at the end of each beacon interval The AutoBcTx mode starts 274Peaenhteval symbols before the end of the beacon interval This transition has priority over all other operating modes For data transmission the HW MAC checks before each transmission begins to confirm that a transaction can be finished an inter frame spacing time before the end of a CAP GTS so that these transactions cannot interfere with the beacon interval end Ongoing data receptions are canceled before the ZWIR4501 enters the automatic beacon transmission mode Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 49 of 124 ZMmMor reenen E RED After the beacon transmission the HW MAC automatically enters the Rx mode and starts the receiver unless there is a paused CSMA process pending from the previous CAP In this case the TxMode starts automatically and the CSMA procedure is resumed The automatic beacon transmission can be disabled via the AutoBcTxOff This command can be used in Idle Rxldle RxActive and Tx modes The operating mode remains unaffected in this case A TxFIFO usage conflict can occur if the TxFIFO is still occupied with data from a pending ongoing transmission when software needs to write the MSDU of the next beacon into the TxFIFO To reslove this problem the RxFIFO can be used alternatively for the beacon transmission T
15. Then the new channel must be set up by the RPCC and RxMode registers After a waiting time of approximately 200 Us required by the PLL to settle to the new channel the new scan cycle can be initiated via the macControl command ScanOn Note that the active passive and orphan scan processes use the HW MAC Rx and Tx functions Therefore in active and orphan scan the transmission result is also indicated by a Tx interrupt together with the appropriate macTxStatus equal to Success or CAfail_CHbusy During the ScanRx phase a successful data reception and a CRC failure are also indicated by the Rx and CRCfail interrupts If these additional interrupts are not required the user can mask them in the IRQmask register A detailed description of the scan modes from standard context can be found in JEEE 802 15 4 Section 7 5 2 1 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 47 of 124 ZMmMeoor The Analog Mixed Signal Company ZWIR4501 Scan mode previous operating modes Y macControl ScanOn macScanMode yo D D gege A apes b on from Wel Tx on from Wei from Mei from Idle een sui dion Raise Ly y J ee ee macScan macScan macScan macScan V Status Status Status Status ED Passive ActiveTx OrphanTx A ED value if gt previous one J A macScanED if gt previous ae macScan Sta
16. 15 4 Section 7 5 1 1 This register sets the active portion of the superframe in a beacon enabled network The active portion is the SuperframeDuration SD SD 960 25 symbols SD must be smaller than or equal to the beacon interval T BeaconInterval Note that the value 15 is not allowed In 802 15 4 the value 15 is used to disable the superframe In the ZWIR4501 the enable slotted bit must be set to zero in the macTxConfig register to disable any slotted transmission Register Contention Access Period CAP End 3 0 mnemonic macCAPend address 0xCO access R W C code based constant address definition GE CAP END Register Description Range Adar Register Description Range Reset macCAPend Last slot of the contention access period Reference IEEE 802 15 4 Section 7 5 1 1 This register defines the last slot of the CAP within the superframe Register Guaranteed Time Slot GTS Start 3 0 mnemonic macGTSstart address OxC1 access R W C code based constant address definition SF_GTS_START macGTSstart First slot of the guaranteed time slot period Reference IEEE 802 15 4 Section 7 5 1 1 This register defines the first slot of the GTS within the superframe If macGTSlength is set to 0 then no GTS is assigned and the macGTSstart value is ignored If macGTSlength is greater than 0 then macGTSstart must be greater than macCAPend Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual
17. 4 H Leen we 3 MS Figure 4 12 Short GPD Sequence to Immediately Leave the Timer controlled Sleep Mode Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 37 of 124 ZMmMor eene EBL In beacon enabled operation T General defines the wake up time relative to the end of the beacon interval Slave devices in a beacon enabled network can also sleep until the end of the beacon frame before they automatically return to beacon tracking mode This beacon track sleep mode is activated with the macControl BcTrSleep command from the Idle mode In Sleep mode the analog part and 24 MHz crystal oscillator are shut down The SPI is fed from the 24 MHz clock therefore the SPI is not accessible while the 24 MHz is shut down Only the 32 768 kHz RTC continues to run The 24 MHz oscillator is not shut down if the clock output CLKO is configured to feed a signal derived from the 24 MHz clock during Sleep mode refer to section 3 4 Off Mode The lowest power consumption is achieved by using the transceivers Off mode During Off mode both oscillators are switched off and therefore all functions based on the RTC like beacon timing timer controlled sleep mode and GPD are not supported until the RTC is stabilized again The Off mode is enabled and disabled by the following procedures It can only be entered if RTC is active Enter Off mode e Write the value OxBF to the RPD register to switch off the 32 kHz oscillator
18. A These Timer processes run in parallel to the operating mode proccesses Figure 4 10 Operating Modes Overview SDL Diagram cont 4 11 Operation Mode Description The ZWIR4501 has five different modes of power management These modes are user configurable and controlled by the external microcontroller The power modes are as follows e Tx Rx Tx or Rx mode is active The analog front end is powered up e Idle mode The analog front end is powered down but the 24 MHz crystal oscillator remains on e Sleep mode All circuits are switched off except the 32 768 kHz RTC for accurate time reference Power consumption is reduced to 2 3 pA typical e Global Power Down mode The ZWIR4501 enters into Global Power Down mode by setting the Global Power Down GPD function The 32 768 kHz RTC is maintained e Off mode Both clocks and oscillators are shut down The register content is not maintained The Off mode must be reset to enter Idle mode correctly The ZWIR4501 has a Power On Reset POR function refer to section 3 5 1 for further information on POR Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 36 of 124 ZMoor eene E RED 4 11 1 Low Power Modes Global Power Down GPD Mode The ZWIR4501 can be forced into Global Power Down mode at any time requires runing RTC by setting the GPD pin to high It remains in Global Power Down mode until the GPD pin is released to low Figure 4 11 shows
19. Analog Converter Decibel Direct Sequence Spread Spectrum Energy Detection Electrostatic Discharge European Telecommunications Standards Institute Europe Federal Communications Commission First In First Out Global Power Down Guaranteed Time Slot Institute of Electrical and Electronics Engineers Intermediate Frequency Interframe Spacing Interrupt Request 11 References 1 IEEE Std 802 15 4 2003 IEEE Standard for Part 15 4 Wireless Medium Access Control MAC and Physical Layer PHY Specifications for Low Rate Wireless Personal Area Networks LR WPANs Download http standards ieee org getieee802 download 802 15 4 2003 pdf 2 www zmd biz 3 www etsi org 4 www fcc gov 5 ZWIR4501 Starter Kit User Guide including Basic Communication Software software code examples controlling the ZWIR4501 ISM kbit s kHz LNA LoS LP Filter MAC MISO MOSI ZWIR4501 Industrial Scientific Medical Kilobit per second Kilohertz Low Noise Amplifier Line of sight Low Pass Filter Medium Access Controller Master In Slave Out Master Out Slave In Megahertz Micro Lead Frame Packet Error Rate Physical Layer Phase Locked Loop Quad Flat No Lead Quad Flat Pack Radio Frequency Reset Not Real Time Clock Receiver Receive Serial Peripheral Interface Slave Select Not refers to CS Chip Select Transmitter Transmit United States Crystal 6 C code header file that contains the ZWIR4501 s
20. DirectFifoAccess macTxConfig mode the IFS following the transmit frame should be calculated by SW and both the T_SIFS and the T_LIFS register should be temporarily overwritten by the calculated IFS Register Long Inter Frame Spacing 5 0 mnemonic T_LIFS address OxCE access R W C code based constant address definition T_LIFS a Sa See Se T_LIFS Long inter frame spacing in symbols Reference IEEE 802 15 4 Section 7 5 1 2 This register sets the length in symbols of the inter frame spacing that follows frames with an MPDU greater than macMaxSIFSFrameSize octets If the frame is followed by an acknowledgment the inter frame spacing comes after the acknowledge frame The default value is 40 For 802 15 4 compliance this value must be at least 40 Note that in DirectFifoAccess macTxConfig mode the IFS following the transmit frame should be calculated by SW and both the T_SIFS and the T_LIFS register should be temporarily overwritten by the calculated IFS Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 113 of 124 eene E RED 5 14 MAC CSMA Control Register Unit Backoff Period 7 0 mnemonic macUnitBackOffPeriod address 0xC8 access R W C code based constant address definition BTR_UNIT_BACKOFF_PRD OxC8 macUnitBackOffPeriod Number of symbols comprising the basic CSMA CA 0x14 backoff period Reference IEEE 802 15 4 Section 7 5 The macUnitBackOffPeriod defines the l
21. FIFO no epo next beacon frame received Enable Track beacon ble Trat lt lt macBeTrConfigh gt e E eg beacon yes D Y wake up Seen and turnaround required E i Es No beacon confirmation inc macBcTrStatus required by default The Syncloss Beacon beacons Cant and L eountee 2 SrcAddr are checked by the integrated frame SG filter le Beate ES lt C macBeTrConfig gt a Pa e airclerg yes lt maai e Y eacons b welt ei mwar to check PaniD no and address yes o A CN macControl macControl BoFail BcOk L Y A disable disable _ Erfable Taek macBoTr beacon beacon lt macBcTrConfig gt no Status tacking tacking _ fon A SyncLoss yes macBeTr macBoTr macBcTr Status Status Status Scan Track off W SyncLoss 0 next operating modes i l macControl BeTrOff macControl sable beacon RxOn racking TxRxOff 4 macBcTr Status Off disable beacon fequires a new beacon synchronization later tracking vy L KL D KE fo d eme response tumaround Rot mo v ED E 7 RxActive AR x off J q i WEE Rx on macControl Direct ZMD44102 into appropriate operating modes after a beacon has been found Figure 4 23 Beacon Tracking Mode SDL Diagram Copyright 200
22. Frames not passing the CRC check or frame filter are by default automatically removed v from the Rx FIFO j If an acknoledgment is requested by the received frame then the Ack frame will be transmitted automatically in the background J macControl ScanCont p macScan Status OrphanRx Page 48 of 124 ZMmMoor eene E RED 4 11 5 Automatic Beacon Generation The automatic beacon generation AutoBcTx mode is used for coordinators to transmit beacon frames periodically The automatic beacon generation must be initiated once via the macControl command AutoBcTxOn after which the ZWIR4501 transmits a beacon frame every T Beaconinterval symbols At a time 27d Beaconinterv before the end of each beacon interval an interrupt is generated with the IRQreason AutoBcTx requesting the software to prepare the MHR and the MSDU of the next beacon frame The macAutoBcTxStatus sequence is Tx while transmitting the beacon then Done after the beacon transmission and finally TxReady between the interrupt and the transmission of the consecutive beacon If required an additional interrupt indicating the completed beacon transmission can be enabled in the IRQmask register The active portion of the superframe within the beacon interval is configured by the macSuperframeOrder SO refer to section 4 11 7 for further information regarding superframe configuration The current time in symbols within the
23. HW MAC The macTimerControlStatus register will show the status macControlExp The MAC control command execution and rejection indication is the same as described in section 4 3 4 13 4 Receive and Transmit Timestamp The integrated HW MAC generates a timestamp for each received and transmitted frame The receive timestamp is taken at the end of the SFD and stored in the macRxTime register The transmit timestamp is taken at the leading edge of the PHY frame and stored in the macTxTime register For tracked and generated beacon frames the timestamp is also copied to the macBeaconRxTime and macBeaconTxTime register The timer source for the timestamp generation is selected in the macTimerConfig register Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 60 of 124 Lm The Analog Mixed 4 14 Message Sequence Charts MSCs Signal Company ZWIR4501 The following message sequence charts demonstrate how to control the ZWIR4501 by a microcontroller in different typical scenarios The MSCs are not intended to be standard compliant The communication scenarios shown can be implemented in different ways Only a typical solution is depicted See section 4 11 for detailed description on the different operation modes The ZWIR4501 can be used with a software implementation like 9 to provide an IEEE 802 15 4 compliant MAC interface
24. Page 101 of 124 ZMmMoor eene E RED CoordAddrCheck If this bit is set then the source address of the incoming beacon is compared to the coordinator address stored in the macCoordSrcAddr1 2 or macCoordExtAddr1 8 register in addition to the frame filter rules defined in IEEE 802 15 4 Section 7 5 6 2 If the source address of the beacon does not match a PAN identifier conflict is likely and the beacon is not accepted For details about the coordinator address check and PAN identifier conflict resolution refer to IEEE 802 15 4 Section 7 5 2 2 and 7 5 4 1 A failing coordinator address check is indicated in the macBcTrStatus register Note that beacon frames failing the coordinator address check are still stored in the RxFIFO for further processing by the firmware If the CoordAddrCheck bit is not set the source address of beacon frames is not compared to the coordinator address AlignEnable This bit enables the integrated beacon interval timing correction After each tracked beacon the tracking error is derived and used to correct the next beacon interval duration This timing correction reduces the timing drift between a coordinator and a device caused by different crystal frequency offsets Register MAC Beacon Track Status 6 0 mnemonic macBcTrStatus address OxA7 access R C _ code based constant address definition MAC_BTR_STATUS EGRET REECH Tracking waiting until the expected arrival of the next beacon then starting scan f
25. R W C code based constant address definition MAC_BTX_CONFIG paar Regier en Description resar OxB5 macBcTxConfig 0 UseRxFIFO 0x00 7 1 Reserved UseRxFIFO If this bit is set the RxFIFO is used for the beacon transmission instead of the TxFIFO This mode is useful when the coordinator must prepare the next beacon transmission while another transmission is still pending in the TxFIFO If the RxFIFO is used for beacon transmission the integrated HW MAC mac header and address field composition is disabled The MAC header and address field is used directly from the RxFIFO Register MAC Automatic Beacon Transmission Status 2 0 mnemonic macAutoBcTxStatus address OxA8 access R C code based constant address definition MAC_AUTO_BTX_STATUS Adar Register Stas Description resar OxA8 macAutoBcTxStatus 0x00 Off Automatic beacon transmission is off 0x00 0x01 Tx Transmitting a beacon 0x02 Done The beacon is transmitted and waiting for the next beacon 0x04 TxReady Ready to transmit the next beacon Request firmware to prepare the next beacon TxReady is indicated by the IRQ Done IRQ is masked by default Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 99 of 124 ZMmMoor reenen AWIRASO1 The macAutoBcTxStatus register monitors the current status of the automatic beacon Tx state machine The auto beacon Tx cycle begins with the beacon transmission Tx
26. SPlconfig SPI Configuration SPlstart SPI Master Mode Start SPItx SPI Master Mode Transmit Byte Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 74 of 124 The Analog Mixed Signal Company Lm ZWIR4501 Clock seie conguna CikoutConfig Terko Output Orduan cc Recommended Default ae Setup MTPcontrol MTP Control Register 5 2 IRQ Control Configuration and Status Register Interrupt Request Reason 7 0 mnemonic IRQreason address OxAC access R C code based constant address definition IRQ_REASON 4 C ln e po O o o C CO The reasons for pending interrupts are indicated by the high bits in the IRQreason register After the MCU s software has read the IRQreason register it is automatically cleared to 0x00 by hardware After an interrupt has been issued further information on the actual status can be obtained by the corresponding status register like macTxStatus or macRxStatus Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 75 of 124 eene E RED Each of the eight IRQ reasons can have different interrupt conditions Reason Description Associated Status Register Wake Up WakeUp Wake up from Sleep mode Timer T_MacControl or T_General timer expiration macTimerControl CmdError Wrong macControl or macControlT command Status Acknowledge frame received macRxStatus AckTimeOut No Ack frame received withi
27. Scan _ ActveTaFa JC 2 Scan sst 0 a Jac fsmaoss o Ca feon feen o e fen coor o o auos Reay o 0xBO IRQmask4 0 FIFO TxUnderfow o FIFO TxOverflow o FIFO RxUnderflow o a rro e o o emano emden o The IRQmask registers are used to mask the different interrupt conditions The reason for an interrupt request is indicated by the IRQreason register If a bit is set in the mask register the corresponding interrupt to the external MCU is disabled Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 77 of 124 ZMmMoor eene E RED 5 3 PHY Register Note The PHY registers should be changed only while in IDLE mode Register PHY Current Channel 7 0 mnemonic RPCC address 0x00 access R W C code based constant address definition PHY_ CHANNEL 0x00 RPCC 868 3 Europe 0x00 906 North America Reference IEEE 802 15 4 Section 7 6 1 2 The RxMode register must be set according to the US or EU mode Contact ZMD if applications desire non IEEE 802 15 4 compliant frequency channels Check with local authorities for frequency regulations Note that setting the transceiver to channel 10 requires two additional register settings for best performance After setting the channel to 10 by writing the value 0x0A to the RPCC register then write OxFF to the RPCC register and write the value 0x00 to register address 0x01 Copyright 2009 ZMD AG ZWIR4501 D
28. Sheet and User Manual v 1 3 August 19 2009 Page 89 of 124 Teen EE Register Transmit Frame MAC Header 64 bit Source Address Field 63 0 mnemonic mhrSrcAddr64Tx address 0x74 0x7B access R W C code based constant address definition MHR_TX_SRC_ADDR64_1 through MHR_TX_SRC_ADDR64_8 raar Reaser O O oerion OOOO rea Reference IEEE 802 15 4 Section 7 2 1 6 This register stores the MAC header 64 bit source address field for a transmit frame The mhrFc2Tx addressing mode configuration determines whether the transmit frame address field contains the 64 bit source address The addressing field is constructed for each frame within the HW MAC frame former The 64 bit source address corresponds to the IEEE 64 bit extended unique identifier EUI 64 The EUI 64 value is programmed into an on chip EEPROM during production by ZMD To update the mhrSrcAddr64Tx registers with the programmed EUI 64 the MTPcontrol register must be used Refer to section 5 17 for further information on MTP handling Register Transmit Frame CRC Field 15 0 mnemonic mfrCRCTx address Ox7C Ox 7D access R C code based constant address definition MFR_TX_CRC_1 and MFR_TX_CRC_2 mfrCRC_1Tx Transmitted frame CRC field 7 0 mfrCRC_2Tx Transmitted frame CRC field 15 8 Reference IEEE 802 15 4 Section 7 2 1 8 These registers contain the CRC sequence of the last transmitted frame They are for debugging and monitoring purposes Register T
29. The Analog Mixed Signal Company ZWI R450 1 Rx mode AutoBeaconTx Idle THIRK off AutoBeacon Tx J ik L BeaconTrack Rxldle analog Rx on Tx x areas macControl_ tee Wait For Frame RxOn S macTxConfigh3 Response proccess yes previous operating modes turnaround Tx gt Rx a macRxStatus S Acquire s Y Frames not passing the Aquisition CRC check or frame filter are by default automatically removed from the Rx FIFO Interrupt is masked by default l macRxStatus q Rx i timing support walt Ack for MLME POLL wait request for ack ES la nai SE yes turnaround Reon power up rx H FramePend TI MhrFc1Rx 4 y i Se maoRxStatus macRxStatus macRxStatus meee Acquire AckTimeOut Ack Seen S macRxStatus ae o i 1ta Acquire Acquire Acquistion wo l Interrupt is masked by macRxStatus default Rx Frame receptions priority 1 coliding with automatic beacon transmissions receive yes are canceled frame Frames not passing the CRC check or frame _ filter are by default automatically removed from the Rx FIFO ja frameT ceived p 7 amp CRC ok amp frame filter _ priority 2 priority 2 e p p
30. TxFIFO If the frame has not been sent due to a CSMA failure busy channel the frame is not removed from the TxFIFO and can be used for the next transmission or must be removed from the TxFIFO register using the macControl command TxFifoFlush The length of an IEEE 802 15 4 compliant frame is limited by the length field to 127 bytes In DirectFifoAccess mode the integrated HW MAC needs room for two bytes of the TxFIFO for CRC bytes that are appended at the end of the frame Register Receive FIFO 7 0 mnemonic RxFIFO address 0x81 access R W C code based constant address definition RX_FIFO RxFIFO First byte of received data FIFO Data read from this address is shifted out from the RxFIFO Data can also be written to the RxFIFO if the RxFIFO is used as the transmit FIFO for beacon transmission To enable this mode the macBcTxConfig 0 must be set The RxFIFO register can be written only by a single byte access it cannot be used with a multiple byte access i e the length indicator of the SPI protocol can be one only by writing to the RxFIFO see section 3 6 for further information on SPI protocol Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 83 of 124 ZMmMoor teenies EE Register MAC Tx Rx FIFO Status 5 0 mnemonic macFifoStatus address OxA9 access R C _ code based constant address definition MAC_FIFO_STATUS addr Resistor BR eege t Sau 3 Re UnderOv
31. TxOn L Unsuccessful Tx c IRQ Tx _ gt __ CAP finished t e macTxStatus CAfail_CAPfail gt J gt j Prepare 2 lt IRQ AutoBcTx v next beacon O WriteTxFrame gt T_Beacon Auto Beas ScanDuration BeaconTx gt K BeaconTrack S IRQ Beacon gt macBcTrStatus Beacon gt S Check beacon RxFIFO MHR MSDU LQI L A A A a Figure 4 35 MSC Slotted Tx Rx in CAP Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 68 of 124 Lm The Analog Mixed Signal Company PAN Coordinator ZWIR4501 MCU macCAPend 5 ZMD44102 macGTSLength 4 macTxConfig EnSlottMode CSMA GoToRx macGTSstart 11 CR macControl AutoBcTxOn gt _ T_Beaconinterval 24Td_BeaconIntefval xX T_BeaconiInterval Xx T_BeaconScanStart Device ZMD44102 MCU macRxConfig AutoAckEn BeaconTrack FifoStoreLQI AckSquNb 5 one T T_Beacon gacon e ScanDuration CA CON m le IRQ Beacon gt macBcTrStatus Beacon gt Check and confirm beacon RxFIFO MHR MSDU LQI gt J C Rxldle A macControl TxRxOff Di P macCAPend 5 bn macGTSstart 11 Conf R EES gt slotted Tx mode x g macTxConfig EnSlottMode GTS A _Wr
32. and the status then changes to Done A time 27 Beaconinteval before the end of the beacon interval an interrupt is generated and the status is updated to TxReady indicating that the HW MAC is ready for the transmission of the next beacon and is requesting firmware to prepare the beacon A new cycle begins with the start of the next beacon interval and the transmission of the next beacon For details refer to the automatic beacon Tx mode description in section 4 11 5 Register Beacon Interval Delta Time Exponent 3 0 mnemonic Td Beaconinterval address OxD8 access R W C code based constant address definition T_BCN_INTERVAL_D a ae ee Se Td_BeaconInterval Beacon interval delta time exponent 3 0 This register is used for a coordinator in a beacon enabled network If the coordinator has enabled the auto beacon generation an auto beacon Tx interrupt is generated at a time 214 Bescontetg symbols before the transmission of the next beacon The interrupt indicates to the firmware that it must prepare the next beacon frame For details refer to the beacon generation section 4 11 5 The default time after reset is 2 symbols Firmware may need to adjust this value according to the microcontroller speed requirements Register Beacon Transmit Timestamp 23 0 mnemonic macBeaconTxTime address 0xF2 OxF4 access R C code based constant address definition MAC_BCN_TX_TIME_1 through MAC_BCN_TX_TIME_3 raar Reger O
33. down turnaround Tx Tx gt Rx J gt Sach IL R TeR y ION J A een y oH 4 Dn macOpMode macOpMode macOpMode macOpMode macOpMode macOpMode macOpMode macOpMode Idle Rx RxActive Rx Tx Idle BcTr Rx A P a g N gei ox _ Idle Beacon xeon fe off Track XN h J h d 4 v macControl commands to change RxActive the operating mode are executed yes gt digital Rx when Rx mode is in acquisition Da substate or after a frame reception has been completed Wait for frame A Frame response paused Ge due to CAP end SO ee Tee macControl macControl macControl macControl TxOn TRON BcTrOn 1 AutoBcTxOn UR z ar a a Ackr quested amp power down turnaround Poona AutoAckEnable arta ees Con J gt Inge tergetug yes d 8 J bn Leg no i j ML power down macOpMode macOpMode macOpMode macOpMode 1 pn Tx Idle BcTr AutoBcTx Ss E iio Seegen y macOpMode turnaround m e Rete j A A g y Zeg sm T 3 ge i om ide 1 Beacon AutoBeacon maps off IWR off Tak en amp K J p S p x A Figure 4 9 Operating Modes Overview SDL Diagram Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 35 of 124 ZMmMoor reenen E RED e F R SC 7 Idle Paie idie Pie
34. error can be considered constant the ErrorLock bit can be set in order to lock the last timing error estimate Consequently the first beacon interval after a recovered loss of synchronization is corrected with the locked timing error estimate EarlyGuard This bit enables the early guard time window which is used to compensate the timing error between coordinator and slave The timing error becomes important for higher beacon orders and depends upon the crystal frequency deviations During beacon tracking the timing error is tracked and corrected However a residual error will remain for longer beacon intervals The early guard time window delays the GTS transmission by the value defined in the T Delta register LateGuard This bit enables the late guard window If enabled the guard time T Delta is added to the transaction length for CAP and GTS end checks For details refer to the beacon tracking mode and network timing sections 4 11 6 and 4 12 and 4 12 BeaconConfirm If this bit is set the HW MAC will wait for a confirmation of the tracked beacon by the firmware The beacon is accepted by the firmware by sending the macControl command BcOk The beacon is rejected by sending the macControl command BcFail By default the firmware beacon confirmation is disabled and the beacon is accepted automatically if it passes the integrated HW MAC address check Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009
35. f Idle Rxidie Idle Rxidle except Sleep ide js BeaconTrack S Powerdown d TxiRx off es E d gi He E 4 a o s I A l V Ta i Y i x v e p a macControl macControl macControl macControl_ Sleep BcTroft BeTrof AutoBcTxOff L D P eege A macControlT an TimerStart conte macOpMode macOpMode j d PdnSleep PdnSleep vi set timer T_macControl ios timer T_General pe 4 run timer in the run timer in the power down power down back ground back ground J excestrrc Note except RTC oe i g exceptRTC z i and except RTC SPI and D Parallel D Farle r Wr aa iz e Les interface disable disable disable auto aaa Power gt meriace are beacon beacon beacon Doenan di ee Sa disabled tracking tracking transmission piedi i Su disabled V J ang K Bey N A 3 J e er g SC SES mode y L A S execute T_General falling edge IRQ macControl I Sen expired GPD Timer TimerStop EE kel 7 S EE D f powerup ii maven 24Mhz osc IRQ J b Timer A power down gee Ahn powerup ira Perper Cena digital kel j mode L oo reser J depends on the gt macControlT J Y command J macOpMode e gei I we Woo we TxRxoff g TXRx off Jos x y w SS af x
36. frame is skipped and the receive scan phase is entered directly The passive scan process is indicated by the macScanStatus being Passive The orphan scan allows a device to attempt to relocate its coordinator following a loss of synchronization It is similar to the active scan mode except that to start an orphan notification command must be transmitted and then the HW MAC waits for the reception of a command frame If a command frame is received software must check it and then instruct the HW MAC to continue or stop the scan process The macScanStatus indications appropriate to the orphan scan mode are OrphanTx OrphanRx OrphanTxFail and Command If the received command frame requests an acknowledgment and the AutoAckEnable bit is set in the macRxConfig register then the acknowledge frame will be sent automatically by the HW MAC After transmission of the acknowledge frame a Tx interrupt is generated and the macTxStatus is Success Once a scan cycle has been terminated either by the macControl command ScanCont or a scan duration expiration the Rxldle state starts In Rxldle the analog receiver is still powered up but the digital circuit is idle From this state the scan mode can be resumed The macControl commands TxOn RxOn and TxRxOff cause the ZWIR4501 to switch into Tx RxActive or Idle mode respectively In order to start a new scan cycle at another RF channel the HW MAC must first be set to Idle mode via the macControl command TxRxOff
37. from the beginning and selecting the required mode in the first step Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 120 of 124 Lm eene E BAD 7 Mechanical Specifications The ZWIR4501 uses a green package RoHS Package type MLF PQFN48 7 x 7 1 Dimensions 2 3 Package Body Material Low Stress Epoxy 4 Lead Material Cu Alloy 5 Lead Finish solder plating 6 Lead Form no lead Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 121 of 124 eene E RED 8 Limitations This section gives an overview of the currently known issues with the ZWIR4501 samples Short Description Reason Temporary Workaround Until New Release Higher PER Selectivity issues at high sensitivity Use latest version of the Recommended Startup Peun Setup See section 5 17 Detection of frames in A crosstalk from an adjacent channel could Use RSSI value as additional adjacent channel during cause a misinterpretation of scan result information for right frame detection scan Contact ZMD s support team zigbee zmd de for further information 9 Document Revision History First official release ZMD44102 25 Mar 2006 Changes to version 1 0 besides minor corrections 28 Aug 2006 Update sections 1 4 Pin Assignment and 1 5 Pin Description with description of ATESTx RFTEST and RFTESTPWR pins Correct DirectFifoAcc
38. go into Sleep mode and to Global Power Down mode the 24 MHz crystal at any time within a superframe without loosing the network time The timing error between the coordinator and the slave introduced by the crystal frequency deviation is tracked and corrected by the internal HW MAC RTC unit For a slave device the time within the active portion of the superframe as well as the slots is derived from a superframe timer which is fed by the 24 MHz crystal For higher beacon order the superframe timer must be aligned periodically with the RTC timer in order to limit the timing error This alignment is done automatically within a superframe every 30 2 2 9 symbols Depending upon the frequency deviation the SFalignOrder should be set to a value so that the first alignment happens when the timing error becomes more than 3 symbols For details refer to section 4 12 3 Register Short Inter Frame Spacing 5 0 mnemonic T_SIFS address OxCD access R W C code based constant address definition T_SIFS asa Register eege ae T_SIFS Short inter frame spacing in symbols Reference IEEE 802 15 4 Section 7 5 1 2 This register sets the length in symbols of the inter frame spacing that follows frames with an MPDU size up to macMaxSIFSFrameSize If the frame is followed by an acknowledgment the inter frame spacing comes after the acknowledge frame The default value is 12 For 802 15 4 compliance this value must be at least 12 Note that in
39. in sections 4 11 5 and 4 11 6 1 T_TotalTimeFFD This timer can either be initiated by the macControl command TotalTimerStart or if not running it will be started together with the automatic beacon transmitting function AutoBeaconTx It is 24 bit wide up counting timer with symbol resolution which is driven by the 24 MHz crystal Therefore this timer will be paused during Sleep or Gobal Power Down mode The current TotalTimeFFD timer value can be read from the macTotalTimeFFD register T_TotalTimeRFD This timer is only available in beacon tracking mode It is driven by the 32 768 kHz crystal and has a resolution of RTC units 1 32 768 kHz in EU mode and 2 32 768 kHz in US mode It is a count down timer counting from the arrival of the last beacon down to 0 which is the expected arrival of the next beacon The TotalTimeRFD timer is also running during Sleep mode The current TotalTimeRFD timer value can be read from the macTotalTimeRED register Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 59 of 124 ZMmMoor eene E RED 3 T_Superframe This timer counts the symbols of the active portion of the superframe starting from 0 at the beginning of the superframe It is only available after each transmitted or tracked beacon frame Its content can be monitored from the macCurrentSymbolTime register These 3 timers can be selected independently as timer sources for general purpose interrupt and
40. in the following table Table 3 2 SPI Timing parameters SCK clock period SSN low to first active SCK edge SSN high pulse width Table 3 2 SPI Timing parameters Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 21 of 124 Lm eene E RAD 3 7 Parallel Interface The parallel interface consists of the bi directional DataAddress 7 0 bus and the control inputs read RD write WR and address latch enable ALE The direction of the DA 7 0 bus is controlled by the RD input If RD is high DA 7 0 pins are in input mode Setting RD sets DA 7 0 with the delay of trvd to output mode The timing diagram for read and write access is listed in the following table Table 3 3 Parallel Interface Timing Parameters write access DA 7 0 Write Data ALE WR tis tah RD lt read access DAI7 0 Read Data ALE tas Se gt WR tar tzd RD trvd Figure 3 11 Parallel Interface Write Read Access Bee Description Address setup time Address hold time Address to data time far Address to RD owm o Table 3 3 Parallel Interface Timing Parameters Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 22 of 124 ZMoor eene E RED 4 Integrated HW MAC 4 1 Overview The ZWIR4501 is an 868 915 MHz IEEE 802 15 4 compliant transceiver It integrates the complete PHY layer including the RF front end and
41. macTxConfig EnSlottMode CSMA macPANId OxFFFF macScanMode Active 0 a RPCC Channel 0 WriteTxFrame macControl ScanOn 5M OWN IRQ Scan Tx gt macScanStatus ActiveTxFail gt macControl TxRxOff macControl ScanOn 5M OD IRQ Scan Rx gt macScanStatus Beacon gt RxFIFO MHR MSDU LQI macControl ScanOff Pipe macControl TxRxOff RPCC Channel 1 e WriteTxFrame macControl ScanOn Perform CSMA xX S Cc Beacon request command a n Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 ZWIR4501 MCU Configure scan mode s Prepare beacon ms request commad frame and start scan Beacon request S J command tx failed d Active scan on channel 0 ja Read beacon and finish scan By Prepare beacon E request commad frame and start scan S Active scan on channel 1 Figure 4 32 MSC Active Scan Page 65 of 124 Lm The Analog Mixed Signal Company ZWIR4501 PAN Coordinator Beacon Transmission Device Beacon Tracking MCU ZMD44102 ZMD44102 MCU T_Beacon Intervaa _ gt T_BeaconInterval 5 j 4 macSuperframeOrder Confi ti J gure timer Configure timer s macSu
42. off if it is not in use Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 118 of 124 ZMoor reenen E RED 5 17 Recommended Startup Register Setup Register Multiple Times Programmable MTP Memory Control 3 0 mnemonic MTPcontrol address 0x37 access R W C code based constant address definition MTP_CTRL MTPcontrol MTP control register This register is used to overwrite the values of the trimming register and the transceiver s unique 64 bit source address register mhrSrcAddr64Tx in the register bank with the values stored in the MTP The MTP is programmed by ZMD during production The mhrSrcAddr64Tx address in the register bank is replaced by the programmed IEEE 64 bit extended unique identifier EUI 64 ZMD s 24 bit OUI is 0x00117D Recommended MTP procedure e Write the value 0x09 to the MTPcontrol register to initiate the setting e Wait for 500 us or poll the MTPcontrol register by reading it and wait until the read register value s is equal to 0x0C e Write 0x00 to the MTPcontrol register to complete the setting Note that the MTP procedure can be run only once after reset After running the MTP procedure it is recommended that the following registers be set for best performance results Write to register address 0x39 CLIP_CHK_AGC_LVL_TH the value 0x50 Write to register address OxOF AGC_LVL_INIT the value 0x90 Write to register address 0x2E ACQ_PEAK_TH_SC_TRIM the valu
43. superframe and the ongoing network time are monitored by the macCurrentSymbolTime and macTotalTimeFFD registers The macCurrentSymbolTime is zero at the beginning of the superframe and counts up until the end of the superframe and then reverts back to zero until the next superframe The beacon interval is derived from the 24 bit wide T_TotalTimeFFD timer This timer can be started either by the macControl command TotalTimerStart or if it is not running automatically when the automatic beacon generation is started Each transmitted beacon is time stamped at the leading edge The timestamp is taken by default from the T_TotalTimeFFD register and can be read from the macBeaconTxTime register The automatic beacon generation and the related timing and status register are shown in Figure 4 20 below T_Superframe symbols T_TotalTimeFFD symbols beacon Tx time stamp ae macBeaconTxTime T_Beaconinterval4N lt lt H 96025 1 macTotalTimeFFD macCurrentSymbolTime Active Superframe Inactive Beacon Beacon 960 250 gt 21d_Beaconinterval T_Beaconinterval Tx Ready T x macAutoBcTx Status pone x IRQ with IRQreason AutoBcTx Figure 4 20 Automatic Beacon Generation The automatic beacon generation can be initiated only from the Idle or RxActive mode Once activated the HW
44. the GPD sequence and its timing t gt 200 pus GPD high min GPD Mode Idle Global Power Down Idle 200 us 3 ms tiale GPD topp Idle Figure 4 11 Global Power Down Sequence and Timing In the Global Power Down mode the analog part and 24 MHz crystal oscillator are shut down Only the 32 768 kHz RTC continues to run The SPI is fed from the 24 MHz clock therefore the SPI is not accessible while the 24 MHz is shut down The 24 MHz oscillator is not shut down if the clock output CLKO is configured to feed a signal derived from the 24 MHz clock during Global Power Down mode refer to section 3 4 Timer controlled Sleep Mode The Sleep mode can be entered from Idle mode by the macControl Sleep command The sleep duration is defined by the T General register In nonbeacon enabled operation the T General corresponds to the sleep duration followed by the Sleep command The minimum sleep duration in nonbeacon enabled operation is 3 ms Because the sleep duration is configured in RTC units the minimum value using Sleep mode for the T General register is 0x32 in EU mode and 0x63 in US mode Once Sleep mode has been entered it is not possible to access the registers through the SPI or parallel interface The ZWIR4501 can be forced to exit the Sleep mode before the sleep timer expires with a short GPD sequence The short GPD sequence is shown in Figure 4 12 t 200 us GPD short l Mode Sleep Dk 1 ldle
45. the digital signal processing with hardware support for the MAC layer and an interface to an external microcontroller The ZWIR4501 can be controlled via a SPI or a parallel interface It also provides a dedicated IRQ output a Global Power Down GPD input and a chip reset RSN active low input The hardware MAC HW MAC contains a 128 byte transmit FIFO IxFIFO a 256 byte receive FIFO RxFIFO the frame composition and decomposition automatic acknowledge generation the CRC generation and check and a MAC controller together with several support timers The MAC controller provides different operating modes Transmitting slotted and unslotted CSMA GTS direct Receiving Scan ED Passive Active Orphan Beacon Tracking Automatic Beacon Generation Automatic spanning of slotted CSMA and slotted wait for frame response procedure over multiple contention access periods CAP In order to run the implemented operating modes with a minimum of software support and a reduction in the interrupt requirements and workload from the microcontroller a set of timers is integrated to support the HW MAC e TotalTime Superframe RxDefer IFS Ack WaitForAck MaxFrameResponseTime Scan General Purpose The ZWIR4501 uses two different clocks a 24 MHz system clock for the digital core and a 32 768 kHz real time clock RTC It supports different sleep and power down modes During the Sleep and Global Power Down modes the 24 MHz oscil
46. timer controlled MAC control functions and for the receive and transmit timestamp generation The timer selection is controlled by the macTimerConfig register 4 13 2 General Purpose Interrupt The general purpose interrupt is a free programmable timer controlled interrupt First a running timer must be selected in the macTimerConfig register The time of the general purpose interrupt must be programmed in the 24 bit T General register The general purpose timer function is activated by the macControl command GeneralTimerStart When the selected timer reaches the value programmed in T_ General an interrupt with the IRQreason Timer is generated The macTimerControlStatus register will show the status GeneralExp 4 13 3 Timer Controlled MAC Control Command Execution The macControlT command execution timer can be used to run a timer controlled execution of a MAC control command First a timer must be selected in the macTimerConfig register If the device does not run in the beacon transmit mode the timer must be initiated by the macControl command TotalTimerStart The MAC control execution time absolute time value must be programmed in the 24 bit T MacControl register This timer function is activated by writing a MAC control command to the macControlT register When the selected timer reaches the value programmed in T MacControl register an interrupt with the IRQreason Timer is generated and the command in the macControlT register is released to the
47. too short since there will be a residual error of lt 5 symbols caused by the automatic superframe time correction algorithm Given a timing deviation DEV in ppm the SFalignOrder should be set to SFalignOrder gt log2 5 60 DEV For a total symbol time deviation of 80 ppm for example the SFalignOrder should be adjusted to SFalignOrder gt log2 5 60 80e 6 SFalignOrder 11 Superframe and slot time uncertainty relative to the coordinator increases Device up to 960 2 SO 80ppm 1st beacon interval S s beacon interval not S 1 2 3 4 5 6 7 8 9 10 11 12 13 114 115 S corrected a a Following beacon s s intervals beacon interval S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 corrected a o pt 60 2 SFalignOrder Periodic correction of the superframe Superframe and slot time error time relative to the coordinator is limited by the periodic correction Figure 4 26 Superframe Timing Correction Since the superframe timing is not corrected during the initial beacon interval and superframe timing correction cannot completely eliminate the timing error a guard time should be added to the slotted traffic by the HW MAC in order to avoid collisions There is both an early and a late guard time that can be enabl
48. when setting the GPD to high e Set the GPD pin to high level to switch off both oscillators and thus also the digital core Leave Off mode return to Idle mode e Set the GPD pin to low level to switch on both oscillators and thus also the digital core e Reset the ZWIR4501 with trsn noia 2 after which the digital core is active only again RTC timer functions and beacon mode are not available and after 730 ms the RTC becomes active automatically too Or e Reset the ZWIR4501 with trsn noa 3 after which the digital core and the RTC are active again Figure 4 13 shows the Off mode sequence and its timing GPD l l l I f l Idle mode l digital core is active digital core is active Mode Set RPD 0xBF X Off mode l gt GE gt w o RTC support d w RTC support l RSN l l l l Leen hold 27 3 MS l l or l l Idle mode Idle mode incl RTC Mode Set RPD OxBF X orm X mode l d and GPD support Jeu hold 37 730 ms Figure 4 13 Off Mode Sequence and Timing Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 38 of 124 ZMmMeor eene E RED If the transceiver is used only for nonbeacon enabled networks and the timer functionality like Sleep mode is not used i e RTC is not used the digital core and its interface e g SPI can be used after a reset with trsn hold2 3 ms The RTC core including timer functionality operates after 730 ms The OFF mo
49. 0 AgcLvl Figure 4 5 LQI over AgcLvl The LQI value can be calculated by the following simplified equation LQI Integer 320 2 4 AgcLvl i valid for 27 lt AgcLvl lt 133 LQI 0 valid for AgcLvl gt 133 LQI 255 valid for AgcLvl lt 27 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 28 of 124 ZMmMeoor eene E RED 4 7 Receive Signal Strength Indicator RSSI Over a certain dynamic range the measured AgcLvl value is an indirect proportional input signal level The AgcLvI can be used to estimate the receive signal strength of the last successfully received frame The graph in Figure 4 6 shows the correlation between the AgcLv and the input power level Pin dBm 20 40 4 60 4 80 4 100 120 r r r r r r r 1 0 20 40 60 80 100 120 140 160 AgcLvl Figure 4 6 Typical AgcLvl vs RF Input Power Pin For input levels below 95 dBm the estimation of the RSSI value has a higher variation The RSSI value can be calculated by the following simplified equation RSSI dBm 0 6 AgcLvl 14 5 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 29 of 124 ZMmMoor eene E RED 4 8 Energy Detection Level After an energy detection scan a value representing the maximum measured energy level is stored to the macScanED register The stored value can be assigned to a receive signal power level Figure 4 7 dep
50. 09 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 ZWIR4501 Page 4 of 124 Lm The Analog Mixed Signal Company ZWIR4501 4 11 5 Automatic Beacon Generation 49 4 11 6 Beacon Tracking essiri prenre RE Edge eege deg 52 4 11 7 Superframe Configuration cccccceeeeeeeceeee essences dknina anin NENN NANNAN NNN EARRA ANNAR EENAA ANA 55 4 12 Timing Correction ee eee eter e teeter teeter ee eae teen nade seen eae eeeeeaaeeeseeaeeeseeaaeeeseeneeeeeeas 56 4 12 1 Network Timing Correchon cc ceeeeee eneee erent ee etieee ee ttieeeeetnieeeeetiieeeeetiaeeeereaa 56 4 12 2 Beacon Interval Timing Correchon eens ee eeieeeeeeiieeeeetiieeeeesieeeeeeeaa 56 4 12 3 Superframe Timing Correction vieciccccccceecceeseecceceeeanseeeeaccceeveanccvevsaccavesveaeceveveanccvevens 58 4 13 General Purpose Timer Function ccececeeceeceeeeeeeeeecneaeeeeeeeeeeeececeaeceeeeeeeseccneaeeeeeeeeeetees 59 A131 e NEEN 59 4 13 2 General Purpose lnterupt ennnen 60 4 13 3 Timer Controlled MAC Control Command Execution ececeeceeeeeeeeeeeeeaeees 60 4 13 4 Receive and Transmit Timestamp ssssssesenssesseetrrrrsttsttttrtnnnnnstttnnnn nnn nnn errr nn nenne 60 4 14 Message Sequence Charts MGCel 61 5 UE 71 51 Registar SUMMARY osioissa EERSTEN EEN 71 5 2 IRQ Control Configuration and Status cccccecececceeceeeeeeeeececeaeceeeeeeeeseceeaeeeeeeeeeeeeseaeess 75 53 PHY Registe EE 78
51. 1 through MAC_RX_TIME_3 Timestamp of the received frame 7 0 Timestamp of the received frame 15 8 Timestamp of the received frame 23 16 The macRxTime contains the timestamp of the last successfully received frame The timestamp is taken at the start of the MAC frame end of SFD of the received frame from the timer specified in the macTimerConfig register 5 8 MAC Ack Control Register Transmit Ack Frame MAC Header Frame Control Field 4 0 mnemonic mbhrAckFco1Tx address Ox7E access R W C _ code based constant address definition MHR_TX_ACK_FC_1 Ox7E_ mhrAckFc1Tx o Security enabled za Frame pending 2 Acknowledge requested Ji e In eege Reference IEEE 802 15 4 Section 7 2 1 1 Note that the bit ordering within this register is not the same as it is when it appears later in the transmitted Ack frame This register is used to control the acknowledgement frame Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 94 of 124 Teater EE Register Transmit Ack Frame MAC Header Frame Control Field 7 0 mnemonic mbhrAckFc2Tx address Ox7F access R W C code based constant address definition MHR_TX_ACK_FC_2 paar regisora O oosporo 1 Reseved H Destination addressing mode b0 o 3 Destination giereg 3 a Reema 3 s Rema ooo y e Source addressing moe 3 7_ Source addressing mode ot o For IEEE 802 15 4 compliance this register should not been ch
52. 40 1 887 47 19 Table 4 1 Timing Deviation for 120ppm In beacon tracking mode the ZWIR4501 can track and correct the beacon interval timing error relative to its coordinator This minimizes the time the receiver must be turned on before the arrival of the next beacon and therefore helps reduce the power consumption Additionally the superframe time is periodically corrected in order to keep the slot boundaries aligned with the coordinators slot boundaries which reduces collisions in the slotted traffic Moreover a beacon tracking device can go to sleep within the superframe and recover the superframe time on wake up allowing a device for example to sleep until a GTS transmission The features mentioned above will be explained in subsequent Sections 4 12 2 Beacon Interval Timing Correction The integrated beacon interval timing correction measures the time difference between the expected and the actual arrival of the beacon frame The difference is used to adjust the beacon interval and to improve the estimate of the next beacon arrival Figure 4 25 Beacon Tracking Timing Correction illustrates this process The T BeaconScanStart register is used to control the time the receiver is turned on before the expected arrival of the next beacon frame At the end of the initial beacon interval the uncertainty window of the beacon arrival is two times the worst case timing deviation to which the T BeaconScanStart register must be adjusted
53. 9 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 54 of 124 ZMmMoor eene E RED Note that during the beacon tracking scan phase the HW MAC Rx function is used Therefore a successful data reception and a CRC failure are also indicated by an Rx and CRCfail interrupts If these additional interrupts are not required the user can ignore them in the RQreason register 4 11 7 Superframe Configuration A superframe is used in a beacon enabled network The superframe is bound by the beacon frames transmitted by the network coordinator The registers used for the superframe configuration are the same as those for coordinator and slave devices The beacon interval length must be set up in the T_ BeaconInterval register The duration of the active portion of the superframe SD is defined by the macSuperframeOrder SO SD 960 25 symbols SD must be smaller than or equal to the beacon interval T BeaconInterval SO must be in the range from 0 to 14 Note that an SO equal to 15 is not allowed In 802 15 4 the value 15 is used to disable the superframe In the ZWIR4501 the EnableSlottedMode bit must be set to zero in the macTxConfig register to disable any slotted transmission Note that in beacon tracking mode the T_BeaconInterval and macSuperframeOrder registers can be adjusted on the fly after each tracked beacon This may be required to update the superframe configuration according to the superframe s
54. Addr address 0x97 Ox9E access R W C code based constant address definition COORD_EXT_ADDR_1 through COORD_EXT_ADDR_8 Reference IEEE 802 15 4 Section 7 5 4 1 If the CoordAddrCheck is enabled in the macBcTrConfig register the extended source address of the incoming beacon frames are compared to the macCoordExtAddr to determine if the incoming beacon is meant for the device See description of the macBcTrConfig register for further information Register Maximum Lost Beacon Number 3 0 mnemonic macMaxLostBeacons address 0xC3 access R W C code based constant address definition BTR_MAX_LOST_BCNS REECH OxC3 macMaxLostBeacons Maximum number of lost beacons before a loss of 0x04 synchronization indication Reference IEEE 802 15 4 Section 7 5 This register defines the number of consecutive beacons that will cause the internal HW MAC beacon tracking algorithm to generate an IRQ indicating the loss of synchronization Refer to the beacon tracking section 4 11 6 The default value is 4 In order to be 802 15 4 compliant it should not be changed Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 103 of 124 reenen E RED Register Current Number of Lost Beacon Number 3 0 mnemonic macSyncLoss address OxC4 access R C _ code based constant address definition BTR_SYNC_LOSS Current number of lost beacons Reference IEEE 802 15 4 Section 7 5 This register monitors th
55. At completion of the scan an interrupt with the IRQreason Scan and the macScanStatus TimeOut is generated The maximum recorded ED value during the ED scan can be read from the macScanED register For details on the ED level refer to section 4 8 The active scan mode allows a device to locate coordinators transmitting beacon frames In active scan a beacon request frame is transmitted first First the MHR and MSDU must be stored in the register bank and the TxFIFO respectively The macControl command ScanOn initiates the transmission of the frame using CSMA CA During this phase macScanStatus is ActiveTx If the CSMA CA fails due to a busy channel a scan interrupt is generated and the macScanStatus is ActiveTxFail If the transmission is successful the HW MAC activates the receiver and waits for T ScanDuration symbols for the reception of a beacon frame During this phase the macScanStatus is ActiveRx Nonbeacon frames are ignored during the scan Upon reception of a beacon frame an interrupt is generated and the macScanStatus is Beacon At this point the scan process can either be terminated via the ScanOff command or be continued by the ScanCont command until a specific number of beacons have been found The T ScanDuration timer expiration always terminates the scan process which is indicated by an interrupt and a macScanStatus TimeOut indication The passive scan mode is similar to active scan except that transmission of the beacon request
56. C frame must be written into the TxFIFO before the MAC frame The length value must include the whole payload length including MAC header and frame payload length The CRC check sum is added automatically to the sent frame The two CRC bytes should not be included in the length value In the DirectFifoAccess mode the integrated address field composition is bypassed During DirectFifoAccess mode the ZWIR4501 uses the Acknowledge requested bit in the mhrFc1Tx register to determine if an inbound acknowledgement frame is expected Note that the ZWIR4501 does not use the Acknowledge requested bit of the transmit frame control field in the TxFIFO to make this determination If the Acknowledge requested bit in the mhrFc1Tx register is not set and a data frame is transmitted using the macControl command TX_ON an Ack timeout interrupt is not generated If the Ack timeout notification is desired the Acknowledge requested bit in the mhrFc1Tx must be set prior to issuing the macControl command TX_ON Note that in DirectFifoAccess mode the IFS following the transmit frame should be calculated by SW and both the T_SIFS and the T _LIFS register should be temporarily overwritten by the calculated IFS The RxFIFO can be used alternatively as TxFIFO for beacon transmissions In beacon transmission mode a TxFIFO usage conflict can occur if the TxFIFO is still occupied with data from a pending ongoing transmission and if the MCU needs to write the MSDU of the next be
57. OO pesonn O freser macBeaconTxTime1 Timestamp of the transmitted beacon 7 0 macBeaconTxTime2 Timestamp of the transmitted beacon 15 8 macBeaconTxTime3 Timestamp of the transmitted beacon 23 16 The macBeaconTxTime contains the timestamp of the last transmitted beacon The timestamp is taken at the leading edge of the beacon frame from the timer specified in the macTimerConfig register Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 100 of 124 ZMmMoor eene E RED 5 10 2 MAC Beacon Tracking Control Register MAC Beacon Tracking Configuration 6 0 mnemonic macBcTrConfig address OxB4 access R W C code based constant address definition MAC_BTR_CONFIG DESCH 1 eat 2 feme li o hece OOOO a BeaconConfimm Ir C TrackEnable This bit must be set to enable beacon tracking ErrorLock After the 1 two consecutive beacons are tracked successfully the beacon tracking engine starts to correct the expected beacon interval by a timing error estimate The timing error is caused by the crystal frequency deviation between coordinator and slave The frequency deviation depends mostly upon the temperature and age of the crystal and can therefore be considered constant After a loss of synchronization beacon tracking starts with a new beacon scan If the ErrorLock bit is not set it waits for the first two tracked beacons before making the first timing error estimate If the timing
58. OS input Global Power Down from external device active high IRQ CMOS output Interrupt request to external device active low SSN CMOS IO SPI slave select not active low MOSI CMOS IO SPI master out slave in in slave mode MISO CMOS IO SPI master in slave out in slave mode SCK CMOS IO SPI serial clock DA O CMOS IO Data address used for parallel interface DAD CMOS IO Data address used for parallel interface DA 2 CMOS IO Data address used for parallel interface DA 3 CMOS IO Data address used for parallel interface DA 4 CMOS IO Data address used for parallel interface DA 5 CMOS IO Data address used for parallel interface DA 6 CMOS IO Data address used for parallel interface DAI7 CMOS IO Data address used for parallel interface CLKO CMOS output Clock to external device WR CMOS input Write data address used for parallel interface RD CMOS input Read data address used for parallel interface DVDD_3 3 DVDD_3 3 Digital IO power supply post driver typ 3 3 V DVSS Ground Digital ground DVDD 2 4 DVDD Digital core power supply core and pre driver typical 2 4 V ALE CMOS input Address latch enable used for parallel interface AVDD AVDD Analog power supply typical 2 4 V AVSS Ground Anal
59. OpMode changes are shown The status register updates macTxStatus macRxStatus macBcTrStatus macAutoBcTxStatus macScanStatus and the Internal timer and transitions are not shown at this level Refer to the detailed sub mode diagrams Tx Rx Scan Beacon Track AutoTxBeacon ir idle Tx Rxidle yN N eal RxDefer eer RxDefer 3 VE 1 RxActive EE 1 Ractive macControl macControl macControl Lesser Lesser macControl TxOn RxOn ScanOn BcTrOn BcTrSleep AutoBcTxOn 7 SS N f PT mm L N y y Gees power up Rx power down up Rx power up Tx Lisa mode only fom Idle all except from except denendend L orSleep J exceptRTC RxActive from Tx i Y d v He macOpMode macOpMode macOpMode macOpMode macOpMode Scan BcTr PdnSleep BcTr AutoBcTx EAE powerup T S eege fr Beacon jAitosieacon a ko sar 4 Track apes b 2 A gt 4 5 raue li Wait for frame WE ne TUE J i pending 2 d macOpMode A Rxidie SS ATOR ER acTxConfig 3 a or Lo yes lt yes Ack requested Wett ge CET macControl macControl menn See no RxOn TxOn TxRxOff BcTrOn yes 4 la g N N power down tumaround turnaround power
60. OxAD 0xBO Interrupt Condition Mask 1 2 3 4 PHY Register BGG 00 Pe Guenther Setz oE Automatic Gain ContolLevel BO MAC Operating Control EES MAC FIFO Register DES Register macFifoStatus MAC Tx Rx FIFO Status ES Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 71 of 124 eene E RED MAC Tx Control macTxStatus oxs MACTransmtSats fe msduLenaintx ox60 Transmit Frame MSDU Length fee mhrFc1Tx 0x61 Transmit Frame MAC Header Frame Control 87 Field 1 mhrFc2Tx 0x62 Transmit Frame MAC Header Frame Control 87 Field 2 mhrSquNbTx Transmit Frame MAC Header Sequence Number Field mhrDstPanldTx 0x64 0x65 Tx Frame MAC Header Dest PAN Identifier Field mhrDstAddr16 0x66 0x67 Tx Frame MAC Header 16 bit Dest Address Field mhrDstAddr64Tx 0x68 0x6F Tx Frame MAC Header 64 bit Dest Address Field 89 mhrSrcPanldTx 0x70 0x71 Transmit Frame MAC Header Source PAN Identifier Field mhrSrcAddr16Tx 0x72 0x73 Transmit Frame MAC Header 16 bit Source Address Field mhrSrcAddr64Tx 0x74 0x7B Transmit Frame MAC Header 64 bit Source Address Field mfrCRCTx 0x7C 0x7D Transmit Frame CRC Field on OxF8 OxFA Transmit Timestamp on MAC Rx Control MAC Ack Control mhrAckFco1Tx Ox7E Transmit Ack Frame MAC Header Frame 94 Control Field mhrAckFc2Tx Ox7F Transmit Ack Frame MAC Header Frame 95 Control Field T Wai T_WaitForAck Wait for Acknowledge T
61. SMI SX5159 crystal the values for C4 and C5 are typically 43 pF The user should experiment with values near 43 pF to determine the capacitor value for best frequency accuracy in a production environment Any deviation on this system part will result in a large deviation on the carrier frequency and decrease system performance XTAL1 C4 O 24 MHz XTAL2 C5 O Figure 3 2 24 MHz Crystal Oscillator External Components 3 1 2 Low Power Crystal Oscillator 32 768 kHz The 32 768 kHz crystal oscillator is designed for extremely low power operation and it always runs when power is applied to the device There is also a user programmable option to power down the oscillator see description on Off mode section 0 The oscillator provides the time reference for the on chip real time clock The oscillator utilizes an amplitude controlled 2 pin Pierce oscillator with an on chip biasing resistor The recommended crystal to be used with this oscillator is the SMI 155M327 because of frequency tolerance and temperature range specifications The load capacitor values are determined by the specs of the particular crystal selected RTC1 O 32 768 kHz N RTC2 Si O Figure 3 3 32 768 kHz Crystal Oscillator External Components The ZWIR4501 provides external access to the 24 MHz or 32 768 kHz clocks for unique system implementations Refer to section 3 4 for further informati
62. Sheet and User Manual v 1 3 August 19 2009 Page 91 of 124 ZMmMeor eene E RED FifoStoreTimeStamp This bit enables the storage of a 3 byte receive timestamp after the frame in the RxFIFO If FifoStoreLQI is enabled the timestamp is stored after the LOL An appropriate timer must be selected for the timestamp in the macTimerConfig register AckSquNbCheckEnable If this bit is set the sequence number of an incoming acknowledge frame is compared to the sequence number of the transmitted frame that requested the acknowledgment Acknowledge frames for which the sequence number does not match are rejected In the DirectFifoAccess mode the sequence number for the automatic sequence number checking is derived from the header bytes that are written to the TxFIFO Register MAC Receive Status 7 0 mnemonic macRxStatus address OxA4 access R C _ code based constant address definition MAC_RX_STATUS Paar negir sws pesenpton reser Acknowledge frame received Acknowledge frame received si received 0x18 Ack received with frame pending bit set result AckFramePend 0x20 PollNoData No frame received within T MaxFrameResponse after an acknowledge with the frame pending bit set 0x24 PollCAPend No pending data received within the current CAP WaitForFrame process will be summed in the next CAP 0x80 Data Frame without the acknowledge requested bit set received 0xCO DataAck Frame with the acknowledge requested bit set receiv
63. Tx mode returns the macTxStatus as success The status CAfail_CHbusy indicates that transmission failed because the CCA could not sense the channel as idle The CSMA algorithm is described in section 4 11 2 1 Each slotted CSMA transmission starts with a random backoff time If the random backoff is not finished within the current contention access period CAP or within the 1st six slots following the beacon IFS for the battery life extension mode then it is paused and the macTxStatus CAfail_CAPfail is returned The unfinished random backoff is automatically resumed in the next CAP After the random backoff the HW MAC checks whether the current transaction including a possible acknowledgment can be completed before the end of the CAP If the check fails the frame is not transmitted and the returned macTxStatus is CAfail_CAPfail Under this condition the CSMA will automatically resume with a new random backoff in the next CAP For guaranteed time slot GTS transmission the transmitter checks whether the guaranteed time slot is still available in the current superframe and if so whether the transmission including acknowledgement can be completed before the end of the GTS If one of these checks fails the frame is not transmitted and the returned macTxStatus is GTSfail Figure 4 14 on page 40 illustrates the GTS and CAP boundary checks A CAP GTS transmission is done only if the complete transaction including acknowledgment can be completed wi
64. WIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 5 of 124 ZMmMeor eene E BAD 1 General Device Description 1 1 Introduction The ZWIR4501 is a fully integrated CMOS transceiver providing license free multi channel operation in the 868 3 MHz for Europe and 906 MHz to 924 MHz for North America US ISM bands This low power baseband transceiver is optimized for data rates up to 40 kbit s US and incorporates Direct Sequence Spread Spectrum DSSS technology to assure reliable data transfer in hostile RF environments The transceiver is highly integrated and includes a thin Medium Access Control MAC layer resulting in a minimum of external components and lower application costs Because the ZWIR4501 transceiver is based on the IEEE 802 15 4 specification ZMD highly recommends using the IEEE 802 15 4 specification to complement this user manual See section 10 for definitions of abbreviations 1 2 Features IEEE 802 15 4 compliant Direct Sequence Spread Spectrum DSSS Burst data rate 40 kbit s North America 20 kbit s EU Transmit range 100 m LoS Low sleep current multi year battery life SPI and parallel interfaces Thin MAC on PHY ease of integration low overall system costs Internal transmit receive switch external power amplifier capability Variable Tx output power adaptive power density Direct conversion radio reduced cost Microcontroller independent flexibility Fractional N PLL sof
65. ZMeool The Analog Mixed Signal Company ZWIR4501 Data Sheet and User Manual Version 1 3 Release Date 19 August 2009 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 All rights reserved The material contained herein may not be reproduced adapted merged translated stored or used without the prior written consent of the copyright owner The information furnished in this publication is preliminary and subject to changes without notice ZMmMor eene EIDEL Notes Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 All rights reserved The material contained herein may not be reproduced adapted merged translated stored or used without the prior written consent of the copyright owner The information furnished in this publication is preliminary and subject to changes without notice Lm The Analog Mixed Signal Company ZWIR4501 ZWIR4501 Data Sheet and User Manual v 1 1 Single Chip 900 MHz RF Transceiver with Integrated Thin HW MAC IEEE 802 15 4 Compliant ZigBee Ready Description The ZWIR4501 is a fully integrated system on chip CMOS transceiver providing license free multi channel operation in the 868 3 MHz EU and 902 MHz to 928 MHz North America ISM bands This low power RF transceiver is optimized for data rates up to 40 kbit s and incorporates direct sequence spread spectrum technology DSSS to ensure reliable data transfer in host
66. acRxConfig is not asserted the receiver is powered down and the Idle mode starts If the ContRx bit is set the ZWIR4501 remains in RxActive mode and continues with a new acquisition cycle Additionally the ZWIR4501 can be directed from RxActive mode into Tx Idle beacon tracking or AutoBcTx mode with the appropriate macControl command If reception is ongoing while one of these commands is received the reception is first completed before the transition to the requested operating mode occurs During this time the command is buffered in the macControl register The four different scan modes are initiated with the macControl command ScanOn The scan mode is selected in the macScanMode register Some scan modes require additional macControl command interaction For details refer to section 4 11 4 A scan process terminates either with a timeout or a macControl command ScanOff After the scan process the Rxldle state starts and the analog receiver remains on but the digital receiver is stopped From this state a new scan cycle can be initiated by writing the macControl command TxRxOff followed by the macControl command ScanOn Before each scan the channel must be set up in the RPCC From Rxldle mode the RxActive Tx BcTr and Idle modes can be accessed as well Beacon tracking BeaconTrack is initiated with the macControl command BcTrOn This is possible only from Idle mode After successful reception of the first beacon the ZWIR4501 keeps tr
67. ack of the beacon interval and for the following beacons the BeaconTrack state starts automatically at a time T BeaconScanStart in symbols before the expected arrival of the next beacon The ZWIR4501 must be in one of the allowed operating modes indicated in Figure 4 9 on page 35 in order to enter beacon tracking automatically Ongoing data receptions or transmissions will delay the transition to the beacon tracking mode To reduce the power consumption the ZWIR4501 can also be directed to Sleep mode via the macControl command BcTrSleep The ZWIR4501 will automatically wake up at the expected arrival of the next beacon The beacon tracking state is vacated after the successful tracking of a beacon or a SyncLoss timeout and the Rxldle state starts If a CSMA algorithm could not be completed in the previous CAP the TxMode starts automatically after the next tracked beacon and the CSMA algorithm is resumed If a Wait for frame response procedure could not be completed in the previous CAP then the RxMode starts automatically after the next tracked beacon and the Wait for frame response procedure is resumed Beacon tracking can be disabled with Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 33 of 124 ZMmMor reenen E RED the BcTrOff command This command does not cause an operating mode change except during beacon tracking in which case it causes the ZWIR4501 to enter the Idle mode Autom
68. acon into the TxFIFO To avoid this problem use the RxFIFO as an alternative for beacon generation This mode is enabled by setting the UseRxFIFO bit in the macBcTxConfig register In this case the RxFIFO is used in the same way that the TxFIFO is used in direct TxFIFO access mode and the complete beacon frame content must to be written to the RxFIFO In this case the IFS following the beacon frame should be calculated by SW and both the T SIFS and the T LIFS register should be temporarily overwritten by the calculated IFS For auto acknowledge generation the acknowledge frame is generated automatically with the sequence number of the previous received frame and the frame type set to Ack 0b010 The remaining frame control field bits 15 3 can be adjusted by the firmware in the register mhrAckFc1Tx and mhrAckFc2Tx As a rule the frame pending bit mhrAckFc1Tx 1 must be controlled by the MCU For forward compatibility reasons the other bits can also be modified For received frames the MAC header MHR and payload MSDU are queued in the 256 byte RxFIFO Each frame is deposited in the RxFIFO starting with a length indicator followed by the MHR and the MSDU The length indicator defines the length of the MHR and the MSDU A two byte link quality indicator value LQI refer to section 4 6 for further information is appended behind the MSDU to each stored packet low byte first This is enabled by default and can be disabled
69. ad access to IRQreason Figure 4 3 Interrupt Processing See Section 5 2 for further information on interrupts and their registers Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 25 of 124 ZMmMeor eene E RED 4 5 Frame Handling The ZWIR4501 provides a 128 byte TxFIFO and 256 byte RxFIFO Both FIFOs can be flushed independently at any time by the macControl commands TxFifoFlush and RxFifoFlush The TxFIFO can store the content for a minimum of one transmit frame It can be used in two different modes which are selected by the DirectFifoAccess bit in the macTxConfig register In the default mode the TxFiFO is used together with the some register bank space to store the transmit frame content MSDU In this mode the sequence number frame control information source and destination addresses and MSDU length indicator are stored in the register bank Only the MSDU is written to the TxFIFO The transmit frame is then constructed by an integrated frame former which also composes the address field according to the addressing modes of the frame control field refer to section 4 11 2 2 Setting the DirectFifoAccess bit in the macTxConfig register enables the DirectFifoAccess mode In the DirectFifoAccess access mode the complete MAC frame including the frame control bytes sequence number address bytes and MSDU are written to the TxFIFO A length byte indicating the length of the complete MA
70. ally enters the receive mode RxActive The latter case occurs if GoToRx is enabled in macTxConfig or a frame has been transmitted with the acknowledge request bit set in the frame control header mhrFc1Tx From Idle mode the receiver is turned on with the macControl command RxOn The analog receiver is powered up and the acquisition phase is started macRxStatus is RxActive During reception the received frame is stored in the RxFIFO If the received frame has an invalid CRC or does not pass the integrated frame filter see section 4 9 the frame is removed from the RxFIFO and the ZWIR4501 continues with a new acquisition cycle If the frame is accepted the ZWIR4501 can continue automatically in three different ways If a frame with the acknowledge request bit set in the MAC header frame control field mhrFcRx has been received and the AutoAckEnable is asserted in macRxConfig the Tx mode is started after a Rx Tx turnaround and the acknowledge frame is transmitted with a space of T Ack symbols after the received frame The acknowledge frame is generated with the MAC header frame control byte 15 8 set to zero bits and a sequence number from the received frame Software must set the frame control field 7 0 mhrAckFc1Tx before the start of the acknowledge transmission If the received frame does not request an acknowledgment or the AutoAckEnable in macRxConfig is not set either the second or the third path is taken If the ContRx bit in m
71. an Diego CA 92128 Hsinchu City 300 Phone 49 351 88 22 0 Phone 1 858 674 8070 Taiwan Fax 49 351 88 22 606 Fax 1 858 674 8071 Phone 886 0 3 563 1388 zigbee zmd de wireless zmda com Fax 886 0 3 563 6385 General Information http Awww zmd biz Support Contact wireless _support zmda com Print date 8 27 2009 11 40 00 PM Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 124 of 124
72. an mode description section 4 11 4 Register Maximum Measured ED Scan Energy 7 0 mnemonic macScanED address OxA6 access R C code based constant address definition MAC_SCAN_ED DEER Maximum measured energy during an ED Scan Reference IEEE 802 15 4 Section 7 5 2 1 1 After an energy detection scan timeout this register contains the maximum measured energy level of the last scan The macScanED value can be assigned to an energy level Refer to section 4 8 for further information on energy detection level Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 97 of 124 ZMmMoor eene E RED Register MAC Scan Mode Configuration 1 0 mnemonic macScanMode address OxB3 access R W C code based constant address definition MAC_SCAN_MODE paar Regier en Description resar OxB3 macScanMode 1 0 0 energy detection scan 1 active scan 2 passive scan 3 orphan scan Reference IEEE 802 15 4 Section 7 5 2 This register configures the scan mode that is initiated with the macControl ScanOn command For details refer to the scan mode description in section 4 11 4 Register Scan Duration Time 23 0 mnemonic T_ScanDuration address 0xD2 OxD4 access R W C code based constant address definition T_SCAN_DURATION_1 through T_ SCAN _DURATION_3 T_ScanDuration1 Scan duration time 7 0 in symbols T_ScanDuration2 Scan duration time 15 8 in symbols T_ScanDu
73. anged Register Frame to Acknowledge Space 5 0 mnemonic T_Ack address 0xCC access R W C code based constant address definition T ACK Space between a frame and an acknowledge in symbols Reference IEEE 802 15 4 Section 7 5 1 2 This register sets the time in symbols between a frame requesting an acknowledgement and the returned acknowledge frame The default value is 12 In order to be 802 15 4 compliant it should not be changed In slotted mode the Ack frame is deferred until the next backoff period boundary Register Wait for Acknowledge Time 6 0 mnemonic T_WaitForAck address OxCF access R W C code based constant address definition T_WAIT_FOR_ACK es Register Tee Tac T_WaitForAck Wait time for an acknowledge in symbols Reference IEEE 802 15 4 Section 7 5 This register sets the maximum number in symbols to wait for the reception of an acknowledge frame after a transmitted data frame It corresponds to macAckWaitDuration defined in the Standard The default value is 120 In order to be 802 15 4 compliant it should not be changed Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 95 of 124 Lm eene E RAD Register Maximum Frame Response Wait Time 10 0 mnemonic T_MaxFrameResponse address 0xDO 0xD1 access R W C code based constant address definition T MAX_FRM_RESP_1 and MAX_FRM_RESP_2 T_MaxFrameResponse1 Maximum time to respond to a data reque
74. ata Sheet and User Manual v 1 3 August 19 2009 Page 78 of 124 reenen E RED Register PHY Transmitter Mode Register 7 0 mnemonic RTXM address 0x05 access R W C code based constant address definition TX_MODE DEER 0x05 RTXM 2 0 Tx mode 0 Normal 2 Test Mode continuous carrier 4 Test Mode continuous frame with pn code sequence TXIO mode 0 RFIO 1 RFO 5 4 SEL PA LP output power mode 0 0 dBm 1 16 dBm 2 20 dBm 3 26 dBm 7 6 Reserved The Tx mode section is used to set the transmitter to normal operation mode or to continuous transmission mode for test purposes For continuous Tx the macTxConfig register must be set to DirectTx 0x04 and the transmission is initiated by the macControl command TxOn 0x03 The TXIO mode bit determines whether the RFIO or the RFO pad is to be used as Tx output The RFO pad is used with an external power amplifier With the SEL_PA_LP the transmitter output power can be reduced Register PHY Receiver Mode Register 6 0 mnemonic RxMode address 0x08 access R W C code based constant address definition RX_MODE paar reger e OOO ooroo OOOO rea 0x08 RxMode Reserved DO NOT MODIFY 0x22 6 RxUsMode Not implemented Set RxMode 6 to 0 in EU and 1 in US mode Do not modify bits 5 0 Register Energy Detection Threshold 7 0 mnemonic EdThreshold address 0x24 access R W C code based constant address definition ED THRESHOLD ERC ECH
75. atic beacon transmission is initiated with the macControl command AutoBcTxOn A beacon frame is automatically transmitted at every T BeaconInterval symbol An interrupt is generated 27 Be2conltenval Symbols before the end of the beacon interval triggering to the software to prepare the next beacon MAC header and MSDU The ZWIR4501 must be in one of the allowed operating modes indicated in Figure 4 9 in order to enter AutoBcTx automatically Ongoing data receptions are canceled before entering the AutoBcTx mode After the transmission of the beacon frame the ZWIR4501 automatically enters either the RxActive mode and starts receiving or the Tx mode in order to resume a CSMA process that could not be completed in the previous CAP Automatic beacon transmission can be disabled with the macControl command AutoBcTxOff This command does not cause an operating mode change except during AutoBcTx where it causes the ZWIR4501 to enter the Idle mode The ZWIR4501 can be forced to Global Power Down mode at any time by setting GPD to high see Figure 4 11 It remains in Global Power Down mode until GPD is released to low The Sleep mode is entered with the macControl command Sleep The sleep duration is defined by the T General register In nonbeacon enabled operation the T General corresponds to the sleep duration followed by the macControl command Sleep In beacon enabled operation T General defines the wake up time relative to the end of the beacon interval Th
76. by the FifoStoreLQI bit in the macRxConfig register The MHR and the CRC field of the last received frame are also held in the register bank The sequence number mhrSquNbRx is used for the acknowledgement frame in the case of auto acknowledge generation The storage of acknowledge frames can be disabled by the FifoStoreAck bit in the macRxConfig register Frames not passing the CRC or frame filter check are removed from the RxFIFO at the end of the reception The macFramePend register indicates the number of frames in the RxFIFO It is incremented after each stored frame Software can read the macFramePend each time a frame is read from the RxFIFO The macFramePend Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 26 of 124 ZMmMoor eet EE content will be decremented by 1 automatically after each read access In the case that a receive interrupt is generated and the associated macRxStatus is 0x00 or 0x01 the macFramePend register can be used to check for a received frame FIFO overflow and underflow conditions are reported via an interrupt with the IRQreason FIFO The appropriate FIFO status is monitored in the macFifoStatus register For both reading from an empty FIFO and writing to a full FIFO the access is blocked by the FIFO control to prevent the FIFO content from over writing or over reading Default mode macTxConfig 6 0 Direct Tx FIFO access mode macTxConfig 6 1 0x61 mhrFc1Tx 0
77. chronization Loss Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 67 of 124 Lm The Analog Mixed Signal Company ZWIR4501 PAN Coordinator Device MCU ZMD44102 ZMD44102 MCU macCAPend 7 macGTSLength 0 macTxConfig EnSlottMode CSMA GoToRx gt p Auto BeaconTrack macControl AutoBcTxOn gt BeaconTx S B ea CON IRQ Beaconn gt macBcTrStatus Beacon gt 4 Check beacon LH RxFIFO MHR MSDU LQ gt J Rxldle macControl TxRxOff R macCAPend 7 Configure x 4 macGTSLength 0 slotted Tx mode A l macTxConfig EnSlottMode c C d CSMA A t A l macRxConfig AutoAckEn i P e FifoStoreLQI AckSpuNb v te WriteTxFrame 3 S macControl TxOn T_Beaconinterv l T_Beaconinterval gt lt 24Td_BeaconIntefval T_BeaconScanStart T x Perform CSMA T_Beaconinterval XX Xe Data Ack requested Successful CSMA Tx Tel IRQ Tx gt with acknowledgment Receive Frame J macRxStatus DataAck macTxStatus Success gt and prepare Ack 4 ___RxFIFO MHR MSDU LQl m T_Ack RxActive eg orAcl d mhrAckFc1Tx gt x A C k LEX ram macRxStatus Ack _ gt J R x _ WriteTxFrame A d macControl
78. ckEnable If the AutoAckEnable bit is set to 1 the integrated HW MAC automatically transmits an acknowledge frame after the successful reception of a frame with the acknowledge requested bit set Setting this bit in connection with the ContRx bit requires the setting of the GoToRx bit in the macTxConfig register for continuing unslotted receiving after an automatic acknowledgement transmitting ContRx If the ContRx bit is set to 1 the receiver will continue receiving after the reception of a frame Otherwise it will go to Idle mode after a frame reception Do not set this bit for beacon tracking mode Note that the AgcLvl is not stored in the AgcLvl register of the last received frame if this bit is set Using the ContRx bit together with the AutoAckEnable bit requires the setting of the GoToRx bit in the macTxConfig register for continuing unslotted receiving mode after an automatic acknowledgement transmission FifoStoreAck This bit enables the storage of acknowledge frames in the RxFIFO FifoStoreLQl This bit enables the storage of a value to calculate the link quality indicator LQI after a frame in the RxFIFO It is not recommended to use the value that is stored to the RxFIFO after the received frame to calculate the LQI value Instead of that the AgcLvl value should be used to calculate the LQI value If the AgcLvl value is used to calculate the LQI value the FifoStoreLQI bit can be set to 0 Copyright 2009 ZMD AG ZWIR4501 Data
79. d use it for debugging purposes or exception error handling routines There are three possible scenarios shown in Figure 4 2 In case A a valid command has been written to macControl Hardware successfully executes the command and resets the macControl register to 0x00 In case B a command that is undefined or invalid in the current operation mode is requested HW MAC responds with a command error setting macControl to 0x1F A command error is also indicated by an interrupt with the IRQreason CmdError and the macTimerControlStatus CmdError CmdErrorT In case C a command is valid but cannot be executed immediately because of the internal HW MAC status An example is a macControl command TxOn during an ongoing data reception The command is queued until the reception is complete and then executed The execution is indicated by the 0x00 value Only one command can be buffered while the internal HW MAC is executing the previous command Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 24 of 124 ZMmMoor meanest E EE A Valid command External write Internal clear by hardware to macControl 0x00 indicating the command valid command execution B Invalid command External write Internal set by hardware to macControl 0x1F indicating an invalid invalid command command Commana X oF C Valid command with Command is delayed execution External write accepted and Internal clear by hardware to macCont
80. de based constant address definition MSDU_TX_LENGTH msduLengthTx Transmit frame MAC payload length Reference IEEE 802 15 4 Section 5 4 3 The length of the MAC payload MAC service data unit MSDU must also be set to this register before a transmission is started by the macControl command TxOn The MSDU itself is stored in the TxFIFO This length value must only include the frame s payload and not the header length and not the CRC bytes length If the DirectFifoAccess mode is used enabled by setting the DirectFifoAccess bit in the macTxConfig register the length of the frame must be stored as the first byte into the TxFIFO and the msduLengthTx register is not used See section 4 5 for further information on the DirectFifoAccess mode The register content is retained until a new value is assigned or a reset is applied Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 86 of 124 eene E RED Register Transmit Frame MAC Header Frame Control Field 7 0 mnemonic mhrFc1Tx address 0x61 access R W C code based constant address definition MHR_TX_FC_1 Adar Register 8 ee Set 1 Frame ype ot li 2 Jemen O o o a sewe O li 5_ Acknowledgerequested O o Segel eene li Reference IEEE 802 15 4 Section 7 2 1 1 The mhrFc1Tx register contains the lower byte bit 7 0 of the MAC header frame control field of the transmit frame It must be configured before a transm
81. de can be entered again if the RTC core is running 4 11 2 Transmit Mode Tx The ZWIR4501 supports five different transmit modes plus automatic acknowledge frame generation The five transmit modes subdivide into the following modes Three slotted modes e GTS e Slotted CSMA e Slotted Direct Tx Two unslotted modes e Unslotted CSMA e Unslotted Direct Tx The transmit mode is configured in the macTxConfig register A frame transmission is initiated with the macControl command TxOn Before this command the MHR the MSDU and the MSDU length must be stored in the associated register mhrFc1Tx mhrFc2Tx and other address registers and in the TxFIFO Alternatively the complete frame including MHR and MSDU can also be stored in the TxFIFO For details about the frame handling refer to section 4 5 The ZWIR4501 maintains an internal inter frame spacing timer CT LUES T SIFS and the appropriate spacing before transmitting a frame In slotted CSMA and slotted direct Tx mode the first symbol of the transmit frame is aligned with the boundary of a backoff period where the first backoff period starts at the beginning of the superframe The duration of a backoff period can be modified in the macUnitBackOffPeriod register but should be left at the default value for standard compliance DirectTx mode can be used for direct transmission without going through the CSMA algorithm In the case of a successfully completed transmission the
82. de register monitors the current operating mode of the HW MAC Most of the operating mode changes are initiated by macControl commands Note that the common sequence is previous operating mode gt PhySwitch gt new operating mode The PhySwitch state lasts about 200 us for Rx Tx power up or turnaround For details on the different operating modes refer to chapter 4 Integrated HW MAC Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 82 of 124 reenen E RED Register Power Down 7 0 mnemonic RPD address 0x14 access R W C code based constant address definition R PWR_DWN DEER 0x14 6 0 Reserved Ox3F Set this bit to switch off the 32 kHz oscillator with GPD The RPD register is used with the GPD signal to enter and leave the Off mode refer to section O for further information on Off mode It is required to keep the reserved bits unchanged while changing bit 7 i e write the value OxBF to the register if the Off mode 32 kHz oscillator is switched off is desired after setting GPD to high 5 5 MAC FIFO Register Register Transmit FIFO 7 0 mnemonic TxFIFO address 0x80 access W C code based constant address definition TX_FIFO TxFIFO First byte of the transmit FIFO Data written to this address is moved into the TxFIFO Up to 128 bytes can be stored to the TxFIFO The TxFIFO can contain more than one frame After transmitting a frame the corresponding data is removed from the
83. dress definition MHR_RX_SEQ NO mhrSquNbRx Received frame MAC header sequence number Reference IEEE 802 15 4 Section 7 2 1 2 This register contains the MAC header sequence number of the last received frame This sequence number is used in the transmitted acknowledge frames if auto acknowledge is enabled Note that the received frames are queued in the RxFIFO address 0x81 including MAC header and payload refer to section 4 5 Register Received Frame MPDU Length 6 0 mnemonic mpduLengthRx address 0x85 access R C code based constant address definition MPDU_RX_LENGTH ERC REECH mpduLengthRx Received frame mpdu length Reference IEEE 802 15 4 Section 5 4 3 This register contains the PHY payload MAC protocol data unit MPDU length of the last received frame including two CRC bytes Register Received Frame CRC Field 15 0 mnemonic mfrCRCRx address 0x86 0x87 access R C code based constant address definition MFR_RX_CRC_1 and MFR_RX_CRC_2 mfrCRC1Rx Received frame CRC field 7 0 mfrCRC2Rx Received frame CRC field 15 8 Reference IEEE 802 15 4 Section 7 2 1 8 These registers contain the CRC sequence of the last received frame Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 93 of 124 ZMmMor eene E RED Register Receive Timestamp 23 0 mnemonic macRxTime address OxF5 OxF 7 access R C code based constant address definition MAC_RX_TIME_
84. e ZWIR4501 can be forced to exit the Sleep mode by applying a high to low transition on the GPD input see Figure 4 12 For both Sleep and Global Power Down modes the analog part and the 24 MHz crystal oscillator are shut down Only the 32 768 kHz RTC continues to run An exception arises if the clock output CLKO is configured to feed a signal derived from the 24 MHz clock during Global Power Down or Sleep mode refer to ClkOQutConfig register Under this condition the 24 MHz crystal oscillator is not shut down The ZWIR4501 provides two general purpose timer functions that can run in the background of the normal operating mode processes There are three different timer sources available for this function refer to section 4 13 The first function is the T_General timer which can be programmed to generate a timer interrupt at the time configured in the T_ General register The second function can be used to release a MAC control command at a defined time TI macControl The timer is initiated by writing a command to the macControlT register Upon execution of the macControlT command a timer interrupt is generated Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 34 of 124 Lm The Analog Mixed Signal Company ZWIR4501 Operating Modes Note The states represent the operating modes of the ZMD44101 and are spaceholders for more complex underlying FSM s and processes At this level only the mac
85. e 0xC3 Write to register address 0x1D RSTX the value 0x0B Write to register address 0x22 EDO_TRIM the value 0x96 In addition to the above for EU mode e Write to register address 0x3A CLIP_CNT_STARTSMP the value OxF0 e Write to register address 0x2B ACQ_PEAK_TH_1 the value 0x03 e Write to register address 0x2A ACQ_PEAK_TH_O the value DNA or for US mode e Write to register address 0x08 RX_MODE the value 0x62 Write to register address 0x3A CLIP_CNT_STARTSMP the value 0x78 Write to register address 0x3B CLIP_CNT_TH the value 0x04 Write to register address 0x2B ACQ_PEAK_TH_1 the value 0x04 Write to register address 0x2A ACQ_PEAK_TH_O the value 0x00 Check note of the RPCC register regarding channel 10 To reduce the power consumption it is recommended that the clock output signal be switched off Refer to section 5 16 for further information on the ClkOutConfig register settings If the ZWIR4501 is used with an external power amplifier see section 3 3 for further required startup register setup Note Please contact ZMD to receive the latest values before using the recommended values in a product release Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 119 of 124 ZMmMeoor eene E RED 6 Transmitter RF Spectrum Test Modes The transmitter RF spectrum can be measured on the RFIO or RFO pin depending upon the TXIO mode bit in the RTXM register It is highly recommend
86. e beacon frame It counts to the end of slot number 15 Register Current Slot Number 3 0 mnemonic macCurrentSlot address OxEC access R C code based constant address definition MAC_CURR_SLOT macCurrentSlot Current slot within the active superframe portion This register monitors the current slot number within the active portion of the superframe It is derived from the internal superframe timer and requires an FFD generating beacon or an RFD successfully tracking beacon Register Maximum Short Interframe Space SIFS Frame Size 6 0 mnemonic macMaxSIFSFrameSize address O0xC5 access R W C code based constant address definition BTR_MAX_SIFS_FRM_SIZE macMaxSIFSFrameSize Maximum MPDU size in octets that can be followed by an SIFS Reference IEEE 802 15 4 Section 7 5 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 112 of 124 reenen E BEE The macMaxSIFSFrameSize sets the maximum MPDU size in octets that can be followed by an SIFS period The default value is 18 In order to be 802 15 4 compliant it should not be changed Register Superframe Alignment Order 3 0 mnemonic SFalignOrder address OxC6 access R W C code based constant address definition SF_ALIGN ORDER Adar ees eege Seil SFalignOrder Superframe alignment order 3 0 The HW MAC uses the 32 768 kHz RTC to maintain the network time between two beacons This enables a slave device to
87. e current number of lost beacons during beacon tracking If this number reaches macMaxLostBeacons the beacon tracking engine generates a SyncLoss interrupt The macSyncLoss is reset to 0 after each successfully tracked beacon For details refer to the beacon tracking section 4 11 6 Register Beacon Tracking Timing Correction Threshold 3 0 mnemonic BcTrThreshold address OxC7 access R W C code based constant address definition BTR_THRESHOLD OxC7 BcTrThreshold Beacon tracking error threshold to enable the beacon 0x01 interval timing correction If the difference between the estimated beacon interval in the tracking device and the measured beacon interval of the coordinator is greater than this threshold the estimated beacon interval is corrected by the measured difference Register Beacon Scan Duration Time 23 0 mnemonic T_BeaconScanDuration address 0xD9 OxDB access R W C code based constant address definition T BCN SCAN DUR 1 through T BCN_ SCAN DUR 3 T_BeaconScanDuration1 Beacon scan duration time 7 0 in symbols T_BeaconScanDuration2 Beacon scan duration time 15 8 in symbols T_BeaconScanDuration3 Beacon scan duration time 23 16 in symbols These registers define the beacon scan duration in symbols used in the beacon tracking mode For details refer to the beacon tracking mode section 4 11 6 The default beacon scan duration after reset is 960 2 symbols i e about 3 seconds for EU mode For d
88. e done only within the active portion of the superframe That requires that the automatic beacon transmission is active for a coordinator or that a slave has successfully tracked the beacon previously All three modes GTS CSMA and DirectTx are possible in slotted mode In unslotted mode only CSMA or DirectTx are allowed TxOption Configures whether the transmission is a CSMA a GTS or DirectTx transmission A DirectTx transmission is immediately started when initiated by macControl GoToRx If bit GoTORx is set then the device will automatically do a Tx to Rx turnaround after the end of the transmission and then start the receiver It is not necessary to set this bit if the acknowledge requested bit of the mhrFc1Tx register is set It is necessary to set this bit if the ContRx bit and the AutoAckEnable bit of the macRxConfig register are set to continue receiving after an automatic acknowledgement transmission EnableSlottedAck If this bit is set then the Ack transmission in slotted mode is aligned to a backoff period boundary otherwise the slotted Ack is sent 12 symbols default value see T Ack register after the incoming frame as in the unslotted mode This bit takes effect only if the EnableSlottedMode is enabled BatteryLifeExtension This bit enables the CSMA battery life extension mode DirectFifoAccess The DirectFifoAccess mode can be used to implement proprietary frame transmission If this mode is enabled some of the integ
89. e modes The antenna must be connected via an external capacitor for DC blocking e g 22 pF The ZWIR4501 can drive an external power amplifier to increase the coverage Figure 3 6 depicts a block diagram using the ZWIR4501 with an external power amplifier T R VDD3 3 High transmit Low transmit R Active level depends on the used device Figure 3 6 Power Amplifier Configuration Block Diagram The transmitter uses the RFO pin as the RF output and the RFIO as the RF input The external power amplifier and the external RF switch can be controlled switching on or off using a flip flop and the digital transceiver outputs DAO and DA2 The digital signals DAO and DA2 provide short pulses of about 60 us duration high active that can be used together with a flip flop to determine when the transceiver is either in transmit mode or in receive mode The transceiver pins DAO and DA2 need to be configured to digital output by the following register settings after the startup register setup procedure Write to register address 0x05 the value 0x08 Write to register address 0x42 the value 0x20 Write to register address 0x52 the value 0x20 Write to register address 0x55 the value 0x05 Please see section 5 17 for further information on the recommended startup register setup 3 4 Clock Output CLKO The ZWIR4501 can provide an external clock signal on its CLKO pin for optional microcontroller timing The clock output can be configu
90. ebugging purposes firmware can force a timeout of the running beacon scan duration timer by setting T_BeaconScanDuration to 0 Note that for active and passive scans the scan duration time is set in the T ScanDuration register Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 104 of 124 feet EE EE Register Beacon Scan Start Time 10 0 mnemonic T_BeaconScanStart address OxDC 0xDD access R W C code based constant address definition T_BCN_SCAN_START_1 and T_ BCN_SCAN_START_2 ae lee Tac T_BeaconScanStart1 Beacon scan start time 7 0 in symbols T_BeaconScanStart2 Beacon scan start time 10 8 in symbols These registers are used in beacon tracking mode In beacon tracking mode the HW MAC starts to scan for the next beacon T_BeaconScanStart symbols before the expected arrival of the beacon The default value after reset is 10 symbols For details refer to the beacon tracking mode section 4 11 6 Register Timing Error Guard Time 10 0 mnemonic T_Delta address 0xE1 OxE2 access R W C code based constant address definition T DELTA_1 and T_DELTA_2 T_Delta1 Timing error guard time 7 0 in symbols T_Delta2 Timing error guard time 10 8 in symbols The T_Delta time defines the size of the guard time window to compensate for the timing error between the coordinator and the slave introduced by the crystal frequency deviation The timing error becomes important for h
91. ed The result status is indicated by the IRQ The macRXxStatus register is separated into two concurrent sections The state section monitors the current status of the Rx state machine The result section buffers the result of the last reception The result section remains unchanged until the next result update Each result update is indicated by an interrupt For details refer to the Rx mode description section 4 11 3 If the macRxStatus register contains a value of 0x00 or 0x01 after a receive interrupt it is necessary to check with the macFramePend register for a received frame in the RxFIFO Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 92 of 124 teeter EE EE Register Received Frame MAC Header Frame Control Field 15 0 mnemonic mhrFcRx address 0x82 0x83 access R C code based constant address definition MHR_RX_FC_1 and MHR_RX_FC_2 mhrFc1Rx Received frame MAC header frame control field 7 0 mhrFc2Rx Received frame MAC header frame control field 15 8 Reference IEEE 802 15 4 Section 7 2 1 1 This register contains the MAC header frame control field of the last received frame and is debugging and monitoring purposes Note that the received frames are queued in the RxFIFO address 0x81 including MAC header and payload refer to section 4 5 Register Received Frame MAC Header Sequence Number 7 0 mnemonic mhrSquNbRx address 0x84 access R C code based constant ad
92. ed in the macBcTrConfig register The early guard time is used to delay the GTS slot start The late guard time is added to transaction length for the CAP and GTS end checks Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 58 of 124 Lm The Analog Mixed Signal Company ZWI R4501 Short frame Taa aa T_SIFS T Delta Figure 4 27 Early and Late Guard Time T_Delta pus SLO dVO Hes S19 The required guard time length T Delta depends upon the beacon interval alignment status During an initial beacon interval macBcTrStatus Align bit is not set and depending upon the superframe order SO and the worst case symbol timing deviation DEV between the coordinator and a device where the superframe timing correction is not active the guard time should be set T Delta 960 2 DEV Once the beacon interval is aligned to coordinator beacon interval macBcTrStatus Align bit is set and the periodic superframe timing correction is active the guard time can be reduced to T_Delta MINIS T_ Delta 960 2 DEV symbols 4 13 General Purpose Timer Function 4 13 1 Overview The HW MAC provides 3 different timers which can be used for the following functions 1 Program a timer controlled general purpose interrupt 2 Perform a timer controlled execution of a MAC control command 3 Generate timestamps for receive and transmit frames The 3 available timers have already been introduced
93. ed that the MTP procedure be run to ensure the best RF performance before the transmitter RF spectrum test is initiated For output of a repetitive pn code sequence as is used in the preamble e Set the RTXM 0x04 for RFIO or RTXM 0x0C for RFO e Set Direct Tx mode 0x04 in the macTxConfig register e Start the transmitter by writing TxOn 0x03 to the macControl register A typical pn code sequence signal is displayed by below From this configuration the test mode pattern from pn code sequence can be changed to Continuous Carrier Output mode by setting RTXM 0x02 A typical continuous carrier signal is displayed below RBW 3 kHz RF Att 30 dp RBW 20 kHz RF Att 30 dB Ref Lvl VBW 30 Hz Mixer 20 dBm Ref Lvl VBW 200 Hz Mixer 20 dBm 10 dBm SWT 34 s Unit dBm 10 dBm SWT 5s Unit dBm DT aaa aaaea 10 Ea EJ LN LN nh 1 i gtt i SECH i LA T Tada Center 868 3 MHz 120 kHz Span 1 2 MHz Center 868 3 MHz 200 kHz Span 2 MHz Date 2 AUG 2005 13 54 18 Date 1 AUG 2005 17 09 14 Figure 6 1 Typical pn Code Sequence Signal Figure 6 2 Typical Continuous Carrier Signal Changing the RFIO to RFO or vice versa can be done only by running the sequence described above again
94. enabled Register CSMA Random Backoff Generator Seed 7 0 mnemonic CsmaSeed address OxBE access R W C code based constant address definition CSMA_SEED Addr Register i Description eset Seed value of the random backoff generator Writing to this register reinitializes the CSMA random backoff generator with a new seed Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 115 of 124 Lm eene E RAD 5 15 SPI Registers Register SPI Configuration 5 0 mnemonic SPlconfig address OxFB access R W C code based constant address definition SPICONFIG OxFB SPlconfig 7 Notinpenenes SPE SPI System Enable 0 SPI system is off 1 SPI system is on MSTR Master Slave Mode Select 0 SPI is configured as a slave 1 SPI is configured as a master CPOL Clock Polarity Select 0 Active high clocks selected SCK idles low 1 Active low clocks selected SCK idles high CPHA Clock Phase Select Only CPHA 0 mode is supported Do not change this bit SPR1 SPRO SPI Bit Rate Select Master Mode The following table shows the relationship between the SPR1 and SPRO control bits and the bit rate for transfers when the SPI is operating as a master When the SPI is operating as a slave the serial clock is input from the master therefore the SPR1 and SPRO control bits have no meaning He ke v JJ baus Copyright 2009 ZMD AG ZWIR4501 Data Sheet and Us
95. end pending data T X Perform CSMA e x Wait for the pending data Data cb E IRQ Tx xX RORA lt d macTxStatus Success R macRxStatus Data x RxFIFO MHR MSDU LQI gt __ le maa Receive Ack for lt IRQ Rx X c IRQ Tx ___ data frame a L 4 macRxStatus Ack c i macTxStatus Success gt ti d v l e e Sea Seay SS 3 Figure 4 29 MSC Unslotted Data Polling Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 62 of 124 ZMmMoor eet EE EE ZMD44102 MCU l d 1 ScanDuration Configure scan mode macScanMode ED e e RPCC Channel 0 N macControl ScanOn ED ED S c E T_ScanDuration e a S Energy detection n scan on channel 0 ED e mem IRQ Scan macScanStatus TimeOut Ride lt macControl TxRxOff Idle macScanED j k RPCC Channel 1 5 macControl ScanOn ED ED S c KS T_ScanDuration Ja Energy detection 7 scan on channel 1 ED e Km IRQ Scan macScanStatus TimeOut Rxldle macControl TxRxOff in macScanED J d e RPCC Channel 2 l e H Figure 4 30 MSC Energy Detection Scan Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 63 of 124 Lm The Analog Mixed Signal Company Beacon T_ScanDuration Beacon eb maccontroiteron Rxldle fpr corcnannet JL i macCo
96. ength of a backoff period used by the CSMA CA algorithm The default value is 20 In order to be 802 15 4 compliant it should not be changed Register Minimum CSMA CA Backoff Exponent 2 0 mnemonic macMinBe address OxB9 access R W C code based constant address definition CSMA_MIN_BE asc Renter EE Minimum backoff exponent used by CSMA CA Reference IEEE 802 15 4 Section 7 5 The macMinBE sets the minimum backoff exponent used by the CSMA CA algorithm In order to run the CSMA CA algorithm in Battery Life Extension mode macMinBE must be set to a value smaller than 3 Note that this register is initialized to 2 however the default value in the standard is 3 Software might have to initialize this value during start up Note that the range defined by the 802 15 4 standard is 0 to 3 however the HW MAC allows values up to 7 Register Maximum CSMA CA Backoff Exponent 2 0 mnemonic macMaxBe address OxBA access R W C code based constant address definition CSMA_MAX_BE a Roster See Sea Maximum backoff exponent used by CSMA CA Reference IEEE 802 15 4 Section 7 5 The macMaxBE sets the upper boundary for the backoff exponent used by the CSMA CA algorithm The default value is 5 In order to be 802 15 4 compliant it should not be changed Register CSMA_CA Initial Contention Window Size 2 0 mnemonic maclnitialCW address OxBB access R W C code based constant address definition CSMA_INITIAL_CW RECH
97. er Field 15 0 mnemonic mhrSrcPanldTx address 0x70 0x71 access R W C code based constant address definition MHR_TX_SRC_PAN_ID_1 and MHR_TX_SRC_PAN_ID_2 roar reae OOO oeron OOOO rea mhrSrcPanld1Tx Transmit frame MAC header source PAN identifier 7 0 mhrSrcPanld2Tx Transmit frame MAC header source PAN identifier 15 8 Reference IEEE 802 15 4 Section 7 2 1 5 This register stores the MAC header Source PAN identifier field for a transmit frame The mhrFc2Tx addressing mode configuration determines whether the transmit frame address field contains the source PAN identifier field The addressing field is constructed for each frame within the HW MAC frame former Register Transmit Frame MAC Header 16 bit Source Address Field 15 0 mnemonic mhrSrcAddr16Tx address 0x72 0x73 access R W C code based constant address definition MHR_TX_SRC_ADDR16_1 and MHR_TX_SRC_ADDR16 2 al reas eege fres mhrSrcAddr16_1Tx Transmit frame MAC header 16 bit source address 7 0 mhrSrcAddr16_2Tx Transmit frame MAC header 16 bit source address 15 8 Reference IEEE 802 15 4 Section 7 2 1 6 This register stores the MAC header 16 bit source address field for a transmit frame The mhrFc2Tx addressing mode configuration determines whether the transmit frame address field contains the 16 bit source address The addressing field is constructed for each frame within the HW MAC frame former Copyright 2009 ZMD AG ZWIR4501 Data
98. er Manual v 1 3 August 19 2009 Page 116 of 124 ZMmMoor eene E RAD Register SPI Master Mode Start 0 0 mnemonic SPlstart address OxFC access R W C code based constant address definition SPI_START KS i S Addr Register Description Reset SPlstart SPI master transaction start command start 0x01 This is for Master mode only SPIconfig MSTR 1 Writing 0x01 to it starts an SPI master transaction The SPItx is shifted out on the MOSI line and the received byte on the MISO line is stored in the SPIrx register The start bit is automatically reset by hardware Register SPI Transmit Byte 7 0 mnemonic SPItx address OxFD access R W C code based constant address definition SPI_TX This is for Master mode only SPlconfig MSTR 1 This register contains the SPI transmit byte The SPItx byte is shifted out on the MOSI line after the SPlistart 0x01 command Register SPI Receive Byte 7 0 mnemonic SPIrx address OxFE access R C code based constant address definition GP RX Addr Register Description Reset This is for Master mode only SPlconfig MSTR 1 At the end of an SPI master transaction started by the SPlstart 0x01 command the SPIrx register contains the data read from the MISO line Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 117 of 124 ZMmMoor eene E RED 5 16 CLKO Configuration The ZWIR4501 can provide a clock signal on its CLKO pin It
99. ertowindcator OOOO o Seu e fomaem II The macFifostatus register monitors the state of the TxFIFO and RxFIFO The TxFIFO is 128 bytes and the RxFIFO is 256 bytes The FIFO control logic blocks write access to a full FIFO and read access from an empty FIFO and they also generate an interrupt in this case For details refer to section 4 3 Register Frame Pending Number 5 0 mnemonic macFramePend address 0x88 access R C code based constant address definition FIFO_FRM_PEND Number of pending frames in the MAC RxFIFO This register contains the number of received frames queued in the RxFIFO Each time a received frame is stored in the RxFIFO the macFramePend number is increased The register content is decreased by one every time the register is read Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 84 of 124 ZMmMoor eene E RED 5 6 MAC Tx Control Register MAC Transmitter Configuration 6 0 mnemonic macTxConfig address OxBi access R W C _ code based constant address definition MAC_TX_CONFIG DESSERT 0xB1 macTxConfig 0 EnableSlottedMode oO TxOption 00 GTS 01 CSMA default 10 DirectTx s eo OoOO oo 5 Batey Lie Enes Jo e Diect Fo Access y o This register configures the different transmit modes It must be set up correctly before starting a transmission EnableSlottedMode Enables the slotted mode Slotted Tx can b
100. ess Mode description regarding mhrAckFc1Tx register section 4 5 Frame Handling Update Off mode description in section 4 11 1 Low Power Modes Rearrange section 4 11 1 Low Power Modes Update section 4 6 Link Quality Indicator LQI regarding use of AgcLvl value instead of LQI value that is stored in the RxFIFO Recommend to use the AgcLvl value to calculate the LQI value instead of the two bytes that are stored after a received frame to the RxFIFO Update section 4 7 Receive Signal Strength Indicator RSSI regarding curve and approximation equation Update section 4 8 Energy Detection Level regarding curve and approximation equation Correct section 5 17 Recommended Startup Register Setup regarding recommended setting of the EDO_TRIM register value Add information about the order of the scan mode initialization sequence 4 Jun 2007 in section 4 11 4 Scan Modes Update section 4 5 Frame Handling and description of the T SIFS and the T_LIFS register regarding limitations in DirectFifoAccess mode Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 122 of 124 Lm The Analog Mixed Signal Company 10 List of Abbreviations ADC AES IRQ Analog to Digital Converter Advanced Encryption Standard Automatic Gain Control Bit Error Rate Binary Phase Shift Keying Complementary Metal Oxide Silicon Cyclic Redundancy Check Carrier Sense Multiple Access Digital to
101. ged with care since they affect standard compliance In slotted mode the CSMA algorithm is automatically paused if it cannot be finished in the current CAP or in the first six slots following the beacons IFS in battery life extension mode If the CSMA algorithm is paused then a Tx IRQ with the macTxStatus CAfail_CAPfail is returned A paused CSMA process will be resumed automatically in the next CAP aus nableSlotted ac TxContig O Y y NB 0 CW macinitialCW BE macMinBE Locate backoff period boundary NB 0 BE macMinBE Delay for Delay for random 2 E 1 unit random 2 1 unit backoff periods backoff periods N Perform CCA on N backoff period Perform CCA boundary Channel idle Channel idle d lt EdThreshold d lt EdThreshold N N y y EEN NB NB 1 CW maclinitialCW BE min BE 1 macMaxBE BE min BE 1 macMaxBE NB gt macMaxCSMA BackOffs Y Y AA Failure a Success N s macTxStatus macTxStatu C Se Success Locate backoff period boundary d Tx frame NB gt macMaxCSMA BackOffs Y vy Failure D macTxStatus CAfail_CHbusy Figure 4 16 CSMA CA Algorithm Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Note To comply with the 802 15 4 standard do not change the registers show
102. hat the unit is not in symbols but in 1 32 768 kHz units for US and 2 32 768 kHz units for EU For more details on beacon tracking refer to section 4 11 6 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 105 of 124 reenen E RED Register Beacon Receive Timestamp 23 0 mnemonic macBeaconRxTime address OxEF OxF1 access R C code based constant address definition MAC_BCN_RX_TIME_1 through MAC_BCN_RX_TIME_3 macBeaconRxTime1 Timestamp of the received beacon 7 0 macBeaconRxTime2 Timestamp of the received beacon 15 8 macBeaconRxTime3 Timestamp of the received beacon 23 16 The macBeaconRxTime contains the timestamp of the last tracked beacon The timestamp is taken at the leading edge of the beacon frame from the timer specified in the macTimerConfig register 5 11 MAC Timer Control and Values Register MAC Timer and Control Status 4 0 mnemonic macTimerControlStatus address OxAB access R C code based constant address definition MAC_TMR_CTRL_STATUS paar Register BR Eeer Set Status is indicated by the IRQ Register MAC General Purpose Timer Configuration 3 0 mnemonic macTimerConfig address 0xB7 access R W C code based constant address definition MAC_TIMER_CONFIG O orram OOOO C r swere O OOS EE Jimem O SSS C ier setene SSCS EE TimerSelection Selects the timer that is used for the general purpose timer T General interrupt or for the ti
103. he extent ZMD deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed ZMD makes no warranty express statutory implied and or by description including without limitation any warranties of merchantability and or fitness for a particular purpose regarding the information set forth in the Materials pertaining to ZMD products or regarding the freedom of any products described in the Materials from patent and or other infringement ZMD reserves the right to discontinue production and change specifications and prices make corrections modifications enhancements improvements and other changes of its products and services at any time without notice ZMD products are intended for use in commercial applications Applications requiring extended temperature range unusual environmental requirements or high reliability applications such as military medical life support or life sustaining equipment are specifically not recommended without additional mutually agreed upon processing by ZMD for such applications ZMD assumes no liability for application assistance or customer product design Customers are responsible for their products and applications using ZMD components For further information contact ZMD AG ZMD America ZMD Far East Grenzstrasse 28 15373 Innovation Drive 1F No 14 Lane 268 D 01109 Dresden Suite 115 Sec 1 Guangfu Road Germany S
104. he standard refer to EEE 802 15 4 Section 7 5 1 1 CAP GTS Aie Inactive macCAPend 5 Superframe macGTSstart 11 macGTSlength 4 960 2S T Beaconlnterval Figure 4 24 Superframe Configuration Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 55 of 124 ZMmMoor eene E RED 4 12 Timing Correction 4 12 1 Network Timing Correction In a beacon enabled network the coordinator and the beacon tracking device share the same superframe time base The frequency deviation of the crystals leads to a timing error between the coordinator s and the device s time base This timing error will be close to zero immediate following the beacon frame and will then increase over the beacon interval The tolerable limit of the timing deviation for a coordinator defined by IEEE standard is 40 ppm The ZWIR4501 uses the 32 768 kHz crystal based RTC for the beacon tracking time base The worst case frequency deviation for a low cost 32 768 kHz crystal can be assumed to be 80 ppm Hence the total beacon interval timing deviation between coordinator and a device can be up to 40 ppm 80 ppm 120 ppm Table 4 1 shows the timing deviation at the end of the beacon interval for 120 ppm and different beacon order Beacon Order Beacon Interval Timing Deviation 120ppm in symbols in symbols in ms channel 0 61440 7 0 18 245760 29 0 74 12 3932160 472 11 80 14 157286
105. his mode is enabled by setting the UseRxFIFO bit in the macBcTxConfig register In this case the integrated HW MAC frame composition is bypassed and the complete beacon frame content including MHR and MSDU must be written to the RxFIFO see section 4 9 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 50 of 124 ZMmMoor The Analog Mixed Signal Company Automatic beacon transmission mode macControl AutoBcTxOn Tx on Tx on macAutoBcTx Status TxReady macAutoBcTx Status Tx Tx beacon Interrupt is masked IRQ by default AutoBcTx macAutoBcTx Status following beacons macAutoBcTx Status ZWIR4501 Idel Rxidle RxActive Tx macControl AutoBcTxOff disable auto beacon transmission off turnaround Tx gt Rx turnaround Tx gt Rx RxActive digital Rx on Tx resume CSMA next operating modes Figure 4 21 Automatic Beacon Generation Mode SDL Diagram Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 51 of 124 ZMmMeoor reenen E RED 4 11 6 Beacon Tracking The beacon tracking mode is used by devices in a beacon enabled network to track the beacon frames of the network coordinator The ZWIR4501 maintains the network time by its 32 768 kHz RTC allowing the ZWIR4501 to go to Sleep mode within a supe
106. icts the matching of the stored value in the register macScanED to the detected energy Refer to IEEE 8 15 4 2003 Std 1 section 6 7 7 for further information on energy detection 20 40 4 E a 60 5 a 80 4 100 0 50 100 150 200 250 300 macScanED Figure 4 7 Detected Energy Level vs macScanED register value The detected energy can be approximated from the macScanED register value by the following equation Pin dBm 0 185 macScanED 84 9 valid for 0 lt macScanED lt 255 Pin lt 85 dBm valid for macScanED 0 Pin gt 30 dBm valid for macScanED 255 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 30 of 124 ZMmMoor eene E RED 4 9 Frame Filtering The ZWIR4501 has an integrated receive frame filter with the following three filter levels e Level 1 CRC filter e Level 2 Frame type and address field filtering according to section 7 5 6 2 Rejection and Reception in the IEEE standard e Level 3 Operating mode dependent frame type filter At the 1 level frames with an incorrect CRC checksum are rejected In the 2 level the frame type address and PAN identifier are checked according to section 7 5 6 2 Rejection and Reception in the IEEE standard The reference address and PAN identifier against which the check is done must be configured in the register bank section starting from macPanld By default frames with reserved or not defi
107. igher beacon orders A beacon order 7 and a frequency deviation of 40 ppm results in 960 SCH 40ppm 5 symbols timing error at the end of a beacon interval The guard time window must be enabled by setting the EarlyGuard and LateGuard bits in the macBcTrConfig register to 1 The guard time window can be activated separately for early and late checks For early guard the start of GTS transmission is delayed by the T_Delta time For late guard the T_Delta time is added to the calculated transaction time during CAP GTS end check The guard time should be activated only in beacon enabled networks for slave devices Register Last Received Beacon Tracking Error 12 0 mnemonic macBeaconTrackError address OxED OxEE access R C code based constant address definition MAC_BCN_TRACK_ERR_1 and MAC_BCN_TRACK_ERR_2 ada Regier Desorption resar macBeaconTrackError1 Arrival time of the last tracked beacon 7 0 in RTC units macBeaconTrackError2 Arrival time of the last tracked beacon 12 8 in RTC units One RTC unit is 2 32 768 kHz in EU and 1 32 768 kHz US mode The macBeacontTrackError contains the arrival time of the last tracked beacon relative to the expected arrival time It is updated at the end of each successfully tracked beacon and is an indicator of the current beacon tracking timing error The value is signed in 2 s complement representation Positive means an early beacon arrival and negative means a late arrival Note t
108. ile RF environments The high level of integration shown below includes a thin Media Access Control MAC layer resulting in a minimum of external components and lower application costs Key Features IEEE 802 15 4 compliant ZigBee ready ISM band transceiver with RF and baseband Integrated compliant PHY and Thin HW MAC Direct Sequence Spread Spectrum DSSS Burst data rate 20 kbit s EU 40 kbit s US Transmit range 100 meter 0 dBm LoS Low power modes for battery powered devices SPI and parallel interfaces 48 pin QFN 7 x 7 mm package ZWIR4501 Complete PHY Digital Digital RX 1 Synchronization 2 Despreading 3 Demodulation 4 Digital Filtering PLL Dedicated DSP Manager Functions Digital TX Analog Transmitter 1 Spreading 2 Pulse Shaping PLL RC LPF Copyright 2009 ZMD AG Applications Home Control Building Automation Remote Metering Remote Control Wireless Sensor Networks Industrial Networks Remote Keyless Entry two way Health Monitor Networking PC PDA Peripherals Consumer Electronics Operating Data Temperature Range eeeee 40 C to 85 C Supply Voltage Core 2 44 V Supply Voltage Digital I O ee 3 3 V Supply Current Tx active 0 d m 28 mA Supply Current Rx acte 29 mA Supply Current Off Mode 1 3 pA Frequency Bands 868 MHz and 915 MHz Application Specific Thin HW MAC C
109. ime eS T MaxFrameResponse 0xD0 0xD1 Maximum Frame Response Wait Time oe o Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 72 of 124 eene E RED MAC Scan Control macScanmode 0x83 MAC Scan Mode Configuration fes T ScanDuraton Jett pi Scan Duration Time e MAC Beacon Control T Beaconinterval 0xD5 OxD7_ Beacon Interval loo macBcTxConfig OxB5 MAC Automatic Beacon Transmit Configuration macAutoBcTxStatus MAC Automatic Beacon Transmission Status 99 macBcTrConfig MAC Beacon Tracking Configuration 101 MAC Timer Control and Value OxDE 0xE0 General Purpose Timer and Sleep Time macTotalTimeFFD OxE3 OxE5 Current FFD Network Time macTotalTimeRFD OxE6 OxE8 Current RFD Network Time Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 73 of 124 eene E RED MAC Frame Filter Control 0x89 0x8A Reference MAC PAN Identifier macShortAdar Ox8B 0x8C Reference MAC Short Address aExtendedAddr Ox8D 0x94 aExtendedAddr Reference Extended 110 Address MAC Superframe and GTS Control Contention Access a CAP End Guaranteed Time Slot GTS Start meccTsenat es Guaranteed Time Slot GTS Length macMaxSIFSFrameSize OxC5 Maximum Short Interframe Space SIFS 112 Frame Size SFalignOrder Superframe Alignment Order T SIFS Short Inter Frame Spacing T LIFS Long Inter Frame Spacing MAC CSMA Control SPI Registers
110. in accordance with IEEE 802 15 4 Section 7 5 6 2 Lvl3FilterEnable Enable operating mode depending upon frame type filtering e g scan beacon track and waiting for acknowledge PanCoordinator Indicates to the address filter that the device is operating as a PAN coordinator ReservedFrameTypeEnable Enables the reception of frames with reserved frame types This is for upward compatibility ReservedFrameTypeFilterEnable If this bit is set the filter rules in accordance with IEEE 802 15 4 Section 7 5 6 2 are applied for frames with a reserved frame type Register MAC Frame Filter Status 2 0 mnemonic macFilterStatus address OxAA access R C code based constant address definition MAC_FILT_STATUS paar Register eR Desorption resar OxAA macFilterStatus jo CRC failure 1 Address Frame Type failure 2 Coordinator address failure Can be indicated by the IRQ Frame failure and CRC failure interrupts are masked by default Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 109 of 124 Teater E EE Register Reference MAC PAN Identifier 15 0 mnemonic macPanld address 0x89 Ox8A access R W C code based constant address definition AF_PAN_ID_1 and AE DAN ID 2 ERC oron OOOO rea macPanld1 Frame filter reference MAC PAN identifier 7 0 macPanld2 Frame filter reference MAC PAN identifier 15 8 Reference IEEE 802 15 4 Section 7 5 6 2 The macPanld is used a
111. is enabled by default Register CLKO Output Configuration 7 0 mnemonic ClkOutConfig address OxB8 access R W C code based constant address definition CLK_OUT_CONFIG WE ClkOutConfig Ui leg lee N 7 6 RtcDiv M This register configures the clock output on the CLKO pad The clock output depends upon the operation It can be set up differently for the Sleep Global Power Down mode and the Normal mode By default the 24 MHz divided by 4 is selected in Normal mode and the 32 768 kHz RTC clock is selected in Sleep Global Power Down mode Note that if the CLKO is configured to drive a clock derived from the 24 MHz in Sleep or Global Power Down mode the 24 MHz crystal oscillator is not powered down and therefore the low Sleep Global Power Down current consumption is not achieved in these modes SleepModeClock clock configuration in Sleep and Global Power Down mode 0 OFF 1 32 768 kHz M default configuration 2 24 MES IN NormalModeClock clock configuration in other than Sleep or Gobal Power Down mode 0 OFF 1 32 768 kHz M 2 24 MES IN default configuration Clk24Div N 24 MHz clock divider 0 divide by 1 1 divide by 2 2 divide by 4 default configuration 3 divide by 8 RtcDiv M 32 768 kHz clock divider 0 divide by 1 default configuration 1 divide by 2 2 divide by 4 3 divide by 8 To reduce the power consumption it is recommended that the clock output signal be switched
112. is used to control the ZWIR4501 The SPI provides standard lines i e MISO MOSI SCK and SSN The ZWIR4501 s SPI supports both clock polarity modes CPOL 0 and CPOL 1 and both clock phase modes CPHA 0 and CPHA 1 The setting of SPlconfig register determines which mode is used The default configuration is CPOL 0 and CPHA 0 SCK CYCLE 1 2 3 4 5 6 7 8 Reference t CPOL 0 CPOL 1 MOSI From Master No mss e Kos Koa Ks K 2 Ko K tse i Fromsiavey A MS K e Ke XK Xs KK va XX tse X x SS To Slave Figure 3 10 CPHA 0 SPI Transfer Format The ZWIR4501 uses a data transfer protocol allowing single and multiple byte read write access All bytes are transmitted using the MSB first and the LSB last If the SSN line is set to low level the IC s MISO is configured as an output pin Otherwise when SSN line is high MISO is configured as an input pin This allows other devices to use the same bus The read write protocol always starts by setting SSN slave select not to low when accessing the ZWIR4501 through the SPI and then writing two bytes to the SPI slave via the MOSI line The MSB of the first byte is the read write indicator A high bit indicates read access and a low bit indicates write access The read write bit is followed by the length 6 0 descriptor N It controls the length of the data frame D 7 0 to Dy 4 7 0 N must be in the range 1 to 127 The second b
113. ission begins For auto acknowledge generation this register must be updated by the firmware before the acknowledge frame transmission begins The use of the DirectFifoAccess mode requires enabling the acknowledge request bit for the reception of an acknowledgement frame if an automatic Tx Rx switching should be performed See section 4 5 for further information on the DirectFifoAccess mode Register Transmit Frame MAC Header Frame Control Field 15 8 mnemonic mhrFc2Tx address 0x62 access R W C code based constant address definition MHR_TX_FC_2 paar Register eR O oosporo e RECR Destination addressing mode b0 o 3 Destination adaressina mode 3 C H s Rema E e Source adaressna moase To Source addressing mode b1 o Reference IEEE 802 15 4 Section 7 2 1 1 The mhrFc2Tx register contains the upper byte bit 15 8 of the MAC header frame control field of the transmit frame It must be configured before a transmission begins For auto acknowledge generation this register is not used The MAC header frame control field 15 8 is automatically set to 0 by the HW MAC for acknowledge generation Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 87 of 124 tecnico E EE Register Transmit Frame MAC Header Sequence Number Field 7 0 mnemonic mhrSquNbTx address 0x63 access R W C code based constant address definition MHR_TX_SEQ_NO ERC oeron OOOO rea mhrSquNbTx Tran
114. it Example 5 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 14 of 124 ZMmMeoor eene E RED 3 1 Crystal Oscillator The ZWIR4501 utilizes with two crystal oscillators one for 24 MHz and one for 32 768 kHz The 32 768 kHz clock is used as a real time clock during the Sleep mode and for timing adjustments during the beacon enabled mode The 24 MHz clock is used for most of the digital blocks and as the reference frequency for the RF PLL 3 1 1 Reference Crystal Oscillator 24 MHz A 2 pin Pierce oscillator with an on chip biasing resistor provides the necessary reference frequency at 24 MHz This frequency is used for the digital clock supply timing calculations and the PLL that generates the RF carrier frequency For the receive modes the internal circuitry doubles the reference frequency to achieve the digital processing speed during code acquisition This oscillator is active only in Idle transmit and receive power modes see section 2 4 Operation Modes and Current Consumption for further details When the internal oscillator is used C4 and C5 are required as load capacitors for the parallel resonance crystal The values C4 and C5 are determined by the specific crystal used The overall load capacitance is composed of the actual values of C4 and C5 and the parasitic values of the PCB layout and the internal parasitic capacitance of the ZWIR4501 which is 0 65 pF on each pin For the recommended
115. iteTxFrame J t e T_MacControl t 60 x 2 AGO viii Timer isused k macTimerConfig gt to reduce the l TimerSel T_Superframe power consumption v L macControlT TxOn e s T_Beaconinterval XC X Delay until GTS T Die Gee Data Ack requested a gt Successful GTS Tx _ _ _ IRQ rx IRQ Tx _ gt with acknowledgment Receive Frame 2 macRxStatus DataAck macTxStatus Success gt d ACK i gt lt oT ene e RxFIFO MHR MSDU LQI T TASS T Wait mhrAckFc1Tx gt x lg S A C K m S 4 4 IRQ r a macRxStatus Ack gt RxActive 3 e WriteTxFrame gt A d macControl TxOn L Unsuccessful Tx e I IRQ Tx _ GTS is gone ti e macTxStatus GTSfail J _p Prepare lt RQ AutoBcTx v next beacon lt i e O WriteTxFrame __ T_Beacon Auto ae Beacon ScanDuration BeaconTx X IRQ B cb BeaconTrack SE a a a E Figure 4 36 MSC Slotted Tx Rx in GTS In this example a superframe configuration is used as it is shown in Figure 4 24 and the device transmits its data in the firs t slot of its GTS slot 11 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 69 of 124 Lm The Analog Mixed Signal Company ZWIR4501
116. l Power Down GPD input and a reset not RSN input The ZWIR4501 s SPI can be connected to an MCU s hardware SPI implementation or it can be controlled by an MCU s I O lines It is recommended that an input port that can be handled by interrupt control be used for the IRQ line By default both the parallel interface and the SPI in slave mode are available For proper operation the unused interface must be disabled The parallel interface is disabled by setting RD WR and ALE to high and putting the DataAddress 7 0 bus into High Z state The SPI is disabled by setting SSN to high The interfaces can be used only if the transceiver s digital core is active Please see section 2 4 for further information on operating modes Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 18 of 124 ZMmMeoor eene E RED 3 5 1 Power Up The ZWIR4501 s power up sequence and its timing are shown in Figure 3 8 Von J Mode PoR Y RTC Power up Idle 3 ms t 730 ms RTC pwr up Figure 3 8 Power Up Sequence For best performance results set the trim values of the ZWIR4501 after the power up sequence Refer to section 5 17 for configuring ZWIR4501 s trim values after the power up sequence The power up time of 730 ms is needed to settle the 32 kHz RTC osc After this time the ZWIR4501 is fully functional The registers can be accessed after POR For some functionality the RTC is required e g beacon
117. lator is shut down to reduce the power consumption The RTC is running during the Global Power Down and Sleep modes maintaining the network time This enables the ZWIR4501 to go to Sleep mode at any time within a superframe without losing track of the superframe time if operating as a slave device Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 23 of 124 ZMmMoor reenen E RED 4 2 Block Diagram Tx Data Path phy frame byte to bit diff encode spreading pulse shape CRC HI MAC Frame TxFIFO peau K Beacon Gen PHY Tx Control Global Power Down Sleep Timer TotalTime Superframe RxDefer IFS Ack WaitForAck Rx MaxFrameResponseTime Scan Scan BeaconTrack General Purpose AutoBeaconTx Mac Controller Clock Control Tx PHY Rx Control Rx Data Path ED carrier sense acquisition down convert despread diff demod RxFIFO Beacon TxFIFO 256x8 Mac Frame Decomposition Figure 4 1 Digital Core Block Diagram 4 3 MAC Control The HW MAC layer is controlled via the macControl register by a set of defined commands most of which are operating mode dependent The HW MAC also uses the macControl register to provide feedback to the software about command acceptance status After a command release the MCU can read this information an
118. ld set the HW MAC will start a timer T_MaxFrameResponse and wait for the reception of a frame If no data is received within this time an Rx interrupt is generated and the macRxStatus is PollNoData In slotted mode the T_MaxFrameResponse timer will count only CAP symbols If the polled data is not received within the CAP and the T_MaxFrameResponse has not expired an Rx interrupt is generated and the macRxStatus is PollCAPend In this case the T_MaxFrameResponse is paused and the polling process is automatically resumed in the next CAP entry D Figure 4 18 There are several additional ways to exit the Rx mode via macControl commands or timer expirations It is important that an ongoing reception is not interrupted before exiting the Rx mode The expiration of the T BeaconInterval timer has higher priority than any other commands and it causes the ZWIR4501 to enter either beacon tracking or automatic beacon transmission mode automatically depending upon which mode is active The switch to automatic beacon transmission cancels ongoing receptions The macControl commands TxRxOff AutoBcTxOn and TxOn also cause the ZWIR4501 to exit the Rx mode and to enter Idle AutoBcTx or Tx mode respectively Note that the macRxStatus registers are separated into two concurrent sections One section indicates the current processing state and the other shows the result of the last reception For instance if a frame has been received and the receiver continues in
119. ls of the coordinator and the slave The expected end of the current beacon interval is when the macTotalTimeRFD registers are 0 For more details on beacon tracking refer to section 4 11 6 The RFD uses the RTC clock to maintain its network time allowing the device to go into Sleep mode and Global Power Down mode the 24 MHz crystal between two beacons without loosing track of the network time Therefore macTotalTimeRFD is derived from the RTC Note that its unit is 2 32 768 kHz in EU and 1 32 768 kHz in US Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 108 of 124 eene E RED 5 12 MAC Frame Filter Control Register MAC Frame Filter Configuration 3 0 mnemonic macFilterConfig address OxB6 access R W C code based constant address definition MAC_FILT_CONFIG al Resist eR Seege Il OxB6 macFilterConfig 0 Lvi1FilterEnable Lvi2FilterEnable a PanCoordnator 7 4 ReservedFrameTypeEnae 3 5 ReservedFrameTypeFiterenae o Lvl1FilterEnable Enable CRC filter Frames with CRC failure are ignored and removed from the RxFIFO Use of the default filter configuration is recommended in order to be IEEE 802 15 4 compliant For proprietary solutions it is recommended that at least this bit is set to avoid false alarms Lvl2FilterEnable Enables frame type and address filter Frames with illegal frame type and illegal addresses are ignored and removed from the RxFIFO The filter rules
120. macControlT execution time 23 16 These registers set the execution time of the MAC control command buffered in macControlT The timer from which the execution time is derived must be running and can be selected from the macTimerConfig register For details refer to the general purpose timer section 4 13 3 Register General Purpose Timer and Sleep Time 23 0 mnemonic T_ General address O0xDE OxE0 access R W C code based constant address definition T_GENERAL_1 through T GENERAL 3 aac be Description resar T_General1 Sleep time 7 0 in RTC units or general purpose timer T_General2 Sleep time 15 8 in RTC units or general purpose timer T_General3 Sleep time 23 16 in RTC units or general purpose timer One RTC unit is 2 32 768 kHz in EU and 1 32 768 kHz US mode These register define the sleep time duration in RTC units or the timer value of the general purpose timer T_General The source of the general purpose timer is selected in the macTimerConfig register For details refer to the Sleep mode section 0 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 107 of 124 ZMmMor eene E RED Register Current FFD Network Time 23 0 mnemonic macTotalTimeFFD address 0xE3 OxE5 access R C code based constant address definition MAC_TOT_TIME_FFD_1 through MAC_TOT_TIME_FFD_3 macTotalTimeFFD1 Current network time of a FFD 7 0 in symbols macTotalTimeFFD2
121. mer controlled macControlT command execution Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 106 of 124 ZMmMoor reenen E RED TimestampSelection Selects the timer from which the receive and transmit timestamp is derived Timer T_TotalTimeFFD This is a 24 bit timer with symbol time resolution EU mode 50 us US mode 25 us and is driven by the external 24 MHz crystal It either is started automatically by the beacon transmission or it needs to be started stopped by the macControl command TotalTimerStart TotalTimerStop in nonbeacon mode operation Note that during Sleep and Global Power Down modes the 24 MHz crystal oscillator is stopped and as a result this timer is paused T_TotalTimeRFD This timer is driven by the 32 768 kHz crystal and has a resolution of 1 32 768 kHz US or 2 32 768 kHz EU The timer is available only in beacon tracking mode It is a count down timer which counts down from the estimated beacon interval to zero T_Superframe This timer counts the symbols of the active portion of the superframe starting from zero It is available only in slotted mode Register macControlT Command Execution Time 23 0 mnemonic T_MacControl address 0xC9 OxCB access R W C code based constant address definition T_MAC_CTRL_1 through T_MAC_CTRL_3 T_MacControl1 macControlT execution time 7 0 T_MacControl2 macControlT execution time 15 8 T_MacControl3
122. mmands respectively For power efficiency use of the macControl command TxRxOff is recommended after a tracked beacon Beacon tracking can be deactivated with the macControl command BcTrOff from Idle Rxldle RxActive Tx and BeaconTrack mode From BeaconTrack the Idle mode starts For the other modes BcTrOff does not produce an operating mode change Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 53 of 124 ZMmMoor The Analog Mixed Signal Company ZWIR4501 Beacon tracking mode RL 17 idel Rxidle ES i RrActve Rxldle 1 RxActive BeaconTrack Enable beacon tracking RxDefer Tx pe no ayne beacan Direct ZMD44102 into sleep oquired at this moment mode while being in beacon 4 i v ZMD44102 first scans for tracking mode beacon has vY Y Y E macControl h beacon been successfully acquired macControi macControl macControl BcTrOn before BoTrSieep BcTrOff BcTrot _ EnableTra v i A gt a al Jr se lt lt CSMA pending analog Rx on mm weit yes TARx off d b d ri power down Frames not passing the all CRC check or frame coe filter are by default Kee F automatically removed E from the Rx
123. mode and GPD Do not supply DVDD_ 2 4 before DVDD_3 3 to the IC 3 5 2 Reset RSN The ZWIR4501 can be reset by using the RSN pin pin 19 This pin is active low i e setting this line to low starts the reset procedure The reset procedure and its timing are shown in Figure 3 9 Joen hold trsn ret 100 ps Figure 3 9 Reset Sequence Table 3 1 gives the values for the RSN hold time trsy in different operating modes Mode RSN hold time trsn hold Idle TX or Rx mode tRsn hold 1 500 US Sleep or Global Power Down RSN hola 2 3 MS Off mode RSN hold 3 730 ms Table 3 1 Reset Timing Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 19 of 124 ZMmMoor eene E RED For best performance results set the trim values of the ZWIR4501 after the reset sequence Refer to section 5 17 for further information on the recommended trim values See section O for further information on low power modes 3 6 Synchronous Serial Peripheral Interface SPI The SPI is used by default in slave mode The master mode is not described by this document If the master mode is desired please contact ZMD for further information The SPI is configured via the SPlconfig register The SPlconfig register can be used to switch the interface to master mode to operate with another slave and to select the clock phase and clock polarity modes In that case the parallel microcontroller interface
124. n T_WaitForAck set T_MaxFrameResponse WaitForFrame process will resume in the next CAP macScanStatus Scan duration timed out ActiveTxFail Active scan command transmission failed OrphanTxFail Orphan scan command transmission failed SyncLoss Number of macMaxLostBeacons beacons lost during macBcTrStatus beacon tracking Beacon Beacon frame received during beacon tracking CoordAddrFail Beacon frame with received source address not matching the coordinator address Auto BcTx TxReady TxReady Indicate to firmware to prepare the next beacon macAuto Beacon transmission is finished BeTxStatus FIFO TxUnderflow Read access from the empty TxFIFO macFifoStatus EE Write access to the full TxFIFO RxUnderflow Read access from the empty RxFIFO RxOverflow Write access to the full RxFIFO CRC CRCfail Frame with CRC failure received macFilterStatus Frame fail Frame received which failed the Address FrameType check Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 76 of 124 Teater ZMIR4501 Register Interrupt Condition Mask 30 0 mnemonic IRQmask address 0xAD OxBO access R W C code based constant address definition IRQ_MASK_1 IRQ_MASK_2 IRQ_MASK_3 IRQ_MASK_4 address Register Bit Reason Condition Reset i oR mw Jo a fe meou o a fe Premed o s e Pomona o e mx Focare o le e o Ts Ts Tk SG SES OxAF IRQmask3 0 Scan Da
125. n in italics a Success gt macTxStatus Success a Tx frame gt x Page 42 of 124 ZMmMeoor The Analog Mixed Signal Company 4 11 2 2 MHR Address Field Composition ZWIR4501 The transmit frames are formed within the framer module of the ZWIR4501 The MHR is taken from the appropriate registers mhrFc1Tx and following the MSDU is taken from the TxFIFO and appended to the MHR and the frame is then appended to the CRC field and fed into the PHY layer The address field content and length within the MHR depends upon the different addressing mode and frame type settings of the frame control field mhrFc1Tx and mhrFc2Tx The different address field combinations are shown in Figure 4 17 FrameControl 6 11 10 Intra Pan DstAddr Mode irrelevant Beacon AddressField 3 b000 irrelevant irrelevant IntraPan 1 b1 nolntraPan 1 bO IntraPan 1 b1 nolntraPan 1 bO noPanld Addr 2 b00 no Id Addr 2 b00 SrcPanid 16bit 2 b10 64bit 2 b11 SrcPanid SrcPanlid irrelevant IntraPan 1 b1 nolntraPan Data 1 b0 Cmd default IntraPan 1 b1 nolntraPan 1 bO no Id Addr 2 b00 64bit 2 b11 DstPanld DstPanld DstPanld DstPanld DstPanld irrelevant IntraPan 1 b1 nolntraPan 1 bO IntraPan 1 b1 nolntraPan 1 bO no Id Addr 2 b00 DstPanld DstPanld DstPanld DstPanld DstPanld default SrcPanld SrcPanld
126. n interval in RTC units T_Beaconinterval T_Beaconinterval 40 32 768 Internally converted by HW MAC T_Superframe symbols 3 T_TotalTimeRFD RTC units macTotalTimeRFD T_BeaconInterval current timing deviation macCurrentSymbolTime T_Beaconinterval new timing deviation 9607280 4 macBeaconTrackError _ new timing deviation 8 Acti 8 ctive g Superframe ege g a a Sot o 1 27 3 4 5 6 7 9 10 11 12 13 14 15 0 960 250 gt i T_Beaconinterval coordinator gt new timing deviation lt T_Beaconinterval current timing deviation device T_BeaconScanStart macnelr Scan Track Scan Beacon Status y IRQ with IRQ with IRQreason BcTr IRQreason BcTr Figure 4 22 Beacon Tracking Timing The size of the active superframe is adjusted by the macSuperframeOrder SO The network time is monitored by the macTotalTimeRFD register in RTC units 1 32 768 kHz US 2 32 768 kHz EU The start value is the beacon interval minus the estimated timing deviation The value zero is assigned to the expected arrival time of the next beacon frame The arrival time of each tracked beacon frame can be read from the macBeaconRxTime register It is a signed value in RTC units indicating the deviation from the expected arrival time A positive value signifies early arrival and a negative
127. nd the dynamic range further the LNA and mixer gain can be adjusted in the AGC loop In normal operation mode the user or the MAC initiates the reception using the default register values All control signals timing power down are set automatically Transmitter Chain A direct conversion architecture is used for the transmitter of the ZWIR4501 The design is fully differential Only the power amplifier PA output is single ended No external balun is required In normal operation mode the user or the MAC starts the transmission using the default register values All control signals timing power down are set automatically Optionally two default register settings of the transmitter can be changed by writing to the Transmitter Mode Register RTXM By default the internal PA drives 0 dBm 1 mW to a 50 Ohm off chip load This output power can be changed by register settings between 0dBm and 26dBm Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 7 of 124 ZMmMoor reenen E RED 1 4 Pin Assignment Figure 1 2 shows the pin assignment for the ZWIR4501 DVDD_2 4 39 DVDD_ 3 3 48 ATEST3 47 ATEST4 ATEST2 ATEST1 AVDD AVSS ZWIR4501 48 QFN MLF AVDD AVSS RFIO TOP VIEW AVSS RFO AVDD XTAL1 Ground plane at bottom side XTAL2 ETA D D x Je O D I Oo RFTESTPWR DVDD_2 4 Dvpb_24 20 Figure 1 2 Pin Assignment
128. ned frame types are rejected by the level 2 filter For forward compatibility however frames with reserve frame types can be allowed by setting the ReservedFrameTypeEnable bit in the macFilterConfig register In this case the filter rules defined in the section 7 5 6 2 Rejection and Reception in the IEEE standard can also be applied to frames with a reserved frame type by enabling the ReservedFrameTypeFilterEnable bit in the macFilterConfig register The 3 level is an operating mode dependent frame type filter It performs the following filtering Reject all non acknowledge frames while waiting for an acknowledgment Reject all nonbeacon frames in beacon track mode during the beacon scan phase Reject all nonbeacon frames during active and passive scan Reject all non command frames during orphan scan 0000 By default all three filter levels are enabled For debugging purposes or for promiscuous mode operation the three different frame filter levels can be disabled independently in the macFilterConfig register Frames that do not pass a filter level are rejected and automatically removed from the RxFIFO at the end of the reception For debugging purposes an interrupt can be enabled in the IRQmask register indicating frames not passing the filter levels 1 and 2 Note that the frame filter interrupt is independent of the frame filter activation e g the level 2 filter can be disabled in macFilterConfig but an interrupt can still be genera
129. ntrol ScanOn __ Idle Beacon T_ScanDuration ZMD44102 Ss mo o voy e T_ScanDuration e macPanld 0xFFFF macScanMode Passive RPCC Channel 0 macControl ScanOn IRQ Scan Rx gt gt macScanStatus Beacon gt RxFIFO MHR MSDU LQI gt macControl ScanCont IRQ Scan Rx gt macScanStatus Beacon gt RxFIFO MHR MSDU LQI gt macControl ScanOff IRQ Scan Rx gt macScanStatus Beacon gt RxFIFO MHR MSDU LQI gt macControl ScanCont IRQ Scan _ gt macScanStatus TimeOut gt ZWIR4501 gt Configure scan mode e L Read beacon and continue scan za 1 Read beacon and finish scan ri Read beacon and continue scan D Scan end due to time out D Rxldle SS macControl TxRxOff _ SESS Figure 4 31 MSC Passive Scan Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 gt Passive gt scan on channel 0 Passive scan on channel 1 Page 64 of 124 Lm The Analog Mixed Signal Company ZMD44102 Perform CSMA Rxldle Idle Perform CSMA xX Beacon request _ gt command B a C ON T_ScanDuration xX x RxlIdle Idle T_ScanDuration
130. ntrolT and execution of the last command 0x00 down analog front end refer to section 8 0x05 ScanOn Start scan mode 0x06 ScanOff Stop scan passive active orphan scan only 0x07 ScanCont Continue scan passive active orphan scan only 0x08 BcTrOn Start beacon tracking slave only 0x09 BcTrSleep Go into Sleep mode until next beacon slave only Ox0A BcTrOff Stop beacon tracking Confirm the tracked beacon as valid beacon tracking mode Tracked beacon is not valid beacon tracking mode coordinator only coordinator only beacon transmitting devices beacon tracking devices that was stopped by a data reception 0x17 GeneralTimerStart Activate the T_General timer 0x18 GeneralTimerStop Stop the T_General timer 0x19 TxFast Request a transmission without CSMA that quickly follows an Ack frame 802 15 4 7 5 6 3 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 81 of 124 eene E RECHT Addr Register Command Description Reset 0x1F CmdError Command error set by hardware indicating an invalid command either not defined or not appropriate in the current operating mode Reserved by hardware The macControl register is the main control interface to the integrated HW MAC It uses a set of commands to control the HW MAC operating modes The NoCmd 0x00 and CmdError 0x1F commands are reserved by the hardware for feedback information If a command is written t
131. o the macControl register hardware first checks whether it is valid in the current operating mode If the command is not valid the macControl is set to CmdError Ox1F If the command is valid it will remain in the macControl register until it can be accessed and executed After it is accessed the macControl is reset to NoCmd 0x00 The macControl register can queue one another command that is executed after the previous command has been completed For detailed information on the different operating modes and related commands refer to section 4 11 Operation Mode Description Register MAC Operating Mode 3 0 mnemonic macOpMode address 0xA2 access R C code based constant address definition MAC_OP_MODE OxA2 macOpMode 0x00 Idle Idle mode analog front end power down 0x00 0x01 PdnSleep Sleep or Gobal Power Down mode only 32 768 kHz clock running this OpMode cannot be read via SPI 0x02 Tx Transmit mode 0x03 Rxldle Receiver Idle mode analog Rx is on digital Rx is idle 0x04 RxActive Receive mode acquisition reception running 0x05 ScanTx Scan mode Tx active orphan scan while transmitting 0x06 ScanRx Scan mode Rx while scanning receiving 0x07 ScanAck Scan mode Ack transmission orphan scan realignment command acknowledgment 0x08 BcTr Beacon Tracking mode beacon scanning 0x09 AutoBcTx Automatic beacon transmission is ongoing Ox0A PhySwitch Inter operating mode step to switch the PHY state The macOpMo
132. oceed If acknowledgment is requested and AutoAckEnable is asserted in macRxConfig the Tx mode starts exit C Figure 4 18 and an acknowledgment containing the sequence number of the received frame is transmitted The HW MAC develops the frame to acknowledge spacing T_ Ack Software must set the frame pending bit in the frame control field mhrAckFc1Tx within this period If the received frame does not request an acknowledgment or the AutoAckEnable bit is not set either the analog receiver is powered down and the ZWIR4501 returns to Idle mode or depending on the ContRx bit in the macRxConfig register a new acquisition cycle starts The interframe spacing timer IT_LIFS T_SIFS is started at the end of the received frame If the receiver starts from the Tx mode entry A Figure 4 18 the HW MAC waits T_ WaitForAck symbols for the reception of an acknowledge frame If no acknowledge frame is received within this time an Rx interrupt is generated with the associated macRxStatus AckTimeOut If an acknowledgment has been received in time the acknowledge frame is stored in the RxFIFO The MHR is also stored in the register bank Storage of the acknowledge frame in the RxFIFO can be disabled in the macRxConfig register The ZWIR4501 provides support for the MLME POLL primitive which can be enabled by the WaitResponseEnable bit in macRxConfig If this support is enabled and the received acknowledgment has the frame pending bit in the MHR frame control fie
133. og ground RTC1 Analog input 32 768 kHz crystal oscillator input RTC2 Analog output 32 768 kHz crystal oscillator output ATEST4 Analog I O Analog test pin 4 no connection ATEST3 Analog I O Analog test pin 3 no connection Ground Ground plane at bottom side Table 1 1 Pin Descriptions Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 9 of 124 ZMmMor eene E RAD 1 6 System Performance Summary Parameter Value 600 kHz EU and 1200 kHz US Renan EE Phase Locked Loop PLL Sigma delta fractional N i Oper ations ESD Protection gt 2 kV Human Body Model HBM External Components 24 MHz and 32 768 kHz XTAL PLL loop filter RC antenna microcontroller Process Technology 0 25 um CMOS Table 1 2 System Performance Summary Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 10 of 124 eene E RED 2 Device Specification Unless otherwise noted typical values for electrical characteristics over the full range of operating conditions are as follows AVDD DVDD_2 4 2 4 V DVDD_3 3 3 3 V Ta 27 C 2 1 Recommended Operating Conditions ae Digital supply voltage DVDD_2 4 2 2 2 4 2 7 core Digital O supply volage ovon 29 30 3a se vs See t an ar wes e foa Frequency of operation 868 3 MHz EU 906 MHz to 924 MHz US 2 2 Absolute Ma
134. on on CLKO Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 15 of 124 ZMmMeoor eene E RED 3 2 RF Phase Locked Loop A fractional N phase locked loop PLL architecture is used by the ZWIR4501 All functions are integrated on chip except the loop filter The external loop filter circuitry is depicted in Figure 3 4 The 24 MHz crystal see section 3 1 1 provides the reference frequency for both EU and US bands LEE CP LPF_VCO Lk O 1 6k 5 2 2k 5 400pF 5 3 9nF 5 470pF 5 rps CT ool Figure 3 4 PLL Loop Filter In normal operation mode the user sets the frequency channel of the RF PLL before transmission or reception by writing to the phyCurrentChannel register RPCC The data rate EU 20 kbit s US 40 kbit s is adjusted automatically according to the selected channel The channel numbers are defined by the IEEE 802 15 4 standard 1 Figure 3 5 illustrates the channel allocation in the 900 MHz band Channel 0 Channels 1 10 TT 868 3 MHz 902 MHz 928 MHz Figure 3 5 Channel Allocation in the 868 and 915 MHz Bands Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 16 of 124 ZMmMoor eene E RED 3 3 Antenna Connection and Power Amplifier Configuration By default the receiver input and the transmitter output use the same pin RFIO The integrated antenna switch disconnects the respective components in transmit and receiv
135. oniroller Sensor e Frame composition and decomposition e Automatic acknowledge generation Additional MAC functions e CRC check and Protocol implementation generation e Automatic beacon generation and tracking e Set of timer e Host interface ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 iy ay Network support Upper layer functionality Application Interfaces sensor 32 768 kHz All rights reserved The material contained herein may not be reproduced adapted merged translated stored or used without the prior written consent of the copyright owner The information furnished in this publication is preliminary and subject to changes without notice Lm The Analog Mixed Signal Company Table of Contents 1 General Device Description ccsseeeeeecesteeeeeeeeeeeeeeseaeseneeeenseeeeeeeeessaeseseeeeeeseeescaeseseeeenseeeeenees NNEN 12 TEEN L RF Frontengd Description ssrin S NEES NENNEN dee E TI lu 1 5 PIMIDSSCKIPUON DEE 1 6 System Performance Gummanm ccc eee eeenee eee eeeneeeeeeaaeeeeeeaeeeseeaeeeeeeiaeeeseeneeeeeneaes E we E 2 1 Recommended Operating Conditions 00 0 0 ce ceeeceeeeceeeeeeeeneeeeeeaeeeeeeaeeeseeeaeeeseenaeeeeneaes 2 2 Absolute Maximum Rag Seccion aE AAE R 2 9 RR e EC IR 2 4 Operation Modes and Current Consumpton Indie Rn TE 2 6 RE Parameter Summaya EA a EASdE Sek E ATANA 3 Application Circuit and External Component
136. ons are completed first The macBcTrStatus register contains two additional bits indicating the current status of the integrated beacon interval timing correction After each initial beacon i e the first beacon after starting the beacon tracking or the first beacon received after a synchronization loss the Sync bit will be set in the macBcTrStatus register For each subsequent successfully tracked beacon the Align bit and the Sync bit will be set in the macBcTrStatus register indicating that the HW MAC is keeping track of the coordinators beacon interval and that the internal beacon interval timing correction is active For details about the integrated timing correction refer to section 4 12 and 4 12 From Idle mode the ZWIR4501 can be sent into Sleep mode by the BcTrSleep command to reduce power consumption The analog part including the 24 MHz crystal oscillator is powered down The ZWIR4501 s 32 768 kHz RTC keeps track of the network time and wakes up and returns to the beacon tracking mode T BeaconScanStart symbols before the estimated end of the beacon interval in order to track the next beacon frame The wake up is indicated by a WakeUp interrupt As mentioned above the Rxidle state starts after the scan phase In Rxldle the digital core is idle but the analog receiver is powered up This enables a fast receiver start via the macControl command RxOn The Tx and the Idle modes can be initiated via the macControl command TxOn and TxRxOff co
137. or the beacon 0x04 SyncLoss Loss of synchronization number macMaxLostBeacons of consecutive beacon missed 0x08 Beacon Beacon successfully tracked 0x10 Beacon tracked with wrong SrcAdadr possible CorrdAddrFail macPanID conflict 0x20 Sync Initial beacon tracked 0x40 Align Consecutive beacon tracked automatic timing correction is active Status indicated by the IRQ The macBcTrStatus register monitors the beacon track status The loss of synchronization and the arrival tracking of a beacon are indicated by interrupts For details refer to the beacon tracking mode description section 4 11 6 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 102 of 124 reenen E RED Register Coordinator Short Address 15 0 mnemonic macCoordSrcAddr address 0x95 0x96 access R W C code based constant address definition COORD_SRC_ADDR_1 and COORD_SRC_ADDR_2 rs EREH macCoordSrcAddr1 Coordinator reference short address 7 0 macCoordSrcAddr2 Coordinator reference short address 15 8 Reference IEEE 802 15 4 Section 7 5 4 1 If the CoordAddrCheck is enabled in the macBcTrConfig register the short source address of the incoming beacon frames are compared to the macCoordSrcAddr to determine if the incoming beacon is meant for the device See description of the macBcTrConfig register for further information Register Coordinator Extended Address 63 0 mnemonic macCoordExt
138. owledgment feature is enabled with the AutoAckEnable bit in the macRxConfig register If the macControl command TxRxOff is sent after a frame and before the expected acknowledgment frame the reception of the acknowledgment is cancelled In such a situation no receive interrupt is issued and the macRxStatus register reports that the receiver is switched off by containing the value 0x00 The macControl command TxRxOff does not have any influence on the acknowledgement frame reception once the reception of the acknowledgment has been started In this case the entire acknowledgement frame is received and an interrupt is generated with IRQreason 0x02 macRxStatus 0x10 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 40 of 124 ZMmMoor The Analog Mixed Signal Company ZWIR4501 Tx mode Automatically BeaconTrack Idle ctive digital Rx on AutoBeaconTx Tx Rx off Rxlidle analog Rx on y macControl macControl TxOn TxOn resume a paused CSMA proccess previous operating modes RxActive auto ack power up turnaround TxOption turnaround Rx gt Tx sls macTxConfig 2 CSMA direct CSMA b d vv v AA y macTxStatus macTxStatus macTxStatus o mn macTxStatus macTxStatus GTS SItCSMA SitDir UnSItDir Ack Y v y CFP CAP CAP AA KL T
139. pecification extracted from the payload of the tracked beacon frame The active portion of each superframe is divided into 16 slots each of which is composed of a contention access period CAP and a contention free period CFP The CAP always commences immediately after the beacon frame and extends until the end of the slot defined in the macCAPend register Note that the standard requires a minimum CAP length of 440 symbols A transmission using slotted CSMA mode will be located within the CAP automatically by the ZWIR4501 A CAP transaction that cannot be completed before the CAP end is not executed and generates a failure status in the macTxStatus register The CFP can follow the CAP Within the CFP one or more guaranteed time slots GTS can be assigned The GTS starts with the slot number macGTSstart and has a length of macGTSlength This value must not exceed the number of slots from the beginning of the GTS to slot 15 If macGTSlength is set to 0 then no GTS is assigned and the macGTSstart value is ignored If macGTSlength is greater than 0 macGTSstart must be greater than macCAPend GTS transmissions are located within the GTS automatically by the ZWIR4501 A GTS transaction which cannot be completed before the GTS end is not executed and generates a failure status in the macTxStatus register For details on the Tx mode and the GTS CAP transaction checks refer to section 4 11 2 For details about the superframe structure requirements of t
140. perframeOrder d T_BeaconScanDuration d and beacon Td_Beaconlnterval gt l _ __T_BeaconScanStart track mode meau engh ix l e 4 macBcTrConfig TrackEnable 7 d macTxConfig EnSlottMode CSMA mhrFx2Tx mhrSquNbTx macControl BcTrOn Write beacon _ mhrSrcPanldxTx e frame mhrSrcAddrxx_xTx B C TxFIFO MSDU gt S t macTxConfig CSMA EnSlottMode gt T Beacon macRxConfig default _ gt T ScanDuration macControl AutoBcTxOn r Auto a BeaconTx c Beacon 4 d IRQ Beacon Rx gt R IRQreason Beacon gt T_BeaconInterval X S macBcTrStatus Beacon gt Check beacon A 24Td_BeaconInterval T_Beaconintervat RxFIFO MHR MSDU LQI l T Beacon cantan d macControl TxRxOff J a gt d e IRQ Beacon l SXT_Beaconinterval IRQreason AutoBcTx e l Prepare J d next beacon msduLengthTx mhrSquNbTx l TxFIFO MSDU S Auto BeaconTx i R T_Beacon Be CON mam ScanDuration IRQ Beacon Rx gt Rxlidle J IRQreason Beacon gt macBcTrStatus Beacon gt RxFIFO MHR MSDU LQI macControl TxRxOff Le Been Sam Figure 4 33 MSC Basic Beacon Transmission and Tracking Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 66 of 124 Z Moor The Analog Mixed Signal Company ZWI R4501
141. ransmit Timestamp 23 0 mnemonic macTxTime address OxF8 OxFA access R C code based constant address definition MAC_TX_TIME_1 though MAC_TX_TIME_3 Timestamp of the transmitted frame 7 0 Timestamp of the transmitted frame 15 8 Timestamp of the transmitted frame 23 16 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 90 of 124 ZMmMoor eene ZMIR4501 The macTxTime registers contain the timestamp of the last transmitted frame The timestamp is taken at the leading edge of the frame from the timer specified in the macTimerConfig register 5 7 MAC Rx Control Register MAC Receiver Configuration 6 0 mnemonic macRxConfig address OxB2 access R W C code based constant address definition MAC_RX_CONFIG rar reger 6k Description OO fresa OxB2 macRxConfig mn WaitResponseEnable oo AutoAckEnable E RER 5 FoStoreTimeSiamp o To 6 AckSquNeChecknable U WaitResponseEnable This bit enables support for the MLME POLL primitive Reference IEEE 802 15 4 Section 7 1 16 If the receiver is waiting for an acknowledgment and it receives an acknowledge frame it will check the frame pending bit If the frame pending bit is set and the WaitResponseEnable in macRxConfig register is set it will expect the arrival of a data frame In this case it will continue receiving and wait for the arrival of the data frame for the time set in the T MaxFrameResponse register AutoA
142. rated HW MAC features that are derived form the frame forming mechanism are disabled If this bit is set then the integrated HW MAC MAC header and address field construction is disabled In this mode the MAC header and address fields are taken directly from the TxFIFO For further information on the Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 85 of 124 ZMeoor eene E RED DirectFifoAccess mode see section 4 5 For details regarding the Tx operating mode refer to the Tx operating mode description section 4 11 2 Register MAC Transmit Status 7 0 mnemonic macTxStatus address OxA3 access R C code based constant address definition MAC_TX_STATUS Paar Register Stave bescrpion resar 0x01 GTS GTS transmission 0x02 SItCSMA Slotted CSMA transmission 0x10 CAfail_Chbusy Transmission failed due to channel access failure because of a busy channel 0x20 CAfail_ CAPfail Transmission failed due to channel access failure because of CAP end 0x40 GTSfail GTS transmission failed due to unavailable slot 0x80 CAfail_SFend Transmission failed due to super frame end Status is indicated by the IRQ The macTxStatus register monitors the Tx status and the transmission result Each result update is indicated by an interrupt For details refer to the Tx mode description section 4 11 2 Register Transmit Frame MSDU Length 6 0 mnemonic msduLengthTx address 0x60 access R W C co
143. ration3 Scan duration time 23 16 in symbols Reference IEEE 802 15 4 Section 7 5 2 1 These registers define the scan duration in symbols used for the different scan modes For details refer to the scan mode section 4 11 4 The default scan duration after reset is 960 2 symbols For debugging purposes firmware can force a timeout of the running scan duration timer by setting T_ScanDuration to 0 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 98 of 124 reenen E RED 5 10 MAC Beacon Control Register Beacon Interval 23 0 mnemonic T_BeaconInterval address 0xD5 OxD7 access R W C code based constant address definition T_BCN_INTERVAL_1 through T_BCN_INTERVAL_3 T_BeaconInterval1 Beacon interval time 7 0 in symbols T_BeaconInterval2 Beacon interval time 15 8 in symbols T_BeaconInterval3 Beacon interval time 23 16 in symbols These registers define the beacon interval in symbols for the configuration of a beacon enabled network It should be set up correctly according to the superframe configuration before starting beacon generation or beacon tracking For details refer to the beacon generation and beacon tracking sections 4 11 6 and 4 11 5 The default beacon interval after reset is 960 2 symbols i e beacon order is five 5 10 1 MAC Beacon Generation Control Register MAC Auto Beacon Transmit Configuration 0 0 mnemonic macBcTxConfig address OxB5 access
144. re 4 9 Each operating mode is described in detail in subsequent sections The following paragraph explains the SDL diagram in Figure 4 9 on page 35 The ZWIR4501 powers up to Idle mode from which all other operating modes can be entered In Idle mode the 24 MHz oscillator and the 32 768 kHz RTC are running and the analog front end is shut down Note that the 32 768 kHz RTC requires about 730 ms to be stable after the circuit power up see section 3 5 1 for more information on power up Therefore functions relying on the Sleep mode and beacon tracking are available only after this start up time See section 2 5 After power up it is recommended to read the trimming values including the transceiver s unique 64 bit IEEE address from the embedded EEPROM using the MTP procedure see section 5 17 for further information on the recommended startup register setup Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 32 of 124 ZMmMoor eene E RED A data transmission Tx is initiated with the macControl command TxOn The frame MAC header and the MSDU must be stored in the appropriate Tx registers see section 5 6 and the TxFIFO respectively The transmission ends after the successful transmission of the frame or it is terminated by a channel access failure due to a busy channel or an unavailable finished CAP or GTS period After the end of the transmission the ZWIR4501 either returns to Idle mode or automatic
145. reception mode the status will be 0x81 which is an OR combination of the processing state Acquire and the result indicator Data A description of the receive frame handling and RxFIFO management is given in section 4 5 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 44 of 124 ZMmMeoor eene WIR If the macControl command TxRxOff or TxOn is issued while receiving a frame the remaining bytes of the frame are received first then the macControl command is executed Following this sequence a receive interrupt IRQreason 0x02 is generated the corresponding macRxStatus reports three possible results 0x00 0x01 or OxCO In order to determine if the frame was received successfully the macFramePend register must be checked If the macFramePend register indicates a frame was received the frame can be read from the RxFIFO or discarded using the macControl command RxFifoFlush If the inbound frame s field control field had the Ack requested bit set and AutoAckEnable bit in the macRxConfig register is set the acknowledgment frame is transmitted automatically if the macRxStatus equals 0xC0 The acknowledgment frame is not transmitted if the macRxStatus equals 0x00 or 0x01 See section 4 11 2 on page 40 for further information on acknowledgment frame reception while issuing the macControl command TxRxOff Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 45 of 124 Lm
146. red independently for Sleep Global Power Down mode and for the normal operating modes e all modes except Sleep and Global Power Down mode The configuration is set up in the ClkOutConfig register By default the CLKO provides 6 MHz in normal mode and 32 768 kHz in Sleep Global Power Down mode To reduce the power consumption switching off the clock output signal is recommended if it is not being used by the application The clock on the CKLO pin can be configured for external microcontroller clock support by the ClkOutConfig register During the Global Power Down and Sleep modes the clock output signal is switched to 32 768 kHz or to selectable fractions of 32 768 kHz for reduced current consumption During all other states the 24 MHz clock or selectable fractions of 24 MHz can be used on CLKO Pin 36 can directly drive clock input up to 4 mA Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 17 of 124 ZMoor eene E RED 3 5 Interfacing SPlconfig 5 0 SPItx 7 0 Digital Core SPlstart TxFIFO 128 bytes RxFIFO 256 bytes 8 bit port as data bus Interrupt GPIO Figure 3 7 Interface Block Diagram The ZWIR4501 provides two different interfaces a standard based SPI MOSI MISO SCK SSN and a parallel interface Both can be used to access the internal register bank as well as the transmit TxFIFO and receive RxFIFO FIFOs Additionally it has an IRQ output a dedicated Globa
147. register address and other defines like commands status and configuration settings can be requested from zigbee zmd de 7 ZWIR4501 Application Note 01 RF Reference Design incl PCB Design Guidelines ZWIR4501_ANO1_RF_Ref_Design_v1_0 zip can be requested from zigbee zmd de 8 ZWIR4501 Application Note 07 Hardware Abstraction Layer HAL for C8051F12x ZWIR4501_ANO7_HAL_C8051F12x_v1_0 zip 9 ZWIR4501 Software MAC Layer implementation of a SW MAC layer for the ZWIR4501 Starter Kit board can be requested from zigbee zmd de Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 123 of 124 ZMmMoor eene E RED Disclaimer The information furnished herein by ZMD is believed to be correct and accurate as of the publication date However ZMD shall not be liable to any third party for any damages including but not limited to personal injury property damage loss of profits loss of use interruption of business or indirect special incidental or consequential damages of any kind in connection with or arising out of the furnishing performance or use of the technical data No obligation or liability to any third party shall arise from ZMD s rendering technical or other services Products sold by ZMD are covered exclusively by the ZMD standard warranty patent indemnification and other provisions appearing in ZMD standard Terms of Sale Testing and other quality control techniques are used to t
148. rframe and wake up just before the next beacon arrival The crystals frequency offsets can cause a timing deviation between the coordinator and the device On the device side the ZWIR4501 keeps track of this deviation and corrects the beacon interval accordingly As shown in Figure 4 22 there are several timing registers involved in beacon tracking mode The beacon interval in symbols is set up in T_BeaconInterval For the beacon scan phase two parameters must be adjusted The first parameter is T BeaconScanDuration which defines the time period during which the receiver is turned on and the HW MAC waits for the reception of a beacon frame before it is declared lost The second parameter is T BeaconScanStart which defines the time in symbols during which the receiver is turned on and the new scan process is started before the arrival of the next beacon It is not used for the initial beacon acquisition scan For the following beacon frame this parameter must be greater than the timing deviation introduced by the crystal frequency deviation From this point on the ZWIR4501 continues tracking the timing error until a beacon frame is missed Thereafter for subsequent beacon scans this start time can be reduced Since there will be a residual timing error T BeaconScanStart must not be set to less than 5 The timing error effect becomes significant only for higher beacon orders For details on the network timing refer to sections 4 12 and 4 12 Beaco
149. riority 1 Y macControl macControl macControl TxRxOff AutoBcTxOn TxOn 1 mackxStaiite pm Data v v v f li i macRxStatus ages macRxStatus macRxStatus macRxStatus macRxStatus macRxStatus lt ___J PollnoData Off Off Off Off DataAck Y BW _ ContRx no macRxConfigl2 on acRxConfig 3 next operating modes Beacon AutoBeacon _ Idle ers f Idle q e Idle Figure 4 18 Rx Mode SDL Diagram D ZE E ee root wa weem gt wem gt VY ia J Rx gt Tx d Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 46 of 124 ZMmMoor eene E RED 4 11 4 Scan Modes The ZWIR4501 supports the four scan modes energy detection ED active passive and orphan scan The scan mode is selected in the macScanMode register A scan can be activated only from the Idle mode with a macControl command ScanOn Before the macControl command ScanOn is issued the following registers need to be initialized write value 0x10 to register address 0x43 and write value 0x00 to register addresses 0x44 0x45 and 0x46 It is important that register address 0x46 is written last For all four scan modes the scan duration in symbols is set up in the T_ ScanDuration register During an ED scan an 8 symbol long energy detection is performed repeatedly until the scan duration expires The active ED scan is indicated by macScanStatus ED
150. rol queued until 0x00 indicating the valid command execution command execution Figure 4 2 Scenarios for macControl Register 4 4 Interrupts The ZWIR4501 has 23 mask able interrupt conditions which are grouped by eight different interrupt reasons Most of the interrupt conditions correspond to status updates of the HW MAC The IRQ processing is shown in Figure 4 3 below If there is no interrupt the IRQ line is high If an unmasked interrupt condition occurs the IRQ output is set to low On each of the following unmasked interrupt conditions the IRQreason register is updated In response to an IRQ software reads the IRQreason register and the associated status register The IRQreason register is automatically cleared to 0x00 after the register has been read This will reset the IRQ line to high as well If another interrupt condition occurs only on the read access to the IRQreason register the IRQ line will stay low indicating that an interrupt is still pending In this case the IRQreason register is overwritten with the new interrupt reason After an interrupt is issued the corresponding status register is updated to provide more information on the actual reason for the issued interrupt NoIRQ N gt IRQ 1 y 2 IRQreason read gt IRQreason 0 Interrupt condition occurred gt update IRQreason register 1 Another interrupt condition occurred gt update IRQreason register IRQ is cleared after re
151. s d d macRxStatus ACK gt jJ l i e e Re RER E es Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Figure 4 28 MSC Unslotted Tx Rx with Automatic Ack Page 61 of 124 Lm The Analog Mixed Signal Company ZWIR4501 PAN Coordinator Device MCU ZMD44102 ZMD44102 MCU be macRxConfig AutoAckEn gt FifoStoreLQI ContRx AckSquNb d t macTxConfig CSMA GoToRx gt mac TxConfig default gt l gt Configuration d macRxConfig WaitRespEnable macControl RxOn l AutoAckEn FifoStoreLQI AckSqu _ e R x Sg A _ _ WriteTxFrame c e macControl TxOn t i Sent data request y X Perform CSMA command e _ Cmd data request IRQ Tx gt e IRQ Rx macTxStatus Success gt macRxStatus DataAck T_Wait Receive data request RxFIFO MHR MSDU LQI T T_Ack ForAck s command prepare P R Ack set frame pending bit mhrAckFc1Tx frame pending gt x Ack Receive Ack with the wo frame pending bit set gt le xX frame pending bit set Q x R IO in the MHR frame __ macTxStatus Success x macRxStatus AckFramePend gt control section So WriteTxFrame E RxActive A Es mhrTxFc1 Data frame Ack req c macControl TxOn t T MaxFrame S Response S
152. s ess SRREERKEEEEEREEEEEREEEREEEEEREEEEEREEEREREEEER REENEN Al Crvetal Oecllator e eciecniicisci niee RAEE E EAE EEEE EAEE ERE 3 1 1 Reference Crystal Oscillator 24 MHz 3 1 2 Low Power Crystal Oscillator 32 768 kHz 3 2 RF PhaseLocked Loop crecer unien a e r ee EE 3 3 Antenna Connection and Power Amplifier Configuration ccccceeeeceeeeeeeeeeeeeeneeeeeeeeaeees 3 4 Clock Output CL E ccna oie EE ane el de lel aa eh KS IMMOMACING E 35 1 Power Up ie ciccicecscactaccanteders a aa geed 3 5 2 Reset RON 3 6 Synchronous Serial Peripheral Interface PI 3 7 Parallel Interface AA A Integrated HW MAC ee EE ees ce nce ete tat Ee EE Se ET 4 2 Block DaOtamt 22028 tities nadie onn NEEE EAEE EE ENEE EEN 4 3 MAG Control eet ain ahi eae Male Eed EE ge AA Ne e E da Fame Handing s 2es c scaecctes ege ace estes cg sf ebested te ge ee ERC ENEE EES eA 4 6 Link Quality Indicator OI 4 7 Receive Signal Strength Indicator RSSI cccccecsceceeececeeeeeeeeeceeeeeseaeeesaeeeeeeeesecaeeesneeeeees 4 8 Energy Detection Level eslona a a AAE ee eee ede d Frame Puteri is caccteetcencecte Eden ncesend dn NET dete EE 4 10 Operation Mode Overview ccccccceeceeeeeeeeeceeeeeeeeseceaeaeeeeeeesasenaaeeeeeeeeeseeenaeeaeeeeeeeeeeeee 4 11 Operation Mode Description 4 17 1 Low Power Mod Siccici icone ies Ae ane yn eet KCL Transit Mode Tereno seed A eege ee eege dee ees 4 1133 e EE EE AVA Re Copyright 20
153. s reference MAC PAN identifier by the frame filter Register Reference MAC Short Address 15 0 mnemonic macShortAddr address 0x8B Ox8C access R W C code based constant address definition AF_ADDR16_1 and AF_ADDR16 2 macShortAdadr1 Frame filter reference MAC short address 7 0 macShortAddr2 Frame filter reference MAC short address 15 8 Reference IEEE 802 15 4 Section 7 5 6 2 The macShortAdar is used as reference MAC short address by the frame filter Register aExtendedAddr Reference Extended Address 63 0 mnemonic aExtendedAddr address 0x8D 0x94 access R W C code based constant address definition AF_ADDR64_1 through AF_ADDR64_8 roar reser OOO O oorp OOOO Tresa Reference IEEE 802 15 4 Section 7 5 6 2 The aExtendedAddr is used as reference extended address by the frame filter If the ZWIR4501 s unique IEEE address is required to use for the frame filter as well the values of the mhrSrcAddr64Tx registers must be written to the aExtendedAddrX registers Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 110 of 124 reenen E RED 5 13 MAC Superframe and GTS Control Register Superframe Order SO 3 0 mnemonic macSuperframeOrder address OxBF access R W C code based constant address definition SF_ORDER ass Register __bescrpion Range Reet macSuperframeOrder Superframe order active portion of the superframe Reference IEEE 802
154. smit frame MAC header sequence number Reference IEEE 802 15 4 Section 7 2 1 2 The mhrSquNbTx register contains the sequence number of the transmit frame It must be configured before a transmission begins For auto acknowledge generation the sequence number of the acknowledge frame is instead taken from the mhrSquNbRx register in order to use the sequence number of the previously received frame In the DirectFifoAccess mode the mhrSquNbTx register does not have an effect The header of the frame must be written to the TxFIFO and the sequence number for the automatic sequence number checking is derived from the header bytes that are written to the TxFIFO Register Tx Frame MAC Header Dest PAN Identifier Field 15 0 mnemonic mhrDstPanldTx address 0x64 0x65 access R W C code based constant address definition MHR_TX_DST_PAN_ID_1 and MHR_TX_DST_PAN_ID_2 al reas J OO oeseri OOO fres mhrDstPanld1Tx Transmit frame MAC header destination PAN identifier 7 0 mhrDstPanld2Tx Transmit frame MAC header destination PAN identifier 15 8 Reference IEEE 802 15 4 Section 7 2 1 3 This register stores the MAC header destination PAN identifier field for a transmit frame The mhrFc2Tx addressing mode configuration determines whether the transmit frame address field contains the destination PAN identifier field The addressing field is constructed for each frame within the HW MAC frame former Register Tx Frame MAC Header 16 bit De
155. st Address Field 15 0 mnemonic mhrDstAddr16Tx address 0x66 0x67 access R W C code based constant address definition MHR_TX_DST_ADDR16_1 and MHR_TX_DST_ADDR16_ 2 ESCH mhrDstAddr16_1Tx Transmit frame MAC header 16 bit destination address 7 0 mhrDstAddr16_2Tx Transmit frame MAC header 16 bit destination address 15 8 Reference IEEE 802 15 4 Section 7 2 1 4 This register stores the MAC header 16 bit destination address field for a transmit frame The mhrFc2Tx addressing mode configuration determines whether the transmit frame address field contains the 16 bit destination address The addressing field is constructed for each frame within the HW MAC frame former Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 88 of 124 eene E RED Register Tx Frame MAC Header 64 bit Dest Address Field 63 0 mnemonic mhrDstAddr64Tx address 0x68 Ox6F access R W C code based constant address definition MHR_TX_DST_ADDR64_1 through MHR_TX_DST_ADDR64_8 ERC OOOO O ooro OOOO rea Reference IEEE 802 15 4 Section 7 2 1 4 This register stores the MAC header 64 bit destination address field for a transmit frame The mhrFc2Tx addressing mode configuration determines whether the transmit frame address field contains the 64 bit destination address The addressing field is constructed for each frame within the HW MAC frame former Register Transmit Frame MAC Header Source PAN Identifi
156. st in symbols 7 0 T_MaxFrameResponse2 Maximum time to respond to a data request in symbols 10 8 Reference IEEE 802 15 4 Section 7 5 6 3 These registers define the time in symbols that a device waits for a frame after the reception of an acknowledge frame with the FramePending bit set This value corresponds to aMaxFrameResponseTime in the Standard The default value is 1220 symbols In order to be 802 15 4 compliant it should not be changed Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 96 of 124 ZMmMoor eene E RED 5 9 MAC Scan Control Register MAC Scan Status 7 0 mnemonic macScanStatus address OxA5 access R C code based constant address definition MAC_SCAN_STATUS maar Register RE 0x01 ED Energy detection scan active 0x02 ActiveTx Active scan request frame transmission ongoing 0x03 ActiveRx Active scan scanning for beacon 0x05 OrphanTx Orphan scan request frame transmission ongoing 0x40 ActiveTxFail Active scan request frame transmission failed due to channel access failure Ox80OrphanTxFail Orphan scan request frame transmission failed due to channel access failure Status is indicated by the IRQ The macScanStatus register monitors the scan status The successful reception of beacon or command frames during scan the scan time out and the transmission failure of the request frames are indicated by interrupts For details refer to the sc
157. sted bit set the ZWIR4501 automatically activates its receiver and waits for a period T WaitForAck in symbols for the reception of an acknowledge frame Third if acknowledgment is not requested the appropriate inter frame spacing timer is started at the end of the transmit frame and depending upon the GoToRx bit in the macTxConfig register either the Rx mode starts or the ZWIR4501 returns to Idle mode Fourth in all remaining cases either the Rx mode or the Idle mode starts depending upon the GoToRx bit The Tx mode is also used to generate acknowledge frames automatically if they are requested by a received frame and the AutoAckEnable bit is set in the macRxConfig register entry point C in Figure 4 15 The ZWIR4501 maintains the spacing T Ack between the frame and the acknowledge frame At the end of the acknowledge transmission and depending upon the GoToRx bit either the beacon tracking or automatic beacon transmission mode starts if the T BeaconInterval timer has expired or the Rx mode or Idle mode starts depending on the GoToRx bit The inter frame spacing timer starts at the end of the acknowledge frame If the macControl command TxRxOff is sent to the transceiver while a frame is transmitted an interrupt with the IRQreason 0x01 with an associated macControl value of 0x1F is issued indicating that a command error has occurred The frame transmission is completed and the transceiver is switched to receive mode if the automatic ackn
158. ted for frames violating the level 2 check under the condition that the level 2 filter interrupt condition is unmasked in RQmask Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 31 of 124 ZMmMeoor eene E RED 4 10 Operation Mode Overview The following section describes the different operating modes of the ZWIR4501 with the help of several SDL diagrams Figure 4 8 shows the symbols used in these diagrams The green input and output are the GPD and the IRQ respectively Most of the operating mode actions are initiated by the macControl command violet input Status information is held in the status register violet output The yellow symbols show the internal timer start stop commands and expiration flags External direct input GPD from uC Interrupt to uC Input from macControl register macControl will automatically reset to 0 after the transition Status register output uC must poll the register Internal timer expiration bank Internal timer start Decision depends on register setting in register bank Collm internal signals processes transitions and states N State representing a main operating mode IRCH Figure 4 8 SDL Diagram Legend This section begins with an overview of operating modes and the possible paths between them The different operation modes are indicated as gray process symbols in the SDL diagram in Figu
159. thin a long short inter frame space T_LIFS T_SIFS plus a guard time T Delta before the end of the CAP or GTS The guard time is used to Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 39 of 124 ZMmMoor eene E RED compensate for the timing deviation between a device and its coordinator introduced by the different crystal frequency offsets It is significant only for higher superframe orders By default this guard time is disabled If required it can be enabled with the LateGuard bit in the macBcTrConfig register A GTS transmission can also be delayed by the T Delta time in order to compensate for a device s early timing offset relative to its coordinator Again this effect is significant only for higher superframe orders and the early guard time must be enabled in the macBcTrConfig For more details on network timing issues refer to section 4 12 4 12 2 and 4 12 3 Short frame Tack aa h T_SIFS T Delta Figure 4 14 GTS and CAP Check pus S19 dY Ups S19 At the end of a transmission there are several ways that the Tx mode can be exited First if beacon tracking or automatic beacon generation is activated and the T Beaconlinterval timer has expired the ZWIR4501 will automatically enter the automatic beacon transmission or beacon tracking mode This timer expiration has the highest priority Second after the successful transmission of a frame with the acknowledge reque
160. tus TimeOut Frames not passing the CRC check or frame filter are by default automatically removed from the Rx FIFO N receive P acon x beacon request firmware before macScan Status Activex turnaround O gt R receives macScanStat us Beacon v wat firmware to parse beacon mo gt stop scan if number of found beacons a specific number cont scan until the number of found beacons a specific number macControl macControl ScanOff ScanCont macScanMode Active Passive v WS Y macScan macScan macScan macScan Status Status Status Status TimeOut om ActiveTx Passiv next operating modes D cmd using CSMA mhrymsdu set by 7 Fallure D macControl TxOn macControl RxOn macControl TxRxOff Y RxActive digital Rx on macScan Status ActiveTxFail H TimeOut Figure 4 19 Scan Mode SDL Diagram Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 7 gt orphan emd gt using SMA mhr msdu set by firmware befor macscan Status OrphanRx vy turnaround receive macScan Status Command E firmware to parse cmd f macControl 1 TF ailure
161. tus Success macRxStatus Data _ gt l RxFIFO MHR MSDU LQI H d gt RxActive l 4 IRQ AutoBcTx l p e WriteTxFi e BeaconTrack oct Ce L IRQ Beacon gt Auto Beacon Tx Been Been E Figure 4 37 MSC Extracting Data from the Coordinator Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 70 of 124 eene E RED 5 Registers This chapter contains descriptions for the ZWIR4501 s registers These registers can be modified through the SPI or parallel interface by utilizing an additional microcontroller The register description contains a mnemonic for easy referencing a bit description where applicable the access mode R read and or W write and the address of the register within the ZWIR4501 ZMD provides a C code header file that provides the C code based constant definitions for the register s address and other C code based constant definitions as commands status and configuration settings 6 When starting to write C code for any MCU that controls the ZWIR4501 contact ZMD to receive an up to date version of this header file The C code based constant address definition is noted with the register description for easier handling The register description includes a Reset column which provides information about the initial register s content after the reset procedure 5 1 Register Summary IRQ Control Register IRQmask1 2 3 4
162. tware configurable frequency control Integrated MAC Functions e 128 byte TxFIFO 256 byte RxFIFO CRC generation and checking Transmit modes unslotted and slotted CSMA GTS direct Tx Frame forming Automatic acknowledge generation Scan modes active passive energy detection orphan Beacon tracking Automatic beacon generation Frame filtering Timer TotalTime Superframe RxDefer IFS Ack WaitForAck MaxFrameResponseTime Scan Power saving modes Global Power Down Sleep modes while maintaining network time Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 6 of 124 ZMmMoor eene E RED 1 3 RF Frontend Description LP Filter AGC with LPF 5 D bk i S PA SE Pg gt ai Dac a gl ZS Channel 24 MHz wees ees PED XTAL Frequency 48 MHz f osc Doubler Master Bias RF PLL CET _ LPF 1 24 MHz 32 768 kHz Figure 1 1 Integrated Analog PHY Layer Block Diagram Receiver Chain The receiver of the ZWIR4501 uses a direct conversion architecture Zero IF architecture The receiver path consists of a 900 MHz low noise amplifier LNA and a mixer followed by the analog baseband It contains multi stage programmable gain amplifiers low pass filter sections and analog to digital converters ADC All remaining functions are carried out in the digital domain including synchronization de spreading demodulation and the AGC loop control To exte
163. v 1 3 August 19 2009 Page 111 of 124 Teater CS AWIRASO1 Register Guaranteed Time Slot GTS Length 3 0 mnemonic macGTSlength address OxC2 access R W C code based constant address definition SF_GTS_LENGTH aaa Register __Dessripfon Range Reset macGTSlength Length of the GTS in slots Reference IEEE 802 15 4 Section 7 5 1 1 This register defines the length in slots of the GTS within the superframe If macGTSlength is set to 0 then no GTS is assigned This value must not exceed the number of slots from the beginning of the GTS to slot 15 Register Current Symbol Time 23 0 mnemonic macCurrentSymbolTime address OxE9 OxEB access R C code based constant address definition MAC_CURR_SYM_TIME_1 through MAC_CURR_SYM_TIME_3 OxE9 macCurrentSymbolTime1 Current symbol time within the active superframe 0x00 portion 7 0 in symbols OxEA macCurrentSymbolTime2 Current symbol time within the active superframe 0x00 portion 15 8 in symbols OxEB macCurrentSymbolTime3 Current symbol time within the active superframe 0x00 portion 23 16 in symbols The macCurrentSymbolTime monitors the value of the internal superframe timer and shows the current point in time within the active portion of the superframe In the case of an FFD this timer starts with 0 at the beginning of each transmitted beacon In the case of an RFD the timer starts at the end of a tracked beacon and the start value is equal to the length of th
164. value signifies late arrival The symbol time within the active superframe is Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 52 of 124 ZMmMor eene E RED indicated by the macCurrentSymbolTime in symbol units where zero is the beginning of the superframe The current slot number can be read from macCurrentSlot Figure 4 23 on page 54 shows the SDL diagram of the beacon tracking mode Beacon tracking can be activated only from Idle mode via the macControl command BcTrOn It starts with an initial scan for a beacon frame All nonbeacon frames are ignored during this phase If TrackEnable is not set in the macBcTrConfig and no beacon frame is received within T BeaconScanDuration or if TrackEnable is set and no beacon is received in a number macMaxLostBeacons of consecutive beacon scan phases then a loss of synchronization has occurred The synchronization loss with the coordinator is indicated by a beacon track BcTr interrupt and a macBcTrStatus of SyncLoss After the synchronization loss the Rxldle state starts The arrival of a beacon frame within the scan duration is indicated by a BcTr interrupt and a macBcTrStatus of Beacon The PAN identifier and source address of the beacon are verified together with the checksum by the integrated frame filter at the end of the beacon reception Beacon frames that do not pass the filter are rejected and automatically removed from the RxFIFO If required the firm
165. ware can do an additional check of the beacon frame Therefore the BeaconConfirm bit must be set in the macBcTrConfig register In this case firmware can verify the beacon and either accept or reject it via the macControl commands BcOk and BcFail The HW MAC synchronizes to beacons that are not rejected After having synchronized to a beacon the HW Mac will keep track of the beacon The beacon tracking mode is enabled by the TrackEnable bit in the macBcTrConfig register The active tracking is indicated by the macBcTrStatus Track After the reception of the beacon frame three different operating modes can be entered If an unfinished CSMA procedure is pending from the previous CAP the Tx mode will be entered automatically in order to resume the CSMA process If an unfinished Wait for frame response process is pending from the previous CAP then the Rx mode will be entered in order to continue with the Wait for frame response process Otherwise the Rxldle mode starts The Rxldle is an interim state and firmware must direct the HW MAC into an appropriate operating mode If beacon tracking is active the ZWIR4501 automatically returns to the beacon tracking mode T BeaconScanStart symbols before the estimated end of the beacon interval and starts to scan for the next beacon for a time T BeaconScanDuration This automatic switch can be performed from the operating modes Idle RxActive Rxldle RxDefer and Tx Ongoing transmission or recepti
166. x fi f using sisted CSUA Tx frame directly A P Sc check if transmission Yy y check if transmission 8 z GIS including ack can including ack can Txframe x defer Tx to Tx frame using direct acknoledge frame be finished LIFS SIFS before end of CAP slot n if gt current slot be finished LIFS SIFS eg end of CAP unslotted CSMA macTxStatus WEE macTxStatus macTxStatus macTxStatus success macTxStatus success CAfail_CHbusy success success success success GTSfail CAffail_ CAPfail CAffail_CAPfail CA fail_CHbusy CAfail_SFend Ack requested MhrFc1Tx 5 next operating modes Tx gt RXx turnaround wait for ack macTxStatus success Ops Figure 4 15 Tx Mode SDL Diagram GoToRx 1acT xConfig 3 Tx gt Rx ee turnaround e We digital Rx on TxiRx off Tx gt Rx turnaround priority 1 Bozcontracx AutoBcTx Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 41 of 124 Lm The Analog Mixed Signal Company 4 11 2 1 CSMA CA Algorithm ZWIR4501 The CSMA CA algorithm is defined in the standard IEEE 802 15 4 Section 7 5 The algorithm is configured by a set of registers macMinBE and following indicated in italics in Figure 4 16 on page 42 These values should be chan
167. x62 mhrFc2Tx 0x63 mhrSqnNbTx 0x64 0x7B mhr Addr Tx ji 0x60 msduLengthTx TxFIFO 128x8 TxFIFO 128x8 l Ts Tx Frame EECHER In default mode the address filed is composed by the HW MAC according to the frame control address mode settings frames with incorrect CRC are removed from the RxFIFO Rx Frames Msdu Address Mhr S Sep Rx Frame B Rx Frame A RxFIFO 256x8 coke ba Coke ta LengthA copy from the last received frame s 0x82 mhrFc1Rx mhr for internal processing like auto 0x83 mhrFc2Rx 0x84 mhrSqnNbRx acknoledge generation 0x86 mfrCRC1Rx a 0x87 mfrCRC2Rx pending number is increased after each frame writtento the RxFIFO it is automatically decreased on each read access 0x88 macFramePend 2 Figure 4 4 Tx Rx Frame Handling Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 27 of 124 ZMoor eene E RED 4 6 Link Quality Indicator LQI The IEEE 802 15 4 standard defines a Link Quality Indicator LQI see 1 section 6 7 8 This value can be estimated by using the value of the AgcLvl register after a successfully received frame before the receiver is switched on again It is not recommended to use the two bytes that are stored after a received frame to the RxFIFO to estimate the LQI The mapping of the AgcLvl register value to the LQI value is shown by Figure 4 5 0 20 40 60 80 100 120 140 16
168. ximum Ratings Caution Operation beyond these values may cause permanent damage to the device or reduce its reliability Note Values are over free air temperature unless otherwise noted Parameter Symbol Min Typ Max Unit Notes Analog supply votage avo as v Digtal supply votage Jm za ss v o ooo o Digital 10 supply voltage Ip 2 46 v et v JIL 6 v AcwOsO S loutputvotage v 46 v acwosio Analog input volage Vou 38 v manao kengt eg Pn 6 em Storage temperare Ta 65 150 Cc Ss ESD protection Ver 2 W HEN O0RF 15K Human Body Model 2 3 Digital UO CMOS input CMOS output Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 11 of 124 ZMmMoor eene E BAD 2 4 Operation Modes and Current Consumption Note Values are for supply current on 2 4 V power supply Sleep mode timer controlled X active or maintained Please refer to section 4 11 Operation Mode Description for further information 2 5 Startup Time Power on to Idle mode 2 Idle mode to Tx PHY From end of Tx start command to trailing edge of transmitted frame Idle mode to Rx PHY From end of Rx start command to EU mode trailing edge of receive frame o US mode Receiver to transmitter turnaround MAC As defined by 1 EU mode US mode Transmitter to receiver turnaround
169. yte is the address 7 0 For TxFIFO and RxFIFO access the addresses are 0x80 and 0x81 respectively Note that the TxFIFO allows only write access and the RxFIFO allows read and write access please refer to the register description of the RxFIFO During register bank access a number of N bytes is read starting from address 7 0 up to address 7 0 N 1 If the FIFO locations 0x80 or 0x81 are within this range they are skipped and the read write access is continued at location 0x82 Copyright 2009 ZMD AG ZWIR4501 Data Sheet and User Manual v 1 3 August 19 2009 Page 20 of 124 Lm eene E BAD For write access the address 7 0 byte is followed by the data frame Do 7 0 to Dy 7 0 The slave select not SSN line is low during the complete write transfer However SSN high gaps can be inserted between each byte In the read access protocol the data frame is shifted out by the slave on the MISO line Before each data byte an SSN high gap is required As with write access an SSN high gap can be inserted before the address 7 0 byte Note that the SPI cannot be used in GPD or Sleep mode If the SPI protocol has been corrupted or violated a reset of the ZWIR4501 is required write access SCK U I Length 6 0 N a S Dy 7 0 MOSI JUUUUUUUL d i k DO S tsc tss a Figure 3 2 Transfer Protocol SPI Slave Mode CPHA 0 CPOL 0 The timing parameters are listed

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