User Manual UM EN IBS SRE 1A - Digi-Key
Contents
1. t lt gt D7 0 p 4 Valid data 4 51048010 Figure 3 2 Timing for write access Table 3 2 Timing for the microprocessor interface write access Symbol Explanation Minimum Time ty Addresses and CS valid before negative edge of WR 5 ns to Addresses and CS valid after positive edge of WR 5 ns t3 Valid data before positive edge of WR 15ns t4 Valid data after positive edge of WR 10 ns ts WR pulse width 30 ns Read access ICS A3 0 pot tro 2 IRD j j t te 07 0 4 Valid data 5104 011 Figure 3 3 Timing for read access 12 PHOENIX CONTACT 7295_en_01 Microprocessor Access Table 3 3 Timing for the microprocessor interface read access Symbol Explanation Time Minimum Maximum 4 Addresses and CS stable before negative edge of 10 ns IRD t Addresses and CS stable after positive edge of RD 10 ns tg Valid data after negative edge of RD 25ns to Data bus high resistance after positive edge of RD 26 ns tio IRD pulse width 30 ns 3 2 Address Area Assignment Four address lines AO A3 are available for the IBS SRE 1A The address area that can be accessed via the microprocessor interface has the following structure Table 3 4 Address area assignment for the IBS SRE 1A Relative Address Write Register Read Register 0 IBS IN byte 0 IBS OUT b2. The worst case time is therefore t 233 us The CPU has maximum of 233 us after interrupt request to read the CLEAR IRQ register and the IB OUT data registers and to write the IB IN data registers 16 PHOENIX CONTACT 7295_en_01 Technical Data and Ordering Data 4 Technical Data and Ordering Data 4 1 Technical Data Electrical Data Power supply 4 5 V 5 5 VDC Input voltages 0 3 Vcc 0 3 V Current consumption 10 mA Temperature range 40 C 85 C industrial CMOS input voltage High 3 5 Voc 0 3 V Low 0 3 1 5 V Schmitt trigger inputs Positive switching threshold 2 4 V 4 0V Negative switching threshold 10 2 4 Hysteresis 0 5 V CMOS output voltage High 3 7 Vinin Low 0 4 Vmax CMOS output current 2mA 1 All inputs are static All outputs are unwired The oscillator is operating 4 2 Ordering Data Chip Description Type Order No Pcs Pck INTERBUS register expansion chip IBS SRE 1A 2746595 96 with QFP44 housing Documentation Description Type Order No Pcs Pck User manual for the IBS SUPI 3 INTERBUS protocol IBS SUPI 3 UME 1 User manual for the IBS SUPI 3 OPC INTERBUS IBS SUPI3 OPC UME 1 protocol chip User manual for the IBS SUPI 2 INTERBUS protocol IBS SUPI 2 HB E 2758787 1 chip Make sure you always use the latest documentation It can be downloaded at www download phoenixcontact com A conversion table is available on the In
3. This bit is used to separate the hardware connections of the pins and redirect them to bits D3 to D1 Table 3 5 Internal or external configuration of the data length DO Data Length Setting 0 KO to K2 physical pins 1 D1 to D3 bits in the configuration register These bits are used to set the data length Table 3 6 Setting the data length via the register D3 D2 D1 Data Length 0 words 1 word 2 words 4 words 5 words ojo oijo 0 1 0 1 3 words 0 1 0 oo0 o o 6 words This bit is used to enable the interrupt request of the IBS SRE 1A Table 3 7 Enable bit for the interrupt D4 Interrupt Request 0 Disabled 1 Enabled 7295_en_01 PHOENIX CONTACT 15 IBS SRE 3 3 Interrupt Operation Since the connected microprocessor typically reads and writes the INTERBUS data registers asynchronously to the INTERBUS cycle inconsistent data may be transmitted if the read and write process falls in the latch phase of an INTERBUS cycle The latch phase completes the check sequence of every INTERBUS cycle In this phase the stored OUT data is saved to the IB OUT data registers and the data in the IB IN data registers is transferred to INTERBUS In order to prevent the transmission of inconsistent data the IBS SUPI has an interrupt logic for synchronization which provides a range of INTERBUS cyc
4. the specifications for the connection of a register expansion in the IBS SUPI user manual The serial data input SDI of the IBS SRE 1A is connected to the shift register data output ToExR1 or ToExR2 of the IBS SUPI The serial data output SDO of the IBS SRE 1A should be connected to pin FromExR of the IBS SUPI This closes the data ring FromExR SUPI 0 ICSWR RD IRQ 00 07 0 ICSIWRIRD 00 07 0 CS WR RD IRQ SE ADDRESS 5104B004 Figure 2 2 Connection to the IBS SUPI It is also possible to connect up to six expansion chips in succession or to use other conventional shift registers The signals LaOuD LalnD and ResReg should be assigned in parallel to all IBS SRE 1A chips CIKExR clock output of the SUPI should be connected to the clock input of the IBS SRE For the clock supply of other IBS SRE 1A chips or conventional shift registers the CIKRO clock output of the IBS SRE 1A should be used 7295_en_01 PHOENIX CONTACT 7 IBS SRE 2 2 1 Serial Interface Timing The timing for the serial interface matches the timing for the IBS SUPI register expansion The timing for the serial interface of the IBS SRE 1A can be found in the diagrams below gt t 4 SDI n n 1 5104B005 gt t Figure 2 3 Timing for the serial IN interface of the IBS SRE 1 Symbol Explanation Time ty SDI valid after t
5. 37 IRQ 16 GND 38 Test 17 Vcc 39 Vcc 18 A2 40 GND 19 A3 41 LaOuD 20 42 LalnD 21 SDI 43 ResReg 22 GND 44 GND 7295 01 3 IBS SRE 1 3 3 Dimensions 13 9 mm 0 547 in 0 25 10 mm 0 394 in 0 1 E 30 25 E 35 20 as SRE 1 S 40 5 7 5 10 08mm 0 031 in 0 2 0 45 mm 10 039 in 0 2 mm 0 008 in 0 008 in 0 018 in M S E CE Eps E 3 ES S 2 0 65 1 03 mm S E ile ge A 01 mm 0 026 in 0 041 in Elo 0 004 in ES ve sis S SEATING PLANE 7295A002 Figure 1 2 QFP44 housing with dimensions 4 PHOENIX CONTACT 7295 en 01 Introduction 1 3 4 Signal Description Table 1 3 Signal description for the IBS SRE 1A Designation Meaning Type OSC Oscillator input ST KO Configuration inputs for the internal registers ST K1 K2 DO D7 Data bus for the microprocessor interface BD Address bus for the microprocessor interface CI IRD Read Cl
6. DGD OGD OO GD Lionas OGD 6 INSPIRING INNOVATIONS AUTOMATIONWORX User Manual UM EN IBS SRE Order No 2888741 INTERBUS Register Expansion Chip IBS SRE 1A AUTOMATIONWORX User Manual INTERBUS Register Expansion Chip IBS SRE 1A 06 2006 Designation UM EN IBS SRE Revision 01 Order No 2888741 This user manual is valid for Designation Order No IBS SRE 1A 2746595 7295_en_01 PHOENIX CONTACT IBS SRE a gt Please Observe the Following Notes In order to ensure the safe use of the product described we recommend that you read this manual carefully The following notes provide information on how to use this manual User Group of This Manual The use of products described in this manual is oriented exclusively to qualified electricians or persons instructed by them who are familiar with applicable standards and other regulations regarding electrical engineering and in particular the relevant safety concepts Phoenix Contact accepts no liability for erroneous handling or damage to products from Phoenix Contact or third party products resulting from disregard of information contained in this manual Explanation of Symbols Used The attention symbol refers to an operating procedure which if not carefully followed could result in damage to hardware and software or personal injury The note symbol informs you of conditions that must strictly be observed to ach
7. IBS SRE 2 Basic Wiring 2 1 Clock Supply and Initialization 2 1 1 Clock Supply The IBS SRE 1A has a Schmitt trigger input The required clock can be either that of the connected microprocessor or that of the IBS SUPI However if the IBS SUPI clock is used the IBS SUPI must be clocked using an oscillator The quartz circuit of the IBS SUPI must not be modified 16 MHz quartz oscillator 5104B003 Figure 2 1 Clock supply for the IBS SRE 1A 2 1 2 Initialization In order to place the IBS SRE 1A in a defined state after power up the initialization input ResU should be set to Low during the power up phase During operation ResU should be set to High The simplest option is to connect the ResU input of the IBS SRE 1A with the ResU input of the IBS SUPI The power up phase must be at least 125 ns 6 PHOENIX CONTACT 7295_en_01 Basic Wiring 2 2 Connection to the Protocol Chips In addition to the serial data inputs and outputs the IBS SRE 1A has a microprocessor interface for parallel access to internal INTERBUS data registers Connection to the IBS is via the serial data inputs and outputs and the associated control signals Latch Clock Reset Since the IBS SRE 1A was developed as an expansion chip for the IBS SUPI the inputs and outputs for data and control signals can be connected together directly The IBS SRE 1A is connected to the IBS SUPI according to
8. IWR Write Cl IRQ Interrupt Request B2 Control bus for the microprocessor interface ENCR Enable signal for the configuration register CI ENDRR READ enable signal for the data registers Cl ENDRW WRITE enable signal for the data registers Cl SDI Data input for the IBS SRE 1A should be connected to data output TOExR1 or ST ToExR2 of the IBS SUPI SDO Data output for the IBS SRE 1A should be connected to data input FromExR of B2 the IBS SUPI Clock input for the internal shift registers for SRE 1 CI ICIKRO Clock output for the internal shift registers for other IBS SRE 1A chips or B2 conventional shift registers LaOuD Transmission signal for output data for the IBS SRE 1A ST INTERBUS OUT memory area LalnD Transmission signal for input data for the IBS SRE 1A ST IN memory area INTERBUS ResReg Reset signal for the internal data registers of the IBS SRE 1A ST ResU Initialization reset STpu Test Leave open test pin for in circuit test by the ASIC manufacturer B2 Vcc Supply voltage 5 V GND Ground 1 In normal microprocessor mode these signals should be grouped as the chip select for the IBS SRE 1 Cell types BD Bidirectional with Schmitt trigger inputs and 2 mA driver outputs CI CMOS input ST CMOS Schmitt trigger input STpu CMOS Schmitt trigger input with internal pull up B2 2 mA driver output Electrical data See section 4 on page 17 7295 en 01 PHOENIX CONTACT 5
9. any other register expansion chips is shown below High byte High byte of the IBS SUPI Memory area of the IBS SUPI Low byte of the IBS SUPI High byte of the first IBS SRE 1A Memory area of the first register expansion chip Low byte of the first IBS SRE 1A High byte of the second IBS SRE 1A Memory area of the second register expansion chip Low byte of the second IBS SRE 1A High byte of the last IBS SRE 1A Memory area of the last register expansion chip Low byte Low byte of the last IBS SRE 1A 3 2 2 Configuration Register The CONFREG configuration register at relative address 12 be used to set the data length of the IBS SRE 1A via the software However it must be noted that the correct data length of the entire device is stored in the identification register of the IBS SUPI ID8 to 12 In addition an interrupt for alternative synchronization with a microprocessor can be enabled in the configuration register However it is preferable that the interrupt of the IBS SUPI is used for synchronization with the application 14 PHOENIX CONTACT 7295_en_01 Microprocessor Access Switch Data Length Data Length Interrupt Enable D7 D6 D5 D4 D3 D2 DO Switch Data Length Data Length Interrupt Enable Unused 5104B008 Figure 3 4 Structure of the configuration register 0 external 1 internal
10. dz cue 2 1 3 2 Pin Table 4 dette ee 3 1 3 3 Dimensions c 4 1 3 4 Signal Description sic eee tz e itd e ERO T a 5 2 BASIC Ep enna tim 6 2 1 Clock Supply and Initialization 6 2 1 1 Clock S pply 2 ei ire nat oa TES 6 2 1 2 Initialization ot e la eee 6 2 2 Connection to the Protocol Chips ss 7 2 2 1 Serial Interface Timing iiie tete 8 2 3 Setting the Data Length anne 10 3 Microprocessor Access ss 11 3 1 Timing for the Microprocessor Interface 12 3 2 Address Area 22 2 1 ioana ed at a 13 3 2 1 INTERBUS Data Registers 2 200212001111 14 3 2 2 Configuration Register nea e a i a ai i 14 3 3 Interrupt Operation rumes 16 4 Technical Data Ordering Data n sort anca ba ea oda Pe ai Da Phat a le e 17 4 1 Technical i ada epu 17 4 2 Ordering ined eee ied 17 7295_en_01 PHOENIX CONTACT i IBS SRE 1 ii PHOENIX CONTACT 7295_en_01 Introduction 1 Introduction This manual describes the IBS SRE 1A register expansion chip f
11. he rising edge of CIKRI min 1 1 ns to SDI valid before the rising edge of CIkRI min 12 ns 7295_en_01 8 PHOENIX CONTACT Basic Wiring t 4 lt lt t i lt gt rials t SDO 5104B006 Figure 2 4 Timing for the serial OUT interface of the IBS SRE 1A Symbol Explanation Time ty Minimum delay CIKRI after 9 9ns to Maximum delay after 15 5 ns SDO valid after the rising edge of CIKRI min 16 6 ns t4 SDO valid after the rising edge of CIKRO min 1 1 ns 7295 en 01 PHOENIX CONTACT 9 IBS SRE 1 2 3 Setting the Data Length The data length of the serial register expansion chip be set to 0 to 6 words The data length of the IBS SRE 1A can be configured via hardware and via software For configuration via hardware the data length is set by wiring the three pins KO K1 and K2 These pins can be used to make the following settings Table 2 1 Configuration of the data length K2 K1 KO Data Width 0 0 0 0 words 0 0 1 1 word 0 1 0 2 words 0 1 1 3 words 1 0 0 4 words 1 0 1 5 words 1 1 0 6 words As an option the data width can be set by writing to the CONF register of the IBS SRE 1A addressing see section 3 2 2 on page 14 10 PHOENIX CONTACT 7295_en_01 Microprocessor Access 3 Microproce
12. ieve error free operation It also gives you tips and advice on the efficient use of hardware and on software optimization to save you extra work The text symbol refers to detailed sources of information manuals data sheets literature etc on the subject matter product etc This text also provides helpful information for the orientation in the manual We Are Interested in Your Opinion We are constantly striving to improve the quality of our manuals Should you have any suggestions or recommendations for improvement of the contents and layout of our manuals please send us your comments PHOENIX CONTACT GmbH amp Co KG Documentation Services 32823 Blomberg Germany Phone 49 52 35 300 Fax 49 52 35 34 20 21 E mail tecdoc phoenixcontact com PHOENIX CONTACT 7295_en_01 IBS SRE General Terms and Conditions of Use for Technical Documentation Phoenix Contact GmbH amp Co KG reserves the right to alter correct and or improve the technical documentation and the products described in the technical documentation at its own discretion and without giving any notice The provision of technical documentation in particular data sheets installation instructions manuals etc does not constitute any further duty on the part of Phoenix Contact GmbH amp Co KG to furnish information on alterations to products and or technical documentation Any other agreement shall only apply if expressly confirmed in writi
13. le synchronous events as interrupt sources see also IBS SUPI user manual In addition it is possible to request certain events using polling bits see also IBS SUPI user manual If the IBS SUPI cannot be used for synchronization an interrupt request signal is available for synchronizing CPU access to the INTERBUS data registers of the IBS SRE 1A The interrupt is enabled by writing a 1 in bit D4 in the CONF register with relative address 12 only once during initialization is activated on every rising edge of the LalnD transmission signal After every interrupt request IRQ goes to low a read access to relative address 12 is required The contents of this register are not relevant Once relative address 12 has been read the IRQ line goes to inactive high Data can now be read from the IB OUT data registers and the IB IN data registers can be written by the CPU After an interrupt request IRQ low the CPU is available for reading the IB OUT data registers and the relative address 12 as well as for writing the IB IN data registers for the following minimum time t 6 n x 13 x ten 26 67 us Where Length of an INTERBUS bit typical 2 us n Number of data bytes in the entire network Permissible access time for the CPU Please note that the minimum time t applies if the INTERBUS network comprises only the user s device Implemented device 4 bytes 32 bits The IN and OUT direction should be used
14. ng by Phoenix Contact GmbH amp Co KG Please note that the supplied documentation is product specific documentation only Although Phoenix Contact GmbH amp Co KG makes every effort to ensure that the information content is accurate up to date and state of the art technical inaccuracies and or printing errors in the information cannot be ruled out Phoenix Contact GmbH amp Co KG does not offer any guarantees as to the reliability accuracy or completeness of the information provided Phoenix Contact GmbH amp Co KG accepts no liability or responsibility for errors or omissions in the content of the technical documentation in particular data sheets installation instructions manuals etc As far as is permissible by applicable jurisdiction no guarantee or claim for liability for defects whatsoever shall be granted in conjunction with the information available in the technical documentation whether expressly mentioned or implied This information does not include any guarantees on quality does not describe any fair marketable quality and does not make any claims as to quality guarantees or guarantees on the suitability for a special purpose Phoenix Contact GmbH amp Co KG reserves the right to alter correct and or improve the information and the products described in the information at its own discretion and without giving any notice 7295 01 IBS SRE Statement of Legal Auth
15. or the INTERBUS SUPI protocol chip family It can be used to easily expand the data length of the protocol chips if the internal data registers are insufficient The maximum of six additional data words can be accessed via a microprocessor This manual and the manuals for INTERBUS SUPI protocol chips can be used to implement custom INTERBUS devices which should be subjected to a conformance test INTERBUS is a serial sensor actuator bus It comprises a central intelligent controller board controller or master a host system and distributed I O modules IBS protocol chips are used for integrating I O modules an INTERBUS network In this document IBS SUPI refers to all INTERBUS protocol chips in the SUPI range On the I O side the IBS SUPI has a multi function interface MFP Multi Function Pins Depending on the function of the INTERBUS device the MFP interface can be configured as a direct interface or as a processor interface Electrostatic discharge The chip can be damaged or destroyed by electrostatic discharge When handling the chip observe the necessary safety precautions against electrostatic discharge ESD according to EN 61340 5 1 and EN 61340 5 2 1 1 Serial Register Expansion Chip The Serial Register Expansion chip SRE is an ASIC in 0 8 um gate array technology with approximately 4000 gate equivalents It has one serial input and one serial output as well as a microprocessor inte
16. ority This manual including all illustrations contained herein is copyright protected Use of this manual by any third party is forbidden Reproduction translation or electronic and photographic archiving or alteration requires the express written consent of Phoenix Contact Violators are liable for damages Phoenix Contact reserves the right to make any technical changes that serve the purpose of technical progress Phoenix Contact reserves all rights in the case of patent award or listing of a registered design Third party products are always named without reference to patent rights The existence of such rights shall not be excluded Internet Up to date information on Phoenix Contact products can be found on the Internet at www phoenixcontact com Make sure you always use the latest documentation It can be downloaded at www download phoenixcontact com A conversion table is available on the Internet at www download phoenixcontact com general 7000_en_00 pdf PHOENIX CONTACT 7295 01 Table of Contents 1 Introduction aaa ala El a a Ee 1 1 1 Serial Register Expansion Chip ccc ecccecesseeeeeeeeeeecneeeeeeeeeeeeeeeeneeesenaeeeeneeeenaaa 1 1 2 Area of Appl Cation 1 1 3 HOUSING nn 2 1 3 1 Pin Assignment iioc o Eo ee oi EISE LIRE Re SERRE ERR
17. rface for accessing the internal INTERBUS data registers The IBS SRE 1A was specially developed as a register expansion for IBS SUPI INTERBUS protocol chips However it can also be used in other applications For the ordering data please refer to Technical Data and Ordering Data on page 1 17 1 2 Area of Application The IBS SRE 1A is suitable for use in industrial applications Table 1 1 Area of application Value Amount Minimum Typical Maximum Supply voltage 4 5 V 5 0V 5 5 V Temperature 40 C 25 C 85 C 7295_en_01 PHOENIX CONTACT 1 IBS SRE 1 3 Housing Type The IBS SRE 1A is housed in a QFP44 housing 1 3 1 Pin Assignment Quad Flat Pack ENCR ENDRW ENDRR VCC Osc GND SDO SDI ICIKRO CIkRI IRQ A3 reserved VCC VCC GND GND LaOuD LalnD A1 0 ResReg IRD IWR GND 5 OR aaa a N A A A A VCC GND GND 7295A001 Figure 1 1 QFP44 housing with pin assignment 2 PHOENIX CONTACT 7295 01 Introduction 1 3 2 Pin Table Table 1 2 QFP44 pin table Pin No Pin Name Pin No Pin Name 1 DO 23 Vcc 2 D1 24 ENDRR 3 D2 25 ENDRW 4 D3 26 ENCR 5 Vcc 27 GND 6 GND 28 GND 7 GND 29 Vcc 8 D4 30 ResU 9 D5 31 KO 10 D6 32 K1 11 D7 33 K2 12 IWR 34 OSC 13 IRD 35 SDO 14 0 36 15 1
18. ssor Access The IBS SRE is addressed by a microprocessor such as an component e g RAM The IBS SRE 1 has 8 bit bidirectional data bus DO to D7 4 bit address bus 0 to active low control signals Chip Select CS ENCR ENDRR ENDRW Read RD and Write WR and active low interrupt request line IRQ The separate enable signals can be used to specifically enable individual data areas of the IBS SRE 1A The meaning of the signals can be found in the following table Table 3 1 Meaning of chip select signals Enable Signal Meaning ENCR Enable signal for the configuration register ENDRR Enable signal for read access to the data registers ENDRW Enable signal for write access to the data registers In normal microprocessor mode these signals should be grouped as the chip select for the IBS SRE 1A SRE 1A ENCR ICS ENDRR ENDRW 7295A007 Figure 3 1 Chip select signal for the IBS SRE 1A The timing in Figure 3 2 must be observed exactly In the event of access problems 3e when using a Motorola processor e g problems with configuration register access the problems can be solved by connecting pin ENCR to GND 7295 en 01 PHOENIX CONTACT 11 IBS SRE 3 1 Timing for the Microprocessor Interface Write access ICS 0 t E t
19. ternet at www download phoenixcontact com general 7000 en 00 pdf 7295 en 01 PHOENIX CONTACT 17 IBS SRE 1 18 PHOENIX CONTACT 7295_en_01
20. yte 0 1 IBS IN byte 1 IBS OUT byte 1 2 IBS IN byte 2 IBS OUT byte 2 3 IBS IN byte 3 IBS OUT byte 3 4 IBS IN byte 4 IBS OUT byte 4 5 IBS IN byte 5 IBS OUT byte 5 6 IBS IN byte 6 IBS OUT byte 6 7 IBS IN byte 7 IBS OUT byte 7 8 IBS IN byte 8 IBS OUT byte 8 9 IBS IN byte 9 IBS OUT byte 9 10 IBS IN byte 10 IBS OUT byte 10 11 IBS IN byte 11 IBS OUT byte 11 12 CONFREG CLEAR IRQ 13 Unused Unused 14 Unused Unused 15 Unused Unused All registers of the IBS SRE 1A have the default value The INTERBUS data registers are set to their default value via the initialization input ResU and by an INTERBUS reset However the CONFREG configuration register can only be reset via the initialization input ResU 7295 en 01 PHOENIX CONTACT 13 IBS SRE 1A 3 2 1 INTERBUS Data Registers The INTERBUS data registers with addresses 0 to 11 are designed for the exchange of I O data between a slave application and the INTERBUS master The IB IN byte data registers should be written by the slave application This data is IN data for the INTERBUS master whereas the IB OUT byte data registers should be read by the slave application This data is OUT data for the INTERBUS master The value of the data registers falls as the address rises i e fora device with a data width of 8 bytes the byte with address 0 is the high byte and the byte with address 7 is the low byte The value of the data in the memory areas of the IBS SUPI and
Download Pdf Manuals
Related Search