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7534 Group User`s Manual

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1. Data name Structure Operation Synchronize 8 bits Synchronized signal to communicate Packet IDentifier 8 bits Data indicating processing of packet Frame Number 11 bits Data to control the frame during communication by time Address 7 bits Data to confirm the transmit destination of packet and notify from transmitter Endpoint 4 bits Data indicating transfer type used by device Data 8 bits X 0 to 8 bytes Data to be used when the processing specified by PID is executed Token CRCs 5 bits Data to check error when PID is token and SOF Data CRCs 16 bits Data to check error when PID is DATA End Of Packet 2 bits Data indicating the completion of packet Note The DATA numbers in L S are shown in this table PID is classified into 3 kinds in the structure data of Table 2 4 3 Token is used to give the device the instruction of communication processing and report on the processing of the following stages It is only a host to be able to issue the token Data is used to transmit and receive data which is the content of the instruction of the token and execute the processing in the stage It is a host to be able to issue the data when the token is SETUP and OUT and it is a device when the token is IN Handshake indicates the completion of the communication at the end It is a host to be able to issue the handshake when the token is IN and it is a host when the token is SETUP and OUT Table 2 4 4 shows PID
2. 46 Fig 3 5 28 Structure of Serial 1 2 control register 47 Fig 3 5 29 Structure of Serial 1 2 47 Fig 3 5 30 Structure of A D control 48 Fig 3 5 31 Structure of A D conversion register high order 2 49 Fig 3 5 32 Structure of A D conversion register low order 49 Fig 3 5 33 Str ct re of MISAG etii ax d asian pes 50 Fig 3 5 34 Structure of Watchdog timer control register 50 Fig 3 5 35 Structure of Interrupt edge selection register 51 Fig 3 5 36 Structure of CPU mode register 51 Fig 3 5 37 Structure of Interrupt request register 1 52 Fig 3 5 38 Structure of Interrupt control register 1 52 Fig 3 10 1 M37534M4 XXXFP M37534E8FP pin configuration 68 Fig 3 10 2 M37534M4 XXXGP M37534E4GP pin Configuration 69 Fig 3 10 3 M37534M4 XXXSP M37534E8SP M37534RSS pin configuration 70 Rev 3 00 Oct 23 2006 page 8 of 9 RENESAS REJ09B0178 0300 7534 List of tables List of tables CHAPTER 1 HARDWARE Table Pim descrIptiQn Ct xn Eg 8 Table 2 List of supported products 9 Table 3 Push and pop instructions of a
3. 7 Fig 3 2 1 characteristic example double speed 8 Fig 3 2 2 characteristic example at WIT instruction execution 8 Fig 3 2 3 characteristic example At STP instruction execution Ta 25 C 9 Fig 3 2 4 characteristic example At STP instruction execution Ta 85 C 9 Fig 3 2 5 characteristic example at USB suspend Ta 25 C 10 Fig 3 2 6 characteristic example A D conversion executed not executed f Xin 6 2 in double speed 10 Fig 3 2 7 characteristic example of P channel Ta 25 C normal port 11 Fig 3 2 8 characteristic example of P channel Ta 85 C normal port 11 Fig 3 2 9 characteristic example of N channel 25 C Normal port 12 Fig 3 2 10 characteristic example of N channel 85 C Normal port 12 Fig 3 2 11 Vo lo characteristic example of N channel 25 C LED drive 13 Fig 3 2 12 Vo lo characteristic example N channel 85 C LED drive port 13 Fig 3 2 13 L input current of port at pull up transistor connected 14 Fig
4. 38 Fig 3 5 10 Structure of Baud rate 39 Fig 3 5 11 Structure of USB data toggle synchronization register 39 Fig 3 5 12 Structure of USB interrupt source discrimination register 1 39 Fig 3 5 13 Structure of USB interrupt source discrimination register 2 40 Fig 3 5 14 Structure of USB interrupt control 40 Fig 3 5 15 Structure of USB transmit data byte number set register 0 41 Fig 3 5 16 Structure of USB transmit data byte number set register 1 41 Fig 3 5 17 Structure of USB PID control register 0 41 Fig 3 5 18 Structure of USB PID control register 1 42 Fig 3 5 19 Structure of USB address register 42 Fig 3 5 20 Structure of USB sequence bit initialization register 42 Fig 3 5 21 Structure of USB control register 2 2 42 Fig 3 5 22 Structure of Prescaler 12 Prescaler X sese 43 Fig 3 5 23 Str cture of Timer T ua ctp eee xe 43 Fig 3 5 24 Structure of Timer 2 44 Fig 3 5 25 Structure of Timer X mode register 45 3 5 26 Str cture of Timet Xe e deer een 46 Fig 3 5 27 Structure of Timer count source set
5. 33 Fig 2 3 11 Structure of Interrupt control register 1 34 Fig 2 3 12 Serial I O connection examples 35 Fig 2 3 13 Serial connection examples 2 seen 36 Fig 2 3 14 Serial I O transfer data formatl 0 0 37 Fig 2 3 15 Connection diagram eiae cone 38 F1g 2 3 16 Timing ane 38 Fig 2 3 17 Registers setting relevant to transmission 39 Fig 2 3 18 Transmission data setting of Serial 02 40 Fig 2 3 19 Registers setting relevant to reception side 40 Fig 2 3 20 Control procedure of transmission 41 Fig 2 3 21 Control procedure of reception side 42 Fig 2 3 22 Connection tristes 43 2 3 29 MNG RR 43 Fig 2 3 24 Registers setting relevant to transmission side 45 Fig 2 3 25 Registers setting relevant to reception side 46 Fig 2 3 26 Control procedure of transmission 47 Fig 2 3 27 Control procedure of reception enn 48 Fig 2 3 28 Sequence of clearing serial 49 Fig 2 4 1 Communication sequence of 0 5 51 Fig 2 4 2 Data st
6. port 42 pin SDIP 36 pin SSOP 32 pin LQFP Port P1 P10 P16 7 bit structure 10 14 5 bit structure 10 14 5 bit structure Port P2 20 27 8 bit structure 20 27 8 bit structure 20 25 6 bit structure A D converter 8 channel A D converter 8 channel A D converter 6 channel Port P3 P30 P37 8 bit structure P30 P35 P37 7 bit structure P30 P34 5 bit structure INT1 available INTo available INT function not available Port P4 P40 P41 2 bit structure No port No port Rev 3 00 Oct 23 2006 page 51 of 55 5 5 09 0178 0300 7534 Group HARDWARE DIFFERENCES AMONG 32 PIN 36 PIN AND 42 PIN Additionally there are differences of SFR usage and functional defi nitions Table 15 Differences among 32 pin 36 pin and 42 pin SFR Register Address 42 pin SDIP 36 pin SSOP 32 pin LQFP Port P1 Direction 0216 0316 Bit 7 not available Bits 5 to 7 not available Bits 5 to 7 not available Port P2 Direction 0416 0516 All bits available All bits available Bits 6 and 7 not available Port P3 Direction 0616 0716 All bits available Bit 6 not available Bits 5 to 7 not available Port P4 Direction 0816 0916 Bits 2 to 7 not available All bits not available All bits not available Pull up control 1616 Bit 6 definition P35 P36 pull up control Bit 7 definition P37 pull up control
7. Change of A D conversion register Value of comparison voltage Vref At start of conversion 0 0 0 0 VREF First comparison 1 0 0 0 0 0 2 VREF VREF Second comparison 1 1 0 0 0 0 0 0 0 5 t Third comparison 4 A 1 0 0 0 0 0 0 Lisi WEEE 2 4 8 After completion of A result of A D conversion VREF VREF VREF tenth comparison 4 2 34 10 2 4 S 1024 0 A result of the first to tenth comparison Rev 3 00 Oct 23 2006 page 47 of 55 5 5 REJ09B0178 0300 HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT Figures 54 shows A D conversion equivalent circuit and Figure 55 shows A D conversion timing chart 0 to 7 42 version 36 pin version 1 0 to 5 32 version C2 1 5 pF Typical I RUN 12 pF Typical pr Typica Typical voltage Chopper Amp R 1 5 generation circuit 77 Switch tree Vss ladder resistor Notes 1 This is a parasitic diode AD 2 Only the selected analog input is turned Fig 54 A D conversion equivalent circuit Write signal for A D control register 122 XIN cycles AD conversion completion bit Sampling clock Fig 55 A D conversion timing chart Rev 3 00 Oct 23 2006 48 of 55 7tENESAS 09 0178
8. 13 Fig 12 Memory map 4222422 l nnne inten i nennen enne 14 Fig 18 Memory map of special function register SFR 15 Fig 14 Structure of pull up control register 16 Fig 15 Structure of port P1P3 control register 16 Fig 16 Block diagram of 1 iie n acr etr baa 18 Fig 17 Block diagram of ports 2 19 Fig 18 Interrupt control a ER 21 Fig 19 Structure of Interrupt related registers 21 Fig 20 Connection example when using key input interrupt and port PO block diagram 22 Fig 21 Structure of timer X mode register 23 Fig 22 Timer count source set register 2 0 23 Fig 23 Block diagram of timer X timer 1 and timer 2 sse 24 Fig 24 Block diagram of UART serial 1 25 Fig 25 Operation of UART serial 1 01 25 Fig 26 Continuous transmission operation of UART serial 1 0 26 Fig 27 USB mode block diagram 27 Fig 28 USB transceiver block diagram 27 Fig 29 Structure of serial l Orelated registers 1 28 Fig 30 Structure of serial l O1 related registers 2 29 Fig 31 Structure of
9. 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES x INCLUDE TRIM OFFSET 1 lt lt Reference Dimension in Millimeters Symbol Min Nom Max 4 14 94 15 24 15 54 D 36 5 36 7 36 9 E 12 85 13 0 13 15 SEATING PLANE 99 A1 051 A2 38 bp 0 35 0 45 0 55 b2 0 63 0 73 1 03 b3 0 9 1 0 13 0 22 0 27 0 34 9 02 15 e 1 528 1 778 2 028 L 30 5 0036 JEITA Package Code RENESAS Code Previous Code MASS Typ P SSOP36 8 4x15 0 80 PRSP0036GA A 36P2R A 0 5g B O 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET 4 Index mark 18 NI B Reterence Dimension in Millimeters 1 Symbol Min Nom Max s10 D 14 8 15 0 15 2 S E 82 84 86 bp A2 2 0 m 24 0 05 0 35 0 4 0 5 c 0 13 0 15 0 2 2 02 10 Detail F 11 63 11 93 12 2
10. 46 GOnverter ae 47 STOP MOJE 49 Malt mode zu 50 DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP 51 DIFFERENCES AMONG 32 36 PIN AND 42 eene nnns 51 DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY 53 CHAPTER 2 APPLICATION UO pop 2 2 2 1 2 helevant registers ione te 2 2 1 3 Application example of key on wake 6 2 1 4 Handling of unused pins eene entere tenter sistens 7 2 1 5 Notes on input output pins zero Lene eie cota ide rv eb ce dn 8 2 1 6 Termination of unused 9 2 2 10 2 2 1 Memory Map seris eei rede 10 2 2 2 Relevant reglsters E asus 10 2 2 3 Timer application examples 16 2 3 Serial amutu uu suede E 29 Memo y 29 2 3 2 Relevant registers uu reels 29 2 3 3 Serial connection examples 35 Rev 3 00 23 2006
11. HARDWARE GROUP EXPANSION GROUP EXPANSION Renesas plans to expand the 7534 group as follow Memory type Support for Mask ROM version One Time PROM version and Emu lator MCU Memory size ROM PROM size RAM 3122 ROM size Byte 16K Fig 7 Memory expansion plan Currently supported products are listed below Table 2 List of supported products 8 K to 16 K bytes 256 to 384 bytes Package PRSPOOS6GACA 0 8 mm pitch plastic molded SOP PLQPOO032GB A 0 8 mm pitch plastic molded LQFP PRDP0042BA A 42 pin plastic molded SDIP 42SM 42 shrink ceramic PIGGY BACK 384 RAM size Byte P ROM size bytes RAM size Part number ROM size for User bytes Package Remarks M37534M4 XXXFP 8192 8062 256 5 0036 Mask ROM version M37534M4 XXXGP 8192 8062 256 PLQP0032GB A Mask ROM version M37534M4 XXXSP 8192 8062 256 42 Mask ROM version M37534E4GP 8192 8062 256 PLQP0032GB A One Time PROM version blank M37534E8FP 16384 16254 384 5 0036 One Time PROM version blank M37534E8SP 16384 16254 384 PRDP0042BA A One Time PROM version blank M37534RSS 384 4281M Emulator MCU Rev 3 00 23 2006 page 9 of 55 RENESAS REJ09B0178 0300 7534 Group HARDWARE FUNCTIONAL DESCR
12. Serial 1 mode selection bit b7 internal signal Serial 1 01 mode selection bit b6 gt Transmit enable bit Direction register Y Data bus port latch P gt lt USB differential input Serial 1 01 output 1 D input lt USB output enable internal signal 4 Port P12 5 Port P13 pin selection bit Signals during __ Direction output action register Spara pin selection bit Direction oy register Data bus Port latch Spata pin Y selection bit Data bus Port latch P10 P12 P13 input level selection bit 2 P10 P12 P13 inputi Serial 1 02 clock output gt level selection bit Serial 2 clock input Serial 1 02 clock output gt Serial 1 02 clock input P10 P12 P13 P36 P37 input levels are switched to the CMOS TTL level by the port P1P3 control register When the TTL level is selected there is no hysteresis characteristics Fig 16 Block diagram of ports 1 Rev 3 00 Oct23 2006 18 of 55 7tENESAS 09 0178 0300 HARDWARE 7534 Group FUNCTIONAL DESCRIPTION 6 Ports P14 7
13. 2 Use USBVnerour pin USBICON 1 2 Set internal state to USB enabled Set IN token enabled EPOPID XXXX1XXX 2 Set endpoint 0 to be valid USBICON Set endpoint 1 to be valid Set IN token interrupt USBICON 2 Set token interrupt to be valid enabled IREQ1 XXXXXXXO 2 Initialize IN token interrupt request ICON1 XXXXXXX1 2 Set IN token interrupt enable EPOBYTE Set the number of transmit data in this stage USBIR1 Endpoint 0 interrupt occurs if 0 EPOBYTE XXXX9 5 Set the number of transmit data byte TB Write transmit data Max 8 bytes in 1 interrupt processing USBSTS No error if all 0 Error No error can be determined by SUME of bit 6 TRSYNC Toggle normally if 1 In normal tramsmit the next transmit data is set A When communication error or data doggle error occur transmit is executed again B Notes 1 In this figure only USB in interrupt processing is described Note that the storing stack etc is not described 2 IN token interrupt processing of only endpoint 0 is shown in this example 3 Data shown by in program description expresses determination or data setting Fig 2 4 14 USB interrupt processing example IN token Rev 3 00 Oct23 2006 66 of 78 5 5 09 0178 0300 APPLICATION 7534 Group 2 4 USB PID ADDR FOP SYNC PID Data X Data Y l
14. Ba Port PO Input read circuit Port P02 Direction register 0 Port P02 latch Falling edge Es 2 P01 input PULL register bit 1 1 1 detection Port P01 Direction register 0 Port P01 latch 9 P P00 input PULL register bit 0 1 lt Falling edge I detection Port P00 Direction register 0 Port P00 latch Falling edge X E detection ip P channel transistor CMOS output buffer Fig 20 Connection example when using key input interrupt and port PO block diagram gt 2 for pull up Rev 3 00 Oct 23 2006 page 22 of 55 REJ09B0178 0300 RENESAS 7534 HARDWARE FUNCTIONAL DESCRIPTION Timers The 7534 Group has 3 timers timer X timer 1 and timer 2 The division ratio of every timer and prescaler is 1 n 1 provided that the value of the timer latch or prescaler is n All the timers are down count timers When a timer reaches 0 an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer When a timer underflows the inter rupt request bit corresponding to each timer is set to 1 Timer 1 Timer 2 Prescaler 12 always counts 16 Timer 1 and timer 2 always count the prescaler output
15. Bus state detection NRZI BSTFE Reset interrupt request Suspend interrupt request L n Resume interrupt request SYNC decoder PID decoder Y PIDE comparative unit Address p USBA End pointer decoder L CRC check Y CRCE bit stuffing encoder EOP generating unit CRC encoder Transmit shift register SYNC PID generating unit Transmit buffer register I TxRDY Address 001816 EPOBYTE EP1BYTE Token interrupt request i EPOPID EP1PID Fig 27 USB mode block diagram Serial l O1 control register MOD1 77 USB control register UVOE initial value 0 Output enable signal USB reference power source voltage Vol i oltage input Fig 28 USB transceiver block diagram Internal D output signal Internal D output signal Output amplifier D D output amplifier Suspend _ OE internal signal Differential input t lt lt lt lt Single end input Single end input Signal for function stop Output enable signal UUSBVREFOUT OD Rev 3 00 Oct23 2006 page 27 of 55
16. M X AM When T 1 this instruction transfers the con tents M X and M to the ALU which performs a bit wise AND operation and stores the results back in M X When T 1 the contents of A remain unchanged but status flags are changed M X represents the contents of memory where is indicated by X This instruction shifts the content of A or M by one bit to the left with bit 0 always being set to 0 and bit 7 of A or M always being contained in 0 This instruction tests the designated bit i of M or A and takes a branch if the bit is 0 The branch address is specified by a relative ad dress If the bit is 1 next instruction is executed BBS Ai or Mi 1 This instruction tests the designated bit i of the Note 4 M or A and takes a branch if the bit is 1 The branch address is specified by a relative ad dress If the bit is 0 next instruction is executed This instruction takes a branch to the ap pointed address if C is 0 The branch address is specified by a relative address If C is 1 the next instruction is executed This instruction takes a branch to the ap pointed address if C is 1 The branch address is specified by a relative address If C is 0 the next instruction is executed This instruction takes a branch to the ap pointed address when Z is 1 The branch address is specified by a relative address If Z is 0 the next instruction is executed Thi
17. gt Timer or wake up interrupt selection Timer X Timer X mode register address 2B 16 ERE Timer X operating mode Timer mode Timer X count Stop Clear to O when starting count Prescaler X address 2C 16 146 Timer X address 2D 16 Set division ratio Interrupt control register 1 address 16 b7 b0 Timer X interrupt Enabled Interrupt request register 1 address 3C 16 fol Timer interrupt request becomes 1 at 100 ms intervals Fig 2 2 12 Relevant registers setting Rev 3 00 Oct 23 2006 page 18 of 78 7RENESAS REJ09B0178 0300 7534 RESET Initialization SEI INTEDGE address 3A address 2B address 3C address address 2E16 bit0 0 address 2C 16 lt 147 1 address 2D16 lt 256 1 address 2 16 bit3 0 Main processing Procedure for completion of clock set gt Note 1 address 2816 bit8 1 address 2C16 lt 147 1 address 3 16 bit3 0 address 2016 256 1 address 2 16 bit3 0 CLT Note 2 CLD Note 3 Push registers to stack Clock count up 1 10 second to year Pop registers Fig 2 2 13 Control procedure APPLICATION All interrupts disabled Timer X interrupt selected Timer X operating mode Timer mode Clear Timer X interrupt request bit Timer X inte
18. 3 1 3 Electncal characteristi6s sssrin oes 4 3 1 4 A D converter 0 122440100 5 3 1 5 TIMING requirements 6 3 1 6 Switching characteristics 0 22 0 nennen tnter 6 3 2 Typical characteristics ll u Uu u u uu uu u uu u u J 8 3 2 1 Power source current characteristic example characteristic 8 3 2 2 characteristic 11 3 2 3 A D conversion typical characteristics 15 3 3 Notes on ANE 17 3 3 1 Notes on Ii Ierrgp Su 17 3 3 2 Notes on Serial 18 3 3 3 Notes on A D converter 442244 1 a 19 3 3 4 Notes on watchdog 20 3 3 5 Notes on BESET 20 3 3 6 Notes on input and output PINS 20 3 3 Notes oni prograimiming eed ce b rnt 21 3 3 8 Programming and test of built in PROM 22 3 3 9 Notes on built in PROM version 2
19. Input ports and ports Do not open in the input mode Reason power source current may increase depending on the first stage circuit An effect due to noise may be easily produced as compared with proper termination and shown on the above I O ports When setting for the input mode do not connect to or 55 directly Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between a port and Vcc or 55 I O ports When setting for the input mode do not connect multiple ports a lump to Vcc or Vss through a resistor Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between ports At the termination of unused pins perform wiring at the shortest possible distance 20 mm or less from microcomputer pins Rev 3 00 Oct 23 2006 page 24 of 70 7tENESAS 09 0178 0300 APPENDIX 7534 Group 3 3 Notes on use 3 3 11 Notes on CPU mode register 1 Switching method of CPU mode register after releasing reset Switch the CPU mode register CPUM at the head of program after releasing reset in the following method Wait until ceramic oscillator clock is stabilized After releasing reset Start with an on chip oscillator Note Switch the clock division ratio Switch to other mode ex
20. U U 55 3 8 Machine instructions 56 3 9 d WuluclAaur eec 67 3 10 Pin configurations eene nennen nennen nnne nnnm nnne snnt nnne u uu u J 68 Rev 3 00 Oct 23 2006 page 3 of 9 RENESAS REJ09B0178 0300 7534 List of figures List of figures CHAPTER 1 HARDWARE Fig 1 Pin configuration of 37534 37534 0 2 Fig 2 Pin configuration of M37534M4 XXXGP M37534E4GP 3 Fig 3 Pin configuration of M37534RSS M37534M4 XXXSP M37534E8SP 4 Fig 4 Functional block diagram PRSPOO36GA A package type 5 Fig 5 Functional block diagram PLQP0032GB A package type 6 Fig 6 Functional block diagram PRDPO042BA A package type 7 Fig 7 Memory expansi n Plan u aa seed tec De de Re 9 Fig 8 740 Family CPU register structure nennen nennen 10 Fig 9 Register push and at interrupt generation and subroutine call 11 Fig 10 Structure of CPU mode 13 Fig 11 Switching method of CPU mode register
21. 6 P27 AN7 40 USBVREFOUT P41 P37 INTo VREF gt INT1 RESET CNVss X CO NN O1 Cl CO 5 nS x 52 52 0 45834 8 6 Outline PRDP0042BA A Connect a bypass capacitor to a device 2 Connect a capacitor to a device as as close as possible For the capacitor close as possible For the capacitor a ceramic capacitor or an electrolytic a ceramic capacitor or an electrolytic capacitor of 1 0 uF is recommended capacitor of 0 22 uF is recommended Reason of is to reduce the effect by switcing noise of microcomputer to the analog circuit generating USBVREFOUT output Use the bigger capacitor and connect to device at the shortest distance Reason of is to prevent the instability of the USBVREFOUT output due to external noise Fig 58 Handling of Vcc USBVREFOUT pins of M37534E8SP M37534M4 XXXSP M37534RSS Rev 3 00 Oct 23 2006 page 55 of 55 5 5 09 0178 0300 THIS PAGE IS BLANK FOR REASONS OF LAYOUT 2 APPLICATION 2 1 I O port 2 2 Timer 2 3 Serial 2 4 USB 2 5 A D converter 2 6 Reset APPLICATION 7534 Group 2 1 port 2 1 I O port This paragraph explains the registers setting method and the notes relevant to the I O ports 2 1 1 Memory map 000516 000616 000716 000816 000916 Port P4 direction register P4D Fig 2 1 1 Memory map of registers re
22. BJ Fm pfa Oscillation stabilization time 0 Set 0116 in timer 1 and set bit after release of the in prescaler 12 STP instruction automatically 1 Not set automatically These are reserved bits 0 ER Do not write 1 to these bits EX EZ Nothing is allocated for these bits These are write disabled bits fox When these bits are read out the values 0 x Ege EXE Fig 3 5 33 Structure of MISRG Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 50 Watchdog timer control register WDTCON Address 39 16 W Watchdog timer H EEG The high order 6 bits are read only bits STP instruction disable bit STP instruction enabled STP instruction disabled Watchdog timer H count gt Watchdog timer L underflow source selection bit 1 16 Fig 3 5 34 Structure of Watchdog timer control register Rev 3 00 Oct 23 2006 page 50 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register INTEDGE Address 16 B ___ Funcion INTo interrupt edge 0 Falling edge active selection bit Note 1 1 Rising edge active INT interrupt edge 0 Falling edge active selection bit Note 2 1 Rising edge active When these bits are read out the val
23. 9 OF 89 l e 08 Ay Detail F x 020 7 040 Zo 07 Ze 07 L 0 3 0 5 07 L 1 0 Rev 3 00 Oct 23 2006 page 54 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 7 List of instruction code 3 7 List of instruction code JSR ZP IND CLT JSR SP LDX IMM JMP ZP IND WIT 3 byte instruction 2 byte instruction 1 byte instruction Rev 3 00 Oct23 2006 55 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 8 Machine instructions 3 8 Machine instructions Addressing mode Function Details A BIT A R ZP BIT ZP R JOP n OP When T 0 When T 0 this instruction adds the contents 2 and stores the results in When 1 this instruction adds the contents When T 1 of M X M and C and stores the results in MX M C M X and C When T 1 the contents of A re main unchanged but the contents of status flags are changed M X represents the contents of memory where is indicated by X When 0 When T 0 this instruction transfers the con tents of M to the ALU which performs a bit wise AND operation and stores the result When T 1 back in A
24. Bit 6 definition P35 pull up control Bit 7 definition P37 pull up control Bits 6 and 7 not available Port P1P3 control 1716 Bit 0 definition P37 INTo input level selection Bit 1 definition P36 INT1 input level selection Bit 0 definition P37 INTo input level selection Bit 1 not available Bits 0 and 1 not available A DControl 3416 Bits 0 to 2 Input pins selected by setting these bits to 000 to 111 Bits 0 to 2 Input pins selected by setting these bits to 000 to 111 Bits 0 to 2 Input pins selected by setting these bits to 000 to 101 Interrupt edge selection 16 Bit 0 definition INTo interrupt edge selection Bit 1 definition INT1 interrupt edge selection Bit 4 definition Serial 1 01 interrupt selection Bit 0 definition INTo interrupt edge selection Bits 1 and 4 not available Bits 0 1 and 4 not available Interrupt request 3 16 Bit 1 definition UART transmission USB except IN INT1 Bit 2 definition Bit 1 definition UART transmission USB except IN Bit 2 definition Bit 1 definition UART transmission USB except IN Bit 2 not available Interrupt control 3E16 REJ09B0178 0300 Bit 1 definition UART transmission USB except INT1 Bit 1 definition UART transmission USB except IN
25. Bm receive USBIN token disabled interrupt enable bit Interrupt enabled UART transmit USBSETUP Interrupt disabled OUT token Reset Suspend 1 Interrupt enabled Resume INT interrupt enable INTo interrupt enable bit 0 Interrupt disabled Note 2 1 Interrupt enabled 3 Timer X or key on wake up 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 4 Timer 1 interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 2 or serial 2 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled CNTRo or AD converter 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 Nothing is allocated for this bit Do not write 1 to this bit When this bit is read out the value is 0 Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 3 5 38 Structure of Interrupt control register 1 Rev 3 00 23 2006 52 of 70 1320 NE ESAS REJO9B01 78 0300 APPENDIX 7534 Group 3 6 Package outline 3 6 Package outline PRDP0042BA A JEITA Package Code RENESAS Code Previous Code MASS Typ P SDIP42 13x36 72 1 78 PRDP0042BA A 42P4B 4 1g nnannaannaannannnnnnf UUUUUUUUUUUUUUUUUUUUU wore
26. 1 1 1 1 Reset interrupt occurs i 1 1 1 1 1 1 1 1 Resume interrupt enable RSME Remote wake up request flag WKUP Notes 1 In this example USB reset interrupt enable flag RSTE 1 enabled 2 The remote wake up request flag WKUP is not set to 1 when host does not request the remote wake up signal output 3 External input interrupts key on wake up INT o INT1 and CNTRo interrupt Fig 2 4 18 Timing chart of each signal Rev 3 00 Oct 23 2006 page 68 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 2 4 5 Notes concerning USB 1 Determination of interrupt condition in OUT token interrupt processing Determine the occurrence of the reset suspend resume interrupt from other interrupt conditions in the order as shown in Figure 2 4 19 when they occur in the OUT token interrupt processing Not used here OUT token interrupt Set it to 0 or 1 arbitrary Reset gt Interrupt source Reset USBIR2 XXXX XXX Interrupt by Reset occurs if 1 To Reset No Reset processing Suspend Interrupt source Suspend USBIR2 XXXXX XX 2 Interrupt by Suspend occurs if 1 To Suspend No Suspend processing 6 Resume enabled a Interrupt control Enabled USBICON XX XXXXX 2 Interrupt by Resume occurs if RSME 1 To Resume esume disabled Note Set 1 to RSME only in Suspend processing processing i No Token interrupt
27. Not used returns 1 when read Continuous transmit valid bit 0 Continuous transmit invalid 1 Continuous transmit valid Transmit interrupt source selection bit 0 Interrupt when transmit buffer has emptied 1 Interrupt when transmit shift operation is completed Transmit enable bit 0 Transmit disabled 1 Transmit enabled Receive enable bit 0 Receive disabled 1 Receive enabled Serial 1 mode selection bits 00 I O port 01 Not available 10 UART mode 11 USB mode CPU read Disabled CPU write Set Clear Hardware read Used Hardware write Not used CPU read Disabled CPU write Set Clear Hardware read Used Hardware write Not used CPU read Disabled CPU write Set Clear Hardware read Used Hardware write Not used Rev 3 00 Oct23 2006 page 32 of 55 REJ09B0178 0300 RENESAS 7534 HARDWARE FUNCTIONAL DESCRIPTION Note on using USB mode Handling of SEO signal in program at receiving 7534 group has the border line to detect as USB RESET or EOP End of Packet on the width of SEO Single Ended 0 A response apposite to a state of the device is expected The name of the following short words which is used in table 5 shows as follow TKNE Token interrupt enable bit 6 of address 2016 RSME Resume interrupt enable bit 5 of address 2016 RSTE USB reset interrupt enable bit 4 of address 2016 Spec A response of the device requested by Low Speed
28. input current of port at pull up transistor connected Rev 3 00 Oct 23 2006 page 14 of 70 7tENESAS 09 0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics 3 2 3 A D conversion typical characteristics example 1 Definition of A D conversion accuracy The A D conversion accuracy is defined below refer to Fig 3 2 14 Relative accuracy Zero transition voltage Vor This means an analog input voltage when the actual A D conversion output data changes from 0 to 1 Full scale transition voltage Vest This means an analog input voltage when the actual A D conversion output data changes from 1023 to 1022 Non linearity error This means a deviation from the line between Vor and Vrst of a converted value between Vor and Vest Differential non linearity error This means a deviation from the input potential difference required to change a converted value between Vor and Vrsr by 1 LSB of the 1 LSB at the relative accuracy Absolute accuracy This means a deviation from the ideal characteristics between 0 to Vrer of actual A D conversion characteristics Output data Full scale transition voltage 1023 1022 Differential non linearity error LSB Non linearity error LSB Actual A D conversion h s characteristics a 1LSB at relative accuracy b Vn 1 Vn c Difference between the ideal Vn and actual Vn 2 Ideal line of A D conversion betwe
29. 10 bit X 8 channels e Clock generating circuit Built in type connect to external ceramic resonator or quartz crystal oscillator e Watchdog timer iicet caeteri 16 bit X 1 Power source voltage At 6 MHz XIN oscillation frequency at ceramic resonator MUTET 4 1 to 5 5 V 4 4 to 5 25 V at USB operation Power dissipation 30 mW standard Operating temperature range 20 to 85 C 0 to 70 C at USB operation Built in USB 3 3 V Regulator transceiver based Low Speed USB2 0 specification APPLICATION Input device for personal computer peripherals P11 TxD D P10 RxD D P07 06 05 04 02 1 USBVREFOUT P37 INTo Outline PRSPOO36GA A 36P2R A Fig 1 Pin configuration of M37534M4 XXXFP M37534E8FP Rev 3 00 23 2006 2 of 55 REJ09B0178 0300 7tENESAS HARDWARE 7534 Group PIN CONFIGURATION PIN CONFIGURATION TOP VIEW 07 lt gt 25 LED4 P1o RxD D lt 56 LEDs P11 TxD D lt 27 LED2 P12 ScLk 58 M37534M4 XXXGP LED P13 SDATA lt 29 M37534E4GP LEDo P14 CNTRo lt 30 P20 ANo lt 31 P21 AN1 lt 32 1 z ai N A Outline PLQP0032GB A 32P6U A Fig 2 Pin configuration of M37534M4 XXXGP M37534E4GP Rev 3 00 Oct 23 2006 page of 55 5 5 REJ09B0178 0300 7534 Group PIN CONFIGURATION
30. 4 Rev 3 00 Oct 23 2006 page 61 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 2 4 4 USB application example In this section the application examples when using the USB communication are described using examples of the timing chart and register setting 1 Example of processing each control sequence In 7534 Group the control and the determination of the control sequence are executed by software The content of processing is executed in the setup stage transmitting and receiving the data stage of the content are executed and the completion of the sequence is shown in the status stage Note that the contents of the control and the determination are different even in the software of 7534 Group because the following processing is different respectively depending on the content of the setup stage In the control transfer the processing since the data stage is determined when receiving the setup stage the execution of the transmit and receive processing and the number of data bytes are controlled the status stage at the end is executed and the sequence is completed Only the control of each packet is performed because there is no stage in the interrupt transfer Figure 2 4 11 shows the control method of control sequence 1 Control Read Setup Stage Data Stage Status Stage i Endpoint 0 valid 1 Endpoint 0 invalid Endpoint 0 enable flag EP0E 1 0 0 i i Endpoint 0 PID selection flag OUT token
31. APPLICATION 7534 Group 2 5 A D converter 2 5 3 A D converter application examples 1 Conversion of analog input voltage Outline The analog input voltage from a sensor is converted to digital values Figure 2 5 8 shows a connection diagram and Figure 2 5 9 shows the relevant registers setting 7534 Group Fig 2 5 8 Connection diagram Specifications analog input voltage from a sensor is converted to digital values P2v ANo pin is used as an analog input pin A D control register address 3416 b7 50 Analog input pin P20 ANo selected A D conversion start A D conversion register high order address 3616 b7 bo ud A D conversion register low order address 3516 b7 50 A result of A D conversion is stored Note Note After bit 4 of ADCON is set to 1 read out that contents When reading 10 bit data read address 003616 before address 003516 when reading 8 bit data read address 003516 only Fig 2 5 9 Relevant registers setting Rev 3 00 Oct 23 2006 page 75 of 78 5 5 REJ09B0178 0300 7534 Group APPLICATION 2 5 A D converter An analog input signal from a sensor is converted to the digital value according to the relevant registers setting shown by Figure 2 5 9 Figure 2 5 10 shows the control procedure for 8 bit read and Figure 2 5 11 shows the control procedure for 10 bit read ADCON address 3416 bit2 lt
32. Address 31 16 A shift register for serial transmission and reception At transmitting Set a transmission data At receiving A reception data is stored EXE 998 Fig 2 3 8 Structure of Serial l O2 register Rev 3 00 Oct 23 2006 32 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register INTEDGE Address 16 B 2 Funcion Jarse R W INTo interrupt edge 0 Falling edge active B selection bit Note 1 1 Rising edge active INT interrupt edge 0 Falling edge active selection bit Note 2 1 Rising edge active Nothing is allocated for these bits These are write disabled bits When these bits are read out the values 0 gg Serial 1 O1 or INT interrupt x Serial 1 1 selection bit LINT Timer X or key on wake up m Timer X EXE interrupt selection bit 1 Key on wake up Timer 2 or serial 1 2 interrupt 0 Timer 2 selection bit 1 Serial 2 7 CNTRo or AD converter 0 CNTRo interrupt selection bit 1 AD converter Notes 1 32 pin version Not used This is a write disabled bit When this bit is read out the value is 0 2 36 pin and 32 pin version Not used This is a write disabled bit When this bit is read out the value is O Fig 2 3 9 Structure of Interrupt edge selection
33. CMOS output Rev 3 00 Oct 23 2006 page 6 of 70 REJ09B0178 0300 7RENESAS APPENDIX 7534 Group 3 1 Electrical characteristics tc CNTR twH CNTR twH INT INTo INT1 Nem s tw RESET 0 8Vcc 0 2Vcc twH XIN twL ScLk twH SCLk 0 8Vcc tsu SDATA SCLK th ScLk SDATA Ke 0 8Vcc 355555555000 SDATA at receive 050 0 2 Vcc ta Scuk SparA tv ScLk SDATA SDATA at transmit Fig 3 1 3 Timing chart Rev 3 00 Oct 23 2006 page 7 of 70 5 5 09 0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics 3 2 Typical characteristics 3 2 1 Power source current characteristic example characteristic Measuring condition Typical sample Ta 25 C ceramic oscillation when operating system in double speed mode A D conversion not executed lt 2 c g 2 o 2 o o 40 45 Power source voltage Vcc V Fig 3 2 1 Icc Vcc characteristic example in double speed mode Measuring condition Typical sample Ta 25 ceramic oscillation At WIT instruction execution at wait 6 MHz lt 2 2 o o o 5 o Power source voltage Vcc V Fig 3 2 2 characteristic example at WIT instruction execution Rev
34. H input current XIN Vi Voc L input current P00 P07 10 16 20 27 P30 P37 P40 P41 Vi VSS Pin floating Pull up transistors off L input current RESET CNVss VI 55 L input current XIN VI 55 L input current P00 P07 P30 P37 VI 55 Pull up transistors on RAM hold voltage When clock stopped Note 1 11 is measured when the P channel output disable bit of the UART control register bit 4 of address 001B16 is 0 2 SCLK SDATA INTo and have hystereses only when bits 0 1 and 2 of the port P1P3 control register are set to 0 CMOS level 3 It is available only when operating key on wake up Rev 3 00 Oct 23 2006 4 of 70 REJ09B0178 0300 7RENESAS 7534 APPENDIX 3 1 Electrical characteristics Table 3 1 4 Electrical characteristics 2 Vcc 4 1 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions Limits Typ Power source current Double speed mode 6 MHz Output transistors off 6 f XIN 6 MHz WIT state Output transistors off 1 6 Increment when A D conversion is executed f XIN 6 MHz Vcc 5 V 0 8 All oscillation stopped in STP state Output transistors off Ta 25 0 1 Ta 85 3 1 4 A D converter characteri
35. IRE Ld uod uod oa oa dn 62 2 26209 m ea 1NO438 ASN 8 20 5 eee Y 01 av 8 1 8 X 8 z 8 1 WOU IN V H yesoy Bopyoyen 2015 indui 18s u 6 amp 1 NIX indino ndu 42012 v 852 00dO1d 42018 IWNOILONNS Fig 5 Functional block diagram PLQP0032GB A package type RENESAS Rev 3 00 Oct 23 2006 6 of 55 REJO9BO01 78 0300 HARDWARE FUNCTIONAL BLOCK Od Wis 1 r m oa BOO 1nodagAgsn ji ii 8 sasn 8 LO IS oe uod D Hod T sh 2D 03 0D 9 CO VE CDD D bd OLNI 1 01 8 x 8 X 8 8 21 8 H H 2
36. P1o P12 P13 input level gt CMOS level selection bit TTL level Notes 1 For the 32 pin version nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 2 For the 32 pin and 36 pin versions nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 Fig 2 1 5 Structure of P1P3 control register Interrupt edge selection register b7 b6 b5 64 b3 b2 bO Interrupt edge selection register INTEDGE Address 16 At reset P interrupt edge T Falling edge active selection bit Note 1 Rising edge active INT interrupt edge 7 Falling edge active selection bit Note 2 Rising edges active When these bits are read out the values are 0 EXE 4 Serial l O1 or INT interrupt 0 Serial 1 selection bit 1 INT 5 Timer X or key on wake up 0 Timer X interrupt selection bit 1 Key on wake up Timer 2 or serial 2 interrupt 0 Timer 2 selection bit 1 Serial 1 02 7 CNTRo or AD converter 0 CNTRo interrupt selection bit 1 AD converter Notes 1 32 pin version Not used This is a write disabled bit When this bit is read out the value is 0 2 36 pin and 32 pin version Not used This is a write disabled bit When this bit is read out the value is 0 Fig 2 1 6 Structure of Interrupt edge selection re
37. P20 P30 P37 P40 P41 L total peak output current Note 1 7 10 16 P20 P37 P40 P41 L total peak output current Note 1 P30 P36 H total average output current Note 1 00 07 10 16 P20 P30 P37 P40 P41 L total average output current Note 1 7 10 16 P20 P37 P40 P41 L total average output current Note 1 P30 P36 H peak output current Note 2 7 10 16 P20 P30 P37 P40 P41 L peak output current Note 2 00 07 10 16 P20 P37 P4o P41 L peak output current Note 2 P30 P36 H average output current Note 3 7 10 16 P20 37 P40 P41 L average output current Note 3 00 07 10 16 P20 P37 P40 P41 L average output current Note 3 P30 P36 Oscillation frequency Note 4 Vcc 4 1 to 5 5 V at ceramic oscillation or external clock input Double speed mode Note 1 The total output current is the sum of all the currents flowing through all the applicable ports The total average current is an average value measured a term of 100 ms The total peak current is the peak value of all the currents 2 The peak output current is the peak current flowing in each port 3 The average output current IOL avg avg an average value measured a term of 100 ms 4 When the oscillation frequency has
38. P36 40 47 e 32 pin version Ports 15 17 P26 P27 35 37 40 47 Fig 2 1 3 Structure of Port Pi direction register i 0 to 4 Pull up control register b7 b6 b5 b4 b3 b2 bi Pull up control register PULL Address 16 16 pull up control bit 5 Pull up Pull up On PO pull up control bit E Pull up Off 1 Pull up On 2 POs pull up control bit 0 Pull up Off 1 1 Pull up On 3 P04 pull up control bit 0 Pull up Off 1 1 Pull up On 4 P30 P33 pull up control bit 0 Pull up Off 1 1 Pull up On 5 P34 pull up control bit 0 Pull up Off 1 1 Pull up On P35 pull up control bit 0 Pull up Off 1 Note 2 1 Pull up On P37 pull up control bit 0 Pull up Off 1 Note 3 1 Pull up On Notes 1 Pins set to output are disconnected from the pull up control 2 36 pin version P36 is not existed 32 pin version Not used 3 32 pin version Not used Fig 2 1 4 Structure of Pull up control register Rev 3 00 Oct 23 2006 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 1 port Port P1P3 control register b7 b6 b5 64 b3 b2 bi bO Port P1P3 control register P1P3C Address 17 16 B Nam P37 INTo input level selection 1 CMOS level bit Note 1 TTL level P3e INT1 input level selection CMOS level bit Note 2 TTL level
39. The INT1 interrupt does not exist in the 36 pin and 32 pin version 4 The INTo interrupt does not exist in the 32 pin version Rev 3 00 Oct23 2006 page 45 of 55 REJ09B0178 0300 5 5 HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt instruction that is currently in execution Figure 52 shows a timing chart after an interrupt The interrupt processing routine begins with the occurs and Figure 53 shows the time up to execution machine cycle following the completion of the of the interrupt processing routine RD WR Address bus PC 5 5 ses fea sss X BL X BH XAL AH Data bus X Notused XPCHYXPCLY PS X AL X AH X SYNC CPU operation code fetch cycle BL BH Vector address of each interrupt AL AH Jump destination address of each interrupt SPS 0016 or 0116 Fig 52 Timing chart after an interrupt occurs Generation of interrupt request Start of interrupt processing Waiting time for stack push and Main routine post processing 2 Interrupt processing routine o f pipeline 0to7 cycles 2 cycles 5 cycles 7 to 14 cycles At performing 6 0 MHz in double speed mode 1 17 us to 2 34 us Fig 53 Time up to execution of the interrupt processing routine Rev 3 00 Oct23 2006 page 46 of 55 7tENESAS 09
40. UART control register UARTCON 003816 CPU mode register CPUM 001 16 Baud rate generator BRC 003 16 Interrupt request register 1 IREQ1 001016 USB data toggle synchronization register TRSYNC 003016 r l LU ee ee SE 001E16 USB interrupt source discrimination register 1 USBIR1 003E16 Interrupt control register 1 ICON1 001 6 USB interrupt source discrimination register 2 USBIR2 003F16 r j CGj O Rev 3 00 23 2006 page 67 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 10 Pin configurations 3 10 Pin configurations Top view P12 SCLK P11 TxD D P13 SDATA lt gt P1o RxD D P14 CNTRo 0 P20 ANo P21 AN1 POs P22 AN2 lt gt P04 P23 AN3 lt gt P24 AN4 lt gt P02 P25 AN5 lt gt 1 26 P27 AN7 lt gt USBVREFOUT VREF P37 INTo RESET P35 LEDs5 CNVss P34 LED4 Vcc XIN XOUT lt gv N T 60 aL ddXXX vINVESZEIN 2 3 LEDs 1 LED1 o LEDo P3 P3 P3 P3 Outline PRSPOO36GA A Fig 3 10 1 M37534M4 XXXFP M37534E8FP pin configuration Rev 3 00 Oct 23 2006 page 68 of 70 RENESAS REJ09B0178 0300 7534 view 25 P1o RxD D lt 26 P11 TxD D 27 P12 ScLk lt 8 P13 SDATA lt 29 P14 CNT Ro lt 30 P20 ANo lt 31 P21 AN1 lt 32 APPENDIX 3 10 Pin config
41. address 0016 bitO lt 0 Setting of port for communication control address 0116 XXXXXXX12 Generating of a 10 ms interval using Timer PO address 0016 lt 1 Communication start I Transmission data write The first byte of data This write causes Transmit buffer empty flag to be cleared to 0 TB RB address 18 16 lt Confirmation of transfer from Transmit UARTSTS address 19 16 bito 2 buffer register to Transmit shift register Transmit buffer empty flag Transmission data write TB RB address 1816 he second byte of This write causes Transmit buffer empty transmission data flag to be cleared to 0 Confirmation of transfer from Transmit UARTSTS address 19 16 bito 2 buffer register to Transmit shift register Transmit buffer empty flag Confirmation of Transmit shift register s shift UARTSTS address 1916 bit2 completion Transmit shift register shift completion flag address 0016 bitO 0 Communication completion Fig 2 3 26 Control procedure of transmission side Rev 3 00 Oct 23 2006 page 47 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O RESET Initialization X This bit is not used here Set it to 0 or 1 arbitrary SIO1CON address 1 16 lt 101000012 Serial l O1 setting UARTCON address 1 16 lt 000010002 BRG address 1C16 8 1
42. uuu T 2 FEATURES esse E E 2 APPLICATION uuu cect aaaea aeaaea aa aaan aeaa eaaa aaa eaaa a aa abaa iaaah 2 PIN 2 FUNGTIONAL BLOGK u u III ea paa aaa 5 PIN DESCRIPTION Mec Eaa a as aeaa P 8 22252 20 9 FUNCTIONAL DESCRIPTION IILI uA cta nie ere oaa 10 Central Processing Unit 10 Mug 14 VO PONS icc aina a aaa eaaa aaa E a aeaa aE 16 ONUD 20 Ssss Eaa 23 Serial DRESS 25 CONVO UCM 36 aia aaae aeae a aeaa AE E NA A E E AE a a 38 Clock Generating nann 40 NOTES ON PROGRAMNMINGQ U U u 42 NOTES ON USE uuu u as chest ace n aan UL Ic 42 DATA REQUIRED FOR MASK ORDERS U u u u u u u 43 FUNCTIONAL DESCRIPTION SUPPLEMENT u u u u u u 45 OUDE y 45
43. 0002 ADCON address 3416 bit4 lt 0 ADCON address 3416 bit4 1 Read out ADL address 3516 Fig 2 5 10 Control procedure for 8 bit read ADCON address 3416 bitO bit2 0002 ADCON address 3416 bit4 lt 0 ADCON address 3416 bit4 1 Read out ADH address 3616 Read out ADL address 3516 Fig 2 5 11 Control procedure for 10 bit read P20 ANo pin selected as analog input pin A D conversion start Judgment of A D conversion completion Read out of conversion result 2 pin selected as analog input pin A D conversion start Judgment of A D conversion completion Read out of high order digit b9 b8 of conversion result Read out of low order digit 07 bO of conversion result Rev 3 00 Oct23 2006 page 76 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 5 A D converter 2 5 4 Notes on A D converter 1 Analog input pin Make the signal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01uF to 1uF Further be sure to verify the operation of application products on the user side Reason An analog input pin includes the capacitor for analog voltage comparison Accordingly when signals from signal source with high impedance are input to an analog input pin charge and discharge noise generates This may cause the A D conversion comparison precision to be worse 2 Clock
44. 0300 APPENDIX 7534 Group 3 5 List of registers Refer to Figure 2 4 6 Description of register structure for registers relevant to USB USB PID control register 1 EP1PID Address 24 16 67 b6 b5 64 b3 b2 bi 00 FN CPU CPU HW HW Initial value 0 WR RD WR Endpoint 1 PID selection 1X IN token interrupt of DATA0 1 is valid Enable Use flag IN STALL 01 STALL handshake is valid for IN token Clea 00 NAK handshake is valid for IN token Endpoint 1 PID selection Enable Set Use Clear flag IN DATAO 1 Clea DPID1 and SPID1 are used to control the response for IN token DPID1 is used with the token interrupt enable flag TKNE DPID1 is cleared to 0 automatically by hardware when is received X it can be set to 0 or 1 Fig 3 5 18 Structure of USB PID control register 1 USB address register USBA Address 25 16 Initial value Fig 3 5 19 Structure of USB address register USB sequence bit initialization register INISQ1 Address 26 16 67 b6 b5 b4 b3 62 61 00 RD WR RD WR Initial value As sequence bit of endpoint 1 is Dummy initialized Sequence is initialized by writing dummy Fig 3 5 20 Structure of USB sequence bit initialization register USB control register USBCON Address 27 16 07 b6 65 64 b3 62 b 00 maaa RD WR RD WR USBVREFOUT output 0 Output off Set Use valid flag 1 Output on
45. 1 Control of Event interval Timer X Timer 1 Timer 2 When a certain time by setting a count value to each timer has passed the timer interrupt request occurs lt Use gt Generation of an output signal timing Generation of a wait time Function 2 Control of Cyclic operation Timer X Timer 1 Timer 2 The value of the timer latch is automatically written to the corresponding timer each time the timer underflows and each timer interrupt request occurs in cycles Use Generation of cyclic interrupts Clock function measurement of 100 ms see Application example 1 Control of a main routine cycle Function 3 Output of Rectangular waveform Timer X The output level of the CNTRo pin is inverted each time the timer underflows in the pulse output mode Use Piezoelectric buzzer output see Application example 2 Generation of the remote control carrier waveforms Function 4 Count of External pulses Timer X External pulses input to the CNTRo pin are counted as the timer count source in the event counter mode Use Frequency measurement see Application example 3 Division of external pulses Generation of interrupts due to a cycle using external pulses as the count source count of a reel pulse Function 5 Measurement of External pulse width Timer X The or L level width of external pulses input to CNTRo pin is measured in the pulse width measurement mode Use Measurement of externa
46. 1 IREQ1 Address 3C 16 NEN NENNEN IU Eum receive USBIN token P No interrupt request issued interrupt request bit Interrupt request issued UART transmi USBSETUP 0 No interrupt request issued OUT token Reset Suspend 1 Interrupt request issued Resume INT interrupt request bit Note 1 INTo interrupt request bit No interrupt request issued Note 2 Interrupt request issued 3 Timer X or key on wake up No interrupt request issued interrupt request bit 1 Interrupt request issued 4 Timer 1 interrupt request bit 0 No interrupt request issued 1 Interrupt request issued 5 Timer 2 or serial 1 2 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued CNTRo or AD converter 0 No interrupt request issued interrupt request bit 1 Interrupt request issued 7 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 These bits can be cleared to 0 by program but cannot be set Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 3 5 37 Structure of Interrupt request register 1 Interrupt control register 1 b7 06 b5 b4 b3 b2 bi Interrupt control register 1 ICON1 Address 3E 16 _ Function At reset R W
47. 1 7 Structure of Interrupt request register 1 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 bO Interrupt control register 1 ICON1 Address 16 B Name Funcio 1 jJwss R w UART receive USBIN token 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled UART transmit USBSETUP 0 Interrupt disabled OUT token Reset Suspend 1 Interrupt enabled Resume INT interrupt enable INTo interrupt enable bit Interrupt disabled Note 2 Interrupt enabled 3 Timer X or key on wake up Interrupt disabled interrupt enable bit Interrupt enabled 4 Timer 1 interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 Timer 2 or serial 1 2 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled CNTRo or AD converter 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 Nothing is allocated for this bit Do not write 1 to this bit When this bit is read out the value is 0 Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 2 1 8 Structure of Interrupt control register 1 Rev 3 00 Oct 23 2006 page 5 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 1 port 2 1 3 Application example of key on wake up Outline The built in pull up resistor is used P
48. 256 1 p 174 ms intervals bits NK Clear Timer X interrupt request bit 686 0 Clear CNTRo interrupt request bit address 3 16 B EP X interrupt enabled s 1 ONTRo interrupt enabled address 2B 16 bit3 lt 0 Timer X count start Interrupts enabled CNG Timer X interrupt process routine Process errors Error occurs CNTRo interrupt process routine CLT Note 1 Note 1 When using Index X mode flag T CLD Note 2 Note 2 When using Decimal mode flag D Push registers to stack Push registers used in interrupt process routine A PREX Read the count value and store it to RAM Low order 8 bit result of lt Inverted A pulse width measurement A TX High order 8 bit result of Inverted A pulse width measurement PREX address 2C16 lt 256 1 Set division ratio so that Timer X interrupt will occur at TX address 2016 256 1 174 ms intervals Pop registers Pop registers pushed to stack Fig 2 2 23 Control procedure Rev 3 00 Oct 23 2006 28 of 78 1320 NE SAS REJO9B01 78 0300 APPLICATION 7534 Group 2 3 Serial I O 2 3 Serial I O This paragraph explains the registers setting method and the notes relevant to the serial I O 2 3 1 Memory map 003016 Serial l O2 control register SIO2CON 003116 Serial 2 register 51 2 A 003A16 Interrupt edge selection register INTEDGE 003 16
49. 3 2 14 Definition of A D conversion 2 2 15 Fig 3 2 15 A D conversion typical characteristic 16 Fig 3 3 1 Sequence of switch the detection 17 Fig 3 3 2 Sequence of check of interrupt request bit 17 Fig 3 3 3 Structure of interrupt control register 1 18 Fig 3 3 4 Sequence of clearing serial 1 18 Fig 3 3 5 Method to stabilize A D conversion 1 19 Fig 3 3 6 Initialization of processor status 21 Fig 3 3 7 Sequence of PLP instruction execution 21 Fig 3 3 8 Stack memory contents after PHP instruction execution 21 Fig 3 3 9 Status flag at decimal calculations 22 Fig 3 3 10 Programming and testing of One Time PROM version 22 Fig 3 3 11 Switching method of CPU mode register 25 Fig 3 3 12 Countermeasure 2 by software 26 Fig 3 4 1 Selection of packages 27 Fig 3 4 2 Wiring for the RESET pin aaepe RM lote 27 Fig 3 4 3 Wiring for clock 28 Fig 3 4 4 Wiring for CNVss aaa 28 Fig 3 4 5 Wiring for the Ver of the One Time 29 F
50. 4 1 Transfer types of 50 Table 2 4 2 Packet types of 05 52 Table 2 4 3 Data structure of USB 53 Table 244 PID p 53 Table 2 4 5 Special signal of USB 54 CHAPTER 3 APPENDIX Table 3 1 1 Absolute maximum 5 2 2400000 2 Table 3 1 2 Recommended operating 3 Table 3 1 3 Electrical characteristics 1 88 4 Table 3 1 4 Electrical characteristics 2 4 4 8404 5 Table 3 1 5 A D Converter characteristics 1 5 Table 3 1 6 Timing requirements 6 Table 3 1 7 Switching characteristics U naa 6 Table 3 3 1 Programming adapters 2 23 Table 3 3 2 PROM programmer address setting 24 Table 3 5 1 CNTRo active edge switch bit function sssssssessseeeeennenneee 45 Rev 3 00 Oct 23 2006 page 9 of 9 RENESAS REJ09B0178 0300 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USE DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP DIFFERENCES AMONG 32 PIN 36 PIN AND 42 PIN DESCRIPT
51. Address 1F 16 b7 b5 b4 bl eps T RD WR RD WR Suspend request flag 0 No request Ena Clear Set 1 Suspend request ble Suspend request is set to 1 when system enters to state J for 3 ms or more Suspend request is cleared to 0 by writing dummy to this register USB reset request 0 No request Ena Set flag 1 Reset request ble Clear Initial value USB reset request is set to 1 when the SEO signal is input for 2 5 us or more USB reset request is cleared to 0 when the SEO signal is stopped Token PID 0 SETUP interrupt Ena Set determination flag 1 OUT interrupt ble Clear This flag is set to 1 during no SETUP transaction This flag is cleared to 0 when PID of SETUP is detected Token interrupt flag 0 No request Ena Set 1 OUT SETUP token request ble Clear This flag is set to 1 when OUT or SETUP interrupt occurs This flag is cleared to 0 after the end of transaction Fig 3 5 13 Structure of USB interrupt source discrimination register 2 USB dca control register USBICON Address 20 16 b6 b5 b4 b3 62 b bO ae rove ree ere RD WR Initial value Endpoint 1 enable 0 Endpoint 1 invalid Ena Set Use 1 Endpoint 1 valid ble Clear USB reset interrupt 0 USB reset invalid ET Set Use enable 1 USB reset valid Clear This flag is invalid in suspend mode USB reset is always said in suspend mode Resume interrupt 0 R
52. Clear Initial value Remote wake up 0 No request Set Use Clear request flag 1 Remote wake up request Remote wake up request output can be set by setting this flag to 1 This flag is cleaed to 0 automatically after 10 ms from remote wake up request Fig 3 5 21 Structure of USB control register Rev 3 00 Oct 23 2006 42 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Prescaler 12 Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 PRE12 Address 28 16 Prescaler X PREX Address 2C 16 Set a count value of each prescaler value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time ESSE When this register is read out the count value of the corres ponding prescaler is read out EX EN Fig 3 5 22 Structure of Prescaler 12 Prescaler Timer 1 b7 b6 b5 b4 b3 b2 b1 Timer 1 T1 Address 29 16 Set a count value of timer 1 value set in this register is written to both timer 1 and timer 1 latch at the same time When this register is read out the timer 175 count value is read Fig 3 5 23 Structure of Timer 1 Rev 3 00 Oct 23 2006 page 43 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Timer 2 b7 b6 65 64 63 b2 61 00 Timer 2 T2
53. Fig 3 5 6 Structure of UART status register Rev 3 00 Oct 23 2006 page 36 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Refer to Figure 2 4 6 Description of register structure for registers relevant to USB USB status register USBSTS Address 19 16 b7 b 64 b3 62 bi 6 b5 Initial value 0 Buteremoy loe empty flag 1 Buffer empty ble Clear This bit is set to 1 when data is transferred from buffer to shift register by hardware This bit is cleared to 0 by writing to buffer EOP detection flag 0 Not detected Ena Clear Set 1 Detect ble Setting condition of this flag to 1 is as follows Normal EOP detected by hardware False EOP flag FEOPE set Time is out with EOP not detected at data phase or handshake phase This bit is cleared to 0 by writing dummy to this register False EOP error flag 0 No error Ena Clear Set 1 False EOP error ble This bit is set to 1 when the phase is not completed normally This bit is cleared to 0 by writing dummy to this register CRC error flag 0 No error Ena Clear Set 1 CRC error ble This bit is set to 1 when the CRC error occurs at the same timing of EOP detection flag This bit is to 0 cleared by writing dummy to this register PID error flag 0 No error Ena Clear Set 1 PID error ble Setting condition of this flag to 1 is as follows PID of DATAO or DATA1 cannot be
54. Interrupt request register 1 IREQ1 003 16 Interrupt control register 1 Fig 2 3 1 Memory map of registers relevant to serial I O 2 3 2 Relevant registers Transmit Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit Receive buffer register TB RB Address 18 16 The transmission data is written to or the receive data is read out from this buffer register At writing A data is written to the transmit buffer register At reading The contents of the receive buffer register are read out Note The contents of transmit buffer register cannot be read out The data cannot be written to the receive buffer register Fig 2 3 2 Structure of Transmit Receive buffer register Rev 3 00 Oct 23 2006 page 29 of 78 5 5 09 0178 0300 APPLICATION 7534 Group 2 3 Serial I O UART status register b7 b6 b5 64 b3 b2 61 bO UART status register UARTSTS Address 19 16 NENNT s R m buffer empty flag Buffer full TBE Buffer empty Receive buffer full flag RBF Buffer empty Buffer full Transmit shift register shift Transmit shift in progress completion flag TSC Transmit shift completed Hm Overrun error 4 Parity error flag PE No error Parity error Framing error flag FE error Soe PET Summing error flag SE U EE i 7 Nothing is allocated for this bit S is a write disabled bit When th
55. J 34 bit times 22 7 us 136 cycle SETUP token interrupt occurs Read Data 0 Notes 1 In this case Data 2 bytes Cycle 6 MHz 2 Max 14 cycles are required until the interrupt occurs Fig 2 4 15 Data read timing of SETUP token SYNC PID CRC SYNC Data X Data Y 34 bit times 22 7 us 136 cycle OUT token interrupt occurs Read Data 0 Notes 1 In this case Data 2 bytes Cycle 6 2 2 Max 14 cycles are required until the interrupt occurs Fig 2 4 16 Data read timing of OUT token PID ADDR FOP SYNC PID IN token interrupt occurs Read Data 0 22 5 bit times 15 us 90 cycle Notes 1 In this case Data 1 byte Cycle 6 MHz 2 Max 14 cycles are required until the interrupt occurs Fig 2 4 17 Data read timing of IN token endpoint 0 and IN token endpoint 1 token Rev 3 00 Oct 23 2006 page 67 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 4 Processing to special signal In 7534 Group control the USB function to the signal shown in Table 2 4 5 by software At USB reset initialize the registers relevant to USB described in the above section 2 4 3 Also at Suspend execute the STP instruction after the interrupt is enabled Set an external interrupt which is the return condition from the stopped state before STP instruction The enable of resume is included in this condition The generati
56. O to 4 Address 00 16 0216 0416 0616 0816 Write n input mode Read Value of pins pe Note The following ports do not exist so that the corresponding bits are not used 42 pin version Ports P1 7 P42 P47 96 pin version Ports 15 17 P36 40 47 32 pin version Ports 5 17 P26 P27 P35 P37 40 47 Fig 3 5 1 Structure of Port Pi i 0 to 4 Port Pi direction register b7 b6 b5 64 b3 b2 bi bO Port Pi direction register i 0 to 4 Address 01 16 0316 0516 0716 0916 B Name Funcio atreser R W Port Pi direction register 0 Port Pioinput mode x 1 Port Pio output mode 0 Port Pi input mode x 1 Port Pi output mode 0 Port Pizinput mode x 1 Port Piz output mode 0 Port Pisinput mode x 1 Port Pis output mode 0 Port Pia input mode x 1 Port output mode 0 Port Pisinput mode x 1 Port Pis output mode 0 Port Pieinput mode x 1 Port Pie output mode 0 Port Piz input mode x 1 Port output mode Note The following ports do not exist so that the corresponding bits are not used 42 pin version Ports P17 P42 P47 96 pin version Ports 15 17 P36 40 47 32 pin version Ports P15 P17 P26 P27 35 37 40 47 Fig 3 5 2 Structure of Port Pi direction register i 0 to 4 Rev 3 00 Oct 23 2006 page 34 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registe
57. OC 1ST 7DATA 1SP sTALSBX X OX X X gt SP 1ST 8DATA 1PAR 1SP st KBX X X X X X OXSEXCPARY SP 1ST 7DATA 1PAR 1SP X X X Xws8XPARY SP 1ST 8DATA 2SP st X 0X X X 2 1ST 7DATA 2SP KBX X X 2 1ST 8DATA 1PAR 2SP SLALSBX 1ST 7DATA 1PAR 2SP st _ 2SP Serial 1 UART Clock LSB first ST Start bit Serial 02 synchronous 4 SP Stop bit Serial I O MSB first PAR Parity bit Fig 2 3 14 Serial I O transfer data format Rev 3 00 Oct 23 2006 page 37 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O 2 3 5 Serial I O application examples 1 Communication using clock synchronous serial I O transmit receive Outline 2 byte data is transmitted and received using the clock synchronous serial I O Port 0 is used for communication control and outputs the quasi Sroy signal The following explain an example using the serial 1 02 Figure 2 3 15 shows a connection diagram and Figure 2 3 16 shows a timing chart Transmission side Reception side P37 INTo 0 SDATA SDATA 7534 Group 7534 Group Fig 2 3 15 Connection diagram Specifications The Serial 1 02 clock synchronous serial I O is used Synchronous clock frequency 94 kH
58. P27 P30 0 3 to 0 3 P37 Xour USBVREFOUT P40 P41 Power dissipation Note 2 1000 Note 3 Operating temperature 20 to 85 Storage temperature 40 to 125 Notes 1 It is a rating only for the One Time PROM version Connect to Vss for mask ROM version 2 The rating value depends on packages 3 This is the value for the 42 pin version The value of the 36 pin version is 300 mW The value of the 32 pin version is 200 mW Rev 3 00 Oct 23 2006 page 2 of 70 7tENESAS 09 0178 0300 APPENDIX 7534 Group 3 1 Electrical characteristics 3 1 2 Recommended operating conditions Table 3 1 2 Recommended operating conditions 4 1 to 5 5 V Ta 20 to 85 unless otherwise noted Limits Typ Power source voltage 6 MHz 5 0 Power source voltage 0 Analog reference voltage input voltage 0 07 10 16 P20 P30 P37 P40 P41 H input voltage TTL input level selected P10 P12 P13 P36 P37 input voltage RESET XIN H input voltage D D L input voltage 0 07 10 16 P20 P30 P37 P40 P41 L input voltage TTL input level selected P10 P12 P13 P36 P37 L input voltage RESET CNVss L input voltage D D L input voltage XIN H total peak output current Note 1 00 07 10 16
59. REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O Table 2 3 1 shows a setting example of the baud rate generator BRG and transfer bit rate values Figure 2 3 24 shows the registers setting relevant to transmission side Figure 2 3 25 shows the registers setting relevant to reception side Table 2 3 1 Setting example of baud rate generator BRG and transfer bit rate values BRG set value BRG count source Transfer bit rate bps Note 2 Note 1 At 4 9152 MHz At 6 MHz 4 255 300 366 2109375 4 127 7Fis 600 732 421875 4 1200 1464 84375 4 2400 2929 6875 4 4800 5859 375 4 9600 11718 75 4 19200 23437 5 4 38400 46875 76800 93750 153600 187500 307200 375000 Notes 1 Select the BRG count source with bit 0 of the serial 1 01 control register address 1Ais 2 Equation of transfer bit rate f Xin Transfer bit rate bps BRG set value 1 X 16 X m m 1 in the case of bit 0 of the serial I O1 control register address 001A e 0 m 4 in the case of bit 0 of the serial 1 01 control register address 01 1 Rev 3 00 Oct 23 2006 page 44 of 78 REJ09B0178 0300 7RENESAS APPLICATION 7534 Group 2 3 Serial I O Transmission side UART status register address 19 16 b7 60 UARTSTS Transmit buffer empty
60. RESET pin Connecting capacitor In case where the RESET signal rise time is long connect a ceramic capacitor or others across the RESET pin and the Vss pin Use a 1000 pF or more capacitor for high frequency use When connecting the capacitor note the following Make the length of the wiring which is connected to a capacitor as short as possible Be sure to verify the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin it may cause a microcomputer failure Rev 3 00 Oct 23 2006 page 78 of 78 7RENESAS REJ09B0178 0300 3 APPENDIX 3 1 Electrical characteristics 3 2 Typical characteristics 3 3 Notes on use 3 4 Countermeasures against noise 3 5 List of registers 3 6 Package outline 3 7 List of instruction code 3 8 Machine instructions 3 9 SFR memory map 3 10 Pin configurations APPENDIX 7534 Group 3 1 Electrical characteristics 3 1 Electrical characteristics 3 1 1 Absolute maximum ratings Table 3 1 1 Absolute maximum ratings Parameter Conditions Ratings Power source voltage 0 3 to 7 0 Input voltage P0o P07 10 16 P20 P27 P30 0 3 to Vcc 0 3 P37 VREF P40 P41 All voltages are Input voltage RESET XIN based on 55 0 3 to Voc 0 3 Output transistors Input voltage CNVss Note 1 are cut off 0 3 to 13 Output voltage 0 07 10 16 P20
61. STALL IN token DATA0 1 OUT token ACK IN token STALL OUT STALL SPID0O OUT ACK APIDO IN STALL SPIDOI IN DATAO 1 DPIDO 1 1 SETUP no error 4 transaction Sequence bit toggle es dee EE ee maan ji SQTGL OUT no error 2 Control Write Setup Stage Data Stage Status Stage Endpoint 0 valid Endpoint 0 invalid Endpoint 0 enable flag r EP0E s Endpoint 0 PID selection flag OUT token ACK IN token STALL OUT token STALL IN token DATAO 1 OUT STALL SPIDOO OUT ACK APIDO IN STALL SPIDOI IN DATAO 1 DPIDO 1 OUT no error H 1 SETUP no error 4 transaction 1 ACK receive Sequence bit toggle flag SQTGL n L je Notes 1 Only token and DATAO 1 of PID are shown in this figure 2 In this example data stage is 4 transaction Fig 2 4 11 Control method of control sequence Rev 3 00 Oct 23 2006 page 62 of 78 134 NE SAS REJO9B01 78 0300 APPLICATION 7534 Group 2 4 USB 2 Example of processing each transaction In 7534 Group the control and the determination of the packet are executed by software First the content of the received token is determined transmit and receive data according to it are executed the completion of the transaction is shown by the handshake Note that the contents of the control and the determination are different even of the software so that processing is
62. Structure of Interrupt request register 1 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 ICON1 Address 16 B ___ JwrseR W UART receive USBIN token 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled UART transmit USBSETUP 0 Interrupt disabled OUT token Reset Suspend 1 Interrupt enabled Resume INT interrupt enable INTo interrupt enable bit Interrupt disabled Note 2 Interrupt enabled 3 Timer X or key on wake up Interrupt disabled interrupt enable bit Interrupt enabled 4 Timer 1 interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 Timer 2 or serial 2 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled CNTRo or AD converter 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 Nothing is allocated for this bit Do not write 1 to this bit 9 When this bit is read out the value is 0 Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 2 2 10 Structure of Interrupt control register 1 Rev 3 00 Oct 23 2006 page 15 of 78 5 5 09 0178 0300 APPLICATION 7534 Group 2 2 Timer 2 2 3 Timer application examples 1 Basic functions and uses Function
63. The bit managing instructions are read modify write form instructions for reading and writing data by a byte unit Accordingly when these instructions are executed on a bit of the port latch of an port the following is executed to all bits of the port latch As for a bit which is set for an input port The pin state is read in the CPU and is written to this bit after bit managing As for a bit which is set for an output port The bit value of the port latch is read in the CPU and is written to this bit after bit managing Note the following Even when a port which is set as an output port is changed for an input port its port latch holds the output data As for a bit of the port latch which is set for an input port its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents bit managing instructions SEB and CLB instructions Rev 3 00 Oct 23 2006 page 8 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 1 port 2 1 6 Termination of unused pins 1 Terminate unused pins Output ports Open Input ports Connect each pin to Vcc or Vss through each resistor of 1 to 10 Ports that permit the selecting of a built in pull up resistor can also use this resistor As for pins whose potential affects to operation modes such as pins CNVss INT or others select the Vcc pin or the Vss pin according to their operati
64. Timer X over flows comes to the terminal count regis ters or internal memory contents except Timer X will not change during this mode Of course needs VDD me 1 The number of cycles is increased by when T is 1 2 The number of cycles n is increased by 2 when T is 1 3 The number of cycles is increased by 1 when T is 1 4 The number of cycles is increased by 2 when branching has occurred 5 and Z flags are invalid decimal operation mode Rev 3 00 Oct 23 2006 64 of 70 1320 NESAS REJO9B01 78 0300 APPENDIX 7534 Group 3 8 Machine instructions Addressing mode Processor status register Rev 3 00 Oct 23 2006 65 of 70 RENESAS REJ09B0178 0300 7534 Group APPENDIX 3 8 Machine instructions Symbol Contents Contents IMP IMM A BIT A BIT A R ZP BIT ZP BIT ZP R ZP X ZP Y ABS ABS X ABS Y IND ZP IND IND X IND Y REL sP Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit addressing mode Zero page bit relative addressing mode Zero page X addressin
65. USB reset invalid 1 USB reset valid Resume interrupt enable 0 Resume invalid 1 Resume valid Token interrupt enable 0 Token invalid 1 Token valid USB enable flag 0 USB invalid 1 USB valid CPU read Enabled CPU write Clear Hardware read Not used Hardware write Set CPU read Enabled CPU write Disabled Hardware read Not used Hardware write Set Clear CPU read Enabled CPU write Disabled Hardware read Not used Hardware write Set Clear CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Not used Rev 3 00 Oct23 2006 page 29 of 55 REJ09BO1 78 0300 5 5 7534 HARDWARE FUNCTIONAL DESCRIPTION USB transmit data byte number set register 0 EPOBYTE address 002116 CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Not used Not used return 0 when read USB transmit data byte number set register 1 EP1BYTE address 002216 CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Not used Not used return 0 when read USB PID control register 0 EPOPID address 002316 Not used return 1 when read Endpoint 0 enable flag 0 Endpoint 0 invalid 1 Endpoint 0 valid Endpoint 0 PID selection flag 1xxx
66. X it can be set to 0 or 1 Fig 2 4 9 Register structures relevant to USB 3 Rev 3 00 Oct 23 2006 page 60 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB USB address register USBA Address 25 16 7 b6 65 b4 b3 b2 bi b CPU WR RD WR Initial value 0 0 0 0 0 0 0 RD ar USB sequence bit initialization register INISQ1 Address 26 16 b7 b6 b5 b4 b3 62 bi 00 x x x x x x x x As sequence bit of endpoint 1 is initialized Sequence is initialized by writing dummy Initial value USB control register USBCON Address 27 16 67 b6 b5 64 b3 62 bi 00 T T T T T OPU OPU w HW 0 RD WR RD WR USBVREFOUT output 0 Output off Set Use valid flag 1 Output on Clear Remote wake up 0 No request Set Use Clear request flag 1 Remote wake up request Remote wake up request output can be set by setting this flag to 1 This flag is cleaed to 0 automatically after 10 ms from remote wake up request Serial 1 01 control register SIO1CON Address 1 16 67 b6 b5 64 b3 62 bi MEM J S WR RD WR 0 Serial 1 01 mode 00 I O port Use selection bit 01 Not available Clear Serial 1 01 mode 10 UART mode Set Use selection bit 11 USB mode Clear Note Only bits 6 and 7 of SIO1CON are described in this figure because only these bits are used for USB Initial value Initial value Fig 2 4 10 Register structures relevant to USB
67. a duty cycle of 50 96 Rev 3 00 Oct 23 2006 page 3 of 70 5 5 REJ09B0178 0300 7534 APPENDIX 3 1 Electrical characteristics 3 1 3 Electrical characteristics Table 3 1 3 Electrical characteristics 1 Vcc 4 1 to 5 5 V Vss 0 V 20 to 85 C unless otherwise noted Parameter Test conditions H output voltage 00 07 10 16 20 27 P30 P37 P40 P41 Note 1 loH 5 mA Vcc 4 1 to 5 5 V 1 0 mA 4 1 to 5 5 H output voltage Vcc 4 4 to 5 25 V Pull down through 15kQ 5 for D D Pull up through 1 5kQ 5 by USBVREFOUT for D Ta 0 to 70 C L output voltage P00 P07 10 16 P20 P37 P40 P41 loL 2 5 mA 4 1 to 5 5 V loL 1 5 mA 4 1 to 5 5 V L output voltage Vcc 4 4 to 5 25 V Pull down through 15kQ 5 for D D Pull up through 1 5kQ 5 by USBVREFOUT for D Ta 0 to 70 C L output voltage 6 loL 15 mA 4 1 to 5 5 loL 1 5 mA 4 1 to 5 5 V Hysteresis D D Hysteresis CNTRo INTo INT1 Note 2 7 3 Hysteresis RxD SDATA Note 2 Hysteresis RESET H input current P00 P07 10 16 20 27 P30 P37 P40 P41 Vcc Pin floating Pull up transistors off H input current RESET VI Voc
68. addresses 0C08016 to OFFFD16 in the PROM programmer Rev 3 00 Oct 23 2006 page 23 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 3 Notes on use 3 3 10 Termination of unused pins 1 Terminate unused pins Output ports Open Input ports Connect each pin to Vcc or Vss through each resistor of 1 to 10 Ports that permit the selecting of a built in pull up resistor can also use this resistor As for pins whose potential affects to operation modes such as pins CNVss INT or others select the Vcc pin or the Vss pin according to their operation mode I O ports Set the I O ports for the input mode and connect them to Vcc or Vss through each resistor of 1 to 10 Ports that permit the selecting of a built in pull up resistor can also use this resistor Set the O ports for the output mode and open them at L or H When opening them in the output mode the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset Thus the potential at these pins is undefined and the power source current may increase in the input mode With regard to an effects on the system thoroughly perform system evaluation on the user side Since the direction register setup may be changed because of a program runaway or noise set direction registers by program periodically to increase the reliability of program 2 Termination remarks
69. ae gt Store Return Address on Stack 5 lt S lt 5 lt S lt O Store Return Address on Stack Store Contents of Processor 5 lt Status Register on Stack 5 1 lt 86 1 5 lt 5 1 2 Interrupt Service Routine Flag 0 to 1 E RT xecute RTS Execute RTI Fetch the Jump Vector Restore Ret S 5 1 A ddiess 5 Ea Ta Restore Contents of PS lt MS Processor Status Register n lt 5 1 PC lt S PCMS Restore Return Address s lt 5 1 PCH lt M 5 Note The condition to enable the interrupt gt Interrupt enable bit is 1 Interrupt disable flag is O Fig 9 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP Rev 3 00 Oct 23 2006 page 11 of 55 5 5 09 0178 0300 7534 Group Processor status register PS The processor status register is an 8 bit register consisting of flags which indicate the status of the processor after an arithmetic opera tion Branch operations can be performed by testing the Carry C flag Zero Z flag Overflow V flag or the Negative N flag In decimal mod
70. and periodically sets the interrupt request bit Timer X Timer X can be selected in one of 4 operating modes by setting the timer X mode register Timer Mode The timer counts the signal selected by the timer X count source selection bit Pulse Output Mode The timer counts the signal selected by the timer X count source selection bit and outputs a signal whose polarity is inverted each time the timer value reaches 0 from the CNTRo pin When the CNTRo active edge switch bit is 0 the output of the CNTRo pin is started with an output At 1 this output is started with an L output When using a timer in this mode set the port P14 direction register to output mode Event Counter Mode The operation in the event counter mode is the same as that in the timer mode except that the timer counts the input signal from the CNTRo pin When the CNTRo active edge switch bit is 0 the timer counts the rising edge of the CNTRo pin When this bit is 1 the timer counts the falling edge of the CNTRo pin Pulse Width Measurement Mode When the CNTRo active edge switch bit is 0 the timer counts the signal selected by the timer X count source selection bit while the CNTRo pin is When this bit is 1 the timer counts the signal while the CNTRo pin is L In any mode the timer count can be stopped by setting the timer X count stop bit to 1 Each time the timer overflows the interrupt request b
71. and stores the contents of the memory location designated by S in PCL S is again incremented by one and stores the contents of memory location designated by S in PCH 56 541 PCL lt 5 56 541 PCH lt 5 1 This instruction increments 5 by and stores the contents of the memory location designated by S in PCL S is again incremented by one and the contents of the memory location is stored in PCH is incremented by 1 Rev 3 00 Oct 23 2006 page 62 of 70 REJ09B0178 0300 7RENESAS APPENDIX 7534 Group 3 8 Machine instructions Addressing mode Processor status register ABS ABS X ABS Y IND ZP IND IND X IND Y REL 0 JOP n OP n JOP 4 3 3 ue saved in stack Rev 3 00 Oct 23 2006 63 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 8 Machine instructions Addressing mode Symbol Function Details A A ZP BIT ZP n JOP n OP n SBC When T 0 When T 0 this instruction subtracts the E5 2 Note 1 lt value of and the complement of from Note 5 and stores the results in A and C When T 1 When T 1 the instruction subtracts the con
72. arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employe
73. by the interrupt and the setting a related register when using the interrupt of the IN token in Figure 2 4 14 In the OUT token interrupt read data of OUT token and SETUP token at the timing shown in Figures 2 4 15 and 2 4 16 Also in the IN token interrupt write data to IN token endpoint 0 and IN token endpoint 1 at the timing shown in Figure 2 4 17 Rev 3 00 Oct 23 2006 page 64 of 78 7tENESAS 09 0178 0300 7534 Flow chart USBA Set USB communication SIO1CON USBCON USBICON Set OUT token enabled EPOPID Program description APPLICATION 2 4 USB Not used here Set it to 0 or 1 arbitrary 0000000 gt Initial USB address 0 11XXXXXX gt Set hardware I O port to USB mode 1 2 Use USBVrerour 1XXXXXXX 2 Set internal state to USB enabled XXXXAXXX 2 Set endpoint 0 to be valid USBICON IREQ1 ICON1 Set OUT token interrupt enabled X1XXXXXX 2 Set token interrupt to be valid XXXXXX0X 2 Initialize OUT token interrupt request 1 2 Set OUT token interrupt enable OUT token interrupt Reset Supend Resume processing USBIR2 XXXX XXX 2 Interrupt by reset if 2 1 USBIR2 XXxXX XX 2 Interrupt by suspend if 1 USBICON XX9 XXXXX 2 Interrupt by resume if 2 1 Note Set RSME to 1 only in suspend processing Interrupt source Reset Supend Resume processing No Reset Supend Resume proc
74. can be initialized by clearing this flag to 0 The initial values of registers are as follows USB status register address 19 16 0116 USB data toggle synchronization register address 1D 16 7F 16 USB interrupt source discrimination register 1 address 1E 16 7 16 Bits 7 6 and 2 of USB interrupt source discrimination register 2 address 1F 16 00xxx0xx2 Fig 2 4 8 Register structures relevant to USB 2 Rev 3 00 Oct 23 2006 page 59 of 78 5 5 09 0178 0300 APPLICATION 7534 Group 2 4 USB USB transmit data byte number set register 0 EPOBYTE Address 21 16 b7 06 b5 b4 b3 b2 bi 0 sew CPU CPU HW HW Initial value 0 0 0 RB transmitting with endpoint 0 ble Clear USB transmit data byte number set register 1 EP1BYTE Address 22 16 b7 06 b5 b4 b3 b2 bi 00 o ___ CPU HW HW Initial value 0 RD WR Set the number of data byte for Ena Set Use transmitting with endpoint 1 ble Clea USB PID control register 0 EPOPID Address 23 16 67 b6 b5 04 63 b2 60 CPU CPU H W HW RD WR RD WR Endpoint 0 enable 0 Endpoint 0 invalid Ena Set Use flag 1 Endpoint 0 valid ble Clea Unexpected IN or OUT transaction can be ignored by clearing this flag to 0 SETUP transaction cannot be ignored it is always valid Endpoint 0 PID selectio
75. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Elect
76. changed Reason The bit managing instructions are read modify write form instructions for reading and writing data by a byte unit Accordingly when these instructions are executed on a bit of the port latch of an port the following is executed to all bits of the port latch As for a bit which is set for an input port The pin state is read in the CPU and is written to this bit after bit managing As for a bit which is set for an output port The bit value of the port latch is read in the CPU and is written to this bit after bit managing Rev 3 00 Oct 23 2006 page 20 of 70 7tENESAS 09 0178 0300 APPENDIX 7534 Group 3 3 Notes on use Note the following Even when port which is set as an output port is changed for an input port its port latch holds the output data As for a bit of the port latch which is set for an input port its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents bit managing instructions SEB and CLB instructions 3 3 7 Notes on programming 1 Processor status register Initializing of processor status register Flags which affect program execution must be initialized after a reset In particular it is essential to initialize the T and D flags because they have an important effect on calculations Reason After a reset the contents of the processor status register PS are undef
77. chip An external feed back resistor may be needed depending on conditions Oscillation control Stop mode When the STP instruction is executed the internal clock stops at an H level and the oscillator stops At this time timer 1 is set to 0116 and prescaler 12 is set to FFie when the oscillation stabilization time set bit after release of the STP instruction is 0 On the other hand timer 1 and prescaler 12 are not set when the above bit is 1 Accordingly set the wait time fit for the oscillation stabilization time of the oscillator to be used f XiN 16 is forcibly connected to the input of prescaler 12 When an external interrupt is accepted oscillation is restarted but the internal clock remains at H until timer 1 underflows As soon as timer 1 underflows the internal clock is supplied This is because when a ceramic oscillator is used some time is required until a start of oscillation In case oscillation is restarted by reset no wait time is generated So apply an L level to the RESET pin while oscillation becomes stable Wait mode If the WIT instruction is executed the internal clock stops at an H level but the oscillator does not stop The internal clock restarts if a reset occurs or when an interrupt is received Since the oscillator does not stop normal operation can be started immediately after the clock is restarted To ensure that interrupts will be received to
78. conversion register low order 67 b6 25 64 b3 b2 61 A D conversion register low order ADL Address 3516 i W M The read only register in which the A D conversion s results EAE Eag lt 8 bit read gt 2 b7 lt 10 bit read gt T EMG Er pepe pape aro EET id gK l Fig 2 5 4 Structure of A D conversion register low order Rev 3 00 23 2006 72 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 5 A D converter Interrupt edge selection register b7 b6 b5 64 b3 b2 61 bO Interrupt edge selection register INTEDGE Address 16 B ___ Funcio INTo interrupt edge 0 Falling edge active selection bit Note 1 1 Rising edge active INT interrupt edge 0 Falling edge active selection bit Note 2 1 Rising edge active When these bits are read out the values are 0 ES 4 Serial 1 01 or INT interrupt 0 Serial 1 selection bit 1 INT 5 Timer X or key on wake up 0 Timer X interrupt selection bit 1 Key on wake up Timer 2 or serial 2 interrupt 0 Timer 2 selection bit 1 Serial 1 02 7 or AD converter 0 CNTRo interrupt selection bit 1 AD converter Notes 1 32 pin version Not used This is a write disabled bit When this bit is read out the value is
79. counter mode Pulse width measurement mode The function depends on the operating mode Refer to Table 2 2 1 Fig 2 2 6 Structure of Timer mode register Table 2 2 1 CNTRo active edge switch bit function Timer X operation modes CNTRo active edge switch bit bit 2 of address 2B s contents Timer mode 0 CNTRo interrupt request occurrence Falling edge No influence to timer count 1 CNTRo interrupt request occurrence Rising edge No influence to timer count 0 Pulse output start Beginning at H level CNTRo interrupt request occurrence Falling edge Pulse output start Beginning at L level CNTRo interrupt request occurrence Rising edge O Timer X Rising edge count CNTRo interrupt request occurrence Falling edge 1 Timer X Falling edge count CNTRo interrupt request occurrence Rising edge O Timer X level width measurement CNTRo interrupt request occurrence Falling edge 1 Timer X L level width measurement CNTRo interrupt request occurrence Rising edge Pulse output mode 1 Event counter mode Pulse width measurement mode Rev 3 00 Oct 23 2006 page 13 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer Timer count source set register b7 b6 65 64 b3 62 bi bO Timer count source set register 55 Address 2E 16 ____ Function At reset R W rum X count s
80. data at reception to the serial 1 2 register by program 7 of the serial 1 02 control register is set to 1 a half cycle of the shift clock earlier than completion of shift operation Accordingly when using this bit to confirm shift completion a half cycle or more of the shift clock must pass after confirming that this bit is set to 1 before performing read write to the serial 1 2 register Rev 3 00 Oct 23 2006 page 49 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 2 4 USB This paragraph explains operational outline the registers relevant to the USB the registers setting method the application example for communication and notes on use 2 4 1 Outline of USB 7534 Group has USB functions in compliance with the Low Speed USB2 0 specification which are connection standard with PC peripherals In this section the outline of USB communication function and the USB function of 7534 Group are described 1 Transfer type In present PC 2 or more standards used for the connection with peripherals exist RS 232C and Centronics etc USB tries to unite all those communication standards The standard of USB has the host side PC Hub which controls connected peripherals and the connected peripherals side device The following 3 types of communication standards exist depending on the data amount treated on the peripherals side Hi Speed function H S USB operation at 480Mbps Full S
81. detected at data phase after OUT or SETUP token ACK PID cannot be received at handshake phase during IN transaction This bit is cleared to 0 by writing dummy to this register Bit stuffing error flag 0 No error Ena Clear Set 1 Bit stuffing error ble This bit is set to 1 when bit stuffing error occurs at data phase or handshake phase This bit is cleared to 0 by writing dummy to this register ng error flag 0 No error Ena Clear Set 1 Summing error ble when any error of FEOPE CRCE PIDE or BSTFE occurs 0 by writing dummy to this register Receive buffer full 0 Buffer empty Ena Set flag 1 Buffer full ble Clear This bit is set to 1 when data is transferred from shift register to buffer by hardware This bit is cleared to 0 by reading from buffer Fig 3 5 7 Structure of USB status register Rev 3 00 Oct 23 2006 page 37 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Serial 1 01 control register b7 b6 b5 b4 b3 b2 bi Serial 1 01 control register SIO1CON Address 1A 16 _____ Function BRG count source f XIN 9100 selection bit CSS f XIN 4 Nothing is allocated for this bit is a write disabled bit 1 When this bit is read out the value is 1 Continuous transmit valid bit 0 Continuous transmit invalid 1 Continuous transmit valid 3 Transmit interrupt Inter
82. different depending on the content of the token Figure 2 4 12 shows timing chart of the transaction according to each token 1 SETUP token transaction Token Handshake SETUP PID detected OUT token interrupt i i 1 Interrupt processing 1 detected detected detection flag 1 Data Handshake EOP h 1 Token PID determination flag OPID Token interrupt flag RxPID Data received read 2 bytes Receive buffer full flag RxRDY False EOP error 1 PID error occurs 1 False EOP error occurs occurs FEOPE 1 PIDE 1 FEOPE ie news CRC error occur CRCE Summing error flag SUME CRC error occurs CRCE 2 OUT token transaction Token Handshake OUT PID detected OUT token interrupt 1 1 1 Interrupt processing T detected 1 EOP detected EOP detected Token Dat hak EOP detection flag Data Handshake EOP Token PID determination flag OPID Token interrupt flag RxPID Data received read 2 bytes Receive buffer full flag RxRDY PID error occurs 1 False EOP error occurs CRC error occurs PIDE 22 1 CRCE Summing error flag L SUME i CRC error occurs CRCE 3 IN token transaction Token Handshake IN token interrupt Interrupt processing detected EOP detected EOP detected 1 EOP detection flag Token Data Handshake EOP Endpoint determin
83. do not connect multiple ports in a lump to Vcc or Vss through a resistor Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between ports At the termination of unused pins perform wiring at the shortest possible distance 20 mm or less from microcomputer pins Rev 3 00 Oct 23 2006 page 9 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer 2 2 Timer This paragraph explains the registers setting method and the notes relevant to the timers 2 2 1 Memory map 002 16 Timer count source set register 55 003A16 Interrupt edge selection register INTEDGE 003C16 Interrupt request register 1 IREQ1 iy 003E16 Interrupt control register 1 ICON1 Fig 2 2 1 Memory map of registers relevant to timers 2 2 2 Relevant registers Prescaler 12 Prescaler X b7 b6 b5 64 63 b2 61 Prescaler 12 PRE12 Address 28 16 Prescaler X PREX Address 2C 16 Set a count value of each prescaler value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time When this register is read out the count value of the corres ponding prescaler is read out EXE ER E ELS Pele Fig 2 2 2 Structure of Prescaler 12 Prescaler X Rev 3 00 Oct 23 2006 page 10 of 78 1320 NE ESAS REJO
84. failure or a program runaway Fig 3 4 9 Wiring of signal lines where potential levels change frequently 3 Oscillator protection using Vss pattern As for a two sided printed circuit board print a VSs pattern on the underside soldering side of the position on the component side where an oscillator is mounted Connect the VSS pattern to the microcomputer Vss pin with the shortest possible wiring Besides separate this Vss pattern from other Vss patterns An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example GHXIN OBSS x EL XOUT a Vss Separate the Vss line for oscillation from other Vss lines Fig 3 4 10 Vss pattern on the underside of an oscillator Rev 3 00 Oct 23 2006 page 31 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 4 Countermeasures against noise 3 4 5 Setup for I O ports Setup ports using hardware and software as follows lt Hardware gt Connect a resistor of 100 or more to an I O port in series Software As for an input port read data several times by a program for checking whether input levels are equal or not As for an output port since the output data may reverse because of noise rewrite data to its port latch at fixed periods Rewrite data to direction registers and pull up control registers at fixed periods Note When a direction register is set for input port again at fixed periods a several
85. flag Confirm that the data has been transferred from the transmit buffer register to the transmit shift register When this flag is 1 it is possible to write the next transmission data into the transmit buffer register Transmit shift register shift completion flag Confirm transmission completion of one byte unit using this flag 1 Shift of transmission completed Serial 1 control register addreess 1A 16 b7 SIO1CON 0 11 BRG count source 4 Continuous transmit invalid Transmit enabled gt Receive disabled gt UART mode UART control register address 1B 16 b7 UARTCON ofa ojo Character length 8 bits Parity checking disabled Stop bit length 2 stop bits TxD CMOS output Baud rate generator address 1C 16 b7 t Transfer bit rate X 16 X m m 1 in the case of bit 0 of SIO1CON address 001A 16 0 4 in the case of bit 0 of SIO1CON address 001A 16 1 Fig 2 3 24 Registers setting relevant to transmission side Rev 3 00 Oct 23 2006 page 45 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O Reception side UART status register address 19 16 b7 50 UARTSTS Receive buffer full flag Confirm reception completion of one byte unit using this flag 1 At completing reception 0 At readting out Receive buffer register Overrun error flag 1 When data is ready
86. frequency during A D conversion The comparator consists of a capacity coupling and a charge of the capacity will be lost if the clock frequency is too low Thus make sure the following during an A D conversion e is 500 kHz or more Do not execute the STP instruction 3 Method to stabilize A D Converter Method to stabilize A D Converter is described below a A D conversion accuracy could be affected for Bus Powered USB devices while the communicating Figure 2 5 12 shows the method to stabilize A D conversion accuracy inserting a capacitor between Vref and Vss 1 Power supplied by USB Vcc BUS ANo to AN7 USBVREFOUT 0 01 to 1 uF 7534 Group 0 1 to 1 uF O Recommends for A D accuracy Fig 2 5 12 Method to stabilize A D conversion accuracy b It is recommended for A D accuracy to avoid converting while USB communication and use average value of several converted values Rev 3 00 Oct 23 2006 page 77 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 6 Reset 2 6 Reset 2 6 1 Connection example of reset IC Figure 2 6 1 shows the system example to switch to the RAM back up mode when detecting the falling of system power source by the INT interrupt System power source 5V Vcc1 RESET RESET E Vcc2 INT Vss 7534 Group V GND 6 od m i n uw M62009L M62009P M62009FP Fig 2 6 1 Example of poweron reset circuit 2 6 2 Notes on
87. into Receive shift register while Receive buffer register contains the data gt Parity error flag 1 When a parity error occurs the parity checking enabled gt Framing error flag 1 When stop bits cannot be detected at the specified timing gt Summing error flag 1 When any one of overrun parity and framing errors occurs 1 01 control addreess 1A 16 SIO1CON BRG count source 4 Continuous transmit invalid Transmit disabled gt Receive enabled gt UART mode UART control register address 1B 16 7 50 UARTCON Character length 8 bits Parity checking disabled Stop bit length 2 stop bits Baud rate generator address 1C 16 b7 Transfer bit rate X 16 m 1 in the case of bit 0 of SIO1CON address 001A 16 m 4 in the case of bit 0 of SIO1CON address 001A 16 0 1 Fig 2 3 25 Registers setting relevant to reception side Rev 3 00 Oct 23 2006 page 46 of 78 134 NE ESAS REJO9B01 78 0300 APPLICATION 7534 Group 2 3 Serial I O Figure 2 3 26 shows a control procedure of transmission side and Figure 2 3 27 shows a control procedure of reception side AUI s X This bit is not used here Set it to 0 or 1 arbitrary Initialization SIO1CON address 1A16 100100012 Serial l O1 setting UARTCON address 1 16 lt 000010002 address 1C16 lt 8 1
88. nanosecond short pulse may be output from this port If this is undesirable connect a capacitor to this port to remove the noise pulse Port latch gt port pins Fig 3 4 11 Setup for I O ports Rev 3 00 Oct 23 2006 page 32 of 70 7tENESAS 09 0178 0300 APPENDIX 7534 Group 3 4 Countermeasures against noise 3 4 6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation This is equal to or more effective than program runaway detection by a hardware watchdog timer The following shows an example of a watchdog timer provided by software In the following example to reset a microcomputer to normal operation the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine This example assumes that interrupt processing is repeated multiple times in a single main routine processing lt The main routine gt Assigns a single byte of RAM to a software watchdog timer SWDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following condition N 1 gt Counts of interrupt processing executed in each main routine As the main routine execution cycle may change because of an interrupt processing or others the in
89. oscillator clock Switch the clock division ratio Switch to other mode except an on chip oscillator selection bits bits 6 and 7 of CPUM Select one of 1 1 1 2 and 1 8 Y Main routine Note After releasing reset the operation starts by starting an on chip oscillator automatically Do not use an on chip oscillator at ordinary operation Fig 11 Switching method of CPU mode register Rev 3 00 Oct 23 2006 page 13 of 55 3 NE SAS 09 0178 0300 7534 HARDWARE FUNCTIONAL DESCRIPTION Memory Special function register SFR area The SFR area in the zero page contains control registers such as I O ports and timers RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs Interrupt vector area The interrupt vector area contains reset and interrupt vectors RAM area RAM capacity address bytes XXXX16 013F 16 01BF16 ROM area ROM capacity address address bytes YYYY16 727716 8192 00016 08016 Fig 12 Memory diagram Zero page The 256 bytes from addresses 000016 to OOFF 16 are called the zero page area The internal RAM and the special function registers SFR are allocated to this area The zero page addressing mode can be used to specify memory and register a
90. release of the STP instruction 0 Set 0116 in timer1 and FF16 in prescaler 12 automatically 1 Not set automatically Reserved bits return 0 when read Do not write 1 to these bits Not used return 0 when read Fig 47 Structure of MISRG Rev 3 00 Oct 23 2006 page 40 of 55 REJ09B0178 0300 RENESAS HARDWARE 7534 Group FUNCTIONAL DESCRIPTION Clock division ratio selection bit Middle speed High speed double speed mode Prescaler 12 On chip oscillator mode Clock division ratio selection bit Middle speed mode Timing Double speed mode On chip oscillator On chip oscillator mode Note 1 High speed mode Internal clock Qs 5 STP instruction WIT R STP instruction instruction Reset Note 1 On chip oscillator is used only for starting gt 2 Although feed back resistor exists on chip external feed back Interrupt disable flag 1 resistor may be needed depending on conditions Interrupt request Fig 48 Block diagram of system clock generating circuit for ceramic resonator Rev 3 00 23 2006 41 of 55 5 5 REJ09B0178 0300 7534 Group HARDWARE NOTES ON PROGRAMMING NOTES ON USE NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register PS after reset are undefined except for the interrupt disable flag which is 1 Aft
91. request Ena Clear Set 1 Suspend request ble Suspend request is set to 1 when system enters to state J for 3 ms or more Suspend request is cleared to 0 by writing dummy to this register USB reset request 0 No request Ena Set flag 1 Reset request ble Clear USB reset request is set to 1 when the SEO signal is input for 2 5 us or more USB reset request is cleared to 0 when the SEO signal is stopped Token PID 0 SETUP interrupt Ena Set determination flag 1 OUT interrupt ble Clear This flag is set to 1 during no SETUP transaction This flag is cleared to 0 when PID of SETUP is detected Token interrupt flag 0 No interrup Ena Set 1 OUT SETUP token interrupt ble Clear This flag is set to 1 when OUT or SETUP interrupt occurs This flag is cleared to 0 after the end of transaction USB a control 2 USBICON Address 20 16 b3 b2 bl poser ero RD WR RD WR Initial value Endpoint 1 enable 0 Endpoint 1 invalid Ena Set Use 1 Endpoint 1 valid ble Clear USB reset interrupt 0 USB reset invalid Ena Set Use enable 1 USB reset valid ble Clear This flag is invalid in suspend mode USB reset is always valid in suspend mode Resume interrupt 0 Resumue invalid Ena Set Use enable 1 Resume valid ble Clear Token interrupt 0 Token invalid Ena Set Use enable 1 Token valid ble Clear USB enable flag 0 USB invalid Ena Set Use 1 USB valid ble Clear The internal state
92. serial l O1 related registers 3 sse 30 Fig 32 Structure of serial l O1 related registers 4 sse 31 Fig 33 Structure of serial l O1 related registers 5 32 Fig 34 Structure of serial 1 02 control 34 Fig 35 Block diagram of serial 2 34 Fig 36 Serial 1 02 timing LSB first 35 Fig 37 Structure of A D control register 36 Fig 38 Structure of A D conversion register 36 Fig 39 Block diagram of A D converter 36 Fig 40 Block diagram of watchdog 1 37 Fig 41 Structure of watchdog timer control register 37 Fig 42 Example of reset 2 nennen 38 Fig 43 Timing diagram at reset 38 Fig 44 Internal status of microcomputer at reset 39 Fig 45 External circuit of ceramic resonator 40 Fig 46 External clock input 40 Fig 47 Structure of MISRQ 40 Rev 3 00 23 2006 page 4 9 RENESAS REJ09B0178 0300 7534 Group Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig List of figures 48 Block diagram of system clock generating circ
93. signal line and a resistor and a capacitor 3 4 4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals 1 Keeping oscillator away from large current signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a current larger than the tolerance of current value flows Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance ane Mutual Large g XIN current Fig 3 4 8 Wiring for a large current signal line Rev 3 00 Oct 23 2006 page 30 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 4 Countermeasures against noise 2 Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise Reason Signal lines where potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer
94. source Token USBIR2 Interrupt by the source except token occurs if gt Token processing SETUP USBIR2 X XXXXXX2 Interrupt by the source SETUP token occurs if OUT Interrupt by the source OUT token occurs if 1 To SETUP token processing To OUT token processing Fig 2 4 19 Example for determination of resume interrupt 2 Clear of suspend request flag When the request of the suspend interrupt occurs the suspend request flag is set to 1 After the suspend state is fixed the state of this flag is retained during fixed time 13 us The purpose of this is to retain the internal state until the count source to measure the time 3 ms until suspend is fixed is updated Accordingly the state might not change even if this flag is cleared to 0 immediately after the suspend request flag is 1 is determined Clear this flag to O after the wait of 13 us or 79 machine cycle f XIN 6 MHz time after this flag is 1 3 Determination of SEO signal In 7534 Group USB reset and EOP can be distinguished according to the width of the SEO signal However there is the time zone which corresponds any on the dividing line of the time of the width of the signal Moreover the control in a present state is required because there is a difference in processing by the state of the device Accordingly select the processing method in software by the state of the device Figure 2 4
95. the power supply is turned off reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation Rev 3 00 Oct 23 2006 page 25 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 3 Notes on use 3 3 15 USB communication In applications requiring high reliability we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly for example due to external causes such as noise When USB suspend mode with TTL level on P10 P12 P13 input level selection bit bit 3 of address 1716 set to 1 suspend current as Icc might be greater than 300 uA as a spec Countermeasure There are two countermeasures by software to avoid it as follows 1 Change from TTL input level to CMOS input level for P10 P12 P13 port input 2 Change from TTL input level to CMOS input level before STP instruction in suspend routine then after RESUME or Remote wake up interrupt return to TTL input level from CMOS input level That is shown in Figure 3 3 12 SUSPEND Routine Configuration to CMOS input level for P1o P12 P13 input level 44 xxxxx0xxe Configuration to CMOS input level for P10 P12 P13 input level RESUME Routine Configuration to TTL input level for P10 P12 P13 inpu
96. the BRK instruction The BRK flag in the processor status register is always 0 When the BRK instruction is used to generate an interrupt the processor status register is pushed onto the stack with the break flag set to 1 The saved processor status is the only place where the break flag is ever set 6 Index X mode flag T When the flag is 0 arithmetic operations are performed between accumulator and memory e g the results of an operation between two memory locations is stored in the accumulator When the T flag is 1 direct arithmetic operations and direct data transfers are enabled between memory locations i e between memory and memory memory and I O and I O and In this case the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1 The address of memory location 1 is specified by index register X and the address of memory location 2 is specified by normal addressing modes 7 Overflow flag V The V flag is used during the addition or subtraction of one byte of signed data It is set if the result exceeds 127 to 128 When the BIT instruction is executed bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag 8 Negative flag N The N flag is set if the result of an arithmetic operation or data transfer is negative When the BIT instruction is executed bit 7 of the memory location opera
97. type Operation Signal format Suspend Stop of all device function No data transfer for 3 ms Resume Return of device function K state input reset input in the suspend state Reset Initialization of USB setting SEO input for 2 5 us or more Remote wake up Report of return to other devices state output for 1 to 15 ms Rev 3 00 Oct 23 2006 page 54 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 7 USB interface In 7534 Group the USB interface divides one communications line by 2 depending on the contents of data Figure 2 4 3 shows the interface of USB 7534 Group Token SETUP IN OUT Control transfer Endpoint 0 Token IN i Interrupt transfer Endpoint 1 Host system PC Hub Low Speed Function Note Transfer direction shows the DATA transmission direction of PID Fig 2 4 3 USB L S interface 8 System configuration of USB In the system configuration used with the low speed communication device of USB the host side can recognize the connection of the low speed communication device by pull up the D pin with the voltage of 3 0 to 3 6 V and the resistor of 1 5 kQ of communications lines Figure 2 4 4 shows the example of connecting USB L S 7534 Group D pull up resistor 1 5kQ Host system USB cable for L S PC Hub Untwisted Unshielded 3 Meters max Low Speed communication device Note Use the USB connector and USB cable specified to the USB specifications Fig 2
98. 0 2 36 pin and 32 pin version Not used This is a write disabled bit When this bit is read out the value is 0 Fig 2 5 5 Structure of Interrupt edge selection register Interrupt request register 1 b7 b6 b5 64 b3 b2 bi Interrupt request register 1 IREQ1 Address 3C 16 23 2 Bm receive USBIN token E No interrupt request issued interrupt request bit Interrupt request issued UART transmit USBSETUP 0 No interrupt request issued OUT token Reset Suspend 1 Interrupt request issued Resume INT 1 interrupt request bit Note 1 INTo interrupt request bit A No interrupt request issued Note 2 Interrupt request issued 3 Timer X or key on wake up No interrupt request issued interrupt request bit 1 Interrupt request issued 4 Timer 1 interrupt request bit 0 No interrupt request issued 1 Interrupt request issued Timer 2 or serial 1 2 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued CNTRo or AD converter 0 No interrupt request issued interrupt request bit 1 Interrupt request issued 7 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 These bits can be cleared to 0 by program but cannot be set Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disab
99. 0 REJ09B0178 0300 7tENESAS APPENDIX 7534 Group 3 9 SFR memory 3 9 SFR memory map 000016 Port PO PO 002016 USB interrupt control register USBICON 000116 Port PO direction register POD 002116 USB transmit data byte number set register 0 EPOBYTE 000216 Port P1 P1 002216 USB transmit data byte number set register 1 000316 Port P1 direction register P1D 002316 USBPID control register 0 EPOPID 000416 Port P2 P2 002416 USBPID control register 1 EP1PID 000516 Port P2 direction register P2D 002516 USB address register USBA 000616 Port 002616 USB sequence bit initialization register INISQ1 000716 Port P3 direction register P3D 002716 USB control 000916 Port P4 direction register P4D 002916 000016 002016 mer 000E16 002 16 mer count source set register TCSS 000 16 002 16 001016 0030146 Serial 1 2 control register SIO2CON 001116 003116 Serial 1 2 register 5102 001316 003316 001616 Pull up control register PULL 003616 001716 Port P1P3 control register P1P3C 003716 001816 Transmit Receive buffer register TB RB 003816 001916 USB status register USBSTS UART status register UARTSTS 003916 Watchdog timer control register WDTCON 001A16 Serial 1 01 control register SIO1CON 003A16 Interrupt edge selection register INTEDGE 001 16
100. 00 7534 P07 P10 RxD D lt P11 TxD D lt 27 P12 ScLkK P13 SDATA P14 CNT Ro P20 ANo lt gt P21 ANi HARDWARE DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY 2 Connect a capacitor to a device as close as possible For the capacitor a ceramic capacitor or an electrolytic capacitor of 0 22 uF is recommended 116 P34 LED4 15 P33 LED3 M37534M4 XXXGP M37534E4GP 1 P30 LEDo EE 3 P25 AN5 4 P22 AN2 P23 AN3 P24 AN4 Outline PLQPO032GB A Connect a bypass capacitor to a device as close as possible For the capacitor a ceramic capacitor or an electrolytic capacitor of 1 0 uF is recommended Reason of is to reduce the effect by switcing noise of microcomputer to the analog circuit generating USBVREFOUT output Use the bigger capacitor and connect to device at the shortest distance Reason is to prevent the instability of the USBVREFOUT output due to external noise Fig 57 Handling of Vcc USBVREFOUT pins of M37534M4 XXXGP M37534E4GP Rev 3 00 Oct 23 2006 page 54 of 55 REJ09B01 78 0300 RENESAS HARDWARE 7534 Group DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY P14 CNTRO gt P13 SDATA 15 lt P12 SCLK 16 P11 TxD D 2 gt P10 RxD D P21 AN1 lt gt P07 NC 0 P22 AN2 lt gt 5 P23 AN3 lt gt 04 P24 AN4 P25 AN5 02 26
101. 006 33 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 ICON1 Address 16 ee Bm receive USBIN token Interrupt disabled E interrupt enable bit Interrupt enabled UART transmit USBSETUP u Interrupt disabled OUT token Reset Suspend 1 Interrupt enabled Resume INT interrupt enable INTo interrupt enable bit Interrupt disabled Note 2 Interrupt enabled 3 Timer X or key on wake up Interrupt disabled interrupt enable bit Interrupt enabled 4 Timer 1 interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 Timer 2 or serial l O2 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled CNTRo or AD converter 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 Nothing is allocated for this bit Do not write 1 to this bit When this bit is read out the value is 0 Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 2 3 11 Structure of Interrupt control register 1 Rev 3 00 23 2006 page 34 of 78 134 NE SAS REJO9B01 78 0300 APPLICATION 7534 Group 2 3 Serial I O 2 3 3 Serial I O connection examples 1 Control of peripheral IC equippe
102. 012 2 1 7534 SSANO 18534 100 X NIX indui jesay indino 42015 02 L 39018 TVNOILLONn Fig 6 Functional block diagram PRDP0042BA A package type Rev 3 00 Oct 23 2006 7 of 55 REJ09B0178 0300 7534 Group HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1 Pin description Pin Name Function Function expect a port function Vcc Vss Power source Apply voltage of 4 1 to 5 5 V 4 4 to 5 25 V at USB operating to Vcc and 0 V to Vss VREF Analog reference Reference voltage input pin for A D converter voltage USBVREFOUT USB reference Output pin for pulling up a D line with 1 5 external resistor voltage output CNVss CNVss Chip operating mode control pin which is always connected to Vss RESET Reset input Reset input pin for active L XIN Clock input Input and output pins for main clock generating circuit Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins XOUT Clock output lf an external clock is used connect the clock source to the XIN pin and leave the XOUT pin open 00 07 port PO 8 bit I O port Key input key on wake up direction register allows each pin to be individually programmed interrupt input pins as either input or output CMOS 3 state output structure at CMOS compati
103. 0178 0300 HARDWARE 7534 Group FUNCTIONAL DESCRIPTION SUPPLEMENT A D Converter By repeating the above operations up to the lowest order bit of the A D conversion register an analog A D conversion is started by setting AD conversion value converts into a digital value completion bit to 0 During A D conversion internal A D conversion completes at 122 clock cycles 20 34 operations are performed as follows us at f XIN 6 0 MHz after it is started and the 1 After the start of A D conversion A D conversion result of the conversion is stored into the A D register goes to 0016 conversion register 2 The highest order bit of A D conversion register Concurrently with the completion of A D conversion is set to 1 and the comparison voltage Vref is A D conversion interrupt request occurs so that input to the comparator Then Vref is compared the AD conversion interrupt request bit is set to with analog input voltage VIN i 3 As a result of comparison when Vref lt VIN the highest order bit of A D conversion register be comes 1 When Vref gt VIN the highest order bit becomes 0 Relative formula for a reference voltage VREF of A D converter and Vref When 0 Vref 0 _ VREF When n 1 to 1023 Vref 1024 xn n the value of A D converter decimal numeral Table 10 Change of A D conversion register during A D conversion
104. 0300 7534 Stop mode HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT System enters the stop mode by executing the STP instruction In the stop mode the f XIN oscillation is stopped and the internal clock is stopped Accordlingly CPU and the peripheral devices are stopped 1 Stop mode state Table 11 shows the state at stop mode Table 11 Stop mode state Parameter State Parameter State Oscillation Stop Watchdog Stop CPU Stop RAM State retained port State retained at STP instruction SFR State retained Timer 1 and execution prescaler 12 excepted Timer At selecting internal count source CPU register State retained Stop Accumulator At selecting external count source Index register X Operating only Timer X Index register Y UART Stop Stack pointer A D conversion Stop Program counter Serial 1 02 At selecting internal synchronous Processor status register clock Stop At selecting external synchronous clock Operating USB Stop suspend state 2 Stop mode release Stop mode is released by reset input or interrupt occurrence The interrupt sources which can be used for return from stop mode are shown below e INTO e CNTRo Timer Timer X when using external clock Serial 1 02 when using external clock Key on wakeup USB function resume reset When the above interrupt sources are used for return from stop mode execute the STP instr
105. 0916 Port P4 direction register 002916 Timer 1 1 000A16 002A16 Timer 2 T2 000 16 002 1 Timer mode register 000 16 002 16 Prescaler PREX 000016 0020316 Timer X TX 000E16 002 16 Timer count source set register TCSS 000 16 002 16 001016 003016 Serial l O2 control register SIO2CON 001116 003116 Serial l O2 register 5102 001216 003216 001416 00341e A D control register ADCON 001516 003516 A D conversion register low order ADL 001616 Pull up control register PULL 003616 A D conversion register high order ADH 001716 Port P1P3 control register P1P3C 003716 001846 Transmit Receive buffer register TB RB 003816 MISRG 001916 USB status register USBSTS UART status register UARTSTS 003916 Watchdog timer control register WDTCON 001A 6 Serial 1 01 control register SIOTCON 003A16 Interrupt edge selection register INTEDGE 001 1 UART control register UARTCON 003 16 CPU mode register CPUM 001 16 Baud rate generator BRG 003C16 Interrupt request register 1 IREQ1 001Die USB data toggle synchronization register TRSYNC 003016 001 16 USB interrupt source discrimination register 1 USBIR1 003E16 Interrupt control register 1 ICON1 001 6 USB interrupt source discrimination register 2 USBIR2 003F16 Fig 13 Memory map of special fun
106. 1 control register 3 The receive interrupt RI is set when the RBF flag becomes 1 4 After data is written to the transmit buffer at TSC 1 0 5 to 1 5 cycles of the data shift cycle is necessary until changing to TSC 0 Fig 25 Operation of UART serial 1 01 function Rev 3 00 Oct23 2006 25 of 55 REJ09BO1 78 0300 RENESAS 7534 Group HARDWARE FUNCTIONAL DESCRIPTION Serial 1 01 control register SIO1CON The serial 1 control register consists of eight control bits for the serial 1 function UART control register UARTCON The UART control register consists of four control bits bits O to 3 which valid when asynchronous serial I O is selected and set the data format of an data transfer One bit in this register bit 4 is al ways valid and sets the output structure of the P11 TxD pin UART status register UARTSTS The read only UART status register consists of seven flags bits 0 to 6 which indicate the operating status of the UART function and vari ous errors This register functions as the UART status register UARTSTS when selecting the UART The receive buffer full flag bit 1 is cleared to 0 when the receive buffer is read If there is an error it is detected at the same time that data is trans ferred from the receive shift register to the receive buffer and the receive buffer full flag is set A write to the UART status register clears all the error flags OE PE FE and
107. 1 of 9 5 5 09 0178 0300 Table of contents 7534 Group 2 3 4 Serial I O transfer data format 37 2 3 5 Serial I O application examples 38 2 9 6 Notes serial tee rt ex Ee 49 LIU cp M 50 2 41 OUTING OT USB cti kx ama Siem ER see 50 2 4 2 Memory map icone ce agere E Ee e Rata rarus cr gen Db Re abe dne e ec t a 56 2 4 3 Relevant registers 57 2 4 4 USB application example 62 2 4 5 Notes concerning USB uuu a uu erret 69 2 9 A D converter a 71 2 5 1 Memory au ku 71 2 5 2 71 2 5 3 A D converter application examples 75 2 5 4 Notes on A D converter ect e ehe a Ee Lu e Eon ds 77 2 6 ROSO na MN E 78 2 6 1 Connection example of reset 78 2 6 2 Notes RESET pin iiec eL Re dear uS RR RE SLE ERE TROP e 78 CHAPTER 3 APPENDIX 3 1 Electrical characteristics U u u uu uuu uu uu u J T 2 3 1 1 Absolute maximum 2 3 1 2 Recommended operating conditions
108. 20 shows processing to the width of the signal according to the situation TKNE RSME RSTE 0 us 0 50 us 2 50 us 2 67 us D pin state i 1 1 Idle state i i Keep Alive Reset RSTRQ 1 n Reset RSTRQ 1 1 1 Token phase state 1 Signal ignored FEOPE 1 EOP RxPID 1 EOP RxPID 1 Reset RxPID 0 1 Reset RSTRQ 1 Data Handshake 0 Signal ignored FEOPE 1 EOP EOP 1 EOP RSTRQ OJ Reset RSTRQ 1 Reset RSTRQ 1 phase state Suspend state 0 Reset RSTRQ 1 Resume RSTRQ 0 Note Each active state represents the processing is required in H state Fig 2 4 20 Processing for width of SEO signal Rev 3 00 Oct 23 2006 page 69 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 4 USB communication In applications requiring high reliability we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly for example due to external causes such as noise 5 USB suspend current When USB suspend mode with TTL level on P10 P12 P13 input level selection bit bit 3 of address 1716 set to 1 suspend current as Icc might be greater than 300 uA as a spec Countermeasure There are two countermeasures by software to avoid it as follows 1 Change from TTL input level to CMOS input level for P10 P12 P13 port input 2 Chan
109. 3 0 65 0 8 0 95 045 L 0 5 07 Rev 3 00 23 2006 53 of 70 2 1 5 09 0178 0300 APPENDIX 7534 Group 3 6 Package outline PLQP0032GB A JEITA Package Code RENESAS Code Previous Code MASS Typ P LQFP32 7x7 0 80 PLQP0032GB A 32P6U A 0 29 Ho 2 D 24 17 i NOTE 1 DIMENSIONS 1 AND 2 S i co DO NOT INCLUDE MOLD FLASH 25 46 2 DIMENSION 3 DOES INCLUDE TRIM OFFSET bp bi ul pl IReference Dimension in Millimeters Symbol Min Nom D 69 7 0 7 1 Terminal cross section E 69170 74 E 2 984 Az 14 8 8 9 0 92 88 90 92 1 A 1 1417 2 Index mark A 0 01102 F 1 bp 0 32 0 37 0 42 J b 035 c 0 09 0 145 0 20 f N zl tote 0 125
110. 3 3 3 10 Termination of unused Ping 24 3 3 11 Notes CPU mode 25 3 3 12 Notes on using 32 pin 25 3 3 13 Electric characteristic differences among mask ROM and One Time PROM version MCUs 25 3 3 14 Note on power source voltage 25 3 39 15 USB communication 1 citi err e enh ead eae visions 26 3 4 Countermeasures against noise u u u uu uu u uu u 27 3 4 1 Shortest wiring length 27 3 4 2 Connection of bypass capacitor across Vss line and Voc line 29 3 4 3 Wiring to analog input 30 Rev 3 00 23 2006 page 2 of 9 RENESAS REJ09B0178 0300 Table of contents 7534 Group 3 4 4 Oscillator RANEES RINES 30 3 4 5 Setup for ee 32 3 4 6 Providing of watchdog timer function by software 33 3 5 List of teglIStets 2 iii rotae i ane Yu aUe 34 3 6 Package outline 11e erre eer nnne tnn manat nnnm nnn nn tnn nant 53 3 7 List of instruction code
111. 3 00 Oct 23 2006 8 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics Measuring condition At STP instruction execution at stop Typical sample Ta 25 C lt c s o 2 2 o o o 2 o o a 40 45 Power source voltage Vcc V Fig 3 2 3 Icc Vcc characteristic example At STP instruction execution Ta 25 C Measuring condition At STP instruction execution at stop Typical sample Ta 85 C lt 2 2 5 e 2 o n 40 45 Power source voltage Vcc V Fig 3 2 4 Icc Vcc characteristic example At STP instruction execution Ta 85 Rev 3 00 23 2006 page 9 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics Measuring condition At STP instruction execution at USB suspend output current from USBVREFOUT pin included Typical sample Ta 25 C USBVREFOUT 3 29 V Power source current Icc uA 4 5 5 0 Power source voltage Vcc V Fig 3 2 5 characteristic example at USB suspend Ta 25 C Measuring condition A D conversion executed not executed f Xin 6MHz in double speed mode Typical sample Ta 25 C At ceramic oscillation During A D conversion During not A D conversion lt amp c o 2 2 o o 2 2 o o o z o A 4 0 45 Power source volta
112. 3 Table 8 32P6U A added Name of Programming Adapter revised 00 00 2 Jun 21 2004 pages Words standardized On chip oscillator A D converter Electric Characteristic Difference Among Mask ROM and One Time PROM Version MCUs added Note on Power Source Voltage added DATA REQUIRED FOR MASK ORDERS revised 3 3 12 Electric Characteristic Difference Among Mask ROM and One Time PROM Version MCUs 3 3 13 Note on Power Source Voltage added 32P6U A revised Re 3 Oct 23 2006 All pages Package names 36P2R A PRSP0036GA revised Package names 32P6U A PLQP0032GB A revised Package names 42P4B 42 revised USB Spec Rev 1 1 Low Speed USB2 0 specification revised Clock Generating Circuit No external resistor is needed resistor exists on chip No external resistor is needed depending on conditions Fig 45 Pulled up added NOTE added Fig 48 NOTE 2 added NOTES ON PROGRAMMING Watchdog Timer added NOTES ON USE USB Communication added NOTES ON USE Note on A D Converter added 2 4 1 Transfer type Hi Speed function H S added 2 4 5 USB Communication added 2 5 4 3 Method to stabilize A D Converter added 1 2 REVISION HISTORY 7534 Group User s Manual Summary 3 3 3 3 Method to stabilize A D Converter 3 3 4 Notes on watchdog timer 3 3 15 USB Communication added 3 6 Package outline revised RENESAS 8 BIT
113. 31 Structure of serial l O1 related registers 3 b6 CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Not used b7 CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Clear Rev 3 00 Oct 23 2006 page 30 of 55 REJ09B01 78 0300 RENESAS 7534 HARDWARE FUNCTIONAL DESCRIPTION USB sequence bit initialization register INISQ1 address 002616 A sequence bit of endpoint 1 is initialized CPU read Disabled CPU write Dummy Hardware read Not used Hardware write Not used USB control register USBCON address 002716 Not used return 1 when read CPU read Disabled USBVREFOUT output valid flag CPU write Set Clear 0 Output off Hardware read Used 1 Output on Hardware write Not used CPU read Disabled Remote wake up request flag CPU write Set 0 No request Hardware read Used 1 Remote wake up request Hardware write Clear UART status register UARTSTS address 001916 Transmit buffer empty flag 0 Buffer full 1 Buffer empty Receive buffer full flag read write Disable E empty Hardware read Not used Bu B Hardware write Set Clear Transmit shift regi
114. 4 4 USB L S connection example Rev 3 00 Oct23 2006 55 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 24 USB 2 4 2 Memory map 001816 lransmit Receive buffer register TB RB 001916 USB status register USBSTS 001A16 Serial 1 control register SIO1CON Ww 002616 USB sequence bit initialization register 5 1 002716 USB control register USBCON 003 16 Interrupt request register 1 IREQ1 A 003E ie Interrupt control register 1 ICON1 Y y Fig 2 4 5 Memory map of registers relevant to USB Rev 3 00 Oct 23 2006 page 56 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 2 4 3 Relevant registers In this section the contents of control are described as follows Transmit Receive buffer Setting to enable disable of each function including USB communication and interrupts Determination of USB communication error occurrence Setting to stage and handshake by unit of endpoint Auto determination of self address of USB device Figure 2 4 6 shows the description of the register structure and Figure 2 4 7 to Figure 2 4 10 show the register structures relevant to USB Register name Symbol Address b7 b6 b5 b4 b3 b2 l l l T T Initial value ymbol of bit name po I X Initial value undfined Remarks CPU RD Read from CPU Enable Read enabled CPU WR Write from CPU Set Clear Write 0 1 enab
115. 5 2 Relevant registers A D control register b7 b6 b5 b4 b3 b2 61 bO A D control register ADCON Address 3416 Function Analog input pin selection bits b2 b 60 T 0 P2o ANo 1 P21 AN1 0 P22 AN2 1 P23 AN3 0 P24 AN4 1 0 1 P25 AN5 P2e AN6 P27 AN7 C O 3 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the value 0 4 AD conversion completion bit 0 onversion in progress 1 1 Conversion completed Nothing is allocated for these bits These are write disabled bits When these bits are read out the values are 0 Note P26 ANe P27 AN7 be selected in the 36 pin and 42 pin versions This bit can be cleared to 0 by program but cannot be set to 1 Fig 2 5 2 Structure of A D control register Rev 3 00 23 2006 page 71 of 78 ztENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 5 A D converter A D conversion register high order b7 66 25 b4 63 b2 61 bO Em A D conversion register high order ADH Address 3616 The read only register in which the A D conversion s results are stored lt 10 bit read gt Nothing is allocated for these bits These are write disabled bits When these bits are read out the values are 0 Fig 2 5 3 Structure of A D conversion register high order A D
116. 6 or more pulses input in the condition of Timer X 255 Fig 2 2 19 Relevant registers setting Rev 3 00 Oct 23 2006 24 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer RESET Initialization X This bit is not used here Set it to 0 or 1 arbitrary SEI All interrupts disabled INTEDGE address 16 bits 0 Timer X interrupt selected address 2B16 000011102 Timer X operating mode Event counter mode address 281 Count a falling edge of pulses input from CNTR o pin address 291 Set division ratio so that Timer 1 interrupt will occur at address 2C 2 ms intervals address 2D address Timer 1 interrupt enabled Timer X interrupt disabled address 2 16 bit3 0 Timer X count start Interrupts enabled Timer 1 interrupt process routine CLT Note 1 Note 1 When using Index X mode flag T CLD Note 2 Note 2 When using Decimal mode flag D Push registers to stack Push registers used in interrupt process routine IREQ1 address 3C 16 bit3 2 Process as out of range when the count value is 256 or more Read the count value AJ E TA address EDS Store the count value into Accumulator In range i 214 lt A lt 228 the read value with reference value Store the comparison result to Out of range flag Fpulse 0 Fpulse 1 TX address 2016 256 1 Initialize the counter value I
117. 7534 Group 3 3 Notes on use 4 Serial 1 02 transmit receive shift completion flag The transmit receive shift completion flag of the serial 1 02 control register is set to 1 after completing transmit receive shift In order to set this flag to 0 write data dummy data at reception to the serial 1 2 register by program 7 of the serial 1 02 control register is set to 1 a half cycle of the shift clock earlier than completion of shift operation Accordingly when using this bit to confirm shift completion a half cycle or more of the shift clock must pass after confirming that this bit is set to 1 before performing read write to the serial 1 02 register 3 3 3 Notes on A D converter 1 Analog input pin Make the signal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01uF to 1uF Further be sure to verify the operation of application products on the user side Reason An analog input pin includes the capacitor for analog voltage comparison Accordingly when signals from signal source with high impedance are input to an analog input pin charge and discharge noise generates This may cause the A D conversion precision to be worse 2 Clock frequency during A D conversion The comparator consists of a capacity coupling and a charge of the capacity will be lost if the clock frequency is too low Thus make sure the following during an A D conversion f XIN
118. 9B01 78 0300 APPLICATION 7534 Group 2 2 Timer Timer 1 b7 b6 b5 64 b3 b2 61 00 Timer 1 T1 Address 29 16 Set a count value of timer 1 value set in this register is written to both timer 1 and timer 1 latch at the same time EREE When this register is read out the timer 1 s count value is read u Fig 2 2 3 Structure of Timer 1 Timer 2 57 b6 b5 b4 b3 b2 b1 50 Timer 2 T2 Address 2A 16 Set a count value of timer 2 value set in this register is written to both timer 2 and timer 2 latch at the same time When this register is read out the timer 2 5 count value is read F Fig 2 2 4 Structure of Timer 2 Rev 3 00 23 2006 page 11 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer Timer X b7 b6 b5 b4 63 b2 61 00 Timer X TX Address 2D 16 Set a count value of timer X value set in this register is written to both timer X and timer X latch at the same time Xe When this register is read out the timer X s count value is read Fig 2 2 5 Structure of Timer Rev 3 00 Oct 23 2006 page 12 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer Timer X mode register b7 b6 b5 64 b3 b2 bi bO Timer X mode register TM Address 2B 16 paier mode Pulse output mode Event
119. Address 2A 16 Set a count value of timer 2 value set in this register is written to both timer 2 and timer 2 latch at the same time this register is read out the timer 275 count value is read EAE Fig 3 5 24 Structure of Timer 2 Rev 3 00 Oct 23 2006 44 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TM Address 2B 16 Aine mode Pulse output mode Event counter mode Pulse width measurement mode The function depends on the operating mode Refer to Table 3 5 1 pr ERE Fig 3 5 25 Structure of Timer mode register Table 3 5 1 CNTRo active edge switch bit function Timer X operation modes CNTRo active edge switch bit bit 2 of address 2Bis contents Timer mode 0 CNTRo interrupt request occurrence Falling edge No influence to timer count 1 interrupt request occurrence Rising edge No influence to timer count 0 Pulse output start Beginning at level CNTRo interrupt request occurrence Falling edge Pulse output start Beginning at L level CNTRo interrupt request occurrence Rising edge O Timer X Rising edge count CNTRo interrupt request occurrence Falling edge 1 Timer X Falling edge count CNTRo interrupt request occurrence Rising edge 0 Timer X H level width meas
120. B16 000010012 Stop output Stop piezoelectric buzzer output TX address 2D16 94 1 Set division ratio 1 to Timer X and Prescaler X PREX address 2 16 1 1 Main processing Output unit Process piezoelectric buzzer request generated during Yes main processing in output unit Piezoelectric buzzer request TM address 2 16 bit3 1 TM address 2 16 bit3 lt 0 TX address 2D 16 lt 94 1 Start piezoelectric buzzer output Stop piezoelectric buzzer output Fig 2 2 17 Control procedure Rev 3 00 Oct 23 2006 22 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer 4 Timer application example 3 Frequency measurement Outline The following two values are compared to judge whether the frequency is within a valid range value by counting pulses input to P14 CNTRo pin with the timer reference value Specifications pulse is input to the P14 CNTRo and counted by the timer count value is read out at about 2 ms intervals the timer 1 interrupt interval When the count value is 28 to 40 it is judged that the input pulse is valid Because the timer is down counter the count value is compared with 227 to 215 Note Note 227 215 255 initial value of counter 28 to 40 the number of valid count Figure 2 2 18 shows the judgment method of valid invalid of input pulses Figure 2 2 19 sh
121. Bit 2 definition Bit 2 definition INTO Rev 3 00 Oct23 2006 52 of 55 RENESAS Bit 1 definition UART transmission USB except Bit 2 not available HARDWARE 7534 Group DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY DESCRIPTION SUPPLEMENT FOR USE OF USB FUNCTION STABLY P12 SCLK P11 TxD D P13 SDATA gt P10 RxD D P14 CNTRo gt 07 2 21 lt gt POs P22 AN2 lt gt P23 AN3 lt gt P24 AN4 lt gt 02 P25 AN5 P26 AN6 P27 AN7 USBVREFOUT VREF RESET CNVss Vcc XIN gt XOUT lt Vss dd83v S IN d4XXX vINTESZEIN Outline PRSPO036GA Connect a bypass capacitor to a device Connect a capacitor to a device as as close as possible For the capacitor close as possible For the capacitor a ceramic capacitor or an electrolytic a ceramic capacitor or an electrolytic capacitor of 1 0 uF is recommended capacitor of 0 22 uF is recommended Reason of is to reduce the effect by switcing noise of microcomputer to the analog circuit generating USBVREFOUT output Use the bigger capacitor and connect to device at the shortest distance Reason of Q is to prevent the instability of the USBVREFOUT output due to external noise Fig 56 Handling of Vcc USBVREFOUT pins of M37534M4 XXXFP M37534E8FP Rev 3 00 Oct 23 2006 page 53 of 55 5 5 09 0178 03
122. EOP flag FEOPE set Time is out with EOP not detected at data phase or handshake phase This bit is cleared to 0 by writing dummy to this register False EOP error flag 0 No error Ena Clear Set 1 False EOP error ble This bit is set to 1 when the phase is not completed normally This bit is cleared to 0 by writing dummy to this register CRC error flag 0 No error Ena Clear Set 1 CRC error ble This bit is set to 1 when the CRC error occurs at the same timing of EOP detection flag This bit is to 0 cleared by writing dummy to this register PID error flag 0 No error Ena Clear Set 1 PID error ble Setting condition of this flag to 1 is as follows of DATAO DATA1 cannot be detected at data phase after OUT or SETUP token ACK PID cannot be received at handshake phase during IN transaction This bit is cleared to 0 by writing dummy to this register Bit stuffing error flag 0 No error Ena Clear Set 1 Bit stuffing error ble This bit is set to 1 when bit stuffing error occurs at data phase or handshake phase This bit is cleared to 0 by writing dummy to this register Summing error flag 0 No error Ena Clear Set 1 Summing error ble This bit is set to 1 when any error of FEOPE CRCE PIDE or BSTFE occurs This bit is cleared to 0 by writing dummy to this register Receive buffer full 0 Buffer empty Ena Set flag 1 Buffer full ble Clear This bit is se
123. FFD16 16 At reset input Non maskable UART receive 2 FFFB16 FFFA16 At completion of UART data receive Valid in UART mode USB IN token At detection of IN token Valid in USB mode UART transmit 3 FFF916 FFF816 At completion of UART transmit shift or Valid in UART mode when transmit buffer is empty USB SETUP OUT token At detection of SETUP OUT token or Valid in USB mode Reset Suspend Resume At detection of Reset Suspend Resume INT1 Note 3 At detection of either rising or falling edge External interrupt of INT1 input active edge selectable INTo Note 4 4 FFF716 FFF616 At detection of either rising or falling edge External interrupt of INTo input active edge selectable Timer X 5 FFF516 FFF416 At timer X underflow Key on wake up At falling of conjunction of input logical External interrupt valid at falling level for port PO at input Timer 1 6 FFF316 FFF216 At timer 1 underflow STP release timer underflow Timer 2 7 FFF116 FFFO16 At timer 2 underflow Serial 1 02 At completion of transmit receive shift CNTRo 8 16 16 At detection of either rising falling edge External interrupt active edge of CNTRo input selectable A D conversion At completion of A D conversion BRK instruction 9 FFED16 FFECis At BRK instruction execution Non maskable software interrupt Note 1 Vector addressed contain internal jump destination addresses 2 Reset function in the same way as an interrupt with the highest priority 3
124. Fig 2 1 9 Relevant registers setting 6 Fig 2 1 10 Application circuit 6 2 1 11 Control procedure cett he 7 Fig 2 2 1 Memory of registers relevant to 1 10 Fig 2 2 2 Structure of Prescaler 12 Prescaler 10 Fig 2 2 3 Structure of Timer Tu ua e Pu star 11 Fig 2 2 4 Str cture of TIMOR 2 tegat er pesetas rx 11 Fig 2 25 Str ct re of Timer X u uu tuat aaa id Lu adu 12 Fig 2 2 6 Structure of Timer X mode 13 Fig 2 2 7 Structure of Timer count source set 14 Fig 2 2 8 Structure of Interrupt edge selection register 14 Fig 2 2 9 Structure of Interrupt request register 1 15 Fig 2 2 10 Structure of Interrupt control register 1 sss 15 Fig 2 2 11 Timers connection and setting of division 17 Fig 2 2 12 Relevant registers setting 18 Fig 2 2 13 Control DrOCeQUre tte ee es 19 Fig 2 2 14 Peripheral circuit 20 Fig 2 2 15 Timers connection and setting of division ratios 20 Fig 2 2 16 Relevan
125. IN token interrupt of DATA0 1 is valid 01xx STALL handshake is valid for IN token 00xx NAK handshake is valid for IN token xxx1 STALL handshake is valid for OUT token Note xx10 ACK handshake is valid for OUT token xx00 NAK handshake is valid for OUT token x any data Set a number of data byte for transmitting with endpoint 0 Set a number of data byte for transmitting with endpoint 1 CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Not used b4 b5 b6 CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Not used b7 CPU read Enabled CPU write Set Clear Hardware read Used Hardware write Clear Note In the status stage of the control read transfer when PID of data packet DATAO incorrect PID this bit is set forcibly by hardware and STALL handshake is valid USB PID control register 1 EP1PID address 002416 Not used return 1 when read Endpoint 1 PID selection flag 1x IN token interrupt of DATAO is valid 01 STALL handshake is valid for IN token 00 NAK handshake is valid for IN token x any data USB address register USBA address 002516 Set an address allocated by the USB host CPU read Disabled CPU write Set Clear Hardware read Used Hardware write Not used Not used returns 1 when read Fig
126. ION SUPPLEMENT FOR USE OF USB FUNCTION STABLY 7534 Group HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION DESCRIPTION The 7534 Group is the 8 bit microcomputer based on the 740 family core technology The 7534 Group has a USB 8 bit timers and an A D converter and is useful for an input device for personal computer peripherals FEATURES e Basic machine language instructions 69 e The minimum instruction execution time 0 34 us at 6 MHz oscillation frequency for the shortest instruction Memory size ROM iiir eras 8K to 16K bytes nitus 256 to 384 bytes Programmable I O ports 28 36 type PE 24 32 pin type RA 33 42 pin type nterrupts unen 14 sources 8 vectors DUC 8 bit X 3 PIN CONFIGURATION TOP VIEW 12 P13 SDATA gt P14 CNTRo P20 ANo P21 AN1 P22 AN2 lt gt P23 AN3 gt P24 AN4 P25 AN5 lt gt 26 P27 AN7 VREF gt RESET CNVss lt N C1 D m T U ddXXX vINTESZEIN Serial Interface Serial VOT used only for Low Speed USB based on Low Speed USB2 0 specification USB UART Serial eit Perte 8 bit X 1 Clock synchronized e A D converter La u
127. IPTION FUNCTIONAL DESCRIPTION Central Processing Unit CPU The 7534 group uses the standard 740 family instruction set Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set Machine resident 740 family instructions are as follows The FST and SLW instructions cannot be used The MUL and DIV instructions cannot be used The WIT and STP instructions can be used The central processing unit CPU has the six registers Accumulator A The accumulator is an 8 bit register Data operations such as data transfer etc are executed mainly through the accumulator Index register X X Index register Y Y Both index register X and index register Y are 8 bit registers In the index addressing modes the value of the OPERAND is added to the contents of register X or register Y and specifies the real address When the T flag in the processor status register is set to 1 the value contained in index register X becomes the address for the second OPERAND Stack pointer S The stack pointer is an 8 bit register used during sub routine calls and interrupts The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines The lower eight bits of the stack address are determined by the con tents of the stack pointer The upper eight bits of the stack address are determined by the Stack Pa
128. LB and SEB and read modify write instructions of direction registers for calculations such as ROR For setting direction registers use the LDM instruction STA in struction etc As for the 36 pin version set 1 to each bit 6 of the port P3 direc tion register and the port P3 register As for the 32 pin version set 1 to respective bits 5 6 7 of the port P3 direction register and port P3 register A D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low Make sure that is 500kHz or more during A D conversion Do not execute the STP instruction during A D conversion Watchdog Timer The internal reset may not be generated correctly in the middle speed mode depending on the underflow timing of the watchdog timer When using the watchdog timer operate the MCU in any mode other than the middle speed mode i e high speed low speed or double speed mode Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine language instruction table The frequency of the internal clock is the same as that of the Xin in double speed mode twice the Xin cycle in high speed mode and 8 times the Xin cycle in middle speed mode Note on stack page When 1 page is used as stack area by the stack page selection bit the area which can be used as st
129. MX M C tents of M and the complement of C from the contents of M X and stores the results in M X and C A remain unchanged but status flag are changed M X represents the contents of memory where is indicated by X Ai or Mi 1 This instruction sets the designated bit i of A or M This instruction sets C This instruction set D This instruction set 1 This instruction set T This instruction stores the contents of A in M The contents of A does not change This instruction resets the oscillation control F F and the oscillation stops Reset or interrupt input is needed to wake up from this mode This instruction stores the contents of X in M The contents of X does not change This instruction stores the contents of Y in M The contents of Y does not change This instruction stores the contents of A in X The contents of A does not change This instruction stores the contents of A in Y The contents of A does not change This instruction tests whether the contents of M are 0 or not and modifies the N and Z This instruction transfers the contents of S in X This instruction stores the contents of X in A This instruction stores the contents of X in S This instruction stores the contents of Y in A The WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped CPU starts its function after the
130. O functions For receiving set O to bit 3 When receiving bit 7 is cleared by writing dummy data to serial 1 O2 register after shift is completed Bit 7 is set earlier a half cycle of shift clock than completion of shift operation Accordingly when checking shift completion by using this bit the setting is as follows 1 check that this bit is set to 1 2 wait a half cycle of shift clock 3 read write to serial 1 2 register SCLK pin selection bit SCLK Serial 1 2 control register SIO2CON address 003016 Internal synchronous clock selection bits 000 f XIN 8 001 f XIN 16 XIN 010 f XIN 32 011 f XIN 64 110 f XIN 128 111 f XIN 256 SDATA pin selection bit Note 0 I O port SDATA input 1 SDATA output Not used returns 0 when read Transfer direction selection bit 0 LSB first 1 MSB first SCLK pin selection bit 0 External clock SCLK is an input 1 Internal clock SCLK is an output Transmit receive shift completion flag 0 shift in progress 1 shift completed Note When using it as an SDATA input set the port P13 direction register to 0 Fig 34 Structure of serial 1 02 control registers Data bus Internal synchronous clock selection bits SCLK pin selection bit v P12 latch Serial I O counter 2 3 Serial 1 02 interrupt request SDATA pin selection bit
131. POD address 0116 lt XXXXXXX02 Setting of port for communication control UARTSTS address 1916 Confirmation of reception completion Receive buffer full flag 1 Data receception of the first byte This read causes Receive buffer full flag to be cleared to 0 Read out received data from RB address 1816 Error flag check UARTSTS address 1916 616 2 Confirmation of reception UARTSTS address 1916 bit1 completion Receive buffer full flag 1 Data receception of the second Read out received data from byte RB address 1816 This read causes Receive buffer full flag to be cleared to 0 k UARTSTS address 1916 bit6 Errar f g cheg gt Error process PO address 0016 bitO 0 SIO1CON address 1A16 11XXXXXX2 1 01 cleared SIO1CON address 1 16 lt 00 2 l O1 disabled Countermeasure for a bit slip Serial 1 clear procedure SIO1CON address 1A16 101000012 Serial l O1 enabled Fig 2 3 27 Control procedure of reception side Rev 3 00 Oct 23 2006 48 of 78 1320 NE SAS REJO9B01 78 0300 APPLICATION 7534 Group 2 3 Serial I O 2 3 6 Notes on serial 1 Handling of clear the serial 1 1 When serial 1 01 is set again or the transmit receive operation is stopped restarted while serial 1 is operating clear the serial 1 a
132. Ports 20 27 m gt Direction register Y Direction register 93 J gt Data bus 7171 Port latch gt bus Port latch se output A D converter input Timer Analog input pin selection bit CNTRo interrupt input 7 9 Ports 36 P37 8 Ports P3o P35 Pull up control Direction register 9 Direction register Databus 7 Portlatch 7 Data bus t Port latch 94 P37 INTo input level selection bit INT interrupt input I Pull up control 10 Ports P15 P16 4 P41 Direction register Data bus Port latch P10 P12 P13 P36 P37 input levels are switched to the CMOS TTL level by the port P1P3 control register When the TTL level is selected there is no hysteresis characteristics Fig 17 Block diagram of ports 2 Rev 3 00 Oct 23 2006 page 19 of 55 5 5 REJ09B0178 0300 7534 Group HARDWARE FUNCTIONAL DESCRIPTION Interrupts Interrupts occur by 14 different sources 4 external sources 9 inter nal sources and 1 software source Interrupt control All interrupts except the BRK instruction interrupt have an interrup
133. REJ09B0178 0300 2 1 5 7534 Transmit buffer register TB address 001816 HARDWARE FUNCTIONAL DESCRIPTION After setting data to address 001816 a content of the transmit buffer register transfers to the transmit shift register automatically CPU read Disabled CPU write Set Clear Hardware read Used Hardware write Not used Receive buffer register RB address 001816 By reading data from address 001816 a content of the receive buffer register can be read out CPU read Enabled CPU write Disabled Hardware read Not used Hardware write Set Clear USB status register USBSTS address 001916 Transmit buffer empty flag 0 Buffer full 1 Buffer empty EOP detection flag 0 Not detected 1 Detect False EOP error flag 0 No error 1 False EOP error CRC error flag 0 No error 1 CRC error PID error flag 0 No error 1 PID error Bit stuffing error flag 0 No error 1 Bit stuffing error Summing error flag 0 No error 1 Summing error Receive buffer full flag 0 Buffer empty 1 Buffer full Fig 29 Structure of serial l O1 related registers 1 Rev 3 00 Oct 23 2006 page 28 of 55 REJ09B01 78 0300 7tENESAS CPU read Enabled CPU write Disabled Hardware read Not used Hardware write Set Clear CPU read Enabled CPU write Clear Hardware read Not used Hardware write Set CPU read Enab
134. REQ1 address 3C 16 bit3 0 Clear Timer X interrupt request bit Process judgment result Pop registers Pop registers pushed to stack RTI Fig 2 2 20 Control procedure Rev 3 00 Oct 23 2006 page 25 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer 5 Timer application example 4 Measurement of FG pulse width for motor Outline The timer X counts the H level width of the pulses input to the P14 CNTRo pin An underflow is detected by the timer X interrupt and an end of the input pulse H level is detected by the CNTRo interrupt Specifications timer X counts the H level width of the FG pulse input to the P14 CNTRo pin Example When the clock frequency is 6 00 MHz the count source is 2 7 us which is obtained by dividing the clock frequency by 16 Measurement can be made up to 174 ms in the range of FFFF e to 000016 Figure 2 2 21 shows the timers connection and setting of division ratio Figure 2 2 22 shows the relevant registers setting Figure 2 2 23 shows the control procedure Timer X count source Timer X interrupt selection bit Prescaler X Timer X request bit f XiN 6 00 MHz 1 16 1 256 1 256 174 ms 0 No interrupt request issued 1 Interrupt request issued Fig 2 2 21 Timers connection and setting of division ratios Rev 3 00 Oct 23 2006 page 26 of 78 7tENESAS 09 0178 0300 APPLICATION 7534 Group 2 2 Timer Interrupt edge selec
135. Reset address from the Data vector table 8 13 clock cycles Notes 1 An on chip oscillator applies about 250 kHz frequency as clock f at average of Vcc 5 V 2 The mark means that the address is changeable depending on the previous state 3 These are all internal signals except RESET Fig 43 Timing diagram at reset Rev 3 00 Oct 23 2006 38 of 55 RENESAS REJ09B0178 0300 7534 HARDWARE FUNCTIONAL DESCRIPTION Port PO direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Pull up control register USB UART status register Serial l O1 control register UART control register I 1 1 1 USB interrupt control register 2 3 4 5 6 USBPID control register 0 7 USBPID control register 1 8 USB address register 9 20 USB control register 21 Prescaler 12 22 Timer 1 23 Timer 2 24 Timer X mode register 25 Prescaler X 26 Timer X 27 Timer count source set register 28 Serial 1 2 control register 29 A D control register 30 MISRG 31 Watchdog timer control register 32 Interrupt edge selection register 33 CPU mode register 34 Interrupt request register 1 35 Interrupt control register 1 36 Processor status register 37 Program counter Fi
136. SB Vcc BUS ANo to USBVREFOUT 2 0 01to1pF 7534 Group 0 1 to 1 pF Recommends for A D accuracy Fig 50 Method to stabilize A D conversion accuracy b It is recommended for A D accuracy to avoid converting while USB communication and use average value of several con verted values DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc tion 1 Mask ROM Order Confirmation Form 2 Mark Specification Form 3 Data to be written to ROM in EPROM form three identical copies For the mask ROM confirmation and the mark specifications refer to the Renesas Technology Corp Homepage http www renesas com Rev 3 00 Oct 23 2006 page 43 of 55 REJ09B01 78 0300 5 5 HARDWARE 7534 Group ROM PROGRAMMING METHOD The built in PROM of the blank One Time PROM version can be read or programmed with a general purpose PROM programmer us ing a special programming adapter Set the address of PROM pro grammer in the user ROM area Table 8 Special programming adapter _______ of Programming Adapter PLQP0032GB A PCA7435GPG03 PRSP0036GA A PCA7435FP PCA7435FPG02 PRDP0042BA A PCA7435SP PCA7435SPG02 The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes To en sure proper operation after programming t
137. SE bit 3 to bit 6 respectively Writing 0 to the serial 1 mode selection bits MOD1 and MODO bit 7 and 6 of the Serial 1 01 control register also clears all the status flags including the error flags All bits of the serial l O1 status register are initialized to 8116 at reset but if the transmit enable bit bit 4 of the serial 1 01 control register has been set to 1 the continuous transmit valid bit bit 2 becomes 1 Transmit Receive buffer register TB RB The transmit buffer and the receive buffer are located at the same address The transmit buffer is write only and the receive buffer is read only If a character bit length is 7 bit the MSB of data stored in the receive buffer is 0 Baud Rate Generator BRG The baud rate generator determines the baud rate for serial transfer The baud rate generator divides the frequency of the count source by 1 n 1 where n is the value written to the baud rate generator Transmit Receive Clock Transmit Buffer Register Write Signal Serial Output TXD 1 Start Bit c 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit Notes 1 When the serial 1 mode selection bits 67 b6 is 10 the transmit enable bit is 1 and continuous transmit valid bit is 1 writing on the transmit buffer initiates continuous transmission of the same data 2 Select 0 for continuous transmit valid bit to stop continuou
138. SINGLE CHIP MICROCOMPUTER USER S MANUAL 7534 Group Publication Data Rev 1 00 Nov 24 2000 Rev 3 00 Oct 23 2006 Published by Sales Strategic Planning Div Renesas Technology Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan 7534 Group User s Manual 5 5 Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REJO9B0178 0300
139. TOP VIEW P24 AN4 P25 AN5 2 P27 AN7 P40 P41 VREF gt RESET CNVss Vcc XIN XOUT dS893F8SZECIN dSXXX VINVESZEW SSUrESZEW HARDWARE PIN CONFIGURATION P13 SDATA P12 SCLK P11 TxD D P10 RxD D P07 06 05 04 P03 02 USBVREFOUT P37 INTo INT1 Outline 4251 PRDPO0042BA A 42 Fig 3 Pin configuration of M37534RSS M37534M4 XXXSP M37534E8SP Rev 3 00 23 2006 page 4 of 55 REJ09B0178 0300 7RENESAS HARDWARE FUNCTIONAL BLOCK 7534 Group FUNCTIONAL BLOCK Od 1 oF 5 069 x ia dn gud uod d mma Y 01 BIB yesoy 9 x 8 z 8 1 8 2015 C 6 SSANO 18534 indui jeseg V v59e00dSud NVHDVIG 429018 Inox NIX indino 42019 Fig 4 Functional block diagram PRSP0036GA A package type 5 5 Rev 3 00 Oct 23 2006 5 of 55 REJ09B0178 0300 HARDWARE FUNCTIONAL BLOCK 7534 Group
140. Table 2 4 4 PID Packet PID Bit structure Processing type bits 3 to 0 Token 11012 The processing is reported by host to device 10012 Data transmit is requested from host to device 00012 Data receive is requested from host to device 01012 Top of frame is indicated by host to device Data 00112 The state that sequence bit of transmit receive data is even is indicated 10112 The state that sequence bit of transmit receive data is odd is indicated Handshake 00102 Normal completion of communication is reported 10102 The state that device is waiting for communication is reported 11102 Completion error of communication is reported Special 11002 Communication to the L S device which has low priority is enabled In 7534 Group data except SOF and PRE of PID can be controlled by software Rev 3 00 Oct 23 2006 page 53 of 78 5 5 09 0178 0300 APPLICATION 7534 Group 2 4 USB 6 USB special signal The host side has function to control the state of the device side and the device side has the function to transmit the state to the host side and other devices on USB communications line by the signal besides the above mentioned data transfer Usually the transfer confirmation Keep alive Idle only for L S is performed on the USB communication line regardless of data transmit receive The contents of transfer confirmation are as follows host confirms the connection of device on the co
141. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 17 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 2 NE S AS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gr
142. USB2 0 specification SIE Hardware operation in 7534 group F W Recommendation process in the program FEOPE False EOP error flag bit 2 of address 1916 RxPID Token interrupt flag bit 7 of address 1F16 Table 7 Relation of the width of SEO and the state of the device State of device End of data or handshake Idle state End of Token in transaction in transaction Suspend state TKNE X TKNE 1 TKNE 0 RSME 0 RSME 0 RSME 1 7 RSME 0 E RSTE 1 RSTE 1 RSTE 0 or 1 RSTE 0 Spec Ignore Ignore Ignore Keep counting suspend Not detected as EOP in Not detected as EOP in 0 us timer case of no detection EOP case of no detection EOP H SIE SIE returns idle state as SIE returns idle state as 0 5 us time out FEOPE flag is timeup FEOPE flag is Spec Reset or resume set set F W Not acknowledge Not acknowledge Wait for the next EOP flag Spec Keep alive EOP EOP SIE Initialize suspend timer Token interrupt request Set EOP flag 0 5 us count value 2 5 us Not acknowledge Token interrupt processing After checking the set of FAN execute EOP flag go to the next processing SIE Reset interrupt Spec Keep alive or Reset EOP or Reset EOP or Reset request may determine as keep may determine as EOP and may determine as EOP SIE alive and Reset interrupt Reset interrupt and Reset interrupt 2 5 us Keep alive in case of no RxPID 1 gt Token interrupt Continue the proces
143. Use transmitting with endpoint 1 ble Clea Fig 3 5 16 Structure of USB transmit data byte number set register 1 USB PID control register 0 EPOPID Address 23 16 b7 b6 64 b3 b2 bl bO b5 C eme T 0 0 0 0 RD WR RD WR Initial value 0 Endpoint 0 enable 0 Endpoint 0 invalid Ena Set Use flag 1 Endpoint 0 valid ble Clea Unexpected IN or OUT transaction can be ignored by clearing to this flag to 0 SETUP transaction cannot be ignored it is always valid Endpoint 0 PID selection 1x IN token interrupt of DATA 0 1 is valid flag OUT STALL 01Xx STALL handshake is valid for IN token 00XX NAK handshake is valid for IN token Endpoint 0 selection XXX1 STALL handshake i lid for OUT flag OUT ACK ins andshake is valid for Endpoint 0 PID selection XX10 ACK handshake is valid for OUT token flag IN STALL XX00 NAK handshake is valid for OUT token Endpoint 0 PID selection ag IN DATAO 1 DPIDO and SPIDOI are used to control the response for IN token DPIDO is used with the token interrupt enable flag TKNE DPIDO is cleared to 0 automatically by hardware when ACK is received SPIDOO and APIDO are used to control the response for OUT token When DPIDO is changed during token packet the changed value is valid after end of token X it can be set to 0 or 1 Fig 3 5 17 Structure of USB PID control register 0 Rev 3 00 Oct 23 2006 page 41 of 70 5 5 REJ09B0178
144. Vcc pin Fig 3 4 6 Bypass capacitor across the Vss line and the Vcc line Rev 3 00 Oct 23 2006 29 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 4 Countermeasures against noise 3 4 3 Wiring to analog input pins Connect an approximately 100 to 1 resistor to an analog signal line which is connected to an analog input pin in series Besides connect the resistor to the microcomputer as close as possible Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin Besides connect the capacitor to the 55 as close as possible Also connect the capacitor across the analog input pin and the Vss pin at equal length Reason Signals which is input in an analog input pin such as an A D converter comparator input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog input pin is longer necessarily This long wiring functions as an antenna which feeds noise into the microcomputer which causes noise to an analog input pin If a capacitor between an analog input pin and the 55 pin is grounded at a position far away from the Vss pin noise on the GND line may enter a microcomputer through the capacitor Note Microcomputer Analog input pin Note The resistor is used for dividing resistance with a thermistor Fig 3 4 7 Analog
145. ack depends on RAM size Espe cially be careful that the RAM area varies in Mask ROM version One Time PROM version and Emulator MCU NOTES ON USE Handling of Power Source Pin In order to avoid a latch up occurrence connect a capacitor suitable for high frequencies as bypass capacitor between power source pin Vcc pin and GND pin Vss pin Besides connect the capacitor to as close as possible For bypass capacitor which should not be lo cated too far from the pins to be connected a ceramic or electrolytic capacitor of 1 0 uF is recommended Handling of USBVREFOUT Pin In order to prevent the instability of the USBVREFOUT output due to external noise connect a capacitor as bypass capacitor between USBVREFOUT pin and GND Vss pin Besides connect the ca pacitor to as close as possible For bypass capacitor a ceramic or electrolytic capacitor of 0 22 uF is recommended USB Communication applications requiring high reliability we recommend providing the system with protective measures such as USB function initial ization by software or USB reset by the host to prevent USB com munication from being terminated unexpectedly for example due to external causes such as noise When USB suspend mode with TTL level on P10 P12 P13 input level selection bit bit 3 of address 1716 set to 1 suspend current as Icc might be greater than 300 as a spec Countermeasure There are two countermeasures by softwar
146. alid at falling level for port PO at input Timer 1 6 FFF316 FFF216 At timer 1 underflow STP release timer underflow Timer 2 7 FFF116 FFFO16 At timer 2 underflow Serial 1 02 At completion of transmit receive shift CNTRo 8 FFEF16 FFEE16 At detection of either rising or falling edge External interrupt active edge of CNTRo input selectable A D conversion At completion of A D conversion BRK instruction 9 1 At BRK instruction execution Non maskable software interrupt Note 1 Vector addressed contain internal jump destination addresses 2 Reset function in the same way as an interrupt with the highest priority Rev 3 00 Oct 23 2006 page 20 of 55 REJ09B0178 0300 RENESAS HARDWARE 7534 Group FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag 1 BRK instruction Interrupt request Reset Fig 18 Interrupt control bO Interrupt edge selection register INTEDGE address 003A16 INTO interrupt edge selection bit 0 Falling edge active 1 Rising edge active INT1 interrupt edge selection bit 0 Falling edge active 1 Rising edge active Not used returns 0 when read Serial 1 01 or INT1 interrupt selection bit 0 Serial 1 01 1 INT1 Timer X or key on wake up interrupt selection bit 0 Timer X 1 Key on wake up Timer 2 or serial 1 2 interrupt selection bit 0 Tim
147. annel Selector The channel selector selects one of ports P27 AN7 to P20 ANo and inputs the voltage to the comparator Comparator and control circuit The comparator and control circuit compares an analog input volt age with the comparison voltage and stores its result into the A D conversion register When A D conversion is completed the control circuit sets the AD conversion completion bit and the AD interrupt request bit to 1 Because the comparator is constructed linked to a capacitor set f XIN to 500 kHz or more during A D conversion A D control register ADCON address 003416 Analog input pin selection bits 000 P20 ANo 001 P21 AN1 010 P22 AN2 011 P23 AN3 100 P24 AN4 101 P25 AN5 110 26 6 111 P27 AN7 Not used returns 0 when read AD conversion completion bit 0 Conversion in progress 1 Conversion completed Not used returns 0 when read Fig 37 Structure of A D control register Read 8 bit Read out only address 003516 b7 Read 10 bit read out in order address 003616 003516 b7 b0 emos 67 60 e ofa High order 6 bit of address 003616 returns 0 when read Fig 38 Structure of A D conversion register b7 60 A D control register Address 003416 3 A D control circuit P20 ANo P21 AN1 O A D int
148. anted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document b
149. apons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability
150. at Control transfer Not deal with the host which performs the Control transfer in parallel to plural device Connectable to the host which performs the Con trol transfer in parallel to plural device D D transceiver circuit USB function can be used only at the condition of CL 150 pF to 350 pF Deal with the following Low Speed USB2 0 speci fication CL 200 pF to 450 pF Trise and Tfall 75 ns to 300 ns Tr Tf 80 96 to 125 96 Cross over Voltage 1 3 V to 2 0 V Power dissipation at Suspend Rating is Max 300 uA not including the output cur rent of USBVREFOUT Rating is Max 300 including the output current of USBVREFOUT by low power dissipation of D D input circuit and 3 3 V regulator STALL in Status stage ACK is returned once to OUT DATAO to be valid in Status stage STALL is set automaticcally by hardware when OUT DATAO is received in Status stage 6 bit decode of SYNC field SYNC is detected only when 8 bit full code 8016 is complete DIFFERENCES AMONG 32 PIN 36 PIN AND 42 PIN The 7534 Group has three package types and each of the number of I O ports are different Accordingly when the pins which have the function except a port function are eliminated be careful that the functions are also eliminated Table 14 Differences among 32 pin 36 pin and 42 pin SYNC is detected only the low order 6 bits even if the high order 2 bits are corrupted
151. ation RxEP Data written and transmitted 2 bytes Transmit buffer empty fla TARDY ee ee mcm OO O 1 CRC error occurs False EOP error occurs PID error occurs False EOP error occurs CRCE FEOPE PIDE FEOPE Summing error flag E mE cabe SUME Notes 1 The data number of PID is 2 bytes in this example 2 Endpoint ENDP is 0 in this example 3 The dot line on SUME shows the timing of each error occur Fig 2 4 12 Timing chart of the transaction according to each token Rev 3 00 Oct 23 2006 63 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 3 Interrupt processing In 7534 Group the interrupt related to the USB communication processes 7 sources 2 jump destination Accordingly determine the interrupt source and execute the processing after executing the interrupt processing Moreover control the USB function and the interrupt source which has been enabled before interrupt is enabled The interrupt jump destination and the source are shown as follows IN token interrupt IN token endpoint 0 and IN token endpoint 1 OUT token interrupt OUT token SETUP token Reset Suspend and Resume The determination processing at the OUT token in figure by the interrupt and the setting of a related register when using the interrupt of the OUT token is shown in Figure 2 4 13 The determination processing at the IN token endpoint 0 in figure
152. ble input level Whether a built in pull up resistor is to be used or not can be determined by program P10 RxD D port 7 bit I O port Serial 1 function pin P11 TxD D direction register allows each pin to be individually programmed 12 5 as input or output Serial 1 02 function pin P13 SDATA CMOS 3 state output structure at CMOS compatible input level P14 CNTRo CMOS TTL level can be switched for P10 P12 P13 Timer X function pin When using the USB function input level of ports P10 and P11 becomes USB input level and output level of them becomes P15 P16 USB output level 2 port P2 8 bit I O port having almost the same function as Input pins for A D converter P27 AN7 CMOS 3 state output structure at CMOS compatible input level P30 P35 port P3 8 bit I O port direction register allows each pin to be individually programmed as either input or output CMOS 3 state output structure at CMOS compatible input level CMOS TTL level be switched for P36 P37 P30 to P36 can output a large current for driving LED P36 INT1 Whether a built in pull up resistor is to be used or not can be Interrupt input pins P37 INTo determined by program P40 P41 port 2 bit I O port direction register allows each pin to be individually programmed as either input or output Rev 3 00 23 2006 8 of 55 REJ09BO01 78 0300 RENESAS 7534
153. carry the C flag must be initialized to 0 before each calculation To check for a borrow the C flag must be initialized to 1 before each calculation Set D flag to 1 ADC or SBC instruction NOP instruction SEC CLC or CLD instruction Fig 3 3 9 Status flag at decimal calculations 3 JMP instruction When using the JMP instruction in indirect addressing mode do not specify the last address on a page as an indirect address 3 3 8 Programming and test of built in PROM version As for in the One Time PROM version shipped in blank its built in PROM can be read or programmed with a general purpose PROM programmer using a special programming adapter The programming test and screening for PROM of the One Time PROM version shipped in blank are not performed in the assembly process and the following processes To ensure reliability after programming performing programming and test according to the Figure 3 3 9 before actual use are recommended Programming with PROM programmer Screening Caution Leave at 150 for 40 hours Verification with PROM programmer Caution The screening temperature is far higher than the storage temperature Never expose to 150 C Functional check in target device exceeding 100 hours Fig 3 3 10 Programming and testing of One Time PROM version Rev 3 00 Oct 23 2006 page 22 of 70 1324 NESAS REJO9B01 78 0300 APPENDIX 7534 Group 3 3 Notes on use 3 3 9 Notes on b
154. ccumulator or processor status register 11 Table 4 Set and clear instructions of each bit of processor status register 12 Table 5 VO port function table rire u uu LASER ERRARE 17 Table 6 Interrupt vector address and priority 20 Table 7 Relation of the width of SEO and the state of the device 33 Table 8 Special programming adapter 020 1 4141 0 0000000 0000 00000000000000000 43 Table 9 Interrupt sources vector addresses and interrupt 44 Table 10 Change of A D conversion register during A D conversion 46 Table 11 Stop mode 8 ederent dde EXE 48 Table 12 Walt mode State tuens RE ha ce 49 Table 13 Description of improved USB function for 7534 Group 50 Table 14 Differences among 32 pin 36 pin and 42 50 Table 15 Differences among 32 pin 36 and 42 pin SFR 51 CHAPTER 2 APPLICATION Table 2 1 1 Handling of unused pins 7 Table 2 2 1 CNTRO active edge switch bit function eene 13 Table 2 3 1 Setting example of baud rate generator BRG and transfer bit rate values 44 Table 2
155. ce equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
156. cept an on chip oscillator selection bits bits 6 and 7 CPUM Select one of 1 1 1 2 and 1 8 Y Main routine Note After releasing reset the operation starts by starting an on chip oscillator automatically Do not use an on chip oscillator at ordinary operation Fig 3 3 11 Switching method of CPU mode register 3 3 12 Notes on using 32 pin version Do not change the P35 P36 pull up control bit of the pull up control register from the initial value 1 Do not write to 1 to the serial 1 or INT1 interrupt selection bit of the interrupt edge selection register 3 3 13 Electric characteristic differences among mask ROM and One PROM version MCUs There are differences in electric characteristics operation margin noise immunity and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing processes When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version perform sufficient evaluations for the commercial samples of the mask ROM version 3 3 14 Note on power source voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions the microcomputer does not operate normally and may perform unstable operation In a system where the power source voltage drops slowly when the power source voltage drops or
157. ck of CNVss pin has no operational inter ference even if it is connected via a resistor Electric Characteristic Differences Among Mask ROM and One PROM Version MCUs There are differences in electric characteristics operation margin noise immunity and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufac turing processes When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version per form sufficient evaluations for the commercial samples of the mask ROM version Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions the microcomputer does not operate normally and may perform unstable operation In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation Note on A D Converter Method to stabilize A D Converter is described below A D conversion accuracy could be affected Bus Powered USB devices while the communicating Figure 50 shows the method to stabilize A D conversion accu racy inserting a capacitor between Vref and Vss 1 Power supplied by U
158. conversion Operating Conversion is Program counter continued if the WIT instruction is executed during conversion Serial 1 02 At selecting internal synchronous clock Operating At selecting external synchronous clock Operating USB Operating 2 Wait mode release Wait mode is released by reset input or interrupt occurrence In the wait mode since the oscillation is continued the instruction is executed after the system is released from the wait mode The interrupt sources which can be used for return from wait mode are shown below INTO INT1 Timer Serial 1 2 A D conversion Key on wakeup USB function UART Processor status register When the above interrupt sources are used for return from wait mode execute the WIT instruction after the following are set in order to enable the using interrupts Clear the interupt request bit of the interrupt using for return to 0 Q Set the interupt enable bit of the interrupt using for return to 41 Clear the interrupt disable flag to 0 Rev 3 00 Oct23 2006 50 of 55 REJ09B0178 0300 7tENESAS HARDWARE DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP 7534 Group DIFFERENCES AMONG 32 36 PIN AND 42 PIN DESCRIPTION OF IMPROVED USB FUNCTION FOR 7534 GROUP Table 13 Description of improved USB function for 7534 Group No Parameter 7532 7536 Group 7534 Group 1 Response
159. ction register SFR Rev 3 00 Oct 23 2006 page 15 of 55 5 5 REJ09B0178 0300 7534 Ports Direction registers The ports have direction registers which determine the input out put direction of each pin Each bit in a direction register corresponds to individual pin and each pin can be set to be input or output When 1 is set to the bit corresponding to a pin this pin becomes an output port When 0 is set to the bit the pin becomes an input port When data is read from a pin set to output not the value of the pin itself but the value of port latch is read Pins set to input are floating and permit reading pin values If a pin set to input is written to only the port latch is written to and the pin remains floating HARDWARE FUNCTIONAL DESCRIPTION Pull up control PULL By setting the pull up control register address 001616 ports PO and P3 can exert pull up control by program However pins set to output are disconnected from this control and cannot exert pull up control Port P1P3 control P1P3C By setting the port P1P3 control register address 001716 a CMOS input level or a TTL input level can be selected for ports P10 P12 P13 P36 and P37 by program Then as for the 36 pin version set 1 to each bit 6 of the port P3 direction register and port P3 register As for the 32 pin version set 1 to respective bits 5 6 7 of the port P3 direction reg
160. d by a relative address If N is 1 the next instruction is executed PC lt offset This instruction branches to the appointed ad dress The branch address is specified by a relative address B lt 1 PC 2 M S PCH 5 5 1 M S PCL 5 5 1 M S PS 5 5 1 1 lt 1 PCL lt ADL PCH lt ADH When the BRK instruction is executed the CPU pushes the current PC contents onto the stack The BADRS designated in the interrupt vector table is stored into the PC BVC Note 4 This instruction takes a branch to the ap pointed address if V is 0 The branch address is specified by a relative address If V is 1 the next instruction is executed BVS Note 4 This instruction takes a branch to the ap pointed address when V is 1 The branch address is specified by a relative address When V is 0 the next instruction is executed CLB Ai or Mi 0 This instruction clears the designated bit i of A or M CLC This instruction clears C CLD This instruction clears D CLI This instruction clears l CLT This instruction clears T CLV This instruction clears V CMP Note 3 When 0 this instruction subtracts the con tents of M from the contents of A The result is not stored and the contents of A or M are not modified When T 1 the CMP subtracts the contents of M from the contents of M X The result is not stored and t
161. d with CS pin Figure 2 3 12 shows connection examples with a peripheral IC equipped with the CS pin Each case uses the clock synchronous serial I O mode 1 Only transmission 2 Transmission and Reception 7534 Group Peripheral IC 7534 Group OSD controller etc Peripheral IC 1 E2PROM etc 3 Connection of plural IC Use the peripheral IC of which OUT has an N channel open drain output structure and which enters a high impedance state while receiving 7534 Group Peripheral IC1 1 data Note Port means an output port controlled by software CLK IN OUT Peripheral IC2 1 Fig 2 3 12 Serial connection examples 1 Rev 3 00 Oct 23 2006 page 35 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O 2 Connection with microcomputer Figure 2 3 13 shows connection examples with another microcomputer 1 Selecting internal clock 2 Selecting external clock 7534 Group Microcomputer 7534 Group Microcomputer 3 In UART using serial 1 7534 Group Microcomputer Fig 2 3 13 Serial I O connection examples 2 Rev 3 00 Oct 23 2006 page 36 of 78 7tENESAS 09 0178 0300 APPLICATION 7534 Group 2 3 Serial I O 2 3 4 Serial I O transfer data format The clock synchronous or the clock asynchronous UART be selected as the serial I O Figure 2 3 14 shows the serial I O transfer data format 1ST 8DATA 1SP C
162. ddresses in the zero page area Access to this area with only 2 bytes is possible in the zero page addressing mode Special page The 256 bytes from addresses FF0016 to FFFF 16 are called the spe cial page area The special page addressing mode can be used to specify memory addresses in the special page area Access to this area with only 2 bytes is possible in the special page addressing mode 000016 SFR area 010016 Zero page XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area 128 bytes ZZZZ16 FF0016 16 Interrupt vector area FFFE16 FFFF46 Reserved ROM area Special page Rev 3 00 23 2006 page 14 of 55 REJ09B0178 0300 RENESAS HARDWARE 7534 Group FUNCTIONAL DESCRIPTION 000016 Port PO PO 002016 USB interrupt control register USBICON 000116 Port PO direction register 002116 USB transmit data byte number set register 0 000216 Port P1 P1 002216 USB transmit data byte number set register 1 00031e Port P1 direction register 002316 USBPID control register 0 EPOPID 000416 Port P2 P2 002416 USBPID control register 1 EP1PID 000516 Port P2 direction register 002516 USB address register USBA 000616 Port 002616 USB sequence bit initialization register INISQ1 000716 Port P3 direction register 002716 USB control register USBCON 000816 Port P4 P4 002816 Prescaler 12 PRE12 00
163. e the Z V N flags are not valid After reset the Interrupt disable 1 flag is set to 1 but all other flags are undefined Since the Index X mode T and Decimal mode D flags directly affect arithmetic operations they should be initialized in the beginning of a program 1 Carry flag C The C flag contains a carry or borrow generated by the arithmetic logic unit ALU immediately after an arithmetic operation It can also be changed by a shift or rotate instruction 2 Zero flag Z The Z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 and cleared if the result is anything other than 0 3 Interrupt disable flag 1 The flag disables all interrupts except for the interrupt generated by the BRK instruction Interrupts are disabled when the flag is 1 When an interrupt occurs this flag is automatically set to 1 to prevent other interrupts from interfering until the current interrupt is serviced 4 Decimal mode flag D The D flag determines whether additions and subtractions are executed in binary or decimal Binary arithmetic is executed when this flag is 0 decimal arithmetic is executed when it is 1 Decimal correction is automatic in decimal mode Only the ADC and SBC instructions can be used for decimal arithmetic HARDWARE FUNCTIONAL DESCRIPTION 5 Break flag B The B flag is used to indicate that the current interrupt was generated by
164. e contents of and M are transferred to the ALU which performs a bit wise Exclusive OR and stores the results in M X The contents of A remain unchanged but status flags are changed M X represents the contents of memory where is indicated by X WhenT 1 M X VM A lt A 1or This instruction adds one to the contents of A lt 41 1 This instruction adds one to the contents of X Yc Y 1 This instruction adds one to the contents of Y If addressing mode is ABS This instruction jumps to the address desig PCL lt ADL PCH lt ADH If addressing mode is IND PCL lt ADL PCH lt M ADL 1 If addressing mode is ZP IND PCL 00 ADL PCH lt 00 ADL 1 nated by the following three addressing modes Absolute Indirect Absolute Zero Page Indirect Absolute M S PCH 56 5 1 M S PCL This instruction stores the contents of the PC in the stack then jumps to the address desig nated by the following addressing modes 5 5 1 Absolute After executing the above Special Page if addressing mode is ABS Zero Page Indirect Absolute PCL lt ADL PCH ADH if addressing mode is SP PCL lt ADL PCH lt FF If addressing mode is ZP IND PCL 00 ADL PCH 00 ADL 1 When T 0 When T 0 this instruction transfers the con tents M to A When T 1 When T 1 this instruct
165. e to avoid it as follows 1 Change from TTL input level to CMOS input level for P10 P12 P13 port input 2 Change from TTL input level to CMOS input level before STP instruction in suspend routine then after RESUME or Remote wake up interrupt return to TTL input level from CMOS input level That is shown in Figure 49 Rev 3 00 Oct 23 2006 page 42 of 55 REJ09B0178 0300 RENESAS 7534 HARDWARE DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD SUSPEND Routine d Configuration to CMOS input level for Pto P12 P13 input level trout nier s STP input level RESUME Routine Config level x for P1o el 4 xxxxx1xxe Configuration to TTL input level for P10 P12 P13 input level uration to TTL input P12 P13 input levi 2 Remote wake up Routine Configuration to TTL input level for Pio P12 P13 input level 46 xxxxx1xxz Configuration to TTL input level for P10 P12 P13 input level Fig 49 Countermeasure 2 by software One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low ohmic resistance since it has the multiplexed function to be a programmable power source pin VPP pin as well To improve the noise reduction connect a track between CNVss pin and Vss pin with 1 to 10 kQ resistance The mask ROM version tra
166. en Vo to V1022 Analog voltage veer Zero transition voltage Fig 3 2 14 Definition of A D conversion accuracy Vn Analog input voltage when the output data changes from n to n 1 n 0 to 1022 e 1 LSB at relative accuracy gt _Vest Vor V 1022 1 LSB at absolute accuracy 024 V Rev 3 00 Oct23 2006 page 15 of 70 5 5 09 0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics M37534M4 XXXFP A D CONVERTER STEP WIDTH MEASUREMENT Vcc 5 V Zero transition voltage 6 714 mV 5 V Full scale transition voltage 4994 812 mV 6 MHz Differential non linearity error 1 373 mV 0 281 LSB Temp 25 Non linearity error 5 201 mV 1 066 LSB CPU mode double speed mode 1LSB WIDTH Fig 3 2 15 A D conversion typical characteristic example Rev 3 00 Oct23 2006 16 of 70 1320 NE SAS REJO9B01 78 0300 APPENDIX 7534 Group 3 3 Notes on use 3 3 Notes on use 3 3 1 Notes on interrupts 1 Switching external interrupt detection edge For the products able to switch the external interrupt detection edge switch it as the following sequence Clear an interrupt enable bit to 0 interrupt disabled Switch the detection edge Clear an interrupt request bit to O no interrupt request issued L Set the interrupt enable bit to 1 interrupt enabled Fig 3 3 1 Sequence of sw
167. er reset initialize flags which affect program execution In particular it is essential to initialize the T flag and the D flag because of their effect on calculations Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the pre vious contents For executing the instruction for the changed con tents execute one instruction before executing the BBC or BBS in struction Decimal Calculations For calculations in decimal notation set the decimal mode flag D to 1 then execute the ADC instruction or SBC instruction In this case execute SEC instruction CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction the decimal mode the values of the negative V overflow and Z zero flags are invalid Timers When n 0 to 255 is written to a timer latch the frequency division ratio is 1 n 1 When a count source of timer X is switched stop a count of timer X Ports The values of the port direction registers cannot be read That is it is impossible to use the LDA instruction memory opera tion instruction when the T flag is 1 addressing mode using di rection register values as qualifiers and bit test instructions such as BBC and BBS It is also impossible to use bit operation instructions such as C
168. er 2 1 Serial 1 02 or AD converter interrupt selection bit 0 CNTRO 1 AD converter Interrupt request register 1 IREQ1 address 003C16 UART receive USB IN token interrupt request bit UART transmit USB SETUP OUT token Reset Suspend Resume INT1 interrupt request bit INTO interrupt request bit Timer X or key on wake up interrupt request bit Timer 1 interrupt request bit Timer 2 or serial l O2 interrupt request bit CNTRo or AD converter interrupt request bit Not used returns 0 when read 0 No interrupt request issued 1 Interrupt request issued bo Interrupt control register 1 ICON1 address 003E16 UART receive USB IN token interrupt enable bit UART transmit USB SETUP OUT token Reset Suspend Resume INT1 interrupt enable bit INTO interrupt enable bit Timer X or key on wake up interrupt enable bit Timer 1 interrupt enable bit Timer 2 or serial l O2 interrupt enable bit CNTRo or AD converter interrupt enable bit Not used returns 0 when read Do not write 1 to this bit 0 Interrupts disabled 1 Interrupts enabled Fig 19 Structure of Interrupt related registers Rev 3 00 Oct 23 2006 21 of 55 5 5 REJ09B0178 0300 7534 Group HARDWARE FUNCTIONAL DESCRIPTION Key Input Interrupt Key On Wake Up key on wake up interrupt request is
169. errupt request P22 AN2 O P23 AN3 P24 AN4 O P25 AN5 O P26 AN6 O P27 AN7 Comparator 2 20 c c s Fig 39 Block diagram of A D converter A D conversion register high order A D conversion register low order Address 003516 Resistor ladder Le 214 Address 003616 10 Rev 3 00 Oct 23 2006 page 36 of 55 REJ09B01 78 0300 RENESAS 7534 HARDWARE FUNCTIONAL DESCRIPTION Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway The watchdog timer consists of an 8 bit watchdog timer H and an 8 bit watchdog timer L being a 16 bit counter Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register address 003916 is not set after reset Writing an optional value to the watchdog timer control register address 003916 causes the watchdog timer to start to count down When the watchdog timer H underflows an internal reset occurs Accordingly it is programmed that the watchdog timer control register address 003916 can be set before an underflow occurs When the watchdog timer control register address 003916 is read the values of the high order 6 bit of the watchdog timer H STP in struction disable bit and watchdog timer H count source selection bit are read Initial value of watchdog t
170. es against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should
171. essing To Reset Supend Resume processing No token lt gt Interrupt source token Token USBIR2 XXXXXXX 2 Interrupt by token if 2 1 OUT token USBIR2 X XXXXXX 2 Interrupt by OUT token if 2 1 To Setup processing Read receive data Max 8 bytes in 1 interrupt processing Data receive executed Communication error occur USBSTS Error No error can be determined by SUME of bit 6 Data toggle es TRSYNC XXXXXXX 2 Toggle normally if 2 1 Set handshake In normal receive handshake is set to ACK A When communication error or data doggle error occur handshake is set to NAK or STALL according to the contents B In normal receive data is stored C When communication error or data doggle error occur received data in this time is canceled D Store this receive data Notes 1 In this figure only USB in interrupt processing is described Note that the storing stack etc is not described 2 Data shown by in program description expresses determination or data setting Fig 2 4 13 USB interrupt processing example OUT token Rev 3 00 Oct 23 2006 page 65 of 78 REJ09B01 78 0300 5 5 APPLICATION 7534 Group 2 4 USB 0X Not used here Set it to 0 or 1 arbitrary Flow chart Program description USBA X00000002 Initial USB address 0 Set USB communication SIO1CON 11 2 Set I O port to USB mode USBCON 1
172. esumue invalid Ena Set Use enable 1 Resume valid ble Clear Token interrupt 0 Token invalid Ena Set Use enable 1 Token valid ble Clear USB enable flag 0 USB invalid Ena Set Use 1 USB valid ble Clear The internal state can be initialized by clearing this flag to 0 The initial values of registers are as follows USB status register address 19 16 0116 USB data toggle synchronization register address 1D 16 7F 16 USB interrupt source discrimination register 1 address 1E 16 7F 16 Bits 7 6 and 2 of USB interrupt source discrimination register 2 address 1F 16 00xxx0xx2 Fig 3 5 14 Structure of USB interrupt control register Rev 3 00 23 2006 40 of 70 1320 NE SAS REJO9B01 78 0300 APPENDIX 7534 Group 3 5 List of registers Refer to Figure 2 4 6 Description of register structure for registers relevant to USB USB transmit data byte number set register 0 EPOBYTE Address 21 16 67 b6 b5 b4 b3 62 61 00 o o ___ RD WR RD WR Initial value 0 Set the number of data byte for Set Use transmitting with endpoint 0 ble Clear Fig 3 5 15 Structure of USB transmit data byte number set register 0 USB transmit data byte number set register 1 Address 22 16 67 b6 65 b4 63 62 bi 00 X sev RD WR RD WR Initial value 0 Set the number of data byte for Ena Set
173. et a division ratio so that the underflow output period of the timer X can be 250 us 7534 Group Fig 2 2 14 Peripheral circuit example Timer X count source selection bit Prescaler X Timer X PiPiPi TA f XIN 6 00 MHz 1 16 1 94 gt CNTRo Fig 2 2 15 Timers connection and setting of division ratios Rev 3 00 23 2006 20 of 78 1320 NE SAS REJO9B01 78 0300 APPLICATION 7534 Group 2 2 Timer Timer count source set register address 2E 16 b7 ress fo L Timer X count source f XiN 16 Timer X mode register address 2B 16 b7 60 1 pejor Timer X operating mode Pulse output mode active edge switch Output starting at H level Timer X count Stop Clear to 0 when starting count Timer X address 2D 6 b7 60 93 gt Set division ratio 1 Prescaler X address 2C 16 Interrupt control register 1 address 16 b7 50 fol Timer interrupt Disabled Fig 2 2 16 Relevant registers setting Rev 3 00 Oct 23 2006 page 21 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer RESET Initialization X This bit not used here Set it to 0 or 1 arbitrary 1 address 0216 bit4 lt 1 P1D address 0316 lt XXX1XXXX2 TCSS address 2E Timer X count source 16 ICON1 address SE t6 Timer X interrupt disabled TM address 2
174. flag cleared lt SIO2CON address 3016 bit7 Judgment of completion of one byte reception Wait for half cycle of clock Read out received data from SIO2 SIO2 address 3116 Dummy data Transmit receive shift completion flag cleared lt SIO2CON address 3016 bit7 Judgment of completion of one byte reception 1 Wait for half cycle of shift clock Read out received data from SIO2 Fig 2 3 21 Control procedure of reception side Rev 3 00 23 2006 page 42 of 78 1320 NE SAS REJO9B01 78 0300 APPLICATION 7534 Group 2 3 Serial I O 2 Communication using asynchronous serial I O UART transmit receive Outline 2 byte data is transmitted and received using the clock asynchronous serial I O Port 0 is used for communication control Figure 2 3 22 shows a connection diagram and Figure 2 3 23 shows a timing chart Transmission side Reception side gt 7534 Group 7534 Group Fig 2 3 22 Connection diagram Specifications The Serial 1 01 asynchronous serial I O is used Transfer bit rate 9600 bps f Xin 4 9152 MHz divided by 512 Communication control using port 0 Port POooutput level is controlled by software 2 byte data is transferred from the transmission side to the reception side at 10 ms intervals which the timer generates 10 ms Fig 2 3 23 Timing chart Rev 3 00 Oct 23 2006 page 43 of 78 5 5
175. g 44 Internal status of microcomputer at reset USB data toggle synchronization register USB interrupt source discrimination register 1 USB interrupt source discrimination register 2 USB transmit data byte number set register 0 USB transmit data byte number set register 1 USB sequence bit initialization register Address Register contents 000116 0016 000316 000516 000716 000916 001616 001916 001A16 001 16 001016 001 16 001 16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002 16 002816 002616 002016 002 16 003016 003416 003816 003916 003A16 003 16 003C16 003 16 5 X x 1 PCL Contents of address FFFD16 Contents of address FFFC16 Note X Undefined Rev 3 00 Oct 23 2006 39 of 55 REJ09B0178 0300 5 5 7534 Group HARDWARE FUNCTIONAL DESCRIPTION Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator be tween XIN and Xour Use the circuit constants in accordance with the resonator manufacturer s recommended values No external resistor is needed between XIN and Xour since a feed back resistor exists on
176. g mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X modified arithmetic mode flag Overflow flag Negative flag o lt x cc gt 1 UU oo M ADH ADL M 00 ADL Ai Mi OP n Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high order bits of program counter 8 low order bits of program counter 8 high order bits of address 8 low order bits of address FF in Hexadecimal notation Immediate value Zero page address Memory specified by address designation of any ad dressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL in ADH is 8 high order bits and ADL is 8 low or der bits Contents of address indicated by zero page ADL Bit i i 0 to 7 of accumulator Bit i i 0 to 7 of memory Opcode Number of cycles Number of bytes Rev 3 00 Oct 23 2006 page 66 of 7
177. g to VPP pin of One Time PROM version Connect an approximately 5 kQ resistor to the VPP pin the shortest possible in series and also to the Vss pin When not connecting the resistor make the length of wiring between the VPP pin and the Vss pin the shortest possible Note Even when a circuit which included an approximately 5 kQ resistor is used in the Mask ROM version the microcomputer operates correctly Reason The VPP pin of the One Time PROM is the power source input pin for the built in PROM When programming in the built in PROM the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM Because of this noise can enter easily If noise enters the VPP pin abnormal instruction codes or data are read from the built in PROM which may cause a program runaway Approximately CNVss VPP Vss In the shortest distance Fig 3 4 5 Wiring for the VPP pin of the One Time PROM 3 4 2 Connection of bypass capacitor across Vss line and Vcc line Connect an approximately 1 0 uF bypass capacitor across the Vss line and the Vcc line as follows Connect a bypass capacitor across the 55 and the Vcc at equal length Connect a bypass capacitor across the VSS and the Vcc pin with the shortest possible wiring Use lines with a larger diameter than other signal lines for Vss line and Vcc line e Connect the power source wiring via a bypass capacitor to the Vss and the
178. ge Selection Bit If the Stack Page Selec tion Bit is O then the RAM in the zero page is used as the stack area If the Stack Page Selection Bit is 1 then RAM in page 1 is used as the stack area The Stack Page Selection Bit is located in the SFR area in the zero page Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack ad dress are fixed The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 9 Program counter PC The program counter is a 16 bit counter consisting of two 8 bit regis ters PCH and PCL It is used to indicate the address of the next instruc tion to be executed 50 Accumulator 50 Index Register X 50 Y Index Register 50 5 Stack Pointer b15 b7 00 PCL Program Counter b7 bO NIVITI BIDI IIZIC Processor Status Register PS Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig 8 740 Family CPU register structure Rev 3 00 Oct 23 2006 page 10 of 55 REJ09B0178 0300 7tENESAS HARDWARE 7534 Group FUNCTIONAL DESCRIPTION On going Routine Interrupt request Note Execute JSR o 2 a
179. ge Vcc V Fig 3 2 6 characteristic example A D conversion executed not executed f Xin 6MHz in double speed mode Rev 3 00 Oct 23 2006 page 10 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics 3 2 2 VOH IOH characteristic example Measuring condition Ta 25 C characteristics of P channel normal port same charactersistics pins POo P07 10 16 20 27 P3o P37 P40 lt T 9 o 5 3 Q I H output voltage V Fig 3 2 7 VOH IOH characteristic example of P channel Ta 25 C normal port Measuring condition Ta 85 C characteristics of P channel normal port same charactersistics pins 0 0 10 16 20 27 P3o P37 4 P41 H output current mA H output voltage V Fig 3 2 8 VOH IOH characteristic example of P channel Ta 85 C normal port Rev 3 00 Oct 23 2006 page 11 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics Measuring condition Ta 25 C Vor lor characteristics of N channel normal port same charactersistics pins 0 0 10 16 20 27 P37 P40 P41 x 2 2 2 2 o s L output voltage V Fig 3 2 9 Vor loL characteristic example of N channel Ta 25 C Normal port Measu
180. ge from TTL input level to CMOS input level before STP instruction in suspend routine then after RESUME or Remote wake up interrupt return to TTL input level from CMOS input level That is shown in Figure 2 4 21 SUSPEND Routine Configuration to CMOS input level for P1o P12 P13 input level amp 0 Configuration to CMOS input level for P10 P12 P13 input level RESUME Routine Configuration to TTL input level for P1o P12 P13 input level lt a xxxxx1xxe Configuration to TTL input level for P10 P12 P13 input level Remote wake up Routine Configuration to TTL input level for 10 P12 P13 input level 4 Configuration to TTL input level for P10 P12 P13 input level Fig 2 4 21 Countermeasure 2 by software Rev 3 00 Oct 23 2006 page 70 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 5 A D converter 2 5 A D converter This paragraph explains the registers setting method and the notes relevant to the A D converter 2 5 1 Memory map 003416 A D control register ADCON 003516 A D conversion register low order ADL 003616 A D conversion register high order ADH 003A16 Interrupt edge selection register INTEDGE 003 16 Interrupt request register 1 IREQ1 003E16 Interrupt control register 1 Fig 2 5 1 Memory map of registers relevant to A D converter 2
181. generated by applying L level to any pin of port PO that has been set to input mode In other words it is generated when the AND of input level goes from 1 to 0 An example of using a key input interrupt is shown in Fig ure 20 where an interrupt request is generated by pressing one of the keys provided as an active low key matrix which uses ports 0 to as input ports P07 output Port PXx L level output PULL register bit 3 0 Port P07 Direction register 1 Port P07 latch e Falling edge 06 output PULL register bit 3 0 I detection Key input interrupt request Port P06 Direction register 1 Port P06 latch Falling edge P05 output PULL register bit 3 0 1 latch I detection Port P05 Direction register 1 Port P05 Falling edge P04 output PULL register bit 3 0 1 detection gt Port 4 Direction register 1 P03 input PULL register bit 2 1 a Port P04 Falling edge DE latch Port Direction register 0 Port latch Falling edge 2 detection input PULL register bit 2 1 IT
182. gister Rev 3 00 Oct 23 2006 page 4 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 1 port Interrupt request register 1 b7 b6 b5 64 b3 b2 bi bO Interrupt request register 1 IREQ1 Address 3C 16 B receive USBIN token No interrupt request issued interrupt request bit Interrupt request issued UART transmit USBSETUP 0 No interrupt request issued OUT token Reset Suspend 1 Interrupt request issued Resume INT1 interrupt request bit Note 1 INTo interrupt request bit No interrupt request issued Note 2 Interrupt request issued 3 Timer X or key on wake up x No interrupt request issued x interrupt request bit 1 Interrupt request issued 4 Timer 1 interrupt request bit 0 No interrupt request issued 1 Interrupt request issued 5 Timer 2 or serial 1 2 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued CNTRo or AD converter 0 No interrupt request issued interrupt request bit 1 Interrupt request issued 7 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 These bits can be cleared to 0 by program but cannot be set Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 2
183. he contents of X M and A are not modified M X represents the contents of memory where is indicated by X This instruction takes the one s complement of the contents of M and stores the result in M This instruction subtracts the contents of M from the contents of X The result is not stored and the contents of X and M are not modified This instruction subtracts the contents of M from the contents of Y The result is not stored and the contents of Y and M are not modified This instruction subtracts 1 from the contents of AorM Rev 3 00 Oct 23 2006 page 58 of 70 REJ09B0178 0300 7RENESAS APPENDIX 7534 Group 3 8 Machine instructions Addressing mode Processor status register Rev 3 00 Oct 23 2006 59 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 8 Machine instructions Addressing mode Function Details A A ZP JOP n 1 This instruction subtracts one from the current contents of X Yc Y 1 This instruction subtracts one from the current contents of Y When T 0 lt When T 0 this instruction transfers the con tents of the M and A to the ALU which performs a bit wise Exclusive OR and stores the result in A When T 1 th
184. he procedure shown in Figure 51 is recommended to verify programming Programming with PROM programmer Screening Caution 150 C for 40 hours Verification with PROM programmer Functional check in target device Caution The screening temperature is far higher than the storage temperature Never expose to 150 C exceeding 100 hours Fig 51 Programming and testing of One Time PROM version Rev 3 00 Oct 23 2006 44 of 55 RENESAS REJ09B0178 0300 7534 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT Interrupt 7534 group permits interrupts on the 14 sources for 42 pin version 13 sources for 36 pin version and 12 sources for 32 pin version It is vector interrupts with a fixed priority system Accordingly when two or more interrupt requests occur during the same sampling the higher priority interrupt is accepted first This priority is determined by hardware but variety of priority processing can be performed by software using an interrupt enable bit and an interrupt disable flag For interrupt sources vector addresses and interrupt priority refer to Table 9 Table 9 Interrupt sources vector addresses and interrupt priority iii i Vector addresses Note 1 nterrupt source iori i iti p Priority High order I OW Order Interrupt request generating conditions Remarks Reset Note 2 1 F
185. his bit 1 Shift of transmission completed Fig 2 3 17 Registers setting relevant to transmission side Rev 3 00 Oct 23 2006 page 39 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O Serial 2 register address 31 16 b7 5102 Set transmission data After confirming completion of the preceding transmission bit 5 of the interrupt request register 1 1 write data Fig 2 3 18 Transmission data setting of serial 1 02 Serial 1 02 control register address 30 16 b7 60 olo ofofi f Internal synchronous clock f X 64 SDATA pin Input port S DATA input LSB first External clock Transmit receive shift completion flag Fig 2 3 19 Registers setting relevant to reception side Rev 3 00 23 2006 40 of 78 134 NE SAS REJO9B01 78 0300 APPLICATION 7534 Group 2 3 Serial I O Figure 2 3 20 shows a control procedure of transmission side and Figure 2 3 21 shows a control procedure of reception side RESET X This bit is not used here Set it to 0 or 1 arbitrary NES Note When the internal clock is selected and the direction Initialization register of P13 SDATA is set to the input mode Note the SDATA pin is in a high impedance state P1D address 0316 XXXX11XX2 after the data transfer is completed SIO2CON address 3016 010010112 Serial 1 02 setting INTEDGE addres
186. ig 3 4 6 Bypass capacitor across the Vss line and the Voc line 29 Fig 3 4 7 Analog signal line and a resistor and a capacitor 30 Fig 3 4 8 Wiring for a large current 30 Fig 3 4 9 Wiring of signal lines where potential levels change frequently 31 Fig 3 4 10 Vss pattern on the underside of an oscillator 31 Fig 3 4 11 Setup for eranc atria qn 32 Fig 3 4 12 Watchdog timer by software 33 Rev 3 00 23 2006 7 of 9 5 5 09 0178 0300 7534 List of figures Fig 3 5 1 Structure of Port Pi i 0 to 4 34 Fig 3 5 2 Structure of Port Pi direction register i 0 to 4 34 Fig 3 5 3 Structure of Pull up control register 42 1 35 Fig 3 5 4 Structure of Port P1P3 control register 35 Fig 3 5 5 Structure of Transmit Receive buffer register 2 36 Fig 3 5 6 Structure of UART status register 36 Fig 3 5 7 Structure of USB status 37 Fig 3 5 8 Structure of Serial 1 01 control 38 Fig 3 5 9 Structure of UART control register
187. imer By a reset or writing to the watchdog timer control register address 003916 the watchdog timer H is set to FF16 and the watchdog timer L is set to FF1e Write FF16 to the watchdog timer Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register address 003916 When this bit is 0 the count source becomes a watchdog timer L underflow signal The detection time is 174 763 ms at 6 MHz When this bit is 1 the count source becomes 16 In this case the detection time is 683 us at 6 MHz This bit is cleared to 0 after reset Operation of STP instruction disable bit When the watchdog timer is in operation the STP instruction can be disabled by bit 6 of the watchdog timer control register address 003916 When this bit is 0 the STP instruction is enabled When this bit is 1 the STP instruction is disabled and an internal reset occurs if the STP instruction is executed Once this bit is set to 1 it cannot be changed to 0 by program This bit is cleared to 0 after reset Data bus Write FF16 to the watchdog timer control register control register 0 Watchdog timer L 8 Q XIN Q 1 16 1 Watchdog timer 8 Watchdog timer count source selection bit Reset circuit STP Instruction Disable Bit J STP In
188. implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries General Precautions the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Hand
189. ined except for the flag which is 1 Reset Initializing of flags Main program Fig 3 3 6 Initialization of processor status register How to reference the processor status register To reference the contents of the processor status register PS execute the PHP instruction once then read the contents of 5 1 If necessary execute the PLP instruction to return the PS to its original status A NOP instruction should be executed after every PLP instruction PLP instruction execution Fig 3 3 7 Sequence of PLP instruction execution Fig 3 3 8 Stack memory contents after instruction execution Rev 3 00 Oct 23 2006 page 21 of 70 zENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 3 Notes on use 2 Decimal calculations Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation set the decimal mode flag D to 1 with the SED instruction After executing the ADC or SBC instruction execute another instruction before executing the SEC CLC or CLD instruction Notes status flag in decimal mode When decimal mode is selected the values of three of the flags in the status register the N V and Z flags are invalid after a ADC or SBC instruction is executed The carry flag C is set to 1 if a carry is generated as a result of the calculation or is cleared to 0 if a borrow is generated To determine whether a calculation has generated a
190. ion of the same data is made possible This can be used as a simplified PWM Address 001816 P10 RXD O Serial 1 01 control register Address 001A16 Receive buffer full flag RBF Receive interrupt request RI SP Detector UART Control Register Address 001 16 Clock Control Circuit BRG count source selection bit XIN O Division ratio 1 n 1 Baud Rate Generator Address 001 16 ST SP PA Generator P11 TXD Transmit Buffer Register Continuous transmit valid bit Transmit Shift Register Transmit shift register shift completion flag TSC Transmit interrupt source selection bit 52 Transmit interrupt request Transmit buffer empty flag TBE Serial 1 status register Address 001916 Address 001816 Data bus Fig 24 Block diagram of UART serial 1 Transmit Receive Clock Transmit Buffer Register Write Signal Serial Output TXD d 1 Start Bit 74 7 or 8 Data Bit gt 1 or 0 Parity Bit Receive Buffer Register 1 or 2 Stop Bit Read Signal Serial Input RXD Generated at second bit in 2 stop bit Notes 1 Error flag detection occurs at the same time that the RBF flag becomes 1 at 1st stop bit during reception 2 The transmit interrupt can be selected to occur when either the TBE or TSC flag becomes 1 depending on the setting of the transmit interrupt source selection bit TIC of the serial 1 0
191. ion transfers the con M tents of M to M X The contents of A remain unchanged but status flags are changed M X represents the contents of memory where is indicated by X This instruction loads the immediate value in M This instruction loads the contents of M in X This instruction loads the contents of M in Y Rev 3 00 Oct23 2006 page 60 of 70 REJO9BO01 78 0300 5 5 7534 APPENDIX 3 8 Machine instructions Addressing mode Processor status register ABS X ABS Y IND ZP IND IND X IND Y REL OP n OP n OP OP OP OP Rev 3 00 Oct23 2006 page 61 of 70 REJ09B0178 0300 5 5 7534 APPENDIX 3 8 Machine instructions Function Details Addressing mode A A ZP BIT ZP JOP n OP This instruction shifts either or M one bit to the right such that bit 7 of the result always is set to 0 and the bit 0 is stored in C 1 46 2 PC PC 1 This instruction adds one to the PC but does no otheroperation ORA Note 1 When T 0 A lt AVM When T 1 M X M X V M When T 0 this instruction transfers the con tents of A and M
192. is 500 kHz or more Do not execute the STP instruction 3 Method to stabilize A D Converter Method to stabilize A D Converter is described below a A D conversion accuracy could be affected for Bus Powered USB devices while the communicating Figure 3 3 5 shows the method to stabilize A D conversion accuracy inserting a capacitor between Vref and Vss 1 Power supplied by USB Vcc BUS ANo to AN7 m USBVRerouT 0 01t01uF 7 1 7534 Group 1 to 10 0 1 to 1 uF Q Recommends for A D accuracy Fig 3 3 5 Method to stabilize A D conversion accuracy b It is recommended for A D accuracy to avoid converting while USB communication and use average value of several converted values Rev 3 00 Oct 23 2006 page 19 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 3 Notes on use 3 3 4 Notes on watchdog timer The internal reset may not be generated correctly in the middle speed mode depending on the underflow timing of the watchdog timer When using the watchdog timer operate the MCU in any mode other than the middle speed mode i e high speed low speed or double speed mode 3 3 5 Notes on RESET pin 1 Connecting capacitor In case where the RESET signal rise time is long connect a ceramic capacitor or others across the RESET pin and the Vss pin And use a 1000 pF or more capacitor for high frequency use When connecting the capacitor note the follo
193. is bit is read out the value is 1 Fig 2 3 3 Structure of UART status register Serial 1 01 control register b7 b6 b5 b4 b3 b2 b1 bO Serial 1 01 control register SIO1CON Address 1 16 Name Function E BRG count source x selection bit CSS f XiN 4 Nothing is allocated for this bit Ds is a write disabled bit 1 x When this bit is read out the value is 1 Continuous transmit valid bit Continuous transmit invalid Continuous transmit valid 3 Transmit interrupt Interrupt when transmit buffer source selection bit TIC has emptied 1 Interrupt when transmit shift operation is completed 4 Transmit enable bit TE i Transmit disabled Transmit enabled Receive enable bit RE Receive disabled Receive enabled Serial 1 enable bit SIOE port Not available UART mode USB mode Fig 2 3 4 Structure of Serial 1 control register Rev 3 00 Oct 23 2006 page 30 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O UART control register b7 b6 b5 64 b3 b2 bi bO UART control register UARTCON Address 1B 16 Name Function et pues selection bit CHAS 7 bits 7 Parity checking disabled PARE Parity checking enabled oe qe PARS Odd parit Jg Stop bit length selection i bit STPS 4 P11 TxD P channel In output mode 0 CMOS output output d
194. isable bit 1 N channel open drain POFF output Nothing is allocated for these bits These are write disabled bits When these bits are read out the values are 1 Fig 2 3 5 Structure of UART control register Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator BRG Address 1C 16 W AGE Ge Ka Fig 2 3 6 Structure of Baud rate generator Rev 3 00 Oct 23 2006 page 31 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O Serial 1 2 control register b7 b6 b5 64 b3 b2 bi bO Serial 1 02 control register 5102 Address 30 16 B Funcion 1 Atreset RWI Internal synchronous Rage i s IN clock selection bits NER f XiN 32 64 T XJ 28 f XiN 256 Spara pin selection bit port input Note output 4 Nothing is allocated for this bit Te is a write disabled bit When this bit is read out the value is 0 IE 1 MSB first 0 External clock S is input 1 Internal clock 8 is output T l completion flag 1 shift completed Note When using it as a input set the port direction register bit to 0 Fig 2 3 7 Structure of Serial 02 control register Serial 1 02 register b7 b6 b5 b4 b3 b2 b1 bO Serial l O2 register 5102
195. ister and port P3 register 50 Pull up control register PULL address 0016 16 POo pull up control bit P01 pull up control bit pull up control bit P04 P07 pull up control bit P30 P33 pull up control bit P34 pull up control bit 0 Pull up off 1 Pull up on Initial value FF 16 P35 P36 pull up control bit P37 pull up control bit Note Pins set to output ports are disconnected from pull up control Fig 14 Structure of pull up control register 50 Port P1P3 control register P1P3C address 0017 16 P37 INTo input level selection bit 0 CMOS level 1 TTL level P3e INT1 input level selection bit 0 CMOS level 1 TTL level P10 P12 P13 input level selection bit 0 CMOS level 1 TTL level Not used Fig 15 Structure of port P1P3 control register Rev 3 00 23 2006 page 16 of 55 REJO9BO01 78 0300 RENESAS 7534 HARDWARE FUNCTIONAL DESCRIPTION Table 5 I O port function table Pin 00 07 Port P10 RxD D P11 TxD D P12 ScLk P13 SDATA P14 CNTRo P15 16 Port P1 20 P27 AN7 Port P2 5 P3e6 INT1 P37 INTo Port P3 P40 P41 Port P4 Input output I O individual bits format Non port function Related SFRs Diagram No CMOS compatible input level Key input interrupt Pull up control register 1 CMOS 3 sta
196. it Q Toggle flip flo Port P14 latch Timer X latch write Port P14 direction Pulse output mode register Pulse output mode Prescaler 12 latch 8 Timer 1 latch 8 Timer 2 latch 8 To timer 2 f XiN 16 9 Prescaler 12 8 Timer 1 8 Timer 2 8 interrupt request bit To timer 1 interrupt request bit Fig 23 Block diagram of timer X timer 1 and timer 2 Rev 3 00 Oct 23 2006 24 of 55 RENESAS REJ09B0178 0300 7534 HARDWARE FUNCTIONAL DESCRIPTION Serial Interface Serial 1 1 Asynchronous serial I O UART mode Serial 1 01 be used as an asynchronous UART serial I O dedicated timer baud rate generator is also provided for baud rate generation when serial 1 1 is in operation Eight serial data transfer formats can be selected and the transfer formats to be used by a transmitter and a receiver must be identi cal Each of the transmit and receive shift registers has a buffer register the same address on memory Since the shift register cannot be written to or read from directly transmit data is written to the trans mit buffer and receive data is read from the respective buffer regis ters These buffer registers can also hold the next data to be trans mitted and receive 2 byte receive data in succession By selecting 1 for continuous transmit valid bit bit 2 of SIO1CON continuous transmiss
197. it is set Timer X mode register TM Address 002B 16 Timer X operating mode bits b1 50 0 0 mode 0 1 Pulse output mode 1 0 Event counter mode 1 1 Pulse width measurement mode CNTR0 active edge switch bit 0 Interrupt at falling edge Count at rising edge in event counter mode Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0 Count start 1 Count stop Not used return 0 when read Fig 21 Structure of timer X mode register Timer count source set register TCSS Address 002E 16 Timer X count source selection bit Note 0 f XIN 16 1 f XIN 2 Not used return 0 when read Note To switch the timer X count source selection bit stop the timer X count operation Fig 22 Timer count source set register Rev 3 00 Oct23 2006 page 23 of 55 REJ09B01 78 0300 5 5 HARDWARE 7534 Group FUNCTIONAL DESCRIPTION Data bus Prescaler X latch 8 Timer X latch 8 Pulse width Timer mode Timer X count measurement source selection bit mode pulse output mode To timer X CNTRo active Prescaler X 8 Timer X 8 interrupt edge switch bit EM PION TES aps Event 0 counter Timer X count stop bit mode To CNTRo D interrupt request bit CNTRo active edge switch b
198. itch the detection edge Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals This may cause an unnecessary interrupt 2 Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to 0 by using a data transfer instruction execute one or more instructions before executing the BBC or BBS instruction Reason Clear the interrupt request bit to 0 no interrupt issued If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to 0 the value of the interrupt request bit before being cleared to 0 is read Execute the BBC or BBS instruction NOP one or more instructions Data transfer instruction LDM LDA STA STX and STY instructions Fig 3 3 2 Sequence of check of interrupt request bit Rev 3 00 Oct 23 2006 page 17 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 3 Notes on use 3 Structure of interrupt control register 1 Fix the bit 7 of the interrupt control register 1 to O Figure 3 3 3 shows the structure of the interrupt control register 1 b7 50 Interrupt control register 1 address 003 16 Interrupt enable bit Not used fix this bit to 70 Fig 3 3 3 Structure of interrupt control register 1 3 3 2 Notes on se
199. itial value N should have a margin Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents do not change after interrupt processing The interrupt processing routine Decrements the SWDT contents by 1 at each interrupt processing Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles at the fixed interrupt processing count Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less Main routine Interrupt processing routine m SWDT N SWDT lt SWDT 1 CLI Interrupt processing Main processing Return Interrupt processing Main routine routine errors errors Fig 3 4 12 Watchdog timer by software Rev 3 00 Oct 23 2006 page 33 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers 3 5 List of registers Port Pi 67 66 b5 64 b3 62 b1 Port Pi i
200. l pulse frequency measurement of pulse width of FG pulse for a motor see Application example 4 Measurement of external pulse duty when the frequency is fixed FG pulse Pulse used for detecting the motor speed to control the motor speed Rev 3 00 Oct 23 2006 page 16 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer 2 Timer application example 1 Clock function measurement of 100 ms Outline The input clock is divided by the timer so that the clock can count up at 100 ms intervals Specifications clock f Xin 6 00 MHz is divided by the timer clock is counted up in the process routine of the timer X interrupt which occurs at 100 ms intervals Figure 2 2 11 shows the timers connection and setting of division ratios Figure 2 2 12 shows the relevant registers setting Figure 2 2 13 shows the control procedure Timer X count source Timer X interrupt selection bit Prescaler X Timer X request bit x f XiN 6 00 MHz 1 16 1 147 1 256 1 10 Bi Dividing by 4 with software 100 1 0 No interrupt request issued 1 Interrupt request issued Fig 2 2 11 Timers connection and setting of division ratios Rev 3 00 Oct 23 2006 page 17 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer Timer count source set register address 2E 16 Timer X count source f XiN 16 Interrupt edge selection register address 3A 6 INTEDGE 01111
201. led CPU write Disabled Hardware read Not used Hardware write Set Clear 7534 HARDWARE FUNCTIONAL DESCRIPTION Fig 30 Structure of serial l O1 related registers 2 USB data toggle synchronization register TRSYNC address 001016 Not used return 1 when read Sequence bit toggle flag 0 No toggle 1 Sequence toggle CPU read Enabled CPU write Clear Hardware read Not used Hardware write Set USB interrupt source discrimination register 1 USBIR1 address 001 16 Not used return 1 when read Endpoint determination flag 0 Endpoint 0 interrupt 1 Endpoint 1 interrupt CPU read Enabled CPU write Disabled Hardware read Not used Hardware write Set Clear USB interrupt source discrimination register 2 USBIR2 address 001 16 Not used return 1 when read Suspend request flag 0 No request 1 Suspend request USB reset request flag 0 No request 1 Reset request Not used return 1 when read Token PID determination flag 0 SETUP interrupt 1 OUT interrupt Token interrupt flag 0 No request 1 Token request USB interrupt control register USBICON address 002016 Not used return 1 when read Endpoint 1 enable 0 Endpoint 1 invalid 1 Endpoint 1 valid USB reset interrupt enable 0
202. led Set Write only 1 enabled Clear Write only 0 enabled Dummy Initializing by dummy write enabled H W RD Read by hardware Use used by hardware data is no change H W WR Write by hardware Set Clear Write 0 1 is executed by hardware Set Write only 1 is executed by hardware Clear Write only 0 is executed by hardware Shaded area no R W function Fig 2 4 6 Description of the register structure Rev 3 00 Oct 23 2006 page 57 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB Transmit buffer register TB Address 18 16 CPU CPU RD WR After setting data to address 0018 16 Set o the data is transferred to the transmit Clear shift register automatically Transmit buffer empty flag TxRDY is cleared by writing data to this register an ied ps e r CPU HW Hw RD WR RD WR Initial value by reading data from address 001816 ble Clear USB status Lb USBSTS Address 19 16 b7 bb b4 b3 b2 bl 50 1 RD WR RD WR Initial value 5 e ELIT E empty flag 1 Buffer empty ble Clear This bit is set to 1 when data is transferred from buffer to shift register by hardware This bit is cleared to 0 by writing to buffer EOP detection flag 0 Not detected Ena Clear Set 1 Detect ble Setting condition of this flag to 1 is as follows Normal EOP detected by hardware False
203. led bit When this bit is read out the value is 0 Fig 2 5 6 Structure of Interrupt request register 1 Rev 3 00 Oct 23 2006 page 73 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 5 A D converter Interrupt control register 1 b7 b6 b5 64 b3 b2 61 bO Interrupt control register 1 ICON1 Address 3E 16 B Name Function aese R W e interrupt enable bit ami enabled UART transmit USBSETUP Interrupt disabled OUT token Reset Suspend 1 Interrupt enabled Resume INT interrupt enable INTo interrupt enable bit Interrupt disabled Note 2 Interrupt enabled 3 Timer X or key on wake up Interrupt disabled interrupt enable bit Interrupt enabled 4 Timer 1 interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled 5 Timer 2 or serial 1 2 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled CNTRo or AD converter 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 Nothing is allocated for this bit Do not write 1 to this bit When this bit is read out the value is 0 Notes 1 36 version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 2 5 7 Structure of Interrupt control register 1 Rev 3 00 Oct23 2006 74 of 78 1324 NESAS REJO9B01 78 0300
204. levant to I O port 2 1 2 Relevant registers Port Pi b7 66 b5 64 63 b2 bi bO Port Pi Pi i 0 to 4 Address 00 16 0216 0416 0616 0816 B ___ Function jacse R w ppm 0 re pp Write 544 n input mode mme BE Read Value of pins PP ee Note The following ports do not exist so that the corresponding bits are not used 42 pin version Ports P17 P42 P47 36 pin version Ports 15 17 P36 40 47 32 pin version Ports P15 P17 P26 P27 P35 P37 40 47 Fig 2 1 2 Structure of Port Pi i 0 to 4 Rev 3 00 Oct 23 2006 page 2 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 1 port Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register PiD i 2 O to 4 Address 01 16 0316 0516 0716 0916 W 0 Port Pioinput mode x 1 Port Pio output mode 0 Port Pi input mode x 1 Port Pi output mode 0 Port Pizinput mode x 1 Port Pie output mode 0 Port mode 1 Port Pis output mode 0 Port input mode 1 Port output mode 0 Port Pisinput mode 1 Port Pis output mode 0 Port Pieinput mode x 1 Port Pie output mode 0 Port input mode 1 Port output mode Note The following ports do not exist so that the corresponding bits are not used 42 pin version Ports P17 42 4 e 36 pin version Ports 15 17
205. ling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock
206. mmunicate ADDR and transfer type ENDP data execution DATA of the processing ordered by the token handshake the completion of the communication Figure 2 4 2 shows the data structure of the packet Packet type 8bits 8bits 11bits 5bits 2bits SOF 8bits 8bits Tbits 4bits 5bits 2bits 8bits 8bits 8bits X 0 to 8bytes 16bits 2bits Data PD ono 8bits 8bits 2bits Notes 1 The shaded parts show the data which requires processing by software in 7534 Group 2 The DATA number of data PID shows the number in L S 3 Determination of Start Of Frame is not executed because the processing is not required Fig 2 4 2 Data structure of USB packet In 7534 Group the PID ADDR ENDP and DATA of packet structure data in Figure 2 4 2 can be controlled by software Rev 3 00 Oct 23 2006 52 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 5 Data structure Data which composes the communication of USB transmits and receives data that the structure number of bits is different as shown in Figure 2 4 2 continuously by the LSB first Basically the contents except SYNC which is synchronizing signal and EOP which is the completion signal are treated as data Accordingly the difference of the number of bits can be detected by forecasting and determining the following data from the content of PID Table 2 4 3 shows the content of data which composes the packet Table 2 4 3 Data structure of USB packet
207. mmunication line device confirms the normal data transfer of host The confirmation transfer is transmitted by host side for each frame 1ms frame which is the basic time unit of the USB transfer When the host stops all the device the host informs device of the stop of functions by suspending the confirmation transfer for 3 ms or more The signal to stop the function is called Suspend The stopped device can be returned by 2 methods The return is performed basically when there is a change in the device in the stopped state One is a method change on communications line to return to a normal state by restarting the data communication which is suspended before suspend The signal to return is called Resume The other is a method change on the device to return to a normal state by the change in an external input of the device The host can inform all the other connected devices of the return of the device by the change in an external input by outputting K state signal of 1 to 15 ms The signal to activate for other devices is called Remote wake up When the SEO signal of 2 5 us or more is input on communications line regardless of the state of the stop start of the function of the device side the packet and the stage processing the device makes all states concerning the USB function initial state The signal to initialize is called Reset Table 2 4 5 shows a special signal of USB Table 2 4 5 Special signal of USB Signal
208. n 1XXX IN token interrupt of DATA 0 1 is valid Ena Set Use lag OUT STALL 01XX STALL handshake is valid for IN token ble Clea 00XX handshake is valid for IN token Endpoint 0 PID selection boo STALL handshake is valid for OUT lag OUT token ble Clea Endpoint 0 selection xx10 ACK handshake is valid for OUT token Ena Set Use lag IN STALL XX00 NAK handshake is valid for OUT token ble Clea Endpoint 0 PID selection Ena Set Use Clear lag IN DATAO 1 ble Clea DPIDO and SPIDOI are used to control the response for IN token DPIDO is used with the token interrupt enable flag TKNE DPIDO is cleared to 0 automatically by hardware when ACK is received SPIDOO APIDO are used to control the response for OUT token When DPIDO is changed during token packet the changed value is valid after end of token X it can be set to O or 1 USB PID control register 1 EP1PID Address 24 16 67 b6 65 b4 63 62 bi T I T T T 0 RD WR RD WR Initial value 0 Endpoint 1 PID selection 1X IN token interrupt of DATAO 1 is valid Ena Set Use 01 STALL handshake is valid for IN token Clea 00 handshake is valid for IN token Endpoint 1 PID selection Ena Set Use Clear DPID1 and SPID1 are used to control the response for IN token DPID1 is used with the token interrupt enable flag TKNE DPID1 is cleared to 0 automatically by hardware when is received
209. nal synchronous clock selection bits nye f XiN 32 f XiN 64 15 3 28 256 4 ROT is allocated for this bit E is a write disabled bit When this bit is read out the value is AE u aa MSB first sr I External clock S is input Internal clock San is output mmu imum gt PE completion flag 1 shift completed Note When using it as input set the port P13 direction register bit to 0 Fig 3 5 28 Structure of Serial 1 02 control register Serial 1 2 register b7 b6 b5 b4 b3 b2 b1 b0 Serial 1 2 register 5102 Address 31 16 A shift register for serial transmission and reception EAER At transmitting Set a transmission data At receiving A reception data is stored KAGE ER EN Fig 3 5 29 Structure of Serial 1 2 register Rev 3 00 Oct 23 2006 page 47 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers A D control register 67 b6 25 b4 b3 b2 61 bO A D control register ADCON Address 3416 b2 b1 60 0 P2o ANo 1 21 0 P22 AN2 1 P23 AN3 0 P24 AN4 1 P25 AN5 0 P2e ANe 1 P27 AN7 3 Nothing is allocated for this bit This is write disabled bit When this bit is read out the value is 0 4 AD conversion completion bit 0 onversion progress 1 1 Conversion comple
210. nter Notes on use When the active edge of an external interrupt INTo INT1 is set the interrupt request bit may be set Therefore please take following sequence 1 Disable the external interrupt which is selected 2 Change the active edge in interrupt edge selection register in case of CNTRo Timer X mode register 3 Clear the set interrupt request bit to 0 4 Enable the external interrupt which is selected Vector addresses Note 1 R k nterrupt source iori i iti p Priority High order iow order Interrupt request generating conditions emarks Reset Note 2 1 FFFD16 FFFCie At reset input Non maskable UART receive 2 FFFB16 FFFA16 At completion of UART data receive Valid in UART mode USB IN token At detection of IN token Valid in USB mode UART transmit 3 FFF916 FFF816 At completion of UART transmit shift or Valid in UART mode when transmit buffer is empty USB SETUP OUT token At detection of SETUP OUT token or Valid in USB mode Reset Suspend Resume At detection of Reset Suspend Resume At detection of either rising or falling edge External interrupt of INT1 input active edge selectable INTo 4 FFF716 FFF616 At detection of either rising or falling edge External interrupt of INTo input active edge selectable Timer X 5 FFF516 FFF416 At timer X underflow Key on wake up At falling of conjunction of input logical External interrupt v
211. on mode ports Set the I O ports for the input mode and connect them to Vcc or Vss through each resistor of 1 to 10 Ports that permit the selecting of a built in pull up resistor can also use this resistor Set the ports for the output mode and open them at L or When opening them in the output mode the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset Thus the potential at these pins is undefined and the power source current may increase in the input mode With regard to an effects on the system thoroughly perform system evaluation on the user side Since the direction register setup may be changed because of a program runaway or noise set direction registers by program periodically to increase the reliability of program 2 Termination remarks Input ports and I O ports Do not open in the input mode Reason The power source current may increase depending on the first stage circuit An effect due to noise may be easily produced as compared with proper termination and shown on the above I O ports When setting for the input mode do not connect to Vcc or Vss directly Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between a port and or 55 I O ports When setting for the input mode
212. on of these signals can be recognized by the interrupt request The interrupt to a special signal is all included in the OUT token interrupt IN token interrupt IN token endpoint 0 and IN token endpoint 1 OUT token interrupt OUT token SETUP token Reset Suspend and Resume The remote wake up function is used to output signals when to output as USB function is required for the return from the stopped state by an external input Figure 2 4 18 shows timing chart of each signal 1 Resume interrupt return from Suspend Keep alive No change of Reset signal input 1 ms interval communication line 2 5 us or more i i 3 ms or more i 1 i gt 1 1 1 D pin state STP instruction executed Microcomputer operation 1 Suspend interrupt occurs Resume interrupt occurs Reset interrupt occurs 1 1 t OUT token interrupt Interrupt processing Po Suspend request flag USB reset request flag RSTRQ Resume interrupt enable RSME 2 External interrupt return from SUSPEND Keep alive No change of Reset signal input 1 ms interval communication line Remote wake up signal output 2 5 us or more AE 3 ms or more 1 10 ms H 1 4 1 EE e STP instruction executed Microcomputer n operation OUT token interrupt Interrupt processing Suspend request flag SPRQ USB reset request flag RSTRQ
213. or P13 latch P13 SDATA O SDATA pin selection bit Fig 35 Block diagram of serial 1 02 Serial I O shift register 2 8 Rev 3 00 Oct 23 2006 page 34 of 55 REJ09B0178 0300 RENESAS 7534 HARDWARE FUNCTIONAL DESCRIPTION Serial 1 02 operation By writing to the serial 1 2 register address 003116 the serial 2 counter is set to 7 After writing the SDATA pin outputs data every time the transfer clock shifts from a high to a low level And as the transfer clock shifts from a low to a high the SDATA pin reads data and at the same time the contents of the serial 1 2 register are shifted by 1 bit When the internal clock is selected as the transfer clock source the following operations execute as the transfer clock counts up to 8 Serial 2 counter is cleared to 0 Transfer clock stops at an level Interrupt request bit is set Shift completion flag is set Also the SDATA pin is in a high impedance state after the data trans fer is complete Refer to Figure 36 When the external clock is selected as the transfer clock source the interrupt request bit is set as the transfer clock counts up to 8 but external control of the clock is required since it does not stop Notice that the SDATA pin is not in a high impedance state on the completion of data transfer Synchronous clock Transfer clock Serial 1 02 register write
214. ource 16 fale selection bit Note f X N 2 EX Nothing is allocated for these bits These are write disabled bits When these bits are read out the values are 0 ERE End Note To switch the timer X count source selection bit stop the timer X count operation before do that Fig 2 2 7 Structure of Timer count source set register Interrupt edge selection register b7 b6 b5 64 b3 b2 bi bO Interrupt edge selection register INTEDGE Address 16 Name Function At reset pss interrupt edge ve Falling edge active DE selection bit Note 1 Rising edge active interrupt edge 7 Falling edge active selection bit Note 2 1 Rising edge active When these bits are read out the values are 0 EE 4 Serial 1 01 or INT interrupt 0 Serial 1 selection bit 1 INT 5 Timer X or key on wake up 0 Timer X interrupt selection bit 1 Key on wake up Timer 2 or serial 2 interrupt 0 Timer 2 selection bit 1 Serial 1 02 7 or AD converter 0 CNTRo interrupt selection bit 1 AD converter Notes 1 32 pin version Not used This is a write disabled bit When this bit is read out the value is 0 2 36 pin and 32 pin version Not used This is a write disabled bit When this bit is read out the value is 0 Fig 2 2 8 Structure of Interrupt edge selection register Re
215. ows the relevant registers setting Figure 2 2 20 shows the control procedure Input pulse lt 71 4 us or more mE 50 us or less 14 kHz or less 20 2 Invalid gt i Invalid 2 15 _ 58 counts 2ms 2ms _ 4 71 4 us 50 us Fig 2 2 18 Judgment method of valid invalid of input pulses Rev 3 00 Oct 23 2006 page 23 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer Interrupt edge selection register address 16 wwreoce fo gt Timer X or key on wake up interrupt selection Timer X Timer X mode register address 2B 16 b7 Timer X operating mode Event counter mode gt GNTRo active edge switch Falling edge count Timer X count Stop Clear to 0 when starting count Prescaler 12 address 28 16 b7 60 93 Timer 1 address 2916 67 t Set division ratio 1 Prescaler X address 2C 16 b7 50 Timer X address 2D 16 b7 bo Set 255 just before counting pulses 255 After certain time has passed the number of input pulses is decreased from this value Interrupt control register 1 address 3E 16 b7 60 Timer interrupt Disabled Timer 1 interrupt Enabled Interrupt request register 1 address 3C 16 b7 60 mo Judgment of Timer interrupt request bit 1 of this bit when reading the count value indicates the 25
216. peed function F S USB operation at 12Mbps Low Speed function L S USB operation at 1 5Mbps This communication standard depends on the kind of peripherals The transfer type for each peripheral is decided Table 2 4 1 shows the transfer types of USB Table 2 4 1 Transfer types of USB Transfer type L S F S H S Operation Control L S JF S H S This is used when setting up and for all devices common Interrupt L S F S H S This is used when transferring a small amount of data in real time Bulk This is used when transferring a large amount of data in no real time Isochronous This is used when transferring a large amount of data in real time L S Low Speed function F S Full Speed function H S Hi Speed function The 7534 Group has USB Low Speed function and the control transfer and interrupt transfer can be used in Table 2 4 1 Rev 3 00 Oct23 2006 50 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 2 Communication sequence The control transfer and the interrupt transfer have a different communication sequence respectively The control transfer is used when setting up all devices common and communicates combining 3 types of stages in one processing The communication starts first in Setup Stage and Data Stage of the content is executed and then one processing of the communication sequence is completed by executing Status Stage Data can be set from host to device
217. register Interrupt request register 1 b7 b6 b5 64 b3 b2 61 bO Interrupt request register 1 IREQ1 Address 3C 16 Name Function receive USBIN token PE EE NNNM interrupt request issued interrupt request bit Interrupt request issued UART transmit USBSETUP 0 No interrupt request issued OUT token Reset Suspend 1 Interrupt request issued Resume INT1 interrupt request bit Note 1 INTo interrupt request bit M No interrupt request issued Note 2 Interrupt request issued 3 Timer X or key on wake up x No interrupt request issued interrupt request bit 1 Interrupt request issued 4 Timer 1 interrupt request bit 0 No interrupt request issued 1 Interrupt request issued 5 Timer 2 or serial 1 02 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued CNTRo or AD converter 0 No interrupt request issued interrupt request bit 1 Interrupt request issued 7 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 These bits can be cleared to 0 by program but cannot be set Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is O Fig 2 3 10 Structure of Interrupt request register 1 Rev 3 00 Oct 23 2
218. release the STP or WIT state interrupt enable bits must be set to 1 before the STP or WIT instruction is executed When the STP status is released prescaler 12 and timer 1 will start counting clock which is XIN divided by 16 so set the timer 1 inter rupt enable bit to 0 before the STP instruction is executed Note For use with the oscillation stabilization set bit after release of the STP instruction set to 1 set values in timer 1 and prescaler 12 after fully appreciating the oscillation stabilization time of the oscillator to be used Clock mode Operation is started by an on chip oscillator after releasing reset A division ratio 1 1 1 2 1 8 is selected by setting bits 7 and 6 of the CPU mode register after releasing it Note Insert a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by the maker of the oscillator Also if the oscillator manufacturer s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on chip insert a feedback resistor between and Xour following the instruction Fig 45 External circuit of ceramic resonator External oscillation circuit ve Vss Fig 46 External clock input circuit MISRG Address 0038 16 Oscillation stabilization time set bit after
219. rial 1 Handling of serial 1 1 clear When serial l O1 is set again the transmit receive operation is stopped restarted while serial 1 01 is operating clear the serial l O1 as shown in Figure 3 3 4 SIO1CON address 1A16 bit 7 bit 6 102 e Serial 1 enabled Handling of clear serial 1 01 SIO1CON address 1A16 bit 7 bit 6 lt 112 e Serial 1 cleared SIO1CON address 1 16 bit 7 bit 6 002 e Serial 1 disabled UARTCON address 1Bt16 BRG address 1C16 Set again Note Serial 1 1 register set again SIO1CON address 1 16 10XXXXXX ial 1 01 Set again Note Serial 1 enabled Note When the contents of register is not changed setting again is not necessary Fig 3 3 4 Sequence of clearing serial 2 Data transmission control with referring to transmit shift register completion flag The transmit shift register completion flag changes from 1 to 0 with a delay of 0 5 to 1 5 shift clocks When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register note the delay 3 Writing transmit data When an external clock is used as the synchronous clock for the clock synchronous serial I O write the transmit data to the transmit buffer register serial shift register at H of the transfer clock input level Rev 3 00 23 2006 page 18 of 70 7RENESAS REJ09B0178 0300 APPENDIX
220. ring condition 85 C Voi lor characteristics of N channel normal port same charactersistics pins POo P07 10 16 2 27 P37 P4o P41 lt 9 5 o 4 2 a g 2 o L output voltage V Fig 3 2 10 VoL loL characteristic example of N channel Ta 85 C Normal port Rev 3 00 Oct 23 2006 page 12 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics Measuring condition Ta 25 C Voi lor characteristics of N channel LED drive port same charactersistics pins 6 lt 9 o 2 5 o ub 2 a g 2 o L output voltage V Fig 3 2 11 VoL loL characteristic example of N channel Ta 25 C LED drive port Measuring condition Ta 85 C Vo lot characteristics of N channel LED drive port same charactersistics pins 6 lt x amp a 2 2 2 o 2 a 2 2 o L output voltage VoL V Fig 3 2 12 VoL loL characteristic example N channel Ta 85 C LED drive port Rev 3 00 Oct 23 2006 page 13 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 2 Typical characteristics Measuring condition L input current of port at pull up transistor connected same charactersistics pins 0 0 P3o P37 lt 2 2 40 45 Power source voltage Vcc V Fig 3 2 13 L
221. ronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics Z 5 5 C 7 D me lt D D 7534 Group User s Manual RENESAS 8 BIT SINGLE CHIP MICROCOMPUTER 740 FAMILY 740 SERIES Renesas Electronics Rev 3 00 2006 10 www renesas com 10 11 12 13 Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of we
222. rrupt enabled Timer X count source 16 Set division ratio 1 to Prescaler X and Timer X Timer X count start Interrupts enabled Reset Timer to restart count from 0 second after completion of clock set Note 1 Perform procedure for completion of clock set only when completing clock set Note 2 When using Index X mode flag T Note 3 When using Decimal mode flag D Push registers used in interrupt process routine Judge whether clock stops Clock count up Pop registers pushed to stack 2 2 Timer Rev 3 00 Oct 23 2006 page 19 of 78 RENESAS REJ09B0178 0300 7534 Group 3 Timer application example 2 Piezoelectric buzzer output APPLICATION 2 2 Timer Outline The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output Specifications rectangular waveform dividing the clock f Xin 6 00 MHz into about 2 kHz 1995 Hz is output from the P14 CNTRo pin level of the P14 CNTRo pin is fixed to while a piezoelectric buzzer output stops Figure 2 2 14 shows a peripheral circuit example and Figure 2 2 15 shows the timers connection and setting of division ratios Figures 2 2 16 shows the relevant registers setting and Figure 2 2 17 shows the control procedure The level is output while a piezoelectric buzzer output stops 6 4 CNTRo output P14 CNTRo 250 us 250 us S
223. rs Pull up control register b7 b6 b5 64 b3 b2 bi bO Pull up control register PULL Address 16 16 pull up control bit Pull up Pull up On PO pull up control bit E Pull up Off 1 Pull up On 2 P02 POspull up control bit 0 Pull up Off 1 1 Pull up On P04 PO pull up control bit 0 Pull up 1 1 Pull up On 4 P30 P33 pull up control bit 0 Pull up Off 1 1 Pull up On 5 P34 pull up control bit 0 Pull up Off 1 1 Pull up On P35 pull up control bit 0 Pull up Off 1 Note 2 1 Pull up On 7 P37 pull up control bit 0 Pull up Off 1 Note 3 1 Pull up On Notes 1 Pins set to output are disconnected from the pull up control 2 36 pin version P36 is not existed 32 pin version Not used 3 32 pin version Not used Fig 3 5 3 Structure of Pull up control register Port P1P3 control register b7 06 b5 b4 b3 b2 bi Port P1P3 control register P1P3C Address 17 16 B ___ Function jArese P37 INTo input level selection CMOS level bit Note 1 TTL level P3e INT input level selection CMOS level bit Note 2 TTL level Pio P12 P13 input level I CMOS level selection bit TTL level Notes 1 For the 32 pin version nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 2 For the 32 pin and 36 pin versions nothing is allocated for thi
224. ructure of USB packet 2 52 Fig 2 4 3 USB L S interface iier 55 Fig 2 4 4 USB L S connection example 55 Fig 2 4 5 Memory map of registers relevant to 0 5 56 Fig 2 4 6 Description of the register structure 57 Fig 2 4 7 Register structures relevant to USB 1 58 Fig 2 4 8 Register structures relevant to USB 2 sse 59 Fig 2 4 9 Register structures relevant to USB 3 60 Fig 2 4 10 Register structures relevant to USB 4 61 Fig 2 4 11 Control method of control sequence 62 Fig 2 4 12 Timing chart of the transaction according to each token 63 Fig 2 4 13 USB interrupt processing example OUT token 65 Fig 2 4 14 USB interrupt processing example IN 66 Fig 2 4 15 Data read timing of SETUP 67 Fig 2 4 16 Data read timing of OUT 67 Fig 2 4 17 Data read timing of IN token endpoint 0 and IN token endpoint 1 token 67 Fig 2 4 18 Timing chart of each signal nennen nennen nennen 68 Fig 2 4 19 Example for determination of resume 69 Fig 2 4 20 Processing for width of SEO 69 Fig 2 4 21 Coun
225. rupt when transmit buffer source selection bit TIC has emptied 1 Interrupt when transmit shift operation is completed 4 Transmit enable bit 0 Transmit disabled 1 Transmit enabled Receive enable bit RE Receive disabled Receive enabled Serial 1 enable bit SIOE O port Not available UART mode USB mode Fig 3 5 8 Structure of Serial 01 control register UART control register b7 b6 b5 b4 b3 b2 b1 50 UART control register UARTCON Address 1B 16 Name 2 Funtn lu pne ee selection bit CHAS 7 bits eee es DI PARE Parity checking enabled 5 Odd parit Stop bit length selection 7 1 stop bit bit STPS 1 2 stop bits 4 P11 TxD P channel guthul made i outpu output disable bit 1 N channel open drain POFF output 5 Nothing is allocated for these bits These are write disabled bits When these bits are read out the values are 1 Fig 3 5 9 Structure of UART control register Rev 3 00 Oct 23 2006 page 38 of 70 7tENESAS 09 0178 0300 APPENDIX 7534 Group 3 5 List of registers Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator Address 1C 16 rai KAGE Fig 3 5 10 Structure of Baud rate generator Refer to Figure 2 4 6 Description of register struct
226. s 3A16 X1XXXXX02 INTo falling Serial 1 02 selected ICON1 address 16 0X0XX0XX2 INTo interrupt serial 1 02 interrupt disabled IREQ1 address 3C 16 612 Detection of INTo falling edge 1 IREQ1 address 3C 16 bit2 0 IREQ1 address 3C 16 bit5 0 5102 address 3116 The first byte of Transmission data write transmission data One byte transmission starts IREQ1 address 3C te bit5 2 Judgment of completion of one byte transmission 1 IREQ1 address 3C 16 bits 0 The second byte of Transmission data write 5102 address 3116 ansmission data One byte transmission starts IREQ1 address 3C t6 bit5 2 Judgment of completion of one byte transmission Fig 2 3 20 Control procedure of transmission side Rev 3 00 Oct 23 2006 page 41 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O SEE X This bit is not used here Set it to 0 or 1 arbitrary Initialization address 0116 1 address 0016 1 Quasi SRDY signal H SIO2CON P1D address 3016 000000112 Serial 1 02 setting address 0316 00 2 Generation of a 2 ms interval using Timer address 0016 bitO 0 PO address 0016 1 Quasi SRDY signal output SIO2 address 3116 lt Dummy data Transmit receive shift completion
227. s bit This is a write disabled bit When this bit is read out the value is 0 Fig 3 5 4 Structure of Port P1P3 control register Rev 3 00 Oct23 2006 35 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Transmit Receive buffer register b7 b6 b5 64 b3 b2 bi Transmit Receive buffer register TB RB Address 18 16 The transmission data is written to or the receive data is read out from this buffer register At writing A data is written to the transmit buffer register At reading The contents of the receive buffer register are read out Note The contents of transmit buffer register cannot be read out The data cannot be written to the receive buffer register Fig 3 5 5 Structure of Transmit Receive buffer register UART status register b7 b6 b5 b4 b3 b2 61 UART status register UARTSTS Address 19 16 EE Ja buffer empty flag x Buffer full TBE Buffer empty Receive buffer full flag RBF Buffer empty Buffer full Transmit shift register shift Transmit shift in progress completion flag TSC Transmit shift completed pes Lg He Overrun error Parity error flag PE No error Parity error Framing error flag FE I No error AO PE Summing error flag SE 0 E 21 Nothing is allocated for this bit T isa eue bit 1 x When this bit is read out the value is 1
228. s instruction takes a bit wise logical AND of A and M contents however the contents of A and M are not modified The contents of N V Z are changed but the contents of A M remain unchanged BMI f This instruction takes a branch to the ap Note 4 pointed address when N is 1 The branch address is specified by a relative address If N is 0 the next instruction is executed This instruction takes a branch to the ap pointed address if Z is 0 The branch address is specified by a relative address If Z is 1 the next instruction is executed Rev 3 00 Oct 23 2006 page 56 of 70 RENESAS REJ09B0178 0300 7534 APPENDIX 3 8 Machine instructions Addressing mode Processor status register ABS ABS X ABS Y IND ZP IND IND X IND Y REL OP OP OP n JOP JOP JOP 6D 3 70 3 79 3 61 2171 2 Rev 3 00 Oct 23 2006 page 57 of 70 09 0178 0300 2 1 5 7534 Group APPENDIX 3 8 Machine instructions Symbol Function Details Addressing mode A A ZP JOP n it BPL Note 4 This instruction takes a branch to the ap pointed address if N is 0 The branch address is specifie
229. s shown in Figure 2 3 28 SIO1CON address 1 16 bit 7 bit 6 lt 102 e Serial 1 enabled Handling of clear the serial l O1 SIO1CON address 1A16 bit 7 bit 6 112 e Serial l O1 cleared SIO1CON address 1 16 bit 7 bit 6 lt 002 Serial 1 disabled UARTCON address 1Bt16 BRG address 1 16 Set again Note Serial 1 1 register set again SIO1CON address 1 16 10XXXXXX 2 Set again Note Serial 1 01 enabled Note When the contents of register is not changed setting again is not necessary Fig 2 3 28 Sequence of clearing serial 2 Data transmission control with referring to transmit shift register completion flag The transmit shift register completion flag changes from 1 to 0 with a delay of 0 5 to 1 5 shift clocks When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register note the delay 3 Writing transmit data When an external clock is used as the synchronous clock for the clock synchronous serial I O write the transmit data to the transmit buffer register serial I O shift register at of the transfer clock input level 4 Serial 1 02 transmit receive shift completion transmit receive shift completion flag bit 7 of the serial 1 2 control register is set to 1 after completing transmit receive shift In order to set this flag to 0 write data dummy
230. s transmission The TXD pin will stop at high level after completing transmission of 1 byte 3 If the transmit buffer contents are rewritten during a continuous transmission transmission of the rewritten data will be started after completing transmission of 1 byte Fig 26 Continuous transmission operation of UART serial I O Rev 3 00 23 2006 page 26 of 55 REJO9BO01 78 0300 RENESAS 7534 HARDWARE FUNCTIONAL DESCRIPTION Universal serial bus USB mode By setting bits 7 and 6 of the serial 1 control register address 001A16 to 11 the USB mode is selected This mode conforms to Low Speed USB2 0 specification In this mode serial 1 01 interrupt have 6 sources USB in and out token receive set up token receive USB reset suspend and resume The USB status UART status register functions as the USB status register USBSTS There is the USBVREFOUT pin for the USB reference voltage output and a D line with 1 5 kO external resistor can be pull up USB mode block and USB transceiver block show in figures 27 and 28 Data bus P10 D O USB transceiver P11 D O 76 MHz Digital Address 001816 Receive buffer register RxRDY bit stuffing decoder Receive shift register Differential input and Single end input Output data and control USB transmit unit
231. signal SDATA at serial 1 02 output transmit SDATA at serial 1 02 input receive Serial 1 2 interrupt request bit set Note When the internal clock is selected as the transfer and the direction register of P1 3 SDATA pin is set to the input mode the SDATA pin is in a high impedance state after the data transfer is completed Fig 36 Serial 1 02 timing LSB first Rev 3 00 Oct 23 2006 page 35 of 55 5 5 09 0178 0300 7534 Group HARDWARE FUNCTIONAL DESCRIPTION A D Converter The functional blocks of the A D converter are described below A D conversion register AD The A D conversion register is a read only register that stores the result of A D conversion Do not read out this register during an A D conversion A D control register ADCON The A D control register controls the A D converter Bit 2 to 0 are analog input pin selection bits Bit 4 is the AD conversion completion bit The value of this bit remains at O during A D conversion and changes to 1 at completion of A D conversion A D conversion is started by setting this bit to O except during an A D conversion Comparison voltage generator The comparison voltage generator divides the voltage between 55 and VREF by 1024 by a resistor ladder and outputs the divided volt ages Since the generator is disconnected from VREF pin and Vss pin current is not flowing into the resistor ladder Ch
232. signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different type numbers implement a system evaluation test for each of the products BEFORE USING THIS MANUAL This user s manual consists of the following three chapters Refer to the chapter appropriate to your conditions such as hardware design or software development Chapter 3 also includes necessary information for systems development You must refer to that chapter 1 Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions based mainly on setting examples of relevant registers CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer such as the electrical characteristics the list of registers 2 Structure of register The figure of each register structure describes i
233. sing 2 67 US interrupt request processing in case of no interrupt F W Reset processing in case RxPID 0 gt Reset interrupt Reset interrupt of interrupt request processing eset processing case FW processing of interrupt request Resume interrupt Spec Reset Reset Reset processing 2 67 us SIE Reset interrupt request Reset interrupt request Reset interrupt request F W Reset processing Reset processing Reset processing Function of USBPID control register 0 address 002316 Bit 4 STALL handshake control for OUT token of this register is forcibly set by SIE under the special condition shown below Set condition when PID of data packet DATAO incorrect PID in the status stage of the control read transfer SYNC field at reception Normally the SYNC field consists of KJKJKJKK 8 bits However as for SIE of the 7534 Group when the low order 6 bits are KJKJKK it is determined as SYNC Rev 3 00 Oct23 2006 page 33 of 55 REJ09B01 78 0300 5 5 7534 Group HARDWARE FUNCTIONAL DESCRIPTION Serial 1 02 The serial 1 02 function can be used only for clock synchronous se rial I O For clock synchronous serial 1 2 the transmitter and the receiver must use the same clock When the internal clock is used transfer is started by a write signal to the serial l O2 register Serial 1 02 control register SIO2CON The serial 1 2 control register contains 8 bits which control various serial I
234. ster shift completion flag 0 Transmit shift in progress 1 Transmit shift completed Overrun error flag 0 No error 1 Overrun error Parity error flag 0 No error 1 Parity error CPU read Enabled CPU write Clear Hardware read Not used Framing error flag Hardware write Set 0 No error 1 Framing error Summing error flag 0 No error 1 Summing error Not used returns 1 when read Baud rate generator BRG address 001 16 This register is valid only when selecting the UART mode A baud rate value is set CPU read Disabled CPU write Set Clear Hardware read Used Hardware write Not used Fig 32 Structure of serial l O1 related registers 4 Rev 3 00 Oct 23 2006 31 of 55 5 5 09 0178 0300 7534 HARDWARE FUNCTIONAL DESCRIPTION Fig 33 Structure of serial l O1 related registers 5 UART control register UARTCON address 001 16 Character length selection bit 0 8 bits 1 7 bits Parity enable bit 0 Parity checking disabled 1 Parity checking enabled Parity selection bit 0 Even parity 1 Odd parity Stop bit length selection bit 0 1 stop bit 1 2 stop bits P channel output disable bit 0 CMOS output 1 N channel open drain output Not used returns 1 when read Serial l O1 control register SIO1CON address 001A16 BRG count source selection bit 0 f XIN 1 f XIN A
235. stics Vcc 4 4 V to 5 25 V Oscillation stopped in USB mode USB SUSPEND pull up resistor output included Fig 3 1 1 Ta 0to 70 G Table 3 1 5 A D Converter characteristics 1 Vcc 4 1 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions Limits Typ Resolution Linearity error Vcc 4 1 to 5 5 V Ta 25 Differential nonlinear error Vcc 4 1 to 5 5 V 25 VOT Zero transition voltage VREF 5 12 V VFST Full scale transition voltage VREF 5 12 V mV tCONV Conversion time tc XIN RLADDER Ladder resistor IVREF Reference power source input current VREF 5 0 V VREF 3 0 V HA A D port input current loUT is included to this ratings Fig 3 1 1 Power source current measurement circuit in USB mode at oscillation stop Rev 3 00 Oct 23 2006 page 5 of 70 REJ09B0178 0300 5 5 7534 Group APPENDIX 3 1 Electrical characteristics 3 1 5 Timing requirements Table 3 1 6 Timing requirements Vcc 4 1 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter Limits Typ tw RESET Reset input L pulse width External clock input cycle time tWH XIN External clock input H pulse wid
236. stor of 1 to 10 Set to the output mode and open at L H level VREF Connect to Vss GND Xout only when using an external clock Rev 3 00 Oct 23 2006 page 7 of 78 5 5 09 0178 0300 APPLICATION 7534 Group 2 1 port 2 1 5 Notes on input and output pins 1 Notes in stand by state In stand by state for low power dissipation do not make input levels of an input port and an I O port undefined Pull up connect the port to Vcc or pull down connect the port to Vss these ports through a resistor When determining a resistance value note the following points External circuit Variation of output levels during the ordinary operation When using a built in pull up resistor note on varied current values When setting as an input port Fix its input level When setting as an output port Prevent current from flowing out to external Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I O port are undefined This may cause power source current stand by state the stop mode by executing the STP instruction the wait mode by executing the WIT instruction 2 Modifying output data with bit managing instruction When the port latch of an I O port is modified with the bit managing instruction the value of the unspecified bit may be changed Reason
237. struction D 4 40 Block diagram of watchdog timer Internal reset 60 Watchdog timer control register address 0039 16 WDTCON Watchdog timer H read only for high order 6 bit STP instruction disable bit 0 STP instruction enabled 1 STP instruction disabled Watchdog timer H count source selection bit 0 Watchdog timer L underflow 1 16 Fig 41 Structure of watchdog timer control register Rev 3 00 Oct 23 2006 page 37 of 55 REJ09B0178 0300 3 NE SAS 7534 Group HARDWARE FUNCTIONAL DESCRIPTION Reset Circuit The microcomputer is put into a reset status by holding the RESET pin at the L level for 15 us or more when the power source voltage is 4 1 to 5 5 V and XIN is in stable oscillation After that this reset status is released by returning the RESET pin to the level The program starts from the address having the con tents of address FFFDt16 as high order address and the contents of address FFFCt6 as low order address Note that the reset input voltage should be 0 82 V or less when the power source voltage passes 4 1 V Note Power source voltage 0v Reset input voltage OV Note Reset release voltage Vcc 4 1 V Power source as voltage detection circuit Fig 42 Example of reset circuit Clock from on chip oscillator SYNC Address
238. t request bit and an interrupt enable bit and they are controlled by the interrupt disable flag When the interrupt enable bit and the interrupt request bit are set to 1 and the interrupt disable flag is set to 0 an interrupt is accepted The interrupt request bit can be cleared by program but not be set The interrupt enable bit can be set and cleared by program It becomes usable by switching CNTRo and A D interrupt sources with bit 7 of the interrupt edge selection register timer 2 and serial 1 O2 interrupt sources with bit 6 timer X and key on wake up interrupt sources with bit 5 and serial I O transmit and INT1 interrupt sources with bit 4 The reset and BRK instruction interrupt can never be disabled with any flag or bit All interrupts except these are disabled when the in terrupt disable flag is set When several interrupts occur at the same time the interrupts are received according to priority Table 6 Interrupt vector address and priority Interrupt operation Upon acceptance of an interrupt the following operations are auto matically performed 1 The processing being executed is stopped 2 The contents of the program counter and processor status regis ter are automatically pushed onto the stack 3 The interrupt disable flag is set and the corresponding interrupt request bit is cleared 4 Concurrently with the push operation the interrupt destination address is read from the vector table into the program cou
239. t 7 circuit Fig 3 4 2 Wiring for the RESET pin Rev 3 00 Oct 23 2006 page 27 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 4 Countermeasures against noise 3 Wiring for clock input output pins Make the length of wiring which is connected to clock I O pins as short as possible Make the length of wiring within 20mm across the grounding lead of a capacitor which is connected to an oscillator and the Vss pin of a microcomputer as short as possible Separate the Vss pattern only for oscillation from other Vss patterns Reason If noise enters clock I O pins clock waveforms may be deformed This may cause a program failure or program runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer Fig 3 4 3 Wiring for clock I O pins 4 Wiring to CNVss pin Connect the CNVSs pin to the Vss pin with the shortest possible wiring Reason The processor mode of a microcomputer is influenced by a potential at the 55 pin If a potential difference is caused by the noise between pins 55 and Vss the processor mode become unstable This may cause a microcomputer malfunction or a program runaway Fig 3 4 4 Wiring for CNVss pin Rev 3 00 Oct 23 2006 page 28 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 4 Countermeasures against noise 5 Wirin
240. t level 4 P1P3C Configuration to TTL input level for P10 P12 P13 input level 2 Remote wake up Routine Configuration to TTL input level for P10 P12 P13 input level lt Configuration to TTL input level for P10 P12 P13 input level Fig 3 3 12 Countermeasure 2 by software Rev 3 00 Oct 23 2006 page 26 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 4 Countermeasures against noise 3 4 Countermeasures against noise 3 4 1 Shortest wiring length 1 Package Select the smallest possible package to make the total wiring length short Reason The wiring length depends on a microcomputer package Use of a small package for example QFP and not DIP makes the total wiring length short to reduce influence of noise Fig 3 4 1 Selection of packages 2 Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible Especially connect a capacitor across the RESET pin and the Vss pin with the shortest possible wiring within 20mm Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions If noise having a shorter pulse width than the standard is input to the RESET pin the reset is released before the internal state of the microcomputer is completely initialized This may cause a program runaway Reset circuit Rese
241. t registers 0 21 Fig 2 2 17 Control procedure nennen nennt 22 Fig 2 2 18 Judgment method of valid invalid of input pulses 23 Fig 2 2 19 Relevant registers setting nennen nennen 24 Fig 2 2 20 Control procedure 25 Fig 2 2 21 Timers connection and setting of division ratios 26 Fig 2 2 22 Relevant registers setting 27 Fig 2 2 23 Control uu E ES 28 Fig 2 3 1 Memory map of registers relevant to serial 29 Fig 2 3 2 Structure of Transmit Receive buffer register 29 Fig 2 3 3 Structure of UART status register 30 Fig 2 3 4 Structure of Serial 1 01 control 30 Rev 3 00 Oct 23 2006 page 5 049 RENESAS REJ09B0178 0300 List of figures 7534 Group Fig 2 3 5 Structure of UART control register ener 31 Fig 2 3 6 Structure of Baud rate generator 31 Fig 2 3 7 Structure of Serial 1 02 control register 32 Fig 2 3 8 Structure of Serial 1 2 32 Fig 2 3 9 Structure of Interrupt edge selection 33 Fig 2 3 10 Structure of Interrupt request register 1
242. t to 1 when data is transferred from shift register to buffer by hardware This bit is cleared to 0 by reading from buffer Fig 2 4 7 Register structures relevant to USB 1 Rev 3 00 Oct 23 2006 page 58 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB USB data toggle synchronization register TRSYNC Address 1D 16 7 66 b5 64 63 62 bi 00 ID HW WR RD n Initial value 0 NH Sequence bit toggle 0 No toggle p Set flag 1 Sequence toggle ble Setting condition of this flag to 1 is as follows Setting of handshake for OUT token EPOPID is ACK toggle of data PID is performed normally and errors do not occur at data phase during OUT and SETUP transaction When ACK is received during IN transaction This bit is cleared to 0 by writing dummy to this register USB ras source register 1 USBIR1 Address 1E 16 b3 b2 bl 00 EX WR RD WR Initial value 0 0 Endpoint 0 interrupt Ena Set determination flag 1 Endpoint 1 interrupt ble Clear This flag is set to 1 when IN token interrupt of endpoint 1 occurs This flag is cleared to 0 when IN token interrupt of endpoint 0 occurs Writing to this bit is invalid Do not write 1 to bits 0 to 6 USB ME o register 2 Address 1 16 b3 b2 Sa T Es RD WR RD WR Initial value Suspend request flag 0 No
243. te output USB input output level when Serial 1 01 function Serial 1 01 control 2 selecting USB function input output register 3 CMOS compatible input level Serial 1 02 function Serial 1 2 control 4 CMOS 3 state output input output register 5 Note Timer X function input output Timer X mode register 6 10 A D conversion input A D control register 7 8 External interrupt input Interrupt edge selection 9 register 10 Note Port P10 P12 P13 P3e P37 is CMOS TTL input level Rev 3 00 Oct23 2006 17 of 55 REJ09BO01 78 0300 134 NE SAS HARDWARE 7534 Group FUNCTIONAL DESCRIPTION 2 Port P1o Serial 1 01 mode selection bit b7 Pull up control Serial 1 01 mode selection bit b6 Receive enable bit Direction register Serial l O1 mode selection bit m S Serial 1 01 mode selection bit 66 rs Direction Data bus Port latch register HQ Data bus Port latch o gt 94 P10 P12 P13 input level selection bit To key input interrupt lt enerating circuit 2 2 Serial 1 01 3 Port P11 D input 1 P channel output disable bit 3 Serial l O1 mode selection bit 67 D output BENE ial I O1 lecti i Serial l O1 mode selection bit b6 086
244. ted E EZ Note 26 P27 AN7 be selected in the 36 and 42 pin versions This bit can be cleared to 0 by program but cannot be set to 1 Fig 3 5 30 Structure of A D control register Rev 3 00 Oct 23 2006 page 48 of 70 134 NE SAS REJO9B01 78 0300 7534 A D conversion register high order b7 b6 b5 b4 b3 b2 61 bO ENENENE A D conversion register high order ADH Address 3616 The read only register in which the 5 results stored lt 10 bit read gt When these bits are read out the values are 0 Fig 3 5 31 Structure of A D conversion register high order A D conversion register low order b7 b6 b5 b4 b3 b2 b1 b0 ITTI A D conversion register low order ADL Address 3516 The read only register in which the A D conversion s results are stored lt 8 bit read gt b7 lt 10 bit read gt 60 67 Fig 3 5 32 Structure A D conversion register low order Rev 3 00 Oct 23 2006 page 49 of 70 5 5 REJ09B0178 0300 Nothing is allocated for these bits These are write disabled bits APPENDIX 3 5 List of registers PF ES APPENDIX 7534 Group 3 5 List of registers ISRG b7 06 65 64 b3 62 b1 60 MISRG Address 3816
245. ted on by the BIT instruction is stored in the negative flag Table 4 Set and clear instructions of each bit of processor status register Set instruction Clear instruction CLC CLI Rev 3 00 Oct 23 2006 page 12 of 55 REJ09B0178 0300 CLD CLT CLV 7tENESAS HARDWARE 7534 Group FUNCTIONAL DESCRIPTION CPU Mode Register CPUM The CPU mode register contains the stack page selection bit This register is allocated at address 003 16 CPU mode register CPUM address 003B16 Processor mode bits b1 0 Single chip mode 1 0 Not available 1 Stack page selection bit 0 0 page 1 1 page Not used returns 0 when read Do not write 1 to these bits Main clock division ratio selection bits b7 b6 0 2 High speed mode 1 f XIN 8 Middle speed mode 0 applied from on chip oscillator 1 f 6 f XIN Double speed mode Fig 10 Structure of CPU mode register Switching method of CPU mode register Note on stack page Switch the CPU mode register CPUM at the head of program after When 1 page is used as stack area by the stack page selection bit releasing Reset in the following method the area which can be used as stack depends on RAM size Espe cially be careful that the RAM area varies in Mask ROM version One Time PROM version and Emulator MCU After releasing reset Start with an on chip oscillator Note Wait until establish ceramic
246. termeasure 2 by software 70 Fig 2 5 1 Memory of registers relevant to A D 71 Fig 2 5 2 Structure of A D control 71 Fig 2 5 3 Structure of A D conversion register high order 72 Fig 2 5 4 Structure of A D conversion register 72 Fig 2 5 5 Structure of Interrupt edge selection register 73 Fig 2 5 6 Structure of Interrupt request register 7 73 Fig 2 5 7 Structure of Interrupt control register 1 74 Rev 3 00 Oct 23 2006 page 6 of 9 RENESAS REJ09B0178 0300 7534 Group Fig Fig Fig Fig Fig Fig List of figures 2 5 8 Connection diagr aih Mas 75 2 5 9 Relevant registers 75 2 5 10 Control procedure for 8 bit read 76 2 5 11 Control procedure for 10 bit 76 2 5 12 Method to stabilize A D conversion 47 77 2 6 1 Example of poweron reset circuit 78 CHAPTER 3 APPENDIX Fig 3 1 1 Power source current measurement circuit in USB mode at oscillation stop 5 Fig 3 1 2 Output switching characteristics measurement circuit 6 5 Timing Ghall
247. th tWL XIN External clock input L pulse width tc CNTR CNTRo input cycle time tWH CNTR CNTRo INT1 input pulse width tWL CNTR CNTRo INTO INT input L pulse width tc SCLk Serial 1 02 clock input cycle time tWH SCLK Serial 1 02 clock input pulse width tWL SCLK Serial 1 2 clock input L pulse width tsu SDATA SCLK Serial 1 2 input set up time th SCLK SDATA Serial 1 02 input hold time 3 1 6 Switching characteristics Table 3 1 7 Switching characteristics Vcc 4 1 to 5 5 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter Limits Min Typ twH SCLK Serial 1 02 clock output H pulse width tc ScLk 2 30 twL SCLK Serial 1 02 clock output L pulse width tc ScLk 2 30 td SCLK SDATA Serial 1 02 output delay time tv SCLK SDATA Serial 02 output valid time tr SCLk Serial 1 2 clock output rising time Serial 1 02 clock output falling time CMOS output rising time Note CMOS output falling time Note USB output rising time CL 200 to 450 pF Ta 0 to 70 C Vcc 4 4 to 5 25 V USB output falling time CL 200 to 450 pF 0 to 70 Vcc 4 4 to 5 25 V Notes XOUT pin is excluded Measured output pin Fig 3 1 2 Output switching characteristics measurement circuit 100 pF
248. the host gives the device the instruction of the communication processing which the host side executes Token executes data transmit receive Data and indicates the completion of the communication is shown at the end Handshake These communication processings are executed in order by each one unit which has the data structure Packet format and one processing Transaction is completed The content of processing can be identified according to PID Packet IDentifier field which is unit of data Field which composes each packet Not only the content of processing but also the data structure in the packet can be identified by this PID Table 2 4 2 shows the packet type of USB Table 2 4 2 Packet types of USB Packet type Transmitter Operation SOF Start of Frame Host Packet indicating the top of frame 1 ms including all transfer types Token Host Packet indicating the processing to execute Data Host Device indicating the transmit receive data for processing shown by token Handshake Host Device Packet indicating the result of communication processing In 7534 Group the token data and the handshake of packet types in Table 2 4 2 can be controlled by software 4 Packet structure As for the packet type of USB the data and the structure are different by PID Each packet includes the following data shown with PID for which the control is required by 7534 Group token the receiver to co
249. through this sequence Control Write and the result can be read out to host from device Control Read Use endpoint ENDP 0 in the control transfer The interrupt transfer is used when transferring a small amount of data in real time There is no stage unlike the control transfer Only when the host requests data Token IN the device can transmit data Use the endpoint in the interrupt transfer excluding 0 41 is set for the 7534 Group Figure 2 4 1 shows the communication sequence of USB Control Transfer ENDP endpoint 0 Control Read Stage Setup Handshake 1 transaction Handshake 1 or more transaction SETUP gt Data Token IN gt Token OUT p Status Token OUT Handshake 1 transaction Control Write Stage Setup Handshake 1 transaction Data Token OUT Handshake 1 or more transaction gt 5 II 4 4 79 Status Token IN Handshake 1 transaction No data Control Stage Setup Token SETUP Handshake 1 transaction Status Token IN Handshake 1 transaction Interrupt Transfer ENDP 1 Token IN Handshake Note The shaded parts show the case when the device transmits data to the host Fig 2 4 1 Communication sequence of USB Rev 3 00 23 2006 page 51 of 78 2 1 REJ09B0178 0300 APPLICATION 7534 Group 2 4 USB 3 Packet type The host side controls all the communications in USB Basically
250. tion register address 3A 16 60 b7 wee gt Timer X or key on wake up interrupt selection Timer X gt CNTRo or AD converter interrupt source selection CNTRo Timer X mode register address 2B 16 b7 60 11 Timer operating mode Pulse width measurement mode CNTRo active edge switch H level width measurement Timer X count Stop Clear to O when starting count Prescaler X address 2C 16 255 Timer X address 201 Set division ratio 1 b7 50 Interrupt control register 1 address 16 b7 50 ion Timer X interrupt Enabled gt CNTRo interrupt Enabled Interrupt request register 1 address 3C 6 b7 60 asc CRO Timer interrupt request Set to 1 automatically when Timer X underflows gt CNTRo interrupt request Fig 2 2 22 Relevant registers setting Rev 3 00 Oct 23 2006 page 27 of 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer RESET Initialization SEI All interrupts disabled INTEDGE address 3A16 bits 0 Timer X or key on wake up interrupt selection Timer X bit7 0 CNTRo or AD converter interrupt source selection CNTR o operating mode Pulse width measurement mode address ccu UU Measure level of pulses input from CNTR pin adaross 2C 1e Set division ratio so that Timer X interrupt will occur at address 2D16 lt
251. to the ALU which performs a bit wise OR and stores the result in A When T 1 this instruction transfers the con tents of M X and the M to the ALU which performs a bit wise OR and stores the result The contents of remain unchanged but status flags are changed M X represents the contents of memory where is indicated by X This instruction pushes the contents of to the memory location designated by S and decrements the contents of S by one M S PS S lt S 1 This instruction pushes the contents of PS to the memory location designated by S and dec rements the contents of S by one 56 541 A amp M This instruction increments S by one and stores the contents of the memory designated by SinA 56 541 PS M S This instruction increments S by one and stores the contents of the memory location designated by S in PS This instruction shifts either A or M one bit left through C C is stored in bit 0 and bit 7 is stored in C This instruction shifts either A or M one bit right through C C is stored in bit 7 and bit 0 is stored in C This instruction rotates 4 bits of the M content to the right 5 5 PS 5 5 1 PCL lt 5 5 5 1 lt 5 This instruction increments 5 by and stores the contents of the memory location designated by S in PS S is again incremented by one
252. ts functions contents at reset and attributes as follows Note 2 Bits Bit attributes Note 1 b7 b6 b5 b4 b3 b2 bi Contents immediately after reset release CPU mode register CPUM Address 3B 16 Name Function Processor mode bits Not available Stack page selection bit T page Nothing arranged for these bits These are write disabled bits When these bits are read out the contents are 0 Fix this bit to 0 Main clock stop bit gperating Internal system clock selection bit 2 2 selected Bit in which nothing is arranged Bit that is not used for control of the corresponding function Note 1 Contents immediately after reset release 0 at reset release 1 at reset release Undefined at reset release Contents determined by option at reset release Note 2 Bit attributes The attributes of control register bits are classified into 3 bytes read only write only and read and write In the figure these attributes are represented as follows Read enabled Write enabled Read disabled Write disabled 0 write 3 Supplementation For details of software refer to the 740 FAMILY SOFTWARE MANUAL For details of development support tools refer to the Renesas Technology Homepage http www renesas com 7534 Table of contents Table of contents CHAPTER 1 HARDWARE DESCRIPTION
253. uction after the following are set in order to enable the using interrupts Clear the timer 1 interrupt enable bit to 0 bit 4 Clear the timer 2 interrupt enable bit to 0 1 bit 5 Clear the timer 1 interrupt request bit to 0 IREQ1 bit 4 Clear the timer 2 interrupt request bit to 0 IREQ1 bit 5 Clear the interupt request bit of the interrupt using for return to O Set the interupt enable bit of the interrupt using for return to 1 Clear the interrupt disable flag to 0 Rev 3 00 Oct 23 2006 page 49 of 55 REJ09B0178 0300 5 5 7534 Group Wait mode HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT System enters the wait mode by executing the WIT instruction In the wait mode the oscillation is operating but the internal clock is stopped Accordlingly CPU is stopped but the peripheral devices are operating 1 Wait mode state Table 12 shows the state at wait mode Table 12 Wait mode state Parameter State Parameter State Oscillation Stop Watchdog timer Operating CPU Stop RAM State retained port State at WIT instruction execution SFR State retained Timer 1 timer 2 and retained prescaler 12 excepted Timer At selecting internal count source CPU register State retained Operating Accumulator At selecting external count source Index register X Operating Index register Y UART Operating Stack pointer A D
254. ues 0 4 Serial 1 01 or INT interrupt 0 Serial 1 1 selection bit 1 INT 5 Timer X or key on wake up 0 Timer X interrupt selection bit 1 Key on wake up Timer 2 or serial 1 02 interrupt 0 Timer 2 selection bit 1 Serial 1 02 7 or AD converter 0 CNTRo interrupt selection bit 1 AD converter Notes 1 32 pin version Not used This is a write disabled bit When this bit is read out the value is 0 2 36 pin and 32 pin version Not used This is a write disabled bit When this bit is read out the value is O Fig 3 5 35 Structure of Interrupt edge selection register CPU mode register b7 b6 b5 b4 b3 b2 b1 bO CPU mode register CPUM Address 3 16 Function ToO Processor mode bits Single chip mode Not available Not available Not available 2 Stack page selection bit 0 0 page 1 1 page When these bits are read out the values are 0 Do not write 1 Clock division ratio selection 4 J high speedmode 0 1 6 8 middle speed mode 0 Applied from on chip oscillator 1 6 f Xin double speed mode 1 1 Fig 3 5 36 Structure of CPU mode register Rev 3 00 Oct 23 2006 page 51 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register
255. uilt in PROM version 1 Programming adapter Use a special programming adapter shown in Table 3 3 1 and a general purpose PROM programmer when reading from or programming to the built in PROM in the built in PROM version Table 3 3 1 Programming adapters Microcomputer Programming adapter M37534E4GP One Time PROM version shipped in blank PCA7435GPG03 M37534E8SP One Time PROM version shipped in blank PCA7435SP PCA7435SPG02 M37534E8FP One Time PROM version shipped in blank PCA7435FP PCA7435FPGO02 2 Programming reading In PROM mode operation is the same as that of the M5M27C101AK but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes Accurately set the following conditions for data programming reading Take care not to apply 21 V to VPP pin is also used as the CNVSS pin or the product may be permanently damaged Programming voltage 12 5 V Setting of PROM programmer switch refer to Table 3 3 2 Table 3 3 2 PROM programmer address setting PROM programmer start address PROM programmer Product name format end address M37534E4GP Address 0E08016 Note 1 Address OFFFD16 Note 1 Address 0C08016 Note 2 Address OFFFD16 Note 2 M37534E8FP Notes 1 Addersses E08016 to FFFD16 in the built in PROM corresponds to addresses 0E08016 to OFFFD16 in the PROM programmer 2 Addersses C08016 to FFFDt16 in the built in PROM corresponds to
256. uit for ceramic resonator 41 49 Countermeasure 2 by software 43 50 Method to stabilize A D conversion 43 51 Programming and testing of One Time PROM version 44 52 Timing chart after an interrupt eene enn 46 53 Time up to execution of the interrupt processing routine 46 54 A D conversion equivalent 48 55 A D conversion timing n 48 56 Handling of Vcc USBVnerour pins of M37534M4 XXXFP M37534E8FP 53 57 Handling of Vcc USBVnerour pins of M37534M4 XXXGP M37534EAGP 54 58 Handling of Vcc USBVaerour pins of M37534E8SP M37534M4 XXXSP M37534RSS 55 CHAPTER 2 APPLICATION Fig 2 1 1 Memory of registers relevant to I O 2 2 Fig 2 1 2 Structure of Port Pi i 0 to 4 entere nnne nns 2 Fig 2 1 3 Structure of Port Pi direction register i 0 to 4 3 Fig 2 1 4 Structure of Pull up control register 3 Fig 2 1 5 Structure of P1P3 control 4 Fig 2 1 6 Structure of Interrupt edge selection 4 Fig 2 1 7 Structure of Interrupt request register 1 5 Fig 2 1 8 Structure of Interrupt control register 1 4400 5
257. ull up control register address 16 16 b7 50 411 P03 pull up on Interrupt edge selection iregister address 3A 16 INTEDGE gt Timer key on wake up interrupt selection Key on wake up selected Interrupt control register 1 address 3E 16 b7 50 Timer X or key on wake up interrupt Enabled Interrupt request register 1 address 3C 16 b7 60 Timer X or key on wake up interrupt request bit Fig 2 1 9 Relevant registers setting 7534 group i 0 3 I Fig 2 1 10 Application circuit example Rev 3 00 Oct23 2006 78 5 5 REJ09B0178 0300 APPLICATION 7534 Group 2 1 port RESET X This bit is not used here Set it to 0 or 1 arbitrary Initialization PULL address 1616 lt 1112 pull up On Power down procedure INTEDGE address bitS lt 1 Key on wake up selected IREQ1 address 3C e 0 Clear the key on wake up interrupt request bit to 0 ICON1 address 16 bit3 1 Key on wake up interrupt enabled WIT Process continuation Interrupt process of Key on wake up Fig 2 1 11 Control procedure 2 1 4 Handling of unused pins Table 2 1 1 Handling of unused pins Pins Ports name PO P1 P2 P3 P4 Handling Set to the input mode and connect each to Vcc or Vss through a resi
258. urations USBVREFOUT a 16 15 P33 LEDs 14 P32 LEDz2 M37534M4 XXXGP_ 13 P31 LED1 M37534E4GP 12 P3o LEDo Vss Eg EJ P22 AN2 P23 AN3 P24 AN4 P25 AN5 Outline PLQP0032GB A Fig 3 10 2 M37534M4 XXXGP M37534E4GP pin configuration Rev 3 00 Oct 23 2006 page 69 of 70 REJ09B01 78 0300 5 5 APPENDIX 7534 Group 3 10 Pin configurations Top view P13 SDATA P12 SCLK P11 TxD D P10 RxD D P07 06 05 04 02 USBVREFOUT P37 INTo P36 LEDe INT1 P23 AN3 lt gt P24 AN4 gt P25 AN5 26 P27 AN7 P40 P41 VREF RESET CNVss gt Vcc SSHVESZEWN lt NI O1 D m 2 9 dSXXX VINTESZEIN XoUT Vss Outline 4251 PRDP0042BA A Fig 3 10 3 M37534M4 XXXSP M37534E8SP M37534RSS pin configuration Rev 3 00 Oct 23 2006 70 of 70 7RENESAS REJ09B0178 0300 REVISION HISTORY 7534 Group User s Manual Page Summary V 1 10 Sep 15 2001 4 Preface Home page address revised 5 BEFORE USING THIS MANUAL Home page address revised 1 8 Table 1 Function description of Vss VCC revised 1 9 Fig 7 Under development eliminated 1 13 Note on stack page added 1 19 Fig 17 Ports P36 P37 revised 1 42 NOTES ON PROGRAMMING Note on Stack Page added 1 4
259. ure for registers relevant to USB USB data toggle synchronization register TRSYNC Address 1D 16 7 b6 b5 64 b3 b2 bi 00 sora RD WR RD WR Initial value 0 Sequence bit toggle 0 No toggle Fu Bd flag 1 Sequence toggle ble Setting condition of this flag to 1 is as follows Setting of handshake for OUT token in EPOPID is ACK toggle of data PID is performed normally and errors do not occur at data phase during OUT and SETUP transaction When ACK is received during IN transaction This bit is cleared to 0 by writing dummy to this register Fig 3 5 11 Structure of USB data toggle synchronization register USB interrupt source discrimination register 1 USBIR1 Address 1E 16 b7 b6 b5 b4 63 b2 bi 00 Foxe RD WR RD WR Initial value 0 1 Endpoint 0 Endpoint 0 interrupt Ena Set determination flag 1 Endpoint 1 interrupt ble Clear This flag is set to 1 when IN token interrupt of endpoint 1 occurs This flag is cleared to 0 when IN token interrupt of endpoint 0 occurs Writing to this bit is invalid Do not write 1 to bits O to 6 Fig 3 5 12 Structure of USB interrupt source discrimination register 1 Rev 3 00 Oct23 2006 39 of 70 RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Refer to Figure 2 4 6 Description of register structure for registers relevant to USB USB interrupt oe register 2
260. urement CNTRo interrupt request occurrence Falling edge 1 Timer X L level width measurement CNTRo interrupt request occurrence Rising edge Pulse output mode 1 Event counter mode Pulse width measurement mode Rev 3 00 Oct 23 2006 page 45 of 70 5 5 REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Timer X b7 06 b5 64 b3 b2 61 50 Timer X TX Address 2D 16 Set a count value of timer X The value set in this register is written to both timer X and timer X latch at the same time When this register is read out the timer X s count value is read out Fig 3 5 26 Structure of Timer X Timer count source set register b7 b6 b5 b4 b3 b2 b1 00 Timer count source set register TCSS Address 2E 16 Name Function At reset source 0 f XiN 16 selection bit Note 1 2 Nothing is allocated for these bits These are write disabled bits When these bits are read out the values are 0 Note To switch the timer X count source selection bit stop the timer X count operation before do that Fig 3 5 27 Structure of Timer count source set register Rev 3 00 Oct 23 2006 46 of 70 7RENESAS REJ09B0178 0300 APPENDIX 7534 Group 3 5 List of registers Serial 1 2 control register b7 b6 b5 b4 b3 b2 bi Serial 1 02 control register SIO2CON Address 30 16 Inter
261. ut Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offi
262. v 3 00 23 2006 14 of 78 7RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 2 Timer Interrupt request register 1 b7 b6 b5 b4 b3 b2 bi Interrupt request register 1 IREQ1 Address 3C 16 _ Name Funcdin E receive USBIN token D ND interrupt request issued interrupt request bit Interrupt request issued UART transmi USBSETUP 0 No interrupt request issued OUT token Reset Suspend 1 Interrupt request issued Resume INT interrupt request bit Note 1 INTo interrupt request bit a No interrupt request issued Note 2 Interrupt request issued 3 Timer X or key on wake up x No interrupt request issued x interrupt request bit 1 Interrupt request issued 4 Timer 1 interrupt request bit 0 No interrupt request issued 1 Interrupt request issued 5 Timer 2 or serial 2 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued CNTRo or AD converter 0 No interrupt request issued interrupt request bit 1 Interrupt request issued 7 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the value is 0 These bits can be cleared to 0 by program but cannot be set Notes 1 36 pin version and 32 pin version INT1 interrupt does not exist 2 32 pin version INTo interrupt does not exist This is a write disabled bit When this bit is read out the value is 0 Fig 2 2 9
263. wing Make the length of the wiring which is connected to a capacitor as short as possible Be sure to verify the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin it may cause a microcomputer failure 3 3 6 Notes on input and output pins 1 Notes in stand by state In stand by state for low power dissipation do not make input levels of an input port and an I O port undefined Pull up connect the port to Vcc or pull down connect the port to 55 these ports through resistor When determining a resistance value note the following points External circuit Variation of output levels during the ordinary operation When using built in pull up or pull down resistor note on varied current values When setting as an input port Fix its input level When setting as an output port Prevent current from flowing out to external Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I O port are undefined This may cause power source current stand by state the stop mode by executing the STP instruction the wait mode by executing the WIT instruction 2 Modifying output data with bit managing instruction When the port latch of an I O port is modified with the bit managing instruction the value of the unspecified bit may be
264. z 6 MHz divided by 64 Transfer direction LSB first reception side outputs the quasi Sroy signal at 2 ms intervals which the timer generates and 2 byte data is transferred from the transmission side to the reception side SRDY 2 SCLK s YBXBXEXEXENENENEY 969696969668 TEX 2ms 4 gt Fig 2 3 16 Timing chart Rev 3 00 Oct 23 2006 page 38 of 78 RENESAS REJ09B0178 0300 APPLICATION 7534 Group 2 3 Serial I O Figures 2 3 17 and 2 3 19 show the registers setting relevant to the serial 1 02 and Figure 2 3 18 shows the transmission data setting of the serial 1 2 Serial 2 control register address 30 16 b7 0 bi SIO2CON fo Internal synchronous clock f X 64 SDATA pin SDATA output gt LSB first Internal clock Interrupt edge selection register address 3A 16 b7 a mene Hi INTo interrupt edge Falling edge active gt Timer 2 or serial 2 interrupt selection Serial 1 02 Interrupt control register 1 address SE 16 b7 50 INTo interrupt Disabled gt Serial 2 interrupt Disabled Interrupt request register 1 address 3C 16 b7 0 bi mea oj INTo interrupt request Serial 2 interrupt request Confirm transmission completion of one byte unit using t

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