HMC983LP5E - Analog Devices
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1. BIT TYPE NAME Ww DEFLT DESCRIPTION 2 0 R W Auxiliary Device Address 3 000h Chip address used by AUXSPI 0 Use XTAL for AUXSPI clock 3 R W Divide Clock by 4 for AUXSPI 1 0 1 Use XTAL divided by 4 for AUXSPI clock 0 Start AUXSPI when data is written to RegO3h 4 R W Start AUXSPI 1 0 1 reserved 7 5 R W Reserved 3 4h 9 8 R W Reserved 2 2h 13 10 R W Reserved 4 8h 14 R W Reserved 1 0 When 1 keeps the XTAL gate open to get XTAL from the Den RAM Keep Xtal Gate Open l o companion PFD CP chip HMC984LP4E 18 16 R W Reserved 3 Oh Table 13 Reg 05h Integer Set Point Trigger Delay Register BIT TYPE NAME Ww DEFLT DESCRIPTION Sigma Delta Modulator integer set point Specifies the integer Integer Division Ratio part of the division ratio for the RF Divider in fractional mode or 19 0 R W 20 200d the integer division ration in integer mode Also used as delay counter for hardware ramp trigger Pin D4 in Ramp TriggeriDelay ramp mode This value is valid when Reg OEh 11 1 Table 14 Reg 06h Fractional Set Point Down Dwell Register MSB BIT TYPE NAME WwW DEFLT DESCRIPTION Most significant 30 bits to specify fractional set point for Sigma Fractional Blvisionmbatic VSB Delta Modulator Total Fractional bits are 48 29 0 R W 30 0 Down Dwell for Asymmetric Defines the MSB portion of the dwell down time in the2. Tromp Tramp wa B n 1 TF peret ramp sleps numberzn 2 3 4 et 3 ae Tref ji trigger ramp busy 2 mE j ramp busy Figure 24 DC 7 GHz FRACTIONAL N DIVIDER Sweep Function Itis important to note that the synthesized ramp is subject to normal phase locked loop dynamics If the loop bandwidth in use is much wider than the rate of frequency increments then the locking will be fast and the ramp will have a staircase shape If the update rate is higher than the loop bandwidth as is normally the case the loop will not fully settle before a new frequency step is received Hence the swept output will have a lag and will sweep in a near continuous fashion In all sweep modes ramp busy flag indicates an active sweep and will stay high between the 1st and nth ramp increment ramp busy may be monitored on pin D1 by setting Reg O8h 3 0 8h Triggering In sweep mode the DC 7 GHz FRACTIONAL N DIVIDER can be triggered via one of two methods e SPI trigger by setting Reg OEh 12 1 This triggering method is asynchronous to the reference clock To enable SPI trigger write Reg OEh 13 0 e or applying an external trigger on pin D4 Setting Reg OEh 13 1 and Reg O8h 13 Oh configures DC 7 GHz FRACTIONAL N DIVIDER s pin D4 as
3. Pin Number Function Description Interface Schematic DVDD gt 1 SENb sno o fF ze 2 SDI Main SPI Data Input ScK l 3 SCK dL dp b D1 4 D1 GPIO bit 1 O po LLI 5 DO GPIO bit 0 Q DVDD TE 6 AUX_SCLK Auxiliary SPI Clock Output AUX_SDO gt 7 AUX_SENb Auxiliary SPI Enable F O AUX SCLK e 8 AUX_SDO Auxiliary SPI Data Output AUK SEND Q 9 BIAS External Decoupling for Analog Bias Circuits 10 AVDD 3 Volt Power Supply Pin for Internal Reference Cur rent Sources OQ 11 VCCPS 3 Volt Power Supply Pin for Prescaler sc PADDLE GND LL VI ESD VCCHF 1V VCOIN 12 VCOIN Negative Pin for Prescaler Differential Input AC Coupled ERI 13 VCIOP Positive Pin for Prescaler Differential Input AC Coupled X VCOIP vCCHF 1V Z ESD PADDLE GND 4mA 14 VCCHF 3 Volt Power Supply Pin for Prescaler Input Buffer 15 VPPBUF 5 Volt Power Supply Pin for Divider Output Buffer 16 N C No Connect Pin For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com ESMIEEIC nwcesaiesE MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Table 2 Pin Descriptions Continued Pin Number Function l Description Interface Schematic divCkPFDp divCkPFDn 17 divCkPFDn Negativ
4. On board XTAL Hittite 600 00253 00 1 Supply POWER amp Regulators cow O 5 5v HU J32 M Optional External Ref Input Default Configuration Optional lt lt Configuration 44 Control For details on optional configurations see user guide For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com Phone 978 250 3343 Fax 978 250 3373 t JHittite HMC983LP5E MICROWAVE CORPORATION v02 0112 RoHS DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Theory of Operation The DC 7 GHz FRACTIONAL N DIVIDER can be used in following configurations 1 Fractional N or Integer Mode RF Frequency Divider or Prescaler 2 Fractional N Frequency Synthesizer with an appropriate Phase Detector and VCO Primary target application of the DC 7 GHz FRACTIONAL N DIVIDER is to be used in conjunction with the AND FREQUENCY SWEEPER as shown in Figure 19 Together these two components form a high performance low noise ultra low spurious emissions fractional N frequency synthesizer MC984LP4E Loop Filter veo N Vtune fvco N fpd reference source Frequency Delta Sigma Synthesizer Modulator HMC983LP5E Figure 19 Typical Application of HAC984LP4E w
5. no delay 110 6 clock cycles delay 111 Automatic 7 R W Ramp Start Delay Enable 1 0 Delay the start of sweep as defined in Reg 05h 8 R W Autoseed Mode Enable 1 1 Reseed when changing the frac setpoint 1 Enable Phase Step feature Autoseed Mode must be disabled for Phase Step Reg OEh 8 0 Seed Reg Ah amp Reg Bh set the phase advance retard in 2 s complement 9 R W Phase Step 1 a formate Phase Step takes effect when Reg OAh is written Each time registers are written phase will advance retard by the amount specified 10 R W Maintain DSM State Enable 1 0 Maintain DSM state within the same integer boundary 11 R W Ramp Mode Enable 1 0 Puts DSM in frequency sweeper ramp mode 12 R W Ramp Start from SPI 1 0 Start ramp signal from SPI 13 R W Start Ramp from Ext Trigger 1 0 Allow external trigger to manipulate ramp 14 R W Bypass All 1 0 Bypass Delta Sigma Modulator Place synthesizer in Integer Mode without disabling the DSM Cycle Slip Prevention CSP step size In a PLL configuration 18 15 R W CSP Step Size 4 1111b with the HMC984LP4E one step is equivalent to one divided VCO cycle and step size is the number of VCO cycles 19 R W External DSM Sequence Enable 1 0 Use external DSM sequence imported through GPIO Port Use Falling Edge of DSM Clock 20 R W for External Sequence 1 0 Use falling edge of SD clock to get the external sequence Allow external trigger to s
6. seed 17 0 Reg OBh 17 0 into the phase accumulator at the beginning of each ramp Example Calculate sweep parameters for an asymmetric 2 Way sweep from fy 3000 MHz to f 3105 MHz with positive Tramp 2 ms and negative T amp 4 ms and positive dwell time negative dwell time 2 us with fpp 50 MHz and a 48 bit delta sigma modulator size Assuming R 1 1 Calculate the integer and fractional divider values for initial start frequency fo e Start Nint Reg 05h 60d e Start Nfrac Reg 06h Reg 07h 0d 2 Calculate the number of divided R 1 reference periods in the sweep number of frequency increments N e Nup 2 ms 1 50 MHz 100000 e Ndown 4 ms 1 50 MHz 200000 3 Calculate stepsize size of frequency increments e Stepssize up abs f fo Nup abs 3000 MHz 3105 MHz 100000 1050 Hz Then as per Table 6 Reg 12h 29 0 Oh Reg 13h 17 0 1050d 41Ah e stepsize down abs ff f0 Ndown abs 3000 MHz 3105 MHz 200000 525 Hz Then as per Table 6 Reg 19h 29 0 Oh Reg 1Ah 17 0 1050d 41Ah Note that it is possible to have a case where the frequency f cannot be generated exactly In that case it is required to approximate the final frequency to f fy Afstep x N desired final frequency 4 Calculate number of divided R 1 reference periods in required dwell time e Up dwell time Reg 10h 29 0 Reg 11h 17 0 down dwell time Reg O6h 29 0 Reg O7h 17 0 dwell time 1
7. Enable 1 way sweep mode Re 3 Sieen mod 0 OEh 25 1 or enable 2 Way OEh 25 1 Weg P ToplacetheDC 7GHZFRACTIONAL NDIVIDER sweep mode Reg OEh 25 1 is in automatic sweep mode write T DCJGHZFRACTIONALNDIMDER ee CTO OE Reg OEh 2 3 11 To place the in triggered mode write Reg OEh 2 3 in triggered mode write Reg OEh 2 3 DC 7GHzFRACTIONAL NDIVIDERin 99 write Keg tile _ 90 Automatic 1 Way Sweep triggered mode write Reg OEh 2 3 c 90 Automatic User Defined mode is not supported co Beg vene Sweep mode is not supported pp i Program 4 Sweep Reg OEh 26 1 begin sweep in positive direction Reg OEh 26 0 begin sweep in negative direction Direction Program ramp mode symmetrical Reg OEh 22 1 asymmetrical Reg Configure OEh 22 0 If symmetrical ramp mode is Selected Reg OEh 22 1 only Program Reg OEh 22 1 symmetrical Up sweep parameters will be used for both positive and negative sweeps neg 5 r Asymmetrical sweep is not defined asymmetrical and hence down sweep parameters don t need to be programmed In us in 1 Way Sweep mode sweep symmetrical ramp mode the positive and negative ramps are identical and opposite in direction Program Set dwell time dwell time 47 0 Reg 10h 29 0 dwell time 17 0 Reg 11h 17 0 6 Up Sweep Set step size step size 47 18 Reg 12h 29 0 step size 17 0 Reg 13h 17 0 Parameters Set the number of steps in a sweep nu
8. 50 MHz 2 us 1 50 MHz 100 Then as per Table 6 Reg 10h 29 0 Reg 06h 29 0 Oh and Reg 11h 17 0 Reg 07h 17 0 100d 64h Then proceed to configure the sweep according to the steps outlined in Table 6 Serial Port Interface The DC 7 GHz FRACTIONAL N DIVIDER features a four wire serial port for simple communication with the host controller Typical serial port operation can be run with SCK at speeds up to 30 MHz The details of SPI access for the DC 7 GHz FRACTIONAL N DIVIDER is provided in the following sections Note that the READ operation below is always preceded by a WRITE operation to Register 0 to define the register to be queried Also note that every READ cycle is also a WRITE cycle in that data sent to the SPI while reading the data will also be stored by the DC 7 GHz FRACTIONAL N DIVIDER when SENb goes high If this is not desired then it is suggested to write to Register 0 during the READ operation so that the status of the device will be unaffected For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC983LP5E MICROWAVE CORPORATION v02 0112 ROHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Power on Reset and Soft Reset The DC 7 GHz FRACTIONAL N DIVIDER has a b
9. BURR LENGTH SHALL BE 0 15 mm MAX PAD BURR HEIGHT SHALL BE 0 25 m MAX 7 PACKAGE WARP SHALL NOT EXCEED 0 05 mm 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND 9 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN Package Information Part Number Package Body Material Lead Finish MSL Rating P Package Marking DGGHERACTONALNDVMDER RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL1 o 1 4 Digit lot number XXXX 2 Max peak reflow temperature of 260 C For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC983LP5E MICROWAVE CORPORATION v02 0112 RoHSv DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Evaluation PCB e ee ov B BH a aq gt RFOUT i AAN XS 9 Bs lait y A gin 8 Oe E TUAM z a M 998 0 meeee 60060 00000 29 The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown unless mentioned otherwise A sufficient number of via holes should be used to connect the top and bottom ground p
10. Frequency Ramp MSB asymmetric frequency sweep mode valid when Reg OEh 11 1 Table 15 Reg 07h Fractional Set Point Down Dwell Register LSB BIT Inde NAME Ww DEFLT DESCRIPTION Least significant 18 bits to specify fractional set point for Sigma Fractional Division Rate LSB Delta Modulator Total Fractional bit are 48 17 0 R W 18 0 Down Dwell for Asymmetric Defines the LSB portion of the dwell down time in the asymmetric Frequency Ramp LSB frequency sweep mode valid when RegOE 11 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com EJ Hittite MICROWAVE CORPORATION v02 0112 RoHS v HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Table 16 Reg 08h GPIO Configuration Register BIT TYPE NAME Ww DEFLT DESCRIPTION Selects exported output signals to GPIO pins See Table 5 for details Master enable for GPIO Reg 01h 4 1 is required 8 0 R W GPO Output Select 4 Oh Static GPIO test signals for output D4 D3 D2 D1 DO Writing these value and reading them back test the GPIO functionality Master enable for GPIO Reg Oth 4 1 is required 8 4 R W GPO Static Test Value 5 00000b Independent GPIO pin enables 13 9
11. R W GPO Pin Enable 11111b Reg08 Reg08 Reg08 Reg08 Reg08 Reg08 Reg08 Reg08 Reg08 13 2 0 D4 input 13 1 D4 output 12 0 D3 input 12 1 D3 output 11 0 D2 input 11 1 D2 output 10 0 D1 input 10 1 D1 output 9 0 DO input RegO08 9 1 DO output Master enable for GPIO Reg 01h 4 1 is required Table 17 Reg 09h Companion Chip Address Local Register BIT TYPE NAME w DEFLT DESCRIPTION 2 0 R W Ferien HMCIGALPAE Chip 4 2h Chip address of the companion chip HMC984LP4E Table 18 Reg 0Ah Sigma Delta Modulator Seed MSB Register BIT TYPE NAME w DEFLT DESCRIPTION 29 0 R W Seed MSB 30 4241h Most significant bits of the Seed for the 1st accumulator in Sigma Delta Modulator Table 19 Reg OBh Sigma Delta Modulator Seed LSB Register BIT TYPE NAME Ww DEFLT DESCRIPTION 17 0 R W Seed LSB 18 10081h Least significant bits of the Seed for the 1st accumulator in Sigma Delta Modulator Table 20 Reg 0Ch Ramp NSTEP Do wn MSB Register LSB BIT TYPE NAME Ww DEFLT DESCRIPTION 29 0 R W Down Ramp Number of Steps 30 Oh Most significant bits of the number of steps for the frequency MSB ramp in down direction in sweep mode Table 21 Reg 0Dh Ramp NSTEP Down LSB Register BIT TYPE NAME Ww DEFLT DESCRIPTION 17 0 R W Down Ramp Number of Steps 18 Oh Least significant bits of the
12. exports data back on the SDO line For details see the section on READ operation Serial Port READ Operation The SPI can read from the internal registers in the chip The data is available on SDO pin This pin itself is tri stated when the device is not being addressed However when the device is active and has been addressed by the SPI master the DC 7 GHz FRACTIONAL N DIVIDER controls the SDO pin and exports data on this pin during the next SPI cycle DC 7 GHz FRACTIONAL N DIVIDER changes the data to the host on the rising edge of SCK and the host reads the data from DC 7 GHz FRACTIONAL N DIVIDER on the falling edge A typical READ cycle is shown in Figure 28 Read cycle is 40 clock cycles long To specifically read a register the address of that register must be written to dedicated Reg Oh This requires two full cycles one to write the required address and a 2nd to retrieve the data A read cycle can then be initiated as follows 1 The host asserts SENb active low Serial Port Enable followed by a rising edge SCK 2 DC 7 GHz FRACTIONAL N DIVIDER reads SDI the MSB on the 1 rising edge of SCK after SENb 3 DC 7 GHz FRACTIONAL N DIVIDER registers the data bits in the next 29 rising edges of SCK total of 30 data bits The LSBs of the data bits represent the address of the register that is intended to be read 4 Host places the 7 register address bits on the next7 falling edges of SCK MSB to LSB while the DC 7 GHz FRA
13. external clock from GPIO pin to clock DSM 28 R W Reserved 1 0 29 R W Use x16 CSP Step 1 0 s poem the CSP step size given in bits 18 15 by a factor Table 23 Reg OFh VCO Divider Configuration Register BIT TYPE NAME Ww DEFLT DESCRIPTION 0 R W Increase Divider Pulse width 1 0 Increase the width of the clock pulse going to DSM available to DSM only when division ratio 64 1 R W ELE Divider Pulsewigthto 1 1 Increase pulse width low duration of the clock going to PFD Sets current for divider output buffer Helps to control voltage swing for various impedance options 000 5mA 001 2 7 5mA 010 10mA 4 2 R W Output Buffer Current Select 2 011b 011 12 5mA 100 10mA 101 12 5mA 110 2 15mA 111 17 5mA 5 R W Reset RF Divider 1 0 Resets the RF Divider 8 6 R W Divider Resynch Bias Select 8 011b Pessina E for divider resyng Defaultvalue 11 9 R W RF Buffer Bias Select 3 001b Si nai for input RF buffer Default value Divider output pulse width control 000 5 VCO cycles 001 13 VCO cycles 010 21 VCO cycles 14 12 R W Divider Pulsewidth Select 3 011b 011 29 VCO cycles 100 37 VCO cycles 101 45 VCO cycles 110 53 VCO cycles 111 2 61 VCO cycles Table 24 Reg 10h Ramp DWELL Symmetrical or Up MSB Register BIT TYPE NAME Ww DEFLT DESCRIPTION Represents MSB s for ramp dwell time in up and down directions 29 0 R W Symmetric Ramp Dwell MSB 30 0 for symmetric frequency sweep mode In asymmetric mode it
14. external trigger input External trigger on pin D4 is triggered on the rising edge of the trigger GPIO master enable Reg 01h 4 1 is also required For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H U D as O H O LLI H LLI Q D as LLI gt e gt O Z LLI 6 LLI oc LL H Q QD oc O H O LLI H LLI Q D as LLI gt e gt O Z LLI ED 6 LLI oc LL eerdittite awtcosatpse MICROWAVE CORPORATION v02 0112 RoHS DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY e External triggering method can be synchronized with the reference clock by enabling trigger delay Reg OEh 7 1 and programming a trigger delay in Reg 05h 20 0 number of delayed reference periods Writing Reg 05h 20 0 1 for example ensures that the trigger is applied at the instant of the rising edge of the next reference rising edge To disable trigger delay write Reg OEh 7 0 2 Way Sweep Mode DC 7 GHz FRACTIONAL N DIVIDER s 2 Way sweep mode is shown in Figure 25 The 2 Way sweep mode can be automatic or triggered In automatic 2 way sweep the trigger is generated internally based on user defined 2 way sweep mode configuration In a triggered 2 way sweep frequ
15. frequency Functional Diagram H D D oc O H O LLI H LLI Q D as LLI gt e gt O Z LL ED 6 LLI oc LL o z 8 k 8 EE divider applications that require exceptional spurious DENEN SER M RR IN performance 1 a 8 s s s lg Although the DC 7 GHz FRACTIONAL N DIVIDER SENb 1 l l 4 cuiP1 can work with any VCO and or compatible Phase Eg Detector best performance and features will be ae es pal DATA PESISTER AND 3P Ein REESEN achieved when paired with the companion part the SCK i Y 22 D4 HMC984LP4E D1 48 BIT S Lt erz ps Fabricated in SiGe BiCMOS process the SS DC 7 GHz FRACTIONAL N DIVIDER features a BO Y 20 D2 48 bit Delta Sigma Fractional Modulator DSM with VCO SCK M CEQUNTER 79 VDDM programmable phase accumulator size enabling precise control of frequency step size and resolution GOSEN 18 MNCEPEDR Integrated DSM can generate frequencies with nearly VCO SDO 17 aNwCKPFDn 0 Hz frequency error The DSM also includes a built in programmable frequency sweep capability with fel el E e eye 2 various automatic and user defined sweep modes and 2 8 Z 255592 PACKAGE triggering options including hardware trigger pin or a az g g 2 B z GND SPI trigg
16. in auto sweep the new sweep will start immediately after the 2nd trigger as it does in 2 Way mode User Defined Sweep Mode In User Defined Sweep mode the DC 7 GHz FRACTIONAL N DIVIDER is able to generate various user defined sweep patterns by adjusting the time interval between adjacent frequency increments which are executed by trigger events DC 7 GHz FRACTIONAL N DIVIDER s User Defined Sweep Mode is shown in Figure 27 In this mode an external trigger is required for each frequency increment of the sweep For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H U D or e H O Ti H IT e o D a T QO 2 e gt O Z T 5 O LL oc TE H QD D or e H O Ti H IT e o D a TT 2 m gt O Z TT O Li a TE EMI EEICE mmcosaLpse MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Ramp Up Tramp NENNEN Tawell i d 4 1 2 35 4 n n 1 n 2 trigger sweep_busy Figure 27 DC 7 GHz FRACTIONAL N DIVIDER User Defined Sweep User defined sweep can function in both 1 Way or 2 Way sweep mode In 1 Way sweep mode the n 1 trigger will cause the ramp to jump to the start frequency and the n 2 trigger will restart the 1 way sweep ra
17. oc LL H D D oc O H O LLI H LLI Q D as LLI gt e gt O z LLI ED 6 LLI oc LL E Hittite MICROWAVE CORPORATION 02 0112 RoHS v EARTH FRIENDLY Figure 1 RF Input Sensitivity v 40 20 20 40 RF INPUT POWER dBm 60 80 0 2000 4000 6000 8000 10000 RF INPUT FREQUENCY MHz Figure 3 Output Phase Noise with 6 GHz Input in Integer Mode 60 80 100 120 140 PHASE NOISE dBc Hz 160 180 200 ail iani in 10 10 10 10 10 107 10 OFFSET FREQUENCY Hz Figure 5 Time Domain 18 MHz Output 6 5 GHz Input 5 5 A u 5 F o gt E a 5 45 o 4 0 50 100 150 200 TIME ns 1 The maximum and minimum DC 7 GHz FRACTIONAL N DIVIDER Performance 0 dBm for frequencies higher than 6500 MHz HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Figure 2 Output Phase Noise 6 GHz Input Frequency 2 60 80 tN z Output Frequency Frat 100 _ 120 140 PHASE NOISE dBc Hz 160 180 200 10 10 10 10 10 10 10 OFFSET FREQUENCY Hz Figure 4 Time Domain 10 MHz Output 6 5 GHz Input 5 5 divCkPFDp Pin Output OUTOUT VOLTAGE V divCkPFDn Pin Output 0 50 100 150 200 250 300 350 TIME ns Figure 6 Time Domain 35 MHz Output 6 5 GHz Input 5 5 divCkPFDp Pin Output EN OUTP
18. part of frequency division ratio set in Reg 05h 19 0 Nirac is the fractional part of frequency division ratio Nfacl47 18 Reg 06h 29 0 Nya 17 0 Reg 07h 17 0 R is the reference frequency division ratio L is the size of the DSM accumulators set in Reg 16h 5 0 Example 1 Calculate the VCO frequency with the following parameters fsa 90 MHz fg 25 MHz Nn 25 N 1 Where fpgp is the frequency at the phase detector thus R 2 According to Eq 1 the VCO frequency with the above parameters will be L 24 frac For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com T D as O H O LLI H LLI Q D as LLI gt e gt O Z LLI O LLI oc LL H D D oc O H O LLI H LLI Q D as LLI gt e gt O Z LLI ED 6 LLI oc LL eeriittite mmcosaLpse MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY _ SOMHZz 50MHz f 254 1 2500MHz 1 49Hz vco 2 2 924 If accumulator width L is changed to 48 bit then the frequency resolution will improve and the fractional resolution of the VCO frequency will be 88 8178 nano Hz Example 2 Set the VCO frequency to 4600 025 MHz using 100 MHz Crystal R 2 a
19. value for reference division ratio Auxiliary SPI Registers The following two registers define the communication through the AUXSPI If the AUXSPI is enabled Reg O4h 4 0 writes to AUXSPI are executed via Reg 03h The auxiliary device address is expected in Reg 04h 2 0 If DC 7 GHz FRACTIONAL N DIVIDER is working as a standalone frequency divider the AUXSPI clock is expected on the DNSAT pin and Reg 04h 15 must be set to 1 It is recommended to disable AUXSPI when not used Table 11 Reg 03h AUX VCO Data Register BIT TYPE NAME Ww DEFLT DESCRIPTION 3 0 R W AUXSPI Register Address 4 Oh 4 bit Register address for the auxiliary device SPI 12 4 R W AUXSPI Data 9 000h 9 bit long Register Data for the auxiliary device SPI For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com T D as O H O LLI H LLI Q D as LLI gt e gt O Z LLI D ie LLI oc LL H Q QD as O H O LLI H LLI Q o D oc LLI gt e gt O Z LLI D O LLI oc LL Perittite mmcosaLpse MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Table 12 Reg 04h AUX VCO Settings Register
20. when SENb is de asserted It is recommended that during the second phase of the READ operation that Reg 00h is addressed with either the same address or the address of another register to be read during the next cycle SEN 0 1 28 29 30 31 34 35 36 37 38 39 from Master ts t7 SCK from Master e d from Master Xoz9_X028 627 Coi po X A6 X ally A2 X A1 X ao XCA2 X CA1 X CAO y ts soo COC C Ja X O C OC OCOCOCOCLED To Master ts te Figure 28 SPI Timing Diagram DVDD 5 V 10 GND 0 V Table 7 Main SPI Timing Characteristics H D D oc O H O LLI H LLI Q D as LLI gt e gt O Z LLI D O LLI oc LL Parameter Conditions Min Typ Max Units ty SDI to SCK Setup Time 8 nsec to SDI to SCK Hold Time 8 nsec tg SCK High Duration 1 10 nsec t4 SCK Low Duration 10 nsec t5 SENb Low Duration 20 nsec te SENb High Duration 20 nsec t7 SCK to SENb 2 8 nsec tg SCK to SDO out 3 8 nsec 1 The SPI is relatively insensitive to the duty cycle of SCK 2 SENb must rise after the 32 falling edge of SCK but before the next rising SCK edge If SCK is shared amongst several devices this timing must be respected 3 Typical load to SDO is 10 pF maximum 20 pF For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hi
21. 1st accumulator width 00 48 bits 1 0 R W DSM 1st Accumulator Size 2 00b 01 2 32 bits 10 24 bits 11 16 bits DSM 2nd accumulator width 00 48 bits 3 2 R W DSM 2nd Accumulator Size 2 00b 01 32 bits 10 24 bits 11 16 bits DSM 3rd accumulator width 00 48 bits 5 4 R W DSM 3rd Accumulator Size 00b 01 32 bits 10 24 bits 11 16 bits 8 6 R W Disable Frac Register Clock 000b Clock gates for the 3 accumulators fractional part 1 disables the clock 11 9 R W Disable Integer Register Clock 000b es gates for the 3 accumulators integer part 1 disables the 12 R W Disable DSM Mode A Clock 0 1 Disable Delta Sigma Modulator Mode A Clock 13 R W Disable DSM Mode B Clock 0 1 Disable Delta Sigma Modulator Mode B Clock 14 R W Reserved 0 15 R W Disable Integer Path Clock 0 1 Disables Integer Path Clock 16 R W Disable Input Buffer Clock 0 1 Disables Input Buffer Clock 17 R W Disable Output Buffer Clock 0 1 Disables Output Buffer Clock 18 R W Reserved 1 0 19 R W Reserved 1 0 Table 31 Reg 17h This Register does not exist BIT TYPE NAME Ww DEFLT DESCRIPTION This Register does not exist Table 32 Reg 19h Ramp Down Step Size MSB Register BIT TYPE NAME Ww DEFLT DESCRIPTION 29 0 R W Ramp Step Down MSB 30 0 Represents MSB s to define the step size for the ramp in down direction in ramp mode Table 33 Reg 1Ah Ramp Down Step Size LSB Re
22. 50 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H T N as O H O LLI H LLI Q D as LLI gt e gt O Z LLI O LLI oc HE H Q QD oc O H O LLI H LLI Q D as LLI gt e gt O Z LLI ED 6 LLI oc LL Cerdittite mmcosaLpse MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER PADDLE GND ESD j VCCHF 1V VCOIN 100 LOAD VCCHF 100 VCOIP K esp VCCHF 1V EN VA PADDLE GND 4mA Figure 20 RF Input Stage RF Path Fractional N Divider The RF input buffer is followed by a high frequency prescaler and a multi modulus divider The divider has been designed for the best output phase noise and spurious performance in both fractional and integer mode The fractional N divider can divide input frequencies from 32 to 220 1 1048575 in integer mode and from 36 to 220 5 1048571 in fractional N mode The divider output pulse width depends on the RF input period and is adjustable via SPI setting refer to Duty Cycle Setting in register Reg 00h Chip ID Soft Reset Read Register 14 12 The output pulse width recommended setting is 40 to 60 where possible At low output frequencies it may not be possible to set 50 duty cycle In such cases the maximum pulse width setting is recommended RF BUFFER N DIVIDER 7GHz OUTPUT BUFFER VCOIP 20B
23. 7 GHz FRACTIONAL N DIVIDER In such cases the DC 7 GHz FRACTIONAL N DIVIDER is able to recognize an SPI command to the companion part the AND FREQUENCY SWEEPER that requires its own action and act accordingly to update its own corresponding For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H U D as O H O LLI H LLI Q D as LLI 2 e gt O Z LLI 6 LLI oc LL H D D oc O H O LLI H LLI Q D as LLI gt e gt O z LLI ie LLI oc LL E Hittite HMC983LP5E MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY registers Writing DC 7 GHz FRACTIONAL N DIVIDER s own chip address to the companion chip address register Reg 09h will disable this feature Saturation Detection Input Pins DNSAT UPSAT When the DC 7 GHz FRACTIONAL N DIVIDER is operating with its companion chip the AND FREQUENCY SWEEPER as a frequency synthesizer it automatically detects large phase errors and tries to tune the VCO faster by using its algorithm for cycle slip prevention CSP The UPSAT and DNSAT provide indication which frequency is higher VCO or Reference from the counterpart Phase Detector Charge Pump the AND FREQUENCY SWEEPE
24. A Steps 5 12 5 17 5 mA Output Voltage Swing Single Ended Vpullup 5 V 0 75 1 2 V a e Z me Fractional Mode Mode A and Mode B DC 125 Phase Noise 50 MHz PFD 6 GHz Input Integer Mode 160 dBc Hz Fractional Spurious Mis o ee 95 85 dBc Logic Inputs Input High Voltage VIH DVDD 0 4 Input Low Voltage VIL 0 4 Logic Outputs Output High Voltage VOH DVDD 0 4 Output Low Voltage VOL 0 4 DC Load 1 5 mA Serial Port Clock Frequency Main SPI and AUXSPI 30 MHz Power Supplies AVDD VCCPS VCCHF Analog Supplies AVDD should be equal 27 3 33 v to DVDD VPPBUF Output Buffer Supply 4 5 5 5 5 VDDM DVDD Digital Supplies 2 7 3 3 3 Current Consumption IDD Total Current Consumption ir Mi 104 122 mA AVDD AVDD Current 3 V Integer Mode Fractional Mode 5 5 mA VCCPS VCCPS Current 3 V Integer Mode Fractional Mode 79 79 mA VCCHF VCCHF Current 3 V Integer Mode Fractional Mode 8 8 mA VDDM VDDM Current 3 V Integer Mode Fractional Mode 11 11 mA DVDD Total DVDD Current 3 V Integer Mode Fractional Mode 1 19 mA VPPBUF Total VPPBUF Current 5V 5 uA For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com D D as O H O LLI H LLI Q D as LLI gt e gt O Z LLI O LLI
25. ANALOG HittiLc DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK eervittite HMC983LP5E MICROWAVE CORPORATION vo2 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Typical Applications Features Continued The DC 7 GHz FRACTIONAL N DIVIDER is suitable Integrated Frequency Sweeper oF Linear Coherent Sweeps Test Equipment 2 Way 1 Way amp User Defined Sweep Modes Portable Instruments Automatic or Triggered i Programmable Seed High Performance Fractional N Frequency Synthe SPI amp External Triggering sizers with Ultra Low Spurious 5 GPIO s can be used for External DSM Stand Alone Divider and or Delta Sigma Modulator Cycle Slip Prevention Support with PFD Chip Features HMC984LP4E Wideband DC 7 GHz Input Differential VCO Input amp Divider Output peo Frequency Divider Programmable Output Current Control Low Noise 160 dBc Hz 5 mA to 17 5 mA Open Collector Output Driver Low Spurious Largest Spurious 95 dBc 32 pin 5 x 5mm LP5 Package 48 bit 100 MHz Delta Sigma Modulator DSM Configurable DSM Size Programmable Seed Phase Step General Description DC 7 GHz FRACTIONAL N DIVIDER is a fractional frequency divider targeted for fractional N frequency synthesis and stand alone low noise
26. CTIONAL N DIVIDER reads the address bits on the corresponding rising edge of SCK For a read operation this is 0000000 5 Host places the 3 chip address bits 111 on the next 3 falling edges of SCK MSB to LSB 6 SENb goes from low to high after the 40th rising edge of SCK This completes the first portion of the READ cycle 7 The host asserts SENb active low Serial Port Enable followed by a rising edge SCK For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H T N as O H O LLI H LLI Q D as LLI gt e gt O Z LLI 6 LLI oc LL ESMIEEIC 5 nwcessiesE MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY 8 DC 7 GHz FRACTIONAL N DIVIDER places the 30 data bits 7 address bits and 3 chip id bits on the SDO on each rising edge of the SCK commencing with the first rising edge beginning with MSB 9 The host de asserts SENb i e sets SENb high after reading the 40 bits from the SDO output The 40 bits consists of 30 data bits 7 address bits and the 3 chip id bits This completes the read cycle Note that the data sent to the DC 7 GHz FRACTIONAL N DIVIDER SPI during this portion of the READ operation is stored in the SPI
27. EEPER EARTH FRIENDLY VPPBUF SUPPLY 3 D S 9 j Di I Figure 22 Generic Divider Output Interface SUPPLY INTERNAL PULL UP RESISTORS lol 10 250 ra y o i Figure 23 Divider Interface with AND FREQUENCY SWEEPER Chip Address Pins The DC 7 GHz FRACTIONAL N DIVIDER has three SPI chip address pins SPI address 2 0 CHIP3 CHIP2 CHIP1 which enable multiple DC 7 GHz FRACTIONAL N DIVIDER devices to use the same SPI bus SPI chip address bits are read at power up or every time DC 7 GHz FRACTIONAL N DIVIDER is reset By default all three pins are internally pulled to DVDD thus there is no need to connect the pins to DVDD to set them to logic high To assign a 0 to any chip address bit the corresponding pin should be connected to ground Whenusedonthesame SPIbustogetherwiththecompanion part the AND FREQUENCY SWEEPER toformafrequency synthesizer some SPI commands such as changing the reference division ratio to the AND FREQUENCY SWEEPER may also require an action by the DC 7 GHz FRACTIONAL N DIVIDER In order to avoid the necessity to write two separate SPI transfers to implement one command one to configure AND FREQUENCY SWEEPER and the other one to configure the DC 7 GHz FRACTIONAL N DIVIDER it is possible to write the SPI address of the companion part AND FREQUENCY SWEEPER into Reg 09h of the DC
28. IONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY In all sweep modes the starting sweep direction can be set to positive increasing or negative decreasing The trigger can be applied instantaneously or delayed by a programmable time delay DC 7 GHz FRACTIONAL N DIVIDER s sweep function is illustrated in Figure 24 The DC 7 GHz FRACTIONAL N DIVIDER generates a frequency sweep by implementing automatic or triggered in User Defined Mode discrete miniature frequency increments in time A smooth and continuous sweep is then generated at the output of the VCO after the stepped signal is filtered by the loop filter as shown in Figure 24 The stepped sweep approach enables the frequency synthesizer comprising of DC 7 GHz FRACTIONAL N DIVIDER together with its counterpart the HMC984LPAE to be in lock for the entire duration of the sweep This approach results in a number of advantages over conventional methods including e The ability to generate a linear sweep e The ability to have phase coherence between different sweep ramps so that the phase profile of each sweep is identical e The ability to generate user defined sweeps in User Defined Sweep Mode mnm Cd TE Crystal Oscillator HMC983LPSE HMC984LP4E Loop Filter VTUNE RF Out T su vco dE ER N B p od ES C a N BL Ramp Up Ramp Down Ramp Up Ramp Down Trump Tramp
29. IT N VCOIN CONTROL Figure 21 Divider Path Divider Output Buffer The divider output is differential and the output buffer stage is an open collector amplifier with off chip pull up resistors Due to sharp rise and fall times at the divider output the external path should be designed differentially using RF techniques When DC 7 GHz FRACTIONAL N DIVIDER and AND FREQUENCY SWEEPER are operating together as a frequency synthesizer 50 Q pull up resistors are provided in AND FREQUENCY SWEEPER VPPBUF pin should be connectedto 5 V power supply This pin does notsink DC currentandis only usedtobiasthe internal ESD diodes and to provide an appropriate voltage level for the phase detector chip AND FREQUENCY SWEEPER The two possible interface configurations are shown in Figure 22 and Figure 23 below The rising edge of the HMC983LP5E divider output divCkPFDp and falling edge of divCkPFDn are conditioned and re synchronized for best spectral performance The alternative edges are not This means for best spectral performance the HMC983LP5E must be used with a PFD not an analog mixer For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC983LP5E MICROWAVE CORPORATION v02 0112 ROHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SW
30. NCY MHz Figure 16 One Way Frequency Sweep 10 MHz PFD and 10 Hz external trigger 7000 6900 6800 6700 FREQUENCY MHz 6600 6500 6400 0 200 400 600 800 1000 TIME ms Figure 18 PLL Cycle Slip Prevention 50 MHz PFD s 7050 4i 7000 CSP Enabled 6950 i CSP Enabled 7 RegOEh 1 8 15 5h 6900 6850 6800 L a PLL OUTPUT FREQUENCY GH 6750 6700 TIME us 6 Measured with 50 O impedance per line Buffer current is controled via Reg OFh 4 2 7 Measured with 50 impedance per line Buffer current is controled via Reg OFh 4 2 8 Measured with HUC983LP5E HMC984LP4E chip set as fractional N synthesizer Crystal input frequency 100 MHz CP current 2 5 mA CP offset current 245 uA Loop filter bandwidth 87 KHz DSM Mode B selected Cycle Slip Prevention CSP is disabled in HMC984LPA4E by setting Reg Oth 4 0 Setting Reg 01h 4 1 enables CSP in the two chip PLL For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t T Hittite HMC983LP5E MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Table 2 Pin Descriptions
31. R The CSP algorithm manipulates the RF Divider and the Phase Detector at appropriate intervals to lock faster See AND FREQUENCY SWEEPER data sheet for more details These pins should be connected to ground if not used REF Eno Pin REF Eno pin is a digital output pin that is used by the DC 7 GHz FRACTIONAL N DIVIDER to request crystal oscillator clock from the Phase Detector Charge Pump chip the AND FREQUENCY SWEEPER The crystal oscillator clock is multiplexed on the DC 7 GHz FRACTIONAL N DIVIDER s DNSAT pin The internal frequency divider programmed in Reg 02h is used to generate the actual reference frequency present at the phase detector The imported clock is only used to communicate through the AUXSPI At all other times the clock and the local reference dividers are turned off In stand alone applications if the DC 7 GHz FRACTIONAL N DIVIDER is required to communicate through the auxiliary SPI the DC 7 GHz FRACTIONAL N DIVIDER will expect to receive the auxiliary SPI clock on DNSAT pin Setting Reg 04h 15 1 keeps the auxiliary SPI clock enabled on the DNSAT pin Multi Purpose Digital IO Pins DO D1 D2 D3 D4 GPIO Pins The five general purpose digital input outputs can be used for various modes of operation as well as test debugging purposes GPIO pins are enabled by writing Reg O1h 4 1 GPIO master enable Setting Reg O1h 4 0 places the GPIO pins in tri state high impedance mode GPIO pins are configured in
32. ROWAVE CORPORATION v02 0112 RoHS v EARTH FRIENDLY Table 5 GPIO Pin Assignment and Output Signals HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Y RS DC 7 GHz FRACTIONAL N DIVIDER GPIO Pins ieg O8h 3 0 E T i D4 D3 D2 D1 DO 0110 reserved reserved reserved 0 0 0111 reserved reserved reserved reserved reserved 1000 ramp ready flag ramp start flag ramp stop flag ramp busy falg reserved 1001 1111 0 0 0 0 0 Fractional Mode of Operation In addition to providing simple integer division ratios the DC 7 GHz FRACTIONAL N DIVIDER has a sophisticated configurable 48 bit Delta Sigma Modulator DSM that allows fractional division of the input frequency in ultra fine steps The DSM s size can be configured to 16 24 32 48 bits Reg 16h 5 0 DC 7 GHz FRACTIONAL N DIVIDER s auto seed mode allows coherent frequency sweeps The DC 7 GHz FRACTIONAL N DIVIDER with its counterpart the AND FREQUENCY SWEEPER together with an external VCO comprise a fully functional fractional N synthesizer In that case the output frequency of the external VCO is given by f f fco a Nit OST Ns lint frac Eq 1 When the DC 7 GHz FRACTIONAL N DIVIDER is being used as frequency divider the output frequency is given by fut 22 Eq 2 Nint a Where fuco is the VCO frequency in Hz ftal is the crystal oscillator frequency in Hz Nin is the integer
33. Reg 08h 13 0 All of the pins can configured to be either inputs or outputs by writing to Reg 08h 13 9 In frequency sweep mode pin D4 can be used as an external trigger pin by writing Reg O8h 13 0 Writing to Reg O8h 3 0 selects DC 7 GHz FRACTIONAL N DIVIDER S internal signals to be multiplexed out on the GPIO pins as shown in Table 5 Signals include 1 The output of the Delta Sigma Modulator Reg O8h 3 0 0010 b 2 GPIO test signals Reg O8h 3 0 0000 b which outputs data written to Reg O8h 8 4 to test the GPIO pins 3 Sweep status flags when the DC 7 GHz FRACTIONAL N DIVIDER is configured to be in sweep mode Reg O8h 3 0 1000 b Table 5 GPIO Pin Assignment and Output Signals DC 7 GHz FRACTIONAL N DIVIDER GPIO Pins D4 D3 D2 D1 DO leg 08h 3 0 0000 gpo test out 4 gpo test out 3 gpo test out 2 gpo test out 1 gpo test out 0 0001 reserved reserved reserved reserved reserved 0010 DSM_OUT 4 DSM_OUT 3 DSM_OUT 2 DSM_OUT 1 DSM_OUT 0 0011 reserved reserved reserved reserved reserved 0100 reserved reserved reserved reserved reserved 0101 reserved reserved reserved reserved reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com E Hittite MIC
34. T SWING Vpp OUTPUT BUFFER CURRENT mA 4 Measured with 50 Q impedance per line integer Mode 15 mA Output Buffer Current Reg OFh 4 2 selected 5 Measured with 50 Q impedance per line integer Mode 15 mA Output Buffer Current Reg OFh 4 2 selected For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H T N as O H O LLI H LLI Q D as LLI gt e gt O Z LLI 6 LLI oc LL H D D oc O H O LLI H LLI Q D as LLI gt e gt O z LLI ED 6 LLI oc LL E Hittite MICROWAVE CORPORATION 02 0112 RoHS v EARTH FRIENDLY Figure 13 100 MHz Output Swing vs Buffer Current 0 9 0 85 0 8 SINGLE ENDED OUTPUT SWING Vpp OUTPUT BUFFER CURRENT mA Figure 15 Two Way Frequency Sweep 50 MHz PFD s 7000 FREQUENCY MHz 0 5 10 15 20 TIME ms Figure 17 PLL Cycle Slip Prevention 100 MHz PFD 7050 CSP Enabled Reg0Eh 18 15 1h Mu A e e o CSP Enabled 7 RegOEh 18 15 8h PLL OUTPUT FREQUENCY MHz 0 50 100 150 200 250 300 TIME us HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Figure 14 Input Return Loss 0 RETURN LOSS dB 3 0 2000 4000 6000 8000 FREQUE
35. UT VOLTAGE V 0 20 40 60 80 100 TIME ns indicate operational limits of the may degrade with input power greater than 2 Due to Delta Sigma modulation in fractional mode the output phase noise peaks at frequency offset of fout 2 from the output Agilent MXG N5182A used as a signal source 3 Rohde amp Schwarz SMBV100A used as a signal source For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com EJ Hittite MICROWAVE CORPORATION v02 0112 RoHS v EARTH FRIENDLY Figure 7 Time Domain 124 MHz Output 6 5 GHz Input 5 5 OUTPUT VOLTAGE V TIME ns Figure 9 Time Domain 61 MHz Output 6 5 GHz Input 55 OUTPUT VOLTAGE V TIME ns Figure 11 10 MHz Output Swing vs Buffer Current 0 9 0 85 0 8 SINGLE ENDED OUTPUT SWING Vpp OUTPUT BUFFER CURRENT mA HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Figure 8 Time Domain 66 MHz Output 6 5 GHz Input OUTPUT VOLTAGE V 7 divCkPFDn Pin Output TIME ns Figure 10 Time Domain 66 MHz Output 6 5 GHz Input 5 5 divCkPFDp Pin Output iR OUTPUT VOLTAGE V TIME ns Figure 12 50 MHz Output Swing vs Buffer Current 0 9 0 85 0 8 0 75 0 7 0 65 SINGLE ENDED OUTPU
36. e 2 and Figure 3 As a result it is not possible to achieve the same noise floor in fractional mode as in integer mode without further filtering CW Frequency Sweeper The DC 7 GHz FRACTIONAL N DIVIDER features a built in frequency sweeper function that supports automatic or externally triggered sweeps External triggering can be executed via an external trigger pin D4 or the SPI interface DC 7 GHz FRACTIONAL N DIVIDER sweep function can be configured to operate in the following modes e 2 Way sweep mode e Repeating alternating positive and negative frequency sweep ramps e Frequency increments swept with automatic sequencer e Automatic or triggered e Symmetric or asymmetric the positive ramp can have a different slope from that of the negative ramp e 1 Way Sweep Mode e Repeating one directional frequency sweeps followed by a reset to the starting frequency e Frequency increments swept with automatic sequencer e Triggered User defined sweep mode e Manually programmed user defined sweep patterns e Triggered e Symmetric or asymmetric the positive ramp can have a different slope from that of the negative ramp For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC983LP5E MICROWAVE CORPORATION v02 0112 ROHS v DC 7 GHz FRACT
37. e Pin for Open Collector Divider Output Driver 18 divCkPFDp Positive Pin for Open Collector Divider Output Driver z 5 19 VDDM 3V Supply Pin for Digital Section of the Frequency Divider OE F D2 20 D2 GPIO bit 2 O ps 21 D3 GPIO bit 3 D4 22 D4 GPIO bit 4 Gate Control Output to request TCXO Clock Export from H QD D or e H O ri LL IT e o D a TT 2 m gt O Z TT O LL a TE S REF Eno HMC984LP4E DVDD Q 4 ES 24 CHIP1 Chip Address Pin 1 CHIP 25 CHIP2 Chip Address Pin 2 nino 26 CHIPS Chip Address Pin 3 CHIP3 L l 27 30 DVDD 3V Power Supply for Digital o PVDD e DNSAT 28 DNSAT VCO Saturation Input flag from HMC984LP4E Chip For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com tT Hittite HMC983LP5E MICROWAVE CORPORATION v02 0112 RoHS DC 7 GHz FRACTIONAL N DIVIDER E AND FREQUENCY SWEEPER Table 2 Pin Descriptions Continued Pin Number Function l Description Interface Schematic DVDD 29 UPSAT Reference Saturation Input flag from HMC984LP4E Chip HPAL G DVDD 31 CEN Chip E
38. ecification Operating Temperature Range 40 C to 85 C i 3 pem 3 is not implied Exposure to absolute maximum rating conditions for Maximum Junction Temperature 125 C extended periods may affect device reliability Storage Temperature 65 to 4125 C ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Outline Drawing H Q QD as O H O LLI H LLI Q o D oc LLI gt e gt O Z LLI D ie LU oc LL TOP VIEW BOTTOM VIEW 012 938 201 5 10 007 DH 016 0 40 REF be 193 4 90 008 0 20 MIN 32 25 gt J D 1 24 a D c1 r ma N PIN 1 H983 9 oi aa x s rs XXXX E penati on 022 0 56 SS Im po 535 8 17 2 cj E D 9 16 LOT NUMBER r 33 88 sova L 039 2 L 031 0 80 002 0 05 NOTES 000 0 00 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED i 7 SEATING 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY i PLANE 3 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN 003 0 08 c Cc 4 DIMENSIONS ARE IN INCHES MILLIMETERS 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 PAD
39. ency ramps are triggered either by external pin D4 or SPI trigger Ramp Up Ramp Down Tramp c Tawell Tramp Tawell n Tref ramp_step ramp_busy Figure 25 DC 7 GHz FRACTIONAL N DIVIDER 2 Way Triggered Sweep Triggered 1 Way Sweeps DC 7 GHz FRACTIONAL N DIVIDER s 1 Way sweeps is shown in Figure 26 Unlike 2 Way sweeps 1 Way sweeps require that the VCO hop back to the start frequency after the dwell period Triggered 1 Way sweeps also require a 3rd trigger to start the new sweep The 3rd trigger must be timed appropriately to allow the VCO to settle after the large frequency hop back to the start frequency Subsequent odd numbered triggers will start each sweep and repeat the process For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com tT Hittite HMC983LP5E MICROWAVE CORPORATION v02 0112 RoHS DC 7 GHz FRACTIONAL N DIVIDER E AND FREQUENCY SWEEPER Ramp Up Ramp Up M Tramp Tramp e fg re EM a ramp_steps_number n Lm ramp step ramp step 2 4 i Tref 1 trigger j trigger _ sweep_busy Figure 26 DC 7 GHz FRACTIONAL N DIVIDER 1 Way Triggered Sweep 1 Way sweeps are not recommended in auto sweep mode since
40. er with optional delayed trigger DC 7 GHz FRACTIONAL N DIVIDER is a versatile part capable of various configurations It has 5 general purpose I Os GPIOs DSM outputs are made available from the GPIO port enabling the DC 7 GHz FRACTIONAL N DIVIDER to import and or export DSM sequences for various configuration options DC 7 GHz FRACTIONAL N DIVIDER divider outputs are differential open collector with programmable current to accommodate different off chip loads For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com EJ Hittite MICROWAVE CORPORATION v02 0112 RoHSv EARTH FRIENDLY HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Table 1 Electrical Specifications TA 25 C AVDD VCCPS VCCHF VDDM DVDD 3 V 10 VPPBUF 5 V 10 GND 0 V Parameter Conditions Min Typ Max Units RF Input Characteristics RF Input Frequency range DC 7 GHz RF Input Sensitivity 15 10 0 dBm RF Input Capacitance External Match Recommended 3 pF Divider Range 20 bit Integer Mode 32 1 048 575 Fractional Mode 36 1 048 571 Divider Output Characteristics Output Buffer Current Programmable in 2 5 m
41. gister BIT TYPE NAME Ww DEFLT DESCRIPTION 17 0 R W Ramp Step Down LSB 18 0 Represents LSB s to define the step size for the ramp in down direction in ramp mode For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com D D as O H O LLI H LLI Q D as LLI gt e gt O Z LLI 6 LLI oc LL
42. ith HMC983LP5E to Form a Frequency Synthesizer The DC 7 GHz FRACTIONAL N DIVIDER consists of the following functional blocks 1 RF Input Buffer 2 7 GHz Frequency Prescaler and Multi Modulus Divider 3 48 bit Configurable Fractional Delta Sigma Modulator 4 Bias Circuit 5 Differential Output Driver 6 Frequency Sweeper 7 Main Serial Port Interface 8 Auxiliary Serial Port Interface Output Only 9 General Purpose Digital lO 10 Power On Reset Circuit RF Input Buffer The RF input stage provides the path from the external VCO to the fractional RF Divider The RF input path is rated to operate nominally from DC to 7 GHz The DC 7 GHz FRACTIONAL N DIVIDER RF input stage is a differential common emitter stage with DC coupling and is protected by ESD diodes as shown in Figure 20 RF input is not matched to 50 Q due to wide input frequency range At low frequencies a simple shunt 50 Q resistor can be used external to the package to provide a 50 O match For better performance it is recommended to match the RF inputs externally and provide differential drive from the VCO In most applications the input is used single ended into either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking capacitor The preferred input level for best spectral performance is 10 dBm For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 2
43. lanes The evaluation circuit board shown is available from Hittite upon request Table 4 Evaluation Order Information Item Contents Part Number DC 7 GHz FRACTIONAL N DIVIDER and HMC984LP4E PLL Chipset Evaluation PCB USB Interface Board E K I T O 1 Evaluation Kit 6 USB A Male to USB B Female Cable DO7GH RACTIONAL NDMDER CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H U D oc O H O LLI H LLI Q D as LLI 2 e gt O Z LLI D ie LLI oc LL H D D oc O H O LLI H LLI Q D as LLI gt e gt O Z LLI D ie LLI oc LL E Hittite MICROWAVE CORPORATION v02 0112 RoHS v EARTH FRIENDLY Evaluation PCB Block Diagram Internal VCO RF Out WU 28 Vtune Out J5 fI HAT AU RF 2 RF 4 Out TAN J3 f LOU Optional RFin FOR J27 Ill LU To USB Board ie e o e e o GND g L lt 7 GHz Typical Power HMC507 LP5 12 14 On board VCO with Divider HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Passive LPF cw Q Qus V
44. mber of steps 47 18 Reg 14h 29 0 number of steps 17 0 Reg 15h 17 0 Program Down Sweep Set dwell time dwell time 47 0 Reg 06h 47 18 dwell time 17 0 Reg Parameters 07h 17 0 7 Only if using Set step size step size 47 18 Reg 19h 29 0 step size 17 0 Reg e Asymmetrical sweep is not defined asymmetrical 1Ah 17 0 in 1 Way Sweep mode sweep if Reg Set the number of steps in a sweep number of steps 47 18 Reg OCh 29 0 OEh 22 0 in number of steps 17 0 Reg ODh 17 0 Step 5 e To use SPI trigger write Reg OEh 13 0 to select SPI trigger SPI trigger is executed by writing to Reg OEh 12 1 To use external trigger on pin D4 write Reg OEh 13 1 to configure pin D4 as an external trigger Write Reg O08h 13 Oh to configure pin D4 to be an input Applying master enable to GPIO pins Reg Oth 4 1 is required Configure and 8 apply triader e Enable trigger delay Reg OEh 7 1 or disable trigger delay Reg OEh 7 0 pp y trigg e f using trigger delay write delay value to Reg 05h 20 0 where Reg 05h 20 0 number of delayed reference periods Writing Reg 05h 20 0 1 for example ensures that the trigger is applied at the instant of the rising edge of the next reference rising edge DC 7 GHz FRACTIONAL N DIVIDER sweep parameters are defined in the following way fo Initial frequency of the synthesizer fr Frequency of the synthesizer at the end of the sweep R Reference divider
45. mp step n 1 Detailed Sweeper Configuration Recommended procedure for configuring DC 7 GHz FRACTIONAL N DIVIDER sweeper in all three modes is shown in Table 6 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com EJ Hittite HMC983LP5E MICROWAVE CORPORATION v02 0112 ROHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Table 6 DC 7 GHz FRACTIONAL N DIVIDER Sweeper Configuration Sequence Sweeper Modes Steps Description 2 Way Sweep Mode User Defined Sweep Mode 1 Way Sweep Mode 4 Lock to start e set the integer Reg 05h and fractional Reg 06h and Reg 07h divider values frequency fo Optionally if required the seed Reg OAh and Reg OBh can also be programmed Place the DSM 2 in s ep mode Write Reg OEh 11 1 Disable single step ramp mode Reg OEh 24 0 so that each frequency ete a oe es Disable single step ramp mode Reg increment will be incremented Tey LEN aM EOM OEh 24 0 so that each frequency frequency increment will require a automatically trigger increment will be incremented Enable 2 way sweep mode Disable 99 automatically Configure 1 way sweep mode Reg OEh 25 Enable 1 way sweep mode Reg
46. n up and down directions 17 0 R W Symmetric Ramp Step Size 18 0 for symmetric frequency sweep mode In asymmetric mode it represents the up step size only Table 28 Reg 14h Ramp NSTEP Symmetrical or Up MSB Register BIT TYPE NAME Ww DEFLT DESCRIPTION Represents the MSB of the number of steps for the frequency 29 0 R W Symmetric Ramp Number of 30 0 ramp in up and down directions in symmetric frequency sweep Steps MSB mode In asymmetric mode it represents the number of steps in up direction only Table 29 Reg 15h Ramp NSTEP Symmetrical or Up LSB Register BIT TYPE NAME Ww DEFLT DESCRIPTION Represents the LSB of the number of steps for the frequency 17 0 R W Symmetric Ramp Number of 18 0 ramp in up and down directions in symmetric frequency sweep Steps LSB mode In asymmetric mode it represents the number of steps in up direction only For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Application Support Phone 978 250 3343 or apps hittite com Order On line at www hittite com E Hittite MICROWAVE CORPORATION 02 0112 RoHS EARTH FRIENDLY HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Table 30 Reg 16h DSM Configuration Register BIT TYPE NAME ow DEFLT DESCRIPTION DSM
47. nable CEN o DVDD 32 SDO Main SPI Data Output ee For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H T N oc O H O LLI H LLI Q D as LLI gt e gt O Z LLI 6 LLI oc LL EMIEEICE 5 nwcossiesE MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Table 3 Absolute Maximum Ratings Nominal 3V Supplies to GND 0 3 to 3 6 V Thermal Resistance Rth 1 junction to ground paddle 40 C W Nominal 3V Digital Supply to 3V Analog Supply 03 1040 9 V Reflow Soldering m Peak Temperature 260 C Nominal 5V Supply to GND VPPBUF 0 3 to 5 5 V Time at Peak Temperature 40s divCkp divCkn common mode DC VCCPS 0 5 V min ESD Sensitivity HBM Class 1B VCOIP VCOIN Single Ended AC 50 0 c 7 dBm Source VCOIP VCOIN Differential AC 50 Q 13 dBm Source Digital Input Voltage Range 0 25 to DVDD 0 5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only Minimum Digital Load 1kQ functional operation of the device at these or any other conditions i above those indicated in the operational section of this sp
48. nd L 16 Compare if L 32 For this example the fp p 100 MHz 2 50 MHz The overall division ratio is 4600 025 MHz 50 MHz 92 0005 The nearest integer would be 92 thus N Reg 05h 19 0 92d 5Ch For L 16 Nyac 32 768 or 33d rounded up Thus Nya 33d or 21h Reg 06h 29 0 0 Reg 07h 17 0 21h For L 32 Nga 2147483 648 or 2147484d rounded up Thus Nac 20C49Ch Reg 06h 29 0 8h Reg 07h 17 0 001100010010011100 d Since N 4 must be an integer the actual frequencies in the two cases will have an error of 177 02 Hz for L 16 and only 40 004098 Hz for L 32 Phase Noise in Integer and Fractional Modes In a normal integer frequency divider the in band phase noise is scaled from the input phase noise by 20Log10 N where N is the divider value In HMC983LP5E fractional mode the frequency divider is modulated by the Delta Sigma Modulator to generate output frequencies that are fractional multiple of the input frequency Delta Sigma Modulator shapes the quantization noise such that quantization noise density has a high pass shape which peaks at Fs 2 where Fs is the sampling frequency the divider output frequency in case of HMC983LP5E In fractional mode this quantization noise peak appears at an offset frequency of Fout 2 In the PLL this peak is attenuated by the loop filter However when the HMC983LP5E is used stand alone in fractional mode its output will exhibit the quantization noise as shown in Figur
49. number of steps for the frequency ramp in down direction in sweep mode For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com T D as O H O LLI H LLI e D as LLI gt e gt O Z LLI D O LLI oc LL H D N as O H O LLI H LLI Q D as LLI gt e gt O Z LL ED 6 LLI oc LL FIDE nwcosuesE MICROWAVE CORPORATION v02 0112 RoHS v DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY Table 22 Reg OEh Sigma Delta Modulator Configuration Register BIT TYPE NAME Ww DEFLT DESCRIPTION DSM Type 00 MASH1 Reserved 1 0 R W SD Modulator Type 2 11b 01 MASH11 Reserved 10 MASH111 Delta Sigma Modulator Mode B 11 Delta Sigma Modulator Mode A Ramp Auto Repeat Control from Recommended to write 1 to this bit in ramp mode When this bit 2 R W 1 0 is 1 the ramp will repeat itself if ramp auto repeat on off from SPI 2t spi is 1 at the end of the each sweep 13 R W Ramp Auto Repeat Control from 1 0 Ramp will automatically repeat itself if this bit is 1 and bit 2 is SPI On Off also set to 1 Delay through the integer signal path to compensate for the fractional path 6 4 R W Integer Path Delay 3 111 000
50. represents the up dwell time only Table 25 Reg 11h Ramp DWELL Symmetrical or Up LSB Register BIT TYPE NAME Ww DEFLT DESCRIPTION Represents LSB s for ramp dwell time in up and down directions 17 0 R W Symmetric Ramp Dwell LSB 18 0 for symmetric frequency sweep mode In asymmetric mode it represents the up dwell time only For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com T D as O H O LLI H LLI Q D as LLI gt e gt O Z LLI 6 LLI oc LL H Q QD as O H O LLI H LLI e D oc LLI gt e gt O Z LLI D ie LLI oc LL EJ Hittite MICROWAVE CORPORATION v02 0112 RoHS EARTH FRIENDLY HMC983LP5E DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Table 26 Reg 12h Ramp Step Size Symmetrical or Up MSB Register LSB BIT TYPE NAME Ww DEFLT DESCRIPTION A Represents the MSB for ramp step size in up and down 29 0 R W P Ramp Step Size 30 0 directions for symmetric frequency sweep mode In asymmetric mode it represents the up step size only Table 27 Reg 13h Ramp Step Size Symmetrical or Up LSB Register BIT TYPE NAME w DEFLT DESCRIPTION i Represents the LSB for ramp step size i
51. tart locking process Writing to the 21 R W Lock using External Trigger Pin 1 0 Integer or Fractional Division ratio registers does not have any effect when this bit is set to 1 PLL will lock only when external trigger goes high Use symmetric frequency sweeping for up and down directions 22 R W Symmetrical Ramp Mode 1 1 otherwise DN parameters are taken from Registers Reg OCh Reg ODh Reg 19h and Reg 1Ah for asymmetric mode 23 R W Integer Mode Lock Strobe 1 0 Re lock when integer set point Reg 06h is updated Single step the ramp Each step of the ramp must be popped by 24 RIN Singlestep Ramp Mode Enable strobe either SPI or Hardware pin 25 R W Single Direction Ramp Mode 1 0 Single direction mode for ramp ramp one way pop to base the Enable other way Starting direction of ramp It is only loaded while rampmode 0 26 R W Ramp Start Direction 1 1 1 Positive 0 Negative For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com EJ Hittite MICROWAVE CORPORATION v02 0112 HMC983LP5E RoHS DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY 27 R W Use External Clock for DSM 1 0 1 Use
52. ttite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC983LP5E MICROWAVE CORPORATION v02 0112 RoHS DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER Register Map Table 8 Reg 00h Chip ID Soft Reset Read Register BIT TYPE NAME Ww DEFLT DESCRIPTION 6 0 R W Read Register Address 7 0 Address of the register to be read in the next cycle 17 R W Soft Reset 1 0 Soft Reset Writing 1 generates soft reset Resets all the digital and registers to default states Writing 0 resumes normal chip operation 31 8 R W Chip ID 24 97330h Part Number Description Read regOOh returns chip ID Table 9 Reg 01h Settings Register BIT TYPE NAME Ww DEFLT DESCRIPTION 0 R W VCO Buffer Enable 1 1 Enables VCO input RF buffer 1 R W Reserved 1 1 Write O to this bit 2 R W AUXSPI Enable 1 1 Enables Auxiliary SPI 3 R W Sigma Delta Enable 1 1 Enables Sigma Delta Function 4 R W GPIO Enable 1 1 Enables output from all GPIO pins 5 R W RF Divider Enable 1 1 Enables RF Divider 6 R W Output Buffer Enable 1 1 Enables Divider Output Driver 7 R W Bias Enable 1 1 Enables bias generator for all blocks 8 R W PSCLK to Digital Enable 1 1 Enable Prescaler clock going to digital counters 9 R W Unused 1 1 Table 10 Reg 02h R Divider Register BIT TYPE NAME Ww DEFLT DESCRIPTION 13 0 R W R Divider Ratio 14 1h Local
53. uilt in Power On Reset POR and a serial port accessible Soft Reset SR POR is accomplished when power is cycled for the DC 7 GHz FRACTIONAL N DIVIDER while SR is accomplished via the SPI by writing Reg 00h 80h followed by writing Reg 00h 00h All chip registers will be reset to default states approximately 250 us after power up Serial Port WRITE Operation The host changes the data on the falling edge of SCK and the DC 7 GHz FRACTIONAL N DIVIDER reads the data on the rising edge A typical WRITE cycle is shown in Figure 28 It is 40 clock cycles long 1 The host both asserts SENb active low Serial Port Enable and places the MSB of the data on SDI followed by a rising edge on SCK 2 DC 7 GHz FRACTIONAL N DIVIDER reads SDI the MSB on the 1st rising edge of SCK after SEND 3 DC 7 GHz FRACTIONAL N DIVIDER registers the data bits D29 DO in the next 29 rising edges of SCK total of 30 data bits 4 Host places the 5 register address bits A6 A0 on the next 7 falling edges of SCK MSB to LSB while the DC 7 GHz FRACTIONAL N DIVIDER reads the address bits on the corresponding rising edge of SCK 5 Host places the 3 chip address bits CA2 CAO 110 on the next 3 falling edges of SCK MSB to LSB Note the DC 7 GHz FRACTIONAL N DIVIDER chip address is fixed as 7d or 111b 6 SENb goes from low to high after the 40th rising edge of SCK This completes the WRITE cycle 7 DC 7 GHz FRACTIONAL N DIVIDER also
54. value Reg 02h 13 0 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com T D as O H O LLI H LLI Q D as LLI gt e gt O Z LLI O LLI oc LL H Q QD oc O H O LLI H LLI Q D as LLI gt e gt O Z LLI ED O LLI oc LL Eerittite mmcosaLpse MICROWAVE CORPORATION v02 0112 RoHS DC 7 GHz FRACTIONAL N DIVIDER AND FREQUENCY SWEEPER EARTH FRIENDLY stepsize frequency increment step size In case of symmetric and UP sweeps stepsize 47 18 Reg 12h 29 0 stepsize 17 0 Reg 13h 17 0 In case of asymmetric sweeps downsweep stepsize 47 18 Reg 12h 29 0 down sweep stepsize 17 0 Reg 13h 17 0 Afstep Frequency step size stepsize i L Size of the DSM set in Reg 16h 5 0 Tref Period of the divided reference fpfp at the phase detector Tye xtal N Total number of frequency step increments in a single sweep N 47 18 Reg 14h 29 0 N 17 0 Reg 15h 17 0 Tramp Total time of one frequency sweep from f to f Tramp Tret X N Then final frequency f is given by f fo Afstep X N Setting autoseed Reg OEh 8 1 ensures that different sweeps have identical phase profile This is achieved by loading the seed seed 47 18 Reg OAh 29 0
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