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DSP56652 Baseband Digital Signal Processor User`s Manual

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1. Application Date Programmer MCU Interrupts NINT4 Description N P R 0 No interrupt pending 1 INT4 interrupt request pendin Lower Halfword Ec Normal Interrupt Pending Register EET Lower Halfword NINT3 Description Address 0020 000E 0 No interrupt pending Reset 0000 1 INT3 interrupt request pending Read Write NINT2 Description NINTS Description 0 No interrupt pending 0 No interrupt pending 1 INT2 interrupt request pending 1 INT5 interrupt request pending NINT1 Description NINT6 Description 0 No interrupt pending 0 No interrupt pending 1 INT1 interrupt request pending 1 INT6 interrupt request pending NINTO Description NINT7 Description 0 No interrupt pending 0 No interrupt pending 1 INTO interrupt request pending 1 INT7 interrupt request pending NS2 Description NURTS Description 0 No interrupt pending 0 No interrupt pending 1 Software Interrupt 2 request pending 1 UART RTS Delta interrupt request pending NS1 Description 0 No interrupt pending NKPD Description 1 Software Interrupt 1 request pending 0 No interrupt pending 1 Keypad Interface interrupt request NSO Description pending 0 No interrupt pending 1 Software Interrupt 0 request pending 15 13 12 11 10 9 8
2. Application Date Programmer S C P TXNK Description 1 NACK detected SCP Status Register SCPE Description Address 0020_B006 1 Parity error detected Reset 00C01 Read Write SCFE Description SCTC Description 1 Frame error detected 1 Transmit complete SCOE Description 1 Overrun error detected SCTY Description 1 TX data buffer is empty SCSC Description 1 SENSE pin has changed state SCFN Description 1 Receive FIFO not empty SCSP Description 0 SENSE pin low 1 SENSE pin high SCFF Description 1 Receive FIFO full 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOTE Reset value of bit O depends on Reserved E 74 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer SCP SCPDR SCP Data Register Address 0020_B008 Reset 00uu SCP Data Bits Read Write 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 SCPD7 SCPD6 SCPD5 SCPD4 SCPD3 SCPD2 SCPD1 SCPDO 0 0 0 0 0 0 0 0 0 0 SMEN Description 0 Pins function as GPIO 1 Pins function as SCP SCP Port Con
3. Application Date Programmer B B P TIE Description 0 Transmit Interrupt disabled B B P G R B 1 Transmit Interrupt enabled BBP Control Register B Address X FFA7 END Reset 0000 RE Description Read Write 0 Receive disabled 1 Receive enabled RIE Description 0 Disable interrupt TE Description 1 Enable interrupt when a word is mE received 0 Transmit disabled 1 Transmit enabled TLIE Description 0 Disable interrupt RCIE Description 1 Enable interrupt for last transmit 0 Disable interrupt time slot xS 1 Enable receive interrupt RLIE Description x TCIE Description 0 Disable interrupt a 0 Disable interrupt 1 Enable interrupt for last receive Ee time slot 1 Enable transmit interrupt TEIE Description RCE Description 0 Disable interrupt 0 Counter disabled 1 Enable interrupt for transmit error 1 Enable receive counter REIE Description TCE Description 0 Disable interrupt 0 Counter disabled 1 Enable interrupt for receive error 1 Enable transmit counter Serial Output Flags 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 REIE TEIE RLIE TLIE RIE TIE RE TE RCIE TCIE RCE TCE OF1 OFO 0 0 Reserved Motorola Programmer s Data Sheets E 85 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc E 86 DSP56652 User s Manual Motorola
4. Enable interrupt for data reception S C P SCDPE Description 0 SIMDATA pin disabled SCAC R 1 SIMDATA pin enabled Smart Card Activation Control Register SCPE Description Address 0020_B002 Reset 0000 0 PWR_EN pin disabled Read Write 1 PWR_EN pin enabled SCRS Description APDE Description 0 SIMRESET pin asserted 0 Auto power down disabled 1 SIMRESET pin deasserted 1 Auto power down enabled SCCLK Description 0 SIMCLK pin disabled 1 SIMCLK pin enabled 15 14 13 12 11 10 5 4 3 2 1 0 i SCCLK SCRS SCDPE SCPE APDE 0 0 0 0 0 0 0 0 0 SCFFIE Description 0 Interrupt disabled S C P E R 1 Enable interrupt for receive FIFO full SCP Interrupt Enable Register ETE Address 0020 B004 SCRRIE Description Reset 0000 0 Interrupt disabled Read Write 1 Enable interrupt for receive error SCFNIE Description SCSCIE Description 0 Interrupt disabled 0 Interrupt disabled SCTCIE Description 0 Interrupt disabled 1 Enable interrupt for card sense change Enable interrupt for transmission complete 4 3 2 1 0 Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 73 Freescale Semiconductor Inc
5. CCR Mnemonic Syntax P T S L E U N Z V C ABS ABSD P O EA EEA ADC ADC S D P ehea ee rna ewe SE ADD ADD S D P TT po PT gt ADD iiiiii D 2 ADD iii D 1 TT po PT gt ADDL ADDL S D P ox gt ADDR ADDR S D P PET ME DET SE DET EN ER RE SN RE RUE AND AND S D P T oem 2 l0 AND iiiiii D 2 x des est rola AND AND iii D 1 TIED 2 l0 ANDI ANDI EE 3 212 ASL ASL S D P wp a E 7 ASL ii S D 1 RE E ee ES ASL sss S D 1 E PE gt x 7 2 ASR ASR S D P I 1 1 TATTOO 1 ASR sss S D LS 1 x x x x m x 0 2 ASR ii S D 1 SS ala oe Bcc Bcc PC An 4 eS a RR Bcc PC aa 4 EET PE ERE Ro e ts BCHG BCHG bbbb S lt aa gt 2 2 2 9 BCHG bbbb S lt ea gt 2 U A 212 BCHG bbbb S lt pp gt 2 2 7 7 2 7 9 BCHG bbbb S lt qq gt 2 2 7 7 2 7 9 9 BCHG bbbb DDDDDD 2 1 BCLR BCLR bbbb S lt pp gt 2 2 2 2 2 BCLR bbbb S lt ea gt 2 U A 7 2 2 BCLR bbbb S lt aa gt 2 2 7 7 2 7 BCLR bbbb S lt qq gt 2 sp weed Em BCLR bbbb DDDDDD 2 212 2 2 2 2 BRA BRA PC Rn 4 zx A E rex fem BRA PC aa 4 A sce RS PR Motorola Programmer s Reference D 7 For More Information On This Product
6. BBPCRB SRDB BBPCRC DSP CLK BBPTSR STDB m TX Shift Register We TCLK A BBPSR BBPTX Y YYY YY T Interrupts Clock Frame Sync Generators a SC1B Control Logic and Port Control a SC2B ma SCKB Figure 14 2 BBP Block Diagram 14 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transmit and Receive Clocks 14 1 Data and Control Pins Each of the ports contains six pins The names and functions of these pins are summarized in Table 14 1 Table 14 1 SAP and BBP Pins Function SAP Pin BBP Pin Asynchronous Mode Synchronous Mode SCOA SCOB Receiver Clock Serial Flag 0 SC1A SC1B Receiver Frame Sync Serial Flag 1 SC2A SC2B Transmitter Frame Sync Tx and Rx Frame Sync SCKA SCKB Transmitter Clock Tx and Rx Clock SRDA SRDB Serial Receive Data Pin STDA STDB Serial Transmit Data Pin The functions of the serial clock pin SCK and serial control pins SC0 2 for each port depend on whether the port clock and frame sync signals operate independently asynchronous mode or are common synchronous mode Signal directions input or output for these four pins are determined by the Serial Control Pin Direction SCD 2 0 and Serial Clock Pin Direction SCKD bits in Control Register C for each port SAPCRC
7. Register Bit Name Function Address Bit Original New Original New Interrupts 0000 ISR 30 SMPDINT SMPD 0000 ISR 28 25 L1 replaced with PT 0004 NIER in all bit names 0008 FIER 000C NIPR 0010 FIPR X FFFE IPRP 7 6 TIMPL 1 0 PTPL 1 0 Edge Port 9000 EPPAR 7 0 EPPAR 7 0 EPPA 7 0 QSPI 5F00 QPCR 7 0 PC 7 0 QPC 7 0 5F02 QDDR 7 0 PD 7 0 QDD 7 0 5F04 QPDR 7 0 D 7 0 QPD 7 0 PIT 7000 ITCSR PITCSR 7002 ITDR PITMR 7004 ITADR PITCNT PWM 6014 TCR TCNT 6016 PWCR PWMR 6018 PWCNR PWCNT PT 3800 TCTR PTCR 3802 TIER PTIER 3804 TSTR PTSR 3806 TEVR PTEVR 3808 TIPR TIMR 8 0 TIPV 8 0 TIMV 8 0 380C CTIPR CTIMR 13 0 CTIPV 13 0 CTIMV 13 0 3810 CFPR CFMR 8 0 CFPV 8 0 CFMV 8 0 3814 RSPR RSMR 7 0 RSPV 7 0 RSMV 7 0 3816 PDPAR PTPCR 7 0 PDGPC 7 0 PTPC 7 0 3818 PDDR PTDDR 7 0 PDDR 7 0 PTDD 7 0 381A PDDAT PTPDR 7 0 PDDAT 7 0 PTPD 7 0 381E RTPTR MTPTR 3822 RTBAR MTBAR D 26 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Acronym Changes Table D 11 DSP56652 Acronym Changes Continued Register Bit Name Function Address Bit Original New Original New UART 4080 UCR1 13 TRDYEN TRDYIE RRDYEN RRDYIE TXMPTYEN TXEIE RTSDEN RTSDIE UARTEN UEN 4082 UCR2 12 CTS CT
8. Application Date Programmer Ed g e P O rt EPPAn Description 00 Pin INTn is level sensitive E P P A R 01 Pin INTn defined as rising edge detect Edge Port Pin Assignment Register 10 Pin INTn defined as falling edge detect Address 0020_9000 11 Pin INTn defined as both rising and Reset 0000 falling edge detect Read Write 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 EPPA7 EPPA6 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1 EPPAO E P D D R EPDDn Description Edge Port Data Direction Register 0 Pin is input Address 0020_9002 1 Pin is output Reset 0000 Read Write 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDDO 0 0 0 0 0 0 0 0 0 Edge Port Data Register Port Data Bits Address 0020 9004 Reset 00uu Read Write 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPDO 0 0 0 0 0 0 0 0 0 Edge Port Flag Register Edge Port Flags Address 0020 9006 Reset 0000 Read Write 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 EPF7 EPF6 EPF5 EPF3 EPF2 EPFO Reserved E 38 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc
9. 8 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory 8 4 1 QSPI Control Registers The following registers govern QSPI operation e SPCR Serial Port Control Register e QCRO 3 QSPI Control Registers e SPSR Serial Port Status Register e SCCRO0 4 Serial Channel Control Registers SPCR Serial Port Control Register 0020 5F06 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O CSPOL CSPOLICSPOLACSPOL1CSPOLO QE3 QE2 QE1 QEO HLTIE TRCIE WIE TACE HALT DOZE QSPE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Either the EQSPI bit in the NIER or the EFQSPI bit in the FIER must be set in order to generate any of the interrupts enabled in the SPCR see page 7 7 Table 8 3 SPCR Description Name Description Settings CSPOL 4 0 Chip Select Polarity 4 0 These bits determine the 0 SPICSn is active low default Bits 15 11 active logic level of the QSPI chip select outputs 1 SPICSn is active high QE 3 0 Queue Enable 3 0 Each of these bits enables its 0 Queue n is disabled default Bits 10 7 respective queue to be triggered If QEn is cleared a 1 Queue n is enabled trigger to this queue is ignored If QEn is set a trigger for Queue n makes Queue n active and the QAn bit in the SPSR is asserted Queue n executes when i
10. Register Name Peripheral Address Page BBPCRA BBP Control Register A BBP X FFA6 14 18 BBPCRB BBP Control Register B BBP X FFA7 14 19 BBPCRC BBP Control Register C BBP X FFA8 14 21 BBPDDR BBP GPIO Direction Register BBP X FFAE 14 24 BBPPCR BBP Port Control Register BBP X FFAF 14 25 BBPPDR BBP Port Data Register BBP X FFAD 14 24 BBPRMR BBP Receive Counter Modulus Register BBP X FFA4 14 17 BBPRX BBP Receive Data Register BBP X FFAA 14 23 BBPSR BBP Status Register BBP X FFAQ 14 22 BBPTMR BBP Transmit Counter Modulus Register BBP X FFA5 14 17 BBPTSR BBP Time Slot Register BBP X FFAB 14 23 BBPTX BBP Transmit Data Register BBP X FFAC 14 23 CFC Channel Frame Counter PT 0020_380E 10 22 CFMR Channel Frame Modulus Register PT 0020_3810 10 23 CKCTL Clock Control Register MCU Core 0020_C000 4 5 cso Chip Select 0 Register EIM 0020_1000 6 9 CS1 Chip Select 1 Register EIM 0020 1004 CS2 Chip Select 2 Register EIM 0020 1008 CS3 Chip Select 3 Register EIM 0020_100C CS4 Chip Select 4 Register EIM 0020_1010 CS5 Chip Select 5 Register EIM 0020_1014 CTIC Channel Time Interval Counter PT 0020_380A 10 22 CTIMR Channel Time Interval Modulus Register PT 0020_380C 10 22 DCR DSP Side Control Register MDI X FF8A 5 25 DRRO DSP Receive Register 0 MDI X FF8F 5 28 DRR1 DSP Receive Register1 MDI X FF8E 5 28 DSR DSP Side Status Register MDI X FF8B 5 26 DTPTR Delay Table Pointer PT 0020_3824 10 25 D
11. URX 15 14 13 12 11 10 9 8 7 65 43 2 1 0 4000 CHARRDY ERR OVRRUN FRMERR BRK PRERR Rx DATA 403C UTX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4040 Tx DATA 407C UCR1 15 14 13 12 11 10 9 8 7 6 5 4 xac 4080 TxFL 1 0 TRDIETXENRxFL 1 0 RRDYIE RxEN IREN TXEIE RTSDIE SNDBRK DOZEJUEN UCR2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4082 IRTS CTSC CTSD PRENPROE STPB ws JeLksrc T UBRGR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4084 CD 11 0 USR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4086 TXE RTSS TRDY RRDY RTSD UTS 15 14 13 jg A 10 9 8 7 6 5 4 3 2 1 0 4088 FRCPERR LOOP LOOPIR UPCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 408A PC 3 0 UDDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 408C PDC 3 0 UPDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 14 0 408E PD 3 0 11 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers 11 4 1 UART Control Registers URX UART Receive Register 0020_4000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O CHARRDY ERR OVRRUN FRMERR BRK PRERR Rx DATA RESET 0 0 0 0 0 0 0 0 The 16 entry receive buffer FIFO is accessed through the URX register at address 0020_4000 This register is actually mapped to 16 word addresses from 0020_4000 to 0020_403C to support LDM instructions At reset the flag bits in the most significant byte are
12. Table 7 1 MCU Interrupt Sources Continued Interrupt ISR Bit Where Source Om n Name amp No Source s Enabled Page Edge I O 8 separate INT7 12 5 INT7 INTO Pin Asserted port S INTO QSPI 4 ORed QSPI 24 QSPI HALT Command SPCR 8 13 QSPI Trigger Collision QSPI Queue Pointer Wraparound End of Transfer QSPIControl 8 22 RAM PIT 1 separate PIT 16 Periodic Interrupt Timer 0 PITCSR 9 3 GPT 8 ORed TPW 17 PWM Count Rollover TPWIR 9 16 GP Timer Count Overflow PWM Output Compare Input Capture 1 2 4 Output Compare 1 3 Protocol 3 separate PT2 28 2 PT Events mcu_int 2 1 0 PTIER 10 18 Timer 5 ORed PTO 6 PTM 25 PT Error PT HALT Command PT Reference Slot Counter 0 PT Channel Frame Counter 0 PT Channel Time Interval Counter 0 UART 2 separate URX 31 UART Receiver Ready UCR1 11 11 2 ORed UTX 29 UART Transmitter Ready UART Transmitter Empty URT 13 RTS Pin State Change S SmartCard 1 separate SMP 30 SIM Sense Change SCPIER 12 13 4 ORed C SCP 22 SCP Transmit Complete SCP Receive FIFO Not Empty SCP Receive FIFO Full SCP Receive Error Keypad 1 separate KPD 14 KPD Key Closure KPCR 13 5 Interface Software 3 separate S2 S 2 0 Software Interrupts 2 1 0 0 1 The MDI and Edge l Ointerrupts are asynchronous All other interrupts are synchronous 2 The Edge I O interrupts can be edge or level sensitive All other interrupts are level sensitive only Motorola Int
13. Reset 0000 LOOP Description Read Write 0 Normal operation I 1 Receiver connected to transmitter FRCPERR Description 0 No intentional parity errors generated 1 Intentional parity error generated LOOPIR Description 0 Normal IR operation 1 IR Receiver connected to IR transmitter Reserved E 70 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer U P C R UPCn Description 0 Pin is GPIO pin UART Port Control Register 1 Pin is UART pin Address 0020_408A Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPC3 UPC2 UPC1 UPCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U D D R UDDn Description 0 Pin is input when GPIO UART Data Direction Register Address 0020_408C Reset 0000 Pin is output when GPIO Reserved Read Write UDD3 UDD2 UDD1 UDDO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U P D R Port Data Bits UART Port Data Register Address 0020_408E Reset 000u Read Write 15 14 13 12 11 10 8 6 4 3 2 1 0 UPD3 UPD2 UPD1 UPDO Motorola Program
14. Application Date Programmer WIE Description QS P 0 Queue wraparounds do not cause hardware interrupts from QSPI to MCU S P C R 1 Queue wraparounds QPWF flag set cause hardware interrupts from QSPI to MCU Serial Port Control Register Address 0020 5F06 Reset 0000 Read Write TACE Description 0 Trigger accumulation for Queue 1 is disabled TRCIE Description 1 Trigger accumulation for Queue 1 is led Queues 0 2 and 3 are 0 Trigger collisions do not cause enab je hardware interrupts from QSPI to unaffected MCU 1 Trigger collisions cause hardware interrupts from QSPI to MCU HALT Description 0 QSPI HALT is disabled HLTIE Description 1 QSPI HALT is requested 0 Hardware interrupts from QSPI to MCU caused by HALTA flag are disabled DOZE Description 1 Hardware interrupts from QSPI to MCU caused by HALTA flag are 0 QSPI ignores DOZE mode enabled 1 DOZE mode causes QSPI to halt at end of executing queue QEn Description 0 Queue n triggering is inactive QSPE Description 1 Queue n triggering is active on 0 QSPI disabled MCU or Protocol Timer triggers 1 QSPI enabled CSPOLn Description 0 SPICSn is active low 1 SPICSn is active high 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSPOL4 CSPOL3 CSPOL2 CSPOL1 CSPOLO QE3 QE2 QE1 QEO HLTIE TRCIE WIE TACE HALT DOZE QSPE Motorola Programmer s Data Sheets E 39 For More Information On This Product Go to www
15. RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O FKPD FURTS FINT7 FINT6 FINT5 FINT4 FINT3 FINT2 FINT1 FINTO FS2 FS1 FSO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The FIPR works in the same fashion as the NIPR to monitor fast interrupts Table 7 4 NIPR and FIPR Description Name Bit s Interrupt Setting NIPR FIPR NURX FURX 31 UART Receiver Ready 0 No interrupt request NSMPC FSMPC 30 SIM Position Change he Hate mUPITegue et Penang NUTX FUTX 29 UART Transmitter NPT2 0 FPT2 0 28 26 Protocol Timer 2 0 NPTM FPTM 25 Protocol Timer Interrupts NQSPI FQSPI 24 QSPI NMDI FMDI 23 MDI NSCP FSCP 22 SCP RxD TxD or Error NTPW FTPW 17 Timer PWM NPIT FPIT 16 PIT NKPD FKPD 14 Keypad Interface NURTS FURTS 13 UART RTS NINT7 0 FINT7 0 125 External Interrupt 7 0 NS2 0 FS2 0 2 0 Software Interrupt 2 0 Motorola Rs 79 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Interrupt Controller ICR Interrupt Control Register 0020_0014 BIT31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT16 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO EN Source Number Vector Number RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The ICR
16. 14 14 For More Information On This Product Go to www freescale com Enable Bit BBP Receive Data with Overrun Error REIE ROE BBP Receive Data RIE RDF BBP Receive Last Slot RLIE BBP Receive Frame Counter RCIE BBP Transmit Data with Underrun Error TEIE TUE BBP Transmit Last Slot TLIE BBP Transmit Data TIE TDE BBP Transmit Frame Counter TCIE DSP56652 User s Manual Motorola Freescale Semiconductor Inc SAP and BBP Control Registers 14 9 SAP and BBP Control Registers Table 14 5 and Table 14 6 are summaries of the SAP and BBP control registers respectively including the acronym bit names and address of each register Table 14 5 Serial Audio Port Register Summary SAPCNT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFB4 LV 15 0 SAPMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFB5 LV 15 0 SAPCRA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFB6 PSR WL 1 0 DC 4 0 PM 7 0 SAPCRB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFB7 REIE TEIE RLIE TLIE RIE TIE RE TE TCE OF 1 0 SAPCRC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFB8 FSP FSR FSL 1 0 BRM SHFD CKP SCKD SCD 2 0 MOD SYN SAPSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFB9 RDF TDE ROE TUE RFS TFS IF 1 0 SAPRX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFBA Receive Word SAPTSR 15 14 13 12 11 10
17. Reserved RXMA Description PT EV R 0 Macro not active PT Event Register 1 Receive macro is active Address 0020_3806 Reset 0000 Read Write ACT Description TXMA Description 0 Frame Table 0 active 0 Macro not active 1 Frame Table 1 active 1 Transmit macro is active THIP Description 0 Timer not halted 1 Timer HALT in progress 15 14 13 12 11 10 8 6 4 3 2 1 0 THIP TXMA RXMA ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Time Interval Modulus Register Timer Interval Modulus Address 0020_3808 Reset 0000 Value Read Write 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 TIMV8 TIMV7 TIMV6 TIMV5 TIMV4 TIMV3 TIMV2 TIMV1 TIMVO 0 0 0 0 0 0 0 0 Channel Time Interval Counter Channel Time Interval Address 0020_380A Reset 0000 Value Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTIV13 CTIV12 CTIV11 CTIV10 CTIV9 CTIV8 CTIV7 CTIV6 CTIV5 CTIV4 CTIV3 CTIV2 CTIV1 CTIVO Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 61 Freescale Semiconductor Inc Application Date Programmer CT M R Channel Time Interval Channel Time Interval Modulus Register Modulus Value Address 0
18. Application Date Programmer QC R2 HMD2 Description 0 Queue 2 halts only at end of queue Queue Control Register 2 Address 0020_5FOC 1 pane halts on any sub queue Reset 0000 oungary Read Write LE2 Description Queue 2 Pointer 0 Queue 2 reloading disabled 1 Queue 2 reloading enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LE2 HMD2 QP25 QP24 QP23 QP22 QP21 QP20 0 0 0 0 0 0 0 0 0 Queue Control Register 3 HMD3 Description Address 0020_5FOE Reset 0000 0 Queue 3 halts only at end of queue Read Write 1 Queue 3 halts on any sub queue boundary LE3 Description 0 Queue 3 reloading disabled Queue 3 Pointer 1 Queue 3 reloading enabled 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 x QP35 QP34 QP33 QP32 QP31 QP30 Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 41 Freescale Semiconductor Inc Application Date Programmer QA1 Description QS Pl 0 Queue 1 is not active 1 Queue 1 is active S P S R QAO Description Serial Po
19. Pin No Peripheral Port Primary Signal Function In DSP Trace Address Mode P10 MOD DSP AT DSP Address Tracing Strobe N11 COLUMNO DSP ADDRO M11 COLUMN1 DSP_ADDR1 P12 Borrowed from COLUMN2 DSP_ADDR2 N12 ra COLUMN3 DSP_ADDR3 P13 COLUMN4 DSP_ADDR4 M12 COLUMN5 DSP_ADDR5 K14 ROWO DSP_ADDR6 J13 ROW1 DSP_ADDR7 J11 ROW2 DSP_ADDR8 J14 ROW3 DSP_ADDR9 H13 ROW4 DSP_ADDR10 L7 Borrowed from SIMCLK DSP_ADDR11 SmartCard Port P8 SENSE DSP_ADDR12 Mg SIMDATA DSP_ADDR13 N9 SIMRESET DSP_ADDR14 K7 PWR_EN DSP_ADDR15 The Address Visibility Multiplexing is enabled by writing 4 to the OnCE Test and Logic Control Register OTLCR The OTCLR is accessed by writing 10011 to the RS 4 0 field in the OnCE Command Register OCR For more information on OnCE operation refer to the DSP56600 Family Manual 4 20 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 5 MCU DSP Interface The MDI provides a mechanism for transferring data and control functions between the two cores on the DSP56652 The MDI consists of two independent sub blocks a shared memory space with read write access for both processors and a status and message control unit The primary features of the MDI include the following e 1024 x 16 bit shared memory in DSP X data memory space e interrupt or poll driven message control e flexible software contro
20. Application Date Programmer DS P M DI DGIR1 Description 0 No interrupt pending DS R 1 MCU General Interrupt 1 pending MGIP1 is set DSP Side Status Register Address X FF8B Reset C060 aah Read Write DTIC Description 1 Signal to MCU to clear MTIR bit in MSR bit 9 write only DGIRO Description 0 No interrupt pending 1 MCU General Interrupt 0 pending MCP Description MGIPO is set 0 No interrupt pending 1 MCU Side Command interrupt DRF1 Description pending 0 DRR1 is empty 1 DRR1 has data DWSC Description 1 Signal to MCU to clear DWS bit in MSR bit 8 write only DRFO Description 0 DRRO is empty 1 DRRO has data MPN 0 1 Description 00 MCU in STOP mode 01 MCU in WAIT mode DTE1 Description 10 MCU in DOZE mode 0 DTR1 has data a 11 MCU in Normal mode 1 DTR1 is empty DTEO Description DEP Description 0 DTRO has data 0 No event pending 1 DTRO is empty 1 DSP Side event pending DSP Side Flags 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTEO DTE1 DRFO DRF1 DGIRO DGIR1 DTIC MCP DWSC MPM1 MPMO DEP DF2 DF1 DFO 0 Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 15 Application Freescale Semiconductor Inc Date Programmer 15 DSP MDI 14 13 12 DRRO DSP Receive Register 0 Address X FF8F Reset uuuu Read Write 11 10 9 8 7 6 5 4 3 2 1 0
21. For More Information On This Product Go to www freescale com Bits 6 0 the baud rate for the associated peripheral The SCKDF field includes two division ST factors The MSB SCKDF6 is a prescaler bit SCKDF 6 0 Division Factor that divides MCU_CLK by a factor of 4 if set 000_0000 2 or by 1 if cleared while SCKDF 5 0 divide MCU CLK by a factor of 1 to 63 00 3E 000 0001 4 There is an additional division by 2 The 000 0111 16 effective SCK baud rate is MCU_CLK 100_0000 8 SCKDF 5 0 1 3 SCKDF 6 1 2 100 1011 96 The lone exception is SCKDF 6 0 7F in 111 1110 504 which case SCK MCU CLK 111 1111 1 8 20 DSP56652 User s Manual Motorola Freescale Semiconductor Inc QSPI Registers and Memory CPHA 0 SCK CKPOL 0 SCK CKPOL 1 I cs CSPOL 1 1 1 Serial Cycle SCK CKPOL 0 SCK CKPOL 1 i cs CSPOL 1 i CSCKD r Figure 8 2 QSPI Serial Transfer Timing Motorola Queued Serial Peripheral Interface 8 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory 8 4 2 MCU Transfer Triggers The last four 16 bit addresses in the utilized memory area 0020 5FF8 to 0020_5FFE are used for MCU triggers to Queue0 Queue3 respectively When the MCU writes to one of these addresses the QSPI generates a trigger for the appropriate queue in the same fashion as a protocol
22. Bit 11 Debug mode 1 PWM runs in Debug mode TDBG GP Timer DBG Enables IC and OC operation O GP timer frozen in Debug mode default Bit 10 during Debug mode 1 GP timer runs in Debug mode PWD PWM DOZE Enables PWM operation during O PWM enabled in DOZE mode default Bit 9 DOZE mode 1 PWM disabled in DOZE mode PWE PWM Enable Enables PWM operation If PWE 0 PWM disabled PWCNT stopped default Bit 8 and TE are both cleared the prescaler is 1 PWM enabled PWCNT is running stopped TD GP Timer DOZE Enables IC and OC operation 0 GP timer enabled in DOZE mode default Bit 7 during DOZE mode 1 GP timer disabled in DOZE mode TE GP Timer Enable Enables IC and OC O IC and OC disabled TCNT stopped Bit 6 operation If PWE and TE are both cleared the default prescaler is stopped 1 IC and OC enabled TCNT is running PSPW 2 0 Prescaler for PWM These bits select the Bits 5 3 MCU CLK divisor for the clock that drives PSPW 2 0 PWCNT Prescaler PWONT f PST 2 0 TCNT Prescaler PST 2 0 Prescaler for GP Timers These bits select the Bits 2 0 MCU_CLK divisor for the clock that drives TCNT 000 2 default 001 92 010 93 011 24 100 25 101 26 110 27 111 28 Motorola Timers 9 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM TPWMR Timers and PWM Mode Register 0020_6002 Bit15 14 13 12 11 10 9 8 7 6 5 4 3
23. Table 4 11 Debug Port Pin Multiplexing MUX_CTL 0 aes da MUX CTL 1 GPCR Bit 1 GPCR 0 Module Pin Module Pin UART K11 0 TRST SAP STDA Interrupt INT6 DSR Controller J12 1 TMS SAP SRDA Interrupt INT7 DTR or SCLK2 Controller G13 5 DSP_DE SAP SC2A KP ROW6 DCD G11 6 TCK SAP SCKA KP ROW7 Rit E11 7 RESET_IN MCU Timer IC2A UART RTS D14 MCU DE UART CTS E14 TDO UART TxD E12 TDI UART RxD MCU Timer ICI The DSR function for K11 is enabled by setting GPCR bit O AND using the pin as GPIO in the Edge Port The DTR function for J12 is enabled by setting GPCR bit 1 AND using the pin as an Edge Port interrupt The SCLK function for J12 is enabled by setting GPCR bit 1 AND setting the CLKSRC bit in UCR2 The DCD function for G13 is enabled by clearing GPCR bit 5 AND using the pin as GPIO in the Keypad Port The RI function for G11 is enabled by clearing GPCR bit 6 AND using the pin as GPIO in the Keypad Port When MUX_CTL 0 the E12 pin is connected to both the UART RxD input and the Timer IC1 input Table 4 12 Timer Pin Multiplexing b GPCR Bit 1 GPCR 0 do GPCR Bit i Port Pin Port Pin N13 2 MCU Timer OC1 KP COL6 M13 3 MCU Timer PWM KP COL7 H14 4 MCU Timer IC2B KP ROW5 Figure 4 4 shows the relationship between these 11 pins and their controls 4 16 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Free
24. 0020 380E Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O CFCv 8 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 14 CFC Description Name Description CFCV 8 0 Channel Time Interval Value This field contains the current CFC value CFC is described on Bits 8 0 page 10 3 Note Writing CFC with zero when it is enabled sets the CFNI bit in PTSR and generates an interrupt if the CFNIE bit in PTIER is set 10 22 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc PT Registers CFMR Channel Frame Modulus Register 0020_3810 Bitib 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O CFMV 8 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 15 CFMR Description Name Description CFMV Channel Frame Modulus Value This field contains the value loaded into CFC when it is enabled Bits 8 0 and when it rolls over A CFMV value of 0 is not supported This register should be written before the CFC is enabled RSC Reference Slot Counter 0020_3812 Bitib 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O RSCV 7 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 16 RSC Description Name Description RSCV 7 0 Reference Slot Count Value This field contains the current RSC value RSC is described on Bits 7 0 page 10 4 Note Writing RSC with zero when it is enabled sets the RSNI bit in
25. Register Bit Name Function Address Bit Original New Original New SAP X FFB4 TCRA SAPCNT X FFB5 TCLR SAPMR X FFB6 CRAA SAPCRA X FFB7 CRBA SAPCRB X FFB8 CRCA SAPCRC X FFB9 SSISRA SAPSR X FFBA RXA SAPRX X FFBB TSRA SAPTSR X FFBC TXA SAPTX X FFBD PDRA SAPPDR 5 0 PD 5 0 SAPPDJ 5 0 X FFBE PRRA SAPDDR 5 0 PDC 5 0 SAPDDI 5 0 X FFBF PCRA SAPPCR 5 0 PC 5 0 SAPPC 5 0 BBP X FFA4 RCRB BBPRMR X FFA5 TCRB BBPTMR X FFA6 CRAB BBPCRA X FFA7 CRBB BBPCRB X FFA8 CRCB BBPCRC X FFAQ SSISRB BBPSR X FFAA RXB BBPRX X FFAB TSRB BBPTSR X FFCC TXB BBPTX X FFAD PDRB BBPPDR 5 0 PD 5 0 BBPPD 5 0 X FFAE PRRB BBPDDR 5 0 PDC 5 0 BBPDD 5 0 X FFAF PCRB BBPPCR 5 0 PC 5 0 BBPPC 5 0 Motorola Programmer s Reference D 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Acronym Changes D 30 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix E Programmers Data Sheets These programmer s sheets are intended to simplify programming the various registers in the DSP56652 They can be photocopied and used to write in the binary bit values and the hexadecimal value for each register The programmer s sheets are provided in the same order as the sections in this document Sheets are also provided for certain registers that are described in other documents Table E 1 list
26. 020 cee eee ee 5 2 MDI MCU Side Memory Mapping 0 000 e eee eee 5 3 MDI Register S YACEN 5 7 MDI Mess ge EXC oos cu ore ERES Ve eee he ERI E Ren 5 8 DSP to MCU General Purpose Interrupt 20055 5 9 EIM Block Diagram E vad oa Re Resa E ERRARE 6 1 Example EIM Interface to Memory and Peripherals 6 2 MCU Interrupt Controller nox a ES 7 2 Hardware Priority PIO Web ts ace d ertet RC ds 7 3 Internal IRQA D Connection sssseeeeee eee eee 7 11 Idee I PITI 244 e bd ba Nl tea ss 7 16 QSPDSISnab Eloy eu hn S bos dl ao tesi 4 8 5 QSPI Serial Transfer Timing o 472 os Seb ie be ee eA Get cogs Baas 8 21 PIT Block Diarias seed a 9 2 PIT Timing Using the PITMR n Rr 9 2 Watchdog Timer Block Diagram 0 0 0 0 ce eee eee eee 9 5 GP Timer PWM Clocks 23 E cR De pr EE ECC s 9 7 GP Timer Block Diagram 12 23 xe ede he IRR EE ae ees Ree 9 9 List of Figures xi For More Information On This Product Go to www freescale com Figure 9 6 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 11 1 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 13 1 Figure 13 2 Figure 14 1 Figure 14 2 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure A 1 Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure A 6 Figure A 7 Figure A 8 Figure A 9 xii Freescale Semiconductor Inc PWM B
27. Freescale Semiconductor Inc Application Date Programmer MCU Interrupts Description F E R 0 Interrupt source is masked 1 Protocol Timer MCUO interrupt Upper Halfword source enabled Fast Interrupt Enable Register Upper Halfword XS Address 0020 0008 EFPTM Description Reset 0000 0 Interrupt source is masked Read Write 1 Protocol Timer interrupt source enabled EFPT1 Description 0 Interrupt source is masked EFQSPI Description 1 Protocol Timer MCU1 interrupt f k source enabled 0 Interrupt source is masked 1 QSPI interrupt source enabled EFPT2 Description 0 Interrupt source is masked EFMDI Description 1 Protocol Timer MCU2 interrupt 0 Interrupt source is masked source enabled z 1 MDI interrupt source enabled EFUTX Description 0 Interrupt source is masked EFSCP Description 1 UART Transmitter Ready interrupt 0 Interrupt source is masked source enabled 1 SIM Card Tx Rx or Error interrupt source enabled EFSMPD Description 0 Interrupt source is masked EFTPW Description 1 SIM Auto Power Down interrupt 0 Interrupt source is masked source enabled z 1 General Purpose Timer PWM interrupt source enabled EFURX Description 0 Interrupt source is masked EFPIT Description 1 UART Receiver Ready interrupt source enabled 0 Interrupt source
28. E 6 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer GPC4 Description M C U Co re 0 Pin H14 functions as ROW5 1 Pin H14 functions as IC2 General Port Control Register GPC3 Description Address 0020 CCOO 0 Pin M13 functions as COL7 Reset 0000 Bead Write 1 Pin M13 functions as PWM GPC5 Description GPC2 Description 0 Pin G13 functions as ROW6 0 Pin N13 functions as COL6 1 Pin G13 functions as SC2A 1 Pin N13 functions as OC1 DTR accessed by configuring as output in KDDR GPC1 Description GPC6 Description 0 Pin J12 functions as INT7 0 Pin G11 functions as ROW7 1 Pin J12 functions as SRDA A ONSAS SCRA DTR accessed by configuring as output in EPDDR GPC7 Description GPCO Description 0 Pin E11 functions as RTS 0 Pin K11 functions as INT6 1 Pin E11 functions as IC2 1 Pin K11 functions as STDA DSR accessed by configuring as output in EPDDR STO bit value is reflected 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
29. Message From Long or Acknowledgment Message Long or MCU to DSP Opcode Short From DSP to MCU Opcode Short Number Number memory_write request 1 long memory_write response 1 short memory_read request 2 long memory_read response 2 long memory_check request 3 long memory_check response 3 long start_application request 4 long none NA NA invalid message other either invalid_opcode response 4 short The following sections describe the structure of each message A 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 2 1 memory_write request memory write request is a long message from the MCU to the DSP used to write to the DSP program or data RAM The structure of this message is shown in Figure A 3 The first entry in MDI memory is the message opcode The second entry contains the number of words to write to DSP memory The third entry contains two fields XYP and source address offset The XYP field which occupies the upper two bits of the entry determines which memory space to access as shown in Table A 3 The source address offset occupies the lowest ten bits of the third entry and indicates the location in the MDI memory space of the data to be written to the DSP The last entry of the message contains the DSP destination address to which the data is to be written In most cases the source address offset points to the word fol
30. 6 3 ElM Features This section discusses the following features of the EIM e Configurable bus sizing e External boot ROM control Bus watchdog operation e Error condition reporting e External display of internal bus activity e Emulation Port e General purpose outputs 6 3 1 Configurable Bus Sizing The EIM supports byte halfword and word operands allowing access to 8 and 16 bit ports It does not support misaligned transfers The port size for each chip select is programmed through the DSZ 1 0 bits in the associated CS control register In addition the portion of the data bus used for transfer to or from an 8 bit port is programmable via 6 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Features the same bits An 8 bit port can reside on external data bus bits D 15 8 or D 7 0 Connecting 8 bit devices to D 15 8 reduces the load on the lower data lines A word access to or from an 8 bit port requires four bus cycles to complete A word access to or from a 16 bit port requires two bus cycles to complete A halfword access to or from an 8 bit port requires two bus cycles to complete In a multi cycle transfer the lower two address bits A 1 0 are incremented appropriately The EIM contains a data multiplexer that routes the four bytes of the MCU interface data bus to their required positions for proper interface to memory and
31. Table 5 15 MRR1 Description MRR1 is a 16 bit read only register that reflects the data written on the DSP side to DTR1 Reading MRR1 clears the MCU Receive Register 1 Full bit MRF1 in the MSR and sets the DSP Transmit Register 1 Empty bit DTE1 in the DSR It can also trigger a transmit interrupt on the DSP side if the DTIE1 bit in the DCR is set A single 8 bit read from MRR1 also updates all status information MRRO MCU Receive Register O 0020_2FFE BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from MCU to DSP RESET Table 5 16 MRRO Description MRRO is a 16 bit read only register that reflects the data written on the DSP side to DTRO Reading MRRO clears the MCU Receive Register O Full bit MRFO in the MSR and sets the DSP Transmit Register O Empty bit DTEO in the DSR It can also trigger a transmit interrupt on the DSP side if the DTIEO bit in the DCR is set A single 8 bit read from MRRO also updates all status information Motorola MCU DSP Interface 5 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers 5 6 2 DSP Side Registers DCR DSP Side Control Register X FF8A BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O DTIEO DTIE1 DRIEO DRIE1 MCIE DMF 2 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note The MDIPL bits in the Periphe
32. data data data data data data data data data data data data data data data data 15 data 14 data 13 data 12 data DRR1 DSP Receive Register 1 Address X FF8E Reset uuuu Read Write 11 10 9 8 7 6 5 4 3 data data data data data data data data data 2 data 4 data 0 data 15 14 13 12 DTRO DSP Transmit Register 0 Address X FF8D Reset uuuu Read Write 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data 15 14 13 12 DTR1 DSP Transmit Register 1 Address X FF8C Reset uuuu Read Write 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data E 16 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer E
33. Figure A 8 Format of memory_check request Message A 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 2 7 start_application request start_application request is a long message from the MCU to the DSP requesting the DSP to leave the boot mode and begin executing the user program The format of this message is shown in Figure A 9 The entry following the start_application request opcode in MDI shared memory is the starting address of the user program in program memory When the DSP receives this message it jumps to the specified program address location and begins executing code at that location The DSP does not generate a response to this message MDI Messaging Unit Registers 15 14 10 9 0 l MCU address DSP address i MCU_MDI_BASE 2 offset MDI Shared Memory DSP MDI BASE offset l start_application request starting address Figure A 9 Format of start_application request Message Motorola DSP56652 DSP Bootloader A 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 2 8 invalid opcode response invalid opcode response is a short message from the DSP to the MCU in response to any unrecognized message opcode The format of this message is shown in Figure A 10 The RET field in MDI RO is used to indicate the length of the unrecognized m
34. Name Description Settings QPC 7 0 QSPI Pin Configuration Each bit determines 0 GPIO default Bits 7 0 whether its associated pin functions as QSPl or 1 QSPI GPIO 8 24 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory QDDR QSPI Data Direction Register 0020_5F02 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO QDD7 QDD6 QDD5 QDD4 QDD3 QDD2 QDD1 QDDO SCK MOSI MISO SPICS4 SPICS3 SPICS2 SPICS1 SPICSO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8 9 QDDR Description Name Description Settings QDD 7 0 QSPI Data Direction 7 0 Determines O Input default Bits 7 0 whether each pin that is configured as GPIO 1 Output functions as an input or an output whether or not the QSPI is enabled QPDR QSPI Port Data Register 0020_5F04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO QPD7 QPD6 QPD5 QPD4 QPD3 QPD2 QPD1 APDO SCK MOSI MISO SPICSA4 SPICS3 SPICS2 SPICS1 SPICSO RESET 0 0 0 0 0 0 0 0 Table 8 10 QPDR Description Name Description QPD 7 0 QSPI Port GPIO Data 7 0 Each of these bits contains data for the corresponding QSPI pin if it Bits 7 0 is configured as GPIO Writes to QPDR are stored in
35. OE External Data 0 15 Interface Module Address 0 18 E Flash 512Kx16 Data 0 15 LCD Control pomo momo momo mo omo momo m momo momo moo mmo mom ETE Data 0 7 Figure 6 2 Example EIM Interface to Memory and Peripherals 6 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 6 1 EIM Signals The EIM signal descriptions in Section 2 4 External Interface Module are repeated and expanded in Table 6 1 for convenience EIM Signals Table 6 1 ElM Signal Description Signal Name Type Reset State Signal Description A0 A21 Output Driven low Address bus These signals specify the address for external memory accesses If there is no external bus activity AO A21 remain at their previous values to reduce power consumption DO D15 Input Output Input Data bus These signals provide the bidirectional data bus for external memory accesses They remain in their previous logic state when there is no external bus activity to reduce power consumption D ii m o Output Output Driven high Driven high Read write This signal indicates the bus access type A high signal indicates a bus read A low signal indicates a write to the bus This signal can also be used as a memory write enable WE signal When accessing a peripheral chip the signal acts as a read w
36. PRERR Parity Error Set when parity is enabled andthe 0 No parity error default Bit 10 calculated parity in the received character does 1 Parity error detected for this character not match the received parity bit indicating that the data may be corrupted PRERR is never set when parity is disabled Cleared when the register is read Rx DATA Received Data This field contains the character in a received frame In 7 bit mode bit 7 is always Bits 7 0 Zero Motorola UART 11 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers UTX UART Transmit Register 0020_4040 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Tx DATA RESET 0 0 0 0 0 0 0 0 The 16 entry transmit buffer FIFO is accessed through the UTX register at address 0020 4040 This register is actually mapped to 16 word addresses from 0020 4040 to 0020 407C to support STM instructions Reading one of these registers returns zeros in bits 15 8 and random data in bits 7 0 Table 11 5 UTX Description Name Description Settings Tx DATA Transmit Data This field contains data to be transmitted to the far end device Writing to this Bits 7 0 register initiates transmission of a new character Data is transmitted LSB first In 7 bit mode bit 7 is ignored Tx DATA should only be written when the TRDY bit in USR is set indicating that UT
37. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer E M EBC Description G S C R4 0 Read and write accesses both assert EBO 1 Chip Select Register 4 Address 0020 1010 1 Only write accesses can assert Reset uuuu Read Write WEN Description DSZ1 DSZO Description 0 The EBO T signals are negated 0 0 8 bit port on D 8 15 pins normally 0 1 8 bit port on D 0 7 pins 1 The EBO 1 signals are negated half 1 0 16 bit port on D 0 15 pins a clock cycle earlier on write accesses 1 1 Reserved OEA Description p 7 SP Description 0 The OE signal is negated normally 0 User mode accesses allowed 1 The OE signal is asserted half a clock cycle later on read accesses 1 User mode accesses prohibited CSA Description z WP Description 0 The CS signal is asserted normally 0 Writes are allowed 1 The CS signal is asserted one l cycle later on read and write 1 Writes are prohibited accesses and an extra cycle inserted between back to back Cyclas PA Description EDC Description 0 CS pin at logic high 0 No delay occurs after a read cycle 1 CS pin at logic low 1 One clock cycle is
38. The following steps are required to begin QSPI operation 1 Write the QPCR to configure unused pins for GPIO and the rest for QSPI 2 Write the SPCR to adjust Chip Select pin polarities and enable queues and interrupts 3 Write the QCRs to initialize the queue pointers and determine behavior when executing queues are preempted 4 Write the SCCR registers to adjust the baud rate phase polarity and delays for the SCK for each CS pin as well as the order bits are sent 5 Write the Data RAM with information to be transmitted for each queue 6 Write the Control RAM with control information for each queue including c Data width 8 or 16 bits d Enable data reception if applicable e Chip select or queue termination 7 Enable the QSPI by setting the QSPE bit in the SPCR At this point the QSPI awaits a queue trigger to initiate a transfer 8 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Operation 8 3 2 Queue Transfer Cycle A QSPI transfer is initiated by a transfer trigger There are eight possible sources of transfer triggers four from the MCU and four from the Protocol Timer An MCU trigger is activated by writing to one of the four trigger addresses at 0020_5FF8 0020_5FFE The content of the write is ignored the write itself is the trigger In normal operation the following sequence occurs 1 2 The MCU or Protoc
39. data ram define OSPI D RAM REDCAP MCU QSPI 0x400 Control Registers define QSPI C REG REDCAP MCU UART 0x 00 Manual Trigger Registers define OSPI T REG REDCAP MCU UART Oxff8 Hifdef ASSEM control registers define OSPI QPCR 0x00 define OSPI ODDR 0x02 define OSPI OPDR 0x04 define QSPI SPCR 0x06 B 30 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc define OSPI QCRO 0x08 define OSPI OCR1 0x0a define OSPI QCR2 0x0c define OSPI QCR3 0x0e define QSPI SPSR 0x10 define QSPI SCCRO 0x12 define OSPI SCCR1 0x14 define QSPI SCCR2 0x16 define QSPI SCCR3 0x18 define OSPI SCCR4 Oxla trigger registers define QSPI TRIGO 0x0 define OSPI TRIGl 0x2 define OSPI TRIG2 0x4 define QSPI TRIG3 0x6 else struct redcap qspi c reg unsigned short qpcr port control register unsigned short qddr port data direction register volatile unsigned short qpdr port data register unsigned short spcr spi control register volatile unsigned short qcr0 queue control register 0 volatile unsigned short qcrl1 queue control register 1 volatile unsigned short qcr2 queue control register 2 volatile unsigned short qcr3 queue control register 3 volatile unsigned short spsr spi status register unsigned short sccr0 serial channel control register 0 unsigned short sccrl serial chann
40. define REDCAP MCU RSR 0x0020C400 Reset Source Register define REDCAP MCU EMULPORT 0x0020C800 Emulation Port Control define REDCAP MCU GPCR 0x0020CC00 General Port Control Reserved 0x00300000 through O3fffffff External memory associated with chip Selects define REDCAP MCU CSO BASE 0x40000000 Chip Select 0 define REDCAP MCU CSO SIZE 0x01000000 define REDCAP MCU CS1 BASE 0x41000000 Chip Select 1 define REDCAP MCU CS1 SIZE 0x01000000 define REDCAP MCU CS2 BASE 0x42000000 Chip Select 2 define REDCAP MCU CS2 SIZE 0x01000000 define REDCAP MCU CS3 BASE 0x43000000 Chip Select 3 define REDCAP MCU CS3 SIZE 0x01000000 define REDCAP MCU CS4 BASE 0x44000000 Chip Select 4 B 22 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Include File define REDCAP MCU CS4 SIZE 0x01000000 define REDCAP MCU CS5 BASE 0x45000000 Chip Select 5 define REDCAP MCU CS5 SIZE 0x01000000 kkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP Clock Control Register example usage unsigned short clock unsigned short REDCAP MCU CKCTL kkkkkkkkkkkkkkkkkkkkkkkkkkkkk define REDCAP CKCTL CKIHD 0x0001 define REDCAP CKCTL MCS 0x0002 define REDCAP CKCTL MCD 1 0x0000 define REDCAP CKCTL MCD 2 0x0004 define REDCAP CKCTL 1 MCD 4 0x0008 define REDCAP CKCTL 1 MCD 8 0x000C define REDCAP CKCTL MCD 16 0x0010
41. A 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 2 3 memory read request memory read request is a long message from the MCU to the DSP requesting an upload of data from the program X or Y data space The format of this message is shown in Figure A 5 The next entry in MDI memory following the memory read request opcode is the number of DSP words to read The third entry contains two fields XYP and destination address offset The XYP field determines which memory space of the read as shown in Figure A 3 on page A 5 The destination address offset contains the location in MDI shared memory at which the DSP stores the data it reads The last entry source address indicates the address in DSP program X or Y memory space of the data to be read The choice of destination address offset is arbitrary but care should be taken to ensure that the DSP does not overwrite any of the words in the original message Figure A 5 Format of memory read request Message MDI Messaging Unit Registers 15 14 13 10 9 0 l MCU address DSP address i MCU_MDI_BASE 2 offset MDI Shared Memory DSP MDI BASE offset l memory_read request 5 of DSP words to read XYP unused dest address offset source address MCU_MDI_BASE DSP_MDI_BASE 2 dest_address_offset dest_address_offset DSP uses this location for its
42. Figure 12 5 SCP Interrupts Motorola Smart Card Port 12 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Registers 12 3 SCP Registers Table 12 1 is a summary of the SCP control and GPIO registers including the acronym bit names and address least significant halfword of each register The most significant halfword of all register addresses is 0020 Table 12 1 SCP Register Summary SCPCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B000 CKSEL NKOVR DOZE SIBR SCSRISCPT SCIC NKPE SCTESCRE SCACR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B002 SCCLK SCRS SCDPE SCPE APDE SCPIER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B004 SCTCIE SCFNIE SCFFIE SCREIE SMSCIE SCPSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B006 SCFFISCFN SCTY SCTC TXNK SCPE SCFE SCOE SMSC SCSP SCPDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B008 SCPD 7 0 SCPPCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B00A SMEN PDIR 4 0 PDAT 4 0 12 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 12 3 1 SCP Control Registers SCP Registers SCPCR SCP
43. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer CKP Description B B P 0 Transmit bit clock rising edge Receive bit clock falling edge default 1 Transmit bit clock falling edge B B P C RC Receive bit clock rising edge BBP Control Register C EE Address X FFA8 SCKD Description Reset 0000 0 External clock source Read Write 1 Internal clock source SCD2 Description SHFD Description 0 SCD2 pin is input 0 Data shifted out MSB first 1 SCD2 pin is output 1 Data shifted out LSB first SCD1 Description FSL1 FSLO Description 0 SCD1 pin is input 0 0 WL bit clock for both TX 1 SCD1 pin is output and RX 0 1 1 bit clock for TX SCDO Description WL bit clock for RX 0 SCDO pin is input 1 0 1 bit clock for both TX and RX 1 SCDO pin is output 1 1 WL bit clock for TX 1 bit clock for RX MOD Description FSR Description 0 Normal mode 0 Frame sync occurs with first bit of 1 Network mode current frame 1 Frame sync occurs with last bit of SYN Description previous frame 0 Asynchronous mode 1 Synch d FSP Description MEE Pre TERES 0 Positive frame sync 1 Negative frame sync 15 14 13 12 11 10
44. JSCLR bbbb S lt ea gt aaaa 4 JSCLR bbbb S lt aa gt aaaa JSCLR bbbb DDDDDD aaaa JSCLR bbbb S qq aaaa JSET JSET bbbb S lt pp gt aaaa JSET bbbb S ea aaaa 4 JSET bbbb S lt aa gt aaaa JSET bbbb DDDDDD aaaa JSET bbbb S qq aaaa JSR JSR aa JSR ea 3 JSSET JSSET bbbb S lt pp gt aaaa JSSET bbbb S lt ea gt aaaa JSSET bbbb S lt aa gt aaaa JSSET bbbb DDDDDD aaaa JSSET bbbb S lt qq gt aaaa LRA LRA PC Rn gt ODDDDD LRA PC aaaa gt ODDDDD T gt l T Qo A A A A Co a a A B A AP Ay A Ay A Cl ol a ala AP S al sto l l l l l A c l l Motorola Programmer s Reference D 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Instruction Reference Tables Table D 4 DSP Instruction Set Summary Continued Mnemonic Syntax CCR LSL LSL D LSL sss D LSL ii D LSR LSRD LSR ii D LSR sss D zz a a IN oj 0 o oj oj o lt LUA LEA LUA ea gt ODDDDD LUA Rn aa gt 01DDDD MAC MAC 2 s QQ d MAC S1 S2 D MAC su uu MAC S1 S2 D MACI MACR MACRI MAX MAX A B
45. PT Operation Rx Hit initiating activity corresponding to the entry s event code The pointer is then incremented to the next entry in the table In similar fashion the transmit macro uses the Transmit Macro Table Pointer TxPTR in MTPTR to generate Tx Hit The Event Control Unit ECU responds to FT Hit Tx Hit or Rx Hit by reading the event code EC associated with the table entry that generated the hit The ECU decodes the EC and initiates one of the following events Force one of the eight TOUT pins high or low e Issue one of the four QSPI triggers Control event table sequencing Alert the interrupt controller to generate one of these interrupts one of the three MCU interrupts DSP interrupt DSP IRQD one of the sixteen DSP vector interrupts In addition the ECU can initiate a Transmit or Receive Macro A macro cannot initiate another macro The Interrupt Controller receives inputs from the ECU CFC RSC and Error Detector to generate the appropriate interrupt Error detection is described in Section 10 2 4 on page 10 11 Interrupts are detailed in Section 10 2 5 on page 10 11 10 2 PT Operation This section describes all aspects of PT operation including sequencing and generating events within a frame and in the transmit and receive macros the various PT operating modes error detection and a summary of the interrupts generated by the PT 10 2 1 Frame Events The PT provides two frame tables to
46. Register Functional Block Page Acronym Name ElM CSO Chip Select 0 Register E 17 CS1 Chip Select 1 Register E 18 CS2 Chip Select 2 Register E 19 CS3 Chip Select 3 Register E 20 CS4 Chip Select 4 Register E 21 CS5 Chip Select 5 Register E 22 EIMCR EIM Configuration Register E 23 Emulation Port EPDDR Emulation Port Data Direction Register E 24 EPDR Emulation Port Data Register E 24 Interrupts ISR Interrupt Source Register E 25 NIER Normal Interrupt Enable Register E 27 FIER Fast Interrupt Enable Register E 29 NIPR Normal Interrupt Pending Register E 31 FIPR Fast Interrupt Pending Register E 33 ICR Interrupt Control Register E 35 IPRP Interrupt Priority Register Peripherals E 36 IPRC Interrupt Priority Register Core E 37 Edge Port EPPAR Edge Port Pin Assignment Register E 38 EPDDR Edge Port Data Direction Register E 38 EPDDR Edge Port Data Register E 38 EPFR Edge Port Flag Register E 38 QSPI SPCR Serial Port Control Register E 39 QCRO Queue Control Register 0 E 40 QCR1 Queue Control Register 1 E 40 QCR2 Queue Control Register 2 E 41 QCR3 Queue Control Register 3 E 41 SPSR Serial Port Status Register E 42 SCCRO Serial Channel Control Register O E 43 SCCR1 Serial Channel Control Register 1 E 44 SCCR2 Serial Channel Control Register 2 E 45 SCCR3 Serial Channel Control Register 3 E 46 SCCR4 Serial Channel Control Register 4 E 47 QSPI Control RAM E 48 QPCR QSPI Port Control Register E 49 QDDR QSPI Data Direction Register E 49 QPDR QSPI Port D
47. SCPSR SCP Status Register 0020_B006 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O SCFF SCFN SCTY SCTC TXNK SCPE SCFE SCOE SMSC SCSP RESET 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Table 12 5 SCPSR Description Name Type Description Settings SCFF R RDC SCP Receive FIFO Full Set when all four O FIFO can receive more data default Bit 9 receive FIFO characters are filled Cleared by 1 FIFO full reading the SCPDR SCFN R RDC SCP Receive FIFO Not Empty Set when O FIFO empty default Bit 8 the FIFO contains at least one character 1 FIFO not empty Cleared by reading the SCPDR SCTY R WDC SCP Transmit Register Empty Set when 0 Transmit register not empty Bit 7 the transmit data register is empty signalling 1 Transmit register empty default the MCU that a character can be written to SCPDR Cleared by reading the SCPDR Normally the MCU uses the SCTC bit rather than SCTY to determine when the next character can be sent SCTC R WDC SCP Transmit Complete Set after O Next transmission not complete Bit 6 transmitting the second stop bit of a frame 1 Transmission complete default one additional bit time later if a NACK is received Cleared by writing the SCPDR TXNK R WDC NACK Received for Transmitted Word 0 No NACK default Bit 5 Set when a NACK is detected while 1 NACK received transmitting a character Cleared by writing the SCPDR or by hardware reset TXNK is set simultaneously with S
48. equ mdi mcr mrie0 Oxf MCU Receive Interrupt 0 enable bits of the MCU side Status Register MSR equ mdi msr mf0 0x0 MCU side Flag 0 equ mdi msr mfl 0x1 MCU side Flag 1 equ mdi msr mf2 0x2 MCU side Flag 2 equ mdi msr mep Ox4 MCU side Event Pending equ mdi msr don 0x5 DSP power mode equ mdi msr msmp Ox6 MCU Shared Memory access pending equ mdi msr drs 0x7 DSP Reset State equ mdi msr dws 0x8 DSP Wake from Stop equ mdi msr mtir Ox9 MCU Protocol Timer wake DSP from stop amp IRO equ mdi msr mgipl Oxa MCU General Interrupt 1 pending equ mdi msr mgip0 Oxb MCU General Interrupt 0 pending equ mdi msr mtel Oxc MCU transmit register 1 empty equ mdi msr mte0 Oxd MCU transmit register 0 empty equ mdi msr mrfl Oxe MCU Receive register 1 full equ mdi msr mrf0 Oxf MCU Receive register 0 full f Protocol timer prot equates B 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc general definitions equ prot memory base address equ prot programable registers base address equ prot testmode registers base address MCU Equates 0x00203000 0x00203800 0x00203c00 programable registers of the protocol timer bits of equ Motorola prot tctr prot ptcr prot tier prot ptier prot tstr prot ptsr prot tevr prot ptevr prot tipr prot timl
49. l 1 1i Ili l 41l DMAC DMAC S1 S2 D ss su uu N 1 di ee DO DO xxx aaaa 5 2 54 NS A e m e DO DDDDDD aaaa 5 2597 eem DO S ea aaaa 5 U Siro a a gt sem DO S lt aa gt aaaa 5 NR TS jas ns e DO FOREVER DO FOREVER aaaa 4 ex ems ES ENDDO ENDDO 1 ns p pe ia c e etras EOR EOR SD P x quaeque eu EOR iiiiii D 2 2l 0 EOR iii D 1 _ 9 9l 0 EXTRACT EXTRACT SSS s D 1 10 EXTRACT iiii s D 2 10 D 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Instruction Reference Tables Table D 4 DSP Instruction Set Summary Continued CCR Mnemonic Syntax P T EXTRACTU EXTRACTU SSS s D 1 EXTRACTU diiii s D 2 IFcc IFcc 1 e aS a S ES Cu IFcc U IFcc U 7 2 2 ILLEGAL ILLEGAL INC INC D INSERT INSERT SSS qqq D INSERT iiii qqq D Jcc Jcc aa oj oO lt o ol o oj o oj o Jcc ea ms JCLR JCLR bbbb S lt ea gt aaaa 4 JCLR bbbb S lt pp gt aaaa JCLR bbbb S lt aa gt aaaa JCLR bbbb DDDDDD aaaa JCLR bbbb S lt qq gt aaaa JMP JMP aa JMP ea 3 JScc JScc aa JScc ea JSCLR JSCLR bbbb S lt pp gt aaaa
50. prot ctic prot ctipr prot ctiml prot cfc prot cfpr prot cfml prot rsc prot rspr prot rsml prot pdpar prot ptpcr prot pdadr prot ptddr prot pddat prot ptpdr prot ftptr prot rtptr prot mtptr prot ftbar 0x0 0x0 0x2 0x2 0x4 0x4 0x6 0x6 0x8 0x8 Oxa Oxc Oxc Oxe 0x10 0x10 0x12 0x14 0x14 0x16 0x16 0x18 0x18 Oxla Oxla Oxic Oxle Oxle 0x20 0x22 0x22 0x24 prot tctr te prot tctr time prot tctr mter prot tctr tdzd prot tctr spbp prot tctr hltr prot tctr cfce prot tctr rsce prot ptcr te equ prot ptcr time control register old name control register NEW NAME interrupt enable register old name interrupt enable register NEW NAME status register old name Status register NEW NAME timer event register old name timer event register NEW NAME time interval prescaler old name time interval modulus latch NEW NAME Channel time interval counter Channel time interval preload register old name Channel time interval modulus latch NEW NAME Channel frames counter Channel frames preload register old name Channel frames modulus latch NEW NAME Reference slot counter Reference slot preload register old name Reference slot modulus latch NEW NAME Port D functionalty register old name Protocol Timer Port Control Register NEW NAME Port D directivity register old name Protocol Timer Data Direction Register NEW NAME Po
51. 0 ee eee eee eee eee C 4 Appendix D Programmer s Reference MCU Instruction Reference Tables a 23 5 3 st dede D 1 DSP Instruction Reference Tables 2o ses HEP OSS RII D 7 MCU Internal I O Memory Map 0 cece eee D 14 DSP Internal I O Memory Mapivet 3 24 tes weh ERES ERR Gee ees D 19 Resister Index 2S usa d yh Ree Ss ees Wa o S eee a ee eens D 22 Acronym Changes AE eee tay ES eS A o ACE pd AS D 26 Appendix E Programmer s Data Sheets DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Figure 1 1 Figure 2 1 Figure 3 1 Figure 3 2 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 6 1 Figure 6 2 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 8 1 Figure 8 2 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Motorola DSP56652 Block Diagram ci A EX RRAEERMAE 1 2 Signal Group OrSanIZ OO A Es 2 2 MCU Memory Map ds sia ou a ore Ala p AL Ce Nt 3 2 e A et ane ts oa eae eat Wate es Sete a M 3 5 DSP56652 Clock Scheme s soia ra oso Rb des 4 2 DSP PLL and Clock Generator iive tha chs ob da 4 3 DSP56652 Reset Circuits ede wh Pede tX ES ed ne aa dt 4 10 MUX Connectivity Scheme 20 cee cee eee eee nee 4 17 MDI Block Diagram cesse ete Ro Rt A ha 5 1 MDI DSP Side Memory Mapping
52. 0 Another event dsp int affects the DSP indirectly by generating DSP IRQD through the MDI Refer to the description of the MTIR bit in the MSR on page 5 21 Dsp irq differs from the CVR events in that it can wake the DSP from STOP mode 10 2 6 General Purpose Input Output GPIO Any of the eight PT output pins TOUT7 0 can be configured as GPIO GPIO functionality is determined by three registers The Protocol Timer Port Control Register PTPCR determines which pins are GPIO and which function as PT pins The Protocol Timer Direction Register PTDDR configures each GPIO pin as either an input or output 10 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Event Codes The Protocol Timer Port Data Register PTPDR contains input data from GPI pins and data to be driven on GPO pins GPIO register functions are summarized in Table 10 3 Table 10 3 PT Port Pin Assignment Port Pin i Function 1 X Protocol Timer 0 0 GP input 0 1 GP output 10 3 PT Event Codes Table 10 4 lists the 128 possible PT events and their corresponding event codes Table 10 4 Protocol Timer Event List Event Name Conn Description Tx macro 00 Start Tx macro with delay O Tx macro1 01 Start Tx macro with delay 1 Tx macro2 02 Start Tx macro with delay 2 Tx macro3 0
53. 0000 0020_0008 FIER Fast Interrupt Enable Register 0000 0020_000C NIPR Normal Interrupt Pending Register 0000 0020_0010 FIPR Fast Interrupt Pending Register 0000 0020_0014 ICR Interrupt Control Register 0000 External Interface Module EIM 0020_1000 CSO Chip Select O Register F861 0020_1004 CS1 Chip Select 1 Register uuuu 0020_1008 CS2 Chip Select 2 Register uuuu 0020_100C CS3 Chip Select 3 Register uuuu 0020_1010 CS4 Chip Select 4 Register uuuu 0020_1014 CS5 Chip Select 5 Register uuuu 0020_1018 EIMCR EIM Configuration Register 0038 MCU DSP Interface MDI 0020_2FF2 MCVR MCU Side Command Vector Register 0060 0020_2FF4 MCR MCU Side Control Register 0000 0020_2FF6 MSR MCU Side Status Register 3080 0020_2FF8 MTR1 MCU Transmit Register 1 0000 0020 2FFA MTRO MCU Transmit Register O 0000 0020 2FFC MRR1 MCU Receive Register 1 0000 0020 2FFE MRRO MCU Receive Register O 0000 DSP56652 User s Manual Motorola Freescale Semiconductor Inc MCU Internal I O Memory Map Table D 8 MCU Internal I O Memory Map Continued Address Register Name Reset Value Protocol Timer PT 0020_3800 PTCR PT Control Register 0000 0020_3802 PTIER PT Interrupt Enable Register 0000 0020_3804 PTSR PT Status Register 0000 0020_3806 PTEVR PT Event Register 0000 0020_3808 TIMR Time Interval Modulus Register 0000 0020_3
54. 0020_408C UDDR UART Data Direction Register 0000 0020_408E UPDR UART Port Data Register 000u Queued Serial Peripheral Interface QSPI 0020_5000 to 0020_507F QSPI Control RAM uuuu 0020 5400 to 0020 547F QSPI Data RAM uuuu 0020 5F00 QPCR QSPI Port Control Register 0000 0020 5F02 QDDR QSPI Data Direction Register 0000 0020 5F04 QPDR QSPI Port Data Register 0000 0020 5F06 SPCR Serial Port Control Register 0000 0020 5F08 QCRO Queue Control Register 0 0000 0020 5F0A QCR1 Queue Control Register 1 0000 0020 5FO0C QCR2 Queue Control Register 2 0000 0020 5FOE QCR3 Queue Control Register 3 0000 0020_5F10 SPSR Serial Port Status Register 0000 0020_5F12 SCCRO Serial Channel Control Register O 0000 0020_5F14 SCCR1 Serial Channel Control Register 1 0000 0020 5F16 SCCR2 Serial Channel Control Register 2 0000 0020 5F18 SCCR3 Serial Channel Control Register 3 0000 0020_5F1A SCCR4 Serial Channel Control Register 4 0000 0020_5FF8 MCU Trigger for Queue O 0020_5FFA MCU Trigger for Queue 1 0020_5FFC MCU Trigger for Queue 2 0020_5FFE MCU Trigger for Queue 3 General Purpose Timer and Pulse Width Modulator PWM 0020_6000 TPWCR Timers and PWM Control Register 0000 0020_6002 TPWMR Timers and PWM Mode Register 0000 D 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Internal I O Memory Map Table D 8 MCU Internal I O Memory Map
55. 1 Enabled When MRIEO is cleared MRFO is ignored and no receive interrupt request 0 is issued MRIE1 R W MCU Receive Interrupt Enable 1 When O Receive interrupt 1 request disabled Bit 14 MRIE1 is set a receive interrupt request 1 is default issued when the MRF1 bit in the MSR is set 1 Enabled When MRIE1 is cleared MRF1 is ignored and no receive interrupt request 1 is issued MTIEO R W MCU Transmit Interrupt Enable 0 If MTIEO O Transmit interrupt O request disabled Bit 13 is set a transmit interrupt O request is default generated when the MTEO bit in the MSR is 1 Enabled set If MTIEO bit is cleared MTEO is ignored and no transmit interrupt request 0 is issued MTIE1 R W MCU Transmit Interrupt Enable 1 If MTIE1 O Transmit interrupt 1 request disabled Bit 12 is set a transmit interrupt 1 request is default generated when the MTE1 bit in the MSR is 1 Enabled set If MTIE1 bit is cleared MTE1 is ignored and no transmit interrupt request 1 is issued MGIEO R W MCU General Interrupt Enable 0 If this bit O General interrupt O request disabled Bit 11 is set a general interrupt O request is issued default when the MGIPO bit in the MSR is set If 1 Enabled MGIEO is clear MGIPO is ignored and no general interrupt request 0 is issued MGIE1 R W MCU General Interrupt Enable 1 If this bit O General interrupt 1 request disabled Bit 10 is set a general interrupt 1 request is issued default when th
56. 11 1 UART Definitions The following definitions apply to both transmitter and receiver operation 1 Using GPIO pins for DSR DCD DTR and RI 2 Using the GP timer Motorola UART 11 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Architecture Bit Time The time allotted to transmit or receive one bit of data Start Bit One bit time of logic zero that indicates the beginning of a data frame A start bit must begin with a one to zero transition Stop Bit One bit time of logic one that indicates the end of a data frame Frame A series of bits consisting of the following sequence 1 A start bit 2 7 or 8 data bits 3 optional parity bit 4 oneor two stop bits BREAK A frame in which all bits including the stop bit are logic zero This frame is normally sent to signal the end of a message or the beginning of a new message Framing Error An error condition in which the expected stop bit is a logic zero This can be caused by a misaligned frame noise a BREAK frame or differing numbers of data and or stop bits between the two devices Note that if a UART is configured for two stop bits and only one stop bit is received this condition is not considered a frame error Parity Error An error condition in which the calculated parity of the received data bits in a frame differs from the frame s parity bit Parity error is only calculated after an entire fra
57. 2 1 1 1 1 1 2 1 1 1 1 4 n2 e STDA SRDA SCKA SCOA SC2A STDB SRDB SCKB SCOB SC2B ine o N SIZO SIZ1 PSTATO PSTAT3 MCU_DE DSP_DE Boom oa a an ua TCK TDI TDO TS TRST TEST Figure 2 1 Signal Group Organization DSP56652 User s Manual For More Information On This Product Go to www freescale com External Interrupts Protocol Timer Keypad Port UART Queued Serial Peripheral Interface QSPI Smart Card Port SCP Serial Audio Codec Port SAP Baseband Codec Port BBP Emulation Port Debug Control Port JTAG Test Access Port TAP Motorola 2 1 Power Freescale Semiconductor Inc Power The DSP36652 power pins are listed in Table 2 2 Table 2 2 Power Power Signals Description Voca Address bus power Lines C1 and F1 supply isolated power to the address bus drivers Voce SIM power Line L8 supplies isolated power for the smart card I O drivers Veco Bus control power Line L3 supplies power to the bus control logic Veco Data bus power These lines supply power to the data bus Voce Audio codec port power This line supplies power to audio codec I O drivers Vecr Clock output power This line supplies a quiet power source for the CKOUT output Ensure that the input voltage to this line is well regulated and uses an extremely low impedance path to ti
58. 3 or the MCU command interrupt IPL 0 2 These interrupts are issued by setting the appropriate bits in MCVR See Table 5 10 on page 5 18 7 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Interrupt Controller Table 7 7 Interrupt Source Priorities within an IPL Level 3 Non maskable Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest MDI MCU NMI Levels 0 1 2 Maskable Highest TRQA Protocol Timer CVRO IRQB from DSP_IRQ pin Protocol Timer CVR1 IRQC from MDI Protocol Timer CVR2 TRQD from Protocol Timer Protocol Timer CVR3 MDI MCU command Protocol Timer CVR4 BBP Receive Data with Overrun Error Protocol Timer CVR5 BBP Receive Data Protocol Timer CVR6 BBP Receive Last Slot Protocol Timer CVR7 BBP Receive Frame Counter Protocol Timer CVR8 BBP Transmit Data with Underrun Error Protocol Timer CVR9 BBP Transmit Last Slot Protocol Timer CVR10 BBP Transmit Data Protocol Timer CVR11 BBP Transmit Frame Counter Protocol Timer CVR12 SAP Receive Data with Overrun Error Protocol Timer CVR13 SAP Receive Data Protocol Timer CVR14 SAP Receive Last Slot Protocol Timer CVR15 SAP Transmit Data with Underrun Error MDI Receive O SAP Transmit Last Slot MDI Receive 1 SAP Transmit Data MDI Transmit O SAP Timer Counter Rollover Lowest MDI Transmit 1 7 2
59. 6 U A MOVEM P lt aa gt DDDDDD 6 2 MOVEP MOVEP S lt pp gt s lt ea gt 2 U A 2121912 2 2 MOVEP S lt pp gt P lt ea gt 6 U A 2 2 2 MOVEP S lt pp gt DDDDDD 1 2 2 2 MOVEP X lt qq gt s lt ea gt 2 U A 2 2 2 2 MOVEP Y lt qq gt s lt ea gt zz 2 U A 2 2 MOVEP X lt qq gt DDDDDD 1 2 MOVEP Y lt qq gt DDDDDD 1 MOVEP S lt qq gt P lt ea gt 6 U A 2121912 ou x MPY MPY 2 s QQ d 1 mn ee ca Md a MPY su uu MPY S1 S2 D su uu 1 es rst mes 7 nn MPYI MPYI Ziiiiii QQ D 2 ELS E SE MPYR MPYR 2 s QQ d 1 SL oe arse est i s MPYRI MPYRI iiiiii QQ D 2 e ax 5 Xx au NEG NEG D P Al Sese X NOP NOP 1 5 eR Rm NORMF NORMF SSS D 1 pex ew 1 2 NOT NOT D P X ee IE Pea 0 210 OR OR SD P Il l l lol OR iiiiii D 2 a pue 3 59 ce OR iii D 1 a 3 mms ORI ORI EE 3 2 21 REP REP xxx 5 a a a a NE REP DDDDDD 5 trio P la REP S lt ea gt 54U Y M E E TR REP S lt aa gt 5 wei em o A ea eee RESET RESET 7 NR rd ra a ira RND RND D P MESS LE ROL ROLD P Ss peser me rr ROR RORD P l 1 2 0 RTI RTI 3 2 2 RTS RTS 3 zm fy ee E E E SBC SBC S D P a SEE E Ei STOP STOP 10 a ce s SUB S
60. A delay of up to four instructions can occur between an MDI register write and the resulting change in the DSR Refer to the 56600 Family Manual Appendix B Section 5 Peripheral Pipeline Restrictions for a description of possible problems and work arounds Testing the DEP bit in the DSR requires one additional clock delay above the 56600 manual description Continuous one cycle accesses to the Shared Memory Can stall MCU Refer to Example 5 2 on page 5 4 for sample code that avoids lengthy MCU stalls Entering DSP STOP mode Motorola Enable IRQC write a non zero value to the ICPL bits in the IPRC Enable IRQD write a non zero value to the IDPL bits in the IPRC Ensure minimum delay from previous STOP mode Section 5 3 2 on page 5 12 Ensure the DEP bit in the DSR is cleared MCU DSP Interface 5 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Software Restriction Summary Table 5 6 DSP Side Restrictions Action Restriction Clearing serviced interrupts Table 5 7 MCU Side Restrictions Write 1 to the DWSC bit in the DSR to clear IRQC Write 1 to the DTIC bit in the DSR to clear IRQD Action Restriction Byte wide writes to shared memory The MDI latches all 16 bits when receiving data written to it In byte wide writes the MCU drives only the written 8 bits the unspecified byte in the shared memory
61. CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit CTIC value bit the Time Interval Preload Register TIPR oe names the Time Interval Modulus Register TIMR NEW NAMES WO Dd UH CO PO ILS CO 0x0 CTIPR value bit 0 0x1 CTIPR value bit 1 Equates and Header Files For More Information On This Product Go to www freescale com the Channel Time Interval Preload Register CTIPR old names B 5 MCU Equates bits of the Channel Time Interval Modulus Register CN NEW NAMES bits of the Channel Frame Counter bits of the Channel Frame Preload Register CFPR old names bits of the Channel Frame Modulus Register CFMR NEW NAMES B 6 equ equ Freescale Semiconductor Inc prot ctipr ctipv 2 prot ctipr ctipv 3 prot ctipr ctipv 4 prot ctipr ctipv 5 prot ctipr ctipv 6 prot ctipr ctipv 7 prot ctipr ctipv 8 prot ctipr ctipv 9 prot ctipr ctipv 10 prot ctipr ctipv 11 prot ctipr ctipv 12 prot ctipr ctipv 13 prot ctiml ctimv 0 prot ctiml ctimv 1 prot ctiml ctimv 2 prot ctiml ctimv 3 prot ctiml ctimv L4 prot ctiml ctimv 5 prot ctiml ctimv 6 prot ctiml ctimv 7 prot ctiml ctimv 8 prot ctiml ctimv 9 prot ctiml ctimv_ 10 prot ctiml ctimv Zu prot cti
62. D 15 8 D 7 0 1 Bytes labeled with a dash are not required They are ignored on read transfers and driven with undefined data on write transfers 6 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Features 6 3 4 Error Conditions The following conditions cause a Transfer Error Acknowledge TEA to be asserted to the MCU e An access to a disabled chip select 1 e an access to a mapped chip select address space where the CSEN bit in the corresponding CS control register is clear e A write access to a write protected chip select address space 1 e the WP bit in the corresponding CS control register is set e A user access to a supervisor protected chip select address space 1 e the SP bit in the corresponding CS control register is set A bus watchdog time out when an access does not terminate within 128 clocks of being initiated e A user access to a supervisor protected internal ROM RAM or peripheral space i e the corresponding SP bit in the EIM Configuration register is set 6 3 5 Displaying the Internal Bus Show Cycles Although the MCU can transfer data between internal modules without using the external bus it may be useful to display an internal bus cycle on the external bus for debugging purposes Such external bus cycles called show cycles are enabled by the SHEN 1 0 bits in the EIM Configurat
63. Each defined bit in this register corresponds to an MCU interrupt source If an interrupt is asserted and the corresponding NIER bit is set the interrupt controller asserts a normal interrupt request to the core If the corresponding NIER bit is cleared i e if the interrupt is masked the interrupt is not passed to the core and does not affect the high priority interrupt circuit All interrupts are masked out of reset Register bits corresponding to unused interrupts may be read and written but have no affect on interrupt controller operation Only word writes will update the NIER Byte or half word writes will terminate normally but will not update the register The FIER works identically to the NIER except that a fast interrupt is generated for a given request rather than a normal interrupt Care should be taken to avoid setting the same bit position in both registers or both a normal and fast interrupt will be generated Motorola Interrupts 7 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Interrupt Controller Table 7 3 NIER FIER Description Name Bit s Interrupt Setting NIER FIER EURX EFURX 31 UART Receiver Ready O Interrupt source masked ESMPC EFSMPC 30 SCP Position Change eS enabled EUTX EFUTX 29 UART Transmitter EPT2 0 EFPT2 0 28 26 Protocol Timer 2 0 EPTM EFPTM 25 Protocol Timer Interrupts EQSP
64. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates I_IRQD EQU I VEC 16 IROD from Protocol Timer wake from stop Protocol Timer Interrupts I PT CVRO EQU I VEC 20 Protocol Timer CVRO I PT CVR1 EQU I VEC 22 Protocol Timer CVR1 I PT CVR2 EQU I VEC 24 Protocol Timer CVR2 I PT CVR3 EQU I VEC 26 Protocol Timer CVR3 I PT CVR4 EQU I VEC 28 Protocol Timer CVR4 I PT CVR5 EQU I VEC 2A Protocol Timer CVR5 I PT CVR6 EQU I VEC 2C Protocol Timer CVR6 I PT CVR7 EQU I VEC S2E Protocol Timer CVR7 I PT CVR8 EQU I VEC 30 Protocol Timer CVR8 I PT CVR9 EQU I VEC 32 Protocol Timer CVR9 I PT CVR10 EQU I VEC 34 Protocol Timer CVR10 CVR11 EQU 1 VEC S36 Protocol Timer CVR11 Protocol Timer CVR12 Protocol Timer CVR13 Protocol Timer CVR14 Protocol Timer CVR15 CVR12 EQU I VEC 38 CVR13 EQU I VEC S3A CVR14 EQU I VEC S3C CVRI5 EQU I VEC S3E 23993 r A A EF SCHENN I SAP RD EQU I VEC 40 SAP Receive Data SAP Receive Data With Exception Status I SAP RLS EQU I VEC 44 SAP Receive last slot I SAP TD EQU I VEC4 46 SAP Transmit data I SAP TDE EQU I VEC 48 SAP Transmit Data With Exception Status I SAP TLS EQU I VEC 4A SAP Transmit last slot I SAP TRO EQU I VEC S4C SAP Timer counter roll over BBP Interrupts I BBP RD EQU I VEC4 50 BBP Receive Data I BBP RDE E
65. Freescale Semiconductor Inc Application Date Programmer Control RAM Address 0020_5000 to 507F Rer Reset 0000 CONT Description Read Write 0 Deactivate chip select 1 Keep chip select active PAUSE Description 0 Not a queue boundary 1 Queue boundary PCS 0 2 Delay After Transfer 000 SPICO activated 001 SPIC1 activated 010 SPIC2 activated 011 SPIC3 activated RE Description 100 SPIC4 activated 0 Receive disabled 101 NOP No SPIC line activated 1 Receive enabled 110 EOTIE End of transfer interrupt enabled 111 EOQ End of queue BYTE Description 0 16 bit data 1 8 bit data 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 PCS2 PCS1 PCSO Reserved E 48 For More Information On This Product DSP56652 User s Manual Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer Q P R QPCn Description 0 Pin is GPIO pin QSPI Port Control Register Address 0020 5F00 1 Pin is QSPI pin Reset 0000 Read Write 15 14 13 12 11 10 7 6 5 4 3 2 1 0 QPC7 QPC6 QPC5 QPC4 QPC3 QPC2 QPC1 QPCO QDDR QSPI Data Direction Register Address 0020 5F02 Reset 0000 Read Write Description P
66. MCU or DSP hardware reset asserting MDIR or asserting DHR poll the DRS bit in the MSR until it is cleared before accessing the shared memory to ensure DSP reset is complete After DSP reset 5 16 Ensure that the DSP PLL has been relocked e g item 5 on page 5 5 before the MCU accesses shared memory DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers 5 6 MDI Registers In general the MDI registers on the DSP side and MCU side are symmetrical They are summarized in Table 5 8 Table 5 8 MDI Signalling and Control Registers MCU Side DSP Side Function Name Address Name Address MCU Command Vector Register MCVR 0020_2FF2 Control Register MCR 0020 2FF4 DCR X FF8A Status Register MSR 0020 2FF6 DSR X FF8B Transmit Register 1 MTR1 0020_2FF8 DTR1 X FF8C Transmit Register O MTRO 0020_2FFA DTRO X FF8D Receive Register 1 MRR1 0020 2FFC DRR1 X FF8E Receive Register O MRRO 0020_2FFE DRRO X FF8F The correspondence between transmit registers on one side and receive registers on the other side is listed in Table 5 9 Table 5 9 MCU DSP Register Correspondence MCU Register MCU Address DSP Register DSP Address MTR1 0020 2FF8 DRR1 X FF8E MTRO 0020_2FFA DRRO X FF8F MRR1 0020 2FFC DTR1 X FF8C MRRO 0020_2FFE DTRO X FF8D Motorola MCU DS
67. NEW NAMES equ prot rsml rsmv 0 0x0 rsml value bit 0 equ prot rsml rsmv 1 0x1 rsml value bit 1 equ prot rsml rsmv 2 0x2 rsml value bit 2 equ prot rsml rsmv 3 0x3 rsml value bit 3 equ prot rsml rsmv 4 Ox4 rsml value bit 4 equ prot rsml rsmv 5 0x5 rsml value bit 5 equ prot rsml rsmv 6 0x6 rsml value bit 6 equ prot rsml rsmv 7 0x7 rsml value bit 7 bits of the Port D Pin Assignment Register PDPAR old names equ prot pdpar pdgpc 0 0x0 Select the function of pin 0 in port equ prot pdpar pdgpc 1 0x1 Select the function of pin 1 in port equ prot pdpar pdgpc 2 0x2 Select the function of pin 2 in port equ prot pdpar pdgpc 3 0x3 Select the function of pin 3 in port equ prot pdpar pdgpc 4 0x4 Select the function of pin 4 in port equ prot pdpar pdgpc 5 0x5 Select the function of pin 5 in port equ prot pdpar pdgpc 6 0x6 Select the function of pin 6 in port equ prot pdpar pdgpc 7 0x7 Select the function of pin 7 in port UUUUUUUU bits of the Protocol Timer Port Control Register PTPCR NEW NAMES equ prot ptpcr ptpc 0 0x0 Select the function of pin 0 in port D equ prot ptpcr ptpc 1 0x1 Select the function of pin 1 in port D equ prot ptpcr ptpc 2 0x2 Select the function of pin 2 in port D equ prot ptpcr ptpc 3 0x3 Select the function of pin 3 in port D equ prot ptpcr ptpc 4 0x4 Select the function of pin 4 in port D Motorola Equates and Header Files B 7 For More Info
68. Nevertheless the user may wish to ensure that all shared memory writes are completed before entering STOP This can be done by polling MSR bit 6 until it is cleared before issuing the STOP instruction 3 Pending MCU events MCU software should poll the MEP bit in the MSR until it is cleared just before issuing the STOP instruction This ensures that the DSP has acknowledged all previous MCU generated events so that it can be made aware of the MCU power mode change 5 3 2 DSP Low Power Modes The MCU can wake the DSP from WAIT mode by issuing any of the interrupts listed in Section 5 2 3 1 on page 5 10 MCU software can wake the DSP from STOP in one of the following three ways 1 A DSP Wake from STOP command setting the DWS bit in the MSR 2 A Protocol Timer DSP interrupt 3 A DSP hardware reset setting the DHR bit in the MCR 5 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes The MCU can also wake the DSP externally with an external DSP interrupt external DSP debug request JTAG DSP debug command or system reset DSP software should ensure that the MCU can track each DSP transition to and from STOP mode before the next one occurs This is essential for proper control of the shared memory clock see Section 5 3 3 One way to accomplish this is to provide a minimum delay measured in MCU clocks between consecutive DSP entranc
69. Normal Interrupt Pending Register Upper Halfword Bae Address 0020_000C META Description Reset 0000 0 No interrupt pending Read Write 1 Protocol Timer interrupt request pending NPT1 Description 0 No interrupt pending NQSPI Description 1 Protocol Timer MCU interrupt x request pending 0 No interrupt pending 1 QSPI interrupt request pending NPT2 Description 0 No interrupt pending NMDI Description 1 Protocol Timer MCU2 interrupt 0 No interrupt pending request pending 1 MDI interrupt request pending NUTX Description 0 No interrupt pending NSCP Description 1 UART Transmitter Ready interrupt 0 No interrupt pending request pending 1 SIM Card Tx Rx or Error interrupt request pending NSMPD Description 0 No interrupt pending NTPW Description 1 SIM Auto Power Down interrupt 0 No interrupt pending request pending 7 1 General Purpose Timer PWM interrupt request pending NURX Description 0 No interrupt pending NPIT Description 1 UART Receiver Reagy interrupt request pending 0 No interrupt pending 1 Periodic Interrupt Timer interrupt request pending 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NURX NSMPD NUTX NPT2 NPT1 NPTO NPTM NQSPI NMDI NSCP NTPW NPIT 0 0 0 0 NOTE NIPR can only be written as a 32 bit Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 31 Freescale Semiconductor Inc
70. RSR Register 0020 C400 CKCTL Register x 0020 C000 SIM Card Reserved 1 2M 0020 B000 Keypad GPIO 0020_A000 0020_9000 0020_8000 0020_7000 0040_0000 0020_6000 Peripherals 2M 0020_5000 0020_0000 0020_4000 2 kbytes Internal RAM Modulo Mapped in 0020_3000 0010_0000 0020_2000 16 kbytes Internal ROM Modulo Mapped in 0020_1000 0000_0000 0020_0000 Figure 3 1 MCU Memory Map 3 1 2 RAM The MCU memory map allocates 1 Mbyte for internal RAM The actual size of the RAM is 2 KB starting at address 0010_0000 and is modulo mapped into the remainder of the 1 Mbyte space Read and write access to internal RAM space returns TA except in user 3 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Memory Map mode while supervisor protection is active in which case TEA is returned resulting in termination and an access error exception Software should not rely on modulo mapping because future DSP5665x chip implementations may behave differently 3 1 3 Memory Mapped Peripherals Interface requirements for MCU peripherals are defined to simplify the hardware interface implementation while providing a reasonable and extendable software model The following requirements are currently defined others may be added in the future Agiven peripheral device appears only in the 4 kbytes region s allocated to it e Fo
71. Reset State Signal Description SPICSO SPICS4 Output GPI Serial peripheral interface chip select 0 4 These output signals provide chip select signals for the Queued Serial Peripheral Interface QSPI The signals are programmable as active high or active low SPICSO 3 have internal pull up resistors and SPICS4 has an internal pull down resistor SCK Output GPI Serial clock This output signal provides the serial clock from the QSPI for the accessed peripherals The delay number of clock cycles between the assertion of the chip select signals and the first transmission of the serial clock is programmable The polarity and phase of SCK are also programmable MISO MOSI Input Output GPI GPI Synchronous master in slave out This input signal provides serial data input to the QSPI Input data can be sampled on the rising or falling edge of SCK and received in QSPI RAM most significant bit or least significant bit first Synchronous master out slave in This output signal provides serial data output from the QSPI Output data can be sampled on the rising or falling edge of SCK and transmitted most significant bit or least significant bit first 8 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Architecture Address Control RAM 64x7 Address Status Register
72. SAPSR or BBPSR The pin is latched during reception of the first received bit after an RES and the corresponding IF bit is set when the contents of the port s receive shift register are transferred to the SAPRX or BBPRX Latching the flag input pin allows the signal to change state without affecting the flag state until the first bit of the next received word When configured as an output the flag pin reflects the state of the Output Flag OFO or OF 1 bit in Control Register B SAPCRB or BBPCRB When one of these bits is changed the value is latched the next time the contents of SAPTX or BBPTX are transferred to the port s transmit shift register The corresponding flag pin changes state at the start of the following frame normal mode or time slot network mode and remains stable until the first bit of the following word is transmitted Use the following sequence for setting output flags when transmitting data 1 Wait for the TDE bit to be set indicating the TXB register is empty 2 Write the OFO and OF bits flags 3 Write the transmit data to the TXB register For each port the two flags operate independently but can be used together for multiple serial device selection They can be used unencoded to select one or two codecs or can be decoded externally to select up to four codecs 14 3 5 TDM Interrupts In network mode interrupts can be generated at the end of the last slot in a transmit or receive frame The interrupts a
73. TMS is used to sequence the TAP controller state machine It is sampled on the rising edge of TCK Note When this signal is enabled the primary TMS signal is disconnected from the TAP controller See Table 2 19 on page 2 19 DSP IRQ Input Input DSP External Interrupt Request This active low Schmitt trigger input can be programmed as a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If the DSP is in the STOP state and DSP IRQ is asserted the DSP exits the STOP state 1 As Schmitt trigger interrupt inputs these signals can be programmed to be level sensitive positive edge triggered or negative edge triggered An edge triggered interrupt is initiated when the input signal reaches a particular voltage level regardless of the rise or fall time However as signal transition time increases the probability of noise generating extraneous interrupts also increases 2 7 Protocol Timer Table 2 10 describes the eight Protocol Timer signals Table 2 10 Protocol Timer Output Signals Name Type Reset State Signal Description TOUTO Input or Input Timer Outputs 0 7 These timer output signals can also be configured TOUT7 Output as GPIO The default function after reset is GPI Motorola Signal Connection Description 2 9 For More Information On This Product Go to www freescale com Keypad Port Freescale Semiconductor
74. Together with 0 Data is changed on the first transition of Bit 15 CKPOLn this bit determines the relation SCK default between SCK and the data stream on MOSI 1 Data is latched on the first transition of and MISO When the CPHAn bit is set data SCK is changed on the first transition of SCK when the SPICSn line is active When the CPHAn bit is cleared data is latched on the first transition of SCK when the SPICSn line is active The timing diagrams for QSPI transfer when CPHAn is 0 and when CPHAn is 1 are shown in Figure 8 2 on page 8 21 CKPOLn Clock Polarity for SPICSn Selects the 0 Bit 14 logic level of SCK when the QSPI is not 1 transferring data the QSPI is inactive When the CKPOLn bit is set the inactive state for SCK is logic 1 When the CKPOLn bit is cleared the inactive state for SCK is logic 0 CKPOL is useful when changes in SCK polarity are required while SPICSn is inactive The timing diagrams for QSPI transfer when CKPOLn is O and when CKPOLn is 1 are shown in Figure 8 2 on page 8 21 Inactive SCK state logic low default Inactive SCK state logic high Motorola Queued Serial Peripheral Interface 8 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory Table 8 6 SCCR Description Continued Name Description Settings LSBFn Bit 13 Transfer Least Significant Bit First for SPICSn These bits s
75. UPDR Description Name Description UPD 3 0 UART Port GPIO Data 3 0 Each of these bits contains data for the corresponding UART pin if it Bits 3 0 is configured as GPIO Writes to UPDR are stored in an internal latch and driven on any port pin configured as an output Reads of this register return the value sensed on input pins and the latched data driven on outputs 11 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 12 Smart Card Port The Smart Card Port SCP is a serial communication channel designed to obtain user information such as identification It is a customized UART with additional features for the SCP interface as specified by ISO 7816 3 and GSM 11 11 Typically a DSP56652 application uses this port to obtain subscriber information and a smart card containing this information is referred to as a Subscriber Interface Module SIM Figure 12 1 presents a block diagram of the SCP SCP Clock Transmitter Receiver SCP it nterrup pe SCDPE Auto Power Down Metre 1 4 1i SIMDATA SIMCLK SENSE PWR EN SIMRESET Power Power Switch o aa Interface and SMPC Data Clock Sense Voc Reset Smart Card Figure 12 1 Smart Card Port Interface Systems that do not require the SCP can configure the port as GPIO 12 1 SCP Architecture This section gives an overview of the SCP pin
76. Write the Transmit Register with the first transmit data word If no data is to be sent for the first time slot write to the Time Slot register SAPTSR or BBPTSR instead to avoid an underrun error The content written to the Time Slot Register is irrelevant and ignored Set the TE bit 3 If the Transmit Register has been written the data is copied to the transmit shift register at the next TES for the first time slot in a frame For other time slots the copy takes place at the beginning of the next time slot The Transmit Register retains the current data until it is written again The TDE bit is set If the TIE bit is set an interrupt is generated At this point the Transmit Register or Time Slot Register is written depending on the following circumstances f If data is to be transmitted in the next time slot that data is written to the Transmit Register g Ifthe next time slot is idle but subsequent time slots are to be used the Time Slot Register is written to avoid a transmit underrun error Either of these writes clears TDE If the shift register contains data the data is shifted out to the STDx pin clocked by the transmit bit clock If the shift register is empty data was written to the Time Slot Register rather than the Transmit Register the STDx pin is tri stated for that time slot If data is to be sent for any subsequent time slots in the frame or if this is the last time slot in the frame the cycle re
77. X 73 X 73 safe ccell X 73 X 73 X 8 X 8 X 8 X 8 1 amp 1 amp X amp X amp X 86 X 8 X 8 X 8 0 amp X 87 X 87 X 101 X 101 X 101 safe ccell X 101 1 amp X 101 X 101 X 101 X 101 X 114 X 114 X 114 X 114 X 114 X 114 X 114 X 114 1 amp X 114 1 Z amp X 114 X 114 X 8 safe ccell X 8 1 amp X 121 1 amp X 123 1 amp X 125 1 amp X 127 1 Z 1 Z 1 Z 1 Z dis rslt 1 Z 1 Z 1 Z 1 Z 1 Z le Z 1 Z 1 Z dis rslt Ly Z 1 Z 1 Z 1 Z T Z 1 Z l Z 1 Z 1 Z 1 Z 1 Z 1 Z 1 Z 1 Z 1 Z 1 Z dis rslt 1 Z 1 Z T Z 1 Z DSP56652 User s Manual Go to www freescale com MM QM Ko ge MMM Ko ge MMMM NM MM HM NM SM eo Motorola Freescale Semiconductor Inc Boundary Scan Description Language 129 BC 1 control 1 amp 130 BC 6 TOUT 4 bidir X 129 1 2Z 131 BC 1 control 1 amp 132 BC 6 TOUT 5 bidir X 131 1 Z 133 BC 1 control 1 amp 134 BC 6 TOUT 6 bidir X 133 1 2Z 135 BC 1 control 1 amp 136 BC 6 TOUT 7 bidir X 135 1 Z 137 BC 1 control 1 amp 138 BC 6 SPICS 4 bidir X 137 1 Uns 139 BC 1 control
78. and BBPCRC Pins that are not used for SAP or BBP operation can be configured as GPIO Pin functions are further described in the following sections Receive and transmit clocks Section 14 2 on page 14 3 e Data transmission and reception Section 14 4 on page 14 9 Serial flags Section 14 3 4 on page 14 8 14 2 Transmit and Receive Clocks Several options are provided to configure the SAP and BBP transmit and receive bit clocks including clock sources internal or external frequency polarity and BRM SAP only 14 2 1 Clock Sources The transmit and receive clock source s can be either external or internal For an external clock source the pins functioning as clocks are configured as inputs For an internal clock source clock pins are configured as outputs The BBP internal clock is derived from Motorola Serial Audio and Baseband Ports 14 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transmit and Receive Clocks DSP CLK the SAP internal clock is derived from either DSP_CLK or the Bit Rate Multiplier clock BRM_CLK as determined by the BRM bit in the SAP Control Register C SAPCRC Clock sources and pins are governed by SAPCRC BBPCRC control bits SYN which selects synchronous or asynchronous mode SCKD and SCDO as shown in Table 14 2 Table 14 2 SAP BBP Clock Sources Receive Receive Transmit Clock Transmit SYN SCKD eee Clock Source Clock Out S
79. and default as general purpose inputs GPI after reset Table 2 9 Interrupt Signals Signal Name Type Reset State Signal Description INTO INTS Input or Input Interrupts 0 5 These signals can be programmed as interrupt inputs Output or GPIO signals As interrupt inputs they can be programmed to be level sensitive positive edge triggered or negative edge triggered Normal MUX_CTL driven low INT6 STDA DSR Input or Output Output Output Input Interrupt 6 When selected this signal can be programmed as an interrupt input or a GPIO signal As an interrupt input it can be programmed to be level sensitive positive edge triggered or negative edge triggered Audio Codec Serial Transmit Data alternate When programmed as STDA this signal transmits data from the serial transmit shift register in the serial audio codec port Note When this signal functions as STDA the primary STDA signal is disabled See Table 2 15 on page 2 16 Data Set Ready When programmed as GPIO output this signal can be used as the DSR output for the serial data port See Table 2 12 Alternate MU X CTL driven high TRST Input Input Test Reset alternate When selected this signal acts as the TRST input for the JTAG test access port TAP controller The signal is a Schmitt trigger input that asynchronously initializes the JTAG test controller when asserted
80. bits enable low power control through software UART functions in the various hardware controlled low power modes is shown in Table 11 2 Table 11 2 UART Low Power Mode Operation DOZE Mode Normal WAIT STOP Mode Mode Mode System Clock ON ON OFF UART Serial I F ON ON OFF Internal Bus ON ON OFF If DOZE mode is entered with the DOZE bit asserted while the UART serial interface is receiving or transmitting data the UART completes the receive or transmit of the current character then signals to the far end transmitter or receiver to stop sending or receiving Control status and data registers do not change when entering or exiting low power modes 11 3 6 Debug Mode In Debug mode URX reads do not advance the internal RX FIFO pointer so repeated URX reads do not cause the URX to change once it contains a valid character Motorola UART 11 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers 11 4 UART Registers Table 11 3 is a summary of the UART control and GPIO registers including the acronym bit names and address least significant halfword of each register The most significant halfword of all register addresses is 0020 Table 11 3 UART Register Summary
81. by clearing the SCRS bit in the Smart Card Activation Control Register SCACR 2 The smart card is powered up The SCPE bit in the SCACR can be set to turn on an external power supply for the card 3 The SIMDATA pin is put in the reception mode tri stated by setting the SCDPE bit in the SCACR 4 The SCP drives a stable glitch free clock SIM_CLK on the SIMCLK pin by setting the SCCLK bit in the SCACR 5 SIMRESET is deasserted by clearing the SCSR bit The power down sequence specified in ISO 7816 is implemented by the DSP36632 as follows 1 SIMRESET is asserted by setting the SCRS bit 2 SIMCLK is turned off pulled low by clearing the SCCLK bit 3 SIMDATA transitions from tristate to low by clearing the SCDPE bit 4 SIM Vcc is powered off The SCPE bit is cleared if it was used to activate an external power supply The power down sequence can be performed in hardware by setting the APDE bit in the SCACR The deactivation sequence is initiated by a rising edge on the SENSE pin so that the sequence can be completed before the card has moved far enough to lose connections with the contacts The SCACR control bits in the above power down sequence are adjusted automatically 12 2 2 Clock Generation SCP clock operation is illustrated in Figure 12 3 on page 12 5 The SCP generates its primary data clock SIM_CLK by dividing CKIH by four or five depending on the state of the CKSEL bit in the Smart Card Port Control Re
82. cmp mem_write a jeq lt memory write cmp mem read a jeq memory read cmp start_app a jeq lt start application cmp mem check a jeq lt memory check if it didn t match any of these it s invalid long message move gt inval_long msg x1 invalid_message return a invalid message indication _waitl jclr DTEO x DSR waitl don t clobber a previous message _wait2 jclr DTE1 x DSR wait2 don t clobber a previous message movep x0 x DTR1 put invalid data in DIR1 movep x1 x DTRO invalid opcode indication in DTRO jmp lt START BOOT MODE A and return to start CELTAS TTD E E E EEEE EEEE E E E E ETT memory write jsr download from mcore jmp lt START BOOT MODE A download from mcore This subroutine is used to perform A 20 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program memory downloads from the M CORE to the DSP Inputs r0 points to MDI memory 1 location past memory write request Registers Used e Ne Ne e Ne e Ne e 9 9 9 9 9 e e 9 e R M N A B X Y 0 c c c c c lc cc 2 C a ee We a RR 5 c changed 6 4 amp amp 7 A oL xdef download from mcore download from mcore retrieve number of words to process move x r0 n0 n0 Awords retrieve memory space MDI address move x r0 x0 move x0 a and ZS 03FF a keep lower 10 bits add M
83. data data data data data data data data data data data data data Motorola Programmer s Data Sheets E 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer DRIEO Description 0 Interrupt disabled D C R 1 DSP Receive Interrupt O enabled DSP Side Control Register Address X FF8A Reset 0000 Read Write DRIE1 Description 0 Interrupt disabled 1 DSP Receive Interrupt 1 enabled DTIE1 Description 0 Interrupt disabled 1 DSP Transmit Interrupt 1 enabled MCIE Description 0 Interrupt disabled 1 MCU Command Interrupt enabled DTIEO Description 0 Interrupt disabled 1 DSP Transmit Interrupt O enabled DSP to MCU Flags 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTIEO DTIE1 DRIEO DRIE1 MCIE DMF2 DMF1 DMFO 0 0 0 0 0 0 0 0 0 Reserved E 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
84. define REDCAP CKCTL CKOS 0x0020 define REDCAP CKCTL CKOE 0x0040 define REDCAP CKCTL CKOHE 0x0080 define REDCAP CKCTL DCS 0x0100 kkkkkkkkkkkkkkkkkkkkk REDCAP Reset Source Register example usage unsigned short reset source unsigned short REDCAP MCU RSR kkkkkkkkkkkkkkkkkkkkk define REDCAP RSR EXR 0x0001 define REDCAP RSR WDR 0x0002 kkkkkkkkkkkkkkkkkkkkk REDCAP Fmulation Port Control example usage struct redcap emulport em port struct redcap emulport REDCAP MCU EMPORT KKK KKK KKK RARA RK RAR Hifdef ASSEM define EMU DIR 0 define EMU DATA 2 else struct redcap emulport unsigned short emddr em port data direction register volatile unsigned short emdr em port data register y endif kkkkkkkkkkkkkkkkkkkkk REDCAP General Port Control example usage Motorola Equates and Header Files B 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Include File unsigned short gpcr unsigned short REDCAP MCU GPCR kkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkk REDCAP External Interface Module example usage struct redcap eim eim struct redcap eim REDCAP MCU EIM kkkkkkkkkkkkkkkkkkkkk ifdef _ASSEM define EIM CSOCR 0x0 define EIM CSICR 0x4 define EIM CS2CR 0x8 define EIM CS3CR Oxc define EIM CS4CR 0x10 define EIM CS5CR 0x14 define EM CR 0x18 else struct redcap eim unsigned
85. waiting for and executing MCU messages until the MCU requests the DSP to exit the boot mode and start the user s application A 2 1 Short and Long Messages The normal boot mode uses both the MDI messaging unit registers and the MDI shared memory for message transfers Shorter messages are conveyed in one or both messaging unit registers For longer messages such as downloading a program to the DSP MDI RO is used to point to the rest of the message in the MDI shared memory The format for short messages is shown in Figure A 1 on page A 3 The most significant bit of MDI RO is used to indicate whether the message is a short message S 1 or a long message S 0 The eight least significant bits of MDI_RO hold the message opcode Bits 1 For simplicity the messaging unit registers MTRO MTR1 MRRO and MRR1 for the MCU transmit and receive registers respectively DTRO DTR1 DRRO and DRRI for the DSP transmit and receive registers respectively are referred to as MDI_RO and MDI RI A 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot 8 13 can contain message information if needed If the short message uses the MDI_R1 register as well the DW bit bit 14 in MDI_RO should be set MDI Messaging Unit Registers 15 14 13 8 7 0 MDI R1 information if used set DWz1 Figure A 1 Short Message Format The format for lon
86. 0 IRQB DSP IRQ 4E 0 2 Reserved 14 0 IRQC MDI 50 0 2 BBP Receive Data 16 0 IRQD Protocol Timer 52 0 2 BBP Receive Data With Overrun Error 18 0 Reserved 54 0 2 BBP Receive Last Slot 1A 0 Reserved 56 0 2 BBP Receive Frame Counter 1C 0 Reserved 58 0 2 BBP Transmit Data 1E 0 Reserved 5A 0 2 BBP Transmit Data with Underrun Error 20 0 Protocol Timer CVRO 5C 0 2 BBP Transmit Last Slot 22 0 Protocol Timer CVR1 5E 0 2 BBP Transmit Frame Counter Motorola Interrupts 7 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Interrupt Controller Table 7 6 DSP Interrupt Sources Continued Pour IPL Interrupt Source Rl IPL Interrupt Source 24 0 Protocol Timer CVR2 60 0 2 3 MDI MCU default command MCU NMI 26 0 Protocol Timer CVR3 62 0 2 MDI Receive 0 28 0 Protocol Timer CVR4 64 0 2 MDI Receive 1 2A 0 Protocol Timer CVR5 66 0 2 MDI Transmit O 2C 0 Protocol Timer CVR6 68 0 2 MDI Transmit 1 2E 0 Protocol Timer CVR7 6A F 0 2 Reserved 30 0 Protocol Timer CVR8 32 0 Protocol Timer CVR9 34 0 Protocol Timer CVR10 36 0 Protocol Timer CVR11 38 0 Protocol Timer CVR12 3A 0 Protocol Timer CVR13 3C 0 Protocol Timer CVR14 3E 0 Protocol Timer CVR15 IRQA should be disabled 2 Any interrupt starting address including a reserved address can be used for MCU NMI IPL
87. 0 0 The SAPSR and BBPSR are 8 bit read only registers Table 14 10 SAP BBP Status Register Description Name Description Settings RDF Receive Data Register Full Set when the 0 No new data received default Bit 7 contents of the receive shift register are 1 New data in Receive Register transferred to the Receive Register Cleared by reading the Receive Register TDE Transmit Data Register Empty Set when the O Last transmit word has not yet been Bit 6 contents of the Transmit Register are transferred copied to transmit shift register to the transmit shift register Cleared by a write to 1 Last transmit word has been copied to the Receive Register or the Time Slot Register transmit shift register default ROE Receiver Overrun Error Set when the last bit O No receive error default Bit 5 of a word is shifted into the receive shift register 1 Receiver overrun error has occurred and RDF is set meaning that the previous received word has not been read Cleared by reading the Status Register then the Receive Register TUE Transmitter Underrun Error Set when the O No transmit error default Bit 4 transmit shift register is empty and a time slot 1 Transmitter underrun error has occurred occurs meaning that the Transmit Register has not been written since the last transmission Cleared by reading the Status Register then writing the Transmit Register or the Tim
88. 0 0 0 0 0 0 0 0 0 0 PIT Modulus Register Address 0020 7002 Reset FFFF Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data PIT Counter Address 0020 7004 Reset uuuu Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data E 50 For More Information On This Product DSP56652 User s Manual Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer WDBG Description WC R 0 Watchdog Timer not affected by Debug mode Watchdog Control Register Address 0020 8000 1 Watchdog Timer disabled in Debug Reset 0000 mode Read Write WDE Description 7 at WDZE Description 0 Watchdog Timer is disabled 0 Watchdog Timer not affected by 1 Watchdog Timer is enabled DOZE mode 1 Watchdog Timer disabled in DOZE mode Watchdog Time Out 15 14 13 12 11 10 8 7 6 4 2 1 0 WT5 WT4 WT3 WT2 WT WTO WDE WDBG WDZE 0 0 0 0 0 0 0 0 Watchdog Service Register Address 0020 8002 Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WS15 WS14 WS13 WS12 WS11 WS10 WS9
89. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9 1 ITCSR Description Type Name ia Description Settings DBG R W Debug Controls PIT function in Debug mode 0 PIT runs normally default Bit 5 1 PIT is frozen OVW R W Counter Overwrite Enable Determines if a 0 PITMR write does not affect Bit 4 write to PITMR is simultaneously passed through PITCNT default to PITCNT 1 PITMR write immediately overwrites PITCNT ITIE R W PIT Interrupt Enable Enables an interrupt O Interrupt disabled default Bit 3 when ITIF is set 1 Interrupt enabled Note Either the EPIT bit in the NIER or the EFPIT bit in the FIER must also be set in order to generate this interrupt see page 7 7 ITIF R 1C PIT Interrupt Flag Set when the counter value O Counter has not reached zero Bit 2 reaches zero cleared by writing it with 1 or writing default to the PITMR 1 Counter has reached zero RLD R W Counter Reload Determines the value loaded O FFFF default Bit 1 into the counter when it rolls over 1 Value in PITMR 1 R W Read write R 1C Read or write with 1 to clear write with O ingored Motorola Timers 9 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Watchdog Timer PITMR PIT Modulus Register 0020_7002 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O PIT Modulus Value RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 This re
90. 000 yields a divisor of 1 and FFF yields a divisor of 4096 USR UART Status Register 0020_ 4086 Bit15 14 13 12 4 10 9 8 7 6 5 4 3 2 1 Bito TXE RTSS TRDY RRDY RTSD RESET 1 0 1 0 0 0 0 0 0 0 0 0 0 4 0 0 All bits are read only and writes have no effect with the exception of RTSD which is cleared by writing it with one Table 11 9 USR Description Name Description Settings TXE Transmitter Empty Set when all data in UTX 0 UTX or transmit buffer contains unsent data Bit 15 FIFO has been sent Cleared by a write to UTX default 1 2 UTX and transmit buffer empty RTSS RTS Pin Status Indicates the current status of the RTS pin When the USR is read a snapshot of Bit 14 the RTS pin is taken immediately before this bit is presented to the data bus TRDY Transmitter Ready Set when the number of O Number of unsent characters is above the Bit 13 unsent characters in UTX FIFO falls below the threshold default threshold determined by the TxFL bits in UCR1 1 Number of unsent characters is below the Cleared when the MCU writes enough data to fill threshold the UTX above the threshold RRDY Receiver Ready Set when the number of O Number of unread characters is below the Bit 9 characters in URX FIFO exceeds the threshold threshold default determined by the RxFL bits in UCR1 Cleared 1 2 Number of unread characters is above the when th
91. 0xa 0x9 0x8 0x7 0x6 0x4 0x1 0x0 Equates and Header Files MCU Equates B 21 Freescale Semiconductor Inc MCU Include File B 2 MCU Include File DSP56651 DSP56652 C include file for M CORE Revision History 1 0 may 28 1998 ifndef _REDCAP H_ define REDCAPH kkkkkkkkkkkkkkkkkkkkk REDCAP MCU MEMORY MAP kkkkkkkkkkkkkkkkkkkkk On chip ROM 16 KB starting at location 0 define REDCAP MCU ROM BASE 0x00000000 define REDCAP 1 MCU ROM SIZE 0x00004000 On chip RAM 2KB starting at specified location define REDCAP MCU RAM BASE 0x00100000 define REDCAP 1 MCU RAM SIZE x00000800 On chip peripherals base addresses define REDCAP MCU PIC 0x00200000 Interrupt Controller define REDCAP MCU EIM 0x00201000 External Interface Module define REDCAP MCU MDI 0x00202000 MCU DSP Interface define REDCAP MCU PROT 0x00203000 Protocol Timer define REDCAP MCU UART 0x00204000 UART define REDCAP MCU OSPI 0x00205000 Queued SPI define REDCAP MCU PWM 0x00206000 PWM Input Capture Timers define REDCAP MCU PIT 0x00207000 Periodic Interrupt Timer define REDCAP MCU WDT 0x00208000 Watchdog Timer define REDCAP MCU INTPINS 0x00209000 Interrupt Pins Control define REDCAP MCU KPP 0x0020A000 Keypad Port define REDCAP MCU SCP 0x0020B000 Smart Card Port define REDCAP MCU CKCTL 0x0020C000 Clock Control Register
92. 1 SIMCLK driven by the SIM_CLK signal Cleared by software or automatically after the card is removed if the APDE bit is set SCRS Smart Card Reset This bit drives the 0 SIMRESET pulled low default Bit 3 SIMRESET pin It is controlled automatically after 1 SIMRESET driven high the card is removed if the APDE bit is set SCDPE Smart Card Data Pin Enable Setting this bit 0 SIMDATA pulled low default Bit 2 allows the SIMDATA pin to function as a receiver 1 SIMDATA functions as SCP transmit or or transmitter It is cleared automatically after the receive pin card is removed if the APDE bit is set SCPE Smart Card Power Enable This bit drives the 0 PWR_EN pulled low default Bit 1 PWR EN pin which can switch on an external 1 PWR EN driven high power supply to power the smart card It is cleared automatically after the card is removed if the APDE bit is set APDE Auto Power Down Enable Setting this bit 0 Software performs power down sequence Bit 0 allows hardware to control the SCP pins to default perform the power down sequence automatically 1 Hardware automatically performs power after the smart card is removed down sequence 12 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Registers SCPIER SCP Interrupt Enable Register 0020_B004 Bit15 14 13 12 11 1
93. 1 4 1 2 2 SA ann E E E E T AE ET soe tos 1 6 1 2 3 MECU DSP Interface uu uM E ttt E E E tad E T E del 1 9 Chapter 2 Signal Connection Description ral POWEL UR ET ETIN TEN wee E ONE Rd 2 3 22 A A edis aud iori UN 2 4 2 3 Clock and Phase Locked Loop E AA A OSS 2 5 24 lt External Interface Module by eck ca ST REN oe ONG eee CES CREER ewe SORES 2 6 2 59 Reset Mode and Multiplexer Control iris Se whoa ios 2 7 26 Internal Interr ptsa sacer ea me AS AA AS 2 8 2 Protocol LIME eaae EA A AAA 2 9 28 Keypad Poit AAA T at both s a r a a a Li a 2 10 2 9 DAR E A E A i E EA SA 2 13 210 OS Plains tee cena SN EEE ETENIM AE E ques 2 15 2d O O ace 4 IE SR Lg sui Meter etu oe tala 2 16 2 12 AO RARAS AS INES ie Mab AMG NANG pac ed WG RA Rane AE 2 16 2al BBP TAE Ani A 2 18 2 14 MCU Emulation Port 5e E ber ER nd S 2 18 ZTS Deb t Port Cont diosa Oen REX a Edd REN A 2 18 2 16 J EAOG DestoXecess POR uses Ceu mos eR ES CER RUE RSEN RN 2 9 Chapter 3 Memory Maps Sel MICU Memory Maps saos aon uite o M rites iet a M apu Ed NS AU S LM 3 1 3 1 1 ROM eeri E ER O 3 1 3 12 Io A REPTCTPT 3 2 Motorola Table of Contents iii For More Information On This Product Go to www freescale com 3 1 3 3 1 4 3 1 5 3 2 3 2 1 3 2 2 3 2 3 3 2 4 4 1 4 1 1 4 1 2 4 1 3 4 2 4 3 4 3 1 4 3 2 4 4 4 4 1 4 4 2 4 4 3 4 5 4 5 1 4 5 2 5 1 5 1 1 5 1 2 5 1 3 5 1 4 5 2 5 2 1 5 2 2 5 2 3 5 2 4 Freescale Semiconductor Inc Memor
94. 10 9 8 7 6 5 4 3 2 1 0 PD 5 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDC 5 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEN PC 5 0 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers 14 9 1 SAP and BBP Control Registers SAPCNT SAP Timer Counter X FFB4 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 SAP Timer Count This read only register holds the value of the SAP timer RESET BBPRMR BBP Receive Counter Modulus Register X FFA4 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 BBP Receive Counter Load Value RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register contains the value that is loaded in the BBP receive frame counter register when the counter is enabled and when the counter rolls over SAPMR SAP Timer Modulus Register X FFB5 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 SAP Timer Load Value RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register contains the value that is loaded in the SAPCNT register when the timer is enabled and when the timer rolls over BBPTMR BBP Transmit Counter Modulus Register X FFA5 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 BBP Transmit Counter Load Value RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register contains the value that is loaded in the BBP transmit frame counter register when the counter is enabled and when the counter rolls over M
95. 104 BC 6 105 BC 6 106 BC 6 107 BC 6 108 BC 6 109 BC 6 110 BC 6 111 BC 6 112 BC 6 113 BC 6 114 BC 1 115 BC 6 BC 6 ADDR 17 117 BC 6 118 BC 6 119 BC 1 num cell 120 BC 1 121 BC 1 122 BC 6 123 BC 1 124 BC 6 125 BC 1 126 BC 6 127 BC 1 128 BC 6 Freescale Semiconductor Inc Boundary Scan Description Language DATA 5 DATA 4 DATA 3 DATA 2 port DATA 1 DATA 0 CS5 CS B 4 CS B 3 CS B 2 CS B 1 CS B 0 RW B OE B CKO CKOH CKIL EB B 0 EB B 1 ADDR 0 ADDR 1 ADDR 2 port ADDR 3 T ADDR 4 ADDR 5 ADDR 6 ADDR 7 ADDR 8 ADDR 9 ADDR 10 ADDR 11 ADDR 12 ADDR 13 ADDR 14 ADDR 15 L ADDR 16 r bidir ADDR 18 ADDR 19 ADDR20 port ADDR21 TOUT 0 TOUT 1 TOUT 2 TOUT 3 For More Information On This Product L L bidir bidir bidir bidir func bidir bidir output2 output2 output2 output2 control control output2 output2 bidir output2 output2 output2 input bidir bidir bidir bidir bidir func bidir control bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir control bidir X 114 bidir bidir output2 func output2 control bidir control bidir control bidir control bidir X 73 X 73
96. 2 Enabling DSP Interrupt Sources Two steps are required to enable DSP interrupt sources 1 Assign the desired priority level to each peripheral and write to the Peripheral Interrupt Priority Register IPRP Each of the four peripherals that can interrupt the DSP MDI PT SAP and BBP as well as the MDI Command interrupt can be assigned a priority level from 0 lowest to 2 Motorola Interrupts 7 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Interrupt Controller highest This assignment is done by writing to the IPRP The choice of priority level for each peripheral depends on several factors driven by the end application including Rate of service requests Latency requirements e Access to the alternate register bank Length of service routine e Total number of interrupt sources in the system This step is normally done once during system initialization 2 Program the appropriate peripheral registers to generate the desired interrupt requests 7 2 3 DSP Interrupt Control Registers IPRP Interrupt Priority Register Peripherals X FFFE BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O MDIPL 1 0 PTPL 1 0 SAPPL 1 0 BBPPL 1 0 MDCPL 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7 8 IPRP Description Name Description Setting MDIPL 1 0 MDI Interrupt Priority Level 00 Disabled default Bits 9 8 01 Priority level
97. 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Lower Halfword Interrupt Control Register Lower Halfword Reset 0000 Read Write Accessible Only in Supervisor Mode Source Number EN Description 0 Priority hardware disabled Priority hardware disabled Vector Number 15 14 13 12 11 10 9 8 7 E 6 5 4 3 2 1 0 EN SRC4 SRC3 SRC2 SRC1 SRCO VEC6 VEC5 VECA VEC3 VEC2 VEC1 VECO 0 0 0 NOTE ICR can only be written as a 32 bit Reserved Motorola For More Information On This Product Programmer s Data Sheets Go to www freescale com E 35 Freescale Semiconductor Inc Application Date Programmer SAP IPL PL1 PLO Mode P R P 0 0 Interrupts disabled Interrupt Priority Register Peripheral D i Interrupts enabled IPL 0 Address X FFFE 1 0 Interrupts enabled IPL 1 Reset 0000 1 1 Interrupts enabled IPL 2 Read Write BBP IPL PL1 PLO Mode z 0 0 Interrupts disabled Protocol Timer IPL 0 1 Interrupts enabled IPL 0 PL1 PLO Mode z 1 0 Interrupts enabled IPL 1 0 0 Interrupts disabled 1 1 Interrupts enabled IPL 2 0 1 Interrupts enabled IPL 0 1 0 Interrupts enabled IPL 1 1 1 I
98. 4 PITMR PIT Modulus Register Timers 0020_7002 9 4 PITCSR PIT Control and Status Register Timers 0020_7000 9 3 KDDR Keypad Data Direction Register KP 0020_A004 13 6 KPCR Keypad Control Register KP 0020_A000 13 5 KPDR Keypad Data Register KP 0020_A006 13 6 KPSR Keypad Status Register KP 0020_A002 13 5 MCR MCU Side Control Register MDI 0020_2FF4 5 19 MCVR MCU Side Command Vector Register MDI 0020_2FF2 5 18 MRRO MCU Receive Register O MDI 0020_2FFE 5 24 MRR1 MCU Receive Register 1 MDI 0020_2FFC 5 24 MSR MCU Side Status Register MDI 0020_2FF6 5 21 MTBAR Macro Tables Base Address Register PT 0020_3822 10 25 MTPTR Macro Table Pointer PT 0020_381E 10 24 MTRO MCU Transmit Register 0 MDI 0020_2FFA 5 24 MTR1 MCU Transmit Register 1 MDI 0020_2FF8 5 24 NIER Normal Interrupt Enable Register Interrupts 0020_0004 7 7 NIPR Normal Interrupt Pending Register Interrupts 0020_000C 7 9 OMR Operating Mode Register DSP Core 4 13 PCTLO PLL Control Register 0 DSP Core X FFFD 4 6 PCTL1 PLL Control Register 1 DSP Core X FFFC 4 7 PTPDR PT Port Data Register PT 0020_381A 10 26 PTDDR PT Data Direction Register PT 0020_3818 10 26 PTPCR PT Port Control Register PT 0020_3816 10 26 PTCR PT Control Register PT 0020_3800 10 17 PTIER PT Interrupt Enable Register PT 0020_3802 10 18 PWCNT PWM Counter Register Timers 0020_6018 9 17 PWMR PWM Modulus Register Timers 0020_6016 9 17 Motorola Programmer s Reference D 23 For More Information On This Product Go
99. 5 4 3 2 1 0 data data data data data data data data data data data data data data data data TCNT Timer Count Register Address 0020_6014 Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data PWMR PWM Modulus Register Address 0020_6016 Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data PWCNT PWM Count Register Address 0020_6018 Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data Motorola Programmer s Data Sheets E 57 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer Protocol Ti mer TDZD Description 0 Protocol Timer ignores DOZE mode 1 Protocol Timer stops during DOZE PTC
100. 6 Programmable Output Generalidad RSEN 6 7 6 3 7 Einulaton POT EAS AAA DES EAS 6 8 04 ETRE ASS AS A E HERS eee A A IRE 6 9 Chapter 7 Interrupts d MCU Interrupt Controller 2 bss ade pb ad eb EN Anas 7 1 7 1 1 Functional OVAS WA AA EA 7 1 7 1 2 Exception Priority iw 5 4 A ARA 7 2 7 1 3 Enabling MCU Interrupt Sources 20 0 cece eee eens 7 3 7 1 4 A 4 Cursos Ma REESE NEN E ei SERE bei 7 4 7 1 5 MCU Interrupt Registers c 045cs2s05s RR RE RR 7 6 4 2 tDSPIniertupt Controller x 222A ade Rete ex ae ee NAE 7 10 7 2 1 DSP Inte nop SOUICES obere area dee aout Ado ie e ar eds 7 10 12 2 Enabling DSP Interrupt Sources 20 0 cee eee eee eee 7 13 71 2 3 DSP Interrupt Control Registers 4 vus ira is a Sal wre 7 14 Ted Edge PO E O a 7 15 Motorola Table of Contents V For More Information On This Product Go to www freescale com 8 1 8 1 1 8 1 2 8 1 3 8 1 4 8 1 5 8 1 6 8 1 7 8 1 8 8 2 8 2 1 8 2 2 8 2 3 8 2 4 8 3 8 3 1 8 3 2 8 3 3 8 3 4 8 3 5 8 3 6 8 3 7 8 4 8 4 1 8 4 2 8 4 3 8 4 4 9 1 9 1 1 9 1 2 92 9 2 1 9 2 2 9 3 vi Freescale Semiconductor Inc Chapter 8 Queued Serial Peripheral Interface A E AS MEW a R A 8 2 Programmable Baud Rates ci annan 8 2 Programmable Queue Lengths and Continuous Transfers 8 2 Programmable Peripheral Chip Selects 1 2 eerte eg 8 2 Programmable Queue Pointers diia exe RERO C ES 8 3 Four Transfer Activation TriggerS sees xe
101. 8 7 6 5 4 3 2 1 0 FSP FSR FSL1 FSLO SHFD CKP SCKD SCD2 SCD1 SCDO MOD SYN Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 87 Freescale Semiconductor Inc Application Date Programmer TUE Description B B PS R 1 TX underrun occurred BBP Status Register Address X FFA9 Reset 0000 Read Write TFS Description 1 TX frame sync occurred ROE Description 1 RX overrun occurred RFS Description 1 RX frame sync occurred TDE Description 1 TX data register empty Serial Input Flags RDF Description 1 RX data register has data 9 Reserved E 88 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer BBP BBPRX BBP Receive Data Register Address X FFAA Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 High Byte Low Byte BBPTSR BBP Time Slot Register Address X FFAB Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dummy Register Written During Inactive Time Slots BBPTX BBP Transmit Data Register Address
102. 88 CS1 output data 128 TOUT3 input output data 89 CSO output data 129 TOUT4 control 90 R W input output data 130 TOUT4 input output data 91 OE output data 131 TOUT5 control 92 CKO output data 132 TOUT5 input output data 96 CKOH output data 133 TOUT6 control 94 CKIL input data 134 TOUT6 input output data 95 EBO input output data 135 TOUT7 control 96 EB1 input output data 136 TOUT7 input output data 97 ADDRO input output data 137 SPICS4 control 98 ADDR1 input output data 138 SPICS4 input output data 99 ADDR2 input output data 139 SPICS3 control 100 ADDR3 input output data 140 SPICS3 input output data 101 ADDR 7 0 control 141 SPICS2 control 102 ADDR4 input output data 142 SPICS2 input output data 103 ADDR5 input output data 143 SPICS1 control 104 ADDR6 input output data 144 SPICS1 input output data 105 ADDR7 input output data 145 SPICSO control 106 ADDR8 input output data 146 SPICSO input output data 107 ADDR9 input output data 147 SCK control 108 ADDR10 input output data 148 SCK input output data 109 ADDR11 input output data 149 MISO control 110 ADDR12 input output data 150 MISO input output data 111 ADDR13 input output data 151 MOSI control 112 ADDR14 input output data 152 MOSI input output data 113 ADDR15 input output data 153 DSP_IRQ input data 114 ADDR 19 8 control 154 SCKB control 115 ADDR16 input output data 155 SCKB input output data 116 ADDR17 input output data 156 SCBO control 117 ADDR18 input output data
103. Continued Address Register Name Reset Value 0020_6004 TPWSR Timers and PWM Status Register 0000 0020_6006 TPWIR Timers and PWM Interrupts Enable Register 0000 0020_6008 TOCR1 Timer 1 Output Compare Register 0000 0020 600A TOCR3 Timer 3 Output Compare Register 0000 0020 600C TOCR4 Timer 4 Output Compare Register 0000 0020_600E TICR1 Timer 1 Input Capture Register 0000 0020_6010 TICR2 Timer 2 Input Capture Register 0000 0020_6012 PWOR PWM Output Compare Register 0000 0020_6014 TCNT Timer Counter 0000 0020_6016 PWMR PWM Modulus Register 0000 0020_6018 PWCNT PWM Counter 0000 Periodic Interrupt Timer PIT 0020_7000 PITCSR PIT Control and Status Register 0000 0020_7002 PITMR PIT Modulus Register FFFF 0020_7004 PITCNT PIT Counter uuuu Watchdog Timer 0020_8000 WCR Watchdog Control Register 0000 0020_8002 WSR Watchdog Service Register 0000 Edge Port EP 0020_9000 EPPAR Edge Port Pin Assignment Register 0000 0020_9002 EPDDR Edge Port Data Direction Register 0000 0020_9004 EPDDR Edge Port Data Register 00uu 0020_9006 EPFR Edge Port Flag Register 0000 Keypad Port KP 0020_A000 KPCR Keypad Control Register 0000 0020_A002 KPSR Keypad Status Register 0000 0020_A004 KDDR Keypad Data Direction Register 0000 0020_A006 KPDR Keypad Data Register uuuu Motorola Programmer s Reference For More I
104. Control Register 0020_B000 Bit15 14 13 12 11 10 9 8 6 5 4 3 2 1 Bit 0 CKSEL NKOVR DOZE SIBR SCSR SCPT SCIC NKPE SCTE SCRE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 2 SCPCR Description Name Description Settings CKSEL Clock Select Determines if the CKIH divisor O CKIH divided by 5 default Bit 9 that generates SIM CLK is 4 or 5 1 CKIH divided by 4 NKOVR NACK on Receiver Overrun Enables overrun O NACK not generated Bit 8 checking and reporting 1 NACK is generated on overrun error DOZE DOZE Mode Controls SCP operation in DOZE 0 SCP ignores DOZE mode default Bit 7 mode 1 SCP stops in DOZE mode SIBR SIM Baud Rate Determines the SIM_CLK O Baud rate SIM_CLK 372 default Bit 6 divisor to generate the SIM baud clock 1 Baud rate SIM_CLK 64 SCSR SCP System Reset Setting this bit resets the SCPSR and state machines Other registers are not Bit 5 affected If the SCSR bit is set while a character is being sent or received the transmission is completed before reset occurs SCPT SCP Parity Type Selects odd or even parity In O Even parity default Bit 4 initial character mode hardware adjusts this bit 1 Odd parity automatically SCIC SCP Initial Character Mode Setting this bit O Parity determined by writing SCPT bit Bit 3 implements initial character mode in which parity default is determined by the first character sent by the 1 Parity determined by initial character from c
105. DRR1 equ MDI IO BASE e DSP side receive register 1 DIRO equ MDI IO BASE d DSP side transmit register 0 DIR1 equ MDI IO BASE c DSP side transmit register 1 DSR equ MDI IO BASE Sb DSP side status register DCR equ MDI IO BASE a DSP side control register WMDI DSP side Status Register DSR bits DFO equ 0 DSP side Flag 0 DFl equ 1 DSP side Flag 1 DF2 equ 2 DSP side Flag 2 DEP equ 4 DSP Event Pending MPMO equ 5 MCU Power Mode bit 0 MPM1 equ 6 MCU Power Mode bit 1 DWSC equ 7 DSP Wake from Stop interrupt Clear MCP equ 8 MCU Command Pending DTIC equ 9 DSP Protocol Timer Interrupt clear DGIR1 equ 10 DSP General Interrupt Request 1 bit DGIRO equ 11 DSP General Interrupt Request 0 bit DRFl equ 12 DSP Receive register 1 Full DRFO equ 13 DSP Receive register 0 Full DIEl equ 14 DSP Transmit register 1 Empty DTEO equ 15 DSP Transmit register 0 Empty WMDI DSP side Control Register DCR bits DMFO equ 0 DSP side MCU messaging flag 0 DMF1 equ 1 DSP side MCU messaging flag 1 DMF2 equ 2 DSP side MCU messaging flag 2 MCIE equ 8 MCU Command Interrupt Enable DRIE1 equ 12 DSP Recieve 1 Interrupt Enable DRIEO equ 13 DSP Recieve 0 Interrupt Enable DTIE1 equ 14 DSP Transmit 1 Interrupt Enable DTIEO equ 15 DSP Transmit 0 Interrupt Enable Register Addresses of BBP BBP PCRB EQU SFFAF BBP Port Control Register BBP PRRB EQU SFFAE BBP GPIO Direction Register BBP PDRB EQU SFFAD BBP GPIO Data Register BBP
106. DSP shared Active 0 1 MCU stalls until DSP access completes memory contention Multiple DSP one cycle instructions stall the MCU further Control registers Either 2 2 1 Minimum case DSP clock frequency gt gt MCU clock frequency Maximum case DSP clock frequency MCU clock frequency More cycles required if DSP clock MCU clock 5 2 MDI Messages and Control The MDI provides a means for the MCU and DSP to exchange messages independent of the shared memory array A typical message might be I have just written a message of N words starting at offset X in memory or I have just finished reading the last data block sent For ease and flexibility the protocol for exchanging these messages is not predefined in hardware but can be implemented with a few simple software commands 5 2 1 MDI Messaging System Messages are exchanged between the two processors through special purpose control registers Most of these registers are symmetric and work together to exchange messages in the following ways 1 Each of two 16 bit write only transmit registers is copied in a corresponding read only receive register on the other processor s side These registers can be used to transfer 16 bit messages or frame information about messages written to the shared memory such as number of words initial address and message code type 2 Writing to a transmit register clears a transmitter empty bit in the status register on the tr
107. DSP56652 entity is 0000 amp version 000110 amp manufacturer s use 0001000010 amp sequence number 00000001110 amp manufacturer identity 1 1149 1 requirement attribute REGISTER ACCESS of DSP56652 entity is BYPASS ENABLE MCU ONCE ENABLE DSP ONCE DSP DEBUG REQUEST attribute BOUNDARY LENGTH of DSP56652 entity is 198 attribute BOUNDARY REGISTER of DSP56652 entity is num cell port func safe ccell dis rslt 0 BC 1 control 1 amp 1 BC 6 DSP DE B bidir X 0 1 2Z amp 2 BC 1 control 1 amp 3 BC 6 ROW 7 bidir X 2 1 Z amp A BC 1 control 1 amp 5 BC 6 ROW 6 bidir X 4 1 2Z amp 6 BC 1 control 1 amp 7 BC 6 ROW 5 bidir X 6 1 Z amp 8 BC 1 control 1 amp 9 BC_6 ROW 4 bidir X 8 1 2Z amp 10 BC 1 control 1 amp 11 BC 6 ROW 3 bidir X 10 1 Z 8 12 BC 1 control 1 amp 13 BC 6 ROW 2 bidir X 12 1 Z 8 14 BC 1 control 1 amp 15 BC 6 ROW 1 bidir X 14 1l Z amp 16 BC 1 control 1 amp 17 BC 6 ROW 0 bidir X 16 1 2Z amp 18 BC 1 control 1 amp 19 BC 6 INT 7 bidir X 18 1 Z amp num cell port func safe ccell dis rslt 20 BC 1 control 1 amp 21 BC 6 INT 6 bidir X 20 1 Z 8 C 8 DSP56652 User s Manual Motorola For More Information On This Produc
108. Data RAM ROM 7 1 K x 16 10K x 16 Protocol Timer Y Data Y Data RAM ROM 6K x 16 10K x 16 Serial Audio Codec I F Program X Data RAM RAM Baseband 512 x 24 48K x 24 DSP56652 Codec I F Figure 1 1 DSP56652 Block Diagram DSP core DSP56600 architecture Single cycle arithmetic instructions Fully pipelined 16 x 16 bit parallel multiply accumulator MAC Two 40 bit accumulators including extension bits 40 bit parallel barrel shifter Highly parallel instruction set with unique DSP addressing modes Position independent code support Nested hardware DO loops DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc DSP56652 Key Features Fast auto return interrupts On chip support for software patching and enhancements Real time trace capability via external address bus On chip memory 4K x 32 bit MCU ROM 512 x 32 bit MCU RAM 48K x 24 bit DSP program ROM 512 x 24 bit DSP program RAM 10K x 16 bit DSP X data ROM 10K x 16 bit DSP Y data ROM 7 1 K x 16 bit X data RAM 6K x 16 bit Y data RAM On chip peripherals Fully programmable phase locked loop PLL for DSP clock generation External interface module EIM for glueless system integration External 22 bit address and 16 bit data MCU buses 32 source MCU interrupt controller Intelligent MCU
109. EFOSP 24 asPi EMDI EFMDI 23 MDI ESCP EFSCP 22 SCP RxD TxD or Error ETPW EFTPW 17 Timer PWM EPIT EFPIT 16 PIT EKPD EFKPD 14 Keypad Interface EURTS EFURTS 13 UARTRTS EINT7 0 EFINT7 0 12 5 External Interrupt 7 0 ES2 0 EFS2 01 2 0 Software Interrupts 1 Setting any of the software interrupt enable bits ES2 0 NES2 0 immediately generates an interrupt to the MCU 7 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Interrupt Controller NIPR Normal Interrupt Pending Register 0020_000C BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT16 NURX NSMPC NUTX NPT2 NPT1 NPTO NPTM NQSPI NMDI NSCP NTPW NPIT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO NKPD NURTS NINT7 NINT6 NINT5 NINT4 NINT3 NINT2 NINT1 NINTO NS2 NS1 NSO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The NIPR is used to monitor impending normal interrupts Writes to this register are ignored All unused bits always read as 0 except for bits 2 0 which always read as 1 FIPR Fast Interrupt Pending Register 0020_0010 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16 FURX FSMPC FUTX FPT2 FPT1 FPTO FPTM FQSPI FMDI a FPIT
110. EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDDO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7 11 EPDDR Description Name Description Settings EPDD 7 0 Each of these bits controls the data direction of O Input default Bits 7 0 the corresponding Edge I O pin Pin direction is 1 Output independent of its programmed level edge mode Motorola Interrupts 7 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Edge Port EPDR Edge Port Data Register 0020_9004 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPDO RESET 0 0 0 0 0 0 0 0 Table 7 12 EPDR Description Name Description EPD 7 0 Each of these bits contains data for the corresponding Edge I O pin Writes to EPDR are stored in Bits 7 0 an internal latch and driven on any port pin configured as an output Reads of this register return the value sensed on input pins and the latched data driven on outputs EPFR Edge Port Flag Register 0020_9006 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPFO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7 13 EPFR Description Name Description EPF7 0 Edge Port Flag 7 0 Each bit in this register is set when the associated pin detec
111. EQU 15 e Ne Ne Ne BBP Control Register C Bit Flags BBP_SYN EQU 0 Sync Async Control BBP MOD EQU 1 BBP Mode Select BBP SCD EQU 1C Serial Control Direction Mask BBP SCDO EQU 2 Serial Control 0 Direction BBP_SCD1 EQU 3 Serial Control 1 Direction BBP SCD2 EQU 4 Serial Control 2 Direction BBP_SCKD EQU 5 Clock Source Direction BBP CKP EQU 6 Clock Polarity BBP SHFD EQU 7 Shift Direction BBP_FSL EQU 3000 Frame Sync Length Mask FSLO FSL1 BBP_FSLO EQU 12 Frame Sync Length 0 BBP FSL1 EQU 13 Frame Sync Length 1 BBP_FSR EQU 14 Frame Sync Relative Timing BBP_FSP EQU 15 Frame Sync Polarity e Ne Ne Ne H 7 BBP Status Register Bit Flags Serial Input Flag Mask Serial Input Flag 0 Serial Input Flag 1 Transmit Frame Sync Flag Receive Frame Sync Flag Transmitter Underrun Error FLag BBP IF EQU 3 BBP IFO EQU 0 BBP IF1 EQU 1 BBP TFS EQU 2 BBP RFS EQU 3 BBP TUE EQU 4 e Ne Ne 99 e e B 36 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates BBP_ROE EQU 5 Receiver Overrun Error Flag BBP_TDE EQU 6 Transmit Data Register Empty BBP_RDF EQU 7 Receive Data Register Full Register Addresses Of SAP SAP PCRA EQU SFFBF SAP Port Control Register SAP PRRA EQU SFFBE SAP GPIO Direction Register SAP PDRA EQU SFFBD SAP GPIO Data Register SAP TXA EQU SFFBC SAP Transmit Data Register SAP TSR
112. Inc 2 8 Keypad Port With the exception of alternate signal functions DSP_DE and TCK the signals described in Table 2 11 are GPIO when not programmed otherwise and default as GPI after reset Table 2 11 Keypad Port Signals Signal Name Type Reset State Signal Description COLO COL5 Inputor Input Column Strobe 0 5 As keypad column strobes these signals can be Output programmed as regular or open drain outputs COL6 Input or Input Column Strobe 6 As a keypad column strobe this signal can be Output programmed as regular or open drain output OC1 Output MCU Timer Output Compare 1 This signal is the MCU timer output compare 1 signal Programming of this signal function is performed using the general port control register and the keypad control register COL7 Input or Input Column Strobe 7 As a keypad column strobe this signal can be Output programmed as regular or open drain output PWM Output PWM Output Note Programming of this signal function is performed using the general port control register and the keypad control register ROWO Input or Input Row Sense 0 4 These signals function as keypad row senses ROW4 Output ROW5 Input or Input Row Sense 5 This signal functions as a keypad row sense Output IC2 Input MCU Timer Input Capture 2 This signal is the input capture for the MCU input capture 2 timer Note Programming of this signal function is performed using the general por
113. LSRC RX 0011 1110 0000 rrrr Copy RXO into C before shifting LSRI LSRI RX IMM5 0011 111i iiii rrrr Unaffected MFCR MFCR RX CRY 0001 000c cccc rrrr Unaffected MOV MOV RX RY 0001 0010 ssss rrrr Unaffected MOVF MOVF RX RY 0000 1010 ssss rrrr Unaffected MOVI MOVI RX IMM7 0110 Oiii iiii rrrr Unaffected MOVT MOVT RX RY 0000 0010 ssss rrrr Unaffected Motorola Programmer s Reference D 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Instruction Reference Tables Table D 1 MCU Instruction Set Summary Continued Mnemonic Instruction Syntax Opcode C Bit MTCR MTCR RX CRY 0001 100c cccc rrrr Unaffected unless CRO PSR specified MULT MULT RX RY 0000 0011 ssss rrrr Unaffected MVC MVC RX 0000 0000 0001 rrrr Unaffected MVCV MVCV RX 0000 0000 0011 rrrr Unaffected NOT NOT RX 0000 0001 1111 rrrr Unaffected OR OR RX RY 0001 1110 ssss rrrr Unaffected RFI RFI 0000 0000 0000 0011 ROTLI ROTLI RX IMM5 0011 100i iiii rrrr Unaffected RSUB RSUB RX RY 0001 0100 ssss rrrr Unaffected RSUBI RSUBI RX IMM5 0010 100i iiii rrrr Unaffected RTE RTE 0000 0000 0000 0010 n a SEXTB SEXTB RX 0000 0001 0101 rrrr Unaffected SEXTH SEXTH RX 0000 0001 0111 rrrr Unaffected ST BHW ST B H W RZ RX DISP 1001 zzzz iiii rrrr Unaffected ST STB STH STW RZ RX DISP STM STM RF R15 RO 0000 0000 0111 rrrr Unaffecte
114. M WEN Description 0 The EBO 1 signals are negated CSCRO a 1 The EBO 1 signals are negated half Chip Select Register 0 a clock cycle earlier on write Address 0020_ 1000 accesses Reset F861 Read Write i EBC Description 0 Read and write accesses both OEA Description assert EBO 1 0 The OE signal is negated normally 1 Only write accesses can assert 1 The OE signal is asserted half a EBO clock cycle later on read accesses DSZ1 DSZO Description CSA Description 0 0 8 bit port on D 8 15 pins 0 The CS signal is asserted normally 0 1 8 bit port on D 0 7 pins 1 The CS signal is asserted one 1 0 16 bit port on D 0 15 pins cycle later on read and write accesses and an extra cycle 1 1 Reserved inserted between back to back cycles SP Description EDC Description 0 User mode accesses allowed 0 No delay occurs after a read cycle 1 User mode accesses prohibited 1 One clock cycle is inserted after a read cycle WP Description 0 Writes are allowed WWS Description 1 Writes are prohibited 0 Read and write WAIT states same 1 Write WAIT states Read WAIT CSEN Description states 1 PETS 0 Chip Select function is disabled and CSO pin is an output WSC 0 3 Description 1 Chip Select function is enabled Binary value of number of external memory wait states 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSC3 WSC2 WSC1 WSCO WWS EDC CSA OEA WEN EBC DSZ1 DSZO SP WP CSEN Reserved Motorola Programmer s Data
115. MAXM MAXM A B MERGE MERGE SSS D MOVE No Parallel Data Move DALU MOVE xx gt DDDDD MOVE ddddd DDDDD U move po pol ow O MOVE S lt ea gt DDDDD 1 U A I MOVE S lt aa gt DDDDD 1 MOVE S lt Rn aa gt DDDD 2 MOVE S Rn aaaa gt DDDDDD 3 MOVE d X Y lt ea gt YY 14U A l MOVE X lt ea gt XX 8 d gt Y 1 U A l MOVE A gt X ea X0 A 1 U MOVE B gt X ea X0 B 1 U MOVE YO A A Y ea 1 U MOVE YO B B Y ea 1 U MOVE L lt ea gt LLL 1 U A MOVE L lt aa gt LLL 1 MOVE X ea XX 8 Y lt ea gt Y Y 1 MOVEC MOVEC xx gt 1DDDDD 1 MOVEC S ea 1DDDDD 1 U A I MOVEC S lt aa gt 1DDDDD 1 MOVEC MOVEC DDDDDD 1ddddd 1 7 NPN 3 Y NPN 3 Y VOL Nl Ny Y M20 2 sw y NPN 3 Y D 10 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc DSP Instruction Reference Tables Table D 4 DSP Instruction Set Summary Continued CCR Mnemonic Syntax P T S L EJU N Z V C MOVEM MOVEM P lt ea gt DDDDDD
116. MCU DSP Interface MDI X FF8A DCR DSP Side Control Register 0 X FF8B DSR DSP Side Status Register C000 X FF8C DTR1 DSP Transmit Register 1 0 X FF8D DTRO DSP Transmit Register 0 0 X FF8E DRR1 DSP Receive Register1 0 X FF8F DRRO DSP Receive Register O 0 Baseband Port BBP X FFA4 BBPRMR BBP Receive Counter Modulus Register 0 X FFA5 BBPTMR BBP Transmit Counter Modulus Register 0 X FFA6 BBPCRA BBP Control Register A 0 X FFA7 BBPCRB BBP Control Register B 0 X FFA8 BBPCRC BBP Control Register C 0 X FFAQ BBPSR BBP Status Register 40 X FFAA BBPRX BBP Receive Data Register FFFF X FFAB BBPTSR BBP Time Slot Register 0 X FFAC BBPTX BBP Transmit Data Register 0 X FFAD BBPPDR BBP Port Data Register 0 X FFAE BBPDDR BBP GPIO Direction Register 0 X FFAF BBPPCR BBP Port Control Register 0 Serial Audio Port SAP X FFB4 SAPCNT SAP Timer Counter 0 X FFB5 SAPMR SAP Timer Modulus Register 0 X FFB6 SAPCRC SAP Control Register A 0 X FFB7 SAPCRB SAP Control Register B 0 Motorola Programmer s Reference D 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Internal I O Memory Map D 20 Table D 9 DSP Internal I O Memory Map Continued Address Register Name Reset Value X FFB8 SAPCRA SAP Control Register C 0 X FFB9 SAPSR SAP
117. MCU enters MCU exits STOP mode STOP mode 10 2 3 1 Enabling the PT The PT is enabled by setting the TE bit in PTCR If the TIME bit in PTCR is set the PT is enabled immediately if TIME is cleared PT operation starts at the first CFE after TE is set The TIME bit should only be changed while the PT is disabled TE cleared 10 2 3 2 Halting the PT PT event execution can be halted in one of two ways 1 Executing the end_of_frame_halt command at the end of a table Frame table event execution stops immediately 2 Setting the HLTR bit in PTCR Frame table event execution continues until one of the end of frame commands event codes 7A 7C is executed In either event the THIP bit in the PTIER is set to indicate that the PT is in the process of halting Note 10 10 DSP56652 User s Manual For More Information On This Product Go to www freescale com The PTCR should not be written while a halt is in process or erratic behavior can result Motorola Freescale Semiconductor Inc PT Operation If the MTER bit in PTCR is set macro activity stops immediately after the end_of_frame event is executed If MTER is cleared macro activity continues until the end_of_macro command When all PT activity has finished the THS bit in PTSR is set to indicate that the PT is in halt mode A timer halt interrupt is asserted if the THIE in PTIER is set During halt mode the PT counters and registers remain active The
118. MCU side e g transmit register O written Software should poll DEP until it is cleared before entering STOP mode Reading the DSR to check the DEP bit should be the last MDI access before entering STOP otherwise the DEP can be set as a result of that additional action Allow three NOPs or their equivalent timing after an instruction that sets an event before DEP is updated to accommodate pipeline effects Proper verification of DEP value can prevent loss of shared memory accesses and failure to inform the MCU side of events while the DSP is in STOP mode DF 2 0 R MCU Flags Reflect the MDF 2 0 bits in the O Corresponding MDF bit cleared Bits 2 0 MSR 1 Corresponding MDF bit set 1 R Read only 1S Write 1 only write with 0 ingored R 1S Read write 1 only write with O ingored 5 26 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc MDI Registers DTR1 DSP Transmit Register 1 X FF8C BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from MCU to DSP RESET Table 5 19 DTR1 Description DTR1 is a 16 bit write only register Data written to DTR1 is reflected on the MCU side in MRR1 DTR1 and MRR1 are not double buffered Writing to DTR1 overwrites the data in MRR1 clears the DTE1 bit in the DSR and sets the MRF1 bit in the MSR It can also trigger a receive interrupt on the MCU si
119. Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM TPWSR Timers and PWM Status Register 0020_6004 Biti5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 PWO TOV PWF IF2 IF1 OF4 OF3 OF1 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Each of the bits in this register is cleared by writing it with 1 Writing zero to a bit has no effect Table 9 5 TPWSR Description Name Description Settings PWO PWM Count Rollover Indicates if PWCNT has 0 PWCNT has not rolled over default Bit 7 rolled over 1 PWCNT has rolled over since PWO was last cleared TOV Timer Count Overflow Indicates if TCNT has 0 TCNT has not overflowed default Bit 6 overflowed 1 TCNT has overflowed since TOV was last cleared PWF PWM Output Compare Flag Indicates whether O PWM compare has not occurred default Bit 5 the PWM compare occurred 1 PWM compare has occurred since PWF was last cleared IF2 Input Capture Flags Each bit indicates that the O Capture has not occurred default Bit 4 associated input capture function has occurred 1 Capture has occurred since IF bit was last cleared IF1 Bit 3 OF4 Output Compare Flags Each bit indicates that O Compare has not occurred default Bit 2 the associated output compare function has 1 Compare has occurred since OF bit was last occurre
120. Motorola UART 11 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers 11 4 2 GPIO Registers Four of the UART pins can function as GPIO governed by the following control registers UPCR UART Port Control Register 0020_408A Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O UPC3 UPC2 UPC1 UPCO CTS RTS TxD RxD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 11 UPCR Description Name Description Settings UPC 3 0 Pin Configuration Each bit determines O GPIO default Bits 3 0 whether its associated pin functions as UART or 1 UART GPIO UDDR UART Data Direction Register 0020_408C Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O UDD3 UDD2 UDD1 UDDO CTS RTS TxD RxD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 12 UDDR Description Name Description Settings UDD 3 0 UART Data Direction Each of these bits O Input default Bits 3 0 determines the data direction of the associated 1 Output pin if it is configured as GPIO UPDR UART Port Data Register 0020_408E Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O UPD3 UPD2 UPD1 UPDO CTS RTS TxD RxD RESET 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 13
121. O 10 Priority level 1 PTPL 1 0 Protocol Timer Interrupt Priority Level 11 Priority level 2 Bits 7 6 SAPPL 1 0 SAP Interrupt Priority Level Bits 5 4 BBPPL 1 0 BBP Interrupt Priority Level Bits 3 2 MDCPL 1 0 MDI Command Priority Level Bits 1 0 7 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Edge Port IPRC Interrupt Priority Register Core X FFFF BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O IDTM IDPL 1 0 ICTM ICPL 1 0 IBTM IBPL 1 0 lATM IAPL 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7 9 IPRC Description Name Description Setting IDTM Interrupt D Trigger Mode Should remain level sensitive O Level sensitive default Bit 11 1 Edge sensitive ICTM Interrupt C Trigger Mode Should remain level sensitive Bit 8 IBTM Interrupt B Trigger Mode Should remain level sensitive Bit 5 ATM Interrupt A Trigger Mode Bit 2 IDPL 1 0 Interrupt D Priority Level This interrupt should be enabled 00 Disabled default Bits 10 9 before the DSP enters STOP mode 01 Priority level 0 10 Priority level 1 ICPL 1 0 Interrupt C Priority Level This interrupt should be enabled 11 Priority level 2 Bits 7 6 before the DSP enters STOP mode IDPL 1 0 Interrupt B Priority Level This interrupt is generated by the Bits 4 3 DSP_IRQ pin It should be act
122. One bit is shifted on each cycle of a 1x transmit clock It derives the 1x clock from the 16x clock produced by the clock generator Transmission can begin as soon as UTX is written or can be delayed until the far end receiver asserts the RTS signal Interrupts can be generated when RTS changes state and when UTX is empty or the number of untransmitted words falls below a programmed threshold The transmitter is enabled by setting the TXEN bit in UART Control Register 1 UCR1 11 2 2 Receiver The UART receiver contains a 16 word FIFO URX one character per word enabling the MCU to perform block reads using the Load Multiple LDM command It receives bits serially from the UART receive pin RxD strips the start stop and parity if present bits and stores the characters in URX To provide jitter and noise tolerance the receiver samples each bit 16 times and applies a voting technique to determine the bit s value The receiver monitors data for proper frame construction BREAK characters all zeros parity errors and receiver overrun Each of the 16 URX words contains a received character data field error flags and a character ready flag to indicate when the character Motorola UART 11 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Architecture is ready to be read Errors flags include those for frame parity BREAK and receiver overrun as well as a general e
123. PROT RTPTR 0xlE fdefine PROT FTBAR 0x20 define PROI RTBAR 0x22 define PROT DTPTR 0x24 else struct redcap prot ctrl unsigned short tctr timer control register unsigned short tier timer interrupt enable register volatile unsigned short tstr timer status register volatile unsigned short tevr timer event register unsigned short tipr time interval prescaler register volatile unsigned short ctic channel time internal counter unsigned short ctipr channel time interval preload regiser volatile unsigned short cfc channel frame counter unsigned short cfpr channel frame preload register volatile unsigned short rsc reference slot counter unsigned short rspr reference slot preload register unsigned short pdpar port d pin assignment register unsigned short pddr port d direction register volatile unsigned short pddat port d data register volatile unsigned short ftptr frame table pointer register volatile unsigned short rtptr receive transmit macro tables pointer regis ter unsigned short ftbar frame table base address register unsigned short rtbar receive tranmit macro tables base address register volatile unsigned short dtptr delay table pointer register y endif Fendif B 3 DSP Equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk DSP Equates for DSP56651 DSP56652 B 32 DS
124. PT2 0 28 26 Protocol Timer 2 0 PTM 25 Protocol Timer 5 ORed QSPI 24 QSPI 4 ORed MDI 23 MDI 6 ORed SCP 22 SCP 3 ORed TPW 17 Timer PWM 8 ORed PIT 16 PIT KPD 14 Keypad Interface URTS 13 UART RTS INT7 0 12 5 External Interrupt 7 0 S2 0 2 0 Software Interrupt 2 0 T6 DSP56652Use rsMaua Motorda For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Interrupt Controller NIER Normal Interrupt Enable Register 0020_0004 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16 EURX ESMPC EUTX EPT2 EPT1 EPTO EPTM EQSPI EMDI ESCP ETPW EPIT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O EKPD EURTS EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINTO ES2 ES1 ESO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIER Fast Interrupt Enable Register 0020 0008 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16 EFURXEFSMPC EFUTX EFPT2 EFPT1 EFPTO EFPTM EFQSPI EFMDI EFSCP EFTPW EFPIT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O EFKPD EFURTSJ EFINT7 EFINT6 EFINT5 EFINT4 EFINT3 EFINT2 EFINT1 EFINTO NES2NNES1 NESO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The NIER is used to enable pending interrupt requests to the core
125. PTSR and generates an interrupt if the RSNIE bit in PTIER is set RSMR Reference Slot Modulus Register 0020_3814 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BitO RSMVI 7 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 17 RSMR Description Name Description RSMV Reference Slot Modulus Value This field contains the value loaded into RSC when it is enabled and Bits 7 0 when it rolls over An RSMV value of 0 is not supported This register should be written before the RSC is enabled Motorola Protocol Timer 10 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers FTPTR Frame Table Pointer 0020_381C Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O FTPTR 6 0 RESET 0 0 0 0 0 0 0 0 0 Table 10 18 FTPTR Description Name Description FTPTR 6 0 Frame Table Pointer 6 0 These read only bits contain a pointer to the next frame table entry Bits 6 0 MTPTR Macro Table Pointer 0020 381E Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 TxPTR 6 0 RxPTR 6 0 RESET 0 0 Table 10 19 MTPTR Description Name Description TxPTR 6 0 Transmit Macro Pointer 6 0 These read only bits contain a pointer to the next transmit macro Bits 14 8 table entry RxPTR 6 0 Receive Macro Pointer 6 0 These read only bits contain a pointer to
126. QSPI command a higher priority QSPI trigger or a power down mode Motorola Queued Serial Peripheral Interface 8 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Operation 8 3 3 Ending a Transfer Cycle A transfer cycle ends when all data in the queue has been transferred This condition is indicated in the last control halfword by either setting the PAUSE bit or programming the PCS field with NOP or EOQ refer to the Control RAM description on page 8 22 8 3 3 1 PAUSE At the completion of transfer of each queue entry the QSPI checks whether the PAUSE bit is set in the control halfword for that entry If so the QSPI assumes it has reached the end of the programmed queue and clears the QAn and the QXn flags If EOTIE is detected in the PCS field of the control halfword for that queue entry the QSPI sets the EOTn flag in the SPSR and generates an interrupt to the MCU If the PAUSE bit is cleared the QSPI continues the transfer process 8 3 3 2 NOP and EOQ Each time the QSPI loads a queue entry from RAM step 3 or 10 in the transfer cycle on page 8 9 it checks for EOQ end of queue or NOP no operation in the PCS field If the QSPI detects one of these codes it assumes it will reach the end of the programmed queue after it completes the transfer of the current datum and clears the QAn and QXn flags If EOTIE is detected for the present queue entry the QSPI asserts the EOTn flag
127. REG BASE REDCAP MCU MDI 0xFF2 ifdef ASSEM define MDI MCVR 0x2 define MDI MCR 0x4 define MDI MSR 0x6 define MDI MIR1 0x8 define MDI MIRO Oxa define MDI MRR1 Oxc define MDI _MRRO Oxe Motorola Equates and Header Files For More Information On This Product Go to www freescale com B 25 Freescale Semiconductor Inc MCU Include File else struct redcap mdi regs volatile unsigned short mcvr command vector register volatile MC bit volatile unsigned short mcr control register volatile MDIR bit volatile unsigned short msr status register unsigned short mtrl transmit register 1 unsigned short mtr0 transmit register 0 volatile unsigned short mrrl receive register 1 read only volatile unsigned short mrr0 receive register 0 read only y endif mcvr register bits define MCVR MNMI 0x0001 define MCVR MCVO 0x0002 define MCVR MCV1 0x0004 define MCVR MCV2 0x0008 define MCVR MCV3 0x0010 Zdefine MCVR MCV4 0x0020 define MCVR MCV5 0x0040 define MCVR MCV6 0x0080 define MCVR MC 0x0100 mcr register bits Zdefine MCR MFO 0x0001 define MCR MF1 0x0002 define MCR MF2 0x0004 define MCR MDIR 0x0040 define MCR DHR 0x0080 define MCR MGIEl 0x0400 define MCR MGIEO 0x0800 define MCR MTIEl 0x1000 define MCR MTIEO 0x2000 define MCR MRIE1 0x4000 define MCR MRIEO 0x8000 msr register bits define MSR MFO 0x0001 define MSR MF1 0x0002 define MSR MF
128. SCDO EQU 2 Serial Control 0 Direction SAP SCD1 EQU 3 Serial Control 1 Direction SAP SCD2 EQU 4 Serial Control 2 Direction SAP SCKD EQU 5 Clock Source Direction SAP CKP EQU 6 Clock Polarity SAP SHFD EQU 7 Shift Direction SAP BRM EQU 8 Binary Rate Multiplier BRM enable SAP FSL EQU 3000 Frame Sync Length Mask FSLO FSL1 SAP FSLO EQU 12 Frame Sync Length 0 SAP FSL1 EQU 13 Frame Sync Length 1 SAP FSR EQU 14 Frame Sync Relative Timing SAP FSP EQU 15 Frame Sync Polarity e Ne Ne Ne SAP Status Register Bit Flags SAP_IF EQU 3 Serial Input Flag Mask SAP IFO EQU 0 Serial Input Flag 0 SAP IF1 EQU 1 Serial Input Flag 1 SAP TFS EQU 2 Transmit Frame Sync Flag SAP_RFS EQU 3 Receive Frame Sync Flag SAP TUE EQU 4 Transmitter Underrun Error FLag SAP_ROE EQU 5 Receiver Overrun Error Flag SAP TDE EQU 6 Transmit Data Register Empty SAP RDF EQU 7 Receive Data Register Full EQUATES for Exception Processing if DEF I VEC leave user definition as it is else I VEC equ 0 endif Non Maskable interrupts RESET EQU I VEC 00 Hardware RESET STACK EQU I VEC 02 Stack Error ILL EQU I VEC 04 Illegal Instruction DBG EQU I _VEC S06 Debug Request TRAP EQU I VEC 08 Trap H HH He ses H I IROA EQU I_VEC S10 I IROB EQU I VEC 12 IROB fram DSP IRQ pin I IROC EQU I VEC 14 IRQC from MDI wake up from stop B 38 DSP56652 User s Manual Motorola
129. SS 1 2 2 1 4 Program Patch Logic The program patch logic PPL block provides a way to adjust program code in the on chip ROM without generating a new mask Implementing the code correction is done by replacing a piece of ROM based code with a patch program stored in RAM The PPL consists of four patch address registers PARO PAR3 and four patch address 1 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview comparators Each PAR points to a starting location in the ROM code where the program flow is to be changed The PC register in the PCU is compared to each PAR When an address of a fetched instruction is identical to an address stored in one of the PARs the program data bus is forced to a corresponding JMP instruction replacing the instruction that otherwise would have been fetched from the ROM 1 2 2 2 DSP Side Peripherals The DSP side peripherals for the DSP56652 are primarily targeted at handling baseband and audio processing e Two improved synchronous serial ports connect to external codecs to process received baseband information The SAP connects to a standard audio codec This port also provides a general purpose timer The BBP connects to a standard RF IF codec e DSP OnCE facilitates test and debug 1 2 2 3 DSP Side Memory All DSP memory is contained on chip DSP program memory is 24 bits wide while
130. STDB Output Input Baseband Codec Transmit Data This output signal transmits serial data from the baseband codec serial transmitter shift register SRDB Input Input Baseband Codec Receive Data This input signal receives serial data and transfers the data to the baseband codec receive shift register SCKB Input or Input Baseband Codec Serial Clock This bidirectional signal provides the Output serial bit rate clock It is used by both transmitter and receiver in synchronous mode or by the transmitter only in asynchronous mode SCOB Input or Input Baseband Codec Serial Clock 0 This signal s function is determined Output by the SCLK mode Synchronous mode serial I O flag O Asynchronous mode receive clock I O SC1B Input or Input Baseband Codec Serial Clock 1 This signal s function is determined Output by the SCLK mode Synchronous mode serial I O flag O Asynchronous mode receiver frame sync I O SC2B Inputor Input Baseband Codec Serial Clock 2 This signal s function is determined Output by the SCLK mode Synchronous mode transmitter and receiver frame sync I O Asynchronous mode transmitter frame sync I O 2 14 MCU Emulation Port The signals described in Table 2 17 are GPIO when not programmed otherwise and default as GPI after reset Table 2 17 Emulation Port Signals Signal Name Type Reset State Signal Description SIZO SIZ1 Output Input Data Size These output signals encod
131. Scan Architecture The block diagram of these two TAPs is shown in Figure 15 1 All JTAG testing functions in the DSP56652 are performed by the DSP TAP controller The JTAG specific functions required by IEEE 1149 1 are not included in the MCU TAP controller which is bypassed in JTAG compliance mode The MCU TAP controller is only active in MCU OnCE emulation mode in which the two controllers are enabled and connected serially MCU OnCE operation is described in the MMC2001 Reference Manual DSP OnCE operation is described in the DSP56600 Family Manual This chapter describes aspects of the JTAG implementation that are specific to the DSP56600 core including items which the IEEE standard requires to be defined and additional information specific to the DSP core implementation For internal details and applications of the standard refer to the IEEE 1149 1 document Motorola JTAG Port 15 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc m W MCU DE MCU DEBUG TOR TAP STATE TS7 LOGIC RESET TRST i MCU ONCE ENABLE MCU ONCE ENABLE p e MCU OnCE TAP e and Mode Select TDI E MCU_TDO e W TDI MODE TDO A 0 JTAG OnCE TDI MUX es ZE e TDI O DSP OnCE and chip level DSP_TDO JTAG TAP ae p gt W DSP DE Figure 15 1 DSP56652 JTAG Block Diag
132. Several facets of SAP and BBP TDM operation can be controlled including synchronous or asynchronous mode frame configuration frame sync parameters serial I O flags and interrupts 14 3 1 Synchronous and Asynchronous Modes The transmit and receive sections for each port can operate either synchronously or asynchronously as determined by the Synchronous Mode SYN bit in the SAPCRC or BBPCRC In asynchronous mode there are separate independent signals and pins for the transmit clock receive clock transmit frame sync TFS and receive frame sync RFS The synchronous mode has a common transmit and receive clock and a common transmit and receive frame syncs Pin assignments for these signals are listed in Table 14 1 on page 14 3 14 3 2 Frame Configuration Each port can be configured for one time slot per frame normal mode or multiple time slots per frame network mode Each of these modes is periodic A non periodic on demand mode is also provided The mode is determined by Operation Mode MOD bit in the SAPCRC or BBPCRC and the Frame Rate Divider Control DC 4 0 bits in the SAPCRA or BBPCRA as shown in Table 14 3 Table 14 3 Frame Configuration MOD DC 4 0 Value Mode DC 4 0 Meaning 0 0 31 Normal Word transfer rate 1 1 1 31 Network Number of time slots 1 1 0 On Demand 14 3 2 1 Normal Mode Normal mode is typically used to transfer data to or from a single device There can be
133. Signal Connection Description 2 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Interface Module 2 4 External Interface Module The bus bus control and chip select signals of the EIM are listed in Table 2 5 Table 2 6 andTable 2 7 respectively Table 2 5 Address and Data Buses Signal Name Type Reset State Signal Description A0 A21 Output Driven low Address bus These signals specify the address for external memory accesses If there is no external bus activity AO A21 remain at their previous values to reduce power consumption DO D15 Input Output Input Data bus These signals provide the bidirectional data bus for external memory accesses They remain in their previous logic state when there is no external bus activity to reduce power consumption Table 2 6 Bus Control Signal Name Type Reset State Signal Description R W Output Driven high Read Write This signal indicates the bus access type A high signal indicates a bus read A low signal indicates a write to the bus This signal can also be used as a memory write enable WE signal When accessing a peripheral chip the signal acts as a read write Output Driven high Enable Byte 0 When driven low this signal indicates access to data byte 0 D8 D15 during a read or write cycle This pin may also act as a write byte enable
134. Software Restriction Summary jset ZDTEO x DSR tx sbr MCU software should verify that the DSP is not engaged in MDI signalling activity before asserting MDIR This can be done by performing the following steps a Disable the DSP interrupt event in the Protocol Timer by clearing the DSIE bit in the PTIER b Verify that both DWS and MTIR MSR bits 8 and 9 are cleared The instruction immediately following assertion of the MDIR bit may be overridden by the reset sequence with all registers retaining their reset values Therefore software should wait at least one instruction before writing to MDI registers 5 5 MDI Software Restriction Summary Tables 5 5 through 5 7 summarize the various constraints on MDI software Table 5 5 General Restrictions Action Restriction Writing to a transmit register Wait for a Transmitter Empty interrupt or poll the Transmitter Empty bit in the status register Reading from a receive register Wait for a Receiver Full interrupt or poll the Receiver Full bit in the status register Table 5 6 DSP Side Restrictions Action Restriction Setting DGIR 0 1 to issuing general interrupt request Verify that DGIR 0 1 is cleared Configuring IRQC and IRQD Delay between MDI register write and reflection in DSR Define IRQC as level triggered by clearing the ICTM bit in the IPRC Define IRQD as level triggered by clearing the IDTM bit in the IPRC
135. UART enabled the transmitter stops immediately and pulls TxD to logic one 11 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers UCR2 UART Control Register 2 0020_4082 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O IRTS CTSC CTSD PREN PROE STPB CHSZ CLKSRC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 7 UCR2 Description Name Description Settings IRTS Ignore RTS Pin Setting this bit configures the 0 RTS qualifies data transmission default Bit 14 UART to ignore the RTS pin enabling it to 1 RTS ignored transmit at any time When IRTS is cleared the UART must wait for RTS to assert before it can transmit CTSC CTS Pin Control This bit determines whether O CTSD bit controls CTS default Bit 13 hardware or software controls the CTS pin When 1 Receiver control CTS CTSC is set the receiver controls CTS automatically deasserting it when URX is full When CTSC is cleared the CTS pin is driven by the CTSD bit CTSD CTS Driver This bit drives the CTS pin when 0 CTS driven high default Bit 12 CTSC is cleared Setting this bit asserts CTS 1 CTS driven low meaning that it is driven low clearing CTSD deasserts pulls high CTS When CTSC is set this bit has no effect PREN Parity Enable Controls the parity g
136. WS8 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WSO Reserved Motorola Programmer s Data Sheets E 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer TD Description PWM 0 Timers are enabled in DOZE mode 1 Timers are disabled in DOZE mode Timers and PWM Control Register TE Description Address 0020_6000 0 Timers are disabled Reset 0000 Read Write 1 Timers are enabled PWE Description PSPW 0 2 Description 0 PWM counter is disabled 000 PWM prescaler factor 1 1 PWM counter is enabled 001 PWM prescaler factor 2 010 PWM prescaler factor 4 011 PWM prescaler factor 8 PWD Description 100 PWM prescaler factor 16 0 PWM counter is enabled in DOZE 101 PWM prescaler factor 32 mode n 1 PWM counter is disabled in DOZE ie APIO mode 111 PWM prescaler factor 128 TDBG Description PST 0 2 Description 0 Timer stops in Debug mode 000 Timer prescaler factor 1 1 Timer runs in Debug mode 001 Timer prescaler factor 2 010 Timer prescaler factor 4 A 011 Timer prescaler factor 8 PWDBG Description 100 Timer prescaler factor 16 0 PWM counter stops during Debug 101 Timer prescaler fact
137. accesses allowed 1 The OE signal is asserted half a clock cycle later on read accesses 1 User mode accesses prohibited CSA Description WP Description 0 The CS signal is asserted normally 0 Writes are allowed 1 The CS signal is asserted one cycle later on read and write 1 Writes are prohibited accesses and an extra cycle inserted between back to back cycles PA Description EDC Description 0 CS pin at logic high 0 No delay occurs after a read cycle 1 CS pin at logic low 1 One clock cycle is inserted after a read cycle CSEN Description e 0 Chip Select function is disabled wws Description and CSO pin is an output 0 Read and write WAIT states same 1 Chip Select function is enabled 1 Write WAIT states Read WAIT states 1 WSC 0 3 Description Binary value of number of external memory wait states 31 16 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 WSC3 WSC2 WSC1 WSCO WWS EDC CSA OEA WEN EBC DSZ1 DSZO SP WP PA CSEN Reserved E 22 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer ElM 3116 15 14 13 12 11 10 9 8 7 6 5 4 Description User mode access to internal ROM EIMCR om User mode access p internal RO
138. address register addresses relative to base address equ eim cs0 control reg 0x0 equ eim csl control reg 0x4 equ eim cs2 control reg 0x8 equ eim cs3 control reg Oxc Motorola Equates and Header Files B 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Equates equ eim cs4 control reg equ eim cs5 control reg equ eim configuration reg 0x10 0x14 0x18 Bits definitions for the EIM CS configuration registers equ eim cs csen 0x0 equ eim cs pa equ eim cs wp equ eim cs sp equ eim cs dsz equ eim cs ebc equ eim cs wen equ eim cs oea equ eim cs csa equ eim cs edc equ eim cs ws equ eim cs wsc 0x1 0x2 0x3 0x4 0x6 0x7 0x8 Chip select enable Output value for CSO only when csen 0 Write Protec Supervisor Protect Data Port Size Enable Byte Control Determines when EBO 1 outputs are negated during a write cycle Determines when OE is asserted during a read cycle Chip Select Assert Extra Dead Cycle Write Wait State Wait State Control EIM configuration register bits definitions equ eim cr shen equ eim cr hdb equ eim cr spram equ eim cr spram equ eim cr spiper equ eim cr epen Peripheral Interrupt Controller equ pic base address equ pic isr equ pic normal enable equ pic fast enable equ pic normal pending equ pic fa
139. address bit address bit address bit address bit OU 0o ND IDO address bit address bit address bit address bit address bit address bit address bit OU 0o NN IDO Receive delay base address bit 0 Receive delay base address bit 1 Receive delay base address bit 2 Receive delay base address bit 3 Transmit delay pointer bit 0 Transmit delay pointer bit 1 Transmit delay pointer bit 2 Oxb Transmit delay base address bit 0 Oxc Transmit delay base address bit 1 Oxd Transmit delay base address bit 2 Oxe Transmit delay base address bit 3 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc general definitions Motorola urx urx 20 utx utx 60 ucrl ucr2 ubrg usr uts upcr uddr updr ucrl uen ucrl doze ucrl sndbrk ucrl rtsden ucrl rtsdie ucrl txmptyen ucrl txeie ucrl iren ucrl rxen ucrl rrdyen ucrl rrdyie ucrl rxflO ucrl rxfll ucrl txen ucrl trdyen ucrl trdyie ucrl txflO ucrl txfll ucr2 ws ucr2 chsz ucr2 stpb ucr2 proe ucr2 pren ucr2 cts ucr2 ctsd ucr2 CTSC ucr2 irts UART status register USR usr rtsd usr rrdy usr trdy usr rtss usr txmty 0x00204000 0x00204020 0x00204040 0x00204060 0x00204080 0x00204082 0x00204084 0x00204086 0x00204088 0x0020408a 0x0020408c 0x0020408e UART control register 1 UCR1 ucrl uarten 0
140. address offset which is also equal to the DSP offset and the 16 bit MCU addresses offset is OFFycu OFEINT 2 All MCU accesses to the MDI shared memory should be evenly aligned 16 bit accesses to ensure valid operation 5 1 3 Shared Memory Access Contention Access contentions are resolved in hardware DSP access has precedence because it runs on a faster clock than the MCU which is stalled until the DSP access is completed Contention is defined as simultaneous access read or write by both MCU and DSP to the same 1 4 Kword of the shared memory Simultaneous access to different 1 4K blocks of shared memory or to the MDI control registers proceed without stall Motorola MCU DSP Interface 5 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Memory The MCU side contains a data buffer to store a halfword from a write request enabling the MCU to write with no stall even if the memory array is busy with a DSP access However if a second access read or write is attempted before the buffer is cleared the MDI will stall the MCU Some stalls may last less then one MCU clock and so may not even be evident on the MCU side On the other hand several consecutive 1 cycle accesses by the DSP to the MDI memory can stall an MCU access for the equivalent number of clock cycles For example Example 5 1 show a program loop that transfers data from X to Y memory Any attempt by the MCU t
141. amp DSP IRQ B A9 8 SRDB ALO 8 EGND All amp SRDA A12 8 STDA A13 8 AGND Bl C2 amp ADDR Gl H3 G5 G4 G3 F5 F4 F2 El F3 E4 E3 E2 C2 B2 C3 amp ADDR21 B3 A QVCC B7 H1 J14 M8 amp MOSI B8 amp SCB E9 D9 B9 amp SCA B10 C10 D10 amp SCKA B11 amp PSTAT C13 B13 B12 C11 8 KGND B14 AVDD Cl El amp HVDD C6 amp OGND C7 H12 J2 N8 8 SCKB C8 amp STDB C9 8 KVDD C12 og SIZ D12 C14 amp SCK D7 amp DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Boundary Scan Description Language MISO D8 amp EVDD D11 amp MUX CTL D13 amp CTS B D14 amp RESERVED E8 amp RTS B Ell amp RX E12 amp TEST E13 amp TX El4 amp TDO F10 amp TCK F11 amp DSP DE B F12 8 TDI F13 TRST B Fl4 amp MCU DE B G10 amp ROW K14 J13 J11 J10 H13 H14 G13 G11 amp TMS G14 amp EB B H4 H2 amp GGND H10 L13 amp GVDD H11 L11 amp FGND Jl amp CKIH J3 amp CKOH J4 amp CKIL J5 amp INT L12 N14 M14 L14 K13 K12 Kll J12 amp CKO Kl amp FVDD K2 8 OE B K3 amp RW B K4 8 DATA N3 M4 P2 P3 N4 14 P4 N5 M
142. and generates an interrupt to the MCU The EOQ command can also be used to program the next entry point for the queue without MCU intervention If LEn in QCRn is set when a cycle terminates with EOQ the QSPI writes the 6 least significant bits of the queue entry s datum into the QPn field of QCRz 8 3 4 Breaking a Transfer Cycle Normally once a queue is started transfer continues until an end of queue is indicated When the queue completes its transfer the next active queue with the highest priority begins execution However a queue can be interrupted at a sub queue boundary to enable a higher priority queue to execute rather than waiting for the current queue to finish If a higher priority queue is triggered while a lower priority queue is executing and the HMD bit of the lower priority queue s QCR is cleared the QSPI suspends the execution of the lower priority queue at the next sub queue boundary and starts executing the higher priority queue The QA bit of the suspended queue remains set and the QSPI resumes execution of the lower priority queue after it has completed the execution of the higher priority queue A sub queue boundary is a queue entry whose control halfword contains a cleared CONT bit and or a PCS field that activates a different SPICS line than the currently active one 8 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Operatio
143. and Memory Table 8 5 SPSR Description Continued Name Type Description Settings TRC Bit 5 R 1C Trigger Collision Asserted when a transfer trigger for one of the queues occurs while the queue is activated QAn 1 Software should allow sufficient time for a queue to finish executing a queue in normal operation before the queue is retriggered If the TRCIE bit is set in the SPCR assertion of the TRC bit generates an interrupt to the MCU This bit can be cleared by the MCU by writing a value of logic 1 into it For Queue 1 TRC is only asserted when the trigger counter TRCNT 1111b and a new trigger occurs The MCU clears TRC by writing it with 1 0 No collision 1 A collision has occurred QPWF Bit 4 R 1C Queue Pointer Wraparound Flag If a queue pointer contains the value 7F and is incremented to read the next word in the queue step 10 the QP wraps around to address 00 and QPWF is asserted If the WIE bit in the SPCR has been set an MCU interrupt is generated The MCU clears QPWF by writing it with 1 QPWF is not asserted when a QP is explicitly written with 00 as a result of an EOQ command from Control RAM Note O No wraparound 1 A wraparound has occurred EOT 3 0 Bits 3 0 R AC End of Transfer When the PCS field of a queue entry is EOTIE PCS 110 the QSPI asserts the associated EOT bit and generates an interrupt to the MCU Beca
144. anywhere in MDI memory MDI Messaging Unit Registers 15 14 13 12 10 9 0 l MCU address DSP address i MCU_MDI_BASE 2 offset MDI Shared Memory DSP_MDI_BASE offset I memory_check request sa RAM unused result_address_offset uu EUR 4 I MCU_MDI_BASE DSP_MDI_BASE 2 dest address offset dest address offset l DSP uses this location for its long reply message AF Figure A 7 Format of memory_check request Message Motorola DSP56652 DSP Bootloader A 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 2 6 memory_check response memory check response is a long message from the DSP to the MCU in response to a memory check request message The format of this message is shown in Figure A 8 Note that this message resides in MDI shared memory location specified in the result address offset field of the memory check request message The entry in MDI shared memory following the memory_check response opcode is the return code 0000 indicates success and 0001 indicates failure The following entry is the failure address if the memory check has failed and zero if the check is successful MDI Messaging Unit Registers 15 14 10 9 0 MCU address DSP address i MCU_MDI_BASE 2 offset MDI Shared Memory DSP MDI BASE offset I memory_check request c3 return code 0 success 1 failure failure address if failure O otherwise
145. card is removed during DOZE mode All state machines and registers retain their current values When exiting DOZE mode the SCP reenables all its clocks and resumes operation with its previously retained state If the DOZE bit in the SCPCR is cleared the SCP continues full operation in DOZE mode When the MCU enters STOP mode the SCP gates off the CKIH clock and freezes all state machines and registers Software must complete all transmit receive transactions and power down the SCP before entering STOP mode When exiting the Stop mode the SCP reenables all its clocks and resumes operation with its previously retained state 12 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Operation 12 2 5 Interrupts The SCP generates two interrupts to the MCU e SMPC is generated when the smart card position is changed i e inserted or removed e SCP indicates all other SCP interrupt conditions generated by transmission reception and errors Error interrupts have priority over transmit and receive interrupts Receive interrupts are not cleared until the SCPDR is read Figure 12 5 illustrates the sources and conditions that generate the various SCP interrupts SMPC Interrupt Error Parity Error Frame Error Overrun Transmit Complete SCTC Tx SCP SCTCIE Interrupt Rx FIFO Not Empty SCFN SCFNIE B E j Rx Rx FIFO Full SCFF SCFFIE
146. configured so that its last data entry is written to its queue pointer thus programming the start address for the next queue trigger from the queue itself This enables wrapping to the beginning of the queue or branching from one sequence to another when a new transfer trigger activates the queue 8 1 8 Pause Enable at Queue Entry Boundaries A queue transfer can be programmed to terminate at queue entry boundaries by inserting a PAUSE command in the control halfword of the queue entry at that boundary This feature enables each of the four transfer triggers to provide programmable multiple task support and considerably reduces MCU intervention 8 2 QSPI Architecture This section describes the QSPI pins control registers functional modules and special purpose RAM Most of these components are shown in the QSPI flow diagram in Figure 8 1 The QSPI port can also function as GPIO which is governed by three control registers that are also described Motorola Queued Serial Peripheral Interface 8 3 For More Information On This Product Go to www freescale com QSPI Architecture 8 2 1 QSPI Pins Freescale Semiconductor Inc The QSPI pin description in Section 8 2 is repeated in Table 8 1 for convenience All pins are GPIO when not programmed otherwise and default as general purpose inputs after reset Note The DSP36652 QSPI always functions as SPI master Table 8 1 Serial Control Port Signals Signal Name Type
147. counts down to the value preprogrammed in the PWOR the pulse is asserted and following events occur 1 The PWF bit in TPWSR is set 2 An interrupt is generated if the PWFIE bit in TPWCR has been set 3 If the PWC bit in TPWMR is set the PWM output pin is driven to its active state which is determined by the PWP bit in TPWMR When PWCNT counts down to zero the pulse is deasserted generating the following events 1 The PWO bit in TPWSR is set 2 An interrupt is generated if the PWOIE bit in TPWCR has been set 3 If the PWC bit in TPWMR is set the PWM output pin is driven to its inactive state 4 The PWMR value is reloaded to PWCNT The pulse duty cycle can range from 0 PWOR 0 to 99 9985 65535 65536 100 PWOR PWMR FFFF The PWM period can vary between a minimum of 2 MCU_CLK cycles and a maximum of 65536 256 MCU_CLK cycles 9 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM 9 3 3 GP Timer and PWM Registers TPWCR Timer and PWM Control Register 0020_6000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O PWDBG TDBG PWD PWE TD TE PSPW 2 0 PST 2 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9 3 TPWCR Description Name Description Settings PWDBG PWM Debug Enables PWM operation during 0 PWM frozen in Debug mode default
148. default Bits 15 8 1 Output KRDD 7 0 Keypad Row Pin Data Direction Bits 7 0 Each of these bits determines the data direction of the associated pin Valid data should be written to the KPDR before any of these bits are configured as outputs KPDR Keypad Port Data Register 0020_A006 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O KCD 7 0 KRD 7 0 Table 13 6 KPDR Description Description RESET Name Each of these bits contains data for the corresponding keypad pin Writes to KPDR are stored in an internal latch and driven on any port pin configured as an output Reads of this register return the value sensed on input pins and the latched data driven on outputs KCD 7 0 Keypad Column Data Bits 15 8 KRD 7 0 Keypad Row Data Bits 7 0 13 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 14 Serial Audio and Baseband Ports The Serial Audio Port SAP and the Baseband Port BBP are both DSP peripherals based on the synchronous serial interface SSI included in several other Motorola DSP devices Each port supports full duplex serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Motorola SSI Features common to both the SAP and the BBP include the following e Independent transmit and recei
149. e PWCNT The PWM Counter reflects the current PWCNT value Figure 9 6 is a block diagram of the pulse width modulator The pulse width modulator is based on a 16 bit free running down counter PWCNT The PSPW 2 0 bits in TPWCR select one of eight possible divisions of MCU_CLK as the clock for PWCNT PSPW 2 0 can be changed at any time to select a different frequency for the PWCNT clock the change does not take effect until the 8 bit divider rolls over to zero When the PWE bit in TPWCR is set PWCNT is loaded with the value in PWMR and begins counting down If PWE is later cleared the counter freezes at its current value If PWE is set again PWCNT is reloaded with PWMR and begins counting down The MCU can read PWCNT at any time to get the current value of PWCNT 1 These registers also contain bits used by the GP timer Motorola Timers 9 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM PWM Prescaler Clock Output PWO gull PWOIE MCU Peripheral Bus PWP PWC Interrupt PWFIE ene Figure 9 6 PWM Block Diagram PWCNT is frozen when the MCU enters STOP mode DOZE mode if the PWD bit in TPWCR is set or Debug mode if the PWDBG bit in TPWCR is set In each case PWCNT resumes counting from its frozen value when the respective mode is exited If PWD or PWDBG are cleared entering the associated mode does not affect PWM operation When PWCNT
150. freescale com Freescale Semiconductor Inc Application Date Programmer QC RO HMDO Description 0 Queue 0 halts only at end of queue Queue Control Register 0 Address 0020 5F08 1 O halts on any sub queue Reset 0000 EHE Read Write LEO Description 1 P Queue 0 Pointer 0 Queue 0 reloading disabled 1 Queue 0 reloading enabled 15 14 13 12 11 10 8 5 4 3 2 1 0 LEO HMDO QP05 QP04 QPO3 QP02 QP01 QPOO 0 0 0 0 0 0 0 0 HMD1 Description QC R 1 0 Queue 1 halts only at end of queue Queue Control Register 1 1 eor hans cd ds ad Address 0020_5FOA Reset 0000 Read Write Trigger Counter LE1 Description 0 Queue 1 reloading disabled 1 Queue 1 reloading enabled Queue 1 Pointer 15 14 13 12 11 10 9 8 7 E 5 4 3 2 1 0 Reserved TRCNT3 TRCNT2 TRCNT1 TRCNTO QP15 QP14 QP13 QP12 QP11 QP10 E 40 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc
151. generates a TEA error and the CS signal is not asserted PA Pin Assert Controls the Chip Select pin when itis O CS pin at logic low Bit 1 operating as a general purpose output i e the 1 CS pin at logic high CSEN bit is cleared This bit is ignored if the CSEN bit is set Note that Chip Select 0 does not have a PA bit CSEN Chip Select Enable When CSEN is set the CS 0 CS pin disabled Bit 0 pin is asserted during an access to its address 1 CS pin enabled space When CSEN is cleared an access to the CS address space generates a TEA error and the CS pin is not asserted Motorola External Interface Module 6 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Registers EIMCR EIM Configuration Register 0020_1018 BIT 31 7 6 5 4 3 2 1 BITO EPEN SPIPER SPRAM SPROM HDB SHEN1 0 RESET 0 0 1 1 1 0 0 0 Table 6 7 ElMCR Description Name Description Settings EPEN Emulation Port Enable Controls the functions of O Pins function as GPIO default Bit 6 the Emulation Port pins SIZ 1 0 and PSTAT 3 0 1 Emulation Port drives the pins with the MCU SIZ 1 0 and PSTAT 3 0 signals SPIPER Supervisor Protect Internal Peripheral O User Mode access to internal peripherals Bit 5 Prohibits User Mode access to all internal allowed peripheral space When SPIPER is set a read or 1 User Mode access to internal peripherals write
152. if so programmed This output is used when accessing 8 bit wide SRAM UJ Output Driven high Enable Byte 1 When driven low this signal indicates access to data byte 1 DO D7 during a read or write cycle This pin may also act as a write byte enable if so programmed This output is used when accessing 8 bit wide SRAM Output Driven high Table 2 7 Chip Select Signals Bus select When driven low this signal indicates that the current bus access is a read cycle and enables slave devices to drive the data bus with a read Signal Name Type Reset State Signal Description CSO Output Chip driven Chip Select 0 This signal is asserted low based on the decode of the internal address bus bits A 31 24 and is typically used as the external flash memory chip select After reset accesses using CSO have a default of 15 wait states Output Driven high Chip Selects 1 4 These signals are asserted low based on the decode of the internal address bus bits A 31 24 of the access address When not configured as chip selects these signals become general purpose outputs GPOs After reset these signals are GPOs that are driven high Output Driven low Chip Select 5 This signal is asserted high based on the decode of the internal address bus bits A 31 24 of the access address When not configured as a chip select this signal functions as a GPO After
153. inserted after a head cycle CSEN Description TENES 0 Chip Select function is disabled WWS Description and CSO pin is an output 0 Read and write WAIT states same 1 Chip Select function is enabled 1 Write WAIT states Read WAIT states 1 WSC 0 3 Description Binary value of number of external memory wait states 31 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSC3 WSC2 WSC1 WSCO WWS EDC CSA OEA WEN EBC DSZ1 DSZO SP WP PA CSEN Reserved Motorola Programmer s Data Sheets E 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer E M EBC Description C S C R 5 0 Read and write accesses both assert EBO 1 Chip Select Register 5 a Address 0020 1014 1 only write accesses can assert Reset uuuu Read Write WEN Description DSZ1 DSZO Description 0 The EBO 1 signals are negated 0 0 8 bit port on D 8 15 pins normally 0 1 8 bit port on D O 7 pins 1 The EBO 1 signals are negated half 1 0 16 bit port on D 0 15 pins a clock cycle earlier on write accesses 1 1 Reserved OEA Description e SP Description 0 The OE signal is negated normally A 0 User mode
154. is 0 Deactivate chip select Bit 3 activated or deactivated between transfers When the CONT 1 Keep chip select active bit is set the chip select line continues to be activated between the transfer of the present queue entry and the next one When the CONT bit is cleared the chip select line is deactivated after the transfer of the present queue entry PCS 2 0 Peripheral Chip Select Field Determines the action to be Bits 2 0 taken at the end of the current queue entry transfer PCS 2 0 QSPI Action SPICn Activated The specified chip select line is asserted 000 SPICO Activated NOP No SPICS line activated At the end of the current 001 SPIC1 Activated transfer the QSPI deasserts the SPICS lines and waits for a 010 SPIC2 Activated new transfer trigger to resume operation The queue pointer is set to point to the next queue entry 011 SPIC3 Activated 1 PIC4 Activat EOTIE End of Transfer interrupt enabled The value of the 90 SEIT Aaly PCS field from the previous queue entry determines the 101 NOP SPICS line asserted for this transfer At the end of the current transfer the QSPI asserts the associated EOT flag in the 110 EOTIE SPSR and generates an interrupt to the MCU 111 EOQ EOQ End of Queue The QSPI completes the transfer of the 1 All other bits in the current queue entry clears the QA and QX bits of the current control halfword are queue and processes the next active queue with the highest disregarded priority If the LE b
155. is generated if the TCIE bit in BBPCRB is set Setting the RCE bit in BBPCRB enables the receive frame counter and loads it with the value in the BBP Receive Counter Modulus Register BBPRMR The counter is decremented by receive frame sync When the counter rolls over it is again loaded with BBPRMR and an interrupt is generated if the RCIE bit in BBPCRB is set Note Although these counters are technically not involved in BBP operation the BBP must be enabled by setting the PEN bit and at least one of the PC 5 0 bits in the BBP Port Control Register BBPPCR to enable the counters Motorola Serial Audio and Baseband Ports 14 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Interrupts 14 8 Interrupts Table 14 4 presents a summary of the possible interrupts the DSP can generate for each port ordered from highest to lowest priority assuming they are all assigned the same interrupt priority level along with their corresponding status and interrupt enable bits if any Table 14 4 SAP and BBP Interrupts Interrupt SAPCRB Interrupt SAPSR Status Bit Enable Bit SAP Receive Data with Overrun Error REIE ROE SAP Receive Data RIE RDF SAP Receive Last Slot RLIE SAP Transmit Data with Underrun Error TEIE TUE SAP Transmit Last Slot TLIE SAP Transmit Data TIE TDE SAP Timer Counter Rollover TCIE BBPCRB Interrupt BBPSR Status Bit
156. location may contain corrupt data Writing to MCVR Ensure that the MC bit in the MCVR is cleared before writing Setting the DWS bit in the MSR Ensure DWS is cleared before setting it PT timer DSP interrupt If the MSIR bit in the MSR is set when the protocol timer issues a dsp_int event i e a previous DSP interrupt event has not been serviced the second interrupt request is lost Entering MCU STOP mode Verify that the MEP bit in the MSR is clear MDI reset Before setting the MDIR bit in the MCR or DHR MCR bit 7 do the following 1 Disable the DSP Protocol Timer interrupt by clearing the DSIE bit in the PT Interrupt Enable Register PTIER 2 Verify that the DWS bit in the MSR is cleared to ensure that the DSP has serviced the last wake up from STOP 3 Verify that the DTIC bit in the DSR is cleared to ensure that there are no outstanding protocol timer interrupt requests 4 Poll the MSMP bit in the MSR until it is cleared to ensure all shared memory writes occur In addition before setting MDIR do the following 1 Verify that the DSP side is not engaged in MDI activity e g by issuing NMI 2 Check that the DPM bit in the MSR is cleared indicating that DSP is not in STOP mode Hardware will ignore the MDIR bit if DSP is in STOP mode After asserting MDIR delay at least one instruction time before writing to an MDI register to ensure it is not overwritten by reset After any MDI reset
157. maskable Me Description 1 Command Interrupt is 0 No interrupt issued non maskable Sets MCP bit in DSR 15 13 11 10 9 8 7 6 5 4 3 2 1 l 0 MC Reserved MCV6 MCV5 MCV4 MCV3 MCV4 MCV1 MCVO MNMI Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer M C U M DI MGIP1 Description 0 No interrupt pending M S R 1 MCU General Interrupt 1 pending MCU Side Status Register MTIR Description Address 0020_2FF6 Reset 3080 0 No interrupt pending Read Write 1 Protocol Timer DSP Interrupt pending MGIPO Description 0 No interrupt pending DWS Description 1 MCU General Interrupt O pending 0 No interrupt pending 1 IRQC asserted to awaken DSP from STOP mode MTE1 Description 0 MTR1 has data DRS Description i MTR1 is empty 0 DSP is not in RESET state 1 DSP currently in RESET state MTEO Description 0 MTRO has data MSMP Description 1 MTRO is empty 0 No memory access pending 1 Shared memory access pending MRF1 Description 0 MRR1 is empty DPM Description 1 MRR1 has data 0 DSP is in Normal mode 1 DSP is in STOP mod
158. mode due to a debug request or as the result of meeting a breakpoint condition it asserts DSP_DE as an output signal for three clock cycles to acknowledge that it has entered debug mode When this signal is enabled the primary DSP DE signal is disabled Note Motorola Signal Connection Description For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keypad Port Table 2 11 Keypad Port Signals Continued Signal Name Type Reset State Signal Description Normal MUX CTL driven low ROW7 Input or Input Row Sense 7 This signal functions as a keypad row sense Output SCKA Input Audio Codec Serial Clock alternate This signal provides the serial bit rate clock for the serial audio codec port In synchronous mode the signal provides the clock input or output for both the transmitter and receiver In asynchronous mode the signal provides the clock for the transmitter only Note When this signal is used as SCKA the primary SCKA signal is disabled See Table 2 15 on page 2 16 RI Output Ring Indicator This signal can be used as the RI output for the serial data port See Table 2 12 on page 2 13 Note Programming of these functions is done through the general port control register and the SAP control register Alternate MUX CTL driven high TCK Input Input Test Clock alternate This signal provides the TCK input for th
159. multiple up to 32 time slots per frame according to the DC 4 0 bits but data is transferred and received only in the first time slot Thus in normal mode DC 4 0 effectively determine the word transfer rate 14 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TDM Options 14 3 2 2 Network Mode Network mode is typically used in TDM systems employing multiple devices Two to 32 time slots can be selected with the DC 4 0 bits and data is transferred and received in each time slot 14 3 2 3 On Demand Mode On demand mode is selected by adjusting the MOD bit for network mode and clearing DC 4 0 In this mode frame sync is not periodic but is generated only when data is available to transmit The TFS must be internal output and the RFS must be external input Therefore either synchronous or asynchronous mode can be used in simplex operation but full duplex operation requires asynchronous mode On demand mode is useful for interfacing to a codec that requires a continuous clock 14 3 3 Frame Sync The frame sync frequency for each port is Frame sync frequency bit clock frequency WL x DC 1 where bit clock the transmit or receive bit clock frequency derived in Section 14 2 2 on page 14 4 WL Binary value of the word length 8 12 or 16 as specified by the WL 1 0 bits in SAPCRA or BBPCRA DC Binary value of the DC 4 0 bits in SA
160. of these bits contains data for the corresponding SCP pin if it Bits 4 0 is configured as GPIO Writes to these bits are stored in an internal latch and driven on any port pin configured as an output Reads of these bits return the value sensed on input pins and the latched data driven on outputs 12 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 13 Keypad Port The keypad port KP is a 16 bit peripheral designed to ease the software burden of scanning a keypad matrix It works with any sized matrix up to eight rows by eight columns With appropriate software support keypad logic can detect debounce and decode one or two keys pressed simultaneously A key press generates an interrupt that can bring the MCU out of low power modes The KP is designed for a keypad matrix that shorts intersecting row and column lines when a key is depressed It is not intended for use with other switch configurations 13 1 Keypad Operation This section describes KP pin configuration software polling required to determine a valid keypress low power operation and noise suppression circuitry Figure 13 1 is a block diagram of the keypad port pull up Data Direction Data Control KDR 15 8 KDDR 15
161. or equal to MCU CLK 4 1 2 DSP CLK The DSP clock input DSP REF is selected from either CKIL or buffered CKIH by the DCS bit in the CKCTL DSP REF drives the DSP clock generator either directly or through a PLL according to the PEN bit in PLL Control Register 1 PCTL 1 The clock generator divides its input by two and puts out the core DSP_CLK signal and a two phase clock to drive peripherals DSP peripherals can also use CKIH as an input Figure 4 2 is a block diagram of the DSP clock system CLKGEN DSP REF Predivider PLL Loop Low Power Frequency Divider Multiplication PLL ae MF Out MF Ip Fext MF 2 u Fext MF 2 Clock PDF DSP_REF PDF 1 to 128 MF 1 to 4096 DF 20 to 27 PVCC PGND PVCC PCAP Figure 4 2 DSP PLL and Clock Generator Motorola Core Operation and Configuration 4 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generation When the PLL is enabled its input is divided by a predivide factor PD bits in PCTL1 and PCTLO and another divide factor DF bits in PCTL1 which is intended to decrease the DSP_CLK frequency in low power modes The DF bits can be adjusted without losing PLL lock The PLL also multiplies the input by a factor determined by the MF bits in PCTLO The PLL output frequency is PLLOUT DSP_REF x MF x 2 PD x DF and the clock generator output frequency is DSP_CLK DSP_REF x MF PD x DF The PLL can be bypass
162. parallel shifter with a 40 bit input and a 40 bit output 1 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview e A bit field unit BFU with a 40 bit barrel shifter e Two data bus shifter limiter circuits The data ALU registers can be read or written over the X data bus XDB and the Y data bus YDB as 16 or 32 bit operands The source operands for the data ALU which can be 16 32 or 40 bits always originate from data ALU registers The results of all data ALU operations are stored in an accumulator A seven stage pipeline executes one instruction per clock cycle The destination of every arithmetic operation can be used as a source operand for the immediate following operation without penalty The MAC unit comprises the main arithmetic processing unit of the DSP core and performs all of the calculations on data operands For arithmetic instructions the unit accepts as many as three input operands and outputs one 40 bit result formatted as Extension Most Significant Product Least Significant Product EXT MSP LSP The multiplier executes 16 bit x 16 bit parallel fractional multiplies between two s complement signed unsigned or mixed operands The 32 bit product is right justified and added to the 40 bit contents of either the A or B accumulator A 40 bit result can be stored as a 16 bit operand The LSP can either be tr
163. ptpdr ptpd 1 prot ptpdr ptpd 2 prot ptpdr ptpd 3 prot ptpdr ptpd 4 prot ptpdr ptpd 5 prot ptpdr ptpd 6 prot ptpdr ptpd 7 Select the direction of pin Select the direction of pin Select the direction of pin Select the direction of pin Select the direction of pin Select the direction of pin Select the direction of pin Select the direction of pin 0x0 Port D Data pin 0 0x1 Port D Data pin 1 0x2 Port D Data pin 2 0x3 Port D Data pin 3 Ox4 Port D Data pin 4 0x5 Port D Data pin 5 0x6 Port D Data pin 6 0x7 Port D Data pin 7 0x0 Port D Data pin 0 0x1 Port D Data pin 1 0x2 Port D Data pin 2 0x3 Port D Data pin 3 0x4 Port D Data pin 4 0x5 Port D Data pin 5 0x6 Port D Data pin 6 0x7 Port D Data pin 7 bits of the Frame Table Pointer FTPTR 0x0 Frame table pointer bit0 0x1 Frame table pointer bitl 0x2 Frame table pointer bit2 0x3 Frame table pointer bit3 Ox4 Frame table pointer bit4 0x5 Frame table pointer bit5 0x6 Frame table pointer bit6 prot ftptr ftptr 0 prot ftptr ftptr 1 prot ftptr ftptr 2 prot ftptr ftptr 3 prot ftptr ftptr 4 prot ftptr ftptr 5 prot ftptr ftptr 6 bits of the Receive Transmit macro Table Pointer RTPTR old names B 8 DSP56652 User s Manual For More Information On This Product Go to www freescale com UUUUUUUU Motorola Motorola Freescale Semiconductor Inc prot rtptr rxptr 0 prot rtptr rxp
164. requires that the frequency of MCU_CLK which drives the MCU peripherals be greater than or equal to CKIL Therefore when CKIL drives the MCU clock the division factor should be 1 1 e MCS 2 0 in the CKCTL register are cleared see page 4 5 Figure 9 2 is a timing diagram of PIT operation using the PITMR to reload the counter TU UU UU UU OSC 4 PITCNT E 0002 0001 0000 0005 0004 0003 PITMR 0005 Figure 9 2 PIT Timing Using the PITMR 9 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Periodic Interrupt Timer Setting the OVW bit in the ITCSR enables the counter to be updated at any time A write to the PITMR register simultaneously writes the same value to PITCNT if OVW is set The PIT is not affected by the low power modes It continues to operate in STOP DOZE and WAIT modes PIT operation can be frozen when the MCU enters Debug mode if the DBG bit in the PITCSR is set When Debug mode is exited the timer resumes operation from its state prior to entering Debug mode If the DBG bit is cleared the PIT continues to run in Debug mode Note The PIT has no enable control bit It is always running except in debug mode 9 1 2 PIT Registers The following is a bit description of the three PIT registers PITCSR PIT Control Status Register 0020_7000 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 DBG OVW ITIE ITIF RLD RESET 0
165. response Message oooooooommcom o A 8 Format of memory_check request Message ooooooooomoooo o A 9 Format of memory_check request Message 000 A 10 Format of start_application request Message 20 A 11 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure A 10 Format of invalid_opcode response Message 0oo ooooommooo A 12 Figure A 11 Mapping of DSP Program Memory words to MDI message words A 13 Motorola List of Figures xiii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc xiv DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 2 12 Table 2 13 Table 2 14 Table 2 15 Table 2 16 Table 2 17 Table 2 18 Table 2 19 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Motorola DSP56652 Signal Functional Group Allocations 2 1 POWELL A R s 2 3 Ground 4 4 aye eor a cs e a rp pe qp DEE ale DE 2 4 PEL and Clock Stenals ek 03 d ds tret Wate er autos eut ate ee Sate geht eat 2 5 Address and Data Buses ea oa vede o ds bes 2 6 Bus Control val ER
166. table entries are subject to the following restrictions 1 A macro cannot invoke another macro i e macros cannot be nested 2 Commands that affect frame table operation which include all end_of_frame commands and the table_change command are for frame tables only 3 The last entry in a macro must be the end_of_macro command 10 2 2 1 Delay Event The delay event invokes a programmed delay of a specified number of frames and time intervals before the next command in the macro is executed This event is only valid in macros and cannot appear in the frame tables There are actually eight event codes for invoking the receive macro and eight for the transmit macro Each of these event codes specifies a different entry in the receive or transmit delay table to be used when the macro calls a delay event Each delay table entry contains a 7 bit frame delay FD and a 14 bit time interval delay TID as shown in Figure 10 5 15 6 0 Offset MEE 0 Byte Offset 0 N Byte Offset 1 15 13 0 ae TID 2 Byte Offset 2 A Byte Offset 3 Figure 10 5 Delay Table Entry When a receive macro is called the delay index 0 through 7 determined by the particular event code used for the call is loaded into the Receive Delay Pointer RDPTR field in the Delay Table Pointer DTPTR This number represents the offset from the Receive Delay Table Base Address RDBA encoded in the DTPTR at initialization Thus DTPTR points to a specific numb
167. the data has been read MDI Messaging Unit Registers 15 14 13 10 9 0 I MCU address DSP address i MCU_MDI_BASE 2 offset MDI Shared Memory DSP MDI BASE offset I memory_read response 2 Pul return code 02success 1 invalid memory space specified of DSP words read unused dest_address_offset source address MCU_MDI_BASE DSP_MDI_BASE 2 dest address offset dest address offset Lo Mw e e e e Se ee a aA Figure A 6 Format of memory_read response Message A 2 2 5 memory_check request memory check request is a long message from the MCU to the DSP requesting a test of the DSP 0 5k program RAM A 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot Note Although this protocol supports provisions to test all of the memory spaces the bootloader only implements testing of the 0 5k program RAM space The format of this message is shown in Figure A 7 The entry following the opcode in shared memory contains two fields The upper three bits specify the RAM space to be tested always 100 for the bootloader and the lower ten bits specify the MDI address the at which DSP stores its long reply message Normally the return address offset points to the next word so that return_address_offset mdi_offset 2 However the protocol allows for the long reply message to be located
168. the next receive macro Bits 6 0 table entry FTBAR Frame Table Base Address Register 0020 3820 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O FTBA1 6 0 FTBAO 6 0 RESET 0 0 Table 10 20 FTBAR Description Name Description FTBA1 6 0 Frame Table 1 Base Address 6 0 These bits specify the offset from the beginning of PT RAM Bits 14 8 0020_3000 of the first entry in Frame Table 1 They should be initialized before the PT is enabled FTBAO 6 0 Frame Table 0 Base Address 6 0 These bits specify the offset from the beginning of PT RAM Bits 6 0 of the first entry in Frame Table 0 They should be initialized before the PT is enabled 10 24 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers MTBAR Macro Table Base Address Register 0020_3822 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 TxBA1 6 0 RxBAO 6 0 RESET 0 0 Table 10 21 MTBAR Description Name Description TxBA1 6 0 Transmit Macro Base Address 6 0 These bits specify the offset from the beginning of PT RAM Bits 14 8 of the first entry in the transmit macro They should be initialized before the first transmit macro is activated RxBAO 6 0 Receive Macro Base Address 6 0 These bits specify the offset from the beginning of PT RAM Bits 6 0 of the first entr
169. to the chip package to connect between the Voca lines and the GNDg lines Motorola Signal Connection Description 2 3 For More Information On This Product Go to www freescale com Ground 2 2 Ground Freescale Semiconductor Inc The DSP36652 ground pins are listed in Table 2 3 Table 2 3 Ground Ground Signals Description GND Address bus ground These lines connect system ground to the address bus GND SIM ground These lines connect system ground to the smart card bus GNDc Bus control ground This line connects ground to the bus control logic GNDp Data bus ground These lines connect system ground to the data bus GNDp Audio codec port ground These lines connect system ground to the audio codec port GNDF Clock output ground This line supplies a quiet ground connection for the clock output drivers GNDa GPIO ground These lines connect system ground to GPIO keypad data port interrupts STO and JTAG I O drivers GNDy Baseband codec and timer ground These lines connect system ground to the baseband codec and timer I O drivers GND Emulation port ground These lines connect system ground to the emulation port I O drivers GNDp Analog PLL circuit ground This line supplies a dedicated quiet ground connection for the analog PLL circuits GNDp Analog PLL circuit ground This line supplies a dedicated quiet ground connection for the analog PLL circui
170. unsigned short dsp program i write syn message 1 mdimem0 1234 wait for confirm message 1 while mdimeml Sabcd write sync message 2 mdimem0 5678 Motorola DSP56652 DSP Bootloader A 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode C Messaging Unit Boot wait for confirm message 2 while mdimeml Scdef A 4 Mode C Messaging Unit Boot The messing unit memory boot mode can also be used if all that is required is to fill the lower 0 5k DSP program RAM and begin execution at DSP program address P 0000 This mode uses the MDI messaging unit registers so there is no need for additional synchronization logic In this mode the MCU should write a maximum of 511 DSP program words one at a time to the two messaging unit registers The most significant portion of each word should be written to MDI RO and the least significant portion to MDI RI The DSP reads MDI RO first so the MCU should write MDI RO first Also the MCU should poll the transmit empty bits in the MDI status register to ensure that the DSP has read each register before a new value is written Example A 2 is pseudo C program of a boot using the MDI messaging unit Example A 3 Messaging Unit Boot unsigned short mtr0 unsigned short MDI MTRO unsigned short mtrl unsigned short MDI MIRI volatile unsigned short msr unsigned short MDI MSR write
171. up Resistor Control KDDR 15 8 KPCR 15 8 Pin Function pull up Resistors 0 X Input Enabled 1 0 Output totem pole Disabled 1 1 Output open drain Enabled 13 1 1 2 Row Pins Row pins intended for keypad operation must be configured as inputs by clearing the corresponding KRD bits in the KDDR and for keypad operation rather than GPIO by setting the corresponding KRE bits in the KPCR When pulled low each row pin configured for keypad operation sets the KPKD bit in the Keypad Status Register KPSR and generates an interrupt Row pins configured as GPIO do not set the status flag or generate an interrupt when they are pulled low The KPKD bit is cleared by reading the KPSR then writing the KPKD bit with 1 A discrete switch can be connected to any row input pin that is not part of the keypad matrix The second terminal of the discrete switch is connected to ground If the pin is configured as an input and for keypad operation hardware detects closure of the switch and generates an interrupt if the corresponding row pin is configured for keypad operation Care should be taken not to configure a row pin for both KP operation and as an output In this configuration a keypad interrupt is generated if the associated data bit in the Keypad Data Register KPDR is written with zero pulling the pin low 13 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale
172. 0 move b0 x rl return code success fail move n0 x r1 words move x0 b old memory space amp MDI address add 5 b new MDI address is offset by 5 move b1 x 11 memory space amp MDI address move r0 x r1 DSP source address cmp mem x a jeq mem read x cmp mem_y a jeq mem read y only option left is mem read p jmp mem read p mem read x do nO loop move x r0 x0 move x0 x rl loop jmp lt mem read return Motorola DSP56652 DSP Bootloader A 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program mem read y do n0 loop move y r0 x0 move x0 x rl loop jmp mem read return mem read p do n0 loop movep p r0 x lt lt BPMRG movep X BPMRH X 11 store p data in movep X BPMRL x rl big endian format _loop jmp lt mem read return mem read fail write unsuccessful MDI header info move fail b0 move b0 x 11 return code fail mem read return form long message return same for both success and failure move nl a MDI address for long or long_header a _wait jclr DTEO x DSR wait don t clobber a previous message movep al x DTRO rts A A A A A A A A A NA end of memory read request start 512pram memory check request e Ne Ne 99 e A A rrr memory check retrieve memory type and address move x r0 x1 move xl al and S03FF a save only lower 10 bits offset move al nl s
173. 0 9 8 7 6 5 4 3 2 1 Bit O SCTCIE SCFNIE SCFFIE SCREIE SMSCIE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note In addition to the individual interrupt enable bits in the SCPIER the following bits must also be set in order to generate the respective interrupts see page 7 7 SIM Sense Change either ESMPD in the NIER or EFSMPD in the FIER All other interrupts either ESCP in the NIER or EFSCP in the FIER Table 12 4 SCPIER Description Name Description Settings SCTCIE SCP Transmit Complete Interrupt Enable Allows an interrupt O Interrupt disabled default Bit 4 to be generated when the SCTC bit in the SCPSR is set 1 Interrupt enabled SCFNIE SCP Receive FIFO Not Empty Interrupt Enable Allows an Bit 3 interrupt to be generated when the SCFN bit in the SCPSR is set SCFFIE SCP Receive FIFO Full Interrupt Enable Allows an interrupt to Bit 2 be generated when the SCFF bit in the SCPSR is set SCREIE SCP Receive Error Interrupt Enable Allows an interrupt to be Bit 1 generated when the SCPE SCFE or SCOE bit in the SCPSR is set SMSCIE SIM SENSE Change Interrupt Enable Allows an interrupt to be Bit O generated when the SMSC bit in the SCPSR is set Motorola Smart Card Port 12 13 For More Information On This Product Go to www freescale com SCP Registers Freescale Semiconductor Inc
174. 0 IRQ B enabled IPL 1 Level sensitive 0 1 1 IRQ B enabled IPL 2 Level sensitive 1 0 0 IRQ B disabled no IPL Edge sensitive 1 0 1 IRQ B enabled IPL 0 Edge sensitive 1 1 0 IRQ B enabled IPL 1 Edge sensitive 1 1 1 IRQ B enabled IPL 2 Edge sensitive ICTM ICPL1 ICPLO IRQ C Mode Trigger Mode 0 0 0 IRQ C disabled no IPL Level sensitive 0 0 1 IRQ C enabled IPL 0 Level sensitive 0 1 0 IRQ C enabled IPL 1 Level sensitive 0 1 1 IRQ C enabled IPL 2 Level sensitive 1 0 0 IRQ C disabled no IPL Edge sensitive 1 0 1 IRQ C enabled IPL 0 Edge sensitive 1 1 0 IRQ C enabled IPL 1 Edge sensitive 1 1 1 IRQ C enabled IPL 2 Edge sensitive IDTM IDPL1 IDPLO IRQ D Mode Trigger Mode 0 0 0 IRQ D disabled no IPL Level sensitive 0 0 1 IRQ D enabled IPL 0 Level sensitive 0 1 0 IRQ D enabled IPL 1 Level sensitive 0 1 1 IRQ D enabled IPL 2 Level sensitive 1 0 0 IRQ D disabled no IPL Edge sensitive 1 0 1 IRQ D enabled IPL 0 Edge sensitive 1 1 0 IRQ D enabled IPL 1 Edge sensitive 1 1 1 IRQ D enabled IPL 2 Edge sensitive Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 37 Freescale Semiconductor Inc
175. 00 0100 SCK MCU CLK 10 TII 100 1011 SCK MCU CLK 96 CPHA1 Description m 111 1110 SCK MCU CLK 504 0 Data changes on first SCK transition 111_1111 SCK MCU_CLK 1 1 Data latches on first SCK transition 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPHA1 CKPOL1 LSBF1 DATR12 DATR11 DATR10 CSCKD12 0SCKD11 CSCKD10 SCKDF16 SCKDF15 SCKDF14 SCKDF13SCKDF12 SCKDF11SCKDF10 E 44 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Application Freescale Semiconductor Inc Date Programmer QSPI SCCR2 Serial Channel Control Register 2 Address 0020_5F16 Reset 0000 CSCKDF2 0 2 Assertion to Activation Delay 000 1 SCK cycle delay 001 2 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay 101 32 SCK cycles delay 110 64 SCK cycles delay 111 128 SCK cycles delay SCK MCU_CLK 2 3 SCKFD2 6 1 SCKDF2 0 5 1 All values for SCKDF2 0 6 are valid Sample values are shown SCKDF2 0 6 Description 000_0000 SCK MCU_CLK 2 000_0001 SCK MCU_CLK 4 000_0111 SCK MCU_CLK 16 100_0000 SCK MCU_CLK 8 000_0100 SCK MCU_CLK 10 100_1011 SCK MCU_CLK 96 111_1110 SCK MCU_CLK 504 Read Write DATR2 0 2 Delay After T
176. 0000 through Oxffffffff is reserved Motorola Equates and Header Files B 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Equates MCU DSP Interface MDI equates general definitions equ mdi registers base address 0x00202ff0 equ mdi memory base address 0x00202000 registers of the messaging unit equ mdi mcvr 0x2 MCU side Command Vector Register equ mdi mcr Ox4 MCU side Control Register equ mdi msr Ox6 MCU side Status Register equ mdi mtrl 0x8 MCU side Transmit Register 1 equ mdi mtr0 Oxa MCU side Transmit Register 0 equ mdi mri Oxc MCU side Recieve Register 1 equ mdi mrr0 Oxe MCU side Receive Register 0 bits of the MCU side Cammand Vector register MCVR equ mdi mvr mmi 0x0 MCU command Non Maskable Interrupt equ mdi mcvr mc 0x8 MCU Cammand active bit bits of the MCU side Control Register MCR equ mdi mcr mdf0 0x0 MCU to DSP Flag 0 equ mdi mcr mdfl 0x1 MCU to DSP Flag 1 equ mdi mcr mdf2 Ox2 MCU to DSP Flag 2 equ mdi mcr mdir 0x6 MDI software Reset equ mdi mcr dhr 0x7 DSP Hardware Reset equ mdi mcr mgiel Oxa MCU General Interrupt 0 enable equ mdi mcr mgie0 Oxb MCU General Interrupt 1 enable equ mdi mcr mtiel 0xc MCU transmit Interrupt 1 enable equ mdi mcr mtie0 0xd MCU transmit Interrupt 0 enable equ mdi mcr mriel Oxe MCU Receive Interrupt 1 enable
177. 020_380C Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTIMVI3 CTIMV12 CTIMV11 CTIMV10 CTIMV9 CTIMV8 CTIMV7 CTIMV6 CTIMV5 CTIMV4 CTIMV3 CTIMV2 CTIMV1 CTIMVO 0 0 C FC Channel Frame Count Channel Frame Counter Value Address 0020 380E Reset 0000 Read Write 15 14 18 12 11 10 8 7 6 5 4 3 2 1 0 CFCV8 CFCV7 CFCV6 CFCV5 CFCV4 CFCV3 CFCV2 CFCV1 CFCVO 0 0 0 0 0 0 0 0 C FM R Channel Frame Modulus Channel Frame Modulus Register Value Address 0020_3810 Reset 0000 Read Write gt 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Reserved E 62 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer Protocol Timer RSC Reference Slot Counter Address 0020_3812 Reset 0000 Read Write Reference Slot Count Value 7 6 5 4 3 2 1 0 RSCV7 RSCV6 RSCV5 RSCV4 RSCV3 RSCV2 RSCV1 RSCVO 0 0 RSMR Reference Slot Modulus Register Address 0020_3814 Reset 0000 Read Write Reference Slot Modulus Value 7 6 5 4 3 2 1 0 RSMV7 RSMV6 RSMV5 RSMV4 Reserved RSMV3 RSMV2 RSMV1 RSMVO Motorola Programmer s Data Sheets For Mor
178. 0x8 0x9 Oxa Receive macro base address bit 3 Receive macro base address bit 4 Receive macro base address bit 5 Receive macro base address bit 6 Transmit macro base Transmit macro base Transmit macro base Oxb Transmit macro base Oxc Transmit macro base Oxd Transmit macro base Oxe Transmit macro base address bit address bit address bit address bit address bit address bit address bit DO i C NO r2 CO bits of the Macro Table Base Address Register MIBAR NEW NAMES 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x8 0x9 Oxa Receive Receive Receive Receive Receive Receive Receive Transmit macro base Transmit macro base Transmit macro base Oxb Transmit macro base Oxc Transmit macro base Oxd Transmit macro base Oxe Transmit macro base bits of the Delay Table Pointer DTPTR Receive delay pointer bit 0 Receive delay pointer bit 1 Receive delay pointer bit 2 prot dtptr rdptr 0 prot dtptr rdptr 1 prot dtptr rdptr 2 prot dtptr rdba 0 prot dtptr rdba 1 prot dtptr rdba 2 prot dtptr rdba 3 prot dtptr tdptr 0 prot dtptr tdptr 1 prot dtptr tdptr 2 prot dtptr tdba 0 prot dtptr tdba 1 prot dtptr tdba 2 prot dtptr tdba 3 UART equates B 10 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x8 0x9 Oxa macro base macro base macro base macro base macro base macro base macro base address bit address bit address bit
179. 1 amp 140 BC 6 SPICS 3 bidir X 139 1 2 num cell port func safe ccell dis rslt 141 BC 1 control 1 amp 142 BC 6 SPICS 2 bidir X 141 1 Z 143 BC 1 control 1 amp 144 BC 6 SPICS 1 bidir X 143 1 Z 145 BC 1 control 1 amp 146 BC 6 SPICS 0 bidir X 145 1 Z 147 BC 1 control 1 amp 148 BC 6 SCK bidir X 147 1 Z 149 BC 1 control 1 amp 150 BC 6 MISO bidir X 149 1 Z 151 BC 1 control 1 amp 152 BC 6 MOSI bidir X 151 1 Z 153 BC 1 DSP_IR B input X amp 154 BC 1 control 1 amp 155 BC 6 SCKB bidir X 154 1 Z 156 BC 1 control 1 amp 157 BC 6 SCB 0 bidir X 156 1 2Z 158 BC 1 control 1 amp 159 BC 6 SCB 1 bidir X 158 1 2Z num cell port func safe ccell dis rslt 160 BC 1 control 1 amp 161 BC 6 SCB 2 bidir X 160 1 2Z 162 BC 1 control 1 amp 163 BC 6 SRDB bidir X 162 1 2Z 164 BC 1 control 1 amp 165 BC 6 STDB bidir X 164 1 Z 166 BC 1 control 1 amp 167 BC 6 SCA 2 bidir X 166 1 2Z 168 BC 1 control 1 amp 169 BC 6 SCA 1 bidir X 168 1 Z 170 BC 1 control 1 amp 171 BC 6 SCA 0 bidir X 170 1 Z 172 BC 1 control 1 amp 173 BC 6 SCKA bidir X 172 1 Z 174 BC 1
180. 10 0000 rrrr RX copied into C bit before shifting ASRI ASRI RX IMM5 0011 101i iiii rrrr Unaffected BCLRI BCLRI RX IMM5 0011 000i iiii rrrr Unaffected BF BF LABEL 1110 1ddd dddd dddd Unaffected BGENI BGENI RX IMM5 0011 0010 0111 rrrr Unaffected BGENR BGENR RX RY 0001 0011 ssss rrrr Unaffected BKPT BKPT 0000 0000 0000 0000 n a BMASKI BMASKI RX IMM5 0010 0011 0000 rrrr Unaffected BR BR LABEL 1111 Oddd dddd dddd Unaffected BREV BREV RX 0000 0000 1111 rrrr Unaffected BSETI BSETI RX IMM5 0011 010i iiii rrrr Unaffected BSR BSR LABEL 1111 1ddd dddd dddd Unaffected BT BT LABEL 1110 Oddd dddd dddd Unaffected BTSTI BTSTI RX IMM5 0011 011i iiii rrrr Set to value of RX pointed to by IMM5 CLRF CLRF RX 0000 0001 1101 rrrr Unaffected CLRT CLRT RX 0000 0001 1100 rrrr Unaffected CMPHS CMPHS RX RY 0000 1100 ssss rrrr Set as a result of comparison CMPLT CMPLT RX RY 0000 1101 ssss rrrr Set as a result of comparison CMPLTI CMPLTI RX OIMM5 0010 001i iiii rrrr Set as a result of comparison CMPNE CMPNE RX RY 0000 1111 ssss rrrr Set as a result of comparison CMPNEI CMPNEI RX IMM5 0010 101i iiii rrrr Set as a result of comparison DECF DECF RX 0000 0000 1001 rrrr Unaffected DECGT DECGT RX 0000 0001 1010 rrrr Set if RX gt 0 else bit is cleared DECLT DECLT RX 0000 0001 1000 rrrr Set if RX lt 0 else bit is cleared DECNE DECNE RX 0000 0001 1011 rrrr Set if RX 0 else bit is cleared DECT DECT RX 0000 0000 1000 rrrr Unaffected D 2 DSP56652
181. 10 26 Suggested GPIO Pins for UART SignalS oo ooo oomoooo o 11 4 UART Low Power Mode Operation o oooooccooocoooooom o 11 7 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Table 11 3 Table 11 4 Table 11 5 Table 11 6 Table 11 7 Table 11 8 Table 11 9 Table 11 10 Table 11 11 Table 11 12 Table 11 13 Table 12 1 Table 12 2 Table 12 3 Table 12 4 Table 12 5 Table 12 6 Table 12 7 Table 12 8 Table 13 1 Table 13 2 Table 13 3 Table 13 4 Table 13 5 Table 13 6 Table 14 1 Table 14 2 Table 14 3 Table 14 4 Table 14 5 Table 14 6 Motorola Freescale Semiconductor Inc UART Register Summary cms AR Ros URX Description UTX Description UCRI Description UCR2 Description assed ok totus AAA A qus UBRCGH Description s tab a EO dis USRSDeSCEDUOH a A eee oe A eed be RES UFS Description 235 ves A AERP Res e eee eee DA UPCR Description UDDR Description UPDR Description SCP Register Summary SCPCR Description SCACR Descrip ias ex e E E ea SCPIER Descrip ta a soe e e E RASA SCPSR Description SCPDER DOSCPDpLIOI es i ee hr dt AA SCP Pin GPIO Bit Assignments SCPPCR Description Keypad Port pull up Resistor Control Keypad Port Register Summary KPCR Description Generic Description KDDR Description KPDR Description SAP and BBP PINS daras 4 NO n S POR Fi e d att uk SAP BBP Clock Sources Frame Configuration 10 252 2 9 30 ed A ib
182. 12 equ tpw tcr 0x14 old name equ tpwm tcnt 0x14 NEW NAME equ tpm wer 0x16 old name equ tpm pwl 0x16 NEW NAME equ tpm pwonr 0x18 old name equ tpm pwent 0x18 NEW NAME tpwer bits equ tpwm tpwcr pwdbg 11 TPWCR pwdbg bit equ tpwm tpwcr tdbg 10 TPWCR tdbg bit equ tpwm tpwcr pwd 9 TPWCR pwd bit equ tpwm tpwcr pwe 8 TPWCR pwe bit B 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc tpm tpwcr td t m tpwcr te tgm tpwcr pspw2 tpm tpwcr pspwl tgm tpwcr pspwO tpm tpwcr pst2 tpwm tpwcr pstl tpm tpwcr pst tpwm tpumr pwe tpm tpwmr pwp tpwm_tpwsr_pwo tpwm_tpwsr_tov tpwm_tpwsr_pwf tpwn tpwsr if2 tgm tpwsr ifl tpm tpwsr of4 tpm tpwsr of3 tpm tpwsr ofl tpm twir pwoie tpm twir tovie tpm twir pwfie tom twir if2ie tom twir iflie tpwm_twir of4ie tum twir of3ie tpm twir oflie TPWCR td bit TPWCR te bit TPWCR pspw2 bit TPWCR pspwl bit TPWCR pspwO bit TPWCR pst2 bit TPWCR pstl bit TPWCR pst0 bit OrRNWBUD 14 TPWMR we bit 13 TPWMR pwp bit 12 TPWMR fo4 bit 11 TPWMR fo3 bit 10 TPWMR fol bit TPWMR im21 bit TPWMR im20 bit TPWMR imll bit TPWMR iml0 bit TPWMR om41 bit TPWMR om40 bit TPWMR om31 bit TPWMR am30 bit TPWMR oml1 bit TPWMR oml0 bit OPN CQ i U01 J00 0 TPWSR pwo bit TPWSR tov bit TPWSR pwf bit TPWSR i
183. 15 11 1533 25 Pest Modes so 15 11 19323 O A A e ea e 15 11 15 4 MCU TAP Controller o isse oeme norme AES ui nai ii e RR Sq ueg HN 15 12 15 4 1 Entering MCU OnCE Mode via JTAG Control o ooo o o 15 12 15 4 2 Release from Debug Mode for DSP and MCU 15 13 Appendix A DSP56652 DSP Bootloader Al BOO Modes s 2 9 eR dns ESSE ERN ERE RS ERE nur ERE I Ren RR RR A 1 A Mode A Normal MOEBO Eu tae Ree ee EE Eh el a Rk tS A 2 A 2 1 Shortand Lone Messages da ea the eee tee bees wales A 2 Motorola Table of Contents ix For More Information On This Product Go to www freescale com A 2 2 A 2 3 A 2 4 A 3 A 4 AS B 1 B 2 B 3 C 1 52 D 1 D 2 D 3 D 4 D 5 D 6 Freescale Semiconductor Inc Message Descriptions cic ee rl A Bes Chak E NEUE S MU A 4 Comments on Normal Boot Mode Usage ooo oooccooocooocom o A 13 Example of Program Download and Executi0N ooo ooooooo o A 14 Mode B Shared Memory BO0t oooocooccocconcco ees A 15 Mode C Messaging Unit Boots sv 4 dla oh I Nt ly nA A 16 Bootstrap Program sss aiee aneia vete dos a ee IP A Ue Se bob add A 17 Appendix B Equates and Header Files MCU EqUates a er RRS ea Ese RSE OSE RE WERE ERE B 1 MCU Include E162 ERE peu vie nf HENS ROIS B 22 DSP Egu t s a CURRERE eer EHE Ea s bebe pesi nis B 32 Appendix C Boundary Scan Register BSR Bit Definitions ew AR IA A AR C 1 Boundary Scan Description Language
184. 157 SCBO input output data 118 ADDR19 input output data 158 SCB1 control 119 ADDR20 output data 159 SCB1 input output data Motorola Boundary Scan Register C 3 For More Information On This Product Go to www freescale com Boundary Scan Description Language Freescale Semiconductor Inc Table C 1 BSR Bit Definitions Bit Pin Name Pin Type Cell Type Bit Pin Name Pin Type Cell Type 160 SCB2 control 179 PSTAT3 input output data 161 SCB2 input output data 180 PSTAT2 control 162 SRDB control 181 PSTAT2 input output data 163 SRDB input output data 182 PSTAT1 control 164 STDB control 183 PSTAT1 input output data 165 STDB input output data 184 PSTATO control 166 SCA2 control 185 PSTATO input output data 167 SCA2 input output data 186 SIZ1 control 168 SCA1 control 187 SIZ1 input output data 169 SCA1 input output data 188 SIZO control 170 SCAO control 189 SIZO input output data 171 SCAO input output data 190 CTS control 172 SCKA control 191 CTS input output data 173 SCKA input output data 192 RTS control 174 SRDA control 193 RTS input output data 175 SRDA input output data 194 RX control 176 STDA control 195 RX input output data 177 STDA input output data 196 TX control 178 PSTAT3 control 197 TX input output data C 2 Boundary Scan Description Language The following is a listing of the DSP56652 Boundary Sca
185. 2 0x0004 define MSR MEP 0x0010 define MSR DPM 0x0020 define MSR MSMP 0x0040 define MSR_DRS 0x0080 define MSR DWS 0x0100 define MSR MGIPl 0x0400 define MSR MGIP2 0x0800 define MSR MTEl 0x1000 define MSR MTEO 0x2000 define MSR MRFl 0x4000 define MSR MRFO 0x8000 BRRRERRERRRERERERERERERRERER REDCAP Keypad Port KPP example usage struct redcap kppb kppb struct redcap kppb REDCAP MCU KPP B 26 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc MCU Include File kkkkkkkkkkkkkkkkkkkkkkkkkkkk ifdef ASSEM define KPP KPCR 0x0 define KPP_KPSR 0x2 define KPP KDDR 0x4 define KPP KPDR 0x6 else this structure uses halfwords struct redcap kpp unsigned short kpcr keypad control reg volatile unsigned short kpsr keypad status reg unsigned short kddr keypad data dir reg volatile unsigned short kpdr keypad data reg y this structure uses byte addressing struct redcap kppb unsigned char kpcr col keypad control reg cols unsigned char kpcr row keypad control reg rows unsigned char reserved byte not used volatile unsigned char kpsr keypad status reg unsigned char kddr col keypad data dir reg cols unsigned char kddr row keypad data dir reg rows volatile unsigned char kpdr col keypad data reg cols volatile unsigned char kpdr ro
186. 2 1 Bit 0 PWC PWP FO4 FO3 FO1 IM2 1 0 IM1 1 0 OM1 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9 4 TPWMR Description Name Description Settings PWC PWM Control Connects the PWM function to 0 Disconnected default Bit 14 the PWM output pin 1 Connected PWP PWM Pin Polarity Controls the polarity of the 0 Active high polarity default Bit 13 PWM output during the active time of the pulse 1 Active low polarity defined as time between output compare and PWCNT rollover FO4 Forced Output Compare Writing 1 to FOC1 immediately forces the OC1 pin to the output Bit 12 compare state programmed in the associated OM1 1 0 bits The OF1 flag in TPWSR is not affected Setting FOC3 and FOCC4 have no effect because these functions are not pinned out FO3 Each FOC bit is self negating i e always reads 0 Writing 0 to these bits has no effect Bit 11 FO1 Bit 10 IM2 1 0 Input Capture Operating Mode Each pair of 00 Disabled default Bits 9 8 bits determines the input signal edge that triggers 01 Rising edge the associated input compare response 10 Falling edge 1M1 1 0 11 Both edges Bits 7 6 OM1 1 0 These bits determine the OC1 output response 00 Timer disconnected from pin default Bits 1 0 when the compare 1 function is triggered 01 Toggle output 10 Clear output 11 Set output 9 14 DSP56652 User s Manual
187. 2 11 10 9 8 7 6 5 4 3 2 1 Bit O WSR 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register services the watchdog timer and prevents it from timing out To service the timer perform the following steps 1 Write 5555 to the WSR 2 Write SAAAA to the WSR 9 3 GP Timer and PWM This section describes the MCU GP timer and pulse width modulator PWM Although these are separate functions they derive their clocks from a common 8 bit MCU_CLK divider shown in Figure 9 4 They also share several control registers 9 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM MCU_CLK TPWCR PST 0 2 Clock for GP Timer Counter TCNT 8 Bit Divider Clock for PWM Counter PWCNT TPWCR PSPW 0 2 Figure 9 4 GP Timer PWM Clocks 9 3 4 GP Timer The GP timer provides two input capture IC channels and three output compare OC channels The input capture channels use a 16 bit free running up counter TCNT to record the time of external events indicated by signal transitions on the IC input pins The output compare channels use the same counter to time the initiation of three different events Motorola Timers 9 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM 9 3 1 1 GP Timer Operation The GP timer us
188. 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU TAP Controller Table 15 3 Entering MCU OnCE Mode Step TMS JTAG State OnCE Note a 1 Test Logic Reset Idle b 0 Run Test Idle Idle C 1 Select DR Scan Idle d 1 Select IR Scan Idle e 0 Capture IR Idle Capture DSP core status bits f 0 Shift IR Idle The 4 bits of the JTAG ENABLE MCU ONCE instruction 0b001 1 g 0 Shift IR Idle are shifted into the DSP instruction register h 0 Shift IR Idle i 0 Shift IR Idle j 1 Exit1 IR Idle At this point the IR section of the DSP is ready to be loaded The MCU TAP controller shadow logic is ready to reset the JTAG OnCE signal k 1 Update IR OnCE Enabled MCU OnCE mode is enabled 0 Run Test Idle OnCE Enabled MCU OnCE mode is enabled Note When the MCU OnCE mode is enabled the JTAG IR becomes the concatenation of the DSP IR 4 bits and the MCU IR 8 bits Subsequent shifts into the JTAG IR should be 12 bits in length 15 4 2 Release from Debug Mode for DSP and MCU Table 15 4 shows the TMS sequencing for simultaneously releasing the MCU and DSP from Debug mode assuming all internal states have been restored to both cores Motorola JTAG Port 15 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU TAP Controller Table 15 4 Releasing the MCU a
189. 2 on page 14 4 Note The combination of PSR 1 and PM 7 0 00 is reserved and may cause synchronization problems if used 14 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers SAPCRB SAP Control Register B X FFB7 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O REIE TEIE RLIE TLIE RIE TIE RE TE TCE OF1 OFO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BBPCRB BBP Control Register B X FFA7 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O REIE TEIE RLIE TLIE RIE TIE RE TE RCIE TCIE RCE TCE OF1 OFO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note In addition to setting the interrupt enable bits in the SAPCRB or BBPCRB the SAPPL or BBPPL field respectively in the IPRP must be written with a non zero value to generate the respective interrupts see page 7 14 Table 14 8 SAP BBP CRB Description Name Description Settings REIE Receive Error Interrupt Enable Setting this bit O Interrupt disabled default Bit 15 enables an interrupt when a receive overflow 1 Interrupt enabled error occurs TEIE Transmit Error Interrupt Enable Setting this O Interrupt disabled default Bit 14 bit enables an interrupt when a transmit 1 Interrupt enabled u
190. 3 MDI DSP wake from STOP general purpose interrupt using the IRQC interrupt input 4 Protocol Timer DSP wake from STOP general purpose interrupt using the IRQD interrupt input 5 External DSP wake from STOP general purpose interrupt using the IRQB interrupt input The first three interrupts are MDI functions The other two are protocol timer functions that make use of MDI hardware but have no specific MDI instructions The interrupts can be prioritized in Core Interrupt Priority Register IPRC See Table 7 9 on page 7 15 The relative priority of the MDI receive transmit interrupts is fixed as follows Receive register O full RFIEO Receive register 1 full RFIE1 Transmit register 0 empty TEIEO zd S CE a Transmit register 1 empty TEIE1 5 2 3 2 MCU Interrupts There is only one interrupt request line to the MCU interrupt controller The interrupt service routine must examine the MCU Side Status Register MSR to determine the interrupt source The Find First One FF1 instruction can be used for this purpose If some of the interrupts are disabled software can read the MDI Control Register MCR 5 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes and perform an AND operation with the MSR before executing the FF1 instruction The interrupt service routine should clear the General Purpose Interrupt Pending bits MGI
191. 3 Start Tx macro with delay 3 Tx macro4 04 Start Tx macro with delay 4 Tx macro5 05 Start Tx macro with delay 5 Tx macro6 06 Start Tx macro with delay 6 Tx macro7 07 Start Tx macro with delay 7 Rx macroO 08 Start Rx macro with delay O Rx macro1 09 Start Rx macro with delay 1 Rx macro2 0A Start Rx macro with delay 2 Rx macro3 0B Start Rx macro with delay 3 Rx macro4 0C Start Rx macro with delay 4 Rx_macro5 0D Start Rx macro with delay 5 Rx_macro6 0E Start Rx macro with delay 6 Rx_macro7 0F Start Rx macro with delay 7 Negate_Tout0 10 ToutO 0 Assert ToutO 11 Touto 1 Negate Tout 12 Touti 2 0 Assert Tout1 13 Touti 1 10 13 Protocol Timer Motorola For More Information On This Product Go to www freescale com PT Event Codes Freescale Semiconductor Inc Table 10 4 Protocol Timer Event List Continued Event Name ss Description Negate_Tout2 14 Tout2 0 Assert_Tout2 15 Tout2 1 Negate_Tout3 16 Tout3 0 Assert_Tout3 17 Tout3 1 Negate_Tout4 18 Tout4 0 Assert_Tout4 19 Tout4 1 Negate_Tout5 1A Tout5 0 Assert_Tout5 1B Tout5 1 Negate_Tout6 1C Tout6 0 Assert_Tout6 1D Tout6 1 Negate_Tout7 1E Tout7 0 Assert_Tout7 1F Tout7 1 reserved 2F 20 Reserved for future use TriggerO 30 Activate QSPI Trigger O Trigger 31 Activate QSPI Trigger 1 Trigger2 32 Activate QSPI Trigg
192. 4 EMDD3 EMDD2 EMDD1 EMDDO 0 0 0 0 0 0 0 0 0 0 0 0 Emulation Port Data Register Address 0020_C802 Port Data Bits Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMD5 EMD4 EMD3 EMD2 EMD1 EMDO Reserved E 24 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer MCU Interrupts S R 0 No interrupt request 1 Protocol Timer MCUO interrupt Upper Halfword request pending Interrupt Souce Register Upper Halfword ET Address 0020 0000 IM Description Reset 0000 0 No interrupt request Read Write 1 Protocol Timer interrupt request pending PT1 Description 0 No interrupt request l d QSPI Description 1 Protocol Timer MCU1 interrupt request pending 0 No interrupt request 1 QSPI interrupt request pending PT2 Description 0 No interrupt request MDI Description 1 Protocol Timer MCU2 interrupt 0 No interrupt request request pending 1 MDI interrupt request pending UTX Description 0 No interrupt request SCP Description 1 UART Transmitter Ready interrupt 0 No interrupt request req
193. 5 20 Table 5 21 Table 5 22 Table 6 1 Table 6 2 Table 6 3 xvi Freescale Semiconductor Inc OMR Description IS AA ORAE 4 13 Patch JUMP Targets vii sy oe wee AAA oh AR AR 4 14 Debug Port Pin Multiplexing 0 0 0 2 eee eee eee eee 4 16 Timer Pin MIDLDOpIeXIBE Er as 4 16 GPCR DESCEDUDI es Lost n Vot E Re ee me e Fea eee aes 4 18 Pin Function in DSP Address Visibility Mode oo o 4 20 MCU MDI Access TI AA NU CR ACER ERA 5 6 MDI Registers and Symmetry o ooocooccococcocncooco roo 5 7 MCU Wake up Events va kei o EAE Ru EXER REERZKERE 5 12 MDI Reset SQUAD V edid de CR on 5 14 General Reste Ub BS ooa si dcn der d ad it esencia ari dt Nus 5 15 DSP Side RestriCHOHS ui o acts n ns e aue adeo ido eim REC AER 5 15 MCU Side Restrictions v d d RR A A 5 16 MDI Signalling and Control RegisterS o oooooooooomom 5 17 MCU DSP Register Correspondence o ocooccoocconconocoo o 5 17 MCV R Description sr A RANGE 5 18 MCR Description 90 arar its 5 19 MSR Description aese een t eae Ree eee SERS Re ce IR NC PA 5 21 MITRA Description aes oesau aiam ode For PCR te Oras Mew Ad 5 24 MTRO DOSCEDDDOR cof teas oe Roses KEM el SUD E p p Ee AUR 5 24 MRE DeSCHDLO Jd E es est ene 5 24 MRRO Description odo ao oer aC eA SACO Ae 5 24 DER Description 4t ers E Vea RE E AW EVE EYE 5 25 DSR Description 4 5 ee wees ees pume Wee RSS AR es WEE SESS 5 26 DLDRI Deserplion a RERO WAGER A Re o o REE 5 28 DIROJSSCEDOD
194. 511 dsp program words starting at MDI memory offset 2 write msb portion first for i 0 i lt 511 i 1 while msr amp MSR MTE0 0 mtr unsigned short dsp program i gt gt 16 while msr amp MSR MTEl 0 mtrl unsigned short dsp program i A 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program A 5 Bootstrap Program The following bootstrap source code is programmed into the DSP56652 at the factory Use this listing to develop external ROM programming for DSP56652 applications Note When compiling source code the correct X I O equate and interrupt equate files specified by ioequ asm and intequ asm must be used Listings for these files are provided in Appendix B DSP BOOT LOADER CODE FOR 56652 Boot mode is determined from reading the STDA STDB pins STDA STDB 1 1 boot mode A normal boot mode 0 1 boot mode B shared memory boot mode 1 0 boot mode C messaging unit boot mode 0 0 reserved for SPS test modes e Ne Ne Ne Ne 99 9 9 e 99 99 e 9 section BOOTSTRAP long message header long header equ 4000 message opcodes mem write equ 0001 mem read equ 0002 mem check equ 0003 start app equ 0004 inval opc equ 0004 long read write memory codes bits 14 15 mem x equ 0000 00 mem y equ 4000 01 mem p equ 8000 10 mem invalid equ C000 11 long m
195. 53 BC 1 BMODE input X 54 BC 1 control 1 55 BC 6 SIMRESET B bidir X 54 1l Z amp 56 BC 1 control 1 amp 57 BC 6 SENSE bidir X 56 1 2Z amp 58 BC 1 control 1 amp 59 BC 6 SIMDATA bidir X 58 1 2Z 8 num cell port func safe ccell dis rslt 60 BC 1 control 1 amp 61 BC 6 PWR EN bidir X 60 1 2 8 62 BC 1 control 1 amp 63 BC 6 SIMCLK bidir X 62 1 2Z amp 64 BC 6 DATA 15 bidir X 72 1 Z 8 65 BC 6 DATA 14 bidir X 72 1 Z 8 66 BC 6 DATA 13 bidir X 72 1 Z 8 67 BC 6 DATA 12 bidir X 72 1 Z 8 68 BC 6 DATA 11 bidir X 02 A gt 69 BC 6 DATA 10 bidir X 72 1 2 amp 70 BC 6 DATA 9 bidir X 72 1 Z 8 71 BC 6 DATA 8 bidir X 32 1l E amp 72 BC 1 control 1 amp 73 BC 1 control 1 amp 74 BC 6 DATA 7 bidir X 73 1 Z 8 75 BC_6 DATA 6 bidir X 73 1 2 8 Motorola Boundary Scan Register C 9 For More Information On This Product Go to www freescale com 116 76 BC_6 TI BC 6 78 BC 6 79 BC_6 num cell 80 BC_6 sl BC_6 82 BC 1 83 BC 1 84 BC 1 85 BC 1 86 BC 1 87 BC 1 88 BC 1 89 BC 1 90 BC 6 91 BC 1 92 BC 1 93 BC 1 94 BC 1 95 BC 6 96 BC 6 97 BC 6 98 BC 6 99 BC 6 num cell 100 BC 6 101 BC 1 102 BC 6 103 BC 6
196. 56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Reset The DSP36652 provides a read only Reset Source Register RSR to determine the cause of the last hardware reset RSR Reset Source Register 0020_C400 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O WDR EXR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 8 RSR Description Name Description Settings WDR Watchdog Reset Watchdog timer time out O Last reset not caused by watchdog timer Bit 1 1 Last reset caused by watchdog timer EXR External Reset RESET_IN pin assertion O Last reset not caused by RESET IN Bit O 1 Last reset caused by RESET IN If both external and watchdog reset conditions occur simultaneously the external reset has precedence and only the EXR bit is set If a power on reset occurs with no external reset or watchdog reset both bits remain cleared 4 3 1 MCU Reset All MCU peripherals and the MCU core are configured with their default values when RESET_OUT is asserted Note The STO bit in the General Purpose Configuration Register GPCR which is reflected on the STO pin is not affected by reset It is uninitialized by a power on reset and retains its current value after RESET_OUT is asserted The MOD input pin specifies the location of the reset boot ROM device The pin must be driven at l
197. 56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Protocol Timer Architecture 0020_3000 FTBAO 6 0 ATIC 14 Bits EC 7 Bits FEAR N Frame Table 0 FTBA3360 Ff o o sn ATIC 14 Bits Frame Table 1 RxBA 6 0 MEAR RTIC 14 Bits TxBA 6 0 RTIC 14 Bits RDBA S 0 3 HA L TID 14 Bit DTPTR A b TDBA S0 3 HO 2222 TID 14 Bits 0020 3140 Figure 10 2 Event Table Structure The Frame Table Event Comparator FTEC fetches the Absolute Time Interval Count ATIC in the Frame Table entry pointed to by the Frame Table Pointer Register FTPTR The FTEC compares its ATIC value with the current value of CTIC When the values match the FTEC generates an internal signal FT Hit initiating activity corresponding to the entry s event code The pointer is then incremented to the next entry in the table There are two Macro Timing Control Units MTCUS one each for the receive macro and the transmit macro The MTCU for the receive macro loads a down counter with the relative time interval count RTIC in the entry in the Receive Macro Table pointed to by the Receive Macro Table Pointer RxPTR field in the Macro Table Pointer Register MTPTR When the counter reaches zero the receive MTCU generates an internal signal Motorola Protocol Timer 10 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
198. 6 P5 N6 L6 K6 M7 P6 N7 amp PWR EN K7 amp BGND K8 amp PVCC K9 amp CS B L1 12 M2 N1 M3 amp CVDD L3 amp DGND L5 amp SIMCIK L7 amp BVDD L8 amp PCAP L9 amp RESET IN B L10 amp CGND Ml DVDD M5 amp SIMDATA M9 amp RESET OUT B M10 amp COLUMN N11 M11 P12 N12 P13 M12 N13 M13 amp CS5 N2 amp SIMRESET B N9 amp P1GND N10 amp SENSE P8 amp PGND P9 amp BMODE P10 amp STO Pll attribute TAP SCAN IN of TDI signal is true attribute TAP SCAN OUT of TDO signal is true Motorola Boundary Scan Register C 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Boundary Scan Description Language attribute TAP SCAN MODE of TMS signal is true attribute TAP SCAN RESET of TRST B signal is true attribute TAP SCAN CLOCK of TCK signal is 20 0e6 BOTH attribute INSTRUCTION LENGTH of DSP56652 entity is 4 attribute INSTRUCTION OPCODE of DSP56652 entity is EXTEST 0000 amp SAMPLE 0001 amp IDCODE 0010 amp CLAMP 0101 amp HIGHZ 0100 amp ENABLE MCU ONCE 0011 amp ENABLE DSP ONCE 0110 amp DSP DEBUG REQUEST 0111 amp BYPASS 1111 1000 1001 1010 1011 1100 1101 1110 attribute INSTRUCTION CAPTURE of DSP56652 entity is 0001 attribute IDCODE REGISTER of
199. 7 6 5 4 2 1 0 NKPD NURTS NINT7 NINT6 NINT5 NINT4 NINT3 NINT2 NINT1 NINTO NS2 NS1 NSO 0 0 0 NOTE NIPR can only be written as a 32 bit Reserved E 32 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer MCU Interrupts ma TT F P R 0 No interrupt pending 1 Protocol Timer MCUO interrupt Upper Halfword request pending Fast Interrupt Pending Register Upper Halfword Bae Address 0020_0010 EPTM Description Reset 0000 0 No interrupt pending Read Write 1 Protocol Timer interrupt request pending FPT1 Description 0 No interrupt pending FOSPI Description 1 Protocol Timer MCU1 interrupt x request pending 0 No interrupt pending 1 QSPI interrupt request pending FPT2 Description 0 No interrupt pending FMDI Description 1 Protocol Timer MCU2 interrupt 0 No interrupt pending request pending 1 MDI interrupt request pending FUTX Description 0 No interrupt pending FSCP Description 1 UART Transmitter Ready interrupt 0 No interrupt pending request pending 1 SIM Card Tx Rx or Error i
200. 8 L HH Column ested Pins KPCR 15 8 Status ee X ba Ea Row Open Drain Totem Pole Pins KPSR Controls E X A Dx 2 D Keypad Matrix a E S Noise UpTo 8 x8 Ia ja Filter To Interrupt wa x Controller x DX Data CKIL KDDR 7 0 Row Enable pull up Data Direction Control Control Figure 13 1 Keypad Port Block Diagram Motorola Keypad Port 13 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keypad Operation 13 1 1 Pin Configuration The KP provides 16 pins to support any keypad configuration up to eight rows and eight columns Five of these pins ROW7 ROW 5 and COL7 COL 6 are multiplexed with other functions and require specific settings in the General Purpose Configuration Register for keypad operation Refer to Table 4 13 on page 4 18 Any pins not used for the keypad are available as GPIO pins 13 1 1 1 Column Pins Each column pin intended for keypad operation must be configured as an output by setting the corresponding KCD bit in the Keypad Port Data Direction Register KDDR and for keypad rather than GPIO operation by setting the corresponding KCO bit in the Keypad Port Control Register KPCR Column pins configured for keypad operation are open drain with on board pull up resistors column pins configured as GPIO outputs have totem pole drivers with the pull up resistors disabled These configurations are summarized in Table 13 1 Table 13 1 Keypad Port pull
201. 80A CTIC Channel Time Interval Counter 0000 0020_380C CTIMR Channel Time Interval Modulus Register 0000 0020_380E CFC Channel Frame Counter 0000 0020_3810 CFMR Channel Frame Modulus Register 0000 0020_3812 RSC Reference Slot Counter 0000 0020_3814 RSMR Reference Slot Modulus Register 0000 0020_3816 PTPCR PT Port Control Register 0000 0020_3818 PTDDR PT Data Direction Register 0000 0020_381A PTPDR PT Port Data Register uuuu 0020_381C FTPTR Frame Table Pointer uuuu 0020_381E MTPTR Macro Table Pointer uuuu 0020_3820 FTBAR Frame Tables Base Address Register uuuu 0020_3822 MTBAR Macro Tables Base Address Register uuuu 0020_3824 DTPTR Delay Table Pointer uuuu UART 0020_4000 to URX UART Receiver Register 00uu 0020_403C 0020_4040 to UTX UART Transmitter Register 00uu 0020_407C 0020_4080 UCR1 UART Control Register 1 0000 0020 4082 UCR2 UART Control Register 2 0000 0020 4084 UBRGR UART Bit Rate Generator Register 0000 0020 4086 USR UART Status Register A000 Motorola Programmer s Reference D 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Internal I O Memory Map Table D 8 MCU Internal I O Memory Map Continued Address Register Name Reset Value 0020_4088 UTS UART Test Register 0000 0020_408A UPCR UART Port Control Register 0000
202. 9 8 7 6 5 4 3 2 1 0 X FFBB Dummy SAPTX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFBC Transmit Word SAPPDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFBD PD 5 0 SAPDDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFBE PDC 5 0 SAPPCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X FFBF PEN PC 5 0 Motorola Serial Audio and Baseband Ports 14 15 For More Information On This Product Go to www freescale com BBPRMR X FFA4 BBPTMR X FFA5 BBPCRA X FFA6 BBPCRB X FFA7 BBPCRC X FFA8 BBPSR X FFAQ BBPRX X FFAA BBPTSR X FFAB BBPTX X FFAC BBPPDR X FFAD BBPDDR X FFAE BBPPCR X FFAF 14 16 Table 14 6 Baseband Port Register Summary Freescale Semiconductor Inc SAP and BBP Control Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LV 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LV 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR WL 1 0 DC 4 0 PM 7 0 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REIE TEIE RLIE TLIE RIE TIE RE TE RCIETCIE RCE TCE OF 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSP FSR FSL 1 0 SHFD CKP SCKD SCD 2 0 MOD SYN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDF TDE ROE TUE RFS TFS IF 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dummy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Transmit Word 15 14 13 12 11
203. A EQU SFFBB SAP Time Slot Register SAP RXA EQU SFFBA SAP Receive Data Register SAP SSISRA EQU SFFB9 SAP Status Register SAP CRCA EQU SFFB8 SAP Control Register C SAP CRBA EQU SFFB7 SAP Control Register B SAP CRAA EQU SFFB6 SAP Control Register A SAP TCLR EQU SFFB5 SAP Timer Preload register SAP TCRA EQU SFFB4 SAP Timer count register SAP Control Register A Bit Flags SAP PSR EQU 15 Prescaler Range SAP DC EQU 1F00 Frame Rate Divider Control Mask DC0 DC7 SAP WL EQU 6000 Word Length Control Mask WLO WL7 SAP Control register B Bit Flags SAP OF EQU 3 Serial Output Flag Mask SAP OFO EQU 0 Serial Output Flag 0 SAP OF1 EQU 1 Serial Output Flag 1 SAP TCE EQU 2 SAP Timer enable SAP TE EQU 8 SAP Transmit Enable SAP RE EQU 9 SAP Receive Enable SAP TIE EQU 10 SAP Transmit Interrupt Enable SAP RIE EQU 11 SAP Receive Interrupt Enable SAP TLIE EQU 12 SAP Transmit Last Slot Interrupt Enable SAP RLIE EQU 13 SAP Receive Last Slot Interrupt Enable SAP TEIE EQU 14 SAP Transmit Error Interrupt Enable SAP REIE EQU 15 SAP Receive Error Interrupt Enable F d F SAP Control Register C Bit Flags SAP SYN EQU 0 Sync Async Control SAP MOD EQU 1 SAP Mode Select Motorola Equates and Header Files B 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates SAP SCD EQU 1C Serial Control Direction Mask SAP
204. AG Test Access Port When the bottom connector pins are selected by holding the MUX_CTL pin at a logic high all JTAG pins become inactive i e disconnected from the JTAG TAP controller Table 2 19 JTAG Port Signals Signal Name Type Reset State Signal Description TMS Input Input Test Mode Select TMS is an input signal used to sequence the test controller s state machine TMS is sampled on the rising edge of TCK TDI Input Input Test Data Input TDI is an input signal used for test instructions and data TDI is sampled on the rising edge of TCK TDO Output Tri stated Test Data Output TDO is an output signal used for test instructions and data TDO can be tri stated and is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TCK Input Input Test Clock TCK is an input signal used to synchronize the JTAG test logic TRST Input Input Test Reset TRST is an active low Schmitt trigger input signal used to asynchronously initialize the test controller TEST Input Input Factory Test Mode Selects factory test mode Reserved Motorola Signal Connection Description 2 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JTAG Test Access Port 2 20 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 3 Memo
205. AP Transmit Data Register SAP X FFBC 14 23 SCACR Smart Card Activation Control Register SCP 0020_B002 12 12 SCCRO Serial Channel Control Register O QSPI 0020_5F12 8 19 SCCR1 Serial Channel Control Register 1 QSPI 0020 5F14 SCCR2 Serial Channel Control Register 2 QSPI 0020 5F16 SCCR3 Serial Channel Control Register 3 QSPI 0020_5F18 SCCR4 Serial Channel Control Register 4 QSPI 0020_5F1A SCPCR SCP Control Register SCP 0020_B000 12 11 SCPDR SCP Data Register SCP 0020_B008 12 15 SCPIER SCP Interrupt Enable Register SCP 0020_B004 12 13 SCPPCR SCP Port Control Register SCP 0020_BO0A 12 16 SCPSR SCP Status Register SCP 0020_B006 12 14 SPCR Serial Port Control Register QSPI 0020 5F06 8 13 SPSR Serial Port Status Register QSPI 0020 5F10 8 17 TCNT Timer Counter Timers 0020_6014 9 17 PTEVR PT Event Register PT 0020_3806 10 21 TICR1 Timer 1 Input Capture Register Timers 0020 600E 9 16 TICR2 Timer 2 Input Capture Register Timers 0020 6010 D 24 DSP56652 User s Manual Motorola Freescale Semiconductor Inc Register Index Table D 10 Register Index Continued Register Name Peripheral Address Page TIMR Time Interval Modulus Register PT 0020_3808 10 21 TOCR1 Timer 1 Output Compare Register Timers 0020 6008 9 16 TOCR3 Timer 3 Output Compare Register Timers 0020_600A TOCR4 Timer 4 Output Compare Register Timers 0020_600C TPWCR Timers and PWM Control
206. ASISMENE MA MEA IN p M eni d 12 9 12 5 SCP RESISTE S eter vp echar set FEN aged elated but d 12 10 T23 SCP Control Registers ess ode too ees UE Reda 12 11 Had EROS deter tots a ere e ad Ba 12 16 Chapter 13 Keypad Port 13 1 Keypad Operation eel e t RR Med Gee Sad ENSURE ARAS E AREREN 13 1 IJA a Ss ooh eie brakes uote ti aat uh aici AGe oats eas 13 2 T5 L2 Keypad Matix Polling iot id 13 3 13 1 3 Standby and Low Power Operati0N oo ooococoococoocnocooooooo 13 3 13 1 4 Noise Suppression on Keypad Inputs ooo oooccocconcooooooo 13 3 13 2 Keypad Port Regis osa dox eC ratu dca de era d ab EU EA EK 13 4 Chapter 14 Serial Audio and Baseband Ports 14 41 Data amd Control PINS 54 093 409 34 Rr Raed HR ERAS Md ENSE EE ES SR 14 3 14 25 Transmit and Receive Clocks cra AAA RN 14 3 14 2 1 e A A p Neue e vO ee bei eo ROE 14 3 14X2 Clock Prequency sp Ee E ber ERE iiber de id 14 4 1423 Clock Polinty o soo bate wt Pee ee RES Peu tia eA PE eee MORAN EN 14 5 1424 Bit Rate Multiplier SAP Only soi ccene canes cee ewe AER RV 14 5 14 5 TDM Options pio dl eeu ee se Ie es 14 6 viii DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 14 3 1 Synchronous and Asynchronous Modes 020s ee eee 14 6 14 3 2 Frame Configuration ts etd ores b aie le ttes aoe UA wigs hoe 14 6 A ls E IS SHE EROS SES RE d 14 7 14 3 4 Serial VO Pass soriano Er EXE w
207. Application Date Programmer DS P Co re Predivider Factor PLL Control Register 0 Address X FFFD OET Reset 0000 Multiplication Factor m 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD3 PD2 PD1 PDO MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MFO PLL Control Register 1 Address X FFFC Reset 0000 PEN Description PSTP Description 0 PLL disabled 0 PLL disabled during STOP mode 1 PLL enabled 1 PLL operates during STOP mode Predivider Factor as Division Factor Reserved DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Programmer Date Description Stack Extension mapped to X memory Stack Extension mapped to Y memory Description 128 K clock cycle delay 16 clock cycle delay Description PC relative instructions enabled PC relative instructions disabled DSP Core dE 0 OMR Operating Mode Register Reset determined by hardware Read Write SD Extended Stack 0 1 Underflow Flag SEN Description PCD 0 Stack Extension disabled p 0 1 Stack Extension enab
208. CTC SCPE R 1C SCP Parity Error Set when an incorrect 0 No parity error default Bit 4 parity bit has been detected in a received 1 Parity error detected character Cleared by writing with 1 SCFE R 1C SCP Frame Error Set when an expected O No frame error default Bit 3 stop bit in a received frame is sampled asa 0 1 Frame error detected Cleared by writing with 1 SCOE R 1C SCP Overrun Error Set when a new O No overrun error default Bit 2 character has been shifted in to the receive 1 Overrun error detected buffer and the RX FIFO is full Cleared by writing with 1 12 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 12 5 SCPSR Description Continued SCP Registers SIM is inserted or removed generating a falling or rising edge on the SENSE pin Cleared by writing with 1 Name Type Description Settings SMSC R 1C SIM Sense Change Set simultaneously No change on SENSE pin default Bit 1 with the SMPC interrupt when the smart card 1 Edge on SENSE pin detected SCSP R SCP SENSE Pin Reflects the current state of the SCP SENSE pin Bit O 1 R Read only R RDC Read Read SCPDR to clear R WDC Read Write SCPDR to clear R 1C Read write with 1 to clear write with O ignored SCPDR SCP Data Register Bit15 14 13 12 11 10 9 8 7 6 5 4 3 0020_B008 2 1 Bit 0 SC
209. CTIC rolls over to a modulo value contained in the Channel Time Interval Modulus Register CTIMR which is usually the number of TICKs in a radio channel frame The PT can be synchronized to radio channel timing by reloading CTIC at a specific time This can be done either by writing CTIC directly or writing a new value to CTIMR if needed and generating a reload_counter event 10 1 1 3 Channel Frame Counter The CFC is a programmable read write free running 9 bit modulo down counter decremented by the CFE signal It is used to count channel frames If the CFNIE bit in the PTIER is set the CFC generates a Channel Frame Number Interrupt CFNI when it decrements to zero The CFC rolls over to a modulo value contained in the Channel Frame Modulus Register CFMR Motorola Protocol Timer 10 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Protocol Timer Architecture 10 1 1 4 Reference Slot Prescale Counter The RSPC is 12 bit free running modulo 2400 down counter decremented by TICK The output of the counter is a slot reference signal Reference Slot Expire RSE which drives the RSC Systems that do not need this modulo 2400 divider can bypass the RSPC by setting the SPBP bit in the Protocol Timer Control Register PTCR so that TICK drives the RSC directly 10 1 1 5 Reference Slot Counter The RSC is a programmable 8 bit read write free running down counter decremented by RSE It ca
210. DI_base a move al rl rl MDI memory address retrieve DSP memory address move x r0 r0 r0 DSP memory address which memory space move x0 a and 2 C000 a keep only upper 2 bits cmp mem_x a jeq lt mem write x emp fne y a Jed mem write y emp finem p a Jed mem write p if it didn t match it s invalid move write fail b0 jmp lt mem write return mem write x do n0 _end move x r1 x0 move Xx0 x r0 _end jmp lt mem write success mem write y Motorola DSP56652 DSP Bootloader A 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program do n0 end move x 11 x0 move x0 y r0 _end jmp lt mem write success mem write p move 11 point to low word first move 3 n1 do n0 end movep x 11 x BPMRL read data in big endian movep X rl Hnl x BPMRH format This looks odd movep x lt lt BPMRG p r0 but it s faster and more nop efficient _end continue with mem write success mem write success return memory write confirm short message with SUCCESS move write success b0 mem write return return memory write confirm short message with FAIL _ wait jclr DTE0 x DSR _wait make sure DTRO is not full movep b0 x DTRO rts e e 060606060060606060606000606060606000600600600600600600600600600600600600600600600000060006060009099 A A A A AAA AA A AAA A A e e e e e e e end of memory write request start memory read
211. DRESS relatitve to qspi regs base address equ qspi gpcr 0x00 equ qspi qddr 0x02 equ qspi gpdr 0x04 equ qspi spcr 0x06 equ qspi qcr0 0x08 equ qspi qcrl 0x0a equ qspi qcr2 0x0c equ qspi qcr3 0x0e equ qspi spsr 0x10 equ qspi sccr0 0x12 equ qspi sccrl 0x14 equ qspi sccr2 0x16 equ qspi sccr3 0x18 equ qspi sccr4 Oxla QSPI REGISTERS ADDRESS relatitve to qspi trig base address equ qspi trigger0 0x00 equ qspi triggerl 0x02 equ qspi trigger2 0x04 equ qspi trigger3 0x06 BYTE ACCESS relative to qspi regs base address equ qspi gpcrb 0x00 Motorola Equates and Header Files B 13 For More Information On This Product Go to www freescale com MCU Equates Freescale Semiconductor Inc equ qspi gddrb 0x02 equ qspi gpdrb 0x04 equ qspi spcrb 0x06 equ qspi gcrOb 0x08 equ qspi gcrlb 0x0a equ qspi gcr2b 0x0c equ qspi qcr3b 0x0e BYTE ACCESS relative to qspi spsr base address equ qspi spsrb 0x00 equ qspi sccrOb 0x02 equ qspi sccrlb 0x04 equ qspi sccr2b 0x06 equ qspi sccr3b 0x08 equ qspi sccr4b 0x0a BYTE ACCESS relative to qspi trig base address equ qspi triggerO0b 0x00 equ qspi triggerlb 0x02 equ qspi trigger2b 0x04 equ qspi trigger3b 0x06 QSPI QPCR BITS equ qspi gpcr pc equ qspi gpcr pcl equ qspi qpcr pc2 equ qspi gpcr pc3 equ qspi qpcr pc4 equ qspi qpcr pc5 equ qspi qpcr pc6 equ qspi qpcr pc7 QSPI QPCR BITS equ qs
212. DSP interface MDI with 1K x 16 bit dual port RAM as well as messaging status and control unit Serial audio codec port SAP Serial baseband codec port BBP Protocol timer frees the MCU from radio channel timing events Queued serial peripheral interface QSPI Keypad port capable of scanning up to an 8 x 8 matrix keypad General purpose MCU and DSP timers Pulse width modulation PWM output Universal asynchronous receiver transmitter UART with FIFO IEEE 1149 1 compliant boundary scan JTAG test access port TAP Integrated DSP MCU On Chip Emulation OnCE module DSP program address bus visibility mode for system development ISO 7816 compatible smart card port Introduction 1 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview Operating features Comprehensive static and dynamic power management MCU operating frequency DC to 16 8 MHz at 1 8 V DSP operating frequency DC to 58 8 MHz at 1 8 V Internal operating voltage range 1 8 2 5 V with 3 1 V tolerant I O Operating temperature 40 to 85 C ambient Package option 15 x 15 mm 196 lead PBGA 1 2 Architecture Overview The DSP56652 combines the control and I O capability of the MeCORE MCU with the data processing power of the DSP56600 core to provide a complete system solution for a cellular baseband system The DSP subsystem has a closed architecture meaning that all DSP mem
213. Description 0 Interrupt has not occurred 0 Interrupt has not occurred d 1 MCU Interrupt 1 event has occurred 1 DSP Vector Interrupt event has occurred MCUIO Description THS Description 0 Interrupt has not occurred 0 Timer is not in HALT state 1 MCU Interrupt O event has occurred 1 Timer is in HALT state RSNI Description EOFE Description 0 Interrupt has not occurred 1 Reference Slot Number Interrupt 0 No error has occurred 1 End of Frame Error has occurred CFNI Description MBUE Description 0 Interrupt has not occurred 0 No error 1 Channel Frame Number Interrupt 1 Macro Being Used Error has event has occurred occurred CFI Description PCE Description 0 Interrupt has not occurred 0 No error 1 Channel Frame Interrupt event has occurred 1 Pin Contention Error has occurred Wa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCE MBUE EOFE THS DVI DSPI MCUI2 MCUI MCUIO RSNI CFNI CFI Reserved E 60 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programmer Protocol Timer
214. E 4 Data is shifted out from the shift register to the STDx pin clocked by the transmit bit clock 5 The cycle repeats from step 3 If the TDE bit is set when step 3 occurs indicating that new data has not been written to the Transmit Register the Transmit Underflow Error TUE bit in the SAPSR or BBPSR is set If the Transmit Error Interrupt Enable TEIE bit in the SAPCRB or BBPCRB is set an interrupt is generated The previously sent data which has remained in the Transmit Register is again copied to the shift register and transmitted out Note If the TE bit is cleared during a transmission the SAP or BBP completes the transmission of the current data in the transmit shift register before disabling the transmitter TE should not be cleared until the TDE bit is set indicating that the current data has been transferred from the transmit register to the transmit shift register When the transmitter is disabled the STDx pin is tri stated and any data present in the SAPTX or BBPTX is not transmitted Data can be written to a Transmit Register when the TE bit is cleared but is not copied to the shift register until the TE bit is set Motorola Serial Audio and Baseband Ports 14 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Transmission and Reception 14 4 1 2 Network Mode Transmission The following steps illustrate a typical transmission sequence in network mode 1
215. ET OUT is deasserted the MCU boot mode is latched from the MOD signal MOD Input Input Mode Select This signal selects the MCU boot mode during hardware reset It should be driven at least four CKIL clock cycles before RESET OUT is deasserted MOD driven high MCU fetches the first word from internal MCU ROM MOD driven low MCU fetches the first word from external flash memory MUX CTL Input Input Multiplexer Control This input allows the designer to select an alternate set of pins to be used for RESET IN the debug control port signals and the JTAG signals as follows Alternate MUX CTL high TRST TMS Normal MUX CTL low INT6 STDA DSR INT7 SRDA DTR SCLK Interrupt signals See Table 2 9 Keypad signals See Table 2 11 ROW6 SC2A DCD DSP_DE ROWT SCKA RI TCK Serial Data Port UART signals See Table 2 12 TxD TDO RxD IC1 TDI RTS IC2A RESET IN CTS MCU DE STO Output Chip driven Soft Turn Off This is a GPO pin Its logic state is not affected by reset Motorola Signal Connection Description 2 7 For More Information On This Product Go to www freescale com Internal Interrupts 2 6 Internal Interrupts Freescale Semiconductor Inc With the exception of alternate signal functions TRST TMS and DSP_IRQ the signals described in Table 2 9 are GPIO when not programmed otherwise
216. Enable Each bit 0 determines if the corresponding row pin functions 1 as KP generates an interrupt if pulled low or GPIO no interrupt Either the EKPD bit in the NIER or the EFKPD bit in the FIER must also be set in order to generate the keypad interrupts see page 7 7 Note GPIO interrupt disabled default KP interrupt enabled KPSR Keypad Status Register Bit15 14 13 12 11 10 9 8 7 6 5 0020_A002 4 3 2 1 Bit 0 KPKD RESET 0 0 0 0 0 0 0 0 0 0 0 Table 13 4 Generic Description 0 0 0 0 0 valid key closure has been detected and cleared by reading the KPSR then writing KPKD with 1 Name Type Description Settings KPKD R 1C Keypad Keypress Detect This bit reflects O No valid keypress detected default Bit O the keypad interrupt status It is set when a 1 Valid keypress detected 1 R 1C Read or write with 1 to clear write with O ignored Motorola Keypad Port 13 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keypad Port Registers KDDR Keypad Data Direction Register 0020_A004 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 KCDD 7 0 KRDDI 7 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13 5 KDDR Description Name Description Settings KCDD 7 0 Keypad Column Pin Data Direction O Input
217. FO6 SCKDFOS SCKDFO4 SCKDF03 SCKDFO2 SCKDFO1 SCKDFOO Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 43 Application Freescale Semiconductor Inc Date Programmer QSPI S C G R 1 CSCKDF1 0 2 Assertion to Activation Delay 000 1 SCK cycle delay Serial Channel Control Register 1 001 2 SCK cycles delay Address 0020_5F14 Reset 0000 010 4 SCK cycles delay Read Write 011 8 SCK cycles delay 100 16 SCK cycles delay DATR1 0 2 Delay After Transfer 101 32 SCK cycles delay 000 1 SCK cycle delay 110 64 SCK cycles delay 001 2 SCK cycles delay 111 128 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay MCU_CLK 101 32 SCK cycles delay SCK 1 SCKDF1 0 5 1 110 64 SCK cycles delay 2 3 SCKFD1 6 1 SC 0 5 1 111 128 SCK cycles delay All values for SCKDF1 0 6 are valid Sample values are shown LSBF1 Description 0 Data transferred MSB first EST SCKDF1 0 6 Description 1 Data transferred LSB first 000_0000 SCK MCU_CLK 2 000_0001 SCK MCU_CLK 4 CKPOL1 Description 000 0111 SCK MCU CLK 16 0 SCK inactive at logic 1 L 100 0000 SCK MCU CLK 8 1 SCK inactive at logic 0 0
218. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers 10 4 2 GPIO Registers PTPCR PT Port Control Register 0020_3816 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O PTPC 7 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 23 PTPCR Description Name Description Settings PTPC 7 0 PT Port Control Each of these bits determines 0 Bits 7 0 if the corresponding TOUT pin functions as a PT 1 TOUT pin or GPIO GPIO default Protocol timer pin TOUT PTDDR PT Data Direction Register 0020_3818 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 PTDD 7 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 24 PTDDR Description Name Description Settings PTDD 7 0 PT Data Direction For each PT pin that is O Input default Bits 7 0 configured as GPIO the corresponding PTDD pin 1 Output determines if it is an input or output PTPDR PT Port Data Register 0020_381A Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O PTPD 7 0 RESET 0 0 0 0 0 0 0 0 Table 10 25 PTPDR Description Name Description PTPD 7 0 PT Port Data The function of each of these bits depends on how the corresponding TOUT pin is Bits 7 0 configured PT Reading PTPDn reflects the internal latch Writing PTPDn writes the data latch If the PT is disabled TE 0 the PTPDnis
219. Freescale Semiconductor Inc Order this document by DSP56652UM D Rev 0 04 1999 DSP56652 Baseband Digital Signal Processor User s Manual Motorola Incorporated Semiconductor Products Sector 6501 William Cannon Drive West M MOTOROLA Austin TX 78735 8598 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc This document contains information on a new product Specifications and information herein are subject to change without notice This manual is one of a set of three documents Three manuals are required for complete product information the family manual the user s manual and the technical data sheet O Copyright Motorola Inc 1999 All rights reserved Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical expe
220. Freescale Semiconductor Inc TPWCR Description It RR eeeeee iste IER 9 13 TPWMR Description cs ro eere bec eee RE CE UE Nn 9 14 TPWSR Description a A A RS AR 9 15 GNRC DeSCHDUOB c ez uses FREE ER NEUEN EERWRS WWE 9 16 Protocol Timer Operation Mode Summary 10 10 Protocol Timer Interrupt Sources lille 10 12 PT Port Pin A SN E ie Mem ae REN EA 10 13 Protocol Timer Event List ita ead wr ee SEER AN CHI WR ERAI 10 13 Protocol Timer Register SUMMAIy oo oooooooroooroooo 10 15 PTER Descriptio e tima E E ARS 10 17 Additional Conditions for Generating PT Interrupts 10 18 PATER IDSSOHDUOH sus ti te aa esis ad ea es 10 19 PTSR D scripuai ss wetiu i a be Ed be ERAS 10 20 PTEVR Descrip a a ok Se Sea DOR 10 21 TIMB Description sae eta out ae Ad tet ees PEA gee ag 10 21 CTIC DeseripHOB ru ner Fees EEKE EE RUNE 10 22 CTIMR DeserIptlol sye ira de AID 10 22 CPC DESCr POON sa o A A aa 10 22 CEMR Description co eee pet A AR 10 23 RSCIOESCAPIOAS A Dia 10 23 BSMIR DSSCHDUOR cci Reo E E Visto 10 23 IFETRODOSCHDLOR od seo os ead e REN oh a RR ae Paes 10 24 MITEIERCDDOSGEIDUORN 25 EEE 10 24 PIBAR D sctiptiot sse cers pee sak es AE ARS 10 24 MTBAR Description mew RR AGES DAS Ro ee eis 10 25 DIPTR DESC DION rss ose Ss osea 10 25 PTPER Description serieren ron iie A artes 10 26 PTEDDR Descriptor td a abes ae dl dea E AOS 10 26 PELPIDR DeSCCIDHIOD d ete ted x hte ty bita edo reti oet RI odes stica
221. G EQU SFFF4 BPMRG Register M BPMRL EQU FFF3 BPMRL Register M BPMRH EQU FFF2 BPMRH Register Motorola Equates and Header Files B 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates control and status bits in SR Carry Overflow Zero Negative Unnormalized Extension Limit Scaling Bit Interupt Mask Bit 0 Interupt Mask Bit 1 Scaling Mode Bit 0 Scaling Mode Bit 1 DO Forever Flag Arithmetic Saturation Rounding Mode DO Loop Flag i z w E 4 g Pre Ne SS EZ EE e Ne Ne 99 we e control and status bits in OMR M MA EQU 0 Operating Mode A M MB EQU 1 Operating Mode B M MC EQU 2 Operating Mode C M MD EQU 3 Operating Mode D M EBD EQU 4 External Bus Disable bit in OMR M PCD EQU 5 PC relative logic disable M SD EQU 6 Stop Delay M XYS EQU 8 Stack Extention space select M EUN EQU 9 Extended Stack Underflow Flag M EOV EQU 10 Extended Stack Overflow Flag M WRP EQU 11 Extended Stack Wrap Flag M SEN EQU 12 Stack Extended Enable M ATE EQU 15 Address Tracing Enable bit in OMR i Eh R 5 H MDI SHARED MEMORY BASE equ 1c00 MDI IO BASE equ Sff80 MDR IRQ BASE equ 60 WMDI DSP side registers DRRO equ MDI IO BASE S DSP side receive register 0 B 34 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates
222. Go to www freescale com Freescale Semiconductor Inc DSP Instruction Reference Tables Table D 4 DSP Instruction Set Summary Continued CCR Mnemonic Syntax P T S L E JU N Z V C BRKcc BRKcc 5 ex Sa SS SS SS BScc BScc PC Rn 4 e ee e EIER EISE RECEN E BScc PC aa 4 Ex essc s Tree sd ems BSET BSET bbbb S lt pp gt 2 uae ca ie a uuu ne BSET bbbb S lt ea gt 2 U A 212 12 2 BSET bbbb S lt aa gt 2 2 2 4 BSET bbbb DDDDDD 2 2 2 BSET bbbb S lt qq gt 2 2 2 BSR BSR PC Rn 4 ex Pe A m St err rmm BSR PC aa 4 LCD NEED er A a pes BTST BTST bbbb S lt pp gt 2 xe em a Le BTST bbb S lt ea gt 2 U A IN E ems E O O OP BTST bbbb S lt aa gt 2 MESA Em e cte cS re BTST bbbb DDDDDD 2 XE eum rem reme eedem BTST bbbb S lt qq gt 2 i CLB CLB S D 1 0 CLR CLR D P ARA O ol1ilol CMP CMP S1 S2 P Ry R AA x CMP iiiiii D 2 oe x CMP iii D m 1 CMPM CMPM S1 S2 P os rose PERI ci 7 CMPU CMPU ggg D 1 Sofa E NS DEBUG DEBUG 1 2 ry oe enn vay eem DEBUGcc DEBUGcc 5 iio a e ia ee d DEC DEC ER 1 A DIV DIV 1
223. H ns Ss te s M ER Eten Nus 5 28 DERI Descriptions la roS pravos icu med is 5 28 DRRO Description 442 rA a e be EH bes ERU 5 28 EIM Signal Description e A Ra eS 6 3 Chip Select Address Range ita AS A ale oy 6 4 Interface Requirements for Read and Write CycleS 6 6 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Table 6 4 Table 6 5 Table 6 6 Table 6 7 Table 6 8 Table 6 9 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 7 7 Table 7 8 Table 7 9 Table 7 10 Table 7 11 Table 7 12 Table 7 13 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 8 10 Table 9 1 Table 9 2 Motorola Freescale Semiconductor Inc SIZ T O Encoding oere sere RR ir 444045 REESE 6 8 POLAT ISO Encodings Cubano CE e RR e RR ERROR REA ER 6 8 CSCRn Description s ou eoe We pA me obo PANE AINE GU V I ERA 6 9 EIMCR DGSCEIDIOH s si hen TE REWESENtLEU AT ER UEN ERE E VERE 6 12 ODDE Despistaos 6 13 OPDR DE SCEDLDG ty ska bene yea ee dci quen at dp Sa 6 13 MCU Interrupt SourceS dar ace Ax A eee be ae ees 7 4 ISR DeSOHDUOD A PCR GRIP epe teak th Ole ES 7 6 NIER FIER Description yah Paes bg We Se Ve aru Eb 7 8 NIPR and FIPR Description ras Ch ARTES 7 9 ER DESCHpUONS osm idee when euanidse Si lems ea awe eds 7 10 DSP Int rr pt SOURCES Ed Beak ee Wi ake ee wee 7 11 Interrupt Source P
224. INS EPFR 6 else struct redcap_intpins unsigned short eppar pin assignment register unsigned short epddr data direction register volatile unsigned short epdr data register volatile unsigned short epfr flag register y endif kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP Smart Cart Port example usage struct redcap scp scp struct redcap scp REDCAP MCU SCP kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Hifdef ASSEM define SCP SIMCR 0x0 define SCP SIACR 0x2 define SCP SIICR 0x4 define SCP_SIMSR 0x6 define SCP_SIMDR 0x8 deinfe SCP SIPCR 0xA else struct redcap intpinsi unsigned short simcr control register unsigned short siacr activation control register unsigned short siicr interrupt control register volatile unsigned short simsr status register volatile unsigned short simdr transmit and receive data register volatile unsigned short sipcr pins control register y endif kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP UART note rx and tx registers are short halfwords but are lie on long word boundaries to support the use of ldm stm instructions example usage unsigned long uart rx data unsigned long UART R REG unsigned long uart tx data unsigned long UART T REG struct redcap uart ctrl uart ctrl struct redcap uart lt ctrl UART C REG Kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Motorola Equates and Hea
225. INT3 control 66 DATA13 input output data 27 INT3 input output data 67 DATA12 input output data 28 INT2 control 68 DATA11 input output data 29 INT2 input output data 69 DATA10 input output data 30 INT1 control 70 DATA9 input output data 31 INT1 input output data 71 DATA8 input output data 32 INTO control 72 DATA 15 8 control 33 INTO input output data 73 DATA 7 0 control 34 COLUMN7 control 74 DATA7 input output data 35 COLUMN7 input output data 75 DATA6 input output data 36 COLUMN6 control 76 DATA5 input output data 37 COLUMN6 input output data 77 DATA4 input output data 38 COLUMN5 control 78 DATA3 input output data 39 COLUMN5 input output data 79 DATA2 input output data C 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BSR Bit Definitions Table C 1 BSR Bit Definitions Bit Pin Name Pin Type Cell Type Bit Pin Name Pin Type Cell Type 80 DATA1 input output data 120 ADDR21 output data 81 DATAO input output data 121 TOUTO control 82 CS5 output data 122 TOUTO input output data 83 CS4 output data 123 TOUT1 control 84 CS3 output data 124 TOUT1 input output data 85 CS2 output data 125 TOUT2 control 86 R W control 126 TOUT2 input output data 87 EBO EB1 control 127 TOUT3 control
226. Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Configuration Table 4 9 OMR Description Name Description Settings PCD PC Relative Logic Disable Used to reduce power O PC relative instructions can be used Bit 5 consumption when PC relative instructions default branches and DO loops are not used A PC relative 1 PC relative instructions disabled instruction issued while the PC bit is set causes undetermined results If this bit is set and then cleared software should wait for the instruction pipeline to clear at least seven instruction cycles before issuing the next instruction EBD External Bus Disable Setting this bit disables the O External bus circuitry enabled default Bit 4 core external bus drivers and is recommended for 1 External bus circuitry disabled normal operation to reduce power consumption EBD must be cleared to use Address Tracing MB Operating Mode B Used to determine the operating mode in certain devices On the DSP56652 this Bit 1 bit reflects the state of the DSP_IRQ pin at the negation of RESET_IN MA Operating Mode A Used to determine the operating mode in certain devices On the DSP56652 this Bit 0 bit is set after reset 4 4 2 Patch Address Registers Program patch logic block provides a way to amend program code in the on chip DSP ROM without generating a new mask Implementing the code correction is done by rep
227. Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programmer PWM TPWSR Timers and PWM Status Register Address 0020_6004 Reset 0000 Read Write 1F2 Description 0 Timer 2 Input Capture has not occurred 1 Timer 2 Input Capture has occurred PWF Description 0 PWM compare has not occurred 1 PWM compare has occurred TOV Description 0 TONT overflow has not occurred 1 TCNT overflow has occurred PWO Description 0 PWONT rollover has not occurred IF1 Description 0 Timer 1 Input Capture has not occurred 1 Timer 1 Input Capture has occurred OF4 Description 0 Timer 4 Output Compare has not occurred 1 Timer 4 Output Compare has occurred OF3 Description 0 Timer 3 Output Compare has not occurred 1 Timer 3 Output Compare has occurred OF1 Description 0 Timer 1 Output Compare has not occurred Timer 1 Output Compare has occurred PWCNT rollover has occurred Reserved E 54 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Applicati Freescale Semiconductor Inc on Date Programmer PWM Description Interrupt di
228. L restore low byte of DATA from n5 movep n6 x BPMRH restore high byte of DATA from n6 nop movep X BPMRG p r0 write Data to Memory move SABCD n2 Change gdb movep p rO x BPMRG read Data Pattern gt BPMRG movep x BPMRL bO read Data Pattern gt B movep x BPMRH b1 move n5 a0 restore low byte of DATA from n5 move n6 al restore high byte of DATA from n6 cmp a b was the Memory data as expected DSP56652 DSP Bootloader A 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program nop brkne move r0 nop nop _loop i brkne nop nop nop _loop o move SUCCESS Y2 move fail r4 tne r4 r2 move r2 x rl move r0 x 11 write success fail write address e e mem check return form long message return same for both success and failure move nl a nl offset or long_header a _wait jclr DTEO x DSR wait don t clobber a previous message movep al x DTRO jmp lt START BOOT MODE A the following patterns are used by boot mode A mem check request BADDR M 8 place on modulo boundary for burnin mode PATTERNS dc 0055 background pattern high word dc 5555 background pattern low word dc 00AA data pattern high word dc SAAAA data pattern low word dc 00CC background pattern high word dc CCCC background pattern low word dc 0033 data pattern high word dc 3333 data pattern low word NUM PATTERNSequ PATTE
229. M A F is prohibited Only Supervisor EIM Configuration Register access is allowed Address 0020_1018 Reset 0038 Read Write HDB Description SPRAM Description x 0 Lower data bus D 0 15 driven 0 User mode access to internal RAM externally is allowed 1 Upper data bus D 16 31 driven 1 User mode access to internal RAM externally is prohibited Only Supervisor access is allowed SHEN1 SHENO Description SPIPER Description 0 0 Show cycles disabled 0 User mode access to peripherals 0 1 Show cycles enabled is allowed transfers during EDC CSA idle cycles not visible 1 User mode access to internal externally peripherals is prohibited Only Supervisor access is allowed 1 0 Show cycles enabled all transfers visible causes performance loss 1 1 Reserved EPEN Description 0 Emulation port pins configured as GPIO 1 Emulation port pins configured as SIZ 0 1 and PSTAT O 3 3 2 1 0 Reserved SHEN1 SHENO Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 23 Freescale Semiconductor Inc Application Date Programmer E M D D R EMDDn Description Emulation Port Data Direction Register 0 Pin is GPIO input Address 0020_C800 Reset 0000 1 Pin is GPIO output Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMDD5 EMDD
230. M Sense This signal is a Schmitt trigger input that signals when a smart card is inserted or removed SIMDATA Input or Input SIM Data This bidirectional signal is used to transmit data to and Output receive data from the smart card SIMRESET Output Input SIM Reset The SCP can activate the reset of an inserted smart card by driving SIMRESET low PWR_EN Output Input SIM Power Enable This active high signal enables an external device that supplies Vcc to the smart card providing effective power management and power sequencing for the SIM If the port drives this signal high the external device supplies power to the smart card Driving the signal low disables power to the card The signals described in Table 2 15 are GPIO when not programmed otherwise and default as GPI after reset Note SAP signals STDA SRDA SCKA and SC2A have alternate functions as described in Table 2 9 on page 2 8 and Table 2 11 on page 2 10 When those alternate functions are selected the SAP signals are disabled Table 2 15 SAP Signals Signal Name Type Reset State Signal Description STDA Output Input Audio Codec Transmit Data This output signal transmits serial data from the audio codec serial transmitter shift register SRDA Input Input Audio Codec Receive Data This input signal receives serial data and transfers the data to the audio codec receive shift register SCKA Input or Input Audio Codec Se
231. MCU DSP Interface 5 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers 5 28 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 6 External Interface Module The EIM provides signals and logic to connect memory and other external devices to the DSP56652 EIM features include the following e Twenty two bit external address bus and 16 bit external data bus e Six chip selects for external devices each of which provides A 4 Mbyte range Programmable wait state generator Selectable protection Programmable data port size General output signal if not used as a chip select e External or internal boot ROM device selection Bus watchdog counter for all bus cycles External monitoring of internal bus cycles Figure 6 1 shows a block diagram of the EIM A0 A31 R W TSIZ TC D0 D31 External TREQ TBUSY ABORT Interface Module TA TE e 5 ea T c E o E E PSTATO PSTAT1 Figure 6 1 EIM Block Diagram Motorola External Interface Module 6 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 6 2 shows an example of an EIM interface to memory and peripherals A 0 16 l Address 0 16 RAM 128Kx8 Data 0 15 Data 0 7 Address 0 15 LB RAM 64Kx16
232. MDI memory values are undefined at reset so this boot mode requires a bit of MCU DSP synchronization prior downloading the code The first two 16 bit words in the shared MDI memory space are reserved for synchronization messages To download DSP code in the boot mode the MCU must take the following steps 1 Download up to 511 DSP program words to the MDI memory starting at the third MDI memory location Note that the most signification portion is stored first 2 Write synchronization word 1 1234 to MDI shared memory location 0 3 Wait for the DSP to acknowledge this by writing confirmation word 1 abcd to MDI shared memory location 1 4 Write synchronization word 2 5678 to MDI shared memory location 0 5 Wait for the DSP to acknowledge this by writing confirmation word 2 cdef to MDI shared memory location 1 6 The DSP should now be reading the program from the MDI memory locations and jump to P 0000 after the last word has been read These steps are demonstrated in the pseudo C program in Example A 2 Example A 2 Shared Memory Boot unsigned short mdimem unsigned short MDI MEM ADDR 2 volatile unsigned short mdimem0 unsigned short MDI MEM ADDR volatile unsigned short mdimeml unsigned short MDI MEM ADDR 1 write 511 dsp program words starting at MDI memory offset 2 write msb portion first for i 0 i lt 511 i mdimem unsigned short dsp program i gt gt 16 mdimem
233. MR 15 14 13 12 11 8 7 6 5 4 3 2 1 0 3810 EE one RSC 14 11 6 5 4 3 2 1 0 3812 A a RSMR 15 14 11 7 6 5 4 3 2 14 0 3814 rrr a PTPCR 15 14 13 12 11 7 6 5 4 3 2 1 0 3816 regs PTDDR 15 14 11 6 5 4 3 2 1 0 3818 rrr cuu PTPDR 15 14 12 11 7 6 5 4 3 2 1 0 381A rrr a FTPTR 15 14 11 7 6 5 4 3 2 141 0 381C C aa gt MTPTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 381E TxPTR 6 0 RxPTR 6 0 FTBAR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3820 FTBA1 6 0 FTBAO 6 0 MTBAR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3822 TxBAR 6 0 IE RXBAR 6 0 DTPTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3824 TDBA 3 0 TDPTR 2 0 RDBA 3 0 RDPTR 2 0 10 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 4 1 PT Control Registers PT Registers PTCR Protocol Timer Control Register 0020_3800 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O RSCE CFCE HLTR SPBP TDZD MTER TIME TE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 6 PTCR Description Name Description Settings RSCE Reference Slot Counter Enable O Disabled default Bit 9 1 Enabled CFCE Channel Frame Counter Enable 0 Disabled default Bit 8 1 Enabled HLTR Halt Request Setting this bit halts PT operation O No halt request
234. Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Memory is active it will generate the memory clocks at full frequency and all MCU accesses should be synchronized to it 2 Access type An MCU write is done to a buffer at the MCU side If the buffer is empty the MCU takes two cycles to write to the buffer and proceeds without stall the MDI writes the buffer to the shared memory later in a minimum of another two MCU cycles freeing the buffer In case of a read or a write when the buffer is not yet free from a previous write the access will stall 3 Relative frequency of the MCU and the DSP clocks An MCU access generates a request to the DSP side that must be synchronized to the DSP clock 2 DSP clocks in the worst case and an acknowledge from the DSP to the MCU side that must be synchronized to the MCU clock 2 MCU clocks in the worst case The synchronization stall therefore depends on the frequency of both processors The slower the DSP frequency is relative to the MCU frequency the longer the access time measured in MCU clocks In a typical system configuration the DSP s frequency is higher or equal to the MCU s frequency In this assumption the maximum MCU stall is if the frequencies of the MCU and the DSP are equal If the DSP frequency is lower than the MCU frequency the access time measured in MCU clocks may in principle be very long depending on ho
235. Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56600 Core JTAG Operation C Test Logic Reset 1 Run Test Idle Select DR Scan Select IR Scan Capture IR Shift IR ue 0 1 Exit1 IR 0 CD 0 1 Exit2 IR 1 1 Update DR Update IR f o 1 d 0 Figure 15 3 TAP Controller State Machine 1 Exit2 DR 15 1 3 Instruction Register The DSP JTAG implementation includes a 4 bit instruction register without parity consisting of a shift register with four parallel outputs Figure 15 4 shows the Instruction Register configuration B3 B2 B1 BO Figure 15 4 JTAG Instruction Register Motorola JTAG Port 15 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56600 Core JTAG Operation 15 1 3 1 Instruction Register Operation Data is transferred from the shift register to the parallel outputs during the Update IR controller state The four bits are used to decode the eight unique instructions shown in Table 15 2 Table 15 2 JTAG Instructions Code Instruction B3 B2 B1 BO 0 0 0 0 EXTEST Perform external testing for circuit board electrical continuity using boundary scan operations 0 0 0 1 SAMPLE PRELOAD Sample the DSP56652 device system pins during operation and transparently shift out the result in the BSR Preload values to output pins prior to invokin
236. NT at any time to get the current value of TCNT TCNT is frozen when the MCU enters STOP mode DOZE mode if the TD bit in TPWCR is set or Debug mode if the TDBG bit in TPWCR is set In each case TCNT resumes counting from its frozen value when the respective mode is exited If TD or TDBG are cleared entering the associated mode does not affect GP timer operation 1 These registers also contain bits used by the pulse width modulator 9 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc GP Timer and PWM Timer Prescaler Clock Input TOVIE 7 o Interrupt OF1IE Interrupt FO1 CMP OF 1 OC1 OM10 OM11 OFSIE Interrupt FO3 CMP OF38 OM30 OM31 2 OF4IE 2 Interrupt a FO4 3 CMP OF4 i L an OM40 OM41 IF1IE Interrupt TICR1 IFA in in IM10 IMt1 RxD IC1 IF2IE Interrupt TICR2 IF2 IM20 M21 RTS IC2 Figure 9 5 GP Timer Block Diagram Timers 9 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM 9 3 1 1 1 Input Capture The inputs to IC1 and IC2 are UART pins RxD and RTS respectively Each input capture pin has a dedicated 16 bit latch TICR1 2 and input edge detection selection logic Each input capture function can be programmed to trigger on the rising edge falling edge or both edges of the associated IC pin through the as
237. Note When this signal is enabled the primary TRST signal is disconnected from the TAP controller See Table 2 19 on page 2 19 2 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Protocol Timer Table 2 9 Interrupt Signals Continued Signal Name Type Reset State Signal Description Normal MUX CTL driven low INT7 Input or Input Interrupt 7 When selected this signal can be programmed as an Output interrupt input or a GPIO signal As an interrupt input it can be programmed to be level sensitive positive edge triggered or negative edge triggered SRDA Input Audio Codec Serial Receive Data alternate When programmed as SRDA this signal receives data into the serial receive shift register in the serial audio codec port Note When this signal is used as SRDA the primary SRDA signal is disabled See Table 2 15 on page 2 16 DTR Input Data Terminal Ready When programmed as GPIO this signal is used as the DTR positive and negative edge triggered interrupt input for the serial data port See Table 2 12 on page 2 13 SCLK Input Serial Clock This signal provides the input clock for the serial data port UART See Table 2 12 on page 2 13 Alternate MUX CTL driven high TMS Input Input Test Mode Select alternate This signal is the TMS input for the JTAG test access port TAP controller
238. OB RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 11 SAP BBP PDR Description Name Description Settings SAPPD 5 0 Port Data Each of these bits contains data for the corresponding pin if it is configured as GPIO BBPPD 5 0 A write to one of these registers is stored in an internal latch and driven on any port pin Bits 5 0 configured as an output Reads of these registers return the value sensed on input pins and the latched data driven on outputs SAPDDR SAP Data Direction Register X FFBE Bitib 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O SAPDD5 SAPDD4 SAPDD3 SAPDD2 SAPDD1 SAPDDO STDA SRDA SCKA SC2A SC1A SCOA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BBPDDR BBP Data Direction Register X FFAE Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 5 BBPDD5 BBPDD4 BBPDD3 BBPDD 2 BBPDD 1 BBPDDO STDB SRDB SCKB SC2B SC1B SCOB RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 12 SAP BBP DDR Description Name Description Settings SAPDD 5 0 Data Direction Each of these bits determines O Input default BBPDD 5 0 the data direction of the associated pin if it is 1 Output Bits 5 0 configured as GPIO 14 24 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers SAPPCR SAP Port Cont
239. P 1 0 MSR bits 11 10 to deassert the request to the interrupt controller 5 2 4 Event Update Timing An information exchange between the two processors that is reflected in the status register of the receiving processor an event incurs some latency This latency is the delay between the event occurrence at one processor and the resulting update in the status register of the other processor The latency can be expressed as the sum of a number of transmitting side clocks TC and receiving side clocks RC The minimum event latency occurs when there are no other events pending and is equal to TC 2 RC The maximum event latency is incurred when the event occurs immediately after a previous event is issued It is equal to 4 TC 6 RC 5 2 5 MCU DSP Troubleshooting The MCU can use the MDI in the following three ways to identify and correct the source of a DSP malfunction 1 Examine the DPM bit in the MSR to determine if the DSP is stuck in STOP mode If so the MCU can wake the DSP by setting the DWS bit 2 Issue an NMI using the Command Interrupt setting the MC bit in the MCVR The NMI service routine can incorporate a diagnostic procedure designed for such an event Note that the MNMI bit must also be set to enable non maskable interrupts 3 If neither of the first two measures is effective the MCU can issue a hardware reset to the DSP by setting the DRS bit in the MCR 5 3 Low Power Modes Each side of the MDI i
240. P Interface 5 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers 5 6 1 MCU Side Registers MCVR MCU Command Vector Register 0020_2FF2 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO MC MCV 6 0 MNMI RESET 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Table 5 10 MCVR Description Name Type Description Settings MC R 1S MCU Command Used to initiate a DSP O No outstanding DSP command Bit 8 interrupt Setting the MC bit sets the MCP bit interrupt default in the DSR If the MNMI bit in this register is 1 DSP command interrupt has been set a non maskable MCU command interrupt issued and has not been serviced is issued at the DSP side If MNMI is cleared and the MCIE bit in the DCR is set a maskable interrupt request is issued at the DSP side The MC bit is cleared only when the command interrupt is serviced on the DSP side providing a way for the MCU to monitor interrupt service status The MCVR cannot be written while the MC bit is set MCV 6 0 R W MCU Command Vector Vector address displacement for the DSP command interrupt Bits 7 1 With this mechanism the MCU can activate any interrupt from the DSP interrupt table The actual vector value is twice the value of MCV 6 0 The MCV bits can only be written if the MC bit is cleared MNMI R W MCU Non Maskable Interrupt Determines O Maskable interrupt issued wh
241. P data format and protocol are compatible with ISO 7816 The data format is fixed at one start bit eight data bits one parity bit and two stop bits Either receiver can overlay a NACK during the stop bit period to indicate an error by pulling the SIMDATA pin low The SCP generates the NACK in hardware to save software overhead Odd even parity is determined by the SCPT bit in the SCPCR This bit can be explicitly written or adjusted automatically by the first smart card transmission after the card is inserted In the latter mode referred to as the initial character mode the first character sent by the smart card is either 03 to indicate odd parity or 3B to indicate even parity and the parity bit in the frame is set The initial character mode is selected by setting the SCIC bit in the SCPCR 12 2 3 2 SIMDATA Pin The SIMDATA pin serves as both transmitter and receiver for the SCP The transmitter and receiver are enabled by the SCTE and SCRE pins respectively in the SCPCR To avoid contention on the pin only one of these bits should be set at a given time If both bits are cleared the clock input to the baud generator is disabled The first transaction after the smart card is inserted is always from card to SCP so it is recommended that SCRE be set and SCTE cleared as part of initialization and after the card is removed 12 2 3 3 Data Reception When the smart card is inserted and the power up sequence is complete the SCP puts the SIMDA
242. P56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates Revision History 1 0 may 28 1998 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk e Ne Ne Ne Register Addresses for IPR register M IPRC EQU SFFFF Interrupt Priority Register Core M IPRP EQU SFFFE Interrupt Priority Register Peripheral Register Addresses of PLL M PCTLO EQU SFFFD PLL Control Register 0 M PCTL1 EQU SFFFC PLL Control Register 1 PLL Control Register 0 PCILO M MF EQU SOFFF Multiplication Factor Bits Mask MF0 MF11 M PD EQU F000 PreDivider Factor Bits Mask PD3 PDO M PD03 EQU SF000 PreDivider Factor Bits Mask PD3 PDO PLL Control Register 1 PCIL1 M PD46 EQU SOEOO PreDivider Factor Bits Mask PD6 PD4 M DF EQU 7 Division Factor Bits Mask DF0 DF2 M XILR EQU 3 XTAL Range select bit M XTLD EQU 4 XTAL Disable Bit M PSTP EQU 5 STOP Processing State Bit M PEN EQU 6 PLL Enable Bit M PCOD EQU 7 PLL Clock Output Disable Bit Register Addresses Of BIU Bus Control Register not used in this device ID Register M BCR EQU SFFFA M IDR EQU SFFF9 Register Addresses Of PATCH M PAO EQU FFF8 Patch Address Register 0 M PA1 EQU FFF7 Patch Address Register 1 M PA2 EQU FFF6 Patch Address Register 2 M PA3 EQU FFF5 Patch Address Register 3 Register Addresses Of BPMR M BPMR
243. P56652 not covered by the sections describing individual peripherals These features include the following e Clock configurations for both the MCU and DSP e Low power operation Reset e DSP features operating mode patch addresses and device identification e O multiplexing 4 1 Clock Generation Two internal processor clocks MCU_CLK and DSP_CLK drive the MCU and DSP cores respectively Each of these clocks can be derived from either the CKIH or CKIL clock input pins Both pins should be driven even if one input is used for both internal clocks e CKIH is typically in the frequency range of 10 20 MHz The DSP56652 converts CKIH to a buffered CMOS square wave which can be brought out externally on the CKOH pin by clearing the CKOHD bit in the Clock Control Register CKCTL The buffer can be disabled by setting the CKIHD bit in the CKCTL but only if MCU_CLK is driven by CKIL e CKIL is usually a 32 768 kHz square wave input The frequency of each core clock can be adjusted by manipulating control register bits At reset the MCU_CLK is output on the CKO pin Software can change the output to DSP_CLK by setting the CKOS bit in the CKCTL The CKO pin can be disabled by setting the CKOD bit in the CKCTL The DSP56652 clock scheme is shown in Figure 4 1 Motorola Core Operation and Configuration 4 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generation CKIHD Buf
244. PCRA or BBPCRA The following RFS and TFS parameters can be adjusted by bits in SAPCRC or BBPCRC e Duration The sync signals can be either one bit long or one word long by adjusting the Frame Sync Length FSL 1 0 bits In asynchronous mode the sync signals can be the same or different lengths e Direction The signals can be outputs or inputs according to SCD 2 1 e Timing Word length frame syncs can be asserted at the start of a frame or on the last bit of the previous frame by adjusting the Frame Sync Relative timing FSR bit e Polarity The sync signals can be active high or active low based on the Frame Sync Polarity FSP bit Motorola Serial Audio and Baseband Ports 14 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TDM Options 14 3 4 Serial I O Flags In synchronous mode the SCOx and SC1x pins are available as Serial I O Flags Flag I O 1s typically used in codec systems to select among multiple devices for addressing Flag values can change state for each transmitted or received word The DSP56652 provides double buffered control and status bits for the flags to keep them synchronized with the transmit and receive registers Each flag can be configured as an input or output according to the corresponding SCD bit in the SAPCRC or BBPCRC If a flag pin is configured as an input its state is reflected in the Input Flag IFO or IF1 bit in the port Status Register
245. PD 7 0 RESET 0 0 0 0 0 0 0 0 Table 12 6 SCPDR Description Name Description the top of the RX FIFO SCPD 7 0 SCP Data Buffer This field is used both to transmit and receive SCP data Writing to the SCPDR Bits 7 0 enters a new character in the transmit buffer reading the SCPDR register reads the character at Motorola Smart Card Port For More Information On This Product Go to www freescale com 12 15 SCP Registers Freescale Semiconductor Inc 12 3 2 GPIO The five SCP pins can function as GPIO GPIO functions are governed by the SCPPCR register The data direction and port GPIO data fields correspond to the SCP pins as shown in Table 12 7 Table 12 7 SCP Pin GPIO Bit Assignments GPIO Bit SCP Pin 9 4 PWR_EN 8 3 SIMRESET 7 2 SIMDATA 6 1 SENSE 5 0 SIMCLK SCPPCR SCP Port Control Register 0020_B00A Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 SMEN SCPDD 4 0 SCPPDJ A 0 RESET 0 0 0 0 0 0 0 0 0 0 0 Table 12 8 SCPPCR Description Name Description Settings SMEN SCP Port Enable Determines if all five smart 0 GPIO default Bit 15 card pins function as SCP pins or GPIO 1 SCP SCPDD 4 0 SCP Data Direction Each of these bits O Input default Bits 9 5 determines the data direction of the associated 1 Output pin if it is configured as GPIO SCPPD 4 0 SCP Port GPIO Data 4 0 Each
246. PT Motorola Protocol Timer 10 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Operation Table 10 2 Protocol Timer Interrupt Sources Acronym Name Source CFI Channel Frame Interrupt Channel Frame Expire CFE signal CTIC output CFN Channel Frame Number Interrupt Channel Frame Counter CFC expires RSNI Reference Slot Number Interrupt Reference Slot Counter RSC expires MCUIO MCU Interrupt O mcu_intO event MCUM MCU Interrupt 1 mcu int1 event MCUI2 MCU Interrupt 2 mcu_int2 event DSPI DSP Interrupt dsp_int event DVIO DSP Vector Interrupt 0 CVRO event DVI1 DSP Vector Interrupt 1 CVR1 event DVI15 DSP Vector Interrupt 15 CVR15 event TERI Timer Error Interrupt End of Frame Error EOFE Macro Being Used Error MBUE Pin Contention Error PCE THI Timer Halt Interrupt end of frame halt command HLTR bit in PTCR set The PT interrupt generator provides four outputs to the MCU interrupt controller Each of the first three is dedicated to a single interrupt source MCUIO MCUII and MCUD The fourth output is a logical OR combination of DVI CFI CFNI RSNI TERI and THI Note To enable the reception of CFI CFNI and RSNI during a halt state the THIE bit in the PTIER should be cleared after the PT is halted The PT provides for 16 DSP vectored interrupts DVIs through the CVR15 0 events each of which specifies its own DSP vector addresses on VAB 7
247. PT remains in halt mode until the THS bit is cleared by writing it with 1 Event table execution resumes at the beginning of frame table 0 10 2 3 3 PT Operation in Low Power Modes The PT remains active in MCU WAIT mode and also in DOZE mode if the TDZD bit in TCTR is cleared When the MCU enters STOP mode or DOZE mode if TDZD set PT activity immediately stops and all PT counters and registers are frozen For proper PT operation the following steps should be taken before entering DOZE mode when the TDZD bit in the PTCR is set or STOP mode 1 Halt the PT with an end_of_frame_halt command or by setting HLTR 2 Wait for THS to be asserted 3 Disable the PT by clearing TE When the MCU wakes up software must reenable the PT by setting the TE bit 10 2 4 Error Detection The PT s error detector monitors for three types of error during PT activity It sets a bit in the PTSR when an error is detected and generates a Protocol Timer Error Interrupt TERI if the TERIE bit in PTIER is set These errors include End Of Frame Error A CFE has occurred but the timer has not sequenced through one of the end of frame commands EC 7A 7C EOFE is set Macro Being Used Error A frame table calls a macro that is already active MBUE is set e Pin Contention Error Contradicting values drive a PT output pin during the same Time Interval PCE is set 10 2 5 Interrupts Table 10 2 is a summary of the interrupts generated by the
248. Peripheral DCD Data Carrier Detect ROW6 Keypad Port see Section 13 2 on page 13 4 RI Ring Indicator ROWT7 DSR Data Set Ready INT6 Edge Port see Section 7 3 on page 7 15 DTR Data Terminal Ready INT7 In addition any unused UART pins can be configured for GPIO 11 2 6 Frame Configuration The DSP56652 UART configuration must match that of the external device The most common frame format consists of one start bit eight data bits LSB first no parity bit 11 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Operation and one stop bit for a total of 10 bit times per frame All elements of the frame the number of data and stop bits parity enabling and odd even parity are determined by bits in UCR2 11 3 UART Operation This section describes UART transmission and reception clock generation and operation in low power and Debug modes The UART is enabled by setting the UEN bit in UCRI 11 3 1 Transmission The MCU writes data for UART transmission to UTX Normally the UART waits for RTS to be asserted before beginning transmission The RTS pin can be monitored by reading the RTSS bit in the UART Status Register USR When RTS changes state the RTSD bit in USR is set If the RTSDIE bit in UCRI has been set an interrupt is generated as well This interrupt can wake the MCU from STOP mode If RTS is deasserted in mid chara
249. Programmable Peripheral Chip Selects Five chip select pins are provided for connection to up to five SPI peripherals Software can activate any one pin at a given time and each pin can be programmed to be active high or active low The active chip select signal can be changed at any time including during a queue transfer 8 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Architecture 8 1 4 Programmable Queue Pointers Each of the four queues has a programmable queue pointer that contains the RAM address for the next data to be transmitted or received The MCU can configure the QSPI to switch from one task to another by writing the address of the next task to the queue pointer during queue setup 8 1 5 Four Transfer Activation Triggers QSPI transfers are activated by any of four transfer triggers from the protocol timer or the MCU Each timer or MCU transfer trigger initiates a transfer of successive data from RAM starting at the address pointed to by the queue pointer for that trigger 8 1 6 Programmable Delay after Transfer Some serial peripherals require additional chip select hold time after a transfer is completed To simplify the interface to these devices a delay of 1 to 128 serial clock cycles between queues can be programmed at the completion of a queue transfer 8 1 7 Loading a Programmable Address at the End of Queue A queue can be
250. QU I VEC 52 BBP Receive Data With Exception Status I BBP RLS EQU I VEC 54 BBP Receive last slot I BBP RRO EQU I _VEC 56 BBP Receive Frame rolls over I BBP TD EQU I VEC4 58 BBP Transmit data I BBP TDE EQU I VEC 5A BBP Transmit Data With Exception Status I BBP TLS EQU I VEC 5C BBP Transmit last slot I BBP TRO EQU I VEC S 5E BBP Transmit Frame rolls over I MDI MCU EQU I VEC 60 MDI MCU default command vector I MDI RRO EQU I VEC 62 MDI Receive Register 0 interrupt I MDI RR1 EQU I VEC 64 MDI Receive Register 1 interrupt I MDI TRO EQU I VEC 66 MDI Transmit Register 0 interrupt Motorola Equates and Header Files B 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates I MDI TR1 EQU I VEC 68 MDI Transmit Register 1 interrupt INTEND EQU I VEC FF last address of interrupt vector space B 40 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix C Boundary Scan Register This appendix provides detailed information on the Boundary Scan Register BSR including bit descriptions and the Boundary Scan Description Language BSDL listing for the DSP56652 in the 196 pin Plastic Ball Grid Array PBGA package C 1 BSR Bit Definitions Table C 1 is a list of the BSR bit definitions Motorola Boundary Scan Register C 1 For More Information On This Product Go to ww
251. R and JSSET The specific addresses for DSP registers are listed in Table D 9 on page D 19 Motorola Memory Maps 3 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Memory Map and Descriptions 3 2 2 Y Data Memory Y data RAM is a 16 bit wide internal static memory occupying the lowest 6K locations in Y memory space Y 0000 17FF Y data ROM is a 16 bit wide internal static memory occupying 10K locations in Y memory space at Y 8000 A7FF 3 2 3 Program Memory Program RAM is a 24 bit wide high speed static memory occupying the lowest 512 locations in the P memory space P 0000 01FF Program ROM is a 24 bit wide internal static memory occupying 48K locations at P 0800 C7FF The first 1K of this space P 0800 0BFF contains factory code that enables the user to download code to program RAM via the MDI This code is described and listed in Appendix A DSP56652 DSP Bootloader 3 2 4 Reserved Memory All memory locations not specified in the above description are reserved and should not be accessed These areas include the following e X 2000 7FFF and X A4800 FF7F e Y 1800 7FFF and Y A800 FFFF e P 0200 07FF and P C800 FFFF 3 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 4 Core Operation and Configuration This section describes features of the DS
252. R mie PT Control Register Address 0020 3800 Reset 0000 Read Write MTER Description 0 Active macro execution continues to end of macro a 1 Active macro execution halts SPBE Description immediately when HLTR bit is set or 0 Reference Slot Prescaler Counter End of frame halt received RSPC drives RSC 1 RSPC bypassed TICK drives RSC TIME Description 0 Protocol Timer event disabled until HLTR Description CFE occurs 0 Timer HALT not requested 1 Protocol Timer event executes immediately after TE assertion or 1 Timer HALT requested HALT state is exited CFCE Description TE Description 0 Channel Frame Counter disabled 0 Protocol Timer disabled 1 Channel Frame Counter enabled 1 Protocol Timer enabled RSCE Description 0 Reference Slot Counter disabled 1 Reference Slot Counter enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSCE CFCE HLTR SPBP TDZD MTER TIME TE Reserved E 58 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programmer PTIER MCIE2 Description Protocol Timer 0 Interrupt disabled MCU Interrupt 2 enabled Description Interrupt disabled MCU Interrupt 1 enabled Description Interrupt disabled MCU Interrupt 0 enabled Description Interrupt disabl
253. RAM using only the MDI messaging unit registers to transfer data The DSP program must start from program RAM address 0000 No MCU DSP synchronization is required The bootloader reads the SAP STDA pin and the BBP STDB pin configured as GP inputs at reset to determine the boot mode as shown Table A 1 on page A 2 The user must supply pull up and or pull down resisters to STDA and STDB to ensure that the DSP enters the desired mode Motorola DSP56652 DSP Bootloader A 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot Table A 1 DSP56652 Boot Modes STDA STDB Boot Mode 1 1 Mode A Normal MDI boot mode 0 1 Mode B MDI shared memory boot mode 1 0 Mode C MDI messaging unit boot mode 0 0 Reserved for Motorola test modes A 2 Mode A Normal MDI Boot The normal boot mode uses MDI communication between the DSP and MCU to implement the following functions e Download to the DSP program X or Y RAM e Upload from the DSP program X or Y memories RAM or ROM e Run diagnostic tests on the DSP 0 5K program RAM e Start the DSP at a given program address jump to a given address After entering the normal boot mode the DSP waits until a message has arrived from the MCU When it receives a message the DSP performs the necessary actions and in most cases returns an acknowledgment message to the MCU The DSP remains in the normal boot mode
254. RNS A A A A A A A A NA end of memory check request start start application request e Ne Ne 99 e A A A A A NA start application move x x0 r0 jmp ro kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk BOOT MODE B Shared memory Mode ok ee ee AR RR RRE RAR RR RARA RA RR R RAR RARE RAR RAR RAR AR RRA RAR AR RAR A 26 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program START BOOT MODE B move MDI_base xr0 look for protocol B signature 0 _wait0 move x r0 a cmp gt prot B sig 0 a jne lt wait0 reply with protocol B confirm 0 move gt prot_B conf 0 x0 move x0 x r0 1 look for protocol B signature 1 _waitl move x r0 a cmp prot_B sig 1 a jne lt waitl reply with protocol B confirm 1 move prot_B conf 1 x0 move x0 x r0 1 Okay do the download move 0 r1 start of p memory to download lea r0 3 r0 MDI base 3 move 3 n0 do 511 _end movep X r0 Xx BPMRL read data in movep x 10 n0 x BPMRH big endian format movep X BPMRG p r1 nop _end jmp lt 0 H kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk BOOT MODE C Message Unit Mode kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk START BOOT MODE C move 70 r0 do 7511 loop _wait0 jclr DRF0 x DSR _wait0 wait till DRRO is full movep x DRRO al _w
255. Register Timers 0020_6000 9 13 TPWIR Timers and PWM Interrupts Enable Register Timers 0020_6006 9 16 TPWMR Timers and PWM Mode Register Timers 0020_6002 9 14 TPWSR Timers and PWM Status Register Timers 0020_6004 9 15 PTSR PT Status Register PT 0020_3804 10 20 UBRGR UART But Rate Generator Register UART 0020_4084 11 14 UCR1 UART Control Register 1 UART 0020 4080 11 11 UCR2 UART Control Register 2 UART 0020 4082 11 13 UDDR UART Data Direction Register UART 0020 408C 11 16 UPCR UART Port Control Register UART 0020 408A 11 16 UPDR UART Port Data Register UART 0020 408bE 11 16 URX UART Receive Registers UART 0020 4000to 11 9 0020 403C USR UART Status Register UART 0020_4086 11 14 UTS UART Test Register UART 0020_4088 11 15 UTX UART Transmit Registers UART 0020_4040to 11 10 0020_407C WCR Watchdog Control Register Timers 0020_8000 9 6 WSR Watchdog Service Register Timers 0020_8002 9 6 Motorola Programmer s Reference D 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Acronym Changes D 6 Acronym Changes Some register and bit acronyms in the DSP56632 are different than those in previous DSP56000 and M CORE family devices Table D 11 presents a summary of the changes Addresses containing X are DSP X memory addresses All other addresses are the LSP of MCU addresses the MSP is 0020 Table D 11 DSP56652 Acronym Changes
256. S PAR4 PAR3 PAR2 PAR1 PARO E 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer M C U M DI MTIE1 Description 0 Interrupt disabled M C R 1 MCU Transmit Interrupt 1 enabled MCU Side Control Register Address 0020_2FF4 MGIE1 Description Reset 0000 0 Interrupt disabled uae s 1 MCU General Interrupt 1 enabled MTIEO Description 0 Interrupt disabled MGIEO Description 1 MCU Transmit Interrupt O enabled 0 Interrupt disabled 1 MCU General Interrupt O enabled MRIE1 Description 0 Interrupt disabled DHR Description 1 MCU Receive Interrupt 1 enabled 0 No reset issued 1 Resets DSP MRIEO Description 0 Interrupt disabled MDIR Description 1 MCU Receive Interrupt 0 enabled 0 No reset issued 1 Resets MDI on MCU and DSP MCU to DSP Flags 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 MRIEO MRIE1 MTIEO MTIE1 MGIEO MGIE1 DHR MDIR MDF2 MDF1 MDFO 0 0 0 0 0 MCVR Command Vector MCU Side Command Vector Register Address Address 0020 2FF2 Reset 0060 ERR Read Write MNMI Description 0 Command Interrupt is
257. SD 5 WS CHSZ 4086 USR 15 TXMPTY TXE 408A UPCR 3 0 PC 3 0 UPC 3 0 408C UDDR 3 0 PDC 3 0 UDD 3 0 408bE UPDR 3 0 D 3 0 UPD 3 0 Motorola Programmer s Reference D 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Acronym Changes D 28 Table D 11 DSP56652 Acronym Changes Continued Register Bit Name Function Address Bit Original New Original New SCP B000 SIMCR SCPCR 9 VOLTSEL CKSEL E 8 OVRSINK NKOVR 5 SISR SCSSR 4 SIPT SCPT 3 SIIC SCIC 2 SINK NKPE 1 SITE SCTE 0 SIRE SCRE B002 SIACR SCACR 4 SICK SCCLK 3 SIRS SCRS 2 SIOE SCDPE 1 SIVE SCPE 0 SIAP APDE B004 SIICR SCPIER 4 SITCI SCTCIE 3 SIFNI SCFNIE 2 SIFFI SCFFIE 1 SIRRI SCRRIE 0 SIPDI SCSCIE B006 SIMSR SCPSR 9 SIFF SCFF 8 SIFN SCFN 7 SITY SCTY 6 SITC SCTC 5 SITK TXNK 4 SIPE SCPE 3 SIFE SCFE 2 SIOV SCOE 1 SIIP SCSC 0 SIPD SCSP B008 SIMDR SCPDR 7 0 SIMD 7 0 SCPD 7 0 BO0A SIPCR SCPPCR 9 5 PDIR 4 0 SCPDD 4 0 4 0 PDAT 4 0 SCPPD 4 0 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Acronym Changes Table D 11 DSP56652 Acronym Changes Continued
258. SPSR Chip Selects n SPICSO 4 Queue Pointers Serial Channel QSPI Internal Address Bus 7 Bit A e QP 0 3 a Control Registers a SCCR 0 4 Queue Control ES Registers s Fhe Te SCK QCR 0 3 5 enerator a SPI Control S Receive Register Buffer SPCR Shift In Ni Register n MISQ Protocol Timer Trigger Clock Signals Control Logic iiu Address Bus Control Signals if Shift Out Y MOSI Data Bus Register Figure 8 1 QSPI Signal Flow Motorola Queued Serial Peripheral Interface 8 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Architecture 8 2 2 Control Registers A brief summary of the control registers for QSPI and GPIO operation is given below More detailed descriptions can be found in Section 8 4 on page 8 12 The QSPI uses the following control registers e SPSR The Serial Peripheral Status Register indicates which of the four queues is active executing or has ended a transfer with an interrupt It also contains flags for a HALT request acknowledge trigger collision or queue pointer wraparound e SPCR The Serial Peripheral Control Register enables QSPI operation enables the four queues sets the polarity of the five chip selects enables trigger accumulation queue 1 only initiates a QSPI HALT selects QSPI behavior in DOZE mode and enables interrupts for HALT acknowledge trigger collision and queue wraparound e QCR3 0 Each of Queue Co
259. Semiconductor Inc Keypad Operation 13 1 2 Keypad Matrix Polling The keypad interrupt service routine typically includes a keypad polling loop to determine which key is pressed This loop walks a O across each of the keypad columns by clearing the corresponding KCO bit and reads the row values in the KPDR at each step The process is repeated several times in succession and the results of each pass compared with those from the previous pass When several consecutive scans yield the same key closures a valid key press has been detected Software can then determine which switch is pressed and pass the value up to the next higher software layer 13 1 3 Standby and Low Power Operation The keypad does not require software intervention until a keypress is detected Software can put the keypad in a standby state between keypresses to conserve power by clearing the KCO bits in the KPCR Clearing the KCO bits turns off the open drain mode in the corresponding column outputs converting them to totem pole drivers and disconnects the pull up resistors reducing standby current The outputs are forced low by clearing the corresponding bits in the KPDR Row inputs are left enabled The MCU can then attend to other tasks or enter a low power mode The keypad port interrupts the MCU when a key is pressed waking it up if it is in a low power mode The MCU re enables the open drain drivers sets all the column strobes high and runs the keypad polling routi
260. Sheets For More Information On This Product Go to www freescale com E 17 Freescale Semiconductor Inc Application Date Programmer E M WEN Description 0 The EBO 1 signals are negated CSCR1 m 1 The EBO 1 signals are negated half Chip Select Register 1 a clock cycle earlier on write Address 0020 1004 accesses Reset uuuu Read Write EBC Description 0 Read and write accesses both OEA Description assert EBO 1 0 The OE signal is negated normally 1 Only write accesses can assert 1 The OE signal is asserted half a EBOET clock cycle later on read accesses DSZ1 DSZO Description CSA Description 0 0 8 bit port on D 8 15 pins 0 The CS signal is asserted normally 0 1 8 bit port on D 0 7 pins 1 The CS signal is asserted one 1 0 16 bit port on D 0 15 pins cycle later on read and write accesses and an extra cycle 1 1 Reserved inserted between back to back cycles SP Description EDC Description 0 User mode accesses allowed 0 No delay occurs after a read cycle User mode accesses prohibited 1 One clock cycle is inserted after a read cycle WP Description 0 Writes are allowed WWS Description 1 Writes are prohibited 0 Read and write WAIT states same 1 Write WAIT states Re
261. Status Register 40 X FFBA SAPRX SAP Receive Data Register FFFF X FFBB SAPTSR SAP Time Slot Register 0 X FFBC SAPTX SAP Transmit Data Register 0 X FFBD SAPPDR SAP Port Data Register 0 X FFBE SAPDDR SAP GPIO Data Direction Register 0 X FFBF SAPPCR SAP Port Control Register 0 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Internal I O Memory Map Table D 9 DSP Internal O Memory Map Continued Address Register Name Reset Value DSP Core X FFF5 PAR3 Patch 3 Register uuuu X FFF6 PAR2 Patch 2 Register uuuu X FFF7 PAR1 Patch 1 Register uuuu X FFF8 PARO Patch 0 Register uuuu X FFF9 IDR ID Register 0652 X FFFB OGDB OnCE GDB Register 0000 X FFFC PCTL1 PLL Control Register 1 0010 X FFFD PCTLO PLL Control Register 0 0000 X FFFE IPRP Interrupt Priority Register Peripheral 0000 X FFFF IPRC Interrupt Priority Register Core 0000 Motorola Programmer s Reference D 21 For More Information On This Product Go to www freescale com Register Index Freescale Semiconductor Inc D 5 Register Index Table D 10 lists all DSP56652 registers in alphabetical order by acronym and includes the name peripheral address and description page number for each register Table D 10 Register Index
262. T O QP3 LE3 HMD3 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The MCU can read and write QCRO 3 The QSPI can read these registers but can only write to the queue pointer fields QP 5 0 Writing to an active QCR is prohibited while it is executing a transfer It is highly recommended that writing to the QCRs be done only when the QSPI is disabled or in HALT state Table 8 4 QCR Description Name Description Settings LEn Bit 15 Load Enable for Queue n Enables loading a new value to the queue pointer QPn of O QP loading disabled default 1 QP loading enabled Queue n If LEn is set when the QSPI reaches an End Of Queue EOQ command PCS 111 in the Queue n control halfword the value of the least significant byte of the data halfword of that queue entry is loaded into QPn This allows the next triggering of queue n to resume transfer at the address loaded from the data halfword alts at any sub queue boundary alts only at PAUSE NOP or EOQ HMDn Halt Mode for Queue n Defines the point at O Bit 14 1 which the execution of queue n is halted when the MCU sets the HALT bit in the SPCR or when a higher priority transfer trigger is activated H H Queued Serial Peripheral Interface 8 15 For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc QSPI Registers and Memory Tabl
263. T signal and the following reset conditions are established Motorola Core Operation and Configuration 4 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Reset e All peripherals and both cores are initialized to their default values e Both MCU CLK and DSP_ CLK are derived from CKIL e The CKO pin is enabled driving MCU_CLK e The CKIH CMOS converter is enabled and drives the CKOH pin An eight cycle stretch circuit guarantees that RESET_OUT is asserted for at least eight CKIL clock cycles This circuit also stretches the negation of RESET_OUT The precise time between the negation of RESET_IN and RESET_OUT is between seven and eight CKIL cycles Four cycles before RESET_OUT is negated the MOD pin is latched This externally driven pin determines whether the first instruction is fetched from internal MCU ROM or external flash memory connected to CSO as described in Section 4 3 1 on page 4 11 Reset timing is illustrated in Figure 4 3 Pin RESET_OUT lt Low Frequency Reference RESET IN Pin LV Detector In To Internal Resets 3 Cycle Qualified 4 Cycle Stretcher MOD Pin Latch Signal r 4 Cycle Stretcher Pin Watchdog RTS RESET IN Pin Timer MUX Power Up Reset Status Bypass Register MOD Figure 4 3 DSP56652 Reset Circuit Internal MOD Signal to EIM 4 10 DSP
264. TA pin in tristate mode to receive the first transmission from the card The pin is initially at a logic one If the pin goes to a logic low and the receiver detects a qualified start bit it proceeds to decode the succeeding transitions on the SIMDATA pin monitoring for eight data bits two stop bits and correct parity When a complete character is decoded the data is written to the next available space in the four character receive FIFO The MCU reads the data at the top of the FIFO by reading the SCP Data Register SCPDR and the FIFO location is cleared Two receive conditions can be flagged in the SCPSR 1 If the FIFO is empty when the first character is received the SCEN bit is set An interrupt is generated if the SCFNIE bit in the SCPIER is set 2 If the received character fills the FIFO the SCFF bit is set An interrupt is generated if the SCFFIE bit in the SCPIER is set 12 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Operation Three receive error conditions can also be flagged in the SCPSR 1 A parity error is flagged by setting the SCPE bit If the NKPE bit in the SCPCR is set a NACK is sent to the smart card 2 A frame error is flagged if the stop bit is not received by setting the SCFE bit 3 If the FIFO is full when another character is received the SCOE flag is set to indicate an overrun If the NKOVR bit in the SCPCR
265. TBA1 FTBAO 0 0 MIBAR Transmit Base Address Macro Table Base Address Register Receive Base Address Read Write DNE NE EE NENNEN 8 7 6 5 4 3 2 1 0 TxBA6 TxBAS TxBA4 TxBA3 TxBA2 TxBAT TxBAO RxBA6 RxBAS RxBA4 RxBA3 RxBA2 RXBA1 RXBAO 0 0 DIPT H Transmit Delay Table Delay Table Pointer Address 0020 3824 Reset uuuu Receive Delay Base Read Write Transmit Delay Base Receive Delay Table 51 2 vw 110 1wm 9 8s l7 l6 5 4 3 2 1 0 TDBA3 TDBA2 TDBA1 TDBAO TDPTR2 TDPTR1 TDPTRO Reserved RDBA3 RDBA2 RDBA1 RDBAO RDPTR2 RDPTR1 RDPTRO Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 65 Freescale Semiconductor Inc Application Date Programmer PT P C R PTPCn Description 0 Pin is GPIO output PT Port Control Register 1 Pin is Protocol Timer output Address 0020_3816 Reset 0000 Read Write 15 14 13 12 11 10 7 6 5 4 3 2 1 0 PTPC7 PTPC6 PTPC5 PTPC4 PTPC3 PTPC2 PTPC1 PTPCO 0 0 0 0 0 0 0 0 PT D D R PTDDn Description 0 Pin is input when GPIO PT Data Direction Register 1 Pin is out
266. TRO DSP Transmit Register 0 MDI X FF8D 5 28 DTR1 DSP Transmit Register 1 MDI X FF8C 5 28 EIMCR EIM Configuration Register EIM 0020_1018 6 12 EMDDR Emulation Port Control Register Emulation 0020_C800 6 13 EMDR Emulation Port Data Register Emulation 0020_C802 6 13 EPDDR Edge Port Data Direction Register EP 0020_9002 7 17 EPDR Edge Port Data Register EP 0020_9004 7 18 D 22 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Index Table D 10 Register Index Continued Register Name Peripheral Address Page EPFR Edge Port Flag Register EP 0020_9006 7 18 EPPAR Edge Port Pin Assignment Register EP 0020_9000 7 17 FIER Fast Interrupt Enable Register Interrupts 0020_0008 7 7 FIPR Fast Interrupt Pending Register Interrupts 0020_0010 7 9 FTBAR Frame Tables Base Address Register PT 0020_3820 10 24 FTPTR Frame Table Pointer PT 0020_381C 10 24 GPCR General Port Control Register 1 O Mux 0020_CCO 4 18 ICR Interrupt Control Register Interrupts 0020_0014 7 10 IDR ID Register JTAG X FFF9 4 15 IPRC Interrupt Priority Register Core Interrupts X FFFF 7 15 IPRP Interrupt Priority Register Peripheral Interrupts X FFFE 7 14 ISR Interrupt Source Register Interrupts 0020_0000 7 6 PITCNT PIT Counter Timers 0020_7004 9
267. TXB EQU SFFAC BBP Transmit Data Register BBP TSRB EQU SFFAB BBP Time Slot Register BBP RXB EQU SFFAA BBP Receive Data Register BBP SSISRB EQU SFFA9 BBP Status Register BBP CRCB EQU SFFA8 BBP Control Register C BBP CRBB EQU SFFA7 BBP Control Register B Motorola Equates and Header Files B 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Equates BBP_CRAB EQU SFFA6 BBP Control Register A BBP TCRB EQU SFFA5 BBP Tran Frame Preload counter BBP RCRB EQU SFFA4 BBP Rec Frame Preload counter BBP Control Register A Bit Flags BBP PSR EQU 15 Prescaler Range BBP DC EQU 1F00 Frame Rate Divider Control Mask DC0 DC7 BBP WL EQU 6000 Word Length Control Mask WLO WL7 BBP Control register B Bit Flags BBP OF EQU 3 Serial Output Flag Mask BBP OFO EQU 0 Serial Output Flag 0 BBP OF1 EQU 1 Serial Output Flag 1 BBP TCE EQU 4 BBP Tr Frame Cnt enable BBP RCE EQU 5 BBP Rc Frame Cnt enable BBP TCIE EQU 6 BBP Tr Frame RO enable BBP RCIE EQU 7 BBP Rc Frame RO enable BBP TE EQU 8 BBP Transmit Enable BBP RE EQU 9 BBP Receive Enable BBP TIE EQU 10 BBP Transmit Interrupt Enable BBP RIE EQU 11 BBP Receive Interrupt Enable BBP Transmit Last Slot Interrupt Enable BBP Receive Last Slot Interrupt Enable BBP Transmit Error Interrupt Enable BBP Receive Error Interrupt Enable BBP TLIE EQU 12 BBP RLIE EQU 13 BBP TEIE EQU 14 BBP REIE
268. The MCU can immediately disable the QSPI by clearing the QSPE bit in the SPCR All QSPI state machines and the SPSR are reset Data in an ongoing transfer can be lost and the external SPI device can be disrupted 8 3 6 Error Interrupts If a queue pointer contains 3F when the next control halfword is fetched and the QP is not loaded from the data halfword it wraps around to 00 and the QPWF flag in the SPSR is set If the WIE bit in the SPCR is set an interrupt is generated to the MCU If a trigger for a queue occurs while the queue is active the TRC flag in the SPSR is set If the TRCIE bit in the SPCR is set an interrupt is generated to the MCU 8 3 7 Low Power Modes If the QSPI detects a DOZE signal and the DOZE bit in the SPCR is set the QSPI halts its operation as if the HALT bit had been set When the MCU exits DOZE mode it must clear the HALTA bit to resume QSPI operation Motorola Queued Serial Peripheral Interface 8 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory When the QSPI detects a STOP signal it halts immediately by shutting off its clocks The status of the QSPI is left unchanged but any ongoing transfer is lost and the peripheral can be disrupted 8 4 QSPI Registers and Memory This section describes the QSPI control registers data and control RAM and GPIO registers These areas are summarized in Table 8 2 Table 8 2 QSPI Registe
269. UB S D P ESSE PUES SUB iiiiii D 2 ERU MESES aes t SUB Ziii D 1 d DR aer SUBL SUBL S D P EE E XE T E Motorola Programmer s Reference D 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Instruction Reference Tables Table D 4 DSP Instruction Set Summary Continued CCR Mnemonic Syntax P T S UIN vic SUBR SUBR S D P g f Tec Tec JJJ D ttt TTT 1 ae EHE Tcc JJJ D 1 as E Toc ttt gt TTT Ex 1 li lla TFR TFR S D P id ea ee x TRAP TRAP 9 e a TRAPcc TRAPcc 9 20 ya EET p TST TSTS P o l VSL VSL S i L ea 1 U A ED zx WAIT WAIT 10 uE E a D 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Instruction Reference Tables Table D 5 Program Word and Timing Symbols Column Description and Symbols P Parallel Move P Parallel Move N No Parallel Move Not Applicable T Instruction Clock Cycle Counts Add one cycle for each symbol in column U Pre Update A Long Absolute I Long Immediate Table D 6 Condition Code Register CCR Symbols Symbol Description S Scaling bit indicating data growth is detected L Limit bit indicating arithmetic overflow and or data limi
270. User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Instruction Reference Tables Table D 1 MCU Instruction Set Summary Continued Mnemonic Instruction Syntax Opcode C Bit DIVS DIVS RX R1 0011 0010 0001 rrrr Undefined DIVU DIVU RX R1 0010 0011 0001 rrrr Undefined DOZE DOZE 0000 0000 0000 0110 Unaffected FF1 FF1 RX R1 0000 0000 1110 rrrr Unaffected INCF INCF RX 0000 0000 1011 rrrr Unaffected INCT INCT RX 0000 0000 1010 rrrr Unaffected IXH IXH RX RY 0001 1101 ssss rrrr Unaffected IXW IXW RX RY 0001 0101 ssss rrrr Unaffected JMP JMP RX 0000 0000 1100 rrrr Unaffected JMPI JMPI LABEL 0111 0000 dddd dddd Unaffected JSR JSR RX 0000 0000 1101 rrrr Unaffected JSRI JSRI LABEL 0111 1111 dddd dddd Unaffected LD BHW LD B H W RZ RX DISP 1000 zzzz iiii rrrr Unaffected LD LDB LDH LDW RZ RX DISP LDM LDM RF R15 RO 0000 0000 0110 rrrr Unaffected LDQ LDQ R4 R7 RX 0000 0000 0100 rrrr Unaffected LOOPT LOOPT RY LABEL 0000 0100 ssss bbbb Set if signed result in RY gt 0 else bit is cleared LRW LRW RZ LABEL 0111 zzzz dddd dddd Unaffected LSL LSL RX RY 0001 1011 ssss rrrr Unaffected LSLC LSLC RX 0011 1100 0000 rrrr Copy RX 31 into C before shifting LSLI LSLI RX IMM5 0011 110i iiii rrrr Unaffected LSR LSR RX RY 0000 1011 ssss rrrr Unaffected LSRC
271. VR2 delay MCU int 0 Negate Tout6 End of macro activate delay activate delay Protocol Timer 10 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Protocol Timer Programming Example 10 28 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 11 UART The Universal Asynchronous Receiver Transmitter UART module provides communication with external devices such as modems and other serial devices Key features of the UART include the following e Full duplex operation e Full 8 wire serial interface e Direct support of the Infrared Data Association IrDA mechanism e Robust receiver data sampling with noise filtering e 16 word FIFOs for transmit and receive block addressable with the LDM and STM instructions e 7 or 8 bit characters with optional even or odd parity and one or two stop bits BREAK signal generation and detection e 16x bit clock generator providing bit rates from 300 bps to 525 Kbps e Four maskable interrupts e RTS interrupt providing wake from STOP mode e Low power modes e Internal or external 16x clock e Far end baud rate can be automatically determined autobaud The UART performs all normal operations associated with start stop asynchronous communication Serial data is transmitted and received at standard bit rates in either NRZ or IrDA format
272. When the IDCODE instruction is selected the operation of the test logic has no effect on the operation of the on chip system logic as required by the IEEE 1149 1 standard 15 1 3 2 4 ENABLE_MCU_ONCE B 3 0 0011 The ENABLE_MCU_ONCE instruction is not included in the IEEE 1149 1 standard It is provided as a public instruction to allow the user to perform system debug functions When the ENABLE_MCU_ONCE instruction is decoded the DSP JTAG controller is set to the BYPASS mode This is the only function performed by the DSP controller OnCE operation in the MCU is controlled by the MCU s OnCE TAP 15 1 3 2 5 HIGHZ B 3 0 0100 When the HIGHZ instruction is invoked all output drivers including the two state drivers are turned off i e put in the high impedance state and the Bypass Register is selected The HIGHZ instruction also asserts internal reset for the DSP56652 core system logic to force a predictable internal state while performing external boundary scan operations In this mode all internal pullup resistors on all the pins except the TMS TDI and TRST pins are disabled 15 1 3 2 6 CLAMP B 3 0 0101 The CLAMP instruction selects the 1 bit Bypass Register as the serial path between TDI and TDO while allowing signals driven from the component pins to be determined from the BSR During testing of ICs on PCB it may be necessary to place static guarding values on signals that control operation of logic not involved in the te
273. X FFAC Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 High Byte Low Byte Motorola Programmer s Data Sheets E 89 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer BBP BBPPDR BBP Port Data Register Address X FFAD Reset 0000 Read Write Port Data Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BBPPD5 BBPPD4 BBPPD3 BBPPD2 BBPPD1 BBPPDO PEN Description 0 Port pins are tri stated 1 Port pins enabled B B P P C H BBPPCn Description BBP Port Control Register 0 Pin configured as GPIO Address X FFAF Reset 0000 1 Pin configured as SAP Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BBPPC2 BBPPC1 BBPPCO BBPDDR BBPDDn Description BBP Data Direction Register 0 Pin is input Address X FFAE Reset 0000 1 Pin is output Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BBPDD5 BBPDD4 BBPDD3 BBPDD2 BBPDD1 BBPDDO Reserved E 90 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Motorola Programmer s Data Sheets E 91 For More Information On This Product Go to www freescale com Freescale Semico
274. X can accept more data 11 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers UCR1 UART Control Register 1 0020 4080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O TxFL 1 0 TRDYIE TXEN RxFL 1 0 RRDYIE RxEN IREN TXEIE RTSDIE SNDBRK DOZE UEN RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 6 UCR1 Description Name Description Settings TXFL 1 0 Transmit FIFO Interrupt Trigger Level These 00 One FIFO slot default Bits 15 14 bits determine the number of available registers 01 Four FIFO slots in UTX required to indicate to the MCU that space 10 Eight FIFO slots is available to write data to be transmitted When 11 Fourteen FIFO slots the number of available registers rises above this threshold the TRDY bit in USR is set and a maskable interrupt can be generated TRDYIE Transmitter Ready Interrupt Enable Setting O Interrupt disabled default Bit 13 this bit enables an interrupt when the space 1 Interrupt enabled available in UTX reaches the threshold determined by TxFL 1 0 Note Either the EUTX bit in the NIER or the EFUTX bit in the FIER must also be set in order to generate this interrupt see page 7 7 TXEN Transmitter Enable Setting this bit enables the O Transmitter disabled default Bit 12 UART trans
275. a and stop bits and checking for parity according to the configuration in UCR2 When a complete character is decoded the data Motorola UART 11 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Operation is written to the data field in a URX register and the CHARRDY bit in that register is set If a valid stop bit is not detected a frame error is flagged by setting the URX FRMERR bit A parity error is flagged by setting the PRERR bit If a BREAK frame is detected the BRK and FRMERR flags are set If the URX is about to overflow i e the FIFO is full as another character is being received the OVRRUN flag is set If any of these four flags is set the ERR bit is also set If the number of unread words exceeds a threshold programmed by the RxFL 1 0 bits in UCRI the RRDY bit in USR is set and an interrupt is generated if the RRDYIE bit in UCRI has been set Adjusting the threshold to a value of one can effectively generate an interrupt every time a character is ready Reading the URX clears the interrupt and all the flags The CTS pin can be asserted to enable the far end transmitter and deasserted to prevent receiver overflow CTS is driven by receiver hardware if the CTSC bit in UCR2 is set The pin is driven by software via the CTSD bit in UCR2 if CTSC is cleared 11 3 3 UART Clocks The clock generator provides a 16x bit clock for the transmitter and receiver Software can select eit
276. abled EPT2 Description 0 Interrupt source is masked EMDI Description 1 Protocol Timer MCU2 interrupt 0 Interrupt source is masked source enabled 1 MDI interrupt source enabled EUTX Description 0 Interrupt source is masked ESCP Description 1 UART Transmitter Ready interrupt 0 Interrupt source is masked source enabled 1 SIM Card Tx Rx or Error interrupt source enabled ESMPD Description 0 Interrupt source is masked ETPW Description 1 SIM Auto Power Down interrupt 0 Interrupt source is masked bled A 1 General Purpose Timer PWM interrupt source enabled EURX Description 0 Interrupt source is masked EPIT Description 1 UART Receiver Ready interrupt source enabled 0 Interrupt source is masked 1 Periodic Interrupt Timer interrupt source enabled 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EURX ESMPD EUTX EPT2 EPT1 EPTO EPTM EQSPI EMDI ESCP ETPW EPIT 0 0 0 0 NOTE NIER can only be written as a 32 bit Reserved Motorola Programmer s Data Sheets E 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer M C U nte rru pts EINT4 Desc
277. abled default Bit 8 the MCP bit in the DSR is set and the MNMI bit in 1 Maskable interrupts enabled the MCVR is clear a maskable command interrupt is issued If MNMI is set MCIE is ignored In this case if the MCP bit in the DSR is set a non maskable interrupt is issued DMF 2 0 DSP to MCU Flags General purpose flag bits that are reflected on the MCU side in the MF 2 0 bits Bits 2 0 in the MSR 5 24 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers DSR DSP Side Status Register X FF8B BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O DTEO DTE1 DRFO DRF1 DGIRO DGIR1 DTIC MCP DWSC MPM1 MPMO DEP DF 2 0 RESET 1 1 0 0 0 0 0 0 0 0 0 n Table 5 18 DSR Description Name Type Description Settings DTEO R DSP Transmit Register 0 Empty Indicates O Last transmission to MRRO has not Bit 15 if the MCU has read the most recent been read transmission to MRRO This bit is subject to 1 Last transmission to MRRO has been DSP pipeline restrictions See Table 5 6 on read default page 5 15 DTE1 R DSP Transmit Register 1 Empty Indicates O Last transmission to MRR1 has not Bit 14 if the MCU has read the most recent been read transmission to MRR1 This bit is subject to 1 Last transmission to MRR1 has been DSP pi
278. ad WAIT CSEN Description states 1 REA 0 Chip Select function is disabled and CSO pin is an output WSC 0 3 Description 1 Chip Select function is enabled Binary value of number of external memory wait states 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSC3 WSC2 WSC1 WSCO WWS EDC CSA OEA WEN EBC DSZ1 DSZO SP WP CSEN Reserved E 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer E M EBC Description G S C R2 0 Read and write accesses both assert EBO 1 Chip Select Register 2 Address 0020 1008 1 Only write accesses can assert Reset uuuu Read Write WEN Description DSZ1 DSZO Description 0 The EBO T signals are negated 0 0 8 bit port on D 8 15 pins normally 0 1 8 bit port on D 0 7 pins 1 The EBO 1 signals are negated half 1 0 16 bit port on D 0 15 pins a clock cycle earlier on write accesses 1 1 Reserved OEA Description p 7 SP Description 0 The OE signal is negated normally 0 User mode accesses allowed 1 The OE signal is asserted half a clock cycle later on re
279. ad accesses 1 User mode accesses prohibited CSA Description z WP Description 0 The CS signal is asserted normally 0 Writes are allowed 1 The CS signal is asserted one l cycle later on read and write 1 Writes are prohibited accesses and an extra cycle inserted between back to back Cyclas PA Description EDC Description 0 CS pin at logic high 0 No delay occurs after a read cycle 1 CS pin at logic low 1 One clock cycle is inserted after a head cycle CSEN Description TENES 0 Chip Select function is disabled WWS Description and CSO pin is an output 0 Read and write WAIT states same 1 Chip Select function is enabled 1 Write WAIT states Read WAIT states 1 WSC 0 3 Description Binary value of number of external memory wait states 31 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSC3 WSC2 WSC1 WSCO WWS EDC CSA OEA WEN EBC DSZ1 DSZO SP WP PA CSEN Reserved Motorola Programmer s Data Sheets E 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer E M EBC Description C S C R3 0 Read and write accesses both assert EBO 1 Chip Select Register 3 a A
280. ain a snapshot of system data and control signals The snapshot occurs on the rising edge of TCK in the Capture DR controller state The data can be observed by shifting it transparently through the BSR Note Since there is no internal synchronization between the JTAG clock TCK and the system clock CLK the user must provide some form of external synchronization to achieve meaningful results The second function of SAMPLE PRELOAD is to initialize the BSR output cells prior to selection of EXTEST This initialization ensures that known data appears on the outputs when entering the EXTEST instruction Motorola JTAG Port 15 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56600 Core JTAG Operation 15 1 3 2 3 IDCODE B 3 0 0010 The IDCODE instruction selects the ID register and the system logic controls the I O pins This instruction is provided as a public instruction to allow the manufacturer part number and version of a component to be determined through the TAP The ID register is described in Section 15 2 3 on page 15 10 Since the bypass register loads a logic O at the start of a scan cycle whereas the ID register loads a logic 1 into its least significant bit examination of the first bit of data shifted out of a component during a test data scan sequence immediately following exit from Test Logic Reset controller state shows whether such a register is included in the design
281. aitl jclr DRF1 x DSR waitl wait till DRR1 is full movep x DRR1 a0 movep a0 x lt lt BPMRL movep al x lt lt BPMRH nop movep X BPMRG p r0 write to pram512 nop _loop jmp lt 0 endsec end Motorola DSP56652 DSP Bootloader A 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program A 28 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix B Equates and Header Files This appendix provides the equates for both the MCU and DSP in the DSP56632 as well as a C include file for the MCU If code for external bootstrap loading is developed a file containing this listing called ioequ asm should be included in the bootstrap executable B 1 MCU Equates DSP56651 DSP56652 M CORE Assembly equates Revision History 1 0 may 28 1998 16kb on chip rom equ mcu ram base address 0x00000000 equ mcu ram size 0x00004000 2kb on chip ram equ mcu ram base address 0x00100000 equ mcu ram size 0x00000800 peripheral space equ mcu peripherals base address 0x00200000 0x00300000 through Ox3fffffff is reserved external memory equ cs0 base address 0x40000000 equ csl base address 0x41000000 equ cs2 base address 0x42000000 equ cs3 base address 0x43000000 equ cs4 base address 0x44000000 equ cs5 base address 0x45000000 0x4600
282. al normally transfers unless the next cycle is a read cycle to 1 Extra idle cycle inserted in back to back the same CS bank to eliminate data bus external transfers unless the next cycle is contention This is useful for slow memory and a read cycle to the same CS peripherals that have long CS or OE to output data tri state times CSA Chip Select Assert When CSA is set Chip 0 Chip Select asserted normally i e as Bit 9 Select is asserted one clock cycle later during both early as possible no idle cycle inserted read and write cycles and an idle cycle is inserted 1 Chip Select asserted one cycle later idle between back to back external transfers Useful for cycle inserted in back to back external devices that require additional address setup time transfers and address data hold times If WSC 3 0 0000 the CSA bit is ignored OEA OE Assert When OEA is set OE is asserted one 0 OE asserted normally i e as early as Bit 8 half clock later during a read to the CS s address possible space Cycle length is not affected and write 1 OE asserted one half cycle later during a cycles are not affected If WSC 3 0 0000 OEA is read ignored and OE is asserted for half a clock only If EBC in the corresponding register is cleared the EBO 1 outputs are similarly affected WEN Write EB Negate When WEN is set EBO 1 are O EBO 1 negated normally i e as late as Bit 7 negated one half clock earlier during a write to the poss
283. al operations greater than 32 bits A 16 entry alternate register file is provided to minimize exception processing overhead and the CPU supports both vectored and auto vectored interrupts The user programming model contains the program counter sixteen 32 bit general purpose registers and the carry bit A separate supervisor mode is provided for exception processing The supervisor programming model includes all of the user registers plus an additional sixteen 32 bit general purpose registers 12 control registers and 5 scratch registers For a complete description of MeCORE architecture refer to the MeCORE Reference Manual 1 2 1 2 MCU Side Peripherals The MCU side peripherals for the DSP56652 support a variety of I O functions including radio channel timing signal generation periodic interrupts smart card interface LCD displays and key pads e A keypad port supports up to 8 rows and 8 columns The QSPI enables serial communication to multiple peripheral devices through a single port Motorola Introduction 1 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview The SCP provides user information to an external device through a smart card port e A UART connects to a modem or another computer e An edge I O port enables up to eight external interrupts e An interrupt controller prioritizes up to 32 peripheral interrupts e Four timers are provided incl
284. alue in a down counter matches each TIC value an event represented by the corresponding event code is generated The result is a series of events with specific timing and sequence 10 1 Protocol Timer Architecture This section describes the PT functional blocks including the timing components event table and event generation hardware A block diagram of the PT is shown in Figure 10 1 Motorola Protocol Timer 10 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Protocol Timer Architecture MCU Peripheral Bus MCU Interface Address 8 1 JE Data 15 0 MTPTR 6 0 Frame Table 0 E UE Frame Table 1 FT EC 6 0 7 RxPTR 6 0 RxEC 6 0 7 Rx Macro Table TxPTR 6 0 Tx_EC 6 0 7 I Tx Macro Table 8 TDPTR 6 0 OUT RTIC 13 0 Rx Ea 4 QSPI Triggers ATIC 13 0 14 FT Hit 14 DSP MCU Interrupts 7 CFE CFNI CFC VAB 7 1 CTIC MCU_CLK Interrupt E Generator RSNI DSPI RSPC 5 RSC MOD 2400 4 MCU SPBP Interrupts Error E MCU Accessible Detector Figure 10 1 Protocol Timer Block Diagram 10 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Protocol Timer Architecture 10 1 1 Timing Signals and Components The Time Interval Clock Generator TICG generates the primary timing PT reference signal th
285. alue stored in one of these registers the corresponding output compare function is triggered TICR1 Input Capture 1 Register 0020 600E TICR2 Input Capture 2 Register 0020 6010 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O TICRn 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM When TCNT equals the value stored in one of these registers the corresponding input compare function is triggered PWOR PWM Output Compare Register 0020_6012 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O PWOR 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When PWCNT equals the value written to this register the pulse is initiated TCNT Timer Counter 0020 6014 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O TCNT 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This read only register reflects the value of the GP timer counter TCNT PWMR PWM Modulus Register 0020 6016 Biti5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bito PWMR 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The value written to this register is loaded into the PWCNT when the PWM is enabled and each time PWCNT rolls over The PWCNT roll over period equals the value loaded 1 PWCNT PWM Counter 0020 6018 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 PWCNT 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Thi
286. ammar dictates Reset refers to the Reset state The word pin is a generic term for any pin on the chip Because of on chip pin multiplexing more than one signal may be present on any given pin Pins or signals that are asserted low made active when pulled to ground have an overbar over their name for example the SSO pin is asserted low Motorola xxiii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hex values are indicated with a dollar sign preceding the hex value as follows X SFFFF is the X memory address for the Interrupt Priority Register Core IPR C Code examples are displayed in a monospaced font as shown in Example 1 Example 1 Code Example BFSET 0007 X PCC Configure line 1 MISO0 MOSIO SCKO for SPI masterline 2 SSO as PC3 for GPIO line 3 e In code examples the names of pins or signals that are asserted low are preceded by a tilde In the previous example line 3 refers to the SSO pin shown as sso e The word assert means that a high true active high signal is pulled high to Vcc or that a low true active low signal is pulled low to ground The word deassert means that a high true signal is pulled low to ground or that a low true signal is pulled high to Vcc These conventions are summarized in Table 1 Table 1 Signal States Signal Symbol Logic State Signal State Voltage PIN True Asserted G
287. an internal latch and driven on any port pin that is configured as an output Reads of this register return the value sensed on input pins and the latched data driven on outputs Motorola Queued Serial Peripheral Interface 8 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory 8 26 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 9 Timers This section describes three of the four DSP56652 timer modules controlled by the MCU e The periodic interval timer PIT creates a periodic signal that is used to generate a regularly timed interrupt It operates in all low power modes The watchdog timer protects against system failures by resetting the DSP56652 if it is not serviced periodically The watchdog can operate in both WAIT and DOZE low power modes Its time out intervals are programmable from 0 5 to 32 seconds for a 32 kHz input clock e The pulse width modulator PWM and general purpose GP timers run on independent clocks derived from a common MCU CLK prescaler The PWM can be used to synthesize waveforms The GP timers can measure the interval between external events or generate timed signals to trigger external events The protocol timer is described in Chapter 10 9 1 Periodic Interrupt Timer The PIT is a 16 bit set and forget timer that
288. ansmitter side and sets a receiver full bit in the status register on the receiver side which can trigger a maskable receive interrupt on the receiver side if so programmed 5 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Messages and Control 3 Reading a receive register automatically clears the receiver full bit in the status register on the receiver side and sets the transmitter empty bit in the status register on the transmitter side which can trigger a maskable transmit interrupt on the transmitter side if so programmed 4 Three general purpose flags are provided for each transmitter and reflected in the status register at the receiver side The symmetry of the MDI registers is illustrated in Figure 5 4 and Table 5 2 MCU Module Bus DSP Peripheral Bus Figure 5 4 MDI Register Symmetry Table 5 2 MDI Registers and Symmetry MCU Registers DSP Registers Acronym Name Acronym Name MRRO MCU Receive Register 0 DTRO DSP Transmit Register 0 MRR1 MCU Receive Register 1 DTR1 DSP Transmit Register 1 MTRO MCU Transmit Register 0 DRRO DSP Receive Register 0 MTR1 MCU Transmit Register 1 DRR1 DSP Receive Register 1 MSR MCU Status Register DCR DSP Control Register MCR MCU Control Register DSR DSP Status Register MCVR MCU Command Vector Register The message exchang
289. any of the following circumstances The queue transfer is completed and the queue becomes inactive A higher priority queue is asserted The MCU issues a HALT command QA 3 0 R Queue Active The QSPI sets a queue s QA O Queue not active default Bits 11 8 bit when it receives a transfer trigger for that 1 Queue active queue and clears the bit upon completion of the queue transfer HALTA R 1C Halt Acknowledge Flag The QSPI asserts 0 No Halt since last acknowledge or Bit 6 this bit when it has come to an orderly halt at current halt has not been the request of the MCU via an assertion of the acknowledged default HALT bit If the HALT bit is asserted while the 1 Current Halt has been QSPI is transferring a queue the QSPI acknowledged continues the transfer until it either reaches the first sub queue boundary or until it reaches a PAUSE NOP or EOQ command depending on the value of the HMD bit for that queue Then the QSPI asserts HALTA clears the QX bit for the executing queue and halts If the HALT bit is asserted while the QSPI is idle HALTA is asserted and the QSPI halts immediately If the HLTIE bit is set in the SPCR an interrupt is generated to the MCU when HALTA is asserted The MCU clears HALTA by writing it with 1 Motorola Queued Serial Peripheral Interface 8 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers
290. ard after it is inserted see page 12 6 card NKPE NACK on Parity Error Determines if a NACK O No NACK sent default Bit 2 signal is sent SIMDATA pin pulled low if a parity 1 NACK sent on parity error error is detected This affects both the SCP and the smart card SCTE SCP Transmit Enable Setting this bit allows O Disabled default Bit 1 data written to the transmit buffer to be loaded to 1 Enabled the transmit shift register and shifted out on the SIMDATA pin A transmission in progress when SCTE is cleared is completed before the transmitter is disabled SCRE SCP Receive Enable Setting this bit allows 0 Disabled default Bit 0 data received on the SIMDATA pin to be shifted 1 Enabled into the receive shift register and loaded to the receive FIFO A reception in progress when SCRE is cleared is completed before the receiver is disabled Motorola Smart Card Port 12 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Registers SCACR Smart Card Activation Control Register 0020_B002 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 SCCLK SCRS SCDPE SCPE APDE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 3 SCACR Description Name Description Settings SCCLK Smart Card Clock Setting this bit drives 0 SIMCLK pulled low default Bit 4 SIM_CLK to the smart card on the SIMCLK pin
291. ata Register E 49 Periodic Interrupt PITCSR PIT Control and Status Register E 50 Timer PITMR PIT Modulus Register E 50 PITCNT PIT Counter E 50 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table E 1 List of Programmer s Sheets Continued Register Functional Block Page Acronym Name Watchdog Timer WCR Watchdog Control Register E 51 WSR Watchdog Service Register E 51 G P Timer and TPWCR Timers and PWM Control Register E 52 PWM TPWMR Timers and PWM Mode Register E 53 TPWSR Timers and PWM Status Register E 54 TPWIR Timers and PWM Interrupts Enable Register E 55 TOCR1 Timer 1 Output Compare Register E 56 TOCR3 Timer 3 Output Compare Register E 56 TOCR4 Timer 4 Output Compare Register E 56 TICR1 Timer 1 Input Capture Register E 56 TICR2 Timer 2 Input Capture Register E 56 PWOR PWM Output Compare Register E 57 TCNT Timer Count Register E 57 PWMR PWM Modulus Register E 57 PWCNT PWM Counter E 57 Protocol Timer PTCR PT Control Register E 58 PTIER PT Interrupt Enable Register E 59 PTSR PT Status Register E 60 PTEVR PT Event Register E 61 TIMR Time Interval Modulus Register E 61 CTIC Channel Time Interval Counter E 61 CTIMR Channel Time Interval Modulus Register E 62 CFC Channel Frame Counter E 62 CFMR Channel Frame Mo
292. ation On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview 1 2 1 1 Core Description The M eCORE MCU utilizes a four stage pipeline for instruction execution The instruction fetch instruction decode register file read execute and register write back stages operate in an overlapped fashion allowing most instructions to execute in a single clock cycle Sixteen general purpose registers are provided for source operands and instruction results The execution unit consists of a 32 bit arithmetic logic unit ALU a 32 bit barrel shifter a find first one unit FFO result feed forward hardware and miscellaneous support hardware for multiplication and multiple register loads and stores Arithmetic and logical operations are executed in a single cycle with the exception of the multiply and divide instructions The FFO unit operates in a single clock cycle The program counter unit contains a PC incrementer and a dedicated branch address adder to minimize delays during change of flow operations Memory load and store operations are provided for byte halfword and word 32 bit data with automatic zero extension of byte and halfword load data These instructions can execute in two clock cycles Load and store multiple register instructions allow low overhead context save and restore operations A single condition code carry C bit is provided for condition testing and to implement arithmetic and logic
293. atus register that the DSP bootloader program polls to determines when a new message has been received in MDI_RO 5 Ensure that the response to a message does not overwrite that message Each MCU message that invokes a long message reply from the DSP defines the offset in MDI shared memory where the DSP stores the response Care should be taken so that no portion of the reply overwrites any portion of the original message The DSP may need to access the original message while it is writing its response message Motorola DSP56652 DSP Bootloader A 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 4 Example of Program Download and Execution Example A 1 provides a short outline in pseudo C code for downloading and starting a program in normal boot mode In this example all long messages start at the beginning of MDI shared memory the DSP program exists in a long array called dsp programr the program length is contained in a variable called program length and the program starting address is dsp program address Example A 1 Normal Boot unsigned short mdimem unsigned short MDI MEM ADDR unsigned short MTRO unsigned short MDI MIRO volatile unsigned short MRRO unsigned short MDI_MRRO volatile unsigned short MSR unsigned short MDI_MSR prepare to download to the DSP write long message info in shared mem mdimemH memory wr
294. ave offset needed for return add ZMDI base a add MDI base address move al rl return mdi address move mem_check b0 write memory check confirm move b0 x r1 as header move xl a and e000 a keep upper 3 bits cmp pram512 a jeq lt pram check else it s not a valid memory space move fail inv mem b0 return code fail invalid memory A 24 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com pram check e Motorola Freescale Semiconductor Inc Bootstrap Program move b0 x r1 mp lt mem check return check 512 word p ram space e e e L move PATTERNS r3 r3 points to p test patterns do NUM_PATTERNS 4 loop o Up wB movem p 13 n4 get BackGround Pattern high word movem p r3 n3 get BackGround Pattern low word movep n4 x BPMRH movep n3 x BPMRL move 70 r0 r0 points to start of Memory rep 512 fill Memory with BG Pattern up wB movep X BPMRG p r0 Up rB wD rD clr a clr b move 70 r0 movem p r3 n6 get Data Pattern high word movem p r3 n5 get Data Pattern low word movep n6 x BPMRH movep n5 X BPMRL do 512 loop i test all locations move n3 a0 BG Pattern value to A move n4 al movep p rO x BPMRG read BackGround Pattern gt BPMRG move ZSABCD n2 change gdb movep x BPMRL b0 movep x BPMRH b1 cmp a b was the Memory data as expected nop brkne movep n5 X BPMR
295. bit equ prot ptier rsnie 0x2 reference slot number intpt enable bit equ prot ptier mcie0 0x4 MCU interrupt 0 enable bit equ prot ptier mciel 0x5 MCU interrupt 1 enable bit equ prot ptier mcie2 0x6 MCU interrupt 2 enable bit equ prot ptier dsie 0x9 DSP interrupt enable bit equ prot ptier dvie 0xa DSP vector interrupt enable bit equ prot ptier thie 0xb Timer haltinterrupt enable bit equ prot ptier terie 0xc Timer error interrupt enable bit bits of the Protocol Timer Interrupt Enable Register PTIER NEW NAMES equ prot tier cfie 0x0 channel frame interrupt enable bit equ prot tier cfnie 0x1 channel frame number intpt enable bit equ prot tier rsnie 0x2 reference slot number intpt enable bit equ prot tier mcie0 0x4 MCU interrupt 0 enable bit equ prot tier mciel 0x5 MCU interrupt 1 enable bit equ prot tier mcie2 0x6 MCU interrupt 2 enable bit equ prot tier dsie 0x9 DSP interrupt enable bit equ prot tier dvie Oxa DSP vector interrupt enable bit equ prot tier thie Oxb Timer haltinterrupt enable bit equ prot tier terie 0xc Timer error interrupt enable bit bits of the Timer Status Register TSTR old names equ prot tstr cfi 0x0 channel frame interrupt bit equ prot tstr cfni 0x1 channel frame number interrupt bit equ prot tstr rsni 0x2 reference slot number interrupt bit equ prot tstr mcui0 0x4 MCU interrupt 0 bit equ prot tstr mcui
296. bit Event Code field as shown in Figure 10 4 The RTIC value represents the delay in timer intervals from the previous macro event or from the macro call for the first macro event to the event specified in the EC field An RTIC value of 0 or 1 generates the event at the next time interval 15 6 0 Offset KN Byte Offset 0 N Byte Offset 1 15 13 0 z slti a iC Byte Offset 2 N Byte Offset 3 Figure 10 4 Macro Table Entry When a receive macro is called RxPTR is initialized to the first entry in the receive macro table The address of this first entry is contained in the RxBAR field in the Macro Table Base Address Register MTBAR The RTIC value of this first entry is loaded into a 14 bit down counter in the receive MTCU When this counter decremented by the TICK signal reaches zero the MTCU asserts an internal Rx Hit signal to the ECU which generates the event signal specified by the EC field of the macro pointer entry The macro pointer is incremented and the cycle repeats until an end_of_macro command is executed The transmit macro operates in similar fashion The base address of the transmit macro table is stored in the TxBAR field in MTBAR The TxPTR field in MTPTR is the address pointer A transmit MTCU generates an internal Tx Hit signal to the ECU 10 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Operation Macro
297. bit vector 0 bit bit bit bit vector 0 bit vector 0 bit bit bit bit vector 0 bit bit bit bit vector 0 bit bit bit bit vector 0 bit bit bit bit vector 0 bit bit bit bit bit bit vector 0 bit vector 0 bit bit bit to to to to to to to to to to to to to to to 19 15 7 4 2 2 4 Boundary Scan Register Boundary Scan Description Language For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Boundary Scan Description Language DGND linkage bit EVDD linkage bit EGND linkage bit FVDD linkage bit FGND linkage bit GVDD linkage bit vector 0 to 1 GGND linkage bit vector 0 to 1 HVDD linkage bit HGND linkage bit KVDD linkage bit KGND linkage bit BVDD linkage bit BGND linkage bit OVCC linkage bit vector 0 to 3 OVCCH linkage bit vector 0 to 3 QGND linkage bit vector 0 to 3 CS5 buffer bit RESERVED linkage bit ADDR20 buffer bit ADDR21 buffer bit use STD 1149 1 1994 all attribute COMPONENT CONFORMANCE of DSP56652 entity is STD 1149 1 1993 complies with Std 1149 1a 1993 attribute PIN MAP of DSP56652 entity is PHYSICAL PIN MAP constant PBGA196 PIN MAP STRING Dl D4 D2 D3 ADDR20 A2 x TOUT A3 C4 B4 A4 D5 C5 A5 B5 amp SPICS E7 B6 E6 D6 A6 amp HGND A7 amp QVCCH A8 G12 H5 P7
298. ble Controls the CKIH input buffer O Buffer enabled default Bit O 1 Buffer disabled if MCS is cleared Motorola Core Operation and Configuration 4 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generation PCTLO PLL Control Register O X FFFD BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O PD 3 0 MF 11 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 3 PCTLO Descriptions Name Description Settings PD 3 0 Predivider Factor Bits Concatenated with See Table 4 4 on page 4 7 Bits 15 12 PD 6 4 PCTL1 bits 11 9 to define the PLL input PDF MF 11 0 Multiplication Factor Bits Define the MF Bits 11 0 applied to the PLL input frequency MF 11 0 MF 000 1 default 001 2 002 3 FFE 4095 FFF 4096 4 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generation PCTL1 PLL Control Register 1 X FFFC BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O PD 6 4 COD PEN PSTP XTLD XTLR DF 2 0 RESET 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Table 4 4 PCTL1 Description Name Description Settings PD 6 4 Predivider Factor Concatenated with PD 3 0 Bits 11 9 from PCTLO to define the PLL input fre
299. ble 6 9 QPDR Description Name Description EMD 5 0 Emulation Port GPIO Data 5 0 Each of these bits contains data for the corresponding Bits 7 0 Emulation Port pin if the port is configured as GPIO Writes to EMDR are stored in an internal latch and driven on any port pin configured as an output Reads of this register return the value sensed on input pins and the latched data driven on outputs Motorola External Interface Module 6 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Registers 6 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 7 Interrupts This section describes both the MCU and DSP interrupt controllers including the various interrupt and exception sources and how they are configured and prioritized The Edge I O port which provides eight pins for external MCU interrupts is also described 7 1 MCU Interrupt Controller The MCU interrupt controller combines the speed of a highly microcoded architecture with the flexibility of polling techniques commonly employed in RISC designs The result 1s a centralized mechanism that permits polling and prioritizing of the 32 interrupt sources with minimal software overhead This mechanism includes the following features e Find First One instruction This instruction provides a fast mechanism to prioritize pe
300. bled and each time the timer is serviced The timer must be serviced before the counter rolls over or it will reset the system The timer can only be serviced by performing the following steps in sequence 1 Write 5555 to the WSR 2 Write SAAAA to the WSR 9 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Watchdog Timer Any number of instructions can occur between these two steps In fact it is recommended that the steps be in different code sections and not in the same loop This prevents the MCU from servicing the timer when it is erroneously bound in a loop or code section The watchdog timer is subject to the same synchronization logic restrictions as the PIT i e MCU_CLK gt CKIL Figure 9 3 is a block diagram of the Watchdog Timer DOZE From MCU WDZE WDBG Debug From MCU Reset Underflow WDE One Time Write 2Hz for CKIL 32kHz CKIL NOTE Debug is an active low signal from the MCU Prescaler 214 indicating Debug mode Figure 9 3 Watchdog Timer Block Diagram The timer is unaffected by WAIT mode and halts in STOP mode It can either halt or continue to run in DOZE mode depending on the state of the WDZE bit in the WCR In Debug mode the watchdog timer can either halt or continue to run depending on the state of the WDBG bit in the WCR If WDBG is set when the MCU enters Debug mode
301. buffer to the Data RAM overwriting the transmitted data The MCU can then read the received data from RAM The Control RAM is a 64 x 16 bit block that contains a control halfword for each datum in the Data RAM The control information includes chip select or QSPI command end of queue end of transmission or no activity data width of a queue entry 8 or 16 bits receive enable and pause at end of a sub queue Motorola Queued Serial Peripheral Interface 8 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Operation Each datum and corresponding control halfword constitute a queue entry The MCU initializes the Data RAM and the Control RAM by loading them with transmission data and queue transfer control information 8 3 QSPI Operation The QSPI operates in master mode and is always in control of the SPI bus Data is transferred as either least or most significant bit first depending on the LSBFn bit in SCCRa A transfer can be either 8 or 16 bits depending on the value of the BYTE bit for the queue entry When the BYTE bit is set the least significant byte of the Data RAM entry is transferred and if receiving is enabled the least significant byte of the data halfword is valid while the most significant byte is filled with Os The QSPI has priority in using its internal bus If an MCU access occurs while the QSPI is using the bus the MCU waits for one cycle 8 3 1 Initialization
302. cale Semiconductor Inc Test Registers 15 2 Test Registers The DSP core implementation includes three test registers a Boundary Scan Register BSR a 1 bit Bypass Register and a 32 bit Identification Register ID 15 2 1 Boundary Scan Register BSR The Boundary Scan Register BSR in the DSP core JTAG implementation contains bits for all device signal and clock pins and associated control signals In addition the BSR contains a data direction control bit for each bidirectional pin Boundary scan bit definitions are provided in the Boundary Scan Description Language BSDL listing in Appendix C Note As a compliance enable pin MCU_DE is not included in the BSR definition 15 2 2 Bypass Register The Bypass Register allows the serial data path to circumvent the DSP BSR It is activated by the HIGHZ CLAMP and BYPASS instructions When the Bypass Register is selected the shift register stage is set to a logic zero on the rising edge of TCK in the Capture DR controller state Therefore the first bit to be shifted out after selecting the Bypass Register is always a logic zero A drawing of the Bypass Register is shown in Figure 15 5 Shift DR To TDO From TDI CLOCKDR Figure 15 5 JTAG Bypass Register 15 2 3 Identification Register The ID register contains the manufacturer part number and version of the DSP36652 It is read by invoking the IDCODE command It can be used to determine the manufacturer of a componen
303. cleared and the least significant byte which holds the received character contains random data Table 11 4 URX Description Name Description Settings CHARRDY Character Ready Set when the complete O Character not ready default Bit 15 character has been received and error conditions 1 Character ready have been evaluated Cleared when the register is read ERR Error Detected Set when any of the error 0 No error detected default Bit 14 conditions indicated in bits 13 10 is present 1 Error detected Cleared when the register is read OVRRUN Receiver Overrun Set when incoming data is O No overrun default Bit 13 ignored because the URX FIFO is full An overrun 1 Overrun error error indicates that MCU software is not keeping up with the receiver Under normal conditions this bit should never be set Cleared when the register is read FRMERR Frame Error Set when a received character is O No framing error detected default Bit 12 missing a stop bit indicating that the data may be 1 Framing error detected for this character corrupted Cleared when the register is read REAK not detected default BRK BREAK Detect Set when all bits in the frame 0 1 REAK detected for this character Bit 11 including stop bits are zero indicating that the current character is a BREAK FRMERR is also set If odd parity is employed PRERR is also set BRK is cleared when the register is read
304. cleared setting WSC 3 0 0000 results in Number of Wait States one clock transfers WSC 3 0 0001 results in wsc _ E two clock transfers and WSC 3 0 1111 results in 3 0 WWS 0 WWS EI 16 clock transfers When WSC 3 0 0000 the Read Write Read Write WEN OEA and CSA bits are ignored 0000 0 0 0 1 0001 1 1 1 0010 2 2 2 3 1101 13 13 13 14 1110 14 14 14 15 1111 15 15 15 15 Motorola External Interface Module 6 9 For More Information On This Product Go to www freescale com ElM Registers Freescale Semiconductor Inc Table 6 6 CSCRn Description Continued Name Description Settings WWS Write Wait State Specifies whether an additional O Reads and writes are same length Bit 11 wait state is inserted for write cycles When WWS 1 Writes have an additional wait state is set an additional wait state is inserted for write except when WSC 3 0 1111 cycles unless WSC 3 0 1111 which results in a 16 clock cycle write time regardless of the WWS bit Read cycles are not affected When this bit is cleared reads and writes are of the same length Setting this bit is useful for writing to slower memories such as Flash memories that require additional data setup time EDC Extra Dead Cycle When set inserts an idle cycle O Back to back external transfers occur Bit 10 after a read cycle for back to back extern
305. clock generator pac 1 Bit clock derived from IRQ7 DTR 1 RTS pin is ignored pin input 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 IRTS CTSC CTSD PREN PROE STPB CHSZ CLKSRC UBRGR UART Bit Rate Generator Register Address 0020_4084 Reset 0000 Read Write Clock Divider Bits Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 69 Freescale Semiconductor Inc Application Date Programmer RTSS Description UA RT 0 RTS pin is high inactive 1 RTS pin is low active U S R TRDY Description UART Status Register 0 Unsent characters above TXFL 0 1 Address 0020_4086 Reset A000 1 Unsent characters below TXFL 0 1 Read Only RRDY Description TXE Description 0 Unread characters below RXFL 0 1 0 Unsent transmit data 1 Unread characters above RXFL 0 1 1 All transmit data has been sent RTSD Description 0 RTS pin has not changed state 1 RTS pin has changed state 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXE RTSS TRDY RRDY RTSD 0 0 0 0 0 0 0 0 0 0 0 UTS NOTE UART Test Register Address 0020 4088 This register is included for test
306. contain the primary lists of events to be triggered The base addresses of these tables are stored in the Frame Table Base Address Register FTBAR Each entry in a frame table has a 14 bit Absolute TIC field and a 7 bit Event Code field as shown in Figure 10 3 Only one of the frame tables is active at a given time the inactive table can be updated for later use The active table can be switched by encoding an end of frame switch or table change command If the active table is Frame Table 1 it can be switched to Frame Table O with the end of frame halt command 10 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Operation 15 6 0 Offset Byte Offset 0 N Byte Offset 1 15 13 0 E 2 Byte Offset 2 N Byte Offset 3 Figure 10 3 Frame Table Entry Frame table entries are subject to the following restrictions 1 All entries in each frame table must be in sequential order i e with decreasing ATIC fields 2 The ATIC value of each entry in a frame table must be less than the CTIC modulus CTIMR Only one event can be scheduled per ATIC An end_of_frame command must be executed before CTIC rolls over The delay and end_of_macro events are for macros only D get a com Writing to a frame table entry that is currently being executed can generate erratic results To guard against this possibility MCU software can be written so as not
307. control 1 amp 175 BC 6 SRDA bidir X 174 1 Z 176 BC 1 control 1 amp 177 BC 6 SIDA bidir X 176 1 Z 178 BC 1 control 1 amp 179 BC 6 PSTAT 3 bidir X 178 1 Z num cell port func safe ccell dis rslt 180 BC 1 control 1 amp 181 BC 6 PSTAT 2 bidir X 180 1 2Z Motorola Boundary Scan Register C 11 For More Information On This Product Go to www freescale com 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 end DSP56652 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 BC 1 BC 6 Freescale Semiconductor Inc Boundary Scan Description Language T PSTAT 1 T PSTAT 0 SIZ 1 LA SIZ 0 T CTS B T RTS B For More Information On This Product control bidir control bidir control bidir control bidir control bidir control bidir control bidir control bidir 182 184 186 188 190 192 194 196 DSP56652 User s Manual Go to www freescale com Motorola Freescale Semiconductor Inc Appendix D Programmer s Reference This appendix provides a set of reference tables to simplify programming the DSP56652 The tables include the following e Instruction set summaries for both the MCU and DSP e O memory maps listing the con
308. cter the UART completes transmission of the character before shutting off the transmitter Transmitter operation can also proceed without RTS by setting the IRTS bit in UCR2 In this case RTS has no effect on the transmitter or RTSD and cannot generate an interrupt A BREAK character can be sent by setting the SNDBRK bit in UCRI When the MCU sets SNDBRK the transmitter completes any frame in progress and transmits zeros sampling SNDBRK after every bit is sent UTX can be written with more transmit data while SNDBRK is set When it samples SNDBRK cleared the transmitter sends two marks before transmitting data if any in UTX Care must be taken to ensure that SNDBRK is set for a sufficient length of time to generate a valid BREAK When all data in UTX has been sent and the FIFO and shifter are empty the TXE bit in USR is set If the amount of untransmitted data falls below a programmed threshold the TRDY bit in USR is set The threshold can be set for one four eight or fourteen characters by writing TxFL 1 0 in UCR1 Both TXE and TRDY can trigger an interrupt if the TXEIE and TRDYIE bits respectively in UCRI are set The two interrupts are internally wire or d to the interrupt controller 11 3 2 Reception The RxD line is at a logic one when it is idle If the pin goes to a logic low and the receiver detects a qualified start bit it proceeds to decode the succeeding transitions on the RxD pin monitoring for the correct number of dat
309. cts these signals become general purpose outputs GPOs After reset these signals are GPOs that are driven high Chip select 5 This signal is asserted high based on the decode of the internal address bus bits A 31 24 of the access address When not configured as a chip select this signal functions as a GPO After reset this signal is a GPO that is driven low Motorola External Interface Module 6 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chip Select Address Ranges 6 2 Chip Select Address Ranges Each of the six chip select signals corresponds to a 16 Mbyte block in the MCU address space Note that only 22 address lines are available so only the first four Mbytes in each chip select space can be addressed An access above the 4 Mbyte limit modulo wraps back into the addressable space and is not recommended Table 6 2 lists the allocated and addressable ranges for each chip select Table 6 2 Chip Select Address Range Chip Select A 31 24 Allocated prada Space 16 Addressable Range 4 Mbytes cso 01000000 4000_0000 40FF_FFFF 4000_0000 403F_FFFF C81 01000001 4100 0000 41FF FFFF 4100 0000 413F FFFF cs2 01000010 4200_0000 42FF_FFFF 4200_0000 423F_FFFF CS3 91000011 4300_0000 43FF_FFFF 4300_0000 433F_FFFF C84 01000100 4400_0000 44FF_FFFF 4400_0000 443F_FFFF CSS 01000101 4500_0000 45FF_FFFF 4500_0000 453F_FFFF
310. cution Stalled 0 0 1 0 Execute Exception 0 0 1 1 Reserved 0 1 0 0 Processor in Stop Wait or Doze mode 0 1 0 1 Execution Stalled 0 1 1 0 Processor in Debug Mode 0 1 1 1 Reserved 1 0 0 0 Launch instruction 1 0 0 1 Launch Idm stm ldq stq 1 0 1 0 Launch Hardware Accelerator instruction 1 0 1 1 Launch Irw 1 1 0 0 Launch change of Program Flow instruction 1 1 0 1 Launch rte or rfi 1 1 1 0 Reserved 1 1 1 1 Launch jmpi or jsri 6 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Registers 1 Except rte rfi Idm stm Idq stq Irw hardware accelerator or change of flow instructions 6 4 ElM Registers CSCRO Chip Select O Control Register 0020_1000 CSCR1 Chip Select 1 Control Register 0020 1004 CSCR2 Chip Select 2 Control Register 0020 1008 CSCR3 Chip Select 3 Control Register 0020 100C CSCR4 Chip Select 4 Control Register 0020_1010 CSCR5 Chip Select 5 Control Register 0020_1014 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO WSC 3 0 WWS EDC CSA OEA WEN EBC DSZ 1 0 SP WP PA CSEN RESET CSO 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 CS1 1 0 CS2 1 0 CS3 1 0 CS4 1 0 CS5 0 0 Table 6 6 CSCRn Description Name Description Settings WSC 3 0 Wait State Control Bits Determine the number Bits15 12 of wait states for an access to the external device connected to the Chip Select When WWS is
311. cycles delay 001 2 SCK cycles delay 111 128 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay MCU_CLK 101 32 SCK cycles delay SCK 110 64 SCK cycles delay 2 3 SCKFD3 6 1 SCKDF3 0 5 1 111 128 SCK cycles delay All values for SCKDF3 0 6 are valid Sample values are shown LSBF3 Description 0 Data transferred MSB first ET SCKDFS 0 6 Description 1 Data transferred LSB first 000 0000 SCK MCU CLK 2 000 0001 SCK MCU CLK 4 CKPOL3 Description 000_0111 SCK MCU_CLK 16 0 SCK inactive at logic 1 100 0000 SCK MCU CLK 8 1 SCK inactive at logic 0 000 0100 SCK MCU CLK 10 TII 100 1011 SCK MCU CLK 96 CPHA3 Description m 111 1110 SCK MCU CLK 504 0 Data changes on first SCK transition 111_1111 SCK MCU_CLK 1 1 Data latches on first SCK transition 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPHA3 CKPOL3 LSBF3 DATR32 DATR31 DATR30 CSCKD32 CSCKD31 CSCKD30 SCKDF36 SCKDF35 SCKDF34 SCKDF33 SCKDF32 SCKDF31 SCKDF30 E 46 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programmer QSPI SCCR4 Serial Channel Control Register 4 Address 0020_5F1A Reset 0000 CSCKDF4 0 2 Assertion to Activation Delay 000 1 SCK cycl
312. d STOP STOP 0000 0000 0000 0100 Unaffected STQ STQ R4 R7 RX 0000 0000 0101 rrrr Unaffected SUBC SUBC RX RY 0000 0111 ssss rrrr C lt carryout SUBI SUBI RX IMM5 0010 010i iiii rrrr Unaffected SUBU SUBU RX RY 0000 0101 ssss rrrr Unaffected SUB RX RY SYNC SYNC 0000 0000 0000 0001 Unaffected TRAP TRAP TRAP NUMBER 0000 0000 0000 10ii Unaffected TST TST RX RY 0000 1110 ssss rrrr Set if RX amp RY 0 else bit is cleared TSTNBZ TSTNBZ RX 0000 0001 1001 rrrr Set to result of test WAIT WAIT 0000 0000 0000 0101 n a XOR XOR RX RY 0001 0111 ssss rrrr Unaffected XSR XSR RX 0011 1000 0000 rrrr Set to original value of RX 0 XTRBO XTRBO R1 RX 0000 0001 0011 rrrr Set if result 0 else bit is cleared D 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Instruction Reference Tables Table D 1 MCU Instruction Set Summary Continued Mnemonic Instruction Syntax Opcode C Bit XTRB1 XTRB1 R1 RX 0000 0001 001 O rrrr Set if result O else bit is cleared XTRB2 XTRB2 R1 RX 0000 0001 0001 rrrr Set if result 0 else bit is cleared XTRB3 XTRB3 R1 RX 0000 0001 0000 rrrr Set if result O else bit is cleared ZEXTB ZEXTB RX 0000 0001 0100 rrrr Unaffected ZEXTH ZEXTH RX 0000 0001 0110 rrrr Unaffected Motorola Programmer s Reference D 5 For More Information On This Product Go to www freescale com Freesca
313. d an interrupt is generated if the TIE bit in is set 5 Data is immediately shifted out from the shift register to the STDx pin clocked by the transmit bit clock 6 The cycle repeats from step 2 but not at any particular time If the Transmit Register is written before the current time slot has expired step 5 will not occur and the Transmit Register will not accept another word until the current time slot expires Although the SAP transmitter is double buffered only one word can be written to the Transmit Register even when the transmit shift register is empty Transmit underruns are impossible for on demand transmission and are disabled 14 4 2 Data Reception Data reception is enabled by setting the Receive Enable RE pin in SAPCRB or BBPCRB which allows or inhibits transfer from the shift register to the Receive Register Data is received on the SRDA or SRDB pin clocked into the receive shift register by the receive transmit clock When the number of bits received equals the expected word length as selected by the WL bits in SAPCRA or BBPCRA the shift register contents are transferred to the Receive Register SAPRX or BBPRX and the Receive Data Register Full RDF bit in the SAPSR or BBPSR is set If the Receive Interrupt Enable RIE bit in SAPCRB or BBPCRB is set an interrupt is generated Reading the receive register clears the RDF bit If the received word is the first word in a frame the Receive Frame Sync RFS bit in t
314. d cleared OF3 Bit 1 OF1 Bit O Motorola Timers 9 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM TPWIR Timers and PWM Interrupt Enable Register 0020_0006 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 PWOIE TOVIE PWFIE IF2IE IF1IE OFAIE OFSIE OF1IE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Either the ETPW bit in the NIER or the EFTPW bit in the FIER must be set in order to generate any of the interrupts enabled in the TPWIR see page 7 7 Table 9 6 GNRC Description Name Description Settings PWOIE PWM Count Rollover Interrupt Enable O Interrupt disabled default Bit 7 1 Interrupt generated when corresponding TPWSR flag bit is set TOVIE Timer Count Overflow Interrupt Enable Bit 6 PWFIE PWM Output Compare Flag Interrupt Enable Bit 5 IF2IE Input Capture 2 Interrupt Enable Bit 4 IF1IE Input Capture 1 Interrupt Enable Bit 3 OF4IE Output Compare 4 Interrupt Enable Bit 2 OF3IE Output Compare 3 Interrupt Enable Bit 1 OF1IE Output Compare 1 Interrupt Enable Bit 0 TOCR1 Output Compare 1 Register 0020 6008 TOCR3 Output Compare 3 Register 0020_600A TOCR4 Output Compare 4 Register 0020_600C Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O TOCRn 15 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When TCNT equals the v
315. d continuous BREAK TXFL 0 1 Description DOZE Description 00 Interrupt if TX FIFO has slot for 1 or more characters 0 UART enabled during DOZE mode 01 Interrupt if TX FIFO has slot for 4 1 UART disabled during DOZE mode or more characters 10 Interrupt if TX FIFO has slot for 8 UEN Description or more characters 0 UART disabled 11 Interrupt if TX FIFO has slot for 14 or more characters 1 UART enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXFL1 TXFLO TRDYIE TXEN RXFL1 RXFLO RRDYIE RXEN Reserved E 68 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer U A RT PREN Description 0 Parity disabled U C R 2 1 Parity enabled UART Control Register 2 PROE Description Address 0020_4082 0 E it Reset 0000 YSN PALY Read Write 1 Odd parity CTSD Description STPB Description 0 TS pin is inactive high 0 1 Stop bit 1 CTS pin is active low 1 2 Stop bits HSZ D ipti CTSC Description CHS esla dead 0 CTS pin controlled by CTSD 9 Tbit charactors 1 bit ch t 1 CTS pin controlled by receiver erg dead CLKSRC Description IRTS D ipti SE DAN 0 Bit clock generated from 16x bit 0 Transmit only when RTS pin is
316. d remain either unconnected or connected to Vcc to achieve minimal power consumption Also the TCK input is not blocked in STOP mode and should be externally connected to Vcc or ground 15 4 MCU TAP Controller The MCU contains a TAP controller to provide MCU OnCE support It is bypassed in JTAG compliant mode The MCU OnCE operating mode can be selected in two ways e Assertion of the MCU_DE line while the TAP controllers are in the Test Logic Reset state and the TRST input is deasserted e Shifting the ENABLE_MCU_ONCE command into the DSP TAP controller In the MCU OnCE mode the MCU and DSP TAP controllers are serially linked The TDI pin drives the MCU TAP controller TDI input and the MCU TAP controller TDO output drives the DSP TAP controller TDI input The combined Instruction Registers IRs and Data Registers DR s of the two controllers are connected effectively allowing both to be read or written from a single serial input stream The TMS TRST and TCK inputs of the two controllers are connected together forcing an identical sequence of state transitions to occur within the individual TAP controllers To return from the MCU OnCE configuration to JTAG compliant mode deassert the MCU_DE signal and assert TRST 15 4 4 Entering MCU OnCE Mode via JTAG Control Table 15 3 shows the TMS sequencing for entering MCU OnCE mode from JTAG compliant mode by shifting the ENABLE_MCU_ONCE command into the DSP TAP controller 15 1
317. d t ea E Nd Me SAP and BBP Interrupts s desit ee t Aen RS RR A Serial Audio Port Register Summary Baseband Port Register Summary List of Tables For More Information On This Product Go to www freescale com Xix Table 14 7 Table 14 8 Table 14 9 Table 14 10 Table 14 11 Table 14 12 Table 14 13 Table 15 1 Table 15 2 Table 15 3 Table 15 4 Table A 1 Table A 2 Table A 3 Table C 1 Table D 1 Table D 2 Table D 3 Table D 4 Table D 5 Table D 6 Table D 7 Table D 8 Table D 9 Table D 10 Table D 11 Table E 1 XX Freescale Semiconductor Inc SAP BBP CRA Description 0 0 cece eee eee eens 14 18 SAP BBP CRB Description 0 0c cece eee eens 14 19 SAP BBP CRC Description 0 0 eee eee 14 21 SAP BBP Status Register Description llle 14 22 SAP BBP PDR Description cari ta tea p eR es 14 24 SAP BBP DDR Description ya Maney Saw ev e 14 24 SAP BBP PCR DeSCHpLU ol1 5 ex sea eb kaw Medea eae EA 14 25 DSP TAG Pins os ia oe Oey POCHE RR READERS NEM SABRES 15 4 JTAG Instructions es Ls Ges ois o MERE ee e e ER 15 6 Entering MCU OnCE Mode 3 2 noo AR 15 13 Releasing the MCU and DSP from Debug Modes 15 14 DSP56652 Boot Modes 55 3 45 ian Nes P diass c on M ret edd A 2 Message Summary s 2 15 soa Vea ad SH A MR LAUS a A 4 SRA A A USE UELLE Ee A 5 BSR Bit Definitions a a MEI eh e a EIS C 2 MCU Instruction Set Summary 0 0 cee ee
318. d to their default values None of the rest of the DSP56652 system is affected Note MDIR assertion is ignored if the DSP is in STOP mode DSP Hardware Setting the DHR bit in the In addition to the MDI reset conditions above the entire DSP side is Reset MCR reset Memory including MDI shared memory is not affected MCU software should poll the DRS bit MSR bit 7 to determine when the reset sequence on the DSP side has ended and wait for PLL relock if the PLL is reprogrammed see page 5 5 before accessing the shared memory System Reset Power on reset RESET IN asserted Watchdog timer time out The entire system including memory is reset Note that the DSP software RESET instruction does not reset the MDI Before initiating an MDI reset the following items should be considered 1 Pending shared memory write If an MCU write to the shared memory is pending in the write buffer when an MDI reset is initiated the access may be lost To ensure that the data is written software should poll the MSMP bit in the MSR until it is cleared before triggering the MDI reset 2 DSP MDI operations MDIR assertion is asynchronous to DSP operation and can cause unpredictable behavior if it occurs while the DSP is testing an MDI 5 14 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc register bit with an instruction such as MDI
319. data data data data data 0 0 UART Transmit Register Tx Data Address 0020 4040 to 407C Reset uuuu Read Write 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Reserved Motorola Programmer s Data Sheets E 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer U A RT RRDYIE Description U 5 R 1 0 Interrupt disabled 1 Receiver Ready Interrupt enabled UART Control Register 1 Address 0020_4080 T Reset 0000 RXEN Description Read Write 0 Receiver disabled 1 Receiver enabled RXFL 0 1 Description 00 ee contains 1 or IREN Description 01 Interrupt if RX FIFO contains 4 or 0 Infrared interface IrDA disabled more characters 1 Infrared interface IrDA enabled 10 Interrupt if RX FIFO contains 8 or Mone CHAIRS TXEIE Description k alii FO gontains or 0 Interrupt disabled 1 Transmitter Empty Interrupt enabled TXEN Description 0 Transmitter disabled RTSDIE Description 1 Transmitter enabled 0 RTS interrupt disabled 1 RTS interrupt enabled TRDYIE Description 0 Interrupt disabled SNDERIK Description 1 Transmitter Ready Interrupt enabled 8 Bitis olgar d 1 Sen
320. data memory is 16 bits 1 halfword wide Program ROM is 48K by 24 bits and program RAM is 512 by 24 bits Data memory is organized into two separate areas X and Y each accessed by its own address and data buses X and Y data ROM are 10K by 16 bits each X data RAM is 7K by 16 bits and Y data RAM is 6K by 16 bits In addition 1K of X data memory space serves as dual port RAM for the MDI 1 2 3 MCU DSP Interface The MDI provides a way for the MCU and DSP cores to communicate with each other It contains a message and control unit as well as IK x 16 bit dual ported RAM Motorola Introduction 1 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Architecture Overview 1 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 2 Signal Connection Description The DSP36652 input and output signals are organized into functional groups in Table 2 1 below and in Figure 2 1 on page 2 2 Many of the pins in the DSP36652 have multiple functions In Table 2 1 pin function is described to reflect primary pin function Subsequent tables in this section are named for these primary functions and provide full descriptions of all signals on the pins Table 2 1 DSP56652 Signal Functional Group Allocations Functional Group Number of Detail
321. ddress 0020 100C 1 only write accesses can assert Reset uuuu Read Write WEN Description DSZ1 DSZO Description 0 The EBO 1 signals are negated 0 0 8 bit port on D 8 15 pins normally 0 1 8 bit port on D 0 7 pins 1 The EBO 1 signals are negated half 1 0 16 bit port on D 0 15 pins a clock cycle earlier on write accesses 1 1 Reserved OEA Description e SP Description 0 The OE signal is negated normally A 0 User mode accesses allowed 1 The OE signal is asserted half a clock cycle later on read accesses 1 User mode accesses prohibited CSA Description WP Description 0 The CS signal is asserted normally 0 Writes are allowed 1 The CS signal is asserted one cycle later on read and write 1 Writes are prohibited accesses and an extra cycle inserted between back to back cycles PA Description EDC Description 0 CS pin at logic high 0 No delay occurs after a read cycle 1 CS pin at logic low 1 One clock cycle is inserted after a read cycle CSEN Description e 0 Chip Select function is disabled wws Description and CSO pin is an output 0 Read and write WAIT states same 1 Chip Select function is enabled 1 Write WAIT states Read WAIT states 1 WSC 0 3 Description Binary value of number of external memory wait states 31 16 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 WSC3 WSC2 WSC1 WSCO WWS EDC CSA OEA WEN EBC DSZ1 DSZO SP WP PA CSEN Reserved E 20 DSP56652 User s Manual Motorola
322. de if the MRIE1 bit in the MCR is set DTRO DSP Transmit Register O X FF8D BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from MCU to DSP RESET Table 5 20 DTRO Description DTRO is a 16 bit write only register Data written to DTRO is reflected on the MCU side in MRRO DTRO and MRRO are not double buffered Writing to DTRO overwrites the data in MRRO clears the DTEO bit in the DSR and sets the MRFO bit in the MSR It can also trigger a receive interrupt on the MCU side if the MRIEO bit in the MCR is set DRR1 DSP Receive Register 1 X FF8E BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from DSP to DSP RESET Table 5 21 DRR1 Description DRR1 is a 16 bit read only register that reflects the data written on the MCU side to MTR1 Reading DRR1 clears the DRF1 bit in the DSR sets the DTE1 bit in the MSR and can trigger a transmit interrupt on the MCU side if the MTIE1 bit in the MCR is set DRRO DSP Receive Register 0 X FF8F BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from DSP to DSP RESET Table 5 22 DRRO Description DRRO is a 16 bit read only register that reflects the data written on the MCU side to MTRO Reading DRRO clears the DRFO bit in the DSR sets the DTEO bit in the MSR and can trigger a transmit interrupt on the MCU side if the MTIEO bit in the MCR is set Motorola
323. ded mode mode The Extended Stack Overflow is generated when SP equals SZ and an additional push operation is requested while the Extended mode is enabled by the SEN bit The EOV bit is a sticky bit i e can be cleared only by hardware reset or an explicit MOVE operation to the OMAR The transition of EOV from O to 1 causes an IPL 3 Stack Error interrupt EUN Extended Stack Underflow Flag Set when astack O No underflow has occurred default Bit 9 underflow occurs in the Stack Extended mode The 1 Stack underflow in stack extended mode Extended Stack Underflow is generated when the SP equals 0 and an additional pull operation is requested while the Extended mode is enabled by the SEN bit The EUN bit is a sticky bit i e can be cleared only by hardware reset or an explicit MOVE operation to the OMR The transition of EUN from O to 1 causes an Interrupt Priority Level IPL Level 3 Stack Error interrupt XY XY Select for Stack Extension Determines 0 X memory space default Bit 8 memory space for stack extension 1 Y memory space SD Stop Delay Controls the amount of delay after O Long delay 128K DSP_CLK cycles Bit 6 wake up from STOP mode A long delay may be default necessary to allow the internal clock to stabilize 1 Short delay 16 DSP_CLK cycles Note The SD bit is overridden if the PSTP bit in PCTL1 is set forcing wake up with no delay Motorola Core Operation and Configuration 4 13 For More
324. default Bit 5 at the next end_of_frame event Macros may or 1 Halt request may not complete depending on the state of the MTER bit SPBP Slot Prescaler Bypass This bit determines if 0 Not bypassed RSC input Bit 4 RSC is driven by the prescaler output RSE or TICK 2400 defalut the TICK signal 1 Bypassed RSC input TICK TDZD Timer DOZE Disable O PT ignores DOZE mode default Bit 3 1 PT stops in DOZE mode MTER Macro Termination This bit determines if O Macros run to completion default Bit 2 macros are allowed to complete i e continue to 1 Macros halted immediately run until the end_of_macro command when a halt event or halt request is issued TIME Timer Initiate Enable This bit determines if 0 Execution delayed until next CFE default Bit 1 event execution begins immediately or waits for 1 Execution begins immediately after TE is set the next frame signal CFE after the PT is or halt state terminates as soon as CTIC enabled TE set or the PT exits the halt state equal the first ATIC value in the event table TE Timer Enable This bit is a hard enable disable O PT disabled default Bit O of PT activity Clearing TE stops all PT activity 1 PT enabled immediately regardless of the state of MTER Motorola Protocol Timer 10 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers PTIER Protocol Timer Interrupt Enable Registe
325. der Files B 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Include File receive data registers define UART R REG REDCAP MCU UART 0x00 transmit data registers define UART T REG REDCAP MCU UART 0x40 Control Registers define UART C REG REDCAP MCU UART 0x80 ifdef _ASSEM define UART UCR1 0x0 define UART UCR2 0x2 define UART UBRG 0x4 define UART USR 0x6 define UART UTS 0x8 fdefine UART UPCR Oxa define UART UDDR Oxc define UART UPDR 0xe else struct redcap uart ctrl unsigned short ucrl control register 1 unsigned short ucr2 control register 2 unsigned short ubrg baud rate generator register volatile unsigned short usr status register unsigned short uts test register unsigned short upcr port control register unsigned short uddr port data direction register volatile unsigned short updr port data register y endif kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP SPI example usage unsigned short qspi control ram unsigned short QSPI C RAM unsigned short qspi lt data ram unsigned short OSPI D RAM struct redcap gspi c reg qspi ctrl struct redcap qspi c reg OSPI C REG struct redcap qspi t reg qspi trigs struct redcap qspi t reg OSPIDCAP T REG KKK IK KKK dede e IKK IIIA AKI IK control ram define QSPI C RAM REDCAP MCU OSPI40x000
326. dgment to the MCU clock If the DSP runs at a relatively low frequency extra wait states are added to the MCU access Note The synchronization wait states are not related to wait states resulting from memory contention When the DSP is in STOP mode and the MCU is in normal mode the shared memory operates from the MCU clock The memory controller is alerted when the DSP has exited Motorola MCU DSP Interface 5 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Resetting the MDI STOP mode and stalls any pending MCU shared memory access until the memory clocks are switched back to the DSP Note Waking the DSP from STOP can take several MCU clocks The parameters affecting the relative time length include the DSP frequency relative to the MCU frequency the need for PLL relock and the state of the SD bit in the OMR If the total wake from STOP delay is greater than 128 MCU clocks a pending MCU shared memory access can be lost due to an MCU time out interrupt MCU shared memory writes that are separated by MSR bit 6 checks are not subject to this loss because the write is done to a buffer and the MCU bus is released 5 4 Resetting the MDI The MDI can be reset by any of the conditions in Table 5 4 Table 5 4 MDI Reset Sources Reset Type Action Description MDI Reset Setting the MDIR bit in Only the MDI system is reset all status and control registers are the MCR returne
327. dress X FFB5 S e os Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAP Control Register A WL1 WLO Description Address X FFB6 0 8 bits per word Reset 0000 Read Write 1 12 bits per word 1 0 16 bits per word PSR Description 1 1 Reserved 0 No prescale 1 Prescale applied Frame Rate Divider Prescale Modulus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO PSR WL1 WLO DC4 DC3 DC2 DC1 DCO E 78 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer TLIE Description SA P 0 Disable interrupt 1 Enable interrupt for last transmit time slot SAP Control Register B Eu Address X FFB7 RIE Descripuon Reset 0000 0 Disable interrupt Read Write 1 Enable interrupt when a word is received RLIE Description TIE Description 0 Disable interrupt 0 Transmit Interrupt disabled 1 Enable interrupt for last receive 1 Transmit Interrupt enabled time slot RE Description 0 Receiver disabled TEIE Description 1 Receiver enabled 0 Disable interrupt 1 Enable interrupt for transmit error TE Descripti
328. dulus Register E 62 RSC Reference Slot Counter E 63 RSMR Reference Slot Modulus Register E 63 FTPTR Frame Table Pointer E 64 MTPTR Macro Table Pointer E 64 FTBAR Frame Tables Base Address Register E 65 MTBAR Macro Tables Base Address Register E 65 DTPTR Delay Table Pointer E 65 PTPCR PT Port Control Register E 66 PTDDR PT Data Direction Register E 66 PTPDR PT Port Data Register E 66 Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table E 1 List of Programmer s Sheets Continued Register Functional Block Page Acronym Name UART URX UART Receiver Register E 67 UTX UART Transmitter Register E 67 UCR1 UART Control Register 1 E 68 UCR2 UART Control Register 2 E 69 UBRGR UART Bit Rate Generator Register E 69 USR UART Status Register E 70 UTS UART Test Register E 70 UPCR UART Port Control Register E 71 UDDR UART Data Direction Register E 71 UPDR UART Port Data Register E 71 SCP SCPCR SCP Control Register E 72 SCACR Smart Card Activation Control Register E 73 SCPIER SCP Interrupt Enable Register E 73 SCPSR SCP Status Register E 74 SCPDR SCP Data Register E 75 SCPPCR SCP Port Control Register E 75 Keypad Port KPCR Keypad Port Control Register E 76 KPSR Keypad Status Register E 76 KPDDR Keypad Data Direction Registe
329. e MRFO Description 0 MRRO is empty MEP Description 1 MRPO has data 0 No event pending 1 MCU Side event pending MCU Side Flags 15 14 13 12 11 10 9 8 7 5 4 2 1 0 MRFO MRF1 MTEO MTE1 MGIPO MGIP1 MTIR DWS DRS MSMP DPM MEP MF2 MF1 MFO 0 Reserved E 12 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer MCU MDI MRRO MCU Receive Register 0 Address 0020_2FFE Reset uuuu Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data MRR1 MCU Receive Register 1 Address 0020 2FFC Reset uuuu Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data MTRO MCU Transmit Register 0 Address 0020_2FFA Reset uuuu Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data MTR1 MCU Transmit Register 1 Address 0020_2FF8 Reset uuuu Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data
330. e 8 4 QCR Description Continued Name Description Settings TRCNT1 Trigger Count for Queue 1 When the TACE bit in the SPCR is set trigger accumulation is Bits 9 6 enabled and the TRCNT1 field can take values other than 0 If Queue 1 receives a transfer trigger while it is active i e the QA1 bit in the SPSR is set the TRCNT1 field is incremented The TRCNT1 field is decremented when a Queue 1 transfer completes As many as 16 triggers can be accumulated and subsequently processed The TRCNT1 field cannot be incremented beyond the value of 1111 or decremented below O If a trigger for Queue 1 arrives when the TACE bit and all the bits of TRCNT field are set the TRC flag in the SPSR is asserted to signify a trigger collision If transfer of Queue 1 is completed when all the bits in TRCNT field are cleared QA1 is deasserted This field can only be read by the MCU writes to this field are ignored There is no TRCNT field in QCRO QCR2 or QCR3 Bits 9 6 of these registers are reserved QPn Queue Pointer for Queue n This field contains the address of the next queue entry for the Bits 5 0 associated queue The MCU initializes the QP to point to the first address in a queue As queue n executes the QPn is incremented each time a queue entry is fetched from RAM If an EOQ command is identified in the queue entry s control halfword and the LEn bit is asserted the six least significant bits of the data halfword in the queue en
331. e Information On This Product Go to www freescale com E 63 Freescale Semiconductor Inc Application Date Programmer Protocol Timer Frame Table Pointer FTPTR Frame Table Pointer Address 0020_381C Reset 00uu Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTPTR6 FTPTR5 FTPTR4 FTPTR3 FTPTR2 FTPTR1 FTPTRO Transmit Macro Table M T P T R Pointer Macro Table Pointer Address 0020_381E Receive Macro Table Reset uuuu Read Write Pointer 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 TxPTR6 TxPTRS TxPTR4 TxPTR3 TxPTR2 TxPTR1 TxPTRO R PTR6 RXPTRS RXPTRA RXPTR3 RXPTR2 RXPTR1 RXPTRO Reserved E 64 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer FTBAR Frame Table Base Address Re Address 0020 3820 Reset uuuu Protocol Timer Second Frame Table gister Address 0020 3822 Reset uuuu First Frame Table Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTBA16 FTBA15 FTBA14 FTBA13 FTBA12 FTBAT1 FTBA10 FTBA6 FTBAS FTBM FTBA3 FTBA2 F
332. e JTAG test access port TAP controller TCK is used to synchronize the JTAG test logic Note When this signal is enabled the primary TCK signal is disconnected from the TAP controller See Table 2 19 on page 2 19 2 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 9 UART With the exception of alternate signal functions TDO TDI RESET_IN and MCU_DE the signals described in Table 2 12 are GPIO when not programmed otherwise and default as GPI after reset UART The remaining UART signals can be implemented with GPIO pins Suggested allocations include the following e DSR alternate function for INT6 See Table 2 9 on page 2 8 e DTR alternate function for INT7 See Table 2 9 on page 2 8 e DCD alternate function for ROW6 See Table 2 11 on page 2 10 e RI alternate function for ROW7 See Table 2 11 on page 2 10 Table 2 12 UART Signals Signal Name Type Reset State Signal Description TxD TDO Normal MUX CTL driven low Input or Input Output UART Transmit This signal transmits data from the UART Alternate MUX CTL dri ven high Output Test Data Output alternate This signal provides the TDO serial output for test instructions and data from the JTAG TAP controller TDO is a tri state signal that is actively driven in the shift IR and
333. e MCU by setting the DGIRO or DGIR 1 bit in the DSP Side Status Register DSR These interrupts are user maskable on the MCU side Figure 5 6 details the mechanism by which the DSP issues a general purpose interrupt to the MCU 5 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Messages and Control DSP Side MCU Side Status Register Status Register ES Set ESA Write1 Write1 GIR GIP to Clear poros E Control Register Bit Name General GIR General Purpose Interrupt Request Interrupt E Request GIP General Purpose Interrupt Pending GIE General Purpose Interrupt Enable Figure 5 6 DSP to MCU General Purpose Interrupt The MCU to DSP interrupt mechanism Command Interrupt differs from Figure 5 6 in the following ways 1 The interrupt pending bit the MCP bit in the DSR is cleared automatically when the interrupt is acknowledged 2 The trigger bit on the MCU side the MC bit is in the MCVR 3 When a non maskable interrupt is generated the interrupt enable bit on the DSP side the MCIE bit in the DCR is ignored 5 2 2 Message Protocols The message hardware can be used by software to implement message protocols for a wide array of message types Full support is given for both interrupt and polling management The following are examples of different message protocols Amessage of up to 16 bits is written di
334. e MCU reads enough data to bring the threshold number of unread characters in URX below the threshold RTSD RTS Delta Set when the RTS pin changes 0 RTS has not changed state since RTSD was Bit 15 state Cleared by writing the bit with one last cleared default 1 RTS has changed state 11 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers UTS UART Test Register 0020_4088 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 FRCPERR LOOP LOOPIR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register is provided for test purposes and is not intended for use in normal operation Table 11 10 UTS Description Name Description Settings FRCPERR Force Parity Error If parity is enabled the 0 No intentional parity errors generated Bit 13 transmitter is forced to generate a parity error as default long as this bit is set 1 Parity errors generated LOOP Loop Tx and Rx Setting this bit connects the 0 Normal operation default Bit 12 receiver to the transmitter The RxD pin is 1 Receiver connected to transmitter ignored LOOPIR Loop Tx and Rx for Infrared Interface Setting 0 Bit 10 this bit connects the infrared receiver to the 1 infrared transmitter Normal IR operation default IR Receiver connected to IR transmitter
335. e MGIP1 bit in the MSR is set If 1 Enabled MGIE1 is clear MGIP1 is ignored and no general interrupt request 1 is issued Motorola MCU DSP Interface 5 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers Table 5 11 MCR Description Continued Name Type Description Settings DHR R W DSP Hardware Reset Setting DHR issues a hardware reset to the DSP Clearing DHR Bit 7 de asserts the reset Setting DHR also causes MDI reset returning all MDI control and status bits to their default values except the DHR bit itself DHR should be held asserted for a minimum of three CKIL cycles See Reset Mode Select and Interrupt Timing in the DSP56652 Technical Data Sheet After clearing DHR software should poll the DRS bit in the MSR until it is cleared before attempting an access to MDI shared memory If an MDI reset caused by MDIR or DHR being set is done while an MCU write to the shared memory is pending in the write buffer the access may be lost MDIR RO 1S MDI Reset Setting MDIR resets the message and control sections on both DSP and MCU Bit 6 sides All control and status registers except DHR are returned to their default values and all internal states are cleared Data in the shared memory array remains intact only the access control logic is affected After setting MDIR software should poll DRS to determine when the reset sequence on the DSP side has
336. e Slot Register RFS Receive Frame Sync This bit reflects the status of the receive frame sync signal whether Bit 3 generated internally or received externally In normal mode RFS is always set In network mode RFS is set only during the first time slot of the receive frame and remains set for the duration of the word reception regardless of the state of the FSL bit in the SAPCRC or BBPCRC TFS Transmit Frame Sync This bit reflects the status of the transmit frame sync signal whether Bit 2 generated internally or received externally In normal mode TFS is always set In network mode TFS is set only during the first time slot of the transmit frame and remains set for the duration of the word transmission regardless of the state of the FSL bit in the SAPCRC or BBPCRC 1F1 Input Flag 1 In synchronous mode this bit reflects the state of Input Flag 1 which is driven on Bit 1 the SC1x pin IFO Input Flag O In synchronous mode this bit reflects the state of Input Flag 0 which is driven on BitO the SCOx pin 14 22 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers SAPRX SAP Receive Data Register X FFBA BBPRX BBP Receive Data Register X FFAA Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O Receive Word This read only register accepts data from the receive shift register after the last bit of a receive word is shifted
337. e Time Interval Clock TICK This signal is related to symbol duration and typically functions as a sub symbol clock TICK drives two timing chains The primary timing chain generates event timing It contains a Channel Time Interval Counter CTIC which drives a Channel Frame Counter CFC The primary chain has a programmable modulus The auxiliary chain which has a fixed modulus is used as a time slot reference This chain contains a Reference Slot Prescale Counter RSPC which drives a Reference Slot Counter RSC 10 1 1 1 Time Interval Clock Generator The TICG is a 9 bit programmable prescaler that divides MCU_CLK to generate the PT reference clock TICK The TICK frequency range is MCU_CLK 2 to MCU_CLK 512 The TICG modulus value is programmed in the Time Interval Modulus Register TIMR which is loaded into the TICG when it rolls over Changing the TICG value on the fly is not supported 10 1 1 2 Channel Time Interval Counter The CTIC is a programmable read write free running 14 bit modulo down counter decremented by the TICK signal It is used to trigger frame table events and generate the frame reference signal Channel Frame Expire CFE An event is triggered each time the value in CTIC matches the TIC value pointed to in a Frame Table CFE is asserted when the CTIC decrements to zero which can trigger a Channel Frame Interrupt CFI to the MCU if the CFIE bit in the Protocol Timer Interrupt Enable Register PTIER is set
338. e als FRE ORs ERR EEG ORTA 14 8 Aaa TDDNOUDGIUDG tte ath WAY de et NG tek eh Da Raat eek n oe gts s 14 8 144 Data Transmission and Reception 0 0 cece eee eee eee 14 9 14 4 1 Data Transmission 0 cc cece een eens 14 9 144 2 Data Receptor hia ith acer eats Mia ath oe Wig a anita bie 14 11 1443 Dar Formats a EIER ea chee see ty eae See os 14 12 14 5 Software Reset oae IA RRS 14 12 14 6 General Purpose Timer SAP Only 0 0 eee eee eee 14 13 14 7 Frame Counters BBP Only dia ood oh ee os BAS YEA e Rees 14 13 I8 JIntetriple 5 5 Se cata eae O ERS AES Aes OUR 14 14 14 9 SAP and BBP Control Registers 5 ule RE ld eek aks 14 15 149 1 SAP and BBP Control Registers 0 0 eee eee ee eee 14 17 1492 GPIO R6EISUCIS ud code ais IIA gis FOE RES GER PREF E 14 24 Chapter 15 JTAG Port 15 1 DSP56600 Core JTAG Operation 0 0 eee ee nee 15 3 ISEE JTAG PNS Ser E ete Owe see Peewee me ets 15 3 15 2 DSP TAP Controller tice Ws bt de Seat dons We aed cade oth coed Oy Wh dia seta Bs 15 4 15 13 danstfr ction Resister 45 45 vouwes onnar AS HESS ROE ER RC RESIS 15 5 1D Test o e A ox eH ened ER ME Oe ee eh CU e SH RU 15 10 15 2 1 Boundary Scan Register BSR 0 eee eee eee eee 15 10 152 2 Bypass REsister O 15 10 15225 Identitication RESISTE PENES 15 10 15 3 DSP56652 JTAG Port Restrictions cias 44 ERE ha das 15 11 I5 1 Normal ODGratonzx 2 65 wewexwe RAS A EEE EES
339. e delay 001 2 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay 101 32 SCK cycles delay 110 64 SCK cycles delay 111 128 SCK cycles delay SCK MCU_CLK 2 3 SCKFD4 6 1 SCKDFA4 0 5 1 All values for SCKDF4 0 6 are valid Sample values are shown SCKDF4 0 6 Description 000_0000 SCK MCU_CLK 2 000_0001 SCK MCU_CLK 4 000_0111 SCK MCU_CLK 16 100_0000 SCK MCU_CLK 8 000_0100 SCK MCU_CLK 10 100_1011 SCK MCU_CLK 96 111_1110 SCK MCU_CLK 504 Read Write DATR4 0 2 Delay After Transfer 000 1 SCK cycle delay 001 2 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay 101 32 SCK cycles delay 110 64 SCK cycles delay 111 128 SCK cycles delay LSBF4 Description 0 Data transferred MSB first 1 Data transferred LSB first CKPOL4 Description 0 SCK inactive at logic 1 1 SCK inactive at logic O CPHA4 Description 0 Data changes on first SCK transition 1 Data latches on first SCK transition 111 1111 SCK MCU CLK 1 15 14 13 12 11 10 5 4 3 2 1 0 CAPHA4 CKPOL4 LSBF4 DATR42 DATR41 DATR40 CSCKD42 CSCKD41 CSCKD40 SCKDF46 SCKDF45 SCKDF44 SCKDF43 SCKDF42 SCKDF41 SCKDF40 Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 47
340. e eee eee D 1 MCU Instruction Syntax Notation 0 0 eee eee eee D 6 MCU Instruction Opcode Notation 0 020 eese D 6 DSP Instruction Set Summary ues peur Re ose vad eed oes D 7 Program Word and Timing Symbols 000 eee ee D 13 Condition Code Register CCR Symbols 2 45 D 13 Condition Code Register Notation 0 0 e cee eee eee ee D 13 MCU Internal I O Memory Map essen D 14 DSP Internal I O Memory Map 0 0 00 e eee eee eee D 19 Resister Index 252 22 nana Aa an a eo ERE Ee ases s D 22 DSP56652 Acronym Changes sort vie Turmae MER Es D 26 List of Programmers Sheets ases siete dea me e E 1 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Examples Example 5 1 Program Loop That Stalls MCU Access to Shared Memory Example 5 2 Program Loop With No Stall oooocccoocoococccooooo Example 5 3 Dummy Event to Allow MCU to Track DSP Power Mode Change 5 13 Example 11 1 UART Baud Error Calculation ooooooooormo oro 11 6 Example A L Normal Boots 5 os e ES X WERE he Wee A 14 Example A 2 Shared Memory Boot os 04355 42595 EWER RAASERRERWASO nA RR A 15 Example A 3 Messaging Unit Boot oooooooommorrnorraroncano A 16 Motorola List of Examples xxi For More Information On This Product Go to www freescale co
341. e is generated at 10 5 etu s after the start bit The width of the NACK pulse is 1 to 2 etu s The NACK should be sampled at 11 etu s after the start bit If a NACK pulse is received the character should be retransmitted a minimum of 2 etu s after the detection of the error The start of the repeated character should be a minimum of 2 etu s after the detection of the error bit Figure 12 4 shows timing of the data format Motorola Smart Card Port 12 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Operation a 12etu min LSB MSB Start Byte i P Guard Start Byte i 1 period Without parity error Even Parity Bit NACK sample time oy j 2min PEAS 11 etu j Retransmission Start i Error Start Byte i Eds P Signal 7 48 10 5 etu PP With parity error NACK 1 min 2 max etu s 02 A Z ZIJA Z Z Z A Al AJAJIA Initial Character from SCP etu Elementary Time Unit Figure 12 4 SCP Data Formats 12 2 4 Low Power Modes If the DOZE bit in the SCPCR register is set when the MCU enters DOZE mode the SCP completes the current transmit receive transaction then gates off the receive and transmit clocks However the clocks to the Automatic Power Down and the SENSE debouncer circuits remain enabled to allow the SCP to initiate an automatic power down if the smart
342. e mechanism is shown in greater detail in Figure 5 5 Motorola MCU DSP Interface For More Information On This Product Go to www freescale com 5 7 Freescale Semiconductor Inc MDI Messages and Control Transmit Side Receiver Side Receive Register Transmit Register Data Write Data Read Status Register Status Register INE Clear Set Clear Control Register Bit Name Transmit TE Manisri Register Empty E Interrupt RF Receive Register Full Interrupt Request TEIE Transmit Register Empty Request Interrupt Enable RFIE Receive Register Full Interrupt Enable Figure 5 5 MDI Message Exchange In addition to exchanging messages the MDI registers also provide the following special purpose control functions 1 Each core s power mode is reflected in the other core s status register 2 Each core can issue an interrupt to wake the other core from its low power modes STOP and WAIT modes on either side plus DOZE mode on the MCU side 3 The MCU can issue a Command Interrupt to the DSP by setting the MC bit in the MCU Command Vector Register MCVR Software can write the vector address of this interrupt to a register on the MCU side The Command Interrupt can be maskable or non maskable 4 The MCU can issue a hardware reset to the DSP The DSP cannot issue a hardware reset to the MCU 5 The DSP can issue two general purpose interrupt requests to th
343. e the data size for the current MCU access PSTATO Output Input Pipeline State These output signals encode the internal MCU PSTAT3 execution status 2 15 Debug Port Control The signals described in Table 2 18 are GPIO when not programmed otherwise and default as GPI after reset 2 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JTAG Test Access Port Table 2 18 Debug Control Signals Signal Name Type Reset State Signal Description MCU_DE Input or Input Microcontroller Debug Event As an input this signal provides a Output means to enter the debug mode of operation from an external command converter As an output signal it acknowledges that the MCU has entered the debug mode When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition it asserts MCU_DE as an output signal for several clock cycles DSP_DE Input or Input Digital Signal Processor Debug Event This signal functions as Output DSP_DE In normal operation DSP_DE is an input that provides a means to enter the debug mode of operation from an external command converter When the DSP enters the debug mode due to a debug request or as the result of meeting a breakpoint condition it asserts DSP_DE as an output signal for three clock cycles to acknowledge that it has entered debug mode 2 16 JT
344. e to MDI shared Software should ensure that MSMP is cleared memory has not been completed before issuing an MDI reset to ensure that no pending write is lost DPM R DSP Power Mode Reflects the DSP mode of O DSP is in normal or WAIT mode Bit 5 operation default 1 DSP is in STOP mode MEP R MCU Side Event Pending Set when the O Last event update request to DSP has Bit 4 MCU sends an event update request to the been acknowledged DSP side Cleared when the event update 1 Event update request to DSP acknowledge has been received An event is pending any hardware message that should be reflected in the DSR on the DSP side e g transmit register O written Software should poll MEP until it is cleared before entering STOP mode Reading the MSR to check the MEP bit should be the last MDI access before entering STOP otherwise the MEP can be set as a result of that additional action If MEP is not properly verified entering the MCU STOP power mode may not to be reflected at the DSR MF 2 0 MCU Flags General purpose flag bits 0 Corresponding DMF bit cleared Bits 2 0 reflecting the state of DMF 2 0 DCR bits 2 0 1 Corresponding DMF bit set 1 R Read only R 1S Read or write with 1 to set write with O ignored R 1C Read or write with 1 to clear write with O ignored 5 22 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale S
345. e to the Vcc power rail Use a 0 1 uF bypass capacitor located as close as possible to the chip package to connect between the Vccr line and the GND line Veca GPIO power This line supplies power to the GPIO keypad data port interrupts STO and JTAG I O drivers VccH Baseband codec and timer power This line supplies power to the baseband codec and Timer I O drivers Veco Quiet power high These lines supply a quiet power source to the pre driver voltage converters This value should be equal to the maximum value of the power supplies of the chip I O drivers i e the maximum of Veca VccB Veco Veco Voce Vocr Vcca Vech and Veck Vcck Emulation port power This line supplies power to the emulation port I O drivers VccP Analog PLL circuit power This line is dedicated to the analog PLL circuits and must remain noise free to ensure stable PLL frequency and performance Ensure that the input voltage to this line is well regulated and uses an extremely low impedance path to tie to the Vcc power rail Use a 0 1 uF capacitor and a 0 01 uF capacitor located as close as possible to the chip package to connect between the Vccp line and the GNDp and GND p lines Vccao Quiet power These lines supply a quiet power source to the internal logic circuits Ensure that the input voltage to this line is well regulated and uses an extremely low impedance path to tie to the Vcc power rail Use a 0 1 uF bypass capacitor located as close as possible
346. east four CKIL cycles before RESET_OUT is deasserted If MOD is driven low the internal MCU ROM is disabled and CS0 is asserted for the first MCU cycle The MCU fetches the reset vector from address 0 of the CSO memory space which is located at the absolute address 4000_0000 in the MCU address space The internal MCU ROM is disabled for the first MCU cycle only and is available for subsequent accesses Out of reset CSO is configured for 15 wait states and a 16 bit port size Refer to Table 6 6 on page 6 9 for a more detailed description of CSO If MOD is driven high the internal ROM is enabled and the MCU fetches the reset vector from internal ROM at address 0000_0000 4 3 2 DSP Reset Any qualified MCU reset also resets the DSP core and its peripherals to their default values In addition the MCU can issue a hardware or software reset to the DSP through Motorola Core Operation and Configuration 4 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Configuration the MCU DSP Interface MDI A hardware reset is generated by setting the DHR bit in the MCR A software reset can be generated by setting the MC bit in the MCVR to issue a DSP interrupt In this case the interrupt service routine might include the following tasks e Issue a RESET instruction e Reset other core registers that are not affected by the RESET instruction such as the SR and the stack pointer Jump to the ini
347. ecture Overview Each address ALU can update one address register from its respective address register file during one instruction cycle The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation The modifier value is decoded in the address ALU 1 2 2 1 3 Program Control Unit The program control unit PCU performs instruction prefetch instruction decoding hardware DO loop control and exception processing The PCU implements a seven stage pipeline and controls the different processing states of the DSP core The PCU consists of three hardware blocks e program decode controller PDC e program address generator PAG e program interrupt controller PIC The PDC decodes the 24 bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control The PAG contains all the hardware needed for program address generation system stack and loop control The PIC arbitrates among all interrupt requests and generates the appropriate interrupt vector address The PCU implements its functions using the following registers e PC Program Counter register e SR Status Register e LA Loop Address register e LC Loop Counter register e VBA Vector Base Address register e SZ Size register e SP Stack Pointer e OMR Operating Mode Register e SC Stack Counter register The PCU also includes a hardware System Stack
348. ed Reference Slot Interrupt enabled Description Interrupt disabled Channel Frame Number Interrupt enabled Description Interrupt disabled Channel Frame Interrupt enabled MCIE1 PT Interrupt Enable Register 0 Address 0020_3802 Reset 0000 1 Read Write MCIEO DSIE Description 0 0 Interrupt disabled 1 1 DSP Interrupt enabled RSNIE DVIE Description 0 0 Interrupt disabled 1 1 DSP Vector Interrupt enabled CFNIE THIE Description 0 0 Interrupt disabled r 4 1 Timer HALT Interrupt enabled TERIE Description CFIE 0 Interrupt disabled 0 1 Timer Error Interrupt enabled 1 15 13 12 11 10 4 3 2 1 9 8 7 6 5 Reserved MCIEO RSNIE CFNIE CFIE Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 59 Freescale Semiconductor Inc Application Date Programmer 2 DSPI Description Protocol Ti mer 0 Interrupt has not occurred 1 DSP Interrupt event has occurred MCUI2 Description PT Status Register Address 0020_3804 0 Interrupt has not occurred Reset 0000 1 MCU Interrupt 2 event has occurred Read Write MCUI1 Description DVI
349. ed Signals Description Power Vccx 20 Table 2 2 Function specific ground GNDy 17 Table 2 3 General ground GND 20 PLL and clocks 5 Table 2 4 Address bus 22 Table 2 5 External Interface Data bus 16 Module EIM Bus control 4 Table 2 6 Chip selects 6 Table 2 7 Reset mode and multiplexer control 5 Table 2 8 External interrupts 9 Table 2 9 Protocol Timer 8 Table 2 10 Keypad port 16 Table 2 11 UART 4 Table 2 12 Queued Serial Peripheral Interface QSPI 8 Table 2 13 Smart Card Port SCP 5 Table 2 14 Serial Audio Codec Port SAP 6 Table 2 15 Baseband Codec Port BBP 6 Table 2 16 Development amp Test Emulation port 6 Table 2 17 Debug control port 2 Table 2 18 JTAG test access port TAP 6 Table 2 19 Motorola Signal Connection Description For More Information On This Product Go to www freescale com 2 1 Power Function Specific Ground General Ground PLL and Clocks External Interface Module EIM Reset Mode and Multiplexer Control 2 2 VCCA VCCHQ VccQ RESET IN Freescale Semiconductor Inc DSP56652 INTO INT5 INT6 STDA DSR or TRST INT7 SRDA DTR SCK or TMS DSP_IRQ TOUTO TOUT7 COLO COL5 COL6 0C1 COL7 PWM ROWO ROWA ROW5 IC2B ROW6 SC2A DCD or DSP_DE ROW7 SCKA RI or TCK bh aa Bop pp TxD or TDO RxD IC1 or TDI RTS IC2 or RESET_IN CTS or MCU_DE SPICSO SPICS4 SCK MISO MOSI SIMCLK SENSE SIMDATA SIMRESET PWR_EN
350. ed by clearing the PEN bit in PCTL1 It can also be disabled in low power modes by clearing the PSTP bit in PCTL1 In either case the clock generator output is DSP_CLK DSP_REF 2 4 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generation 4 1 3 Clock and PLL Registers CKCTL Clock Control Register 0020_C000 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO DCS CKOHD CKOD CKOS MCD 2 0 MCS CKIHD RESET 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Table 4 2 CKCTL Description Name Description Settings DCS DSP Clock Select Selects the input to the DSP O CKIH default Bit 8 clock generator 1 CKIL CKOHD CKOH Disable Controls the output at the 0 CKOH is a buffered CKIH default Bit 7 CKOH pin 1 CKOH held low CKOD CKO Disable Controls the output of the CKO 0 CKO outputs either MCU CLK or DSP_CLK Bit 6 pin according to CKOS bit default 1 CKO held high CKOS CKO Source Select Selects the clock to be 0 MCU CLK default Bit 5 reflected on the CKO pin 1 DSP CLK MCD 2 0 MCU Clock Divide factor Selects the divisor Bits 4 2 for the MCU clock MCD 2 0 Divisor 0 1 1 2 2 4 3 8 4 16 5 97 Reserved MCS MCU Clock Select Determines MCU clock O CKIL default Bit 1 input 1 CKIH CKIHD CKIH Disa
351. eescale Semiconductor Inc DSP56600 Core JTAG Operation 15 1 3 2 Instruction Descriptions The DSP core JTAG implementation includes the three mandatory public instructions EXTEST SAMPLE PRELOAD and BYPASS and also supports the optional CLAMP instruction defined by IEEE 1149 1 The public instruction HIGHZ provides the capability for disabling all device output drivers The public instruction ENABLE_DSP_ONCE enables the JTAG port to communicate with the DSP OnCE circuitry The public instruction DSP_DEBUG_REQUEST enables the JTAG port to force the DSP core into Debug mode 15 1 3 2 1 EXTEST B 3 0 0000 The external test EXTEST instruction selects the BSR and gives the test logic control of the I O pins EXTEST also asserts internal reset for the DSP56652 core system logic to force a predictable internal state while performing external boundary scan operations By using the TAP controller the Instruction Register is capable of e Scanning user defined values into the output buffers e Capturing values presented to input pins e Controlling the direction of bidirectional pins e Controlling the output drive of tri stateable output pins For more details on the function and use of EXTEST refer to IEEE 1149 1 15 1 3 2 2 SAMPLE PRELOAD B 3 0 0001 The SAMPLE PRELOAD instruction selects the BSR and the system logic controls the I O pins The SAMPLE PRELOAD instruction provides two separate functions First it provides a means to obt
352. eference clock TICK frequency is MCU_CLK n 1 This register should be written before the PT is enabled Note In normal operation TIMR must be greater than 5 to ensure reliable PT event generation However TIMR values of 2 to 5 are sufficient for tracking channel activity when the PT does not execute events such as in low power modes TIMR values of 0 and 1 are not supported Motorola Protocol Timer 10 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers CTIC Channel Time Interval Counter 0020_380A Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O CTIV 13 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 12 CTIC Description Name Description CTIV 13 0 Channel Time Interval Value This field contains the current CTIC value CTIC is described on Bits 13 0 page 10 3 CTIMR Channel Time Interval Modulus Register 0020 380C Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O CTIMV 13 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 13 CTIMR Description Name Description CTIMV Time Interval Modulus Value This field contains the value loaded into CTIC when it rolls over or Bits 13 0 when a reload counter command The actual CTIC modulus is equal to CTIMV 1 For example to obtain a CTIC modulus value of 2400 this field should be written with 2399 95F CFC Channel Frame Counter
353. el control register 1 unsigned short sccr2 serial channel control register 2 unsigned short sccr3 serial channel control register 3 unsigned short sccr4 serial channel control register 4 y struct redcap qspi t reg unsigned short trig0 trigger for queue 0 unsigned short trigl trigger for queue 1 unsigned short trig2 trigger for queue 2 unsigned short trig3 trigger for queue 3 y endif kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP Protocol Timer example usage unsigned short event table unsigned short PROT ET BASE struct redcap prot ctrl prot ctrl struct redcap prot ctrl PROT C REG BASE Kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk event table base address define PROT ET BASE REDCAP MCU PROT 0x000 control registers base address define PROT C REG BASE REDCAP MCU PROT 0x800 ifdef ASSEM define PROT TCTR 0x00 Motorola Equates and Header Files For More Information On This Product Go to www freescale com MCU Include File B 31 Freescale Semiconductor Inc DSP Equates define PROT TIER 0x02 define PROT TSTR 0x04 define PROT TEVR 0x06 define PROT TIPR 0x08 define PROT CTIC 0x0A define PROT CTIPR 0x0C define PROT CFC 0x0E define PROT CFPR 0x10 define PROT RSC 0x12 define PROT RSPR 0x14 define PROT PDPAR 0x16 define PROT PDDR 0x18 fdefine PROT PDDAT 0x1A fdefine PROT FTPTR 0x1C fdefine
354. elect the order in which data is transferred over the MOSI and MISO lines when the SPICSn line is activated for the transfer When the LSBFn is set data is transferred least significant bit LSB first When the LSBFn bit is cleared data is transferred most significant bit MSB first When the BYTE bit in the control halfword is asserted only the least significant byte of the data halfword is transferred the MSB is then bit 7 so the data must be right aligned 0 MSB transferred first default LSB transferred first DATRn 2 0 Bits 12 10 Delay After Transfer for SPICSn These bits controls the delay time between deassertion of the associated SPICS line when queue or sub queue transfer is completed and the time a new queue transfer can begin Delay after transfer can be used to meet the deselect time requirement for certain peripherals CSCKDn 2 0 Bits 9 7 CS Assertion to SCK Activation Delay These bits control the delay time between the assertion of the associated chip select pin and the activation of the serial clock This enables the QSPI port to accommodate peripherals that require some activation time DATR 2 0 CSCKD 2 0 Delay SCK Cycles 000 1 default 001 2 010 011 4 8 100 16 101 32 110 64 111 128 SCKDFn 6 0 SCK Division Factor These bits determine SCKDF Examples
355. emiconductor Inc MDI Registers MTR1 MCU Transmit Register 1 0020_2FF8 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from MCU to DSP RESET Table 5 13 MTR1 Description MTR1 is a 16 bit write only register Data written to MTR1 is reflected on the DSP side in DRR1 MTR1 and DRR1 are not double buffered Writing to MTR1 overwrites the data in DRR1 clears the MCU Transmit Register 1 Empty bit MTE1 in the MSR and sets the DSP Receive Register 1 Full bit DRF1 in the DSR It can also trigger a receive interrupt on the DSP side if the DRIE1 bit in the DCR is set A single 8 bit write to MTR1 also updates all status information MTRO MCU Transmit Register 0 0020_2FFA BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from MCU to DSP RESET Table 5 14 MTRO Description MTRO is a 16 bit write only register Data written to MTRO is reflected on the DSP side in DRRO MTRO and DRRO are not double buffered Writing to MTRO overwrites the data in DRRO clears the MCU Transmit Register O Empty MTEO bit in the MSR and sets the DSP Receive Register O Full bit DRFO in the DSR It can also trigger a receive interrupt on the DSP side if the DRIEO bit in the DCR is set A single 8 bit write to MTRO also updates all status information MRR1 MCU Receive Register 1 0020_2FFC BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Transmitted data from MCU to DSP RESET
356. emory check mem space codes bits 13 14 15 pram512 equ 8000 3 100 response messages success equ 0 fail equ 1 fail inv mm equ 2 Motorola DSP56652 DSP Bootloader A 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program short response messages write success equ 1 lt lt 15 success lt lt 8 mem write write fail equ 1 lt lt 15 fail lt lt 8 mem write inval_long msg equ C000 inval_opc inval short msg equ C100 inval opc 77775377577 BOOT MODE B EQUATES z3r prot B sig 0 equ 1234 prot B sig 1 equ 5678 prot B conf 0 equ Sabcd prot B conf 1 equ cdef PBBBBIPIPPPiiiiii DSP I O REGISTERS 5577577777797 9 575955570 bus switch BPMRH equ SFFF2 bus switch program memory register high BPMRL equ SFFF3 bus switch program memory register low BPMRG equ SFFF4 bus switch program memory register 24bits MDI MDI base equ 1C00 base dp ram address DRRO equ SFF8F dsp receive register 0 DRR1 equ SFF8E dsp receive register 1 DTRO equ SFF8D dsp transmit register 0 DTR1 equ SFF8C dsp transmit register 1 DSR equ SFF8B dsp status register DCR equ SFF8A dsp control register DSR bits DFO equ 0 DSR flag 0 DF1 equ 1 DSR flag 1 DF2 equ 2 DSR flag 2 DRF1 equ 12 DSR receive reg 1 full e Ne Ne 9 Ne 99 NO DRFO equ 13 DSR receive reg 0 full DTE1 equ 14 DSR transmit reg 1 empty DTEO equ 15 DSR transmit reg 0 empty SAP portA and BBP p
357. en MC is Bit 0 if the Command Interrupt issued to the DSP set if DSP DCR bit 8 maskable by setting the MC bit is maskable or non interrupt enable is set default maskable The MNMI bit can only be written if 1 2 Non maskable interrupt generated the MC bit is cleared when MC is set DCR bit 8 is ignored 1 R Read only R W Read write R 1S Read write with 1 to set write with O ingored 5 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers MCR MCU Side Control Register 0020_2FF4 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO MRIEO MRIE1 MTIEO MTIE1 MGIEO MGIE1 DHR MDIR MDF 2 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The MCR is a 16 bit read write register that enables the MDI interrupts on the MCU side and enables the trigger events on the DSP side e g awaken from Stop mode hardware reset flag update etc Note Either the EMDI bit in the NIER or the EFMDI bit in the FIER must be set in order to generate any of the interrupts enabled in the MCR see page 7 7 Table 5 11 MCR Description Name Type Description Settings MRIEO R W MCU Receive Interrupt Enable 0 When O Receive interrupt O request disabled Bit 15 MRIEO is set a receive interrupt request 0 is default issued when the MRFO bit in the MSR is set
358. ended before accessing the shared memory MDF 2 0 R W MCU to DSP Flags General purpose flag bits that are reflected on the DSP side in the Bits 2 0 DF 2 0 bits in the DSR 1 R W Read write RO 1S Always read as 0 write with 1 to set write with O ingored 5 20 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Registers MSR MCU Side Status Register 0020_2FF6 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO MRFO MRF1 MTEO MTE1 MGIPO MGIP1 MTIR DWS DRS MSMP DPM MEP MF 2 0 RESET 0 0 1 1 0 0 0 0 1 0 0 0 Table 5 12 MSR Description Name Type Description Settings MRFO R MCU Receive Register 0 Full Set when the O Latest MRRO data has been read Bit 15 DSP writes to DTRO indicating to the MCU that default the reflected data is available in MRRO MRFO 1 2 New data in MRRO is cleared when the MCU reads MRRO MRF1 R MCU Receive Register 0 Full Set when the O Latest MRR1 data has been read Bit 14 DSP writes to DTR1 indicating to the MCU that default the reflected data is available in MRR1 MRF1 1 New data in MRR1 is cleared when the MCU reads MRR1 MTEO R MCU Transmit Register 0 Empty Cleared O DRRO has not been read Bit 13 when the MCU writes to MTRO set when the 1 DRRO has been
359. enerator in 0 Parity disabled default Bit 8 the transmitter and the parity checker in the 1 Parity enabled receiver PROE Parity Odd Even Determines the functionality O Even parity default Bit 7 of the parity generator and checker This bit has 1 Odd parity no effect if PREN is cleared STPB Stop Bits Determines the number of stop bits O One stop bit default Bit 6 transmitted The STPB bit has no effect on the 1 Two stop bits receiver which expects one or more stop bits CHSZ Character Size Determines the number of 0 8 character bits default Bit 5 character bits transmitted and expected 1 7 character bits CLKSRC Clock Source Determines the source of the 0 CKIH divided by UBRGR default Bit 4 16x transmit and receive clock This bit should 1 IRQ7 DTR pin not be changed during a transmission Motorola UART 11 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers UBRGR UART Bit Rate Generator Register 0020_4084 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 CD 11 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 8 UBRGR Description Name Description Settings CD 11 0 Clock Divider If the CLKSRC bit in UCR2 is cleared CKIH is divided by a number determined by Bits 11 0 this field to generate the 16x bit clock The actual divisor is equal to the value in CD 11 0 plus one i e a value of
360. er KP KCDD7 KCDD6 KCDD5 KCDD4 KCDDn Description 0 Column strobe n pin is an input 1 Column strobe n pin is an output Keypad Data Direction Register Address 0020_A004 Reset 0000 KRDDn Description Read Write 0 Row n pin is an input 1 Row n pin is an output 15 14 13 12 11 10 9 8 E 7 6 5 4 3 2 1 0 KCDD3 KCDD2 KCDD1 KCDDO KRDD7 KRDD6 KRDD5 KRDD4 KRDD3 KRDD2 KRDD1 KRDDO Read Write KPDR Keypad Data Register Address 0020_A006 Reset 0000 Column Data Bits Row Data Bits 15 14 13 12 11 10 9 8 m 6 5 4 3 2 1 0 KCD7 KCD6 KCD5 KCD4 KCD3 KCD2 KCD1 KCDO KRD7 KRD6 KRD5 KRD4 KRD3 KRD2 KRD1 KRDO Motorola Programmer s Data Sheets E 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer SAP SAPCNT SAP Timer Counter Register Address X FFB4 Reset 0000 SAP Timer Count Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAP Timer Modulus Register AP Timer Modulu Ad
361. er 2 Trigger3 33 Activate QSPI Trigger 3 reserved 3F 34 Reserved for future use CVRO 40 DSP vector Interrupt 0 CVR1 41 DSP vector Interrupt 1 CVR2 42 DSP vector Interrupt 2 CVR3 43 DSP vector Interrupt 3 CVR4 44 DSP vector Interrupt 4 CVR5 45 DSP vector Interrupt 5 CVR6 46 DSP vector Interrupt 6 CVR7 47 DSP vector Interrupt 7 CVR8 48 DSP vector Interrupt 8 CVR9 49 DSP vector Interrupt 9 CVR10 4A DSP vector Interrupt 10 CVR11 4B DSP vector Interrupt 11 CVR12 4C DSP vector Interrupt 12 CVR13 4D DSP vector Interrupt 13 CVR14 4E DSP vector Interrupt 14 CVR15 4F DSP vector Interrupt 15 reserved 57 50 Reserved for future use 10 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers Table 10 4 Protocol Timer Event List Continued Event Name phis Description mcu intO 58 Assert MCUINTO signal mcu_int1 59 Assert MCUINT1 signal mcu int2 5A Assert MCUINT2 signal reserved 5B 5F Reserved for future use dsp_int 60 Assert DSPINT signal reserved 77 61 Reserved for future use reload_counter 78 Load CTIMR register to CTIC table change 79 Load first opcode of non active table end of frame halt 7A Last event of frame and PT halt end of frame repeat 7B Last event of frame and load first opcode of current table end of frame switch 7C Last event of frame and load fi
362. er of frame delays and time interval delays invoked each time the macro uses the delay command For example if a frame table entry calls Rx macro2 the TID and the FD are read from the third entry of the receive delay table When this macro calls a delay the event after it is delayed by a total of FD time intervals per frame TID time intervals The transmit macro works in similar fashion using the TDBA and TDPTR fields in DTPTR to point to an entry in the transmit delay table Motorola Protocol Timer 10 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Operation 10 2 3 Operating Modes The PT provides control bits to determine enable halt and low power operation The various operating modes are summarized in Table 10 1 Table 10 1 Protocol Timer Operation Mode Summary Mode Description Activit Entry to Mode FXitfrom P y y Mode Clocks and Event Counters Execution Disabled Timer disabled GPIO activity disabled disabled TE 0 TE 1 only Normal Full PT operation enabled enabled TE 1 TE 0 HALT PT enters HALT state enabled disabled Set HLTR bitor Clear THS and end_of_frame_ HLTR bits halt command DOZE MCU enters DOZE mode with enabled enabled MCU enters MCU exits TDZD 0 peripheral active DOZE mode DOZE mode DOZE MCU enters DOZE mode with disabled disabled TDZD 1 peripheral stop STOP MCU in STOP mode disabled disabled
363. eripherals to provide a single chip cellular base band processor A block diagram of the 56652 is shown in Figure 1 1 1 1 DSP56652 Key Features The following list summarizes the key features of the DSP56652 e M CORE MCU core 32 bit load store MeCORE RISC architecture Fixed 16 bit instruction length 16 entry 32 bit general purpose register file 32 bit internal address and data buses Efficient four stage fully interlocked execution pipeline Single cycle execution for most instructions two cycles for branches and memory accesses Special branch byte and bit manipulation instructions Support for byte halfword and word memory accesses Fast interrupt support via vectoring auto vectoring and a 16 entry dedicated alternate register file Motorola Introduction 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56652 Key Features Watchdog Programmable Timer PWM Timer Interrupt Timer Edge I O External Smart Card Memory I F RAM M Core Keypad 512 x 32 MicroRISC VF Core ROM Queued 4K x 32 SPI UART Clocks MUX MCU DSP r l l l l DSP PLL Interface 1 MCU i OnCE 1K x 16 Dual Port Messaging i X Data RAM Unit MCU JTAG Serial OnCE Audio CODEC I F X Data X
364. errupts 7 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Interrupt Controller 7 1 5 MCU Interrupt Registers Note All Interrupt Controller registers require full 32 bit accesses ISR Interrupt Source Register 0020_0000 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16 URX SMPC UTX PT2 PT1 PTO PTM QSPI MDI SCP TPW PIT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O KPD URTS INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO S2 S1 SO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 The state of each defined bit out of reset is determined by the interrupt request input of the associated peripheral normally the request is inactive The ISR is a read only that reflects the status of all interrupt request inputs to the interrupt controller The requests are synchronized so that reading the ISR always returns a stable value All unused bits always read as 0 except for S 2 0 which always read as 1 Writes to this register have no effect Table 7 2 ISR Description Name Bit s Interrupt Source Setting URX 31 UART Receiver Ready O No interrupt request 1 Interrupt request pending SMPC 30 SIM Position Change UTX 29 UART Transmitter 2 ORed
365. es the following registers e TPWCR The Timer Control Register enables the GP timer selects the TCNT clock frequency and determines GP timer operation in Debug and DOZE modes e TPWMRI The Timer Mode Register selects the edges that trigger the IC functions determines the action taken for the OC function and can force an output compare on any of the OC channels e TPWSRI The Timer Status Register contains flag bits for each IC and OC event and counter rollover e TPWIRI The Timer Interrupt Register enables interrupts for each IC and OC event and counter rollover e TICR1 2 The Timer Input Capture Registers latch the TCNT value when the programmed edge occurs on the associated IC input e TOCR1 3 4 The Timer Output Compare Registers contain the TCNT values that trigger the programmed OC outputs e TCNT The Timer Counter reflects the current TCNT value Figure 9 5 is a block diagram of the GP timer All GP timer functions are based on a 16 bit free running counter TCNT The PST 2 0 bits in TPWCR select one of eight possible divisions of MCU_CLK as the clock for TCNT PST 2 0 can be changed at any time to select a different frequency for the TCNT clock the change does not take effect until the 8 bit divider rolls over to zero TCNT begins counting when the TE bit in TPWCR is set If TE is later cleared the counter freezes at its current value and resumes counting from that value when TE is set again The MCU can read TC
366. es to STOP mode Another method involves waiting for MDI register events to terminate to supply the needed delay With this method the DSP sends at least one MDI register event and waits until the DEP bit in the DSR is cleared before it enters STOP mode To be sure that an event takes place DSP code can issue a dummy event such as the one illustrated in Example 5 3 The DEP check should be the last MDI access before issuing the STOP instruction to guarantee that the MSR is updated properly Example 5 3 Dummy Event to Allow MCU to Track DSP Power Mode Change movep x lt lt DCR x0 movep x0 X lt lt DCR dummy event write back flags nop snops for pipeline delay nop nop _wait jset ZDEP x DSR wait stop After a DSP wake from STOP command IRQC should be deasserted by writing 1 to the DWSC bit in the DSR Similarly after a protocol timer interrupt event IRQD should be deasserted by writing 1 to the DTIC bit in the DSR Clearing either of these bits just as the DSP exits STOP can serve as the MDI register event for the delay required before the next entry to STOP mode 5 3 3 Shared Memory in DSP STOP Mode The shared memory array operates from the DSP clock for either processor unless the DSP is in STOP mode MCU access to the shared memory is internally synchronized to the DSP clock Memory access signals from the MCU require 2 DSP cycles to synchronize to the DSP clock and 2 MCU cycles to synchronize the DSP acknowle
367. escale com Freescale Semiconductor Inc Low Power Modes 4 2 Low Power Modes The DSP56652 features several modes of operation to conserve power under various conditions Each core can run independently in either the normal WAIT or STOP mode The MCU can also run in the DOZE mode which operates at an activity level between WAIT and STOP Each low power mode is initiated by a software instruction and terminated by an interrupt The wake up interrupt can come from any running peripheral In STOP mode certain stopped peripherals can also generate a wake up interrupt Peripheral operation in low power modes for the MCU and DSP is summarized in Table 4 5 and Table 4 6 respectively Table 4 5 MCU Peripherals in Low Power Mode Peripheral Normal WAIT DOZE STOP MCU Running Stopped Stopped Stopped Protocol Timer Running Running Programmable Stopped QSPI Running Running Programmable Stopped UART Running Running Programmable Stopped can trigger wake up Interrupt Controller Running Running Running Stopped can trigger wake up MCU Timers Running Running Programmable Stopped Watchdog Timer Running Running Programmable Stopped PIT O S interrupt Running Running Running Running GPIO Keypad Running Running Running Stopped can trigger wake up MDI MCU side Running Running Programmable Stopped can trigger wake up SCP Running Running Programmable Stopped JTAG OnCE Ru
368. ess least significant halfword of each register The most significant halfword of all register addresses is 0020 All registers except KPSR are byte addressable with column bits in the most significant byte and row bits in the least significant byte Table 13 2 Keypad Port Register Summary KPCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A000 KCO 7 0 KRE 7 0 KPSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A002 KPKD KDDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A004 KCDD 7 0 KRDD 7 0 KPDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A006 KCD 7 0 KRD 7 0 13 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc KPCR Keypad Port Control Register Bit15 14 13 12 11 10 9 8 7 6 5 Keypad Port Registers 0020_A000 4 3 2 1 Bit 0 KCO 7 0 KRE 7 0 0 0 0 0 0 0 0 0 0 Table 13 3 KPCR Description RESET 0 0 0 0 0 0 0 Name Description Settings KCO 7 0 Bits 15 8 Keypad Column Strobe Open Drain 0 Enable Each bit determines if the corresponding 1 pin functions as a keypad column pin strobe operation open drain output in normal operation totem pole output in low power and standby modes or GPIO totem pole output only GPIO default KP open drain output in normal operation KRE 7 0 Bits 7 0 Keypad Row Interrupt
369. essage 0 long 1 short The unrecognized opcode is returned in the MDI RI register MDI Messaging Unit Registers 13 15 14 8 7 0 RET 0zlong 1 short invalid opcode response MDI R1 bad opcode Figure A 10 Format of invalid opcode response Message MDI RO A 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 3 Comments on Normal Boot Mode Usage This section describes several items to keep in mind when using the normal boot mode 1 Downloads and uploads of DSP program memory require two words in the MDI shared memory space because DSP program words are 24 bits wide The most significant portion upper 8 bits should always we stored in the lower memory address followed by the least significant lower 16 bits in the next higher memory address as illustrated in Figure A 11 23 16 15 0 DSP Program Word 7 0 MDI Word at Lower Address 15 0 MDI Word at Lower Address Figure A 11 Mapping of DSP Program Memory words to MDI message words 2 MDI shared memory size is only 1 Kword Data transfers larger than 1 Kword must be split into multiple uploads or downloads 3 The DSP does not perform any error checking MCU software is responsible for ensuring that addresses are within the MDI memory space 4 Writing MDI_RO should be the final step taken to initiate a message This action affects bits in the MDI st
370. f2 bit TPWSR ifl bit TPWSR of4 bit TPWSR of3 bit TPWSR of1 bit OrRNWBUD TWIR pwoie bit TWIR tovie bit TWIR pwfie bit TWIR if2ie bit TWIR iflie bit TWIR of4ie bit TWIR of3ie bit TWIR oflie bit OrRNWBUD ckctl rsr emddr emdr and gpcr registers register addresses Motorola equ equ ckctl rsr For More Information On This Product 0x0020c000 0x0020c400 Equates and Header Files Go to www freescale com MCU Equates Freescale Semiconductor Inc MCU Equates equ emddr 0x0020c800 equ emdr 0x0020c802 equ gpcr 0x0020cc00 bits of CKCTL equ ckctl ckihd 0x0 equ ckctl mcs 0x1 equ ckctl mca0 0x2 equ ckctl mcdl 0x3 equ ckctl mcd2 Ox4 equ ckctl ckos 0x5 equ ckctl ckoe 0x6 equ ckctl_ckohe 0x7 equ ckctl dcs 0x8 bits of RSR equ rsr exr 0x0 equ rsr wdr 0x1 bits of EMDDR equ emddr emdd0 0x0 equ emddr emddl 0x1 equ emddr emdd2 0x2 equ emddr emdd3 0x3 equ emddr emdd4 0x4 equ emddr emdd5 0x5 bits of EMDR equ emdr edO 0x0 equ emdr endl 0x1 equ emdr emd2 0x2 equ emdr emd3 0x3 equ emdr emd4 0x4 equ emdr emd5 0x5 bits of GPCR equ gpcr gpcO 0x0 equ g r gpcl 0x1 equ gpcr gpc2 0x2 equ gpcr gpc3 0x3 equ gpcr gpc4 0x4 equ gpcr gpc5 0x5 equ gpcr gpc6 0x6 equ g r gpc7 0x7 Keypad Port equ kpp base address 0x0020a000 Module Base Address B 18 DSP56652 User s Manual Mo
371. fered CKIH gt DSP Peripherals CKIH Sine to CMOS Selector DSP Power On Reset Clock DSP_CLK KONG Logic Generator DCS_REF CKOH 2 DCS B gt I MCU iis y g Peripherals gt MCU MCU Clock Divider CKOD MCD 0 2 CKO Figure 4 1 DSP56652 Clock Scheme 4 1 1 MCU CLK MCU CLK is driven by either CKIL or buffered CKIH according to the MCS bit in the CKCTL The input is divided by a power of 2 i e 1 2 4 8 or 16 selected by the MCD bits in the CKCTL The divider has two outputs one for the core clock and one for peripherals to support various low power modes MCU peripherals use a combination of CKIL CKIH and MCU_CLK as shown in Table 4 1 4 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Generation Table 4 1 MCU and MCU Peripherals Clock Source Peripheral Peripheral Clock Source MCU MCU_CLK Protocol Timer MCU_CLK QSPI MCU_CLK UART CKIH MCU_CLK for interface to MCU Serial clock should be slower than MCU_CLK by 1 4 rate Interrupt Controller MCU_CLK MCU Timers MCU_CLK Watchdog Timer CKIL MCU CLK for interface to MCU O S Interrupt PIT CKIL MCU CLK for interface to MCU GPIO Keypad MCU CLK CKIL for interrupt debouncer SCP CKIH MCU CLK for interface to MCU Serial clock should be slower than
372. figuration registers in numerical order e A register index providing an alphabetical list of registers and the page numbers in this manual where they are described e A list of acronym and bit name changes from previous 56000 and M CORE family devices D 1 MCU Instruction Reference Tables Table D 1 provides a brief summary of the instruction set for the MCU Table D 2 on page D 6 and Table D 3 on page D 6 list the abbreviations used in the instruction set summary table For complete MCU instruction set details see Section 3 of the MCU Reference Manual MCORERM AD Table D 1 MCU Instruction Set Summary Mnemonic Instruction Syntax Opcode C Bit ABS ABS RX 0000 0001 1110 rrrr Unaffected ADDC ADDC RX RY 0000 0110 ssss rrrr C lt carryout ADDI ADDI RX OIMM5 0010 000i iiii rrrr Unaffected ADDU ADDU RX RY 0001 1100 ssss rrrr Unaffected AND AND RX RY 0001 0110 ssss rrrr Unaffected ANDI ANDI RX IMM5 0010 0011 0000 rrrr Unaffected ANDN ANDN RX RY 0001 1111 ssss rrrr Unaffected ASR ASR RX RY 0001 1010 ssss rrrr Unaffected Motorola Programmer s Reference D 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Instruction Reference Tables Table D 1 MCU Instruction Set Summary Continued Mnemonic Instruction Syntax Opcode C Bit ASRC ASRC RX 0011 10
373. figured as an output SCDO bit in the SAPCRC or BBPCRC is set 14 20 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers SAPCRC SAP Control Register C X FFB8 BBPCRC BBP Control Register C X FFA8 Biti5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O FSP FSR FSL 1 0 BRM SHFD CKP SCKD SCD2 SCD1 SCDO MOD SYN RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 9 SAP BBP CRC Description Name Description Settings FSP Frame Sync Polarity Determines if frame sync O Active high default Bit 15 is active high or active low 1 Active low FSR Frame Sync Relative Timing Determines if O First bit of current frame default Bit 14 frame sync is asserted at the last bit or the 1 Last bit of previous frame previous frame or the first bit of the current frame This bit is effective for word length frame sync only FSL 1 0 Frame Sync Length These bits determine the 00 TFS and RFS are word length default Bits 13 12 duration word length or bit length for both 01 TFS is bit length RFS is word length transmit and receive frame sync 10 TFS and RFS are bit length 11 TFS is word length RFS is bit length BRM SAP Bit Rate Multiplier SAP only Selects either 0 DSP_CLK default Reserved DSP_CLK or BRM_CLK as the input to the bit 1 BRM CLK BBP clock prescaler Bi
374. g Table 4 13 GPCR Description Continued Name Description Settings GPC1 General Port Control for J12 determines if pin J12 0 INT7 DTR SCLK Bit 1 functions as the EP INT7 signal or the SAP SRDA signal 1 SRDA Either of two UART signals can be implemented on pin J12 if GPC1 is cleared The DTR signal requires programming the pin as an interrupt in the edge port The SCLK signal requires disabling the edge port interrupt and enabling SCLK in UCR2 Setting the MUX_CTL pin configures pin J12 as an alternate JTAG TMS signal GPCO General Port Control for K11 determines if pin K11 O INT6 default Bit O functions as the EP INT6 signal or the SAP STDA signal 1 STDA The UART DSR signal can be implemented on pin K11 by clearing GPCO clearing bit 11 in the NIER and FIER to disable the interrupt and configuring the pin as GPIO Setting the MUX_CTL pin configures pin K11 as an alternate JTAG TRST signal Motorola Core Operation and Configuration 4 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc I O Multiplexing 4 5 2 DSP Address Visibility DSP internal activity can be accessed for debugging by enabling the DSP Address Visibility Mode In this mode the 16 DSP program address lines and an address strobe signal are brought out on the pins listed in Table 4 14 Table 4 14 Pin Function in DSP Address Visibility Mode
375. g messages is shown in Figure A 2 The long message is indicated by clearing the S bit in MDI RO The ten least significant bits of MDI RO indicate an offset address into the MDI shared memory Note that this field is 10 bits wide so that it can point to an offset anywhere in the 1 Kword MDI shared memory space The first entry in the MDI shared memory at the indicated offset location is the message opcode This is followed by as many information words as necessary MDI Messaging Unit Registers 15 14 10 9 0 l MCU address DSP address i MCU_MDI_BASE 2 offset MDI Shared Memory DSP_MDI_BASE offset l message opcode information information Figure A 2 Long Message Format Motorola DSP56652 DSP Bootloader A 3 For More Information On This Product Go to www freescale com Mode A Normal MDI Boot Freescale Semiconductor Inc A 2 2 Message Descriptions Table A 2 summarizes the messages that the bootloader supports Initially the bootloader is in an idle loop awaiting a message from the MCU When it receives a message the DSP processes and executes the command then sends an acknowledgment message back to the MCU The only exception to this procedure is the start_application request message for which there is no acknowledgment message If the DSP receives a message it does not recognize it returns a special invalid opcode response Table A 2 Message Summary Message Message
376. g the EXTEST instruction 0 0 1 0 IDCODE Query identification information manufacturer part number and version from an DSP core based device 0 0 1 1 ENABLE MCU ONCE Provide a means of accessing the MCU OnCE controller and circuits to control a target system 0 1 0 0 HI Z Disable the output drive to pins during circuit board testing 0 1 0 1 CLAMP Force test data onto the outputs of the device while replacing its boundary scan register in the serial data path with a single bit register 0 1 1 0 ENABLE DSP ONCE Provide a means of accessing the DSP OnCE controller and circuits to control a target system 0 1 1 1 DSP DEBUG REQUEST Provide a means of entering the DSP into Debug Mode of operation 1000 1110 Reserved for future use Decoded as BYPASS 1 1 1 1 BYPASS Bypass the DSP56652 chip for a given circuit board test by effectively reducing the BSR to a single cell In the Test Logic Reset controller state the Instruction Register is reset to b0010 which is equivalent to the IDCODE instruction In the Capture IR controller state the two least significant bits of the instruction shift register are parallel loaded with b01 as required by the standard The two most significant bits are loaded with the values of the core status bits OS1 and OSO from the OnCE controller 15 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Fr
377. gister SCPCR To determine the bit rate SIM_CLK is further divided by 372 normal mode or 64 speed enhancement mode controlled by the SIBR bit in the SCPCR SIM_CLK is also gated to the smart card through the SIMCLK pin The pin can be pulled low to save power by clearing the SCCLK bit in the SCACR 12 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 12 2 3 Data Transactions SCP Operation This section describes the SCP data format reception and transmission A summary of NACK timing is also included Data paths are shown in Figure 12 3 A linterna RXDS RX Enable Low Power Data Recovery 11 Bit RX Shift Register 7 6 5 4 3 2 1 64 gt SIBR Par Check ICM Detect RX FIFO 4 TX Buffer Parity eese 11 Bit TX Shift Register Heb o o gt e SCDPE Y SCCLK Figure 12 3 SCP Clocks and Data TX Enable Transmitter Low Power Control Logic CKIH SIM_CLK gt 4 or 372 5 Baud Generator CKSEL Motorola Smart Card Port For More Information On This Product Go to www freescale com gt TXDS 12 5 Freescale Semiconductor Inc SCP Operation 12 2 3 1 Data Format The SC
378. gister read only y endif tpwer register bits define TPWCR TE 0x0040 tpwmsr register bits define TPWSR_OF1 0x0001 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP Periodic Interrupt Timer example usage struct redcap pit pit struct redcap pit REDCAP MCU PIT kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk ifdef _ASSEM define PIT ITCSR 0 define PIT ITDR 2 fdefine PIT ITADR 4 else struct redcap pit volatile unsigned short itcsr control and status register unsigned short itdr data register determines modulo volatile unsigned short itadr alternate data register read only y endif kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP Watchdog Timer example usage struct redcap wdt wdt struct redcap wdt REDCAP MCU WDT dese kkkkkkkkkkkkkkkkkkkkkkkkkkkkkk ifdef _ASSEM define WDT WCR 0 fdefine WDT WSR 2 else struct redcap wdt unsigned short wcr watchdog control register unsigned short wsr watchdog service register y endif kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk B 28 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Include File REDCAP Interrupt Pins example usage struct redcap intpins intpins struct redcap intpins REDCAP MCU INTPINS kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk ifdef ASSEM define INTPINS EPPAR 0 define INTPINS EPDDR 2 define INTPINS EPDR 4 define INTP
379. gister contains the value that is loaded into the PITCNT when it rolls over if the RLD bit in the PITCSR is set The default value is FFFF PITCNT PIT Counter 0020_7004 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O AA um aep ur spes A A This read only register provides access to the PIT counter value The reset value is indeterminate RESET 9 2 Watchdog Timer The watchdog timer protects against system failures by providing a means to escape from unexpected events or programming errors Once the timer is enabled it must be periodically serviced by software or it will time out and assert the Reset signal 9 2 1 Watchdog Timer Operation The watchdog timer uses the following registers e WCR The Watchdog Control Register enables the timer loads the watchdog counter and controls operation in Debug and DOZE modes e WSR The Watchdog Service Register is used to reinitialize the timer periodically to prevent it from timing out The watchdog timer is disabled at reset Once it is enabled by setting the WDE bit in the WCR it cannot be disabled again The timer contains a 6 bit counter that is initialized to the value in the WT field in the WCR This counter is decremented by each cycle of the watchdog clock which runs at a fixed rate of CKIL 2 Thus for CKIL 32 768KHz the watchdog timeout period can range from 0 5 seconds to 32 seconds The counter is initialized to the value in the WT field when the watchdog timer is ena
380. gs TE Transmit Enable Enables the SAP or BBP 0 Transmitter disabled default Bit 8 transmitter by allowing data transfer from the 1 Transmitter enabled Transmit Register to the transmit shift register Note The TE bit does not affect the generation of frame sync or output flags RCIE BBP BBP Receive Counter Interrupt Enable O Interrupt disabled default Bit 7 Setting this bit enables an interrupt when the BBP 1 Interrupt enabled receive counter rolls over TCIE BBP BBP Transmit Counter Interrupt Enable O Interrupt disabled default Bit 6 Setting this bit enables an interrupt when the BBP 1 Interrupt enabled transmit counter rolls over RCE BBP BBP Receive Counter Enable Enables the O Counter disabled default Bit 5 BBP receive frame sync counter 1 Counter enabled TCE BBP BBP Transmit Counter Enable Enables the O Counter disabled default Bit 4 BBP transmit frame sync counter 1 Counter enabled TCE SAP SAP Timer Count Enable Enables the SAP O Timer disabled default Bit 2 general purpose timer 1 Timer enabled OF1 Output Flag 1 In synchronous mode SYN bit in the SAPCRC or BBPCRC is set this bit drives Bit 1 serial output flag 1 on the SC1x pin if it is configured as an output SCD1 bit in the SAPCRC or BBPCRC is set OFO Output Flag 0 In synchronous mode SYN bit in the SAPCRC or BBPCRC is set this bit drives Bit 0 serial output flag 0 on the SCOx pin if it is con
381. he SAPSR or BBPSR is set If RDF is set when the shift register is full indicating that the previous received word has not been read the Receive Overrun Error ROE bit in the SAPSR or BBPSR is set and an interrupt is generated if the Receive Error Interrupt Enable REIE bit in the SAPCRB or BBPCRB has been set The newer data is lost Motorola Serial Audio and Baseband Ports 14 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Reset 14 4 3 Data Formats Data words can be 8 12 or 16 bits long Word length is determined by the WL 1 0 bits in the SAPCRA or BBPCRA The shift registers in the SAP and BBP are bidirectional to accommodate data formats that specify MSB first such as those used by codecs and LSB first such as those used by AES EBU digital audio Selection of MSB or LSB first is determined by the SHFD bit in the SAPCRC or BBPCRC 14 5 Software Reset Either port can be reset without disturbing the rest of the system by clearing the PC 5 0 bits in the Port Control Register SAPPCR or BBPPCR This action stops all serial activity and resets the status bits the contents of SAPCRA SAPCRB and SAPCRC are not affected The port remains in reset while all pins are programmed as GPIO and becomes active 1 e functions as the SAP or BBP only if at least one of the pins is programmed as a SAP or BBP pin Note To ensure proper operation of the interface the DSP
382. he Timer IC2 signal 1C2 Setting the MUX_CTL pin configures pin E11 as an alternate RESET_IN signal GPC6 General Port Control for G11 determines if pin G11 ROWT RI Bit 6 functions as the Keypad ROW7 signal or the SAP SCKA SCKA signal The UART RI signal can be implemented on pin G11 by using ROW7 as a general purpose output Setting the MUX_CTL pin configures pin G11 as an alternate JTAG TCK signal GPC5 General Port Control for G13 determines if pin G13 0 ROW6 DCD Bit 5 functions as the Keypad ROWG6 signal or the SAP SC2A 1 SC2A signal The UART DCD signal can be implemented on pin G13 by clearing GPC5 and using ROW6 as a general purpose output Setting the MUX_CTL pin configures pin G13 as an alternate DSP_DE signal GPC4 General Port Control for H14 determines if pin H14 0 ROWS default Bit functions as the Keypad ROWS signal or the Timer IC2 1 1C2 signal This pin is not affected by MUX_CTL GPC3 General Port Control for M13 determines if pin M13 COL7 default Bit 3 functions as the Keypad COL7 signal or the Timer PWM PWM signal This pin is not affected by MUX_CTL GPC2 General Port Control for N13 determines if pin M13 0 COL6 default Bit 2 functions as the Keypad COL6 signal or the Timer OC1 1 OC1 signal This pin is not affected by MUX_CTL 4 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc I O Multiplexin
383. he various SCP interrupts is also provided 12 2 1 Activation Deactivation Control The smart card power up and power down sequences are specified in ISO 7816 3 and GSM 11 11 The signals and control bits provided by the DSP56652 to implement these sequences are illustrated in Figure 12 2 and described below SENSE Edge Set Level Detect mn a Interrupt SMSCIE SMPC Flipflop Clock Enable Interrupt SIM CLK SCCLK CLR E SIMCLK SCDPE_CLR MGU CLK SCP Automatic aa Power Down SCRS CLR Logic SIMRESET MESE SCPE PWR EN SCP Control Bits Figure 12 2 SCP Port Interface and Auto Power Down Logic When the port is enabled the SENSE input detects insertion and removal of the smart card initiating SCP activation and deactivation Inserting the card pulls the SENSE pin low and removing the card pulls the pin high The SENSE pin state is reflected in the SCSP bit in the SCP Status Register SCPSR A rising or falling edge on the SENSE pin sets the SMSC flag in the SCPSR and can generate an interrupt if the SMSCIE bit in the SCP Interrupt Enable Register SCPIER is set Motorola Smart Card Port 12 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Operation The power up sequence specified in ISO 7816 is implemented by the DSP56652 as follows 1 The SIMRESET pin is asserted pulled low
384. her an external or internally generated clock through the CLKSRC bit in UCR2 Clearing CLKSRC selects the internal clock which is derived by dividing CKIH by a number between 1 and 4096 determined by UBRGR This provides sufficient flexibility to generate standard baud rates from a variety of clock sources Clock error calculation is straightforward as shown in Example 11 1 Example 11 1 UART Baud Error Calculation Desired baud rate 115 2 kbps Input clock 16 8 MHz Divide ratio 9 UBRGR 11 0 8 Actual baud rate 16 8 MHz 9 16 116 67 kHz Actual required ratio 116 67 115 2 1 0127 Error per bit 1 27 Error per 12 bit frame 15 Setting the CLKSRC bit selects an external clock SCLK which is input on the INT7 DTR pin 11 3 4 Baud Rate Detection Autobaud The baud rate from the far end transmitter can be determined in software by observing the duration of the logic one and logic zero states of the Input Capture 1 IC1 module which is internally connected to RxD for this purpose 11 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Operation 11 3 5 Low Power Modes The UART serial interface operates as long as the 16x bit clock generator is provided with a clock and the UART is enabled the UARTEN bit in UCR1 is set The internal bus interface is operational if the system clock is running The RXEN TXEN and UARTEN
385. hese pins multiplex various peripherals primarily with the JTAG Debug Port The other 17 pins multiplex peripherals with the DSP Address Trace function 4 5 1 Debug Port and Timer Multiplexing The eight pins listed in Table 4 11 multiplex various peripherals with the Debug Port The pins in Table 4 12 also multiplex different peripherals but are not part of the Debug Port The functions of these pins are determined by the following controls 1 Asserting the MUX CTL pin configures all of the pins in Table 4 11 as debugging signals effectively creating an alternate set of pins for RESET IN MCU DE DSP DE and the five JTAG signals These eight pins can be brought out externally to facilitate debugging Asserting MUX CTL overrides all other controls for these pins MUX_CTL does not affect the pins in Table 4 12 2 Each of eight bits in the GPCR selects the peripheral to which the associated pin is connected Five GPCR bits control pins in Table 4 11 if MUX CTL is not asserted the other three bits control the pins in Table 4 12 3 Once a pin is assigned to a peripheral MUX CTL 0 and or the associated GPCR bit is written that peripheral s Port Configuration Register determines if the pin is configured for the peripheral function or GPIO Motorola Core Operation and Configuration 4 15 For More Information On This Product Go to www freescale com I O Multiplexing Freescale Semiconductor Inc
386. hip select signals for the QSPI The signals are programmable as active high or active low SCK Output Input Serial Clock This output signal provides the serial clock from the QSPI for the accessed peripherals The delay number of clock cycles between the assertion of the chip select signals and the first transmission of the serial clock is programmable The polarity and phase of SCK are also programmable MISO Input Input Synchronous Master In Slave Out This input signal provides serial data input to the QSPI Input data can be sampled on the rising or falling edge of SCK and received in QSPI RAM most significant bit or least significant bit first MOSI Output Input Synchronous Master Out Slave In This output signal provides serial data output from the QSPI Output data can be sampled on the rising or falling edge of SCK and transmitted most significant bit or least significant bit first Motorola For M Signal Connection Description 2 15 ore Information On This Product Go to www freescale com SCP 2 11 SCP The signals described in Table 2 14 are GPIO when not programmed otherwise and default as GPI after reset Freescale Semiconductor Inc Table 2 14 SCP Signals Signal Name Type Reset State Signal Description SIMCLK Output Input SIM Clock This signal is an output clock from the SCP to the smart card SENSE Input Input SI
387. hould not be set in both registers simultaneously or both a normal and fast interrupt request will be generated 2 Enable interrupts in the core by setting the following bits in the MeCORE Program Status Register Exception Enable EE Interrupt Enable IE Fast Interrupt Enable FE Refer to the MeCORE Reference Manual for more information on this register Steps 1 and 2 are normally done once during system initialization 3 For each source from which interrupts are to be used program the appropriate peripheral registers to generate interrupt requests 7 1 4 Interrupt Sources Table 7 1 lists each MCU interrupt source the ISR bit that indicates when the interrupt is asserted and a page reference to the register that enables the interrupt Several interrupt sources are logically ORed because there are more sources than there are inputs to the interrupt controller In these cases the peripheral s status register must be queried to determine the source of the interrupt within the peripheral Table 7 1 MCU Interrupt Sources Interrupt ISR Bit Where Source Remarks Name amp No Source s Enabled Page MDI 6 ORed MDI 23 MCU Transmit Interrupt O 1 MCR 5 19 MCU Receive Interrupt O 1 MCU General Interrupt O 1 7 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Interrupt Controller
388. ht hm ERN UR 8 3 Programmable Delay after Transfer yn cis penx Copas sews Ra ee eae 8 3 Loading a Programmable Address at the End of Queue 8 3 Pause Enable at Queue Entry Boundaries 0 00000 8 3 OSP IAT Chine CS x EC FA oe tava eee aie eave ES 8 3 OSPDPIDSZ 44e fuese SERRE a e de o las lo ca e e 8 4 Control RESISCIS e oe eso sie SURE INE ae onini AR d ate sae wee Sn 8 6 Functional Modules cco eve aces er DA 8 7 RAN uno Adv 8 7 OSPLODBOFAUOIT d stas ea y ae 8 8 A A LEER ee Ore ee ES 8 8 Queue Transfer Gy Cle 3 4 is he ous Desk 8 9 Ends rastras a Send KR ES tee eee es 8 10 Breaking a Transfer C ales 8 10 Palin th OSPI ss asser dte te t o be EXER 8 11 ENTORNOS quote ay ace ee au Sade doe etes dat S asta e quce SUR 8 11 Low Power Modes ocv bw eX Na ne eu qe AE ER REN Rede PN 8 11 OSPLRegisters and Memory toa ERR UE wee cine Seah see ae we Se 8 12 OSPDCOBUODPISCSISICTS S S asco quiete RAE ews SUE 8 13 MCU Transter DHesers Seco quedesc verc v EN ER RR RUE REN TR RH RUE 8 22 Control And Data RAM ker Rei ad debis 8 22 GPIO R sistetS Gu aad grec ape S See dtp te Nu go eb di e ree dique ios 8 24 Chapter 9 Timers Periodic Interrupt Timer uu oue opa price ed Aas dco Roh ee baie ro aru oe EAE S 9 PUT eT AOU uu Asse ann he um SA reli Lum pA Ci ILC Te tla hy 9 1 PLE REIS a ie E NN DE EA 9 3 Watchdog Timer 4 05 a A AA EINER ah 9 4 Watchdog Timer Operaliomu s od edu vedi au EAE M eed S ad EA Rat 9 4 Watchd
389. i cnt Sb adus 2 6 Chip Select Signals eee tone ES VEO E a ESO NA DERE 2 6 Reset Mode and Multiplexer Control Signals luus 2 7 Interrupt Signals 5 05 RDA AAA SS 2 8 Protocol Timer Output Signals 2 9 Keypad Port Signals oce vas TO ARI RA 2 10 UART Srenals us a sean eee Poel HER eee ae 2 13 OSPI Sienals Es oe reek eee ERAS 2 15 DCP Sie als A A eee eas 2 16 O 2 16 BBP Signals ss A MEE EM 2 18 Emulation Port Signals 24425 42 p39 plone Oe PAE RE A 2 18 Debug Control Send cross t Seo eet us Ao 2 19 JTAG P rt Signal Se dai acea SIN cr eum edocet s 2 19 MCU and MCU Peripherals Clock Source o ooo ooooommooo o o 4 3 ERCTL Descrip ich oM aki it eters woe tt ee seh Rot ui 4 5 PC TEO DSSCHDBUOS eret orsus as e ada SER SUERTE 4 6 PGT Description 5 us mde decebat No dC eS a VS 4 7 MCU Peripherals in Low Power Mode 20 02 e eee eee 4 8 DSP Peripherals in Low Power Modes 20 eese 4 8 Programmable Power Saving Features 0 000000 eee 4 9 RSR Description Ai As Rae epa A Rae EOE AS 4 11 List of Tables XV For More Information On This Product Go to www freescale com Table 4 9 Table 4 10 Table 4 11 Table 4 12 Table 4 13 Table 4 14 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 5 11 Table 5 12 Table 5 13 Table 5 14 Table 5 15 Table 5 16 Table 5 17 Table 5 18 Table 5 19 Table
390. ible CS s address space Cycle length is not affected 1 EBO 1 negated one half cycle earlier and read cycles are not affected If WSC 3 0 during a write 0000 WEN is ignored and is EBO 1 are asserted for half a clock only WEN is useful for meeting data hold time requirements for slow memories EBC Enable Byte Control When EBC is set only O EBO 1 asserted for both reads and writes Bit 6 write accesses assert the EBO 1 outputs thus 1 EBO 1 asserted for writes only configuring them as byte write enables EBC should be set for accesses to dual x8 memories DSZ 1 0 Data Port Size These bits define the width of the 00 8 bit port on D 15 8 pins Bits 5 4 device data port 01 8 bit port on D 7 0 pins 10 16 bit port on D 15 0 pins 11 Reserved 6 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Registers Table 6 6 CSCRn Description Continued Name Description Settings SP Supervisor Protect Prohibits User Mode O User Mode access allowed Bit 3 accesses to the CS address space When SP is 1 User Mode access prohibited set a read or write to the CS space while in User Mode generates a TEA error and the CS signal is not asserted WP Write Protect Prohibits writes to the CS address 0 Writes allowed Bit 2 space When WP is set a write attempt to the CS 1 Writes prohibited space
391. in If the word length is less than 16 bits the data is shifted into the most significant bits RESET SAPTSR SAP Time Slot Register X FFBB BBPTSR BBP Time Slot Register X FFAB Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O Dummy RESET This dummy write only register is written to avoid a transmit underrun error for a time slot for which no data is to be transmitted SAPTX SAP Transmit Data Register X FFBC BBPTX BBP Transmit Data Register X FFAC Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O Transmit Word RESET This write only register loads its data into the transmit shift register If the word length is less than 16 bits writes to this register should occupy the most significant bits Motorola Serial Audio and Baseband Ports 14 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers 14 9 2 GPIO Registers SAPPDR SAP Port Data Register X FFBD Bitib 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O SAPPD5 SAPPD4 SAPPD3 SAPPD2 SAPPD1 SAPPDO STDA SRDA SCKA SC2A SC1A SCOA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BBPPDR BBP Port Data Register X FFAD Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 5 BBPPD5 BBPPD4 BBPPD3 BBPPD2 BBPPD1 BBPPDO STDB SRDB SCKB SC2B SC1B SC
392. in is input Pin is outut 9 8 7 6 5 QDD7 QDD6 QDD5 QDD4 4 3 2 1 QDD3 QDD2 QDD1 0 QDDO QPDR QSPI Port Data Register Address 0020_5F04 Reset 00uu Read Write Port Data Bits 8 7 6 5 4 3 2 1 0 Reserved QPD7 QPD6 QPD5 QPD4 QPD3 QPD2 QPD1 QPDO Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 49 Application Freescale Semiconductor Inc Date Programmer Reserved P IT ITIE Description 0 PIT interrupt disabled P ITC S R 1 PIT interrupt enabled PIT Control and Status Register Address 0020_7000 ITIF Description Reset 0000 Read Write 0 PITCNT has not reached zero 1 PITCNT has rolled over OVW Description 0 Write to modulus latch does not RLD Description overwrite PITCNT 0 Counter rolls over to FFFF 1 Write to modulus latch immediately overwrites PITCNT 1 Counter rolls over to PITMR value DBG Description 0 PIT not affected by Debug mode 1 PIT halted by Debug mode 15 14 13 12 11 10 8 7 5 4 3 2 1 0 DBG OVW ITIE ITIF RLD 0 0 0
393. ing 0 No interrupt pending 1 INT2 interrupt request pending 1 INT5 interrupt request pending FINT1 Description FINT6 Description 0 No interrupt pending 0 No interrupt pending 1 INT1 interrupt request pending 1 INT6 interrupt request pending FINTO Description FINT7 Description 0 No interrupt pending 0 No interrupt pending 1 INTO interrupt request pending 1 INT7 interrupt request pending FS2 Description FURTS Description 0 No interrupt pending 0 No interrupt pending 1 Software Interrupt 2 request pending 1 UART RTS Delta interrupt request pending FS1 Description 0 No interrupt pending FKPD Description 1 Software Interrupt 1 request pending 0 No interrupt pending 1 Keypad Interface interrupt request FSO Description pending 0 No interrupt pending 1 Software Interrupt 0 request pending 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 FKPD FURTS FINT FINT6 FINTS FINT4 FINTS FINT2 FINT1 FINTO FS2 FS1 FSO 0 0 0 NOTE FIPR can only be written as a 32 bit Reserved E 34 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer Upper Halfword Interrupt Control Register Upper Halfword Address 0020 0014 Reset 0000 Read Write Accessible Only in Supervisor Mode 31 30 29 28 27 26 25 24 23 22 21
394. initiated the bus watchdog timer expires and forces the access to be terminated by negating the Chip Select output and any control signals that were asserted during the access The bus watchdog timer then asserts a TEA signal back to the MCU resulting in an access error exception The bus watchdog timer is automatically reset after the termination of each access If for some reason an internal MCU peripheral does not terminate its access to the MCU or if the MCU accesses an unmapped location the bus watchdog times out and prevents the MCU from locking up Motorola External Interface Module 6 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Features Table 6 3 Interface Requirements for Read and Write Cycles Signal Encoding Active Interface Bus Sections Transfer ue Internal Internal Internal Internal d 120 A an DSZ 1 0 D 31 24 D 23 16 D 15 8 D 7 0 0 1 0 0 00 D 15 8 01 D 7 0 D 15 8 0 1 D 15 8 D 7 0 D 7 0 1 0 D 15 8 D 7 0 E D 15 8 1 1 D 15 8 Ec D 7 0 z D 7 0 Halfword 1 0 X D 15 8 D 15 8 D 7 0 D 7 0 n D 15 8 D 7 0 x 1 X D 15 8 D 15 8 D 7 0 D 7 0 B D 15 8 D 7 0 Word x X D 15 8 D 15 8 D 15 8 D 15 8 D 7 0 D 7 0 D 7 0 D 7 0 D 15 8 D 7 0
395. ion Register EIMCR When show cycles are enabled the EIM drives the internal address bus A 21 0 onto the external address bus pins A21 A0 In addition the internal data bus D 31 16 or D 15 0 is driven onto the external data bus pins D15 DO according to the HDB bit in the EIMCR 6 3 6 Programmable Output Generation Any chip select signal except CSO can be used as general purpose output by clearing the CSEN bit in the corresponding CS control register When the CSEN bit in the CSO register is cleared CSO is inactive Motorola External Interface Module 6 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Features 6 3 7 Emulation Port The DSP56652 provides a six pin Emulation Port for debugging to provide information about the data size and pipeline status of the current bus cycle The SIZ 1 0 pins indicate the data size using the encoding shown in Table 6 4 The PSTAT 3 0 pins provide pipeline information as shown in Table 6 5 The Emulation Port is enabled by the EPEN bit in the EIMCR and serve as GPIO pins if the port is not enabled Table 6 4 SIZ 1 0 Encoding SIZ1 SIZO Transfer Size 0 0 Word 32 bits 0 1 Byte 8 bits 1 0 Halfword 16 bits 1 1 Reserved Table 6 5 PSTAT 3 0 Encoding PSTAT3 PSTAT2 PSTAT1 PSTATO Internal Processor Status 0 0 0 0 Execution Stalled 0 0 0 1 Exe
396. is generated with PSR 1 and PM 7 0 1 yielding Bit clock frequency BRGCLK BRGCLK 2x 1 x 2 4 If the bit clock is supplied externally the maximum allowed frequency is DSP_CLK 3 14 2 3 Clock Polarity The Clock Polarity CKP bit in the SAPCRC or BBPCRC determines the clock edge on which data and frame sync are clocked out and latched in When the CKP bit is cleared data and frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock When the CKP bit is set data and frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock 14 2 4 Bit Rate Multiplier SAP Only The BRM provides a way for systems with a CKIH of 16 8 MHz to generate a SAP bit clock with the standard codec frequency of 2 048 MHz The BRM applies a 512 525 multiplier to DSP_CLK to generate a 16 384 MHz BRM_CLK from a 16 8 MHz input To generate a 2 048 MHz bit clock perform the following steps 1 Set the BRM bit in the SAPCRC to select BRM_CLK rather than DSP_CLK as the bit rate clock source BRGCLK 2 Set the PSR bit in SAPCRA to disable the prescaler 3 Write 03 to the PM 7 0 bits in the SAPCRA to divide the 16 384 MHz BRGCLK by four Motorola Serial Audio and Baseband Ports 14 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TDM Options 14 3 TDM Options
397. is masked 1 Periodic Interrupt Timer interrupt source enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EFURX EFSMPD EFUTX EFPT2 EFPT1 EFPTO EFPTM EFQSPI EFMDI EFSCP EFTPW EFPIT NOTE FIER can only be written as a 32 bit Reserved Motorola Programmer s Data Sheets E 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer MCU Interrupts FIER Lower Halfword Fast Interrupt Enable Register Lower Halfword Reset 0000 Read Write EFINT5 Description 0 Interrupt source is masked 1 INT5 interrupt source enabled EFINT6 Description 0 Interrupt source is masked 1 INT6 interrupt source enabled EFINT7 Description 0 Interrupt source is masked 1 INT7 interrupt source enabled EFURTS Description 0 Interrupt source is masked 1 UART RTS Delta interrupt source enabled EFKPD Description 0 Interrupt source is masked 1 Keypad Interface interrupt source enabled EFINT4 Description 0 Interrupt source is masked 1 INT4 interrupt source enabled EFINT3 Description 0 Interrupt source is
398. is set a NACK is sent to the smart card The new character is not transferred to the FIFO and is overwritten if another character is received before the FIFO is read Any of the three error conditions generates an interrupt if the SCREIE bit in the SCPIER is set 12 2 3 4 Data Transmission To send a character the MCU should clear the SCRE bit and set the SCTE bit to enable transmission The MCU then writes to the SCPDR the data is stored in a transmit buffer and the SCP transmits the data to the card over the SIMDATA pin The SCP outputs a start bit eight character bits least significant bit first a parity bit and two stop bits If the smart card detects a parity error in the transmission it sends a NACK back to the SCP the SCP alerts the MCU of the failure by setting the TXNK bit in the SCPSR and the MCU must retry the transmission by writing the same data to SCPDR When a frame has been transmitted the transmit buffer is cleared and the SCTC flag in the SCPSR is set if the SCTCIE bit in the SCPIER has been set an interrupt is generated Although a transmission in progress will complete if the transmitter is disabled it is recommended that software waits until SCTC is set before clearing the SCTE bit 12 2 3 5 NACK Timing The following is a summary of the timing for NACK signals as specified in ISO 7816 The unit of time used by the specification is the Elementary Time Unit or etu which is defined as one bit time A NACK puls
399. it prot ptevr rxma 0x1 active Rx macro indicator bit prot ptevr txma 0x2 active Tx macro indicator bit prot ptevr thip 0x3 timer halt in progress indicator bit prot tipr tipv 0 prot tipr tipv 1 prot tipr tipv 2 prot tipr tipv 3 prot tipr tipv 4 prot tipr tipv 5 prot tipr tipv 6 prot tipr tipv 7 prot tipr tipv 8 prot timl timv 0 prot i timl tiny r 1 prot i timl tinv EZ prot timl tinv 3 prot i timl _ tinv 4 prot i timl timv 5 prot timl tinv 6 prot i timl timv a prot timl tinv 8 prot ctic ctiv 0 prot ctic ctiv 1 prot ctic ctiv 2 prot ctic ctiv 3 prot ctic ctiv 4 prot ctic ctiv 5 prot ctic ctiv 6 prot ctic ctiv 7 prot ctic ctiv 8 prot ctic ctiv 9 prot ctic ctiv 10 prot ctic ctiv 11 prot ctic ctiv 12 prot ctic ctiv 13 0x0 0x1 0X2 0x3 0x4 0x5 0x6 Ox7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 Ox7 0x8 prot ctipr ctipv 0 prot ctipr ctipv 1 TIPR value bit 0 TIPR value bit TIPR value bit TIPR value bit TIPR value bit TIPR value bit TIPR value bit TIPR value bit TIPR value bit timl value bit timl value bit timl value bit timl value bit timl value bit timl value bit timl value bit timl value bit timl value bit the Channel Time Interval Counter CTIC 0 O UH CO FO ILLO 0 ONU CO PO ILS CO 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 Oxa Oxb Oxc Oxd
400. it in the QCR of the current queue is asserted the value in the least significant byte of the data halfword in that queue entry is written into the queue s QP Motorola Queued Serial Peripheral Interface 8 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory 8 4 3 2 Data RAM Data halfwords can contain transmission data stored in RAM by the MCU or data received by the QSPI from external peripherals The MCU can read the received data halfwords from RAM Data is transmitted and received by the QSPI as either least or most significant bit first depending on the LSBF bit in SCCR for the associated channel Access to the RAM is arbitrated between the QSPI and the MCU Because of this arbitration wait states can be inserted into MCU access times when the QSPI is in operation Received data is written to the same address at which the transmitted data 1s stored and overwrites it so care must be taken to ensure that no data is lost when receiving is enabled 8 4 4 GPIO Registers Any of the eight QSPI pins can function as GPIO The registers governing GPIO functions are described below QPCR QSPI Port Configuration Register 0020 5F00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O QPC7 apce QPC5 QPC4 QPC3 QPC2 GPC1 QPCO SCK MOSI MISO SPICSA SPICS3 SPICS2 SPICS1 SPICSO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8 8 QPCR Description
401. ite request mdimemtH program length mdimemt 10 14 4 10 download to P memory 4 data starts following this header information mdimemt dsp program address write dsp program to MDI most significant part first for i 0 i lt program length i mdimen unsigned short dsp program i gt gt 16 mdimem t unsigned short dsp program i initiate this long message by writing to MIRO register MTRO 0 msb 0 long message lsbs 0 gt offset 0 wait for acknowledgement from DSP by polling the MRFO bit in MSR while MSR amp MRF0 O read and test the short message memory write response if MRRO 8001 exit 1 DSP write error start the DSP application reset the mdi memory pointer to beginning of mdi mdimem unsigned short MDI MEM ADDR write the long message header mdimemt start application request xmdimem dsp program address initiate the long message by writing to MIRO reg MIRO 0 msb 0 long message lsbs 0 offset 0 A 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode B Shared Memory Boot A 3 Mode B Shared Memory Boot The shared memory boot mode can be used if all that is required is to fill the lower 0 5K DSP program RAM and begin execution at DSP program address P 0000 The
402. iting 1 to this bit clears the MTIR bit in the MSR thus deasserting IRQD and IRQA which is wire or d to IRQD and enabling MTIR to receive another interrupt DTIC always reads zero MCP R MCU Command Pending Set when the MC O No outstanding DSP command Bit 8 bit in the MCVR is set page 5 18 cleared interrupt default when the interrupt generated by setting MC is 1 DSP command interrupt has been serviced issued and has not been serviced Motorola MCU DSP Interface 5 25 For More Information On This Product Go to www freescale com MDI Registers Freescale Semiconductor Inc Table 5 18 DSR Description Continued Name Type Description Settings DWSC 1S DSP Wake from STOP and Interrupt Clear Used by the MDI Wake from STOP and Bit 7 general interrupt IRQC service routine to clear the interrupt Writing 1 to this bit clears the DWS bit in the MSR thus de asserting IRQC and IRQA and enabling DWS to receive another interrupt MPM 1 0 R MCU Power Mode Reflect the MCU power 00 STOP Bits 6 5 mode 01 WAIT 10 DOZE 11 Normal DEP R DSP Side Event Pending Set when the O Last event update request to MCU Bit 4 DSP sends an event update request to the has been acknowledged default MCU side Cleared when the event update 1 Event update request to MCU acknowledge has been received An event pending is any hardware message that should be reflected in the MSR on the
403. ity bit and two stop bits The polarity of the parity bit can established either by programming a register or in the initial Character mode by hardware at the beginning of each communication session Both the card and the port can indicate receiving a corrupted frame no stop bit by issuing a NACK signal pulling the SIMDATA pin low during the stop bit period The SCP can also issue a NACK to the card when its receive buffer overflows to avoid losing further data when it receives incorrect parity and when it receives incorrect protocol data in Initial Character mode Flags and optional interrupts are provided for the three NACK signals The receiver also has flags and optional interrupts to indicate parity error frame error and receiver overrun The SCP generates a primary data clock SIM_CLK which is further divided to generate the bit rate SIM_CLK also drives the SIMCLK pin which can be synchronously pulled low by software 12 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Operation 12 1 3 Power Up Down A transition on the SENSE pin triggers both power up and power down sequences Power up is done under software control while power down can be controlled either by software or hardware 12 2 SCP Operation This section describes SCP activation and deactivation clock generation data transactions and low power mode operation A summary of t
404. ivated using a software protocol between the DSP and the external source signaling the external device when to deassert the interrupt IAPL 1 0 Interrupt A Priority Level This interrupt should remain Bits 1 0 disabled 7 3 Edge Port The Edge Port EP consists of eight GPIO pins INT7 0 each of which can generate an interrupt if the associated bit in the NIER or FIER is set This port is controlled by four configuration registers e EPPAR The EP Pin Assignment Register configures the trigger mechanism for each pin level sensitive or rising and or falling edge triggered e EPFR The EP Flag Register contains bits that are set when the associated Edge I O inputs are triggered e EPDDR The EP Data Direction Register configures each pin as either an input or output Motorola Interrupts 7 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Edge Port e EPDR The EP Data Register serves as a GPIO buffer A write to this register determines the data driven on output pins data received on input pins can be read from this register A diagram of an Edge I O pin is shown in Figure 7 4 EPPAR 2n 1 EPPAR 2n J EPPAR 2n 1 Falling Edge W Detect EPFR Rising Edge e Detect f To Interrupt 4 Dx Controller EPPARn MCU Peripheral Bus EPDDRn Figure 7 4 Edge l O Pin 7 16 DSP56652 User s Manual M
405. ive low Schmitt trigger input that provides a reset signal to the internal circuitry The input is valid if it is asserted for at least three CKIL clock cycles Note When this signal is enabled the primary RESET IN signal is disabled See Table 2 8 on page 2 7 Normal MUX CTL driven low CTS Input or Output Input Clear To Send This signal functions as the UART CTS signal Alternate MU X CTL driven high MCU DE Input or Output Microcontroller Debug Event As an input this signal provides a means to enter the debug mode of operation from an external command converter As an output signal it acknowledges that the MCU has entered the debug mode When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition it asserts MCU DE as an output signal for several clock cycles When this signal is enabled the primary MCU DE signal is disabled Note 2 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com 2 10 QSPI The signals described in Table 2 13 are GPIO when not programmed otherwise and default as GPI after reset Freescale Semiconductor Inc QSPI Table 2 13 QSPI Signals Signal Name Type Reset State Signal Description SPICSO SPICS4 Output Input Serial Peripheral Interface Chip Select 0 4 These output signals provide c
406. kkkkkkk code for SPS test modes resides here F ekkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk boot modes A B C AEREE RERE ERA RE RAR RARE RAR RARE RARA RARA RE RAR RARE RRA RARA RRA RE RARE RE RARA RARA START BOOT e if we got here STDA or STDB must have been set jclr STDA x PDRA START BOOT MODE B jclr STDB x PDRB START BOOT MODE C else both set continue with BOOT MODE A ekkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk BOOT MODE A NORMAL MODE gE RK KKK RARA ARK AR ARK A RAR RARE RARA RARA AAA RARA KER EKER AR RRA RARA RARA START BOOT MODE A e _wait jclr DRF0 x DSR _wait wait till DRRO is full read message from DRRO movep x DRRO x0 short or long message jclr 715 x0 1ong message Motorola DSP56652 DSP Bootloader For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program else it s a short message handle short messages short message there are currently no allowed short messages return an invalid message indication move gt inval_short_msg x1 jmp lt invalid message handle long messages long message retrieve long message opcode move x0 a and S03FF a save only lower 10 bits offset add MDI_base a add MDI base address move al r0 move x r0 x0 x0 long message opcode which long message is it move x0 a
407. l 0x5 MCU interrupt 1 bit equ prot tstr mcui2 0x6 MCU interrupt 2 bit equ prot tstr dsi 0x9 DSP interrupt bit equ prot tstr dvi Oxa DSP vector interrupt bit equ prot tstr thi Oxb Timer haltinterrupt bit equ prot tstr teri Oxc Timer error interrupt bit bits of the Protocol Timer Status Register PTSR NEW NAMES equ prot ptsr cfi 0x0 channel frame interrupt bit equ prot ptsr cfni 0x1 channel frame number interrupt bit equ prot ptsr rsni 0x2 reference slot number interrupt bit equ prot ptsr mcui0 0x4 MCU interrupt 0 bit equ prot ptsr mcuil 0x5 MCU interrupt 1 bit equ prot ptsr mcui2 0x6 MCU interrupt 2 bit equ prot ptsr dsi 0x9 DSP interrupt bit equ prot ptsr dvi xa DSP vector interrupt bit equ prot ptsr thi Oxb Timer haltinterrupt bit equ prot ptsr teri Oxc Timer error interrupt bit B 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc bits of the Timer Event Register TEVR old names bits of Motorola equ equ prot tevr act prot tevr txma 0x0 active table indicator bit prot tevr rxma 0x1 active Rx macro indicator bit Ox2 active Tx macro indicator bit MCU Equates prot tevr thip 0x3 timer halt in progress indicator bit prot ptevr act the Protocol Timer Event Register PTEVR NEW NAMES 0x0 active table indicator b
408. lacing a piece of ROM based code with a patch program stored in RAM There are four patch address registers PARO PAR3 at DSP I O addresses X FFF8 FFES Each PAR has an associated address comparator When an address of a fetched instruction is identical to the address stored in a PAR that instruction is replaced by a JMP instruction to the PAR s jump target address where the patch code resides The patch registers register addresses and jump targets are listed in Table 4 10 Table 4 10 Patch JUMP Targets Patch Register JUMP Register Address Target PARO X FFF8 0018 PAR1 X FFF7 0078 PAR2 X FFF6 0098 PAR3 X FFF5 00F8 For more information refer to the DSP56600 Family Manual DSP56600FM AD DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc I O Multiplexing 4 4 3 Device Identification Register The IDR is a 16 bit read only factory programmed register used to identify the different DSP56600 core based family members This information may be used in testing or by software IDR Device Identification Register X FFF9 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O Revision number Derivative number 652 RESET 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 4 5 O Multiplexing To accommodate all of the functions of the DSP56652 in a 196 pin package 28 of the pins multiplex two or more functions Eleven of t
409. le Semiconductor Inc MCU Instruction Reference Tables Table D 2 MCU Instruction Syntax Notation Symbol Description RX Source or destination register RO R15 RY Source or destination register RO R15 RZ Source or destination register RO R15 range may be restricted IMM5 5 bit immediate value OIMM5 5 bit immediate value offset incremented by 1 IMM7 7 bit immediate value LABEL R1 Register R1 DISP Displacement specified B Byte 8 bits H Half word 16 bits W Word 32 bits RF Register First any register from R1 to R14 RO and R15 are invalid R4 R7 The four registers R4 R7 CRY Source control register CRO CR31 Table D 3 MCU Instruction Opcode Notation Symbol Description rrrr RX field SSSS RY field ZZZZ RZ field ffff Rfirst field cccc Control register specifier iii i One of several immediate fields XX X Undefined fields D 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Instruction Reference Tables D 2 DSP Instruction Reference Tables Table D 4 provide a brief summary of the instruction set for the DSP core Table D 5 Table D 6 and Table D 7 list the abbreviations used in the instruction set summary table For complete DSP instruction set details see Appendix A of the DSP56600 Family Manual DSP56600FM AD Table D 4 DSP Instruction Set Summary
410. le command or setting the HLTR bit in PTCR DVIE DSP Vector Interrupt Enable Enables an MCU Bit 10 interrupt when a CVR command is executed DSIE DSP Interrupt Enable Enables a DSP IRQD Bit 9 interrupt to the DSP through the MDI when a dsp_int command is executed MCIE2 MCU Interrupt 2 Enable Enables an MCU interrupt Bit 6 when an mcu_int2 command is executed MCIE1 MCU Interrupt 1 Enable Enables an MCU interrupt Bit 5 when an mcu_inti command is executed MCIEO MCU Interrupt 0 Enable Enables an MCU interrupt Bit 4 when an mcu intO command is executed RSNIE Reference Slot Number Interrupt Enable Bit 2 enables an MCU interrupt when the RSC decrements to zero CFNIE Channel Frame Number Interrupt Enable Bit 1 Enables an MCU interrupt when the CFC decrements to zero CFIE Channel Frame Interrupt Enable Enables an Bit 0 MCU interrupt when the CTIC decrements to zero Motorola Protocol Timer 10 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers PTSR Protocol Timer Status Register 0020_3804 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 PCE MBUE EOFE THS DVI DSPI MCU2 MCU1 MCUO RSNI CFNI CF RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Each of these bits is cleared by writing it with 1 Writing zero to a bit has no effect Table 10 9 PTSR Description Name Description Setti
411. led 1 ATE Description MB 0 Address Trace disabled 1 Address Trace enabled Description Reflects state of DSP_IRQ at negation of RESET IN Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programmer 15 DSP Core 14 13 PARO Patch Register 0 Address X FFF8 Reset uuuu 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PARO PAR8 PAR7 PAR6 PARS PAR4 PAR3 PAR2 PAR1 PARO 15 14 13 PAR1 Patch Register 1 Address 2 X FFF7 Reset uuuu 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PARO PAR8 PAR7 PAR6 PARS PAR4 PARS PAR2 PAR1 PARO 15 14 13 PAR2 Patch Register 2 Address X FFF6 Reset uuuu 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PARO PAR8 PAR7 PAR6 PARS PAR4 PAR3 PAR2 PAR1 PARO 15 14 13 PAR3 Patch Register 3 Address X FFF5 Reset uuuu 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PARO PAR8 PAR7 PAR6 PAR
412. lled message protocols e MCU can trigger any DSP interrupt regular or non maskable by writing to the command vector control register e Each core can wake the other from low power modes The basic block diagram of the MDI module is shown in Figure 5 1 Shared Memory Address amp Data Buffers 1K Dual Access DSP RAM MCU Side DSP Side Control Control DSP X Data Bus eo 2 ea o E o o 2 o DSP Peripheral Bus Figure 5 1 MDI Block Diagram Motorola MCU DSP Interface 5 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Memory 5 1 MDI Memory The DSP56652 provides special memory areas for the MDI on both the MCU and DSP sides This section describes where these areas are mapped how access contention between the two areas is resolved and memory access timing Note There is no mechanism in MDI hardware to prevent either core from overwriting an area of shared memory written by the other core It is the responsibility of software to ensure data integrity in shared memory for each core 5 1 1 DSP Side Memory Mapping MDI shared RAM is mapped to the X data memory space of the DSP at the top of its internal X data RAM From the functional point of view of the DSP the shared memory is indistinguishable from regular X data RAM A parallel data path allows the MCU to write to shared memory without restricting or stalling DSP accesses in any way In case of si
413. lock Diagram is t AA os 9 12 Protocol Timer Block Diagram 0 0 10 2 Event Table Strueture etae p Cha CR pe Ed AC IS pecie pd AC 10 5 Frame Table Enty ueste E ER VERD 10 7 Macro Table Enty sieved ex ud eel oe x eC tae ef S D ete e 10 8 Delay Fable EOI dotada 10 9 UART Block Diagram aes ARA UE RA RR n 11 3 Smart Card Port Interface is eso p c REAPER FEN EXE 12 1 SCP Port Interface and Auto Power Down Logic 12 3 SCP Clocks and Datare eire uoce ed me tI AAA 12 5 SC AAA eae oq tee di ea acoge ad 12 8 AAA o rede t e vut d das oae ee eee 12 9 Keypad Port Block Diagram 22s due ARR ERE ARA 13 1 Glitch Suppressor Functional Diagram o oooooooommooo o 13 4 DAP Block DIJSEATI s ret a one als 14 2 BBP Block Diagram 2v RAR A RSEN UE 14 2 DSP56652 JTAG Block DiagraM oo ooooooccooconooom o 15 2 DSP56600 Core JTAG Block Diagram o oooooocoommcoom o o 15 3 TAP Controller State Machine oos oes ar YI wees 15 5 JTAG Instruction Register edu Ded ENTE DA M icu ADR 15 5 VEAG By pds sResisiet casos Eve REO EVE S HEREIN wer eS ns 15 10 EAGT RCP ISIE TA A SE NUS REdES 15 11 Short Message POMAR E ER RIOT E HET REA A 3 Long Message Format cuss sash s Re ad A EAS A 3 Format of memory_write request Message oo ooooommommoo A 5 Format of message_write response Message oo oooooomooo o o A 6 Format of memory read request Messag oooooooommoom o o A 7 Format of memory_read
414. long csOcr chip select 0 control register unsigned long cslcr chip select 0 control register unsigned long cs2cr chip select 0 control register unsigned long cs3cr chip select 0 control register unsigned long cs4cr chip select 0 control register unsigned long cs5cr chip select 0 control register unsigned long eimcr eim configuration register y endif kkkkkkkkkkkkkkkkkkkkk REDCAP Interrupt controller example usage struct redcap pic pic struct redcap pic REDCAP MCU PIC kkkkkkkkkkkkkkkkkkkkk Hifdef ASSEM define PIC ISR 0x00 define PIC NIER 0x04 define PIC FIER 0x08 define PIC NIPR 0x0C define PIC FIPR 0x10 Zdefine PIC ICR 0x14 else struct redcap pic volatile unsigned long isr interrupt source register unsigned long nier normal interrupt enable register unsigned long fier fast interrupt enable register volatile unsigned long nipr normal interrupt pending register volatile unsigned long fipr fast interrupt pending register unsigned long icr interrupt control register y endif B 24 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bit masks which apply to isr nier nipr fier and fipr define REDCAP INT URX 0x80000000 define REDCAP INT SMPD 0x40000000 define REDCAP INT UTX 0x20000000 define REDCAP INT PT2 0x10000000 defi
415. long reply message a Se ee Soe PO Motorola DSP56652 DSP Bootloader A 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 2 4 memory_read response memory read response is a long message from the DSP to the MCU in response to a memory read request message The format of this long message is shown in Figure A 6 Note that this long message is located in MDI shared memory at the location defined by the destination address field of the memory_read request message The entry following the memory write request opcode in MDI memory is the return code 0000 indicates success and 0001 indicates failure Failure can only result from the invalid value of 11b to the XYP field in the memory read request message If the return code indicates a failure the DSP does not write the remaining entries in the message The third entry in the memory read response message is the number of DSP words read The fourth entry contains two fields The upper two bits indicate the memory space accessed according to Table A 3 on page A 5 The lower ten bits indicate the location in MDI shared memory where the DSP has stored the read data In all cases the bootloader defines the destination address offset to point to the word following the source address Therefore dest address offset mdi offset 5 The last entry source address indicates the DSP program X or Y space address from which
416. lowing the destination address 1 e source_address_offset mdi_offset 4 However the protocol allows for the data to be located anywhere in the MDI shared memory space MDI Messaging Unit Registers 15 14 13 10 9 0 l MCU address DSP address MCU_MDI_BASE 2 offset MDI Shared Memory DSP_MDI_BASE offset memory_write request of DSP words to write XYP unused source address offset gt destination address MCU_MDI_BASE DSP_MDI_BASE 2 source_address_offset source_address_offset a o e Figure A 3 Format of memory write request Message Table A 3 XYP Field XYP DSP Memory Space 00 X 01 Y 10 P Motorola DSP56652 DSP Bootloader A 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mode A Normal MDI Boot A 2 2 2 memory_write response memory write response is a short message from the DSP to the MCU in response to a memory_write request message The format of this message is shown in Figure A 4 Note that the MDI RI register is not used A RET field of 0 indicates a successful memory_write request if the RET field is 1 the memory_write request failed Thus since memory_write response opcode is 1 the MCU should expect the DSP to respond to a successful memory write with MDI_RO 8001 MDI Messaging Unit Registers 13 15 14 8 7 0 Figure A 4 Format of message_write response Message MDI_RO
417. m Freescale Semiconductor Inc xxii DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Preface This section provides information on the data conventions used in this manual as well as a list of complete product documentation Conventions The following conventions are used in this manual Bits within registers are always listed from most significant bit MSB to least significant bit LSB 1 byte 8 bits 1 halfword 16 bits 2 bytes 1 word 32 bits 4 bytes Bits within a register are indicated AA n 0 when more than one bit is involved in a description For purposes of description the bits are presented as 1f they were contiguous within a register regardless of their actual physical locations in a register All bits in a register are read write unless otherwise noted When a bit is described as set its value is 1 When a bit is described as cleared its value is O Register bits that are unused or reserved for future use are read as O and should be written with O to ensure future compatibility In the register descriptions each of these bits is indicated with a shaded box Jj The word reset is used in three different contexts in this manual There is a reset instruction that is always written as RESET In lower case reset refers to the reset function A leading capital letter is used as gr
418. masked 1 INT3 interrupt source enabled EFINT2 Description 0 Interrupt source is masked 1 INT2 interrupt source enabled EFINT1 Description 0 Interrupt source is masked 1 INT1 interrupt source enabled EFINTO Description 0 Interrupt source is masked 1 INTO interrupt source enabled EFS2 Description 0 Interrupt source is masked 1 Software Interrupt 2 source enabled EFS1 Description 0 Interrupt source is masked 1 Software Interrupt 1 source enabled EFSO Description 0 Interrupt source is masked Software Interrupt 0 source enabled 15 44 13 dE TO 9 08 7 6 5 4 3 2 1 0 EFKPD EFURTS EFINT7 EFINT6 EFINTS EFINT4 EFINT3 EFINT2 EFINT1 EFINTO EFS2 EFS1 EFSO 0 o o NOTE FIER can only be written as a 32 bit Reserved E 30 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer MCU Interrupts Decii N P R 0 No interrupt pending 1 Protocol Timer MCUO interrupt Upper Halfword request pending
419. me is received Overrun Error An error condition in which the receive FIFO is full when another character is received The received character is ignored to prevent overwriting the existing data An overrun error indicates that the software reading the FIFO is not keeping up with character reception on the RxD line 11 2 UART Architecture This section provides a brief description of the UART transmitter receiver clock generator infrared interface pins and frame configuration A block diagram of the UART is presented in Figure 11 1 11 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Architecture Rx FIFO JJ 3 o and Shifter DCE MCU Interface Peripheral Bus ol 4 n Infrared TxD Tx FIFO Interface and Shifter RxD 16x Bit Clock INT7 DTR E 1 PS RI Clock Interrupt Control z l PAR Generator O e ca GPIO M DCD Data Lo 4d DSR Control Figure 11 1 UART Block Diagram 11 2 1 Transmitter The UART transmitter contains a 16 word FIFO UTX with one character byte per word Word aligned characters enable the MCU to perform block writes using the Store Multiple STM command The transmitter adds start stop and optional parity bits to each character to generate a transmit frame It then shifts the frame out serially on the UART transmission pin TxD
420. mer s Data Sheets For More Information On This Product Go to www freescale com E 71 Freescale Semiconductor Inc Application Date Programmer SCSR Description S C P 0 bit is cleared 1 Reset SIM o C P C H SCPT Description SCP Control Register 0 Even parity Address 0020 B000 Reset 0000 1 Odd parity Read Write SCIC Description SIBR Description 0 Parity determined by SIPT bit 0 Baud rate SIM CLK 372 1 Parity determined by smart card 1 Baud rate SIM CLK 64 NKPE Description 0 No NACK on parity error DOZE Description 1 NACK generated on parity error 0 SCP ignores DOZE mode 1 SCP halts in DOZE mode SCTE Description 0 Transmitter disabled NKOVR Description 1 Transmitter enabled 0 No NACK on overrun error 1 NACK generated on overrun error SCRE Description 0 Receiver disabled 1 Receiver enabled CLKSEL Description 0 SIM_CLK CKIH 5 1 SIM_CLK CKIH 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E 72 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programmer
421. mer s Data Sheets For More Information On This Product Go to www freescale com E 83 Freescale Semiconductor Inc Application Date Programmer BBP BBP Receive Counter Modulus Register 1 ees ead Receive Counter Modulus Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BBPTMR BBP Transmit Counter Modulus Register Address X FFA5 Reset 0000 Read Write Transmit Counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BBPCRA BBP Control Register A WL1 WLO Description Address X FFA6 0 8 bits per word Reset 0000 Read Write 1 12 bits per word 1 0 16 bits per word PSR Description 1 Reeds 0 No prescale 1 Prescale applied Frame Rate Divider Prescale Modulus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PM7 PM6 PM5 PM4 PM3 PM2 PMi PMO PSR WL1 WLO DC4 DC3 DC2 DCi DCO E 84 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
422. mes equ updr pd0 0x0 equ updr pdl 0x1 equ updr pd2 0x2 equ updr pd3 0x3 bits of the UART port data register UPDR NEW NAMES equ updr updo 0x0 equ updr updl 0x1 equ updr upd2 0x2 equ updr upd3 0x3 QSPI equates B 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Equates f QSPI BASE ADDRESS equ qspi base address 0x00205000 control ram split into 16 byte sections equ qspi control ram0 base address 0x00205000 equ qspi control raml base address 0x00205010 equ qspi control ram2 base address 0x00205020 equ qspi control ram3 base address 0x00205030 equ qspi control ram4 base address 0x00205040 equ qspi control ram5 base address 0x00205050 equ qspi control ram6 base address 0x00205060 equ qspi control ram7 base address 0x00205070 data ram split into 16 byte sections equ qspi data ram0 base address 0x00205400 equ qspi data raml base address 0x00205410 equ qspi data ram2 base address 0x00205420 equ qspi data ram3 base address 0x00205430 equ qspi data ram4 base address 0x00205440 equ qspi data ramb base address 0x00205450 equ qspi data ram6 base address 0x00205460 equ qspi data ram7 base address 0x00205470 control register base addresses equ qspi regs base address 0x00205 00 equ qspi spsr base address 0x00205 10 equ qspi trig base address 0x00205ff8 QSPI REGISTERS AD
423. mitter If TXEN is cleared during a 1 Transmitter enabled transmission the transmitter is immediately disabled and the TxD pin is pulled high The UTX cannot be written while TXEN is cleared RXFL 1 0 Receive FIFO Interrupt Trigger Level These 00 One FIFO slot default Bits 11 10 bits determine the number of received characters 01 Four FIFO slots in URX required to indicate to the MCU that the 10 Eight FIFO slots URX should be read When the number of 11 Fourteen FIFO slots registers containing received data rises above this threshold the RRDY bit in USR is set and a maskable interrupt can be generated RRDYIE Receiver Ready Interrupt Enable Setting this O Interrupt disabled default Bit 9 bit enables an interrupt when the number of 1 Interrupt enabled received characters in UTX reaches the threshold determined by RxFL 1 0 Note Either the EURX bit in the NIER or the EFURX bit in the FIER must also be set in order to generate this interrupt see page 7 7 Motorola UART 11 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Registers Table 11 6 UCR1 Description Continued Name Description Settings RXEN Receiver Enable Setting this bit enables the O Receiver disabled default Bit 8 UART transmitter 1 Receiver enabled Note The receiver requires a valid one to zero transition to accept a valid charac
424. ml ctimv_ P12 prot ctiml ctimv_ 13 prot cfc cfcv 0 prot cfc cfcv 1 prot cfc cfcv 2 prot cfc cfcv 3 prot cfc cfcv 4 prot cfc cfcv 5 prot cfc cfcv 6 prot cfc cfcv 7 prot cfc cfcv 8 prot cfpr cfpv 0 prot cfpr cfpv 1 prot cfpr cfpv 2 prot cfpr cfpv 3 prot cfpr cfpv 4 prot cfpr cfpv 5 prot cfpr cfpv 6 prot cfpr cfpv 7 prot cfpr cfpv 8 prot cfml cfnv 0 prot lt cfml cfnuv 1 Oxa CTIPR value bit CTIPR value bit CTIPR value bit CTIPR value bit CTIPR value bit CTIPR value bit CTIPR value bit CTIPR value bit CTIPR value bit Oxb CTIPR value bit Oxc CTIPR value bit Oxd CTIPR value bit 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 Oxa Oxb Oxc Oxd ctiml ctiml ctiml ctiml ctiml ctiml ctiml ctiml ctiml ctiml ctiml value bit 0 value bit value bit value bit value bit value bit value bit value bit value bit value bit value bit ctiml value bit ctiml value bit ctiml value bit CFC 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x0 0x1 CFC value bit CFC value bit CFC value bit CFC value bit CFC value bit CFC value bit CFC value bit CFC value bit CFC value bit 0 0d UH CO PO ILS CO CFPR value bit CFPR value bit CFPR value bit CFPR value bit CFPR value bit CFPR value bit CFPR value bi
425. mmer EXR Description 0 The last reset was not caused by M C U Co re an external reset assertion of RESET IN pin 1 The last reset was caused by RESET IN assertion H S R WDR Description Reset Source Register 0 The last reset was not caused by Address 0020_C400 Watchdog timer expiration Reset value depends on cause of reset 1 The last reset was caused by Read Only Watchdog timer expiration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCD 0 2 Description C KCT L 000 MCU clock division factor 1 Clock Control Register 001 MCU clock division factor 2 oe MP M 010 MCU clock division factor 4 Read Write 011 MCU clock division factor 8 100 MCU clock division factor 16 CKOS Description 101 111 Reserved 0 MCU clock driven on CKO pin 1 DSP clock driven on CKO pin MCS Description 0 CKIL selected at multiplexer output CKOD Description 1 CKIH selected at multiplexer output 0 CKO pin enabled 1 CKO pin disabled CKIHD Description 0 CKIH input buffer enabled CKOHD Description 1 CKIH input buffer disabled when 0 CKOH output buffer enabled MCS bit cleared 1 CKOH output buffer disabled DCS Description 0 CKIH provided to DSP core 1 CKIL provided to DSP core 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCS CKOHD CKOD CKOS MCD2 MCD1 Reserved
426. multaneous access from both the MCU and the DSP to the same memory space the DSP access has precedence The DSP programmer must be aware however that data written to that area can be changed by the MCU The MDI message control and status registers are mapped to DSP X I O memory as a regular peripheral accessible via special I O instructions DSP X Data Memory X FFFF X 1 0 Memory X FF80 a MDI DSP Base Address X F So MDI Control TE Registers _ MDI DSP Base Address X 2000 MDI Shared Memory X 1C00 X 0000 Figure 5 2 MDI DSP Side Memory Mapping 5 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Memory 5 1 2 MCU Side Memory Mapping The MCU allocates a 4 kbyte peripheral space to the MDI as shown in Figure 5 3 Control and status registers are mapped to the upper 16 words of this space and shared memory is mapped to the lower 2 kbytes FFFF_FFFF r 0020 2FFF MDI Control us Registers 0020 2FF0 Reserved 54 0020 27FF 0040 0000 gt f MDI Shared Memory Peripherals 2M 0020 2000 0020 0000 0000 0000 Figure 5 3 MDI MCU Side Memory Mapping Note Writes to reserved locations are ignored Reads from reserved locations latch indeterminate data Neither access terminates in an access error The offset conversion formula between the MDI internal
427. n Setting the CONT bit keeps the current chip select line active Clearing the CONT bit deasserts the current chip select line and stops the current transfer If the CONT bit is set and the chip selection in the next queue entry is different than that of the present one the chip select line remains active between queue entry transfers and is deactivated two MCU_CLK cycles before the new chip select line for the next queue entry is activated If both the CONT bit and the PAUSE bit in the queue entry s control halfword are set or if EOQ is detected in the next control halfword the chip select line also continues to be activated after the sub queue queue transfer has been completed 8 3 5 Halting the QSPI When the MCU wants to soft disable the QSPI at a queue boundary it asserts the HALT bit in SPCR If the QSPI is in the process of transferring a queue it suspends the transfer at the next sub queue or queue boundary depending on the queue s HMD bit It then asserts the HALTA bit in the SPSR and QSPI operation stops If the HLTIE bit in the SPCR is set asserting HALTA generates an interrupt to the MCU The QSPI state machines and the QSPI registers are not reset during the HALT process and the QSPI resumes operation where it left off when the MCU deasserts HALTA During the HALT mode the QSPI continues to accept new transfer triggers from the protocol timer and MCU and the MCU can access any of the QSPI registers and RAM addresses
428. n Description Language MOTOROLA Revision History entity DSP56652 is C 4 port SSDT TRST B TCK TMS TDI generic PHYSICAL PIN MAP BEBES For More Information On This Product JTAG BSDL File Generated Sun Feb 23 11 09 20 1997 string bit bit bit bit SOFTWARE PBGA196 DSP56652 User s Manual Go to www freescale com Motorola TDO ADDR DATA RW B EB B OE B INT DSP IRQ B CS B CKIH CKIL CKO CKOH BMODE RESET OUT B RESET IN B STO MUX CTL PCAP PVCC PGND P1GND SIZ PSTAT MCU DE B DSP DE B TEST COLUMN ROW inout bit RX RTS B CTS B TOUT STDA SRDA SCKA SCA STDB SRDB SCKB SCB MOSI MISO SCK SPICS SIMCLK SENSE SIMDATA SIMRESET B PWR EN AVDD CVDD CGND DVDD Motorola Freescale Semiconductor Inc out inout inout inout inout buffer inout in buffer linkage in buffer buffer in buffer in buffer linkage linkage linkage linkage linkage inout inout linkage inout linkage inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout linkage linkage linkage linkage linkage bit bit vector 0 bit vector 0 bit bit vector 0 bit bit vector 0 bit bit vector 0 bit bit bit bit bit bit bit bit bit bit bit bit bit bit vector 0
429. n be used for example to keep track of slot timing in an adjacent cell If the RSNIE bit in the PTIER is set when the RSC decrements to zero a Reference Slot Number Interrupt RSNI is generated The RSC rolls over to a modulo value contained in the Reference Slot Modulus Register RSMR 10 1 2 Event Table The event table is an 80 word dual port RAM starting at the base of the protocol timer peripheral space 0020 3000 Each entry contains a 14 bit field and a 7 bit field all fields are halfword aligned The event table can be dynamically partitioned into two frame tables two macro tables and two delay tables by initializing the base address registers FTBAR MTBAR and DTPTR respectively A frame table a receive macro and a transmit macro can all be active simultaneously Figure 10 2 shows the structure of the event table Note The base address and pointer registers contain entry numbers The actual address in MCU memory is equal to 0020 3000 plus 4 times the entry number The MCU can read and write the event table whether or not the PT is enabled PT control logic has read only access to the event table Arbitration logic ensures that the event table is accessed correctly adding wait states to MCU cycles when necessary 10 1 3 Event Generation The components involved in generating events in the PT include a Frame Table Event Comparator two Macro Timing Control Units an Event Control Unit and an Interrupt Generator 10 4 DSP
430. n interrupt sources to a normal interrupt e NIPR The Normal Interrupt Pending Register reflects the current state of all pending non masked normal interrupt requests e FIER The Fast Interrupt Enable Register provides a centralized place to enable disable interrupt requests and to assign interrupt sources to a fast interrupt e FIPR The Fast Interrupt Pending register reflects the current state of all pending non masked fast interrupt requests e ICR The Interrupt Control Register selects the highest priority interrupt and its vector Figure 7 1 is a block diagram of the MCU interrupt controller ISR FIER FIPR Interrupts From e Fast Peripherals Interrupt to Core Vector Number Autovector Low Power Wake up Priority Circuit Interrupt to Core NIER NIPR Figure 7 1 MCU Interrupt Controller 7 1 2 Exception Priority The MCU core imposes the following priority from highest to lowest among the various exceptions e Hardware Reset 7 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Reset Hardware Breakpoint Fast Interrupt Normal Interrupt Instruction Generated Exceptions Trace MCU Interrupt Controller The interrupt controller registers prioritize the peripheral interrupts by designating each request as either an autovectored normal inte
431. nal pullup resistor TMS Test Mode Select An input that is used to sequence the test controller s state machine TMS is sampled on the rising edge of TCK and includes an internal pullup resistor TDI Test Data Input Serial test instruction and data are received through the Test Data Input TDI pin TDI is sampled on the rising edge of TCK and includes an internal pullup resistor TDO Test Data Output The serial output for test instructions and data TDO is three stateable and is actively driven in the Shift IR and Shift DR controller states TDO changes on the falling edge of TCK TRST Test Reset An input that is used to asynchronously initialize the test controller and select the JTAG compliant mode of operation The TRST pin has an internal pullup resistor DSP_DE Test Data Output A bidirectional pin used as an input to asynchronously initialize the test controller 15 1 2 DSP TAP Controller The DSP TAP controller is responsible for interpreting the sequence of logical values on the TMS signal It is a synchronous state machine that controls the operation of the JTAG logic A diagram of the TAP controller state machine is shown in Figure 15 3 The value shown adjacent to each arc represents the value of the TMS signal sampled on the rising edge of TCK signal For a description of the TAP controller states refer to the JEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture 15 4 DSP56652 User s Manual
432. nd DSP from Debug Modes Step TMS JTAG State OnCE Note a 1 Test Logic Reset Idle b 0 Run Test Idle Idle C 1 Select DR Scan Idle d 1 Select IR Scan Idle e 0 Capture IR Idle Capture DSP core status bits f 0 Shift IR Idle The 4 bits of the JTAG g 0 Shift IR Idle ENABLE_DSP_ONCE instruction l 0b0110 are shifted into the combined h 0 Shift IR Idle DSP MCU instruction register i 0 Shift IR Idle j 0 Shift IR Idle The remaining 8 bits of the MCU OnCE k 0 Shift IR Idle instruction read no register selected go exit 0b11101100 are shifted into O Shift IR Idle the combined DSP MCU IR m 0 Shift IR Idle n 0 Shift IR Idle o 0 Shift IR Idle p 0 Shift IR Idle q 0 Shift IR Idle r 1 Exit1 IR Idle At this point both IR sections are ready to be loaded the MCU with read no register selected go exit the DSP with Enable DSP OnCE S 1 Update IR Idle OnCE is enabled for the DSP already enabled for the MCU t 1 Select DR Scan Idle u 0 Capture DR Idle V 0 Shift DR Idle The 8 bits of the DSP OnCE command read no register selected go exit E 0b11111111 are shifted in V 0 Shift DR Idle w 0 Shift DR Idle A single bit of bypass data corresponding to the MCU portion of the combined DR is shifted in x 1 Exit1 DR Idle y 1 Update DR Idle Following this update both OnCE control blocks release their respecti
433. nderflow error occurs RLIE Receive Last Slot Interrupt Enable In network O Interrupt disabled default Bit 13 mode setting this bit enables an interrupt at the 1 Interrupt enabled end of the last receive time slot in a frame RLIE has no effect in other modes TLIE Transmit Last Slot Interrupt Enable In O Interrupt disabled default Bit 12 network mode setting this bit enables an interrupt 1 Interrupt enabled at the beginning of the last transmit time slot in a frame TLIE has no effect in other modes RIE Receive Interrupt Enable Setting this bit O Interrupt disabled default Bit 11 enables an interrupt when the receive register 1 Interrupt enabled receives the last bit of a word and transfers the contents to the Receive Register TIE Transmit Interrupt Enable Setting this bit O Interrupt disabled default Bit 10 enables an interrupt when the contents of the 1 Interrupt enabled Transmit Register are transferred to the transmit shift register RE Receive Enable Enables the SAP or BBP O Receiver disabled default Bit 9 receiver by allowing data transfer from the 1 Receiver enabled receive shift register to the Receive Register Motorola Serial Audio and Baseband Ports 14 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers Table 14 8 SAP BBP CRB Description Name Description Settin
434. nding interrupt requests It scans the contents of a register and reports the position of the most significant set bit Highest priority status Any interrupt can be configured as the highest priority in which case it is assigned a vectored interrupt Directly vectored interrupts can be serviced with fewer instructions than autovectored interrupts because polling to determine the interrupt s source is not required For more information refer to the M CORE Reference Manual Alternate register set The MCU provides an alternate register set for interrupts including general registers status register and program counter eliminating the need to save program context to the stack e Fast interrupts Critical interrupts can be processed using separate dedicated program counter and status shadow registers not used by the other interrupts Any source can be programmed to generate a normal or fast interrupt Individual enable bits Each interrupt source is individually configured 7 1 1 Functional Overview The MCU interrupt controller is comprised of six registers Motorola Interrupts 7 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Interrupt Controller e ISR The Interrupt Source Register reflects the current state of all interrupt sources within the chip e NIER The Normal Interrupt Enable Register provides a centralized place to enable disable interrupt requests and to assig
435. nductor Inc E 92 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com
436. ne REDCAP INT PT1 0x08000000 define REDCAP INT PTO 0x04000000 define REDCAP INT PIM 0x02000000 define REDCAP INT QSPI 0x01000000 define REDCAP INT MDI 0x00800000 define REDCAP INT SIM 0x00400000 define REDCAP INT TPW 0x00020000 define REDCAP INT PIT 0x00010000 define REDCAP INT KPD 0x00004000 define REDCAP INT URTS 0x00002000 define REDCAP INT INT7 0x00001000 define REDCAP INT INT6 0x00000800 define REDCAP INT INT5 0x00000400 define REDCAP INT INT4 0x00000200 define REDCAP INT INT3 0x00000100 define REDCAP INT INT2 0x00000080 define REDCAP INT INT1 0x00000040 define REDCAP INT INTO 0x00000020 define REDCAP INT S2 0x00000004 define REDCAP INT S1 0x00000002 define REDCAP INT SO 0x00000001 icr manipulation define REDCAP ICR ENABLE 0x00008000 define REDCAP ICR MAKE SRC x x amp 0xlf 7 define REDCAP ICR MAKE VECTOR x x amp 0x7f define REDCAP ICR GET SRC x x gt gt 7 80x1 define REDCAP ICR GET VECTOR x x amp 0x7 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk REDCAP MCU DSP Interface example usage unsigned short mdi shared unsigned short MDI SHARED BASE MCU Include File struct redcap mdi regs mdi regs struct redcap mdi regs MDI 1 REG BASE Kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Shared memory define MDI SHARED BASE REDCAP MCU MDI 0x000 Registers are at the end of the 1K space define MDI
437. ne to determine which key is pressed Care should be taken to enable the open drain drivers before driving the columns high to avoid shorting power to ground through two or more switches 13 1 4 Noise Suppression on Keypad Inputs The noise suppression circuit illustrated in Figure 13 2 qualifies keypad closure signals to prevent false keypad interrupts The circuit is a four state synchronizer driven by CKIL A KP interrupt is not generated until all four synchronizer stages have latched a valid key assertion effectively filtering out any noise less than four clock cycles in duration The interrupt signal is an S R latch output that remains asserted until cleared by software Once cleared the interrupt and its reflection in the KPSR cannot be set again until a period of no key closure is detected In this way the hardware prevents multiple interrupts for the same key press with no software intervention Because the keypad interrupt signal is driven by the noise suppression circuit CKIL must remain powered in low power modes for which the keypad is a wake up source Motorola Keypad Port 13 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Keypad Port Registers To Interrupt Controller Clear Status Flag Figure 13 2 Glitch Suppressor Functional Diagram 13 2 Keypad Port Registers Table 13 2 is a summary of the KP control and GPIO registers including the acronym bit names and addr
438. nformation On This Product Go to www freescale com Freescale Semiconductor Inc MCU Internal I O Memory Map Table D 8 MCU Internal I O Memory Map Continued Address Register Name Reset Value Smart Card Port SCP 0020_B000 SCPCR SCP Control Register 0000 0020_B002 SCACR Smart Card Activation Control Register 0000 0020_B004 SCPIER SCP Interrupt Enable Register 0000 0020_B006 SCPSR SCP Status Register 00Cu 0020_B008 SCPDR SCP Data Register 0000 0020_BO0A SCPPCR SCP Port Control Register 000u MCU Core 0020_C000 CKCTL Clock Control Register 0000 0020_C400 RSR Reset Source Register Emulation Port 0020_C800 EMDDR Emulation Port Control Register 0000 0020_C802 EMDR Emulation Port Data Register 00uu O Multiplexing 0020 CCOO GPCR General Port Control Register 0000 1 These registers are 32 bits wide 2 These 16 bit registers are mapped on 32 bit boundaries to support the LDM instruction 3 These 16 bit registers are mapped on 32 bit boundaries to support the STM instruction D 18 For More Information On This Product DSP56652 User s Manual Go to www freescale com Motorola Freescale Semiconductor Inc DSP Internal I O Memory Map D 4 DSP Internal I O Memory Map Table D 9 lists the DSP I O registers in address numerical order Table D 9 DSP Internal l O Memory Map Address Register Name Reset Value
439. ng ASPE enables QSPI operation The QSPI begins monitoring transfer triggers from the Protocol Timer and the MCU Both the QSPI and the MCU have access to the QSPI RAM Clearing QSPE disables the QSPI All QSPI state machines and the status bits in the SPSR are reset other registers are not affected The MCU can use the QSPI RAM and access its registers and all the QSPI pins revert to GPIO configuration regardless of the value of the QPCR bits To avoid losing an ongoing data transfer and disrupting an external device issue a HALT request and wait for HALTA before clearing QSPE Pending transfer triggers will still be lost 0 QSPI disabled QSPI pins are GPIO default 1 QSPI enabled 8 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory QCRO Queue Control Register 0 0020_5F08 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O LEO HMDO QPO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QCR1 Queue Control Register 1 0020 5F0A BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O LE1 HMD1 TRCNT1 QP1 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QCR2 Queue Control Register 2 0020_5FOC BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O LE2 HMD2 QP2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QCR3 Queue Control Register 3 0020 5FOE BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BI
440. ngs PCE Pin Contention Error Set when two events O PCE has not occurred default Bit 14 attempt to drive opposite values to a PT pin 1 PCE has occurred simultaneously MBUE Macro Being Used Error Set when a frame O MBUE has not occurred default Bit 13 table command calls a macro that is already 1 MBUE has occurred active EOFE End of Frame Error Set when CFE occurs 0 EOFE has not occurred default Bit 12 before an end_of_frame command 1 EOFE has occurred THS Timer Halt State Indicates if the PT is in halt 0 Normal mode default Bit 11 state Operation resumes from the beginning of 1 Halt mode frame table O when THS is cleared DVI DSP Vector Interrupt Set by a CVR event O DVI has not occurred default Bit 10 1 DVI has occurred DSPI DSP Interrupt Set by a dsp_int event 0 DSPI has not occurred default Bit 9 1 DSPI has occurred MCUI2 MCU2 Interrupt Set by an mcu int2 event 0 MCUI2 has not occurred default Bit 6 1 MCUI2 has occurred MCUI1 MCU1 Interrupt Set by an mcu int1 event 0 MCUI1 has not occurred default Bit 5 1 MCUI1 has occurred MCUIO MCUO Interrupt Set by an mcu intO event 0 MCUIO has not occurred default Bit 4 1 MCUIO has occurred RSNI Reference Slot Number Interrupt Set when O RSNI has not occurred default Bit 2 the RSC decrements to zero 1 RSNI has occurred CFNI Channel Frame Number Inter
441. nning Running Programmable Stopped can trigger wake up External interrupt Running Running Running Stopped can trigger wake up Table 4 6 DSP Peripherals in Low Power Modes Peripheral Normal WAIT STOP MDI DSP side Running Running Stopped can trigger wake up BBP Running Running Stopped SAP Running Running Stopped 4 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Reset For further power conservation any running peripheral in a given mode as well as the features summarized in Table 4 7 can be explicitly disabled by software Table 4 7 Programmable Power Saving Features Description Register Reference Disable CKOH CKCTL bit 7 Table 4 2 Disable CKO bit 6 Disable CKIH buffer bit O Disable DSP_CLK PCTL1 bit 7 Table 4 4 Disable PLL bit 6 Disable PLL in STOP mode bit 5 4 3 Reset Four events can cause a DSP56652 reset 1 Power on reset 2 RESET_IN pin is asserted 3 Bottom connector RTS pin acting as RESET_IN is asserted 4 Watchdog timer times out Reset from power on or the watchdog timer time out is immediately qualified An input circuit qualifies the RESET_IN signal from either pin based on the duration of the signal in CKIL clock cycles e 2cycles not qualified e 3cycles may or may not be qualified 4cycles qualified A qualified reset signal asserts the RESET OU
442. nterrupt request pending FSMPD Description 0 No interrupt pending FTPW Description 1 SIM Auto Power Down interrupt 0 No interrupt pending request pending 7 1 General Purpose Timer PWM interrupt request pending FURX Description 0 No interrupt pending FPIT Description 1 UART Receiver Reagy interrupt request pending 0 No interrupt pending 1 Periodic Interrupt Timer interrupt request pending 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FURX FSMPD FUTX FPT2 FPT1 FPTO FPTM FQSPI FMDI FSCP FTPW FPIT 0 0 0 0 NOTE FIPR can only be written as a 32 bit Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 33 Freescale Semiconductor Inc Application Date Programmer M C U nte rru pts FINT4 Description Fl P R y 0 No interrupt pending 1 INT4 interrupt request pendin Lower Halfword lt Md Fast Interrupt Pending Register m Lower Halfword FINT3 Description Address 0020_0012 0 No interrupt pending Reset 0000 1 INT3 interrupt request pending Read Write FINT2 Description FINTS Description 0 No interrupt pend
443. nterrupts enabled IPL 2 MCU Default Command IPL PL1 PLO Mode 0 0 Interrupts disabled MDI IPL 0 1 Interrupts enabled IPL 0 PL1 PLO Mode 1 0 Interrupts enabled IPL 1 0 Interrupts disabled 1 1 Interrupts enabled IPL 2 1 Interrupts enabled IPL 0 1 0 Interrupts enabled IPL 1 1 1 Interrupts enabled IPL 2 15 14 13 12 11 10 9 g 7 E 4 ll 2 1 0 MDIPL1 MDIPLO PTPL1 BBPPLO MDCPL1 MDCPLO Reserved E 36 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer ATM IAPL1 IAPLO IRQ A Mode Trigger Mode 0 0 0 IRQ A disabled no IPL Level sensitive DSP Interru pts 0 0 1 IRQ A enabled IPL 0 Level sensitive 0 1 0 IRQ A enabled IPL 1 Level sensitive P R 0 1 1 IRQ A enabled IPL 2 Level sensitive C 1 0 0 IRQ A disabled no IPL Edge sensitive Interrupt Priority Register Core 1 0 1 IRQ A enabled IPL 0 Edge sensitive Address X FFFF 1 1 0 IRQ A enabled IPL 1 Edge sensitive Reset 0000 1 1 1 IRQ A enabled IPL 2 Edge sensitive Read Write IBTM IBPL1 IBPLO IRQ B Mode Trigger Mode 0 0 0 IRQ B disabled no IPL Level sensitive 0 1 IRQ B enabled IPL 0 Level sensitive 0 1
444. ntrol Registers 3 0 contains the queue pointer for its associated queue enables use of the last data entry in the queue as the start address of the next queue and determines if the queue responds to a HALT at the next sub queue boundary or queue command QCR1 also contains a counter for a trigger accumulator e SCCR4 0 Each of Serial Channel Control Registers 4 0 controls the serial clock frequency phase and polarity for its associated channel the delay between chip select assertion and the serial clock activation the delay between chip select deassertion and the start of the next transfer and the order of data transmission least significant bit first or last These registers determine the GPIO functions of the QSPI pins e QPCR The QSPI Port Configuration Register configures each of the eight pins as either QSPI or GPIO e ODDR The QSPI Data Direction Register determines if each pin that is configured as GPIO is an input or an output e QPDR The QSPI Port Data Register contains the data that is latched on each GPI pin and written to each GPO pin 8 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Architecture 8 2 3 Functional Modules The QSPI functional modules include the following The chip select module uses data from a queue s control RAM entry to select the appropriate SPICS pin and Serial Channel Control Register SCCR f
445. o www freescale com MDI Registers Freescale Semiconductor Inc Table 5 12 MSR Description Continued Name Type Description Settings DWS R 1S DSP Wake From STOP Set by MCU software O No outstanding DWS generated Bit 8 to wake the DSP from STOP mode Setting interrupt request default DWS also asserts DSP IRQC waking the DSP 1 DSP has not serviced last from STOP mode and IRQA which is wire or d DWS generated interrupt to IRQC DWS is cleared when the DSP sets the DWSC bit in the DSR Table 5 18 on page 5 25 at the end of its IRQC service routine IRQC should be enabled via the ICPL bit in the IPRC and made level sensitive by clearing the ICTM bit in the IPRC Software should verify that DWS is cleared before issuing an MDI reset DRS R DSP Reset State Set by any DSP reset O DSP has completed the most recent Bit 7 MCU system reset reset sequence DSP hardware reset caused by setting the 1 2 DSP has not completed the most DHR bit in the MCR recent reset sequence default MDI reset caused by setting the MDIR bit in the MCR DRS is cleared by DSP hardware as it completes the reset sequence Software should ensure that DRS is cleared before accessing MDI shared memory MSMP R MCU Shared Memory Access Pending Set O No outstanding MCU MDI write Bit 6 by an MCU write to MDI shared memory default Cleared when write access is complete 1 Last MCU writ
446. o access the shared memory while the loop is running will be stalled until the loop terminates Example 5 1 Program Loop That Stalls MCU Access to Shared Memory move X r0 a move x r0 b DO N 2 1 _BE NASTY TO MCU move x r0 a a y r4 r0 points to MDI memory move x r0 b b y r4 r4 points to other memory BE NASTY TO MCU move a y r4 move b y r4 To avoid a lengthy MCU stall the DO loop above can be written to allow two cycles per move making time slots available for MCU accesses as illustrated in Example 5 2 Example 5 2 Program Loop With No Stall DO N IM OK MCU OK move x r0 x0 r0 points to MDI memory move x0 y r4 r4 points to other memory _IM OK MCU OK The second instruction in the loop allows pending MCU accesses to execute 5 1 4 Shared Memory Timing The DSP always has priority over the MCU when accessing the shared memory Every DSP access to MDI shared memory or control register lasts one cycle and is executed as part of the DSP pipeline without stalling it In general an MCU peripheral access is two clock cycles excluding instruction fetch time MCU accesses to MDI control registers are always two clock cycles but shared memory accesses usually take longer according to the following parameters Clock source of the shared memory If the DSP is in STOP mode the shared memory will operate using the MCU clocks generated at half frequency If the DSP 5 4 DSP56652 User s
447. og Timer Repito ca v RARE PER UT TUA PATE EU EA ARR 9 6 GP Timer and PWM x veia eei were ee GEI eT APR he a pe E qs 9 6 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com 9 3 1 GP TIMER A A Be EGON EES BE RES eh Bee ANTAS 9 3 2 Pulse Width Modulator d uo id ta 9 3 3 GP Timer and PWM Registers 5 Sov ce y aa Chapter 10 Protocol Timer 10 1 Protocol Timer Architecture lt lt 44 453 283 3 REESE PERI EDEN 10 1 Timing Signals and Components lees 10 12 Event Table coord NANA DS 10 1 3 Event Generation usce wet a taa Net cav lundi 10 2 PT Operation 4959 ro Ge veux LS AE wc sea SR WR rect PR 10 2 1 Fiame Events aac AA e ax ed o true Une nd o e bt ue ala 102 2 Macro Tables e ecd t os 28 10 2 5 Operating Modest Ng oe ec ieu eure 10 24 ror Detection s E HERE EVES DEIN ES LEE SEEN IRR IV ds 100 5 Interrupts 0 vC vedsvReb beet SN Ri IR REN EIE RI Ds 10 2 6 General Purpose Input Output GPIO o o o oooooocoomommo 10 3 PLE odessS sod atus seiten a 104 PI Resiste e ibas ala ced SoS MAT PT Control Register os oyu DI A ES 104 GPIOIRGsISiels pon ES E fe CAG EE Pee Wore wes 10 5 Protocol Timer Programming Example 0000s Chapter 11 UART TEL UART Derinitions it E x ex xaX A ada 112 UART Arehitecture IEA IA AI EE ER RE Eae 11 2 1 AI TT 11022 ARONA A REA AR 11 2 3 lock Generator rario AA RARA A LUA LInfrdred Interface ad coh i Sots e A apo e
448. ol Timer issues a transfer trigger The targeted queue becomes active The QSPI asserts QAn in the SPSR The MCU has previously enabled operation for this queue by setting its enable bit QEn in the SPCR If no higher priority queue is transferring data the targeted queue begins executing The QSPI asserts QXn in the SPSR The QSPI uses the queue pointer QPn in QCRz to determine the offset of the queue s entry in RAM The QSPI reads the datum and command halfword of the queue entry from RAM and writes the datum to the transmit buffer The datum is latched into the shift out register The QSPI selects the peripheral chip select line from the PCS field in the control halfword and asserts it The shift out register uses SCK to shift its contents out to the peripheral through the MOSI pin Received datum is also clocked in to the shift in register if the RE bit in the queue entry s control halfword is set 10 As transfer begins QPn is incremented the next datum and control halfword are read from RAM and the datum is latched in the transmit out buffer 11 All 8 or 16 bits in the queue entry are transmitted When the last bit is transferred the next datum in the transmit buffer is immediately latched into the shift out register and received datum if any is immediately latched to the receive buffer so that there is no delay between transfers Steps 7 11 repeat until the cycle is ended or broken by a
449. on 0 Transmitter disabled Transmitter enabled REIE Description 0 Disable interrupt TCE Description 1 Enable interrupt for receive error i 0 Timer disabled 1 Enable SAP timer Serial Output Flags Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 79 Freescale Semiconductor Inc Application Date Programmer SA P CKP Description 0 Transmit bit clock rising edge SA P C R Receive bit clock falling edge default SAP Control Register C 1 Transmit bit clock falling edge Address X FFB8 Receive bit clock rising edge Reset 0000 VIRA SCKD Description SHFD Description 0 External clock source 0 Data shifted out MSB first 1 Ingmele OR SOME 1 Data shifted out LSB first SCD2 Description BRM Description 0 SCD2 pin is input 0 SAP clock source is DSP CLK 1 SORE pints epar 1 SAP clock source is BRM_CLK a SCD1 Description FSL1 FSLO Description o SCD1 pin is input 0 O WL bitclock for both TX SD pin iS output and RX 0 1 1 bit clock for TX SCDO Description WL bit clock for RX 0 SCDO pin is input 1 0 1 bit clock for both TX and RX 1 SCDO pin is
450. onoces RR ores eee ct een ee S 5 6 Message Protocols oua uua rau Stel euet de ad a D Greta ds 5 9 MIDI IntermuptSOurcesin cts ina 5 10 Event Update Timings seso sees ier cenere ERE As 5 11 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 2 5 MCU DSP Troubleshooting 0 eee eee een eee 5 11 D9 Low Power Mod s i less s ict oO us al trio Mss eth Sick tal tra lee 5 11 S SM MCU Low Power Modest id EE Ud 5 12 3 9 2 DSP Low Power Modes 52 435 45 244 045 RR ER ls EFE e 5 12 5 3 3 Shared Memory in DSP STOP Mode 0 0 2 ee ee eens 5 13 Sar Resetting the MDI io A EA 5 14 5 5 MDI Software Restriction Summary 0 00 cee eee eee eee 5 15 S nNIDDRSSISIBESS S su sare wilds a ee oa ned ape eG ns AM LEA oe ip Mal 5 17 5 6 1 NICU SIde Registers e US RR E pA EA a ied DNE AE 5 18 5 6 2 DSP Side Reglsters 20 5457 sate ur ERRARE ERR a D 5 25 Chapter 6 External Interface Module 6d EIM Signals vs e yo ERES RIEN NM pd awe t 6 3 6 2 Chip Select Address Ranges c eos E ES EE EE ERES EN 6 4 G3 EIM Feat res A Su Lohr A ebd a pedis 6 4 6 3 1 Contigurable Bus SIZE sues AAA 6 4 6 3 2 External Boot ROM Control ie S etu e Pelee d HEN Ree ui 6 5 6 3 3 Bus Watchdog Operation somier es 6 5 6 3 4 Error Conditions A A E PES a E EE BEES 6 7 6 3 5 Displaying the Internal Bus Show Cycles o ooooooooooo ooo 6 7 6 3
451. ons that specify the OMR as a destination such as the MOVEC instruction 4 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Configuration OMR Operating Mode Register BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO ATE SEN WR EOV EUN XYS SD PCD EBD MB MA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 4 9 OMR Description Name Description Settings ATE Address Trace Enable Used in debugging for O Disabled default normal operation Bit 15 internal activity that can be traced via a logic 1 Enabled External bus reflects DSP analyzer internal program address bus SEN Stack Extension Enable 0 Disabled default Bit 12 1 Enabled WR Extended Stack Wrap Flag The DSP sets this bit O No copy required default Bit 11 when it recognizes that the stack extension memory 1 Copy of on chip hardware stack to stack requires a copy of the on chip hardware stack This extension memory is required flag is useful in debugging to determine if the speed of software implemented algorithms must be increased Once this bit is set it can only be cleared by reset or a MOVE operation to the OMR EOV Extended Stack Overflow Flag This flag is set 0 No overflow has occurred default Bit 10 when a stack overflow occurs in the Stack Extended 1 Stack overflow in stack exten
452. or 32 mode 110 Timer prescaler factor 64 1 PWM counter runs during Debug P mode 111 Timer prescaler factor 128 15 14 13 12 11 10 9 8 7 6 5 4 3 E 2 1 0 Reserved E 52 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer PW M FO1 Description Writing a 1 to this bit forces the TPWM R Output Compare 1 function Timers and PWM Mode Register Address 0020_6002 Reset 0000 IM2 0 1 Description Read Writ eae 00 Capture disabled 01 Capture on rising edge only FO3 Description 10 Capture on falling edge only 11 Capture on any edge Not pinned out R iis D ipti EO4 bids da IM1 0 1 Description Not pinned out 00 Capture disabled 01 Capture on rising edge only 10 Capture on falling edge only PWP Description 11 Capture on any edge 0 PWM pin active high L 3 1 PWM pin active low OM1 0 1 Description PWC Description 00 Timer disconnected from pin 0 PWM disconnected from PWM pin 01 Toggle output pin 1 PWM connected to PWM pin 10 Clear output pin 11 Set output pin Reserved Motorola Programmer s Data Sheets E 53 For More
453. or the serial transfer of the queue entry The serial clock generator derives the serial clock SCK from the system clock based on information in the active SCCR The shift in register uses SCK to shift in received data bits at the MISO pin and assembles the bits into a received data halfword or byte When the last bit is received the data is immediately latched in the receive buffer so that the shift in register can receive the next data with no delay If receive is enabled the receive buffer latches each received byte or halfword from the shift in register and writes it to the QSPI Data RAM at the address contained in the queue pointer in the queue s QCR The shift out register uses SCK to shift out transmitted data bits at the MOSI pin It loads the next data from the transmit buffer to be transferred immediately after the last bit of the current datum is sent enabling smooth transmission with no delay The transmit buffer holds the next byte or halfword to be transmitted While the current datum is being transmitted the QSPI loads the next datum to the transmit buffer from Data RAM The address of the next datum is contained in the queue pointer in the queue s QCR 8 2 4 RAM There are two byte addressable QSPI RAM segments The Data RAM is a 64 x 16 bit block that stores transmitted and received QSPI data The MCU writes data to be transmitted in the Data RAM If receive is enabled the QSPI writes received data from the receive
454. ortB PCRA equ SFFBF SAP GPIO control register PRRA equ SFFBE SAP GPIO data direction register PDRA equ SFFBD SAP GPIO data register STDA equ 5 used as port A gpio pin 5 PCRB equ SFFAF BBP GPIO control register PRRB equ SFFAE BBP GPIO data direction register PDRB equ SFFAD BBP GPIO data register STDB equ 5 used as port B gpio pin 5 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk A 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program Begining of code AARRE REEERE RERE REER RRA RE RAR RARE RARA RARA RE RARA RARE RRA RE RAR RARE RARE RE RAA ARA org P 800 bootloader begins at start of ROM START configured SAP and BBP as gpio inputs move 7 S80 r0 movep r0 x PCRA gpio PEN bit set others cleared movep rO x PCRB gpio PEN bit set others cleared move 70 x0 movep X0 x PRRA gpio inputs movep X0 x PRRB gpio inputs nop SIDA STDB d 1 boot mode A normal boot 0 1 boot mode B jump to user ROM ul O boot mode C messaging unit boot gt 0 0 SPS modes jset ZSTDA x PDRA START BOOT jset ZSTDB x PDRB START BOOT else continue with SPS code kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SPS MODES Approx 325 words of Program ROM are reserved for SPS test modes at this location kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
455. ory is contained on the device and the DSP address and data buses do not appear external to the device The MCU subsystem provides both on chip memory and an external bus interface Both processors provide external interrupt pins The two cores communicate through the MDI which includes a block of dual access RAM Each core generates its own independent clock and the DSP core contains a PLL as part of its clock generation subsystem Each processor and its associated peripherals have several low power standby modes A single JTAG port is shared by the two cores for debug and test purposes The JTAG port is integrated with on chip emulation modules for both the MCU and the DSP providing a non intrusive way to interact with the processors and their peripherals and memory The MCU has additional external debug pins for in circuit emulation The DSP program address bus is multiplexed on other DSP36632 pins The pins associated with most peripherals can be programmed individually to function as general purpose input output signals GPIO if their primary functions are not required The exceptions are the MCU pulse width modulator and general purpose timer which have no GPIO capability and the SmartCard Port SCP whose five pins must all function either as SCP pins or GPIO i e cannot be individually programmed 1 2 1 MCU This section describes the MCU core peripherals and memory 1 4 DSP56652 User s Manual Motorola For More Inform
456. otorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Edge Port EPPAR Edge Port Pin Assignment Register 0020_9000 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO EPPA7 EPPA6 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1 EPPAO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 7 10 EPPAR Description Name Description Settings EPPA7 0 Edge Port Pin Assignment 7 0 Each pair of bits determines the 00 Level sensitive trigger mechanism for an Edge I O input Interrupt requests are default always generated from this block but may be masked within the 01 Rising edge sensitive MCU interrupt controller The functionality of this register is 10 Falling edge sensitive independent of the programmed pin direction 11 Both rising and falling edge sensitive Pins configured as level sensitive are inverted so that a logic low on the external pin represents a valid interrupt request Level sensitive interrupt inputs are not latched The interrupt source must assert the signal until it is acknowledged by software to guarantee that a level sensitive interrupt request is acknowledged Pins configured as edge sensitive interrupts are latched and need not remain asserted Pins programmed as edge detecting are monitored regardless of the configuration as input or output EPDDR Edge Port Data Direction Register 0020_ 9002 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO
457. otorola Serial Audio and Baseband Ports 14 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers SAPCRA SAP Control Register A X FFB6 BBPCRA BBP Control Register A X FFA6 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O PSR WL 1 0 DC 4 0 PM 7 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 7 SAP BBP CRA Description Name Description Settings PSR Bit Clock Prescaler Setting this bit bypasses Prescale applied default Bit 15 the divide by eight prescaler to the bit rate 1 No prescale generator Note The combination of PSR 1 and PM 7 0 00 is reserved and may cause synchronization problems if used WL 1 0 Word Length These bits select the word length 00 8 bits per word default Bits 14 13 for transmitted and received data 01 12 bits per word 10 16 bits per word 11 Reserved DC 4 0 Frame Rate Divider Control These bits in conjunction with the MOD bit in the SAPCRC or Bits 12 8 BBPCRC configure the transmit and receive frames Refer to Table 14 3 on page 14 6 In network mode value of this field plus one equals the number of slots per frame In normal mode the value of this field is the number of dummy time slots effectively determining the word transfer rate PN 7 0 Prescale Modulus These bits along with the PSR bit determine the bit clock frequency Refer to Bits 7 0 Section 14 2
458. ource Clock Out Asynchronous Mode 0 0 0 External SCOA B x External SCKA B 0 0 1 Internal SCOA B External SCKA B 0 1 0 External SCOA B Le Internal SCKA B 0 1 1 Internal SCOA B Internal SCKA B Synchronous Mode 1 0 x External SCKA B External SCKA B 1 1 x Internal SCKA B Internal SCKA B Note Although an external serial clock can be independent of and asynchronous to the DSP system clock its frequency must be less than or equal to one third the DSP_CLK frequency 14 2 2 Clock Frequency The frequency of the internally generated bit clock is determined by the source clock an optional divide by 8 prescaler and a programmable prescale modulus as shown in the following equation Bit clock frequency BRGCLK 2 x 2 PSRY x PM 1 where BRGCLK DSP_CLK BBP DSP_CLK or BRM_CLK SAP PSR Prescaler PSR bit in Control Register A SAPCRA or BBPCRA PM Value of the Prescale Modulus PM 7 0 bits in SAPCRA or BBPCRA 14 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Transmit and Receive Clocks The minimum frequency is generated with the prescaler on PSR 0 and the maximum prescale modulus PM 7 0 255 yielding Bit clock frequency BRGCLK BRGCLK 2 x 2 x 256 4096 The combination of PSR 1 and PM 7 0 0 is reserved so the maximum frequency
459. output 1 1 WL bit clock for TX 1 bit clock for RX MOD Description FSR Description 0 Normal mode 0 Frame sync occurs with first bit of 1 Network mode current frame 1 Frame sync occurs with last bit of SYN Description previous frame 0 Asynchronous mode FSP Description 1 Synchronous mode 0 Positive frame sync 1 Negative frame sync 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSP FSR FSL1 FSLO BRM SHFD CKP SCKD SCD2 SCD1 SCDO MOD SYN Reserved E 80 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer TUE Description SAPS R 1 TX underrun occurred SAP Status Register Address X FFB9 Reset 0000 Read Write TFS Description 1 TX frame sync occurred ROE Description 1 RX overrun occurred RFS Description 1 RX frame sync occurred TDE Description 1 TX data register empty Serial Input Flags RDF Description 1 RX data register has data Reserved Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 81 Freescale Semiconductor Inc Application Date Programmer SAP SAPRX SAP Receive Data Register Address X FFBA Reset 0000 Read W
460. peats from step 3 If no further data is to be sent in this frame the first time slot of the next frame can be set up by writing either the Transmit Register with data for the first time slot or the Time Slot Register After transmission of the last data word is completed the TE bit can be toggled cleared and then reset This action disables the transmitter after the last bit has been shifted out of the transmit shift register and the STDx pin remains in the high impedance state until the beginning of the next frame At the next frame sync the next frame begins at step 3 At step 3 if neither the Transmit Register nor the Time Slot Register have been written since step 3 of the previous cycle the TUE bit is set and an interrupt is generated if enabled as described in Normal mode 14 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Transmission and Reception In addition to interrupts for receive and transmit special network mode interrupts are provided to indicate the last slot 14 4 1 3 On Demand Mode A typical transmission sequence in on demand mode is as follows 1 Set the TE bit in the SAPCRB or BBPCRB 2 Write transmit data to the port s Transmit Register 3 The Transmit Register data is copied to the Transmit Shift Register The Transmit Register retains the current data until it is written again 4 The TDE bit is set an
461. peline restrictions See Table 5 6 on read default page 5 15 DRFO R DSP Receive Register 0 Full Set when the O Latest DRRO data has been read Bit 13 MCU writes to MTRO indicating to the DSP default that the reflected data is available in DRRO 1 New data in DRRO DRFO is cleared when the DSP reads DRRO DRF1 R DSP Receive Register 1 Full Set when the O Latest DRR1 data has been read Bit 12 MCU writes to MTR1 indicating to the DSP default that the reflected data is available in DRR1 1 New data in DRR1 DRF1 is cleared when the DSP reads DRR1 DGIRO R 1S DSP General Interrupt Request 0 Setting 0 No interrupt request O default Bit 11 this bit generates an interrupt request to the 1 DSP has issued interrupt request 0 MCU if the MGIEO bit in the MCR is set It is reflected in the MGIPO bit in the MSR It is cleared when the MCU clears MGIPO indicating to the DSP that the MCU has serviced the interrupt DGIR1 R 1S DSP General Interrupt Request 1 Setting O No interrupt request 1 default Bit 10 this bit generates an interrupt request to the 1 DSP has issued interrupt request 1 MCU if the MGIE1 bit in the MCR is set It is reflected in the MGIP1 bit in the MSR It is cleared when the MCU clears MGIP1 indicating to the DSP that the MCU has serviced the interrupt DTIC 1S DSP Protocol Timer Interrupt Clear Used by the Protocol Timer DSP interrupt IRQD Bit 9 service routine to clear the interrupt Wr
462. peripherals Table 6 3 summarizes the possible transfer sizes alignments and port widths as well as the SIZ1 SIZO signals A1 AO signals and DSZ 1 0 bits used to generate them 6 3 2 External Boot ROM Control The MOD input signal is used to specify the location of the boot ROM device during hardware reset If an external boot ROM is used instead of the internal ROM the CSO output can be used to select the external ROM coming out of reset If MOD is driven low at least four CKIL clock cycles before RESET_OUT deassertion the internal MCU ROM is disabled and CSO is asserted for the first MCU cycle The MCU fetches the reset vector from address 0 of the CSO memory space which is located at the absolute address 4000_0000 in the MCU address space The internal MCU ROM is disabled for the first MCU cycle only and is available for subsequent accesses Out of Reset CSO is configured for 15 wait states and a 16 bit port size If MOD is driven high at least four CKIL clock cycles before RESET_OUT deassertion the internal ROM is enabled and the MCU fetches the reset vector from internal ROM at address 0000_0000 6 3 3 Bus Watchdog Operation The EIM contains a bus watchdog timer that monitors the length of all request accesses from the MCU If an access does not terminate i e the bus watchdog timer does not receive an internal Transfer Acknowledge TA signal or Transfer Error Acknowledge TEA signal within 128 clock cycles of being
463. pi qpcr qpc0 equ qspi qpcr qpcl equ qspi qpcr qpc2 equ qspi qpcr qpc3 equ qspi qpcr qpc4 equ qspi qpcr qpc5 equ qspi qpcr qpc6 equ qspi qpcr qpc7 old names ZO UH 0NRO NEW NAMES ZO UH Co 2 I Oo QSPI QDDR BITS old names equ qspi qddr pd0 equ qspi qddr pdl equ qspi qddr pd2 equ qspi qddr p33 equ qspi qddr pd4 equ qspi qddr pd5 equ gspi_qddr_pd6 equ qspi_qddr pd7 NNO BWNHE O QSPI QDDR BITS NEW NAMES equ qspi gddr qddd 0 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Equates equ qspi qddr qddl equ qspi gddr qdd2 equ qspi gddr qdd3 equ qspi qddr qdd4 equ qspi qddr qdd5 equ qspi qddr qdd6 equ qspi qddr qdd7 Z O UH 0 N E QSPI OPDR BITS OSPI QDDR BITS old names equ qspi qpdr do 0 equ qspi qpar dl 1 equ qspi qpdr d2 2 equ qspi qpdr d3 3 equ qspi qpdr d4 4 equ qspi qpdr d5 7 QSPI QPDR BITS QSPI QDDR BITS NEW NAMES equ qspi qpdr qpd0 0 equ qspi qpdr qpdl 1 equ dqspi qpdr qp 2 equ dqspi qpdr qpi3 3 equ dqspi qpdr qpd4 4 equ dqspi qpdr qpd5 5 equ qspi qpdr qpd6 6 equ qspi qpdr qpd7 7 QSPI SPCR BITS equ qspi spcr qspe equ qspi spcr doze equ qspi spcr halt equ qspi spcr wie equ qspi spcr trcie equ qspi spcr hltie equ qspi spcr qe0 equ qspi spcr gel equ qspi spcr ge2 equ qspi spcr qe3 10 eq
464. program must reset the SAP or BBP before changing any of its control registers except for the SAPCRB or BBPCRB 14 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Frame Counters BBP Only 14 6 General Purpose Timer SAP Only The SAP provides a general purpose timer that can be used for debugging The timer is enabled by the TCE bit in the SAPCRB The following two registers control timer operation The SAP Timer Counter SAPCNT is a counter that is decremented by a clock running at a frequency of DSP_CLK 2048 When it decrements to zero a timer counter rollover interrupt is issued e The SAP Timer Modulus Register SAPMR contains a modulus value that is loaded into the SAPCNT register when TCE is set and each time the counter rolls over Note Although this timer is technically not involved in SAP operation the SAP must be enabled by setting the PEN bit and at least one of the PC 5 0 bits in the SAP Port Control Register SAPPCR to enable the timer 14 7 Frame Counters BBP Only The BBP provides two counters that can be used to count transmit and receive frames Setting the TCE bit in BBPCRB enables the transmit frame counter and loads it with the value in the BBP Transmit Counter Modulus Register BBPTMR The counter is decremented by transmit frame sync When the counter rolls over it is again loaded with BBPTMR and an interrupt
465. provides precise interrupts at regular intervals with minimal processor intervention The timer can count down either from the maximum value FFFF or the value written in a modulus latch 9 1 1 PIT Operation Figure 9 1 shows a block diagram of the PIT Motorola Timers 9 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Periodic Interrupt Timer MCU Peripheral Bus PITMR Load Counter PITCNT Count 0 Figure 9 1 PIT Block Diagram Interrupt The PIT uses the following registers e PITCSR The Periodic Interrupt Timer Control and Status Register determines whether the counter is loaded with FFFF or the value in the Module Latch controls operation in Debug mode and contains the interrupt enable and flag bits e PITMR The Periodic Interrupt Timer Module Latch contains the rollover value loaded into the counter e PITCNT The Periodic Interrupt Timer Counter reflects the current timer count Each cycle of the PIT clock decrements the counter PITCNT When PITCNT reaches zero the ITIF flag in the PITCSR is set An interrupt is also generated if the ITIE bit in the PITCSR has been set by software The next tick of the PIT clock loads either FFFF or the value in the PITMR depending on the state of the RLD bit in the PITCSR The PIT clock is a fixed rate of CKIL 4 Internal clock synchronization logic enables the MCU to read the counter value accurately This logic
466. put when GPIO Address 0020_3818 Reset 0000 Read Write 15 14 13 12 11 10 7 6 5 4 3 2 1 0 PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDDO PTPDR PT Port Data Register Address 0020 381A Reset 00uu Read Write Port Data Bits 7 6 5 4 3 2 1 0 PTDAT7 PTDAT6 PTDAT5 PTDAT4 PTDAT3 PTDAT2 PTDAT1 PTDATO Reserved E 66 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer OVRRUN Description UART 0 No FIFO overrun 1 URX FIFO overrun detected FRMERR Description UART Receive Register Address 0020 4000 to 403C 0 No framing error detected Reset 00uu 1 Character has a framing error Read Write 212 BRK Description ERR Description EE 0 Character is not a BREAK 0 No error detected in bits 13 10 1 Character is a BREAK 1 Error detected ER PRERR Description CHARRDY Description 0 No parity error detected 0 Character not ready 1 Parity error detected 1 Character ready Rx Data 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 CHARRDY ERR OVRRUN FRMERR BRK PRERR data data data
467. quency PD 6 0 PLL Divisor divisor The divisor is equal to one plus the value of PD 6 0 00 1 default 01 2 7F 128 COD Clock Output Disable This bit disconnects DSP_CLK from the CKO pin in some implementations Bit 7 In the DSP56652 this bit has no effect PEN PLL Enable Enables PLL operation Disabling O PLL is disabled default DSP_CLK is Bit 6 the PLL shuts down the VCO and lowers power derived directly from DSP REF consumption The PEN bit can be set or cleared 1 PLL is enabled DSP_CLK is derived from by software any time during the chip operation the PLL VCO output PSTP STOP Processing State Controls the behavior O Disable PLL in STOP mode default Bit 5 of the PLL during the STOP processing state 1 Enable PLL in STOP mode Shutting down the PLL in STOP mode decreases power consumption but increases recovery time XTLD These bits affect the on chip crystal oscillator in certain implementations They are not used in the XTLR DSP56652 Bits 4 3 DF 2 0 Division Factor Internal clock divisor that Bits 2 0 determines the frequency of the low power clock DF 2 0 DF Changing the value of the DF bits does not cause a loss of lock condition These bits should be 000 2 default changed rather than MF 11 0 to change the clock frequency e g when entering a low power 001 21 mode to conserve power 111 27 Motorola Core Operation and Configuration 4 7 For More Information On This Product Go to www fre
468. quest When the MCU sets the HALT bit the QSPI finishes any ongoing serial transfer asserts HALTA and halts If a queue is executing when HALT is asserted the QSPI checks the value of the HMD bit in its QCR If HMD is clear the QSPI halts only at the next PAUSE NOP or EOQ commands If HMD is set the QSPI halts at the next sub queue boundary During Halt mode the QSPI continues to accept new transfer triggers from the protocol timer and MCU and the MCU can access any of the QSPI registers and RAM addresses The HALT bit is cleared when HALTA is deasserted so that only one MCU access is required to exit the Halt state The QSPI state machines and the SPCR are not reset during the Halt process so the QSPI resumes operation where it left off NOTE The HALT bit is checked only at sub queue or queue boundaries If the HALT bit is asserted and then deasserted before a sub queue transfer has completed the QSPI does not recognize a Halt request DOZE Enable Determines the QSPI response to Doze mode If the DOZE bit is set when DOZE mode is identified the QSPI finishes any ongoing serial transfer and halts as if the HALT bit were set When the DOZE mode is exited the MCU must clear HALTA for the QSPI to resume operation If the DOZE bit is cleared DOZE mode is ignored ormal operation 0 1 alt request N H 0 QSPI ignores DOZE mode default 1 QSPI halts in DOZE mode QSPE Bit 0 QSPI Enable Setti
469. r 0020_3802 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 TERIE THIE DVIE DSIE MCIE2 MCIE1 MCIEO RSNIE CFNIE CFIE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note The conditions in Table 10 7 must be met in addition to setting the individual interrupt enable bits in the PTIER Table 10 7 Additional Conditions for Generating PT Interrupts PTIER Bit Additional Conditions MCIE2 Set EPT2 bit in the NIER or EFPT2 bit in the FIER MCIE1 Set EPT1 bit in the NIER or EFPT1 bit in the FIER MCIEO Set EPTO bit in the NIER or EFPTO bit in the FIER TERIE Set EPTM bit in the NIER or EFPTM bit in the FIER THIE DVIE RSNIE CFNIE CFIE DSIE Write the IDPL field in the IPRC with a non zero value The NIER and FIER registers are described on page 7 7 The IPRC register is described on page 7 14 10 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers Table 10 8 PTIER Description Name Description Settings TERIE Timer Error Interrupt Enable Enables an MCU O Interrupt disabled default Bit 12 interrupt when a timer error has been detected see 1 Interrupt enabled Section 10 2 4 on page 10 11 THIE Timer HALT Interrupt Enable Enables an MCU Bit 11 interrupt when the PT enters the halt state either from a frame tab
470. r Address 0020_600A Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data TOCR4 Timer 4 Output Compare Register Address 0020_600C Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data TICR1 Timer 1 Input Capture Register Address 0020_600E Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data TICR2 Timer 2 Input Capture Register Address 0020_6010 Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data E 56 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer PWM PWOR PWM Output Compare Register Address 0020_6012 Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6
471. r 0 Address 0020_5F12 Reset 0000 CSCKDFO 0 2 Assertion to Activation Delay 000 1 SCK cycle delay 001 2 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay 101 32 SCK cycles delay 110 64 SCK cycles delay 111 128 SCK cycles delay SCK MCU_CLK 2 3 SCKFDO 6 1 SCKDFO0 0 5 1 All values for SCKDFO 0 6 are valid Sample values are shown SCKDFO 0 6 Description 000_0000 SCK MCU_CLK 2 000_0001 SCK MCU_CLK 4 000_0111 SCK MCU_CLK 16 100_0000 SCK MCU_CLK 8 000_0100 SCK MCU_CLK 10 100_1011 SCK MCU_CLK 96 111_1110 SCK MCU_CLK 504 Read Write DATRO 0 2 Delay After Transfer 000 1 SCK cycle delay 001 2 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay 101 32 SCK cycles delay 110 64 SCK cycles delay 111 128 SCK cycles delay LSBFO Description 0 Data transferred MSB first 1 Data transferred LSB first CKPOLO Description 0 SCK inactive at logic 1 1 SCK inactive at logic 0 CPHAO Description 0 Data changes on first SCK transition 1 Data latches on first SCK transition 111 1111 SCK MCU CLK 1 15 14 13 12 11 10 5 4 3 2 1 0 CAPHAO CKPOLO LSBFO DATRO2 DATRO1 DATROO CSCKDO2 CSCKDO01 CSCKDOO SCKD
472. r E 77 KPDR Keypad Data Register E 77 Serial Audio Port SAPCNT SAP Timer Counter E 78 SAPMR SAP Timer Modulus Register E 78 SAPCRC SAP Control Register A E 78 SAPCRB SAP Control Register B E 79 SAPCRA SAP Control Register C E 80 SAPSR SAP Status Register E 81 SAPRX SAP Receive Data Register E 82 SAPTSR SAP Time Slot Register E 82 SAPTX SAP Transmit Data Register E 82 SAPPCR SAP Port Control Register E 83 SAPDDR SAP GPIO Data Direction Register E 83 SAPPDR SAP Port Data Register E 83 E 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table E 1 List of Programmer s Sheets Continued Register Functional Block Page Acronym Name Baseband Port BBPRMR BBP Receive Counter Modulus Register E 84 BBPTMR BBP Transmit Counter Modulus Register E 84 BBPCRA BBP Control Register A E 84 BBPCRB BBP Control Register B E 85 BBPCRC BBP Control Register C E 87 BBPSR BBP Status Register E 88 BBPRX BBP Receive Data Register E 89 BBPTSR BBP Time Slot Register E 89 BBPTX BBP Transmit Data Register E 89 BBPPCR BBP Port Control Register E 90 BBPDDR BBP GPIO Direction Register E 90 BBPPDR BBP Port Data Register E 90 Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Progra
473. r Memory Summary Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CONT RAM BYTE RE PAUSE CONT PCS EOTIE NOP 000 07F EOQ 080 3FF Reserved DATA RAM MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 400 47F 480 EFF Reserved QPCR PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO FOO SCK MOSI MISO CS4 CS3 CS2 CS1 CSO QDDR PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO F02 SCK MOSI MISO CS4 CS3 CS2 CS1 CSO QPDR D7 D6 D5 D4 D3 D2 D1 DO F04 SCK MOSI MISO CS4 CS3 CS2 CS1 CSO SPCR CSPOLA CSPOLS CSPOL2 CSPOL1 CSPOLO QE3 QE2 QE1 QEO HLTIE TRCIE WIE HALT DOZE QSPE F06 QCRO LEO HMDO QPO F08 QCR1 LE1 HMD1 TRCNT1 QP1 FOA QCR2 LE2 HMD2 QP2 FOC QCR3 LES HMD3 QP3 FOE SPSR QX3 Qx2 QX1 QXO QA3 QA2 QA1 QAO HALTA TRC QPWF EOT3 EOT2 EOT1 EOTO F10 SCCRO CPHAO CKPOLO LSBFO DATRO CSCKDO SCKDFO F12 SCCR1 CPHA1 CKPOL1 LSBF1 DATR1 CSCKD1 SCKDF1 F14 SCCR2 CPHA2 CKPOL2 LSBF2 DATR2 CSCKD2 SCKDF2 F16 SCCR3 CPHA3 CKPOL3 LSBF3 DATR3 CSCKD3 SCKDF3 F18 SCCR4 CPHA4 CKPOL4 LSBF4 DATR4 CSCKD4 SCKDF4 F1A F1C FF7 Reserved FF8 MCU Trigger for Queue O FFA MCU Trigger for Queue 1 FFC MCU Trigger for Queue 2 FFE MCU Trigger for Queue 3 1 All addresses are offsets from 0020 5000
474. r contents Any attempted access within the reserved portion of the peripheral memory space 0020 D000 to 003F FFFF results in TEA termination and an access error exception from an EIM watchdog time out after 128 MCU clock cycles 3 1 4 External Memory Space The MCU memory map allocates 96 Mbytes for external chip access starting at address 4000 0000 Six external chip selects are allocated 16 Mbytes each Only the first 4Mbytes in each 16 Mbyte space are addressable by the 22 address lines A0 A21 An Motorola Memory Maps 3 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Memory Map and Descriptions access to an address more than 4 Mbytes above the chip select base address is modulo mapped into the first 4 Mbytes See Table 6 2 on page 6 4 for more information regarding this portion of the memory map 3 1 5 Reserved Memory Two portions of the MCU memory map are reserved 0040_0000 to 3FFF_FFFF and 4600_0000 to FFFF_FFFF Any attempted access within these reserved portions of the memory space results in TEA termination and an access error exception from an EIM watchdog time out after MCU 128 clock cycles 3 2 DSP Memory Map and Descriptions The DSP56652 DSP core contains three distinct memory spaces e X data memory space e Y data memory space e program P memory space Each of these spaces contains both RAM and ROM In addition the X data space has partitions fo
475. r on chip devices registers are defined to be 16 or 32 bits wide For registers that do not implement all 32 bits the unimplemented bits return zero when read and writes to unimplemented bits have no effect In general unimplemented bits should be written to zero to ensure future compatibility e All peripherals define the exact results for 32 bit 16 bit and 8 bit accesses according to individual peripheral definitions Misaligned accesses are not supported nor is bus sizing performed for accesses to registers smaller than the access size The MCU memory map allocates 2 Mbyte for internal MCU peripherals starting at address 0020 0000 Twelve of the sixteen DSP56652 peripherals are allocated 4 kbytes each and four peripherals are allocated 1 kbyte each for a total of 52 kbytes The remainder of the 2 Mbyte space is reserved for future peripheral expansion Each peripheral space may contain several registers Details of these registers are located in the respective peripheral description sections Software should explicitly address these registers making no assumptions regarding modulo mapping A complete list of these registers and their addresses is given in Table D 8 on page D 14 Read accesses to unmapped areas within the first 52 kbytes of peripheral address space returns the T signal if supervisor permission allows Uninitialized write accesses within the first 52 kbytes also return the TA signal and may alter the peripheral registe
476. r peripherals and the MCU DSP interface MDI All memory on the DSP side is contained on chip there is no provision for connection to external memory The three memory spaces are shown in Figure 3 2 3 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Memory Map and Descriptions X Data 16 Bit Y Data 16 Bit Program 24 Bit FFFF FFFF FFFF Internal X l O Reserved 14K FF80 C800 Internal Internal Reserved 22K Reserved 22K 48K Internal A800 A800 P ROM 10K Internal 10K Internal X ROM Y ROM 8000 8000 Internal Internal Reserved 24K Reserved 26K 2000 MDI 1800 M RAM 1K JUR Internal 6K Internal Reserved 0 5K TA moma we 0 5K Internal X RAM P RAM 0000 0000 0000 Figure 3 2 DSP Memory Map 3 2 1 X Data Memory X data RAM is a 16 bit wide internal static memory occupying the lowest 8K locations in X memory space The upper 1K of this space X 1C00 1CFF is dedicated to the MDI X data ROM is a 16 bit wide internal static memory occupying 10K located at X 8000 A7FF The top 128 locations of the X data memory FF80 S FFFF contain the DSP side peripheral registers and addressable core registers This area referred to as X I O space can be accessed by MOVE MOVEP and the bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCL
477. ral Interrupt Priority Register IPRP must written with a non zero value in order to generate any of the interrupts enabled in the DCR see page 7 7 Table 5 17 DCR Description Name Description Settings DTIEO DSP Transmit Interrupt Enable 0 If DTIEO is set O Transmit interrupt O request disabled Bit 15 a transmit interrupt 0 request is generated when the default DTEO bit in the DSR is set If DTIEO bit is cleared 1 Enabled DTEO is ignored and no transmit interrupt request O is issued DTIE1 DSP Transmit Interrupt Enable 1 If DTIE1 is set O Transmit interrupt 1 request disabled Bit 14 a transmit interrupt 1 request is generated when the default DTE1 bit in the DSR is set If DTIE1 bit is cleared 1 Enabled DTE1 is ignored and no transmit interrupt request 1 is issued DRIEO DSP Receive Interrupt Enable 0 When DRIEO is O Receive interrupt O request disabled Bit 13 Set a receive interrupt request O is issued when the default DRFO bit in the DSR is set When DRIEO is cleared 1 Enabled DRFO is ignored and no receive interrupt request 0 is issued DRIE1 DSP Receive Interrupt Enable 1 When DRIE1 is O Receive interrupt 1 request disabled Bit 12 Set a receive interrupt request 1 is issued when the default DRF1 bit in the DSR is set When DRIE1 is cleared 1 Enabled DRF1 is ignored and no receive interrupt request 1 is issued MCIE MCU Command Interrupt Enable lf this bit is set O Maskable interrupts dis
478. ram 15 2 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56600 Core JTAG Operation 15 1 DSP56600 Core JTAG Operation The DSP36600 core JTAG TAP includes six signal pins a 16 state controller an instruction register and three test data registers The test logic employs a static logic design and is independent of the device system logic A block diagram of the DSP56600 core implementation of JTAG is shown in Figure 15 2 Boundary Scan Register BSR TDI Bypass ID Register 5 i z OnCE Logic Te C Decoder 1 2 1 TDO MUX 4 Bit Instruction Register TMS TCK 3 TAP Ctrl TRST s Figure 15 2 DSP56600 Core JTAG Block Diagram 15 1 1 JTAG Pins As described in the IEEE 1149 1 document the JTAG port requires a minimum of four pins to support the TDI TDO TCK and TMS signals The DSP TAP also provides TRST and DSP_DE pins The pin functions are described in Table 15 1 Motorola JTAG Port 15 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56600 Core JTAG Operation Table 15 1 DSP JTAG Pins Pin Description TCK Test Clock An input that is used to synchronize the test logic The TCK pin has an inter
479. ransfer 000 1 SCK cycle delay 001 2 SCK cycles delay 010 4 SCK cycles delay 011 8 SCK cycles delay 100 16 SCK cycles delay 101 32 SCK cycles delay 110 64 SCK cycles delay 111 128 SCK cycles delay LSBF2 Description 0 Data transferred MSB first 1 Data transferred LSB first CKPOL2 Description 0 SCK inactive at logic 1 1 SCK inactive at logic 0 CPHA2 Description 0 Data changes on first SCK transition 1 Data latches on first SCK transition 111 1111 SCK MCU CLK 1 15 14 13 12 11 10 5 4 3 2 1 0 CAPHA2 CKPOL2 LSBF2 DATR22 DATR21 DATR20 CSCKD22 CSCKD21 CSCKD20 SCKDF26 SCKDF25 SCKDF24 SCKDF23 SCKDF22 SCKDF21 SCKDF20 Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 45 Freescale Semiconductor Inc Application Date Programmer S C G R 3 CSCKDF3 0 2 Assertion to Activation Delay 000 1 SCK cycle delay Serial Channel Control Register 3 001 2 SCK cycles delay Address 0020_5F18 Reset 0000 010 4 SCK cycles delay Read Write 011 8 SCK cycles delay 100 16 SCK cycles delay DATR3 0 2 Delay After Transfer 101 32 SCK cycles delay 000 1 SCK cycle delay 110 64 SCK
480. ransfers the full 16 bits of the queue entry s data halfword ceive disabled RE Receive Enable This bit enables or disables data reception 0 1 ceive enabled Bit 5 by the QSPI The QSPI enables reception of data from the MISO pin for each queue entry in which the RE bit is set and writes the received halfword into the data halfword of that queue entry The received halfword will overwrite the transmitted data that was previously stored in that RAM address DD e e 8 22 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory Table 8 7 QSPI Control RAM Description Continued Name Description Settings PAUSE PAUSE T his bit specifies whether the QSPI pauses after the O Not a queue boundary Bit 4 transfer of a queue entry When the QSPI identifies an 1 Queue boundary asserted PAUSE bit in a queue entry s control halfword the QSPI recognizes that it has reached the end of a queue After transfer of that queue entry the QSPI terminates execution of the queue by clearing the associate QX and QA bits in SPSR It then processes the next activated queue with the highest priority When the QSPI identifies a cleared PAUSE bit it proceeds to transfer the next entry in that queue CONT Continuous Chip Select Specifies if the chip select line
481. re enabled by the Receive Last Slot Interrupt RLIE and Transmit Last Slot Interrupt TLIE bits in the SAPCRB or BBPCRB The other four TDM interrupts Receive Receive Error Transmit and Transmit Error can occur in any TDM mode These interrupts are described in Section 14 4 14 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Transmission and Reception 14 4 Data Transmission and Reception Each port provides configuration options for data transmission and reception as well as data format 14 4 4 Data Transmission The transmission sequence varies somewhat between normal network and on demand modes 14 4 1 1 Normal Mode Transmission The following steps illustrate a typical transmission sequence in normal mode 1 Write the first transmit data word to the port s Transmit Register SAPTX or BBPTX This clears the Transmit Data Register Empty TDE bit in the SAPSR or BBPSR 2 Set the Transmit Enable TE bit in the SAPCRB or BBPCRB 3 At the next TFS the Transmit Register data is copied to the Transmit Shift Register the transmitter is enabled and the TDE bit is set The Transmit Register retains the current data until it is written again If the Transmit Interrupt Enable TIE bit in the SAPCRB or BBPCRB is set an interrupt is generated At this point a new value is normally written to the Transmit Register clearing TD
482. read default DSP reads the reflected data in DRRO MTE1 R MCU Transmit Register 1 Empty Cleared 0 DRR1 has not been read Bit 12 when the MCU writes to MTR1 set when the 1 DRR1 has been read default DSP reads the reflected data in DRR1 MGIPO R 1C MCU General Interrupt 0 Pending Indicates O No interrupt request default Bit 11 that the DSP has requested an interrupt by 1 DSP has issued interrupt request 0 setting the DGIRO bit in the DSR MGIP1 R 1C MCU General Interrupt 1 Pending Indicates O No interrupt request default Bit 10 that the DSP has requested an interrupt by 1 DSP has issued interrupt request 1 setting the DGIR1 bit in the DSR MTIR R MCU Protocol Timer Interrupt Request Set O No outstanding MTIR generated Bit 9 by the protocol timer when it issues a dsp_int interrupt request default event see Table 10 4 on page 10 13 which 1 DSP has not serviced last asserts DSP IRQD waking the DSP from MTIR generated interrupt STOP mode and IRQA which is wire or d to IRQD MTIR is cleared when the DSP sets the DTIC bit in the DSR Table 5 18 on page 5 25 at the end of its IRQD service routine For proper MTIR operation IRQD should be enabled via IPRC bits 10 9 and made level sensitive by clearing IPRC bit 11 Software should verify that MTIR is cleared before issuing an MDI reset setting the MDIR bit in the MCR Motorola MCU DSP Interface 5 21 For More Information On This Product Go t
483. rectly to one of the transmit registers Both transmit registers are used to pass a 2 word message The corresponding receive register of the first word disables its interrupt the register receiving the second word enables its interrupt An interrupt is triggered when the second word is received e Transmit registers pass frame information describing longer messages written to the shared memory Such frame information usually includes an initial address the number of words and often a message type code ADSP general interrupt or the MCU Command Interrupt signals an event or request that does not include data words such as acknowledging the read of a long message from the shared memory Motorola MCU DSP Interface 5 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Messages and Control e Fixed length formatted data is written in a predetermined location in the shared memory A general purpose interrupt DSP or command interrupt MCU signals the other processor that the data is ready One processor uses the three general purpose flags to inform the other processor of its current program state 5 2 3 MDI Interrupt Sources The MDI provides several ways to generate interrupts to both the DSP and MCU 5 2 3 1 DSP Interrupts There are five independent ways for the MCU to interrupt the DSP through the MDI 1 MCU Command Vector interrupt 2 MDI receive transmit interrupt
484. request e Ne e e Ne 99 e e NO e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e jsr upload to mcore jmp START BOOT MODE A upload to mcore This subroutine is used to perform memory uploads from the DSP to the M CORE Inputs r0 points to MDI memory 1 location past memory read request Registers Used M e Ne e e e 99 e e e 959 99 e 99 e 1aaw Lanaz aaar annau I I 0 1 2 A 22 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bootstrap Program e 9 Ne 99 e e xdef upload to mcore upload to mcore retrieve number of words to process move x r0 n0 n0 Awords retrieve memory space MDI address move x r0 x0 move x0 a and S03FF a keep lower 10 bits move al nl save MDI offset to nl add MDI_base a move al rl rl MDI memory address retrieve DSP memory address move x r0 r0 r0 DSP memory address write 1st header word move mem_read b0 move b0 x rl memory read indication long which memory space move x0 a and C000 a keep only upper 2 bits cmp mem_invalid a jeq lt mem read fail if it gets here it s a valid memory space write successful MDI header info move success b
485. reset this signal is a GPO that is driven low DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Reset Mode and Multiplexer Control 2 5 Reset Mode and Multiplexer Control The reset mode select and multiplexer control pins are listed in Table 2 8 Table 2 8 Reset Mode and Multiplexer Control Signals Signal Name Type Reset State Signal Description RESET_IN RESET_OUT Input Output Input Reset Input This signal is an active low Schmitt trigger input that provides a reset signal to the internal circuitry The input is valid if it is asserted for at least three CKIL clock cycles Note If MUX_CTL is held high the RTS signal of the serial data port UART becomes the RESET_IN input line See Table 2 12 on page 2 13 Pulled low Reset Output This signal is asserted low for at least seven CKIL clock cycles under any one of the following three conditions RESET IN is pulled low for at least three CKIL clock cycles The alternate RESET IN signal is enabled by MUX_CTL and is pulled low for at least three CKIL clock cycles The watchdog count expires This signal is asserted immediately after the qualifier detects a valid RESET IN signal remains asserted during RESET IN assertion and is stretched for at least seven more CKIL clock cycles after RESET IN is deasserted Three CKIL clock cycles before RES
486. rial Clock This bidirectional signal provides the serial Output bit rate clock It is used by both transmitter and receiver in synchronous mode or by the transmitter only in asynchronous mode SCOA Input or Input Audio Codec Serial Clock 0 This signal s function is determined by Output the transmission mode Synchronous mode serial I O flag O Asynchronous mode receive clock I O 2 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP Table 2 15 SAP Signals Continued Signal Name Type Reset State Signal Description SC1A Input or Input Audio Codec Serial Clock 1 This signal s function is determined by Output the transmission mode Synchronous mode serial I O flag 1 Asynchronous mode receiver frame sync I O SC2A Input or Input Audio Codec Serial Clock 2 This signal s function is determined by Output the transmission mode Synchronous mode transmitter and receiver frame sync I O Asynchronous mode transmitter frame sync I O Motorola Signal Connection Description 2 17 For More Information On This Product Go to www freescale com BBP 2 13 BBP The signals described in Table 2 16 are GPIO when not programmed otherwise and default as GPI after reset Freescale Semiconductor Inc Table 2 16 BBP Signals Signal Name Type Reset State Signal Description
487. riorities within an IPL o oo ooo oooo oo o 7 13 IPRPCDOSCHDLUDIE e a oe Ne a 7 14 IPRC Description st a a ee RISE Ea ns 7 15 EPPAR Description v uer O A ARS 7 17 EPDDR Descriptiot iced tir EE RA SERRS 7 17 EPDR Desorption Ls cu eoo AS P ORE nO EC EP A 7 18 EPER Description n eio d RR DRE En TCI C RO ORC ES ORS en 7 18 Serial Control Port Signals ness ded PE SC Rc DA EK RR icu ES 8 4 QSPI Register Memory Summary 0 0 eee e eee 8 12 SPCR Description s 523 A eh RE ee eee DOR a ee 8 13 OCR DESTAPE EE EXPE 8 15 SPSR Description s SeseswiswesenM us SARA 8 17 SCCR DGeSCHDUOB S Seis sex DN e RR Rc AO OSE Ihe E 8 19 QSPI Control RAM Description oooooooooooomoomomooo o 8 22 OPER Descriptor e deles ee t iba Ee e RR SUE 8 24 ODDR Description tds ER ERE ANE est ES hy 8 25 OPDR Description serren M os a n RR REOR RE 8 25 ET CSR Description aerorose a rs IM RiNRSR a ne aa da al 9 3 WCR DESTA e e o ad ans 9 6 List of Tables xvii For More Information On This Product Go to www freescale com Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 10 6 Table 10 7 Table 10 8 Table 10 9 Table 10 10 Table 10 11 Table 10 12 Table 10 13 Table 10 14 Table 10 15 Table 10 16 Table 10 17 Table 10 18 Table 10 19 Table 10 20 Table 10 21 Table 10 22 Table 10 23 Table 10 24 Table 10 25 Table 11 1 Table 11 2 xviii
488. ription N E R 0 Interrupt source is masked 1 INT4 interrupt source enabled Lower Halfword Normal Interrupt Enable Register E Lower Halfword EINT3 Description Reset 0000 0 Interrupt source is masked Read Write 1 INT3 interrupt source enabled EINT2 Description EINTS Description 0 Interrupt source is masked 0 Interrupt source is masked 1 INT2 interrupt source enabled 1 INT5 interrupt source enabled EINT1 Description EINT6 Description 0 Interrupt source is masked 0 Interrupt source is masked 1 INT1 interrupt source enabled 1 INT6 interrupt source enabled EINTO Description EINT7 Description 0 Interrupt source is masked 0 Interrupt source is masked 1 INTO interrupt source enabled 1 INT7 interrupt source enabled ES2 Description EURTS Description 0 Interrupt source is masked 0 Interrupt source is masked 1 Software Interrupt 2 source enabled 1 UART RTS Delta interrupt source enabled ES1 Description 0 Interrupt source is masked EKPD Description 1 Software Interrupt 1 source enabled 0 Interrupt source is masked 1 Keypad Interface interrupt source ESO Description enabled 0 Interrupt source is masked 1 Software Interrupt 0 source enabled 15 13 12 11 10 9 8 7 6 5 4 2 1 0 EKPD EURTS EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINTO ES2 ES1 ESO 0 0 0 NOTE NIER can only be written as a 32 bit Reserved E 28 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola
489. rite Enable byte 0 When driven low this signal indicates access to data byte 0 D8 D15 during a read or write cycle This pin may also act as a write byte enable if so programmed Output Driven high Enable byte 1 When driven low this signal indicates access to data byte 1 DO D7 during a read or write cycle This pin may also act as a write byte enable if so programmed Output Input Output Driven high Input Chip driven Output Enable When driven low this signal indicates that the current bus access is a read cycle and enables slave devices to drive the data bus with a read Mode Select This signal selects the MCU boot mode during hardware reset It should be driven at least four CKIL clock cycles before RESET OUT is deasserted MOD driven high MCU fetches the first word from internal MCU ROM MOD driven low MCU fetches the first word from the external memory CS0 Chip select 0 This signal is asserted low based on the decode of the internal address bus bits A 31 24 and the state of the MOD pin at reset It is often used as the external flash memory chip select After reset CSO access has a default of 15 wait states and a port size of 16 bits Output Output Driven high Driven low Chip selects 1 4 These signals are asserted low based on the decode of the internal address bus bits A 31 24 of the access address When not configured as chip sele
490. rite 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 High Byte Low Byte SAPTSR SAP Time Slot Register Address X FFBB Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dummy Register Written During Inactive Time Slots SAPTX SAP Transmit Data Register Address X FFBC Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 High Byte Low Byte E 82 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer SAP P D R Port Data Bits SAP Port Data Register Address X FFBD Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAPPD5 SAPPD4 SAPPD3 SAPPD2 SAPPD1 SAPPDO SAPPCR SAP Port Control Register Address X FFBF Reset 0000 Read Write PEN Description Port pins are tri stated Port pins enabled SAPPCn Description Pin configured as GPIO Pin configured as SAP 4 3 2 1 0 SAPDDR SAP Data Direction Register Address X FFBE Reset 0000 Read Write SAPPC2 SAPPC1 SAPPCO SAPDDn Description 0 Pin is input 1 Pin is output 8 7 6 5 4 3 2 1 0 Reserved SAPDD5 SAPDD4 SAPDD3 SAPDD2 SAPDD1 SAPDDO Motorola Program
491. rmation On This Product Go to www freescale com MCU Equates Freescale Semiconductor Inc prot ptpcr ptpc 5 0x5 Select the function of pin 5 in prot ptpcr ptpc 6 0x6 Select the function of pin 6 in prot ptpcr ptpc 7 0x7 Select the function of pin 7 in bits of the Port D Direction Register Register PDDR old names of pin 0 prot pddr pddr 0 0x0 prot pddr pddr 1 0x1 prot pddr pddr 2 0x2 prot pddr pddr 3 0x3 prot pddr pddr 4 0x4 prot pddr pddr 5 0x5 prot pddr pddr 6 0x6 prot pddr pddr 7 0x7 Select the direction Select the direction Select the direction Select the direction Select the direction Select the direction Select the direction Select the direction of pin of pin of pin of pin of pin of pin of pin 1 2 3 a i 5i 6 7 bits of the Protocol Timer Data Direction Register PIDDR NEW NAMES prot ptddr ptdd 0 0x0 prot ptddr ptdd 1 0x1 prot ptddr ptdd 2 0x2 prot ptddr ptdd 3 0x3 prot ptddr ptdd 4 0x4 prot ptddr ptdd 5 0x5 prot ptddr ptdd 6 0x6 prot ptddr ptdd 7 0x7 bits of the Port D Data Register PDDAT old names prot pddat pddat 0 prot pddat pddat 1 prot pddat pddat 2 prot pddat pddat 3 prot pddat pddat 4 prot pddat pddat 5 prot pddat pddat 6 prot pddat pddat 7 0 Y O U 40h E in port in port in port in port in port in port in port in port bits of the Protocol Timer Port Data Register PIPDR NEW NAMES prot_ptpdr_ptpd_0 prot
492. ro pointer bit the Macro Table Pointer RTPTR NEW NAMES macro pointer bit macro pointer bit macro pointer bit macro pointer bit macro pointer bit macro pointer bit macro pointer bit MCU Equates ONU 0o PN IDO ONU 0o PN IDO DD 04 0o NN IDO 0x8 0x9 Oxa the Frame Table Base Address Register xp Transmit macro pointer bit Transmit macro pointer bit Transmit macro pointer bit Oxb Transmit macro pointer bit Oxc Transmit macro pointer bit Oxd Transmit macro pointer bit Oxe Transmit macro pointer bit the Receive Transmit Base Address Register RTBAR ONU 0o ND I O 0x0 Frame table 0 base address bit 0 0x1 Frame table 0 base address bit 1 0x2 Frame table 0 base address bit 2 0x3 Frame table 0 base address bit 3 Ox4 Frame table 0 base address bit 4 0x5 Frame table 0 base address bit 5 Ox6 Frame table 0 base address bit 6 0x8 Frame table 1 base address bit 0 0x9 Frame table 1 base address bit 1 Oxa Frame table 1 base address bit 2 Oxb Frame table 1 base address bit 3 Oxc Frame table 1 base address bit 4 Oxd Frame table 1 base address bit 5 Oxe Frame table 1 base address bit 6 old names 0x0 Receive macro base address bit 0 0x1 Receive macro base address bit 1 0x2 Receive macro base address bit 2 Equates and Header Files For More Information On This Product Go to www freescale com B 9 MCU Equates Freescale Semiconductor Inc 0x3 0x4 0x5 0x6
493. rol Register X FFBF Bitib 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O PEN SAPPC5 SAPPC4 SAPPC3 SAPPC2 SAPPC1 SAPPCO STDA SRDA SCKA SC2A SC1A SCOA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BBPPCR BBP Port Control Register X FFAF Bitib 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O 5 PEN BBPPC5 BBPPC4 BBPPC3 BBPPC2 BBPPC1 BBPPCO STDB SRDB SCKB SC2B SC1B SCOB RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 13 SAP BBP PCR Description Name Description Settings PEN Port Enable Setting this bit enables all SAP or O All pins tri stated Bit 7 BBP pins to function as defined by all other 1 All pins function as configured register settings When PEN is cleared all port pins are tri stated SAPPC 5 0 Pin Configuration Each bit determines 0 GPIO default BBPPC 5 0 whether its associated pin functions as a 1 SAP or BBP Bits 5 0 peripheral SAP or BBP or GPIO Motorola Serial Audio and Baseband Ports 14 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers 14 26 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 15 JTAG Port The DSP56652 includes two Joint Test Action Group JTAG Test Access Port TAP controllers that are compatible with the JEEE 1149 1 Standard Test Access Port and Boundary
494. round PIN False Deasserted Voc PIN True Asserted Voc PIN False Deasserted Ground 1 Ground is an acceptable low voltage level See the appropriate data sheet for the range of acceptable low voltage levels typically a TTL logic low 2 Vcc is an acceptable high voltage level See the appropriate data sheet for the range of acceptable high voltage levels typically a TTL logic high Documentation This manual DSP56652UM D is one of a set of five documents that provides complete product information for the DSP56652 The other four documents include the following e M CORE Reference Manual MCORERM AD e MMC2001 Reference Manual MMC2001M AD e DSP56600 Family Manual DSP56600FM AD e DSP56652 Technical Data Sheet DSP56652 D XXiv DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 1 Introduction Motorola designed the ROM based DSP56652 to support the rigorous demands of the cellular subscriber market The high level of on chip integration in the DSP56652 minimizes application system design complexity and component count resulting in very compact implementations This integration also yields very low power consumption and cost effective system performance The DSP56652 chip combines Motorola s 32 bit MeCORE MicroRISC Engine and the DSP56600 Digital Signal Processor DSP core with on chip memory a protocol timer and custom p
495. rror flag In the event of a receiver overrun the receiver can deassert the CTS signal to turn off the far end transmitter The receiver is enabled by setting the RxEN bit in UCRI 11 2 3 Clock Generator The clock generator provides a 16x clock signal for the transmitter and receiver The input can be either CKIH or an external clock SCLK applied to the INT7 DTR pin depending on the state of the CLKSRC bit in UART Control Register 2 UCR2 CKIH is divided by a 12 bit value written in the UART Bit Rate Generator Register UBRGR 11 2 4 Infrared Interface The Infrared Interface converts data to be transmitted or received as specified in the IrDA Serial Infrared Physical Layer Specification Each zero driven on the TxD pin is a narrow logic high pulse 3 16 of a bit time in duration each one is a full logic low The receiver in kind interprets a narrow pulse on RxD as a zero and no pulse as a one External circuitry is required to drive an infrared LED with TxD and to convert received infrared signals to electrical signals for RxD The Infrared Interface is enabled by setting the IREN bit in UCRI 11 2 5 UART Pins The DSP56652 provides pins for RTS CTS TxD and RxD The remaining UART signals can be implemented with GPIO pins Suggested GPIO pin allocations are listed in Table 11 1 but any GPIO pins can be used Table 11 1 Suggested GPIO Pins for UART Signals UART Signal Suggested Pin
496. rrupt autovectored fast interrupt or vectored fast interrupt Figure 7 2 illustrates the priority mechanism in flowchart format Evaluate Once Per Clock Highest Priority Interrupt Pending Yes Assert Fast Interrupt and Supply Vector Number Fast Assert Fast Interrupt and Interrupt Pending Autovector Normal Assert Normal Interrupt and Interrupt Pending Autovector No Interrupts Pending Figure 7 2 Hardware Priority Flowchart 7 1 3 Enabling MCU Interrupt Sources Three steps are required to enable MCU interrupt sources 1 Assign each interrupt to either normal or fast processing and set the appropriate bits in the NIER or FIER Each interrupt source can be assigned to either of two interrupt request inputs normal or fast Fast requests are serviced before normal requests there is no difference in latency Motorola Interrupts For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Interrupt Controller The choice of interrupt request for each source depends on several factors driven by the end application including Rate of service requests e Latency requirements e Access to the alternate register bank Length of service routine e Total number of interrupt sources in the system Each interrupt source is enabled as a normal or fast interrupt by setting the appropriate bit in either the NIER or FIER The enable bit s
497. rst opcode of non active table end of macro 7D Last macro event delay 7E Activate delay nop 7F No operation Macros can only be called from the frame tables The negate assert_Tout events are the only events that affect external pins Can be activated only from frame table Boo m Can be activated only from macro table 10 4 PT Registers Table 10 5 is a summary of the 19 user programmable PT control and GPIO registers including the acronym bit names and address least significant halfword of each register The most significant halfword of all register addresses is 0020 Table 10 5 Protocol Timer Register Summary PTCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3800 RSCE CFCE HLTR SPBP TDZD MTER TIME TE PTIER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3802 Pes THe Ove ose ana ezo T Fsweeeg cre PTSR 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 3804 loas oT E a ener PTEVR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 seso T TL LE E ME ME EP EE Tr TXMABXMA ACT Motorola Protocol Timer 10 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers TIMR 15 14 13 12 11 8 7 6 5 4 3 2 1 0 3808 er gt CTIC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 880 AB CTIMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 380C M _____ CFC 14 8 7 6 5 4 3 2 1 0 11 380E A oom CF
498. rt D data Register old name Protocol Timer Port Data Register NEW NAME Frame tables pointers Receive Transmit Macro tables pointers old name Macro table pointers NEW NAME Frame tables base address register Rx Tx Macro tables base address register old name Macro table base address register NEW NAME Delay tables pointers Timer Timer timer timer timer timer the Timer Control Register TCTR old names 0x0 0x1 0x2 0x3 0x4 0x5 0x8 0x9 timer enable bit timer immidiate enable bit macro termination bit Timer doze disable slot prescaler by pass bit halt request bit cfc counter enable bit rsc counter enable bit the Protocol Timer Control Register PICR NEW NAMES 0x0 timer enable bit 0x1 timer immidiate enable bit Equates and Header Files B 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Equates equ prot ptcr mter 0x2 macro termination bit equ prot ptcr tdzd 0x3 Timer doze disable equ prot ptcr spbp 0x4 slot prescaler by pass bit equ prot ptcr hltr 0x5 halt request bit equ prot ptcr cfce 0x8 cfc counter enable bit equ prot ptcr rsce 0x9 rsc counter enable bit bits of the Timer Interrupt Enable Register TIER old names equ prot ptier cfie 0x0 channel frame interrupt enable bit equ prot ptier cfnie 0x1 channel frame number intpt enable
499. rt Status Register Address 0020 5F10 0 Queue 0 is not active Reset 0000 1 Queue 0 is active Read Write HALTA Description QA2 Description 0 QSPI has not halted 0 Queue 2 is not active 1 QSP has halted 1 Queue 2 is active TRC Description 0 Trigger collision has not occurred GAS Description 1 Trigger collision has occurred 0 Queue 3 is not active 1 Queue 3 is active QPWF Description 0 Queue pointer has not wrapped around QXO Description 1 Queue pointer has wrapped around 0 Queue 0 is not executing EOT3 Description 1 Queue 0 is executing 0 Queue 3 transfer not complete axi Description 1 Queue 3 transfer complete 0 Queue 1 is not executing EOT2 Description 1 Queue 1 is executing 0 Queue 2 transfer not complete 1 Queue 2 transfer complete Qx2 Description 0 Queue 2 is not executing EOT1 Description 1 Queue 2 is executing 0 Queue 1 transfer not complete 1 Queue 1 transfer complete QX3 Description i EOTO Description 0 Queue 3 is not executing f 0 Queue 0 transfer not complete 1 Queue 3 is executing 1 Queue 0 transfer complete RES m 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QX3 QX2 QX1 QXO QA3 QA2 QA1 QAO HALTA TRC QPWF EOT3 EOT2 EOT1 EOTO 0 Reserved E 42 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programmer QSPI SCCRO Serial Channel Control Registe
500. rts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and 4i are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer All other tradenames trademarks and registered trademarks are the property of their respective owners For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Preface Chapter 1 Introduction Ll DSP56052 Key Peatures core oz E 5 A E SESS 1 1 M2 Architect re OVED VIEW 4c La ete e e e at 1 4 1 2 1 MCU caduta A e ESA TE
501. rupt Set when O CFNI has not occurred default Bit 1 the CFC decrements to zero 1 CFNI has occurred CFI Channel Frame Interrupt Set when the CTIC O CFI has not occurred default Bit 0 decrements to zero 1 CFI has occurred 10 20 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Registers PTEVR Protocol Timer Event Register 0020_3806 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 THIP TXMA RXMA ACT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTEVR is a read only register Table 10 10 PTEVR Description Name Description Settings THIP Timer Halt in Process Indicates if the PT is in O Normal mode default Bit 3 the process of halting 1 Halt mode in progress TxMA Transmit Macro Active 0 Not active default Bit 2 1 Active RxMA Receive Macro Active 0 Not active default Bit 1 1 Active ACT Active Frame Table O Frame table 0 active default BitO 1 Frame table 1 active TIMR Time Interval Modulus Register 0020_3808 Biti5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 TIMV 8 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 11 TIMR Description Name Description TIMV Time Interval Modulus Value This field contains the value loaded into CTIG when it rolls over Bits 8 0 When TIMV n the PT r
502. rviced Table 7 7 shows the relative priority order of the DSP interrupts Priority level 3 is the highest and O the lowest Level 3 vectors cannot change their priority level but all other vectors can be assigned a level of 0 1 or 2 The table lists these vectors in their relative priority if they are assigned the same priority level 7 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP Interrupt Controller IRQA D are wired internally as shown in Figure 7 3 IRQA is the DSP wake from stop interrupt and is wire ORed to the other three interrupts because they are all intended to wake the DSP as well IRQA should be disabled by clearing IPRC bits 10 9 DSP_IRQ Pin MDI Wake From STOP Protocol Timer Synchronization Logi IRQGA IRQB IRQC IRQD DSP Core Figure 7 3 Internal IRQA D Connection Table 7 6 DSP Interrupt Sources Au IPL Interrupt Source Ris IPL Interrupt Source 00 3 Reserved 40 0 2 SAP Receive Data 02 3 Stack Error 42 0 2 SAP Receive Data With Overrun Error 04 3 Illegal Instruction 44 0 2 SAP Receive Last Slot 06 3 Debug Request Interrupt 46 0 2 SAP Transmit Data 08 3 Trap 48 0 2 SAP Transmit Data with Underrun Error 0A 0E 3 Reserved 4A 0 2 SAP Transmit Last Slot 10 0 RQA 4C 0 2 SAP Timer Counter Rollover 12
503. ry Maps This section describes the internal memory map of the DSP36652 The memory maps for MCU and DSP are described separately 3 1 MCU Memory Map The MCU side of the DSP56652 has a single contiguous memory space with four separate partitions e Internal ROM e Internal RAM e Memory mapped peripherals e External memory space These spaces are shown in Figure 3 1 on page 3 2 3 1 1 ROM The MCU memory map allocates 1 Mbyte for internal ROM The actual ROM size is 16 kbytes starting at address 0000 0000 and is modulo mapped into the remainder of the 1 Mbyte space Read access to internal ROM space returns the transfer acknowledge TA signal except in user mode while supervisor protection is active in which case a transfer error acknowledge signal TEA is returned resulting in termination and an access error exception Any attempt to write to the MCU ROM space also returns TEA Software should not rely on modulo mapping because future DSP5665x chip implementations may behave differently Motorola Memory Maps 3 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Memory Map Base Address FFFF_FFFF 4500_0000 Reserved 4400_0000 4300_0000 4600_0000 4200_0000 External Memory 6 x 16 Mbytes Allocated 4100_0000 6 x 4 Mbytes Addressable 4000_0000 4000_0000 Reserved 0020_D000 G Port Control z ee oe 0020_CC00 Emulation Port Control 0020 C800
504. s data communication and auto power down circuitry Motorola Smart Card Port 12 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCP Architecture 12 1 1 SCP Pins The SCP provides the following five pins to connect to a smart card e SIMDATA a bidirectional pin on which transmit and receive data are multiplexed e SIMCLK an output providing the clock signal to the smart card e SENSE an input indicating if a smart card is inserted in the interface e SIMRESET an output that resets the smart card logic e PWR_EN an output that enables an external power supply for the smart card The five pins can function as GPIO if the SCP function is not required Because SCP operation requires all five pins they cannot be configured for GPIO individually 12 1 2 Data Communication The SCP contains a quad buffered receiver FIFO and a double buffered transmitter A single register serves both as a write buffer for transmitted data and a read buffer for received data Reading the register clears an entry in the receive FIFO and writing the register enters a new character to be transmitted Three flags and optional interrupts are provided for FIFO not empty FIFO full and FIFO overflow The transmitter provides two flags and optional interrupts for character transmitted and TX buffer empty The SCP employs an asynchronous serial protocol containing one start bit eight data bits a par
505. s each programmer s sheet the register described in the sheet and the page in this appendix where the sheet is located Table E 1 List of Programmer s Sheets Register Functional Block 4 Page Acronym Name MCU Configuration RSR Reset Source Register E 6 CKCTL Clock Control Register E 6 GPCR General Port Control Register E 7 DSP Configuration PCTLO PLL Control Register O E 8 PCTL1 PLL Control Register 1 E 8 OMR Operating Mode Register E 9 PATCH Patch Registers E 10 MDI MCR MCU Side Control Register E 11 MCVR MCU Side Command Vector Register E 11 MSR MCU Side Status Register E 12 MRRO MCU Receive Register O E 13 MRR1 MCU Receive Register 1 E 13 MTRO MCU Transmit Register 0 E 13 MTR1 MCU Transmit Register 1 E 13 DCR DSP Side Control Register E 14 DSR DSP Side Status Register E 15 DRRO DSP Receive Register 0 E 16 DRR1 DSP Receive Register1 E 16 DTRO DSP Transmit Register O E 16 DTR1 DSP Transmit Register 1 E 16 Motorola Programmer s Data Sheets E 1 For More Information On This Product Go to www freescale com E 2 Freescale Semiconductor Inc Table E 1 List of Programmer s Sheets Continued
506. s fully active in all low power modes except STOP Each processor can enter and exit a low power mode independently The processor state is unchanged by a transition to and from a low power mode status and control registers do not return to default values Motorola MCU DSP Interface 5 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Low Power Modes 5 3 1 MCU Low Power Modes Various DSP events can awaken the MCU from a low power mode WAIT DOZE or STOP by generating a corresponding interrupt Table 5 3 lists the events and the associated interrupt enable bits in the MCR Table 5 3 MCU Wake up Events Event Interrupt Enable Bit in MCR Transmitting a message to MRRO 15 MRIEO Transmitting a message to MRR1 14 MRIE1 Receiving a message from MTRO 13 MTIEO Receiving a message from MTR1 12 MTIE1 Setting the DGIRO bit in the DSR General Interrupt request 0 11 MGIEO Setting the DGIR1 bit in the DSR General Interrupt request 1 10 MGIE1 The software designer should consider the following points before placing the MCU in STOP mode 1 Compatibility with DSP STOP mode protocol MCU software should accommodate the possibility that the DSP is in STOP when the MCU awakens from its STOP mode 2 Pending shared memory writes A shared memory write that has not completed when the MCU enters STOP mode will execute reliably after the MCU has awakened
507. s read only register reflects the value of the PWM counter PWCNT Motorola Timers 9 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM 9 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 10 Protocol Timer The Protocol Timer PT serves as the control module for all radio channel timing It relieves the MCU from the event scheduling associated with radio communication protocol so that software need only reprogram the PT once per frame or less The events the PT can generate include the following e QSPI triggers can be used to program external devices that have SPI ports e External events driven on the PT pins TOUT 7 0 can be used to control external devices e MCU and DSP interrupts can be used in a variety of ways for example to alert the cores to prepare for a change to a different channel or slot e Transmit and Receive Macros with programmable delays generate repeating event sequences with a single event call A transmit and receive macro can run simultaneously Control events governing PT operation and synchronization Each of these events can be represented by an event code in the protocol timer s event table Each entry that contains an event code is paired with a Time Interval Count TIC value The entries are written in order of decreasing TIC value As the v
508. sabled Timer 1 Input Capture interrupt enabled Description Interrupt disabled Timer 4 Output Compare interrupt enabled Description Interrupt disabled Timer 3 Output Compare interrupt enabled Description Interrupt disabled Timer 1 Output Compare interrupt enabled IF1IE 0 TPWIR Timers and PWM Interrupt Register Address 0020_6006 Reset 0000 Read Write OF4IE 0 IF2IE Description 1 0 Interrupt disabled 1 Timer 2 Input Capture interrupt enabled OFSIE PWFIE Description 9 0 Interrupt disabled 1 PWM Output Compare interrupt enabled OF1IE TOVIE Description 0 0 Interrupt disabled n 1 1 TCNT overflow interrupt enabled PWOIE Description 0 Interrupt disabled 1 PWCNT rollover interrupt enabled 01 15 8 7 6 5 4 3 2 1 0 Reserved Motorola Programmer s Data Sheets E 55 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer TOCR1 PWM Timer 1 TO CR Register Address 0020_6008 Reset 0000 Read Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data data data data data data data data data data data data data data data data TOCR3 Timer 3 Output Compare Registe
509. scale Semiconductor Inc I O Multiplexing GPC2 COLUMNG GPIO OC1 COLUMN6 s GPC3 COLUMN7 GPIO PWM COLUMN7 s GPC4 SCK UART INT6 DSR GPIO ROW5 GPIO IC2B ROW5 MUX CTL STDA GPIO INT7 DTR GPIO INT6 Y Y MUX_CTL SRDA GPIO ROW6 DCD GPIO INT7 TMS MUX_CTL SC2A GPIO ROW7 RI GPIO ROW6 gJ Cc ie U m MUX_CTL SCKA GPIO IC1 ROW7 TCK MUX_CTL TX GPIO GPC7 Tx 2 TDO IC2 Input MCU Timer MUX CTL Rx GPIO T TDI MUX CTL RTS S RESET IN MUX CTL CTS GPIO 1 MCU DE Figure 4 4 MUX Connectivity Scheme Motorola Core Operation and Configuration 4 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc I O Multiplexing GPCR General Port Control Register 0020 CCOO Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 STO GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPCO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 13 GPCR Description Name Description Settings STO Soft Turn Off The value written to this bit is reflected on the STO pin This bit is not affected by reset Bit 15 or the state of the MUX CTL pin GPC7 General Port Control for E11 determines if pin E11 RTS default Bit 7 functions as the UART RTS signal or t
510. sed to time event generation The OC1 pin can be forced to its compare value at any time by setting FOI in the TPWMR The action taken as a result of a forced compare is the same as when an output compare match occurs except that status flags are not set OC3 and OC4 also have forcing bits but they have no effect because the functions are not pinned out 9 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM 9 3 2 Pulse Width Modulator The pulse width modulator PWM uses a 16 bit free running counter PWCNT to generate an output pulse on the PWM pin with a specific period and frequency 9 3 2 1 PWM Operation The PWM uses the following registers TPWCR The PWM Control Register enables the PWM selects the PVCNT clock frequency and determines PWM operation in Debug and DOZE modes e TPWMR The PWM Mode Register connects the PWM function to the PWM output pin and determines the output polarity e TPWSR The PWM Status Register contains flag bits indicating pulse assertion PWCNT PWOR and deassertion PWCNT rolls over e TPWIR The PWM Interrupt Register enables interrupts for each edge of the pulse e PWOR The PWM Output Compare Register contains the PWCNT value that initiates the pulse e PWMR The PWM Modulus Register contains the value loaded into PWCNT when it rolls over This value determines the pulse period
511. selects a fast interrupt source to elevate to the highest priority and specifies the vector to be used to service the interrupt Only word writes will update the ICR Byte or half word writes will terminate normally but will not update the register Table 7 5 ICR Description Name Description Settings EN Enable Highest Priority Interrupt Hardware O Priority hardware disabled default Bit 15 1 Priority hardware enabled Bits 11 7 Source Number Bit position of source to raise to the highest priority Bits 6 0 Vector Number Vector number to supply when highest priority interrupt is pending Refer to the M CORE Reference Manual for the appropriate vector number 7 2 DSP Interrupt Controller The interrupt controller on the DSP side of the DSP36652 is based on the 56600 core Its operation is described in Section 7 3 of the DSP56600 Family Manual 7 2 1 DSP Interrupt Sources Table 7 6 on page 7 11 lists all of the DSP interrupt sources according to their interrupt vectors The vectors are offsets from the program address written to the Vector Base Address VBA register in the program control unit If more than one interrupt request is pending when an instruction is executed the interrupt source with the highest priority level is serviced first When multiple interrupt requests having the same IPL are pending a second fixed priority structure within that IPL determines which interrupt source is se
512. set page 6 10 This during these EDA CSA idle cycles will ensures that all internal transfers can be externally not be visible externally monitored although this setting can impact 10 Show cycles enabled Internal performance termination to the MCU during idle cycles caused by EDC or CSA being set is delayed by one cycle This ensures that all internal transfers can be externally monitored at the expense of performance 11 Reserved 6 12 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ElM Registers EMDDR Emulation Port Data Direction Register 0020_C800 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO EMDD5 EMDD4 EMDD3 EMDD2 EMDD1 EMDDO PSTAT3 PSTAT2 PSTAT1 PSTATO SIZ1 SIZO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6 8 QDDR Description Name Description Settings EMDD 5 0 Emulation Port Data Direction 5 0 determines O Input default Bits 7 0 whether each pin functions as an input or an output when 1 Output the port functions as GPIO Emulation Port is disabled EMDR Emulation Port Data Register 0020_C802 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO EMD5 EMD4 EMD3 EMD2 EMD1 EMDO PSTAT3 PSTAT2 PSTAT1 PSTATO SIZ1 SIZO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ta
513. shift DR controller states Note When this signal is enabled the primary TDO signal is disconnected from the TAP controller See Table 2 19 on page 2 19 Normal MUX RxD IC1 TDI CTL driven low Input or Input Output UART Receive This signal receives data into the UART Input MCU Timer Input Capture 1 The signal connects to an input capture output compare timer used for autobaud mode support Alternate MUX CTL dri ven high Input Input Test Data In alternate This signal provides the TDI serial input for test instructions and data for the JTAG TAP controller TDI is sampled on the rising edge of TCK Note When this signal is enabled the primary TDI signal is disconnected from the TAP controller See Table 2 19 on page 2 19 Motorola Signal Connection Description 2 13 For More Information On This Product Go to www freescale com UART Freescale Semiconductor Inc Table 2 12 UART Signals Continued Signal Name Type Reset State Signal Description Normal MUX CTL driven low RTS IC2 Input or Output Input Input Request To Send This signal functions as the UART RTS signal MCU Timer Input Capture 2 This signal connects to an input capture timer channel Alternate MU X CTL driven high RESET IN Input Input Reset Input This signal is an act
514. sociated IM 1 0 bits in the TPWMR When the programmed edge transition occurs on an input capture pin the associated TICR captures the content of TCNT and sets an associated flag bit IF1 2 in the TPWSR If the associated interrupt enable bit IFIE1 2 in TPWIR has been set an interrupt request is also generated when the transition is detected Input capture events are asynchronous to the GP timer counter so they are conditioned by a synchronizer and a digital filter The events are synchronized with MCU CLK so that TCNT is latched on the opposite half cycle of MCU CLK from TCNT increment An input transition shorter than one MCU CLK period has no effect A transition longer than two MCU_CLK periods is guaranteed to be captured with a maximum uncertainty of one MCU_CLK cycle TICR1 and 2 can be read at any time without affecting their values Both input capture registers retain their values during STOP and DOZE modes and when the GP timer is disabled TE bit cleared 9 3 1 1 2 Output Compare Each output compare channel has an associated compare register TOCR 1 3 4 When TCNT equals the 16 bit value in a compare register a status flag OCF1 3 4 in TPWSR is set If the associated interrupt enable bit OCIE1 3 4 in TPWIR has been set an interrupt is generated OCI can also set clear or toggle the OC1 output pin depending on the state of OMI 1 0 in the TPWMR OC3 and OC4 are not pinned out but their flags and interrupt enables can be u
515. st If the EXTEST instruction were used for this purpose the boundary scan register would be selected and the required guarding signals would be loaded as part of the complete serial data stream shifted in both at the start of the test and each time a new test pattern is entered The CLAMP instruction results in substantially faster testing than the EXTEST instruction because it allows guarding values to be applied using the BSR of the appropriate ICs while selecting their bypass registers Data in the boundary scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its reset state The 15 8 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56600 Core JTAG Operation CLAMP instruction also asserts internal reset for the DSP36632 core system logic to force a predictable internal state while performing external boundary scan operations 15 1 3 2 7 ENABLE DSP ONCE B 3 0 0110 The ENABLE DSP ONCE instruction is not included in the IEEE 1149 1 standard It is provided as a public instruction to allow the user to perform system debug functions When the ENABLE DSP ONCE instruction is decoded the TDI and TDO pins are connected directly to the DSP OnCE registers The particular DSP OnCE register connected between TDI and TDO at a given time is selected by the DSP OnCE controller depending on the DSP OnCE instruction being c
516. st pending equ pic control Bits in the PIC registers equ pic swO equ pic sw equ pic sw equ pic int0 equ pic intl equ pic int2 equ pic int3 equ pic int4 equ pic int5 equ pic int6 equ pic int7 equ pic urts equ pic kpd o RR A gt 09 B 20 0x0 0x2 0x3 0x4 0x5 0x6 0x00200000 0x0 0x4 0x8 Oxc 0x10 0x14 0x0 0x1 0x2 0x5 0x6 0x7 0x8 0x9 Oxa Oxb Oxc Oxd Oxe DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc equ pic pit equ pic_tpw equ pic sim equ pic mii equ pic qspi equ pic prot equ pic proto equ pic protl equ pic prot2 equ pic utx equ pic smpdint equ pic smd equ pic urx Watchdog Timer equ wdt base address equ wdt wer equ wit wsr Periodic Interrupt Timer equ pit base address equ pit itcsr equ pit itdr equ pit itadr equ pit pitcsr equ pit pitml equ pit pitcnt PSR bits equ psr tc equ psr sc equ psr m equ psr ee equ psr ic equ psr ie equ psr fe equ psr af equ psrc Motorola For More Information On This Product Go to www freescale com 0x10 0x11 0x16 0x17 0x18 0x19 Oxla Ox1b Oxlc Oxld 0x13 old name 0x13 NEW NAME Ox1f 0x00208000 0x0 0x2 0x00207000 0x0 old names 0x2 0x4 0x0 NEW NAMES 0x2 0x4 Oxc
517. t CFPR value bit CFPR value bit Wo 00 JD UH UN S cfml value bit 1 cfml value bit 2 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc MCU Equates equ prot cfml cfw 2 0x2 cfml value bit 3 equ prot cfml cfw 3 0x3 cfml value bit 4 equ prot cfml cfw 4 0x4 cfml value bit 5 equ prot cfml cfmv 5 0x5 cfml value bit 6 equ prot cfml cfnuv 6 0x6 cfml value bit 7 equ prot cfml cfw 7 0x7 cfml value bit 8 equ prot cfml cfnv 8 0x8 cfml value bit 9 bits of the Reference Slot Counter RSC equ prot rsc rscv 0 0x0 RSC value bit 0 equ prot rsc rscv 1 0x1 RSC value bit 1 equ prot rsc rscv 2 Ox2 RSC value bit 2 equ prot rsc rscv 3 0x3 RSC value bit 3 equ prot rsc rscv 4 Ox4 RSC value bit 4 equ prot rsc rscv 5 0x5 RSC value bit 5 equ prot rsc rscv 6 0x6 RSC value bit 6 equ prot rsc rscv 7 0x7 RSC value bit 7 bits of the Reference Slot Preload Register RSPR old names equ prot rspr rspv 0 0x0 RSPR value bit 0 equ prot rspr rspv 1 0x1 RSPR value bit 1 equ prot rspr rspv 2 0x2 RSPR value bit 2 equ prot rspr rspv 3 0x3 RSPR value bit 3 equ prot rspr rspv 4 Ox4 RSPR value bit 4 equ prot rspr rspv 5 0x5 RSPR value bit 5 equ prot rspr rspv 6 0x6 RSPR value bit 6 equ prot rspr rspv 7 0x7 RSPR value bit 7 bits of the Reference Slot Modulus Register RSMR
518. t Go to www freescale com Freescale Semiconductor Inc Boundary Scan Description Language 22 BC 1 control 1 amp 23 BC 6 INT 5 bidir X 22 1 2 amp 24 BC 1 control 1 amp 25 BC 6 INT 4 bidir X 24 1 2Z amp 26 BC 1 control 1 amp 27 BC 6 INT 3 bidir X 26 1 2 amp 28 BC 1 control 1 amp 29 BC 6 INT 2 bidir X 28 1 2 8 30 BC 1 control 1 amp 31 BC 6 INT 1 bidir X 30 1 Z amp 32 BC 1 control 1 amp 33 BC 6 INT 0 bidir X 32 1 2Z amp 34 BC 1 control 1 amp 35 BC 6 COLUMN 7 bidir xX 34 1 Z amp 36 BC 1 control 1 amp 37 BC 6 COLUMN 6 bidir X 36 1l Z amp 38 BC 1 control 1 amp 39 BC 6 COLUMMN 5 bidir X 38 1l Z amp num cell port func safe ccell dis rslt 40 BC 1 control 1 amp 41 BC 6 COLUMN 4 bidir xX 40 1l Z amp 42 BC 1 control 1 amp 43 BC 6 COLUMN 3 bidir X 42 1l Z amp 44 BC 1 control 1 amp 45 BC 6 COLUMN 2 bidir X 44 1l Z amp 46 BC 1 control 1 amp 47 BC 6 COLUMN 1 bidir X 46 1l Z amp 48 BC 1 control 1 amp 49 BC 6 COLUMN 0 bidir X 48 1l Z amp 50 BC 1 STO output2 X amp 51 BC 1 RESET IN B input 0 amp 52 BC 1 RESET OUT B output2 X amp amp amp
519. t 8 SHFD Shift Direction Determines if data is sent and O MSB first default Bit 7 received MSB first or LSB first 1 LSB first CKP Clock Polarity Determines the bit clock edge 0 Transmit bit clock rising edge Bit 6 on which frame sync is asserted and data is Receive bit clock falling edge default shifted 1 Transmit bit clock falling edge Receive bit clock rising edge SCKD Serial Clock Pin Direction Determines if the O Input default Bit 5 SCKx pin is an output or an input 1 Output SCD2 Serial Control Pin 2 Direction Determines if O Input default Bit 4 the SC2x pin is an output or an input 1 Output SCD1 Serial Control Pin 1 Direction Determines if O Input default Bit 3 the SC1x pin is an output or an input 1 Output SCDO Serial Control Pin 0 Direction Determines if O Input default Bit 2 the SCOx pin is an output or an input 1 Output MOD Normal Network Mode Select 0 Normal mode default Bit 1 1 Network mode SYN Synchronous Asynchronous Select O Asynchronous mode default BitO 1 Synchronous mode Motorola Serial Audio and Baseband Ports 14 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SAP and BBP Control Registers SAPSR SAP Status Register A X FFB9 BBPSR BBP Status Register A X FFA9 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O RDF TDE ROE TUE RFS TFS 1F1 IFO RESET 0 0 0 0 0 0 0 0 0 1 0 0 0 0
520. t Ata obs a aia boo HZS ART Pins 427d Ere ea EE RE SEA C EISE Ea ER NE es 11 2 6 Frame Configuration 5 05 eR ERE es54ee5aes ABUSE US UART Operator d od Rt eb d abet eise diei A 11 3 1 TEABSIHILSSEOIN A ec ure a SAM Ple aie S AES ia Ere REN a Cx IL32 JRegepuon 42 26 ea rn ae SR S A er 11 3 3 Uo ellos PR Tp 11 3 4 Baud Rate Detection Autobaud o 11 3 5 Low Power MOdGS 4 s 4 3 dne Eh AAA AA GR Motorola Table of Contents Freescale Semiconductor Inc For More Information On This Product Go to www freescale com vii Freescale Semiconductor Inc TL36 Debug Mode sar SAA PE AERE 11 7 LL MARE ERGPISIeES 41 pa ada vel Uwe Mica tuts need poll ad ict DA pde le 11 8 11 4 1 UART Control Registers i5 2 S x ore e reas 11 9 LVAD GPIO Registers ose A E RENE AAA A AES 11 16 Chapter 12 Smart Card Port 1221 TSCP Architect re A a uc atio DC tat da apm ect deduce aii 12 1 12 1 1 SCP DIIS Creed EF NIES DRESSER E E CREUSE ESTER Pu ue TUE 12 2 121 2 Data Communication lt a ita ende oue We RD IVA da 12 2 12 13 Power UP DOWN 20 453 vesee iR RE exe SA NE sue ba S 12 3 12 2 SCP Operation z eranan o AA 12 3 12 2 1 Activation Deactivation Control oooooooooooooooooo o o 12 3 12 7 Clock enero pa reee CES A ENSURE pr t e S dante 12 4 12 2 3 Data Transactions seriei V hehe ON ok EE MEN ES 12 5 TAZA gt Low Power Modes a c E o gee eg ea de la ac rm 12 8 12 2 5 JHtertUDIS ces se ERR SENA ENS E
521. t control register 2 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 2 11 Keypad Port Keypad Port Signals Continued Signal Name Type Reset State Signal Description Normal MUX CTL driven low ROW6 SC2A g Ul Input or Output Input Input or Output Output Row Sense 6 This signal functions as a keypad row sense Audio Codec Serial Control 2 alternate This signal provides I O frame synchronization for the serial audio codec port In synchronous mode the signal provides the frame sync for both the transmitter and receiver In asynchronous mode the signal provides the frame sync for the transmitter only Note When this signal is used as SC2A the primary SC2A signal is disabled See Table 2 15 on page 2 16 Data Carrier Detect This signal can be used as the DCD output for the serial data port See Table 2 12 on page 2 13 Note Programming of these functions is done through the general port control register and the SAP control register Alternate MU X CTL driven high DSP DE Input or Output Input Digital Signal Processor Debug Event This signal functions as DSP DE In normal operation DSP DE is an input that provides a means to enter the debug mode of operation from an external command converter When the DSP enters the debug
522. t is the highest priority active queue Each of these bits can be set or cleared independently of the others HLTIE HALTA Interrupt Enable Enables an interrupt when O Interrupt disabled default Bit 6 the HALTA status flag in the SPSR asserted 1 Interrupt enabled TRCIE Trigger Collision Interrupt Enable Enables an O Interrupt disabled default Bit 5 interrupt when the TRC status flag in the SPSR is 1 Interrupt enabled asserted WIE Wraparound Interrupt Enable Enables an interrupt O Interrupt disabled default Bit 4 when the QPWF status flag in the SPSR is asserted 1 Interrupt enabled TACE Trigger Accumulation Enable Enables trigger 0 Trigger accumulation is disabled Bit 3 accumulation for Queue 1 The trigger count is contained and the TRCNT1 field is cleared in the TRCNT1 field in QCR1 When TACE is set a default trigger to Queue 1 increments TRCNT1 and completion 1 Trigger accumulation enabled of a Queue 1 transfer decrements TRCNT1 Note This function and the TRCNT1 field in QCR1 are available only for Queue 1 Setting or clearing the TACE bit has no effect on Queues 3 2 or 0 Motorola Queued Serial Peripheral Interface 8 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory Table 8 3 SPCR Description Continued Name Description Settings HALT Bit 2 DOZE Bit 1 Halt Re
523. t on a board when multiple sourcing is used Conforming to the IEEE 1149 1 standard in this way allows a system diagnostic controller to determine the type of component in each location through blind interrogation This information is also available for factory process monitoring and for failure mode analysis of assembled boards Motorola s Manufacturer Identity is b00000001110 The Customer Part Number consists of two parts Motorola Design Center Number bits 27 22 and a sequence number bits 15 10 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DSP56652 JTAG Port Restrictions 21 12 The sequence number is divided into two parts Core Number bits 21 17 and Chip Derivative Number bits 16 12 Motorola Semiconductor Israel MSIL Design Center Number is b000110 and DSP Core Number is b00010 Figure 15 6 shows the ID register configuration 31 28 27 22 21 17 16 12 11 1 0 Version Number Customer Part Number Manufacturer Identity Number o 0 0 00 O O 1 1 0 0 O O 1 0 0 O O O 0 0 O O O O O O 1 1 1 0 1 Design Center Number Core Number Derivative Number Figure 15 6 JTAG ID Register 15 3 DSP56652 JTAG Port Restrictions This section describes operation restrictions regarding the DSP56652 JTAG port in normal test and low power modes 15 3 1 Normal Operation JTAG transparency To ensure that the JTAG
524. ter and will not recognize BREAK characters if the RxD line is at a logic low when the receiver is enabled IREN Infrared Interface Enable Setting this bit O Normal NRZ default Bit 7 enables the IrDA infrared interface configuring 1 IrDA the RxD and TxD pins to operate as described in Section 11 2 4 on page 11 4 TXEIE Transmitter Empty Interrupt Enable Setting 0 Interrupt disabled default Bit 6 this bit enables an interrupt when all data in UTX 1 Interrupt enabled has been transmitted Note Either the EUTX bit in the NIER or the EFUTX bit in the FIER must also be set in order to generate this interrupt see page 7 7 RTSDIE RTS Delta Interrupt Enable Setting this bit 0 Interrupt disabled default Bit 5 enables an interrupt when the RTS pin changes 1 Interrupt enabled state Note Either the EURTS bit in the NIER or the EFRTS bit in the FIER must also be set in order to generate this interrupt see page 7 7 SNDBRK Send BREAK Setting this forces the transmitter O Normal transmission default Bit 4 to send BREAK characters effectively pulling the 1 BREAK characters transmitted TxD pin low until SNDBRK is cleared SNDBRK cannot be set unless TXEN and UEN are both set DOZE UART DOZE Mode 0 UART ignores DOZE mode default Bit 1 1 UART stops in DOZE mode UEN UART Enable This bit must be set to enable the O UART disabled default Bit O UART If UEN is cleared during a transmission 1
525. test logic is kept transparent to the system logic in normal operation the JTAG TAP controller must be initialized and kept in the Test Logic Reset controller state The controller can be forced into Test Logic Reset by asserting TRST externally at power up reset The controller will remain in this state as long as TMS is not driven low Connecting the TCK pin The TCK pin does not have an on board pullup resistor and should be tied to a logic high or low during normal operation 15 3 2 Test Modes Signal contention in circuit board testing The control afforded by the output enable signals using the BSR and the EXTEST instruction requires a compatible circuit board test environment to avoid device destructive configurations The user must avoid situations in which the DSP56652 output drivers are enabled into actively driven networks Executing the EXTEST instruction The EXTEST instruction can be performed only after power up or regular hardware reset while EXTAL is provided Then during the execution of EXTEST EXTAL can remain inactive 15 3 3 STOP Mode Entering STOP The TAP controller must be in the Test Logic Reset state to enter and remain in STOP mode Motorola JTAG Port 15 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU TAP Controller e Minimizing power consumption The TMS and TDI pins include on chip pullup resistors In STOP mode these two pins shoul
526. the initial state of the TOUT driver GPI Reading PTPDn reflects the pin value Writing PTPDn writes the data latch GPO Reading PTPDn reflects the data latch which equals the pin value Writing PTPDn writes the data latch which drives the pin value 10 26 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Protocol Timer Programming Example 10 5 Protocol Timer Programming Example The following lines illustrate a typical series of entries in the event table Frame Table No 0 lt abs TIC gt lt abs TIC gt lt abs TIC gt lt abs TIC gt lt abs TIC gt lt abs TIC gt trigger QSPI 0 Rx macroOStart Tx macrolstart trigger CVR5 Rx macro2start Table change Frame Table No 1 abs TIC abs TIC abs TIC abs TIC abs TIC abs TIC Rx macro2start DSP int MCU int 0 trigger QSPI 2 Tx macro3start Rx burst timing macro Tx burst timing macro Rx burst timing macro Rx burst timing macro DSP interrupt MCU interrupt Tx burst timing macro End of frame repeat Receive Macro Table rel TIC gt rel TIC gt rel TIC gt rel TIC gt rel TIC gt Assert Tout3 delay trigger QSPI 1 Negate Tout3 End of macro Transmit Macro Table rel TIC gt rel TIC gt rel TIC gt rel TIC gt rel TIC gt rel TIC gt rel TIC gt Motorola Assert_Tout6 Assert_Tout7 trigger C
527. the timer stops register read and write accesses function normally and the WDE bit one time write lock is disabled If the WDE bit is cleared while in Debug mode it will remain cleared when Debug mode is exited If the WDE bit is not cleared while in Debug mode the watchdog count will continue from its value before Debug mode was entered Motorola Timers 9 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc GP Timer and PWM 9 2 2 Watchdog Timer Registers WCR Watchdog Control Register 0020_8000 Bit15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit O WT 5 0 WDE WDBG WDZE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9 2 WCR Description Name Description Settings WT 5 0 Watchdog Timer Field These bits determine the value loaded in the watchdog counter when it is Bits 15 10 initialized and after the timer is serviced WDE Watchdog Enable Setting this bit enables the O Disabled default Bit 2 watchdog timer It can only be cleared in Debug 1 Enabled mode or by Reset WDBG Watchdog Debug Enable Determines timer 0 Continues to run in Debug mode default Bit 1 operation in Debug mode 1 Halts in Debug mode WDZE Watchdog Doze Enable Determines timer 0 Continues to run in DOZE mode default Bit 0 operation in DOZE mode 1 Halts in DOZE mode WSR Watchdog Service Register 0020 8002 Bit15 14 13 1
528. tial address of the DSP reset routine P 0800 Once the DSP exits the reset state it executes the bootloader program described in Appendix A DSP56652 DSP Bootloader Out of reset CKIL drives the DSP clock until RESET_OUT is negated when the clock source is switched to DSP_REF To ensure a stable clock the DSP is held in the reset state for 16 DSP_REF clocks after RESET_OUT is negated The PLL is disabled and the default source for DSP_REF is CKIH so the DSP_CLK frequency is equal to CKIH 2 It is recommended that clock sources be present on both the CKIH and CKIL pins However should CKIH be inactive at reset the DSP remains in reset until the MCU sets the DCS bit in the CKCTL register selecting CKIL as the DSP clock source In this case the following MCU sequence is recommended 1 Set the DHR bit 2 Set the DCS bit 3 After a minimum of 18 CKIL cycles clear the DHR bit 4 4 DSP Configuration The DSP contains an Operating Mode Register OMR to configure many of its features Four Patch Address Registers PARs allow the user to insert code corrections to ROM A Device Identification Register IDR is also provided 4 4 1 Operating Mode Register The OMR is a 16 bit read write DSP core register that controls the operating mode of the DSP56652 and provides status flags on its operation The OMR is affected only by processor reset by instructions that directly reference it for example ANDI and ORD and by instructi
529. timer trigger The content of the write is irrelevant 8 4 3 Control And Data RAM Data to be transferred reside in Data RAM and each 16 bit data halfword has a corresponding 16 bit control halfword in Control RAM with the same address offset Each data halfword control halfword pair constitutes a queue entry There are a total of 64 queue entries The values in RAM are undefined at Reset and should be explicitly programmed 8 4 3 1 Control RAM Only the 7 LSBs bits 6 0 of each 16 bit queue control halfword are used the 9 MSBs bits 15 7 of each control halfword always read O The MCU can read and write to control RAM while the QSPI has read only access Control RAM 0020_5000 to 0020_507F BIT15 14 13 12 11 10 9 8 7 6 5 4 8 2 1 BITO BYTE RE PAUSECONT PCS 2 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8 7 QSPI Control RAM Description Name Description Settings BYTE BYTE Enable This bit controls the width of transferred data O 16 bit data transferred Bit 6 halfwords When BYTE is set the QSPI transfers only the 8 1 8 bit data transferred least significant bits of the corresponding 16 bit queue entry in Data RAM If receiving is enabled a received halfword is also 8 bits The received byte is written to the least significant 8 bits of the data halfword and the most significant byte of the data halfword is filled with Os When BYTE is cleared the QSPI t
530. ting E Extension bit indicating if the integer portion is in use U Unnormalized bit indicating if the result is unnormalized N Negative bit indicating if Bit 35 or 31 of the result is set Z Zero bit indicating if the result equals O V Overflow bit indicating if arithmetic overflow has occurred in the result C Carry bit indicating if a carry or borrow occurred in the result Table D 7 Condition Code Register Notation Notation Description Bit is set or cleared according to the standard definition by the result of the operation Bit is not affected by the operation 0 Bit is always cleared by the operation 1 Bit is always set by the operation U Undefined Bit is set or cleared according to the special computation definition by the result of the operation Motorola Programmer s Reference D 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Internal I O Memory Map D 3 MCU Internal I O Memory Map Table D 8 lists the MCU I O registers in address numerical order Unlisted addresses are For More Information On This Product Go to www freescale com reserved Table D 8 MCU Internal I O Memory Map Address Register Name Reset Value Interrupts 0020_0000 ISR Interrupt Source Register 0007 0020_0004 NIER Normal Interrupt Enable Register
531. tion 0 No interrupt request 0 No meee request 1 INT7 interrupt request pending 1 INTZ interrupt roguest pending INT1 Description RIS Desedption 0 No interrupt request 0 No interrupt request 1 INT1 interrupt request pending 1 UART RTS Delta interrupt request pending INTO Description EU 0 No interrupt request KPD Description T 1 INTO interrupt request pending 0 No interrupt request 1 Keypad Interface interrupt request pending Software Interrupt Reserved E 26 DSP56652 User s Manual For More Information On This Product Go to www freescale com Motorola Freescale Semiconductor Inc Application Date Programmer MCU Interrupts Sm nio N E R 0 Interrupt source is masked 1 Protocol Timer MCUO interrupt Upper Halfword source enabled Normal Interrupt Enable Register Upper Halfword XS Address 0020 0004 EPIM DOSONDHOD Reset 0000 0 Interrupt source is masked Read Write 1 Protocol Timer interrupt source enabled EPT1 Description 0 Interrupt source is masked EQSPI Description 1 Protocol Timer MCU1 interrupt f source enabled 0 Interrupt source is masked 1 QSPI interrupt source en
532. to write to the active frame table When the protocol timer is enabled or exits the HALT state FTPTR is initialized to the first entry in frame table 0 the FTBAO field in FTBAR When the value in CTIC matches the ATIC field pointed to by FTPTR the FTEC asserts an internal Frame Hit signal to the ECU which generates the event specified by the EC field of the FTPTR entry FTPTR is then incremented The cycle repeats until one of the end_of_frame commands or the table_ change command is executed Each of these commands reinitializes FTPTR to the first entry of one of the frame tables 10 2 2 Macro Tables The protocol timer can generate a separate independent sequence of events for both a transmission burst and a receive burst Both of these sequences or macros can run concurrently with the basic frame table sequence Each of the macros occupies a partition in the event table referred to as a macro table Each macro is called as an event from the frame table In most cases the transmit and receive macro tables only need to be written at initialization providing a substantial reduction in MCU overhead Motorola Protocol Timer 10 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PT Operation Unlike frame table events which are based on the absolute value in CTIC macro events are timed relative to the previous macro event Each entry in a macro table has a 14 bit Relative TIC field and a 7
533. to www freescale com Freescale Semiconductor Inc Register Index Table D 10 Register Index Continued For More Information On This Product Go to www freescale com Register Name Peripheral Address Page PWOR PWM Output Compare Register Timers 0020_6012 9 17 QCRO Queue Control Register 0 QSPI 0020_5F08 8 15 QCR1 Queue Control Register 1 QSPI 0020 5F0A QCR2 Queue Control Register 2 QSPI 0020 5FOC QCR3 Queue Control Register 3 QSPI 0020_5FOE QDDR QSPI Data Direction Register QSPI 0020_5F02 8 25 QPCR QSPI Port Control Register QSPI 0020 5F00 8 24 QPDR QSPI Port Data Register QSPI 0020 5F04 8 25 RSC Reference Slot Counter PT 0020 3812 10 23 RSMR Reference Slot Modulus Register PT 0020 3814 10 23 RSR Reset Source Register MCU Core 0020 C400 4 11 SAPCNT SAP Timer Counter SAP X FFB4 14 17 SAPCRA SAP Control Register C SAP X FFB8 14 18 SAPCRB SAP Control Register B SAP X FFB7 14 19 SAPCRC SAP Control Register A SAP X FFB6 14 21 SAPDDR SAP GPIO Data Direction Register SAP X FFBE 14 24 SAPMR SAP Timer Modulus Register SAP X FFB5 14 17 SAPPCR SAP Port Control Register SAP X FFBF 14 25 SAPPDR SAP Port Data Register SAP X FFBD 14 24 SAPRX SAP Receive Data Register SAP X FFBA 14 23 SAPSR SAP Status Register SAP X FFB9 14 22 SAPTSR SAP Time Slot Register SAP X FFBB 14 23 SAPTX S
534. to the internal peripheral space while in User prohibited default Mode generates a TEA error This bit does not affect CSCRO 5 or EIMCR which can only be accessed in supervisor mode SPRAM Supervisor Protect Internal RAM Prohibits User O User Mode access to internal RAM Bit 4 Mode access to internal RAM When SPRAM is allowed set a read or write to the internal RAM while in 1 User Mode access to internal RAM User Mode generates a TEA error prohibited default SPROM Supervisor Protect Internal ROM Prohibits User O User Mode access to internal ROM Bit 3 Mode access to internal ROM When SPROM is allowed set a read or write to the internal ROM while in 1 User Mode access to internal ROM User Mode generates a TEA error prohibited default HDB High Data Bus selects the internal halfword to be O Lower halfword D 15 0 default Bit 2 placed on the external data bus during a Show 1 Upper halfword D 31 16 Cycle This bit is ignored when SHEN 1 0 are cleared SHEN 1 0 Show Cycle Enable These bits enable the 00 Show cycles disabled default Bits 1 0 internal buses to be reflected on the external buses 01 Show cycles enabled Internal during accesses to internal RAM ROM or termination to the MCU during idle cycles peripherals They can also delay internal caused by EDC or CSA being set is not termination to the MCU during idle cycles caused delayed and internal transfers that occur by EDC or CSA being
535. torola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Equates equ kpp kpcr 0x0 Port Control Register equ kpp kpsr Ox2 Port Status Register equ kpp kddr 0x4 Data direction Register equ kpp kpdr 0x6 Data value Register Subscriber Interface Module SmartCard Port old names equ scp base address 0x0020b000 Module Base Address equ scp siwr 0x0 SIM Control Register equ scp siacr 0x2 SIM Activation Control Register equ scp siicr 0x4 SIM Interrupt Control Register equ scp simsr 0x6 SIM Status Register equ scp simdr 0x8 SIM Tx and Rx Data Register equ scp sipcr Oxa SIM Pins Control Register NEW NAMES equ scp base address 0x0020b000 Module Base Address equ scp scpcr 0x0 SCP Control Register equ scp scacr 0x2 SCP Activation Control Register equ scp scpier 0x4 SCP Interrupt Control Register equ scp scpsr 0x6 SCP Status Register equ scp scpdr 0x8 SCP Tx and Rx Data Register equ scp scppcr Oxa SCP Pins Control Register External Interrupts equ wext base address 0x00209000 Module Base Address equ wext eppar 0x0 Edge Port Pin Assignment Register equ wext epddr 0x2 Edge Port Data Direction Register equ wext epdr 0x4 Edge Port Data Register equ wext epfr Ox6 Edge Port Flag Register EM equ eim registers base address 0x00201000 4 eim base
536. torola Queued Serial Peripheral Interface 8 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Features 8 1 Features The primary QSPI features include the following e Full duplex three wire synchronous transfers e Half duplex two wire synchronous transfers e End of transfer interrupt flag e Programmable serial clock polarity and serial clock phase e Programmable delay between chip select and serial clock e Programmable baud rates e Programmable queue lengths and continuous transfer mode e Programmable peripheral chip selects Programmable queue pointers e Four transfer activation triggers e Programmable delay after transfer e Automatic loading of programmable address at end of queue Pause enable at queue entry boundaries Several of these features are not found on standard SPIs and are further described below 8 1 1 Programmable Baud Rates Each of the peripheral chip select lines in the QSPI has its own programmable baud rate The frequency of the internally generated serial clock can range from MCU_CLK to MCU_CLK 504 8 1 2 Programmable Queue Lengths and Continuous Transfers The number of entries in a queue is programmable allowing the QSPI to transfer up to 63 halfwords or bytes without MCU intervention Continuous transfers of information to several peripherals can be activated with a single trigger resulting in greatly reduced MCU QSPI interaction 8 1 3
537. tr 1 prot rtptr rxptr 2 prot rtptr rxptr 3 4 5 prot rtptr rxptr prot rtptr rxptr prot rtptr rxptr 6 prot rtptr txptr 0 prot rtptr txptr 1 prot rtptr txptr 2 prot rtptr txptr 3 prot rtptr txptr 4 prot rtptr txptr 5 prot rtptr txptr 6 prot mtptr rxptr 0 prot mtptr rxptr 1 prot mtptr rxptr 2 prot mtptr rxptr 3 prot mtptr rxptr 4 prot mtptr rxptr 5 prot mtptr rxptr 6 prot mtptr txptr 0 prot mtptr txptr 1 prot mtptr txptr 2 prot mtptr txptr 3 prot mtptr txptr 4 prot mtptr txptr 5 prot mtptr txptr 6 prot ftbar ftba0 0 prot ftbar ftba0 1 prot ftbar ftba0 2 prot ftbar ftba0 3 prot ftbar ftba0 4 prot ftbar ftba0 5 prot ftbar ftba0 6 prot ftbar ftbal 0 prot ftbar ftbal 1 prot ftbar ftbal 2 prot ftbar ftbal 3 prot ftbar ftbal 4 prot ftbar ftbal 5 prot ftbar ftbal 6 0x6 0x8 0x9 Oxa 0x0 0x1 0x2 0x3 0x4 0x5 0x6 Receive Receive Receive Receive Receive Receive Receive Transmit macro pointer bit Transmit macro pointer bit Transmit macro pointer bit Oxb Transmit macro pointer bit Oxc Transmit macro pointer bit Oxd Transmit macro pointer bit Oxe Transmit macro pointer bit Receive Receive Receive Receive Receive Receive Receive macro pointer bit macro pointer bit macro pointer bit macro pointer bit macro pointer bit macro pointer bit mac
538. trol Register Address 0020 B00A SCPDDn Description Reset 00uu m Read Write 0 anis an input when configured as 1 Pin is an output when configured as GPIO Port Data Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SCPDD4 SCPDD3 SCPDD2 SCPDD1 SCPDDO SCPPD4 SCPPD3 SCPPD2 SCPPD1 SCPPDO Motorola Programmer s Data Sheets For More Information On This Product Go to www freescale com E 75 Freescale Semiconductor Inc Application Date Programmer K P KCOn Description 0 Column strobe output n is totem pole drive 1 Column strobe output n is open drain Keypad Port Control Register Address 0020 A000 KREn Description Reset 0000 0 Row n is not included in key press Read Write detect 1 Row n is included in key press detect 15 14 13 12 11 10 9 8 p 7 6 5 4 3 2 1 0 KCO7 KCO6 KCO5 KCO4 KCO3 KCO2 KCO1 KCOO KRE7 KRE6 KRE5 KRE4 KRE3 KRE2 KRE1 KREO KP S R KPKD Description Keypad Status Register 0 No keypad press detected Address 0020_A002 Reset 0000 1 Keypad press detected Read Write Reserved E 76 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Application Freescale Semiconductor Inc Date Programm
539. try are loaded into QPn before queue execution is completed This initializes the queue pointer for the next queue without MCU intervention A write to the QP field while its queue is executing is disregarded NOTE The QP range is 00 3F for 64 queue entries Because the queue entries themselves are 16 bit halfwords that are byte addressable the actual offset that QP points to is two times the number contained in QP 8 16 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory SPSR Serial Port Status Register 0020_5F10 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO QX3 QX2 QX1 QX0 QA3 QA2 QA1 QAO HALTA TRC QPWF EOTS EOT2 EOT1 EOTO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The MCU can read the SPSR to obtain status information and can write to it in order to clear the HALTA TRC QPWF and EOT 3 0 status flags Only the QSPI can assert bits in this register Table 8 5 SPSR Description T Name n Description Settings QX 3 0 R Queue Executing The QSPI sets a queue s O Queue not executing default Bits 15 12 QX bit when the queue begins execution and 1 Queue executing clears the bit when queue execution stops Queue execution begins when a queue is active and no higher priority higher numbered queue is executing Execution stops under
540. ts GNDa Quiet ground These lines supply a quiet ground connection for the internal logic circuits GND Substrate ground These lines must be tied to ground 2 4 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock and Phase Locked Loop 2 3 Clock and Phase Locked Loop The pins controlling DSP36632 clocks and PLL are listed in Table 2 4 Table 2 4 PLL and Clock Signals Signal Name Type Reset State Signal Description CKIH Input Input High frequency clock input This input can be connected to either a CMOS square wave or sinusoid clock source CKIL Input Input Low frequency clock input This input should be connected to a square wave with a frequency less than or equal to CKIH This is the default input clock after reset CKO Output Driven low DSP MCU output clock This signal provides an output clock synchronized to the DSP or MCU core internal clock phases according the selected programming option The choices of clock source and enabling disabling the output signal are software selectable CKOH Output Driven low High frequency clock output This signal provides an output clock derived from the CKIH input This signal can be enabled or disabled by software PCAP Input Indeterminate PLL capacitor This signal is used to connect the required external filter Output capacitor to the PLL filter Motorola
541. ts the edge input Bits 7 0 programmed in the corresponding EPPA bit The bit remains set until it is cleared by writing a 1 to it A pin configured as level sensitive does not affect this register A write to EPDR that triggers a pin s level or edge will set the corresponding EPF bit The outputs of this register drive the corresponding input of the interrupt controller for those bits configured as edge detecting 7 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 8 Queued Serial Peripheral Interface The Queued Serial Peripheral Interface QSPI is a full duplex synchronous serial interface providing SPI compatible data transfer between the DSP56652 and up to five peripherals Four prioritized data queues Queue3 Queue0 Queue3 is highest priority can be triggered by the protocol timer and the MCU Each queue can contain several sub queues and each sub queue can be transferred to any of the five peripherals The queues can be variable sizes of 8 or 16 bit multiples Note A queue is defined as a series of data that is transferred sequentially Data can be 8 or 16 bits and each data entry occupies a 16 bit location in QSPI Data RAM Each datum in an 8 bit data queue occupies the lower byte of its RAM location the upper byte is zero filled A sub queue is a sequence of data within a queue that is transmitted without interruption Mo
542. u qspi spcr cspol0 11 equ qspi spcr cspoll 12 equ qspi spcr cspol2 13 equ qspi spcr cspol3 14 equ qspi spcr cspol4 15 WOONDU BNF O QSPI OCRn BITS equ qspi qcrn gon 0x3f queue pointer n bits mask equ qspi qcrn hmdn 14 equ qspi qcrn len 15 QSPI QCR1 BITS equ qspi qcrl trent 0x3c0 trigger counter mask for queue 1 QSPI SPSR BITS Motorola Equates and Header Files B 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Equates equ qspi spsr eot0 equ qspi spsr eotl equ qspi spsr eot2 equ qspi spsr eot3 equ qspi spsr qpwf equ qspi spsr trc equ qspi spsr halta equ qspi spsr ga0 equ qspi spsr gal equ qspi spsr ga2 10 equ qspi spsr ga3 11 equ qspi spsr qx0 12 equ qspi spsr qxl 13 equ qspi spsr qx2 14 equ qspi spsr qx3 15 vw 0 NUI CO PO ILS CO QSPI SCCRn BITS equ qspi sccrn sckdfn 0x7f sckdfn bits mask equ qspi sccrn csckdn 0x380 csckdn bits mask equ qspi sccrn datrn 0x1c00 datrn bits mask equ qspi sccrn lsbfn 13 equ qspi sccrn ckpoln 14 equ qspi sccrn cphan 15 Timer PWM base address equ tpw base addr 0x00206000 MCU Timer base address register addresses relative to base equ tpm tpwcr 0x0 equ tpm tmr 0x2 equ tpwm tpwsr 0x4 equ tpw twir 0x6 equ tpw tocrl 0x8 equ tpw tocr3 Oxa equ tpw tocr4 Oxc equ tpw ticrl O0xe equ tpw ticr2 0x10 equ tpwm pwor 0x
543. uding a periodic interval timer to generate periodic interrupts a watchdog timer to protect against system failure apwm and general purpose timer to generate custom signals aprotocol timer with TDMA counters for radio channel control event scheduling QSPI triggers or generating interrupts to either core e MCU OnCE facilitates test and debug 1 2 1 3 MCU Side Memory All MCU memory is 32 bits 1 word wide On chip MCU memory includes 512 words of RAM and 4K words of ROM In addition the EIM provides a 22 bit address 16 bit data bus with control signals to access external memory Programmable timing on this bus allows the use of a wide range of memory devices As many as six external memory banks can be connected 1 2 2 DSP This section describes the DSP core peripherals and memory 1 2 2 1 Core Description The DSP56600 core contains a data arithmetic logic unit an address generation unit a program control unit and program patch logic 1 2 2 1 1 Data Arithmetic Logic Unit The data arithmetic logic unit ALU performs all data arithmetic and logical operations in the DSP core The components of the data ALU include the following Four 16 bit input general purpose registers X1 XO Y1 and YO e A parallel fully pipelined MAC e Six data ALU registers A2 Al AO B2 B1 and BO that are concatenated into two general purpose 40 bit accumulators A and B e An accumulator shifter that is an asynchronous
544. uest pending 1 SIM Card Tx Rx or Error interrupt request pending SMPD Description 0 No interrupt request TPW Description 1 SIM Auto Power Down interrupt 0 No interrupt request request pending 7 1 General Purpose Timer PWM interrupt request pending URX Description 0 No interrupt request PIT Description 1 UART Receiver Ready interrupt request pending 0 No interrupt request 1 Periodic Interrupt Timer interrupt request pending 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 URX SMPD UTX PT2 PT1 PTO PTM QSPI MDI SCP TPW PIT Reserved Motorola Programmer s Data Sheets E 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Application Date Programmer MCU Interrupts INTS Description 0 No interrupt request S R 1 INT5 interrupt request pending Lower Halfword Interrupt Souce Register INT4 Description power Halters 0 No interrupt request Address 0020_0002 Reset 0007 1 INT4 interrupt request pending Read Write INT6 Description INT3 Description 0 No interrupt request 0 No interrupt request 1 INT6 interrupt request pending 1 INT3 interrupt request pending INT7 Description INTA Descrip
545. uncated or rounded into the MSP Rounding is performed if specified 1 2 2 1 2 Address Generation Unit The address generation unit AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses It implements four types of arithmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU is divided into two halves each with its own address ALU Each address ALU has four sets of register triplets and each register triplet is composed of an address register an offset register and a modifier register The two address ALUs are identical Each contains a 16 bit full adder referred to as an offset adder A second full adder referred to as a modulo adder adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register A third full adder called a reverse carry adder is also provided The offset adder and the reverse carry adder are in parallel and share common inputs The only difference between them is that they carry propagates in opposite directions Test logic determines which of the three summed results of the full adders is output Motorola Introduction 1 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Archit
546. urrently executed All communication with the DSP OnCE controller is done through the Select DR Scan path of the JTAG TAP controller 15 1 3 2 8 DSP DEBUG REQUEST B 3 0 0111 The DSP DEBUG REQUEST instruction is not included in the IEEE 1149 1 standard It is provided as a public instruction to allow the user to generate a debug request signal to the DSP core When the DSP DEBUG REQUEST instruction is decoded the TDI and TDO pins are connected to the Instruction Registers When the TAP is in the Capture IR state the OnCE status bits are captured in the Instruction shift register Thus the external JT AG controller must continue to shift in the DBSP DEBUG REQUEST instruction while polling the status bits that are shifted out until Debug mode is entered and acknowledged by the combination 11 on OS 1 0 After the acknowledgment of Debug mode is received the external JTAG controller must issue the ENABLE DSP ONCE instruction to allow the user to perform system debug functions 15 1 3 2 9 BYPASS B 3 0 1xxx The BYPASS instruction selects the single bit Bypass Register and restores control of the I O pins to system logic This creates a shift register path from TDI through the Bypass Register to TDO circumventing the BSR This instruction is used to enhance test efficiency when a component other than the DSP56652 becomes the device under test Motorola JTAG Port 15 9 For More Information On This Product Go to www freescale com Frees
547. use the source for this interrupt is the execution of a command in RAM it may be difficult in some cases to detect the control halfword that was the source for the interrupt The MCU clears each EOT by writing it with 1 O No end of transfer 1 End of transfer has occurred 1 R Read only R 1C Read or write with 1 to clear write with O ingored 8 18 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI Registers and Memory SCCRO Serial Channel Control Register O 0020_5F12 SCCR1 Serial Channel Control Register 1 0020_5F14 SCCR2 Serial Channel Control Register 2 0020_5F16 SCCR3 Serial Channel Control Register 3 0020_5F18 SCCR4 Serial Channel Control Register 4 0020_5F1A BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT O CPHA CKPOL LSBF DATR 2 0 CSCKD 2 0 SCKDF 6 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Each of these registers controls the baud rate timing delays phase and polarity of the serial clock SCK and the bit order for a corresponding chips select line SPICSO 4 The MCU has full access to these registers while the QSPI has only read access to them The MCU cannot write to the SCCR of an active line and it is highly recommended that writes to the SCCRs only be done when the QSPI is disabled or in HALT state Table 8 6 SCCR Description Name Description Settings CPHAn Clock Phase for SPICSn
548. ve cores Z 0 Run Test Idle Idle Z 0 Run Test Idle Idle 15 14 DSP56652 User s Manual Motorola For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A DSP56652 DSP Bootloader The DSP36652 DSP Bootloader is a small program residing in the DSP program ROM that is executed when the DSP exits the reset state The purpose of the bootloader is to provide MCU DSP communication to enable the MCU to download a DSP program to the DSP program RAM through the MCU DSP Interface MDI This appendix describes the various protocols available in the bootloader to communicate with the DSP56652 and how a protocol is selected It also provides a listing of the bootloader program A 1 Boot Modes The user can select one of the following three protocols or modes to use to download code for the DSP e Mode A Normal MDI boot mode implements a protocol incorporating MDI shared memory and messaging registers that enables the user to upload and download data to or from any address in program X or Y memory test the 512 byte program RAM and start the DSP from any address in program memory Mode B MDI shared memory boot mode allows only downloading to program RAM using only the MDI shared memory to transfer data The DSP program must start from program RAM address 0000 Some synchronization between the MCU and DSP is required e Mode C MDI messaging unit boot mode allows only downloading to program
549. ve sections that can operate with separate asynchronous or shared synchronous internal external clocks and frame syncs e TDM operation with either one slot per frame normal mode or up to 32 time slots per frame network mode Programmable word length 8 12 or 16 bits e Program options for frame synchronization and clock generation Features unique to one port include the following The SAP contains a bit rate multiplier BRM to convert a 16 8 MHz input to a 16 834 MHz clock that can generate standard codec clock rates The SAP includes a general purpose timer e The BBP contains transmit and receive frame counters In addition any or all of the pins in each port can be configured as GPIO Figure 14 1 and Figure 14 2 are block diagrams of the SAP and BBP respectively Motorola Serial Audio and Baseband Ports 14 1 For More Information On This Product Go to www freescale com CKIH BRM DSP_CLK BRM_CLK Y Freescale Semiconductor Inc SAPCRA Y Interrupts BRM MUX SAPCRB SAPCRC SAPTSR Clock Frame Sync Generators Bit Rate Multiplier Control Logic and Port Control Figure 14 1 SAP Block Diagram GDB BBPCRA SAPCNT RX Shift Register STDA TX Shift Register 9 TCLK SAPTX BBPRMR BBPTMR
550. w keypad data reg rows y endif kpsr register bits define KPSR KPKD 0x0001 EEEk kkk kkk kk kkk kk kkk kkk k kkk kkk REDCAP Timer PWM TPWM example usage struct redcap tpwm twom struct redcap tpwm REDCAP MCU TPWM kkkkkkkkkkkkkkkkkkkkkkkkkkkkk ifdef ASSEM define TPWM TPWCR 0x00 define TPWM TPWMR 0x02 define TPWM TPWSR 0x04 define TPWM TWIR 0x06 define TPWM TOCRl 0x08 define TPWM TOCR3 Ox0A define TPWM_TOCR4 Ox0C Zdefine TPWM_TICR1 0x0E define TPWM_TICR2 0x10 define TPWM_PWOR 0x12 define TPWM TCR 0x14 define TPWM PWCR 0x16 define TPWM PWCNR 0x18 else struct redcap tpwm unsigned short tpwer control reg unsigned short tpwmr mode reg Motorola Equates and Header Files B 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MCU Include File volatile unsigned short tpwsr status reg unsigned short twir interrupts enable reg unsigned short tocrl timer output compare 1 unsigned short tocr3 timer output compare 3 unsigned short tocr4 timer output compare 4 volatile unsigned short ticrl timer input capture 1 read only volatile unsigned short ticr2 input capture 2 unsigned short pwor pwm output compare volatile unsigned short tcr timer counter register read only unsigned short pwcr pwm count register volatile unsigned short pwcnr pwm counter re
551. w freescale com BSR Bit Definitions Freescale Semiconductor Inc Table C 1 BSR Bit Definitions Bit Pin Name Pin Type Cell Type Bit Pin Name Pin Type Cell Type 0 DSP_DE control 40 COLUMN4 control 1 DSP_DE input output data 41 COLUMN4 input output data 2 ROW7 control 42 COLUMN3 control 3 ROW7 input output data 43 COLUMN3 input output data 4 ROW6 control 44 COLUMN2 control 5 ROW6 input output data 45 COLUMN2 input output data 6 ROW5 control 46 COLUMN1 control 7 ROW5 input output data 47 COLUMN 1 input output data 8 ROW4 control 48 COLUMNO control 9 ROW4 input output data 49 COLUMNO input output data 10 ROW3 control 50 STO output data 11 ROW3 input output data 51 RESET_IN input data 12 ROW2 control 52 RESET_OUT output data 13 ROW2 input output data 53 BMODE input data 14 ROW1 control 54 SIMRESET control 15 ROW1 input output data 55 SIMRESET input output data 16 ROWO control 56 SENSE control 17 ROWO input output data 57 SENSE input output data 18 INT7 control 58 SIMDATA control 19 INT7 input output data 59 SIMDATA input output data 20 INT6 control 60 PWR EN control 21 INT6 control 61 PWR_EN input output data 22 INT5 control 62 SIMCLK control 23 INT5 input output data 63 SIMCLK input output data 24 INT4 control 64 DATA15 input output data 25 INT4 input output data 65 DATA14 input output data 26
552. w slow the DSP is 4 DSP parallel accesses Any DSP access in parallel to an MCU access to the same 1 4K memory block can further stall a pending MCU access If the DSP does not run consecutive one cycle accesses and the MCU frequency is not faster than the DSP s frequency an MCU contention stall will be no more than one MCU cycle 5 DSP PLL If the PLL is reprogrammed during MCU program execution e g after a DSP reset the MCU should not access shared memory until the PLL has reacquired lock If the MCU attempts to access the MDI shared memory before the PLL acquires lock the MCU can time out and generate an error One way to avoid this condition is to take the following steps a DSP software sets an MDI flag bit immediately after setting the PLL b MCU software polls the flag bit until it is set before accessing MDI shared memory MCU side access timing is summarized in Table 5 1 Motorola MCU DSP Interface 5 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MDI Messages and Control Table 5 1 MCU MDI Access Timing DSP MCU Cycles Access Type Clocks Comments Minimum Maximum Shared memory read Inactive 11 11 Assumes write buffer is empty Active 4 8 Shared memory write Either 2 2 Assumes write buffer is empty Buffer busy after Inactive 8 8 Consecutive accesses incur MCU stall shared memory write cycles Active 2 4 MCU
553. x0 old name OxO NEW NAME 0x1 0x4 0x5 old name 0x5 NEW NAME 0x6 old name 0x6 NEW NAME 0x7 0x8 0x9 old name 0x9 NEW NAME Oxa Oxb Oxc Oxd old name Oxd NEW NAME Oxe Oxf UART control register 2 UCR2 ucr2_clksrc 0x4 0x5 old name 0x5 NEW NAME 0x6 0x7 0x8 Oxc old name Oxc NEW NAME OxD Oxe 0x5 0x9 Oxd Oxe Oxf old name Equates and Header Files For More Information On This Product Go to www freescale com MCU Equates Freescale Semiconductor Inc MCU Equates equ usr txe Oxf NEW NAME bits of the UART receiver register URX equ urx prerr Oxa equ urx brk Oxb equ urx frmerr Oxc equ urx ovrrun Oxd equ urx err Oxe equ urx charrdy Oxf bits of the UART test register UTS equ uts loopir Oxa equ uts loop Oxc equ uts frcperr Oxd bits of the UART port control register UPCR old names equ upcr pco 0x0 equ upcr pel 0x1 equ upcr pc2 0x2 equ upcr pc3 0x3 bits of the UART port control register UPCR NEW NAMES equ upcr upcO 0x0 equ upcr upcl 0x1 equ upcr upc2 0x2 equ upcr upc3 0x3 bits of the UART data direction register UDDR old names equ uddr pdcO 0x0 equ uddr pdc1 0x1 equ uddr pdc2 0x2 equ uddr pdc3 0x3 bits of the UART data direction register UDDR NEW NAMES equ uddr uddO 0x0 equ uddr uddl 0x1 equ uddr udd2 0x2 equ uddr udd3 0x3 bits of the UART port data register UPDR old na
554. y Mapped Peripherals nnno nunnana nanana 3 3 External Memory paces a sd da we e lead TURAE o el dad 3 3 ItescryedoMOPIOEV AAA O Ba et DEA 3 4 DSP Memory Map and Descriptions 3 4 X Data Memoty oa 24 sce a E tee oh Suede S ode Sat 3 5 X Data MEMO 5 ance NAAA SaL HEU PASA 3 6 Program Memory i xli Re RRLREBACOCSHURR OR NER Fhe RARUS OUS 3 6 Reserved Memory ya coq Lui rhe A pere lead Mu e ade 3 6 Chapter 4 Core Operation and Configuration CLOACAS EA AA AAA 4 1 MG UE CER aa a dad a rs e wed ted Lo 4 2 DSP CER A o 4 3 Clock and PLIG RebPIStetSs 6 esto A A Es 4 5 Low Power Modest e a od e e cl 4 8 i n rre E 4 9 MCU ESC uu ao 4 11 DSP Resta sl Ee be ib a do 4 11 DSP Configuration i A RE es 4 12 Operating Mode Register fy Soon bee OR CREE ENT 4 12 Patch Address Registers esu Rte re rbd adas Wed aaia 4 14 Device Identification Regis AAA AA 4 15 VOMIT plex EA A EA AA AA 4 15 Debug Port and Timer Multiplexing 0 0 0 0 eee eee ee 4 15 DSP Address Visibility ssec kx Ex Te CERE EE etii wept 4 20 Chapter 5 MCU DSP Interface MDELNIGHIBOEY 5x ex 9555 5 rs Rech Re ERU A EIUS LANA 5 2 DSP Side Memory Mapping 4 v ve SE n o REN RAT 5 2 MCU Side Memory Mapping 4 Eee de y ehe Es 5 3 Shared Memory Access Contention llleeeeeeeeeeeee 5 3 Shared Memory TIMINS i o usua Vae tee d et edes ee A Sat 5 4 MDI Messages and Control vei o Cr SAU A e Re Use RC E RE eA SA 5 6 MDI Messaging System sr c
555. y in the receive macro They should be initialized before the first receive macro is activated DTPTR Delay Table Pointer 0020 3824 Biti5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 TDBA 3 0 TDPTR 2 0 RDBA 3 0 RDPTR 2 0 RESET 0 0 Table 10 22 DTPTR Description Name Description TDBA 3 0 Transmit Macro Delay Table Base Address 3 0 These bits determine the location in memory Bits 14 11 of the first entry in the transmit macro delay table They contain the four most significant bits of the 7 bit offset from the beginning of PT RAM TDBA should be initialized before the first transmit macro is activated TDPTR 2 0 Transmit Macro Delay Pointer 2 0 These read only bits are the three bit offset from TDBA that Bits 10 8 point to the delay table entry of the active transmit macro They are specified by the particular event code that called the macro RDBA 3 0 Receive Macro Delay Table Base Address 3 0 These bits determine the location in memory of Bits 6 3 the first entry in the receive macro delay table They contain the four most significant bits of the 7 bit offset from the beginning of PT RAM RDBA should be initialized before the first receive macro is activated RDPTR 2 0 Receive Macro Delay Pointer 2 0 These read only bits are the three bit offset from TDBA that Bits 2 0 point to the delay table entry of the active receive macro They are specified by the particular event code that called the macro Motorola Protocol Timer 10 25

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