A New Surface-Potentials Based MOSFET Model
Contents
1. Strategy 37 is applied to Current ID VD VG charac teristics for the smaller devices of the L array for both low and high VBS The aim is to optimize gate overlap length XLD in addition to velocity parameters VMAX VOVER VOVERP The optimization is performed in saturation region STRATEGY DEFINITION SCREEN Strategy 38 idvd_linear_HiSIM Strategy 38 is used to optimize contact resistance and potential barrier resistance parameters RS RD and RPOCK1 RPOCK2 on ID VD VG curve at low VBS A single step is used for those optimizations They are performed in linear region of the characteristics VDS start 0 VDSstop 0 5 sweep start 3 sweep stop 5 for Large and Wide device and middle devices STRATEGY DEFINITION SCREEN Current iavatinear_HisiM Routine i IDAVD VG M RPOCKI M RPOCK2 P RS M RD i I 1 2 3 4 5 of Parameters 10 of Steps Rows 10 Target Selection QUIT Figure 20 Local optimization strategy definition screen for Stra teg y 88 idvd_linear_HiSIM TARGET SELECTION SCREEN YDS start YDS stop YGS start YGS stop VBS start VBS stop Current idvd_saturate_HiSIM Routine 1 IDND VG gt MOVER XLD MAX ji I VOVERP RP an A w nN of Parameters 40 of Steps Rows 10 Target Selection QUIT Figure 18 Local optimization strategy definition screen for Strateg y 87 idvd_ saturate HiSIM TARGET SELECTIO2. FastBlaze FastLargeSignal FastMixedMode FastGiga FastNoise Mocasim Spirit Beacon Frontier Clarity Zenith Vision Radiant TwinSim UTMOST UTMOST IL UTMOST IH UTMOST IV PROMOST SPAYN UTMOST IV Measure UTMOST IV Fit UTMOST IV Spice Modeling SmartStats SDDL SmartSpice FastSpice Twister Blast MixSim SmartLib TestChip Promost Rel RelStats RelLib Harm Ranger Ranger3D Nomad QUEST EXACT CLEVER STELLAR HIPEX net HIPEX r HIPEX c HIPEX rc HIPEX crce EM Power IR SI Timing SN Clock Scholar Expert Savage Scout Dragon Maverick Guardian Envoy LISA ExpertViews and SFLM are trademarks of Silvaco International July 2002 Page 16 The Simulation Standard Hints Tips and Solutions Mustafa Taner Applications and Support Engineer Q How can I measure low current FT for Bipolar devices A The input impedence of most network analyzers are around 1 MOhm which is relatively small Due to this low impedence the leakage current on the Base port Typically Port1 becomes high and makes it impossible to find the correct collector current bias when Linear IC or Log IC measurement modes are selected in FT_CE routine For example if the base voltage biased at 0 5V the leakage current to the ground will be 0 5uA For an NPN device with DC gain of 100 this will translate into a collector current loss of 50uA This means that the device can not be biased using current sources Linear IC and Log IC
3. The present section provides all the information needed to understand and use the BSIM3SOI v3 0 model The SmartSpice implementation of the BSIM3SOI v3 0 model is close but not identical to UC Berkeley release The SmartSpice implementation provides a number of improvements and additional parameters currently unsupported in Berkeley s BSIM3SOI v3 0 model Volume 12 Number 7 J uly 2002 In the SmartSpice implementation of the BSIM3SOI v3 0 model enhanced convergence is obtained by properly handling GMIN and DCGMIN control options during transient and DC analysis The GMIN option connects a conductance in parallel with the bulk diodes and between drain and source The option VZERO defines the Modified Nodal Analysis MNA formulation The VZERO 2 option is recommended when simulating in the time domain relatively large circuits with hundreds or thousands of transistors It accelerates simulation and increases the accuracy of simulation results The option CAPDC 1 allows the user to see charge and capacitances in DC see output variables The parameter checking procedure initially used for BSIM3v3 and BSIM4 has been extended to BSIM3SOI v3 0 This checking procedure verifies some critical parameters values and output warnings and or errors to the screen or to a logfile BSIM3SOI v3 0 model has been optimized to take advan tage of the multi processor machines The simulation is speed up when SmartSpice is run on parallel archi
4. 1 The Simulation Standard Both Poisson equations are solved iteratively because they are implicit Using approximations to get explicit equations with regard to terminal voltages would not be an improvement it would SmartSpice Plot 8 File Edit View Options Zoom Alif Belse 4 4 gt al vi sl HiSIM Surface potentials reduce accuracy and convergence is quickly obtained when solving these two equations The internal New ton s algorithm converges within one to ten iterations depending on the circuit This is acceptable for a circuit simulator since simulation times are comparable to those observed using other models The screenshot in Figure 2 shows the surface potentials evolution when VGS increases New in Version 1 1 0 The last improvements are shallow trench isolation STI is accounted for in leakage current model a 2 i i 4 i orso s E A dc1 m1 psi 7 638889e 02 8 491357e 01 lateral field induced capacitance has been added and the resistance model has been improved requiring two more model parameters These new modeling equations make HiSIM even more accurate Modeled Effects HiSIM computes charge control using dedicated parameters to account for the following physical effects Short channel Reverse short channel Pocket implantation Quantum Poly depletion Universal mobility Channel length modulation Velocity overshoot Symmetry at
5. Current Max Sweep start Sweep stop Ea Geometry Geometry Geometry Geometry Geometry QUIT Extract Extract VDSAT DISABLED a DISABLED Figure 4 Local optimization target selection screen for Stra teg y 80 idvg_large_HiSIM GEOMETRY SELECTION SCREEN 10 00 0 50 Figure 5 Local optimiza 0 30 tion geometry selection A screen for Strategy 30 i idvg_large_HiSIM QUIT Strategy 31 idvg_middle_HiSIM This strategy is used to optimized pocket penetration length and maximum pocket concentration LP and NSUBP in a first step then reverse short channel coef ficient 1 and 3 for pocket SCP1 and SCP3 in a second one It will optimize the Current of ID VG charac teristics Figure 6 The middle devices of the L array should be selected for each row in this strategy Pocket parameters are going to be optimized for all VBS value sweep start set to 1 and sweep stop to 5 while short channel parameters are optimized only for VBS O0V as there is no VBS effect on standard short channel effect All this strategy is done for low VDS Those parameters are optimized in subthreshold and around threshold region As for Strategy 30 step 1 and 2 are duplicated in order to iterate the optimization The Simulation Standard STRATEGY DEFINITION SCREEN Current jdvg_middle_HiSIM Routine 2 IDNG VB Pg r NSUBP f y 2 f iscei M IScP3 H Pe M NSUBP
6. The suffix xxx of the bias file is computed as VCE 100 For example bias200 corresponds to gummel plot data measured for VCE 2V Therefore if the user measures simulates or retrieves data using the Gummel routine at VCE 2V and VCE 5V the files named bias200 and bias500 will appear in the UTMOST user directory When the VBE VCE constant or VBE VCB constant options are selected the measurement variables VBE_start VBE_stop and IC_points will be used to determine base voltage VBE However the collector current will not be measured and the base current will not be iterated The value of the base and collector currents will be obtained from the bias xxx file The linear regression method will be used to determine the exact base and collector currents for the given VBE This approach extends the low collector current measurement limits to 5uA to 10uA If the bias xxx is not present during the FT_CE measurement then an error message will be displayed on UTMOST screen E ATTRIEUTES Fe Mase DHT OFTIONS ric 1 lustre Sune Flat 3 is z u H h ei ee Di Extrinsic VEE Figure 2 Gummel plot data Call for Questions If you have hints tips solutions or questions to contnbute please contact our Applications and Support Department Phone 408 567 1000 Fax 408 496 6080 e mail support silvaco com Hints Tips and Solutions Arc hive Check our our Web Page to see more detail
7. regions Gate to Body tunneling current Igb For more details concerning the physical expressions of BSIM3SOI v3 0 model please refer to SmartSpice Modeling Manual Volume 3 3 Model Parameters BSIM3SOIv3 model LEVEL 33 supports all model parameters of BSIM3SOI Partially depleted LEVEL 29 and Fully depleted LEVEL 26 models The additional parameters listed in Table 1 correspond to BSIM3SOIv3 model released by UC Berkeley in May 2002 only Sivaco Improvements Options The option VZERO 2 allows faster runtime when large circuits are used The EXPERT option can be specified to detect possible problems in models before and during simulation such as negative conductances GM GDS and GMBS negative gate capacitances The feature summary of the parameter checking in BSIM3SOI3 v3 0 is provided below To read warnings on screen set the EXPERT option to 777 To perform all possible tests add PARAMCHK 1 to the model card To avoid writing any logfile add PARAMCHK 1 in the model card In order to control the checking procedure two values are used The EXPERT option if equal to 777 non fatal warnings will be displayed on screen The fatal warnings are always sent to screen The PARAMCHK model parameter if equal to 1 or true a full parameter testing will be performed issuing warnings when suspicious parameters values are found July 2002 E T e E E us oretvorage aue to romaeaies
8. while the smaller show a middle group including devices from 10x5 to devices will be used for standard short channel effect 10x0 5 while short group will include device from 10x0 1 10x0 11 On the example shown in Figure 2 the middle group ee Te includes devices from 10x5 to 10x0 2 while short group July 2002 Page 10 The Simulation Standard Run by SILVACO Process CMOS Temp 27 VTH_meas vs L 0 55 eaaa amaaa a amaaa Heas Method Vg Id 100 nA W L Hdraw 10 00 Type PHO F VDS 1 000 0 50 L ie VBS start 0 000 J j X VBS step 0 250 x N RKS si 0 45 4 YOR J gt HAL i ee 4f k m i 4j ii T LA Saai 3 0 40 JN haea i Me l T l HA 0 35 i A i i w te Y 0 30 L d 4 T 0 25 2 1 0 1 2 10 10 10 10 10 11 48 52 SEP 4 2 v 18 7 1 Ldraw Microns SILVACO Intemational Current of Parameters 10 of Steps Rows 7 Figure 2 VIH dependence on Lfora High VDS UTMOST rou tine Validate Local Optmization Strategies After the data is collected The ALL_DC routine can be used for local optimization In this article s example a single ALL_DC routine will be used The different types of data will be displayed in the ALL_DC graphics screen for different optimization strategies This may require more user interface but it is easier to follow each step of local optimizations this way Later the user may automate the local optimization stra
9. 1 GIDL2 GIDL3 Flicker noise NFALP NFTRP CIT VZADDO PZADDO LGATE dependence of velocity overshoot Resistance coefficient 1 caused by the potential barrier Resistance coefficient 2 caused by the potential barrier Resistance coefficient 3 caused by the potential barrier Resistance coefficient 4 caused by the potential barrier Channel length modulation Hardness coefficient of channel contact junction Coefficient for OB contribution Coefficient for OI contribution Substrate current Substrate current coefficient 1 Substrate current coefficient 2 Substrate current coefficient 3 Gate current coefficient 1 Gate current coefficient 2 Gate current coefficient 3 GIDL current coefficient 1 GIDL current coefficient 2 GIDL current coefficient 3 Contribution of the mobility fluctuation Ratio of trap density to attenuation coefficient Capacitance caused by the interface trapped carriers Symmetry at VDS 0 Symmetry conservation coefficient 1 Symmetry conservation coefficient 2 available only in version 1 1 0 The Simulation Standard HiSIM version 1 0 Model Released in UTMOST III Inttoduction HiSIM is a MOSFET model for SPICE circuit simulation that has been developed by Hiroshima University and STARC Company This model present several advantage on the extraction point of view with a reasonable number of parameters a physical reliability of the equations for a wide range of geomet
10. 3 Short channel PARL1 PARL2 SCI SC2 SC3 SCP1 SCP2 DCPS Narrow channel WEC MUEPH2 WO WVTHSC NSTI WSTI Mobility VDSO MUECBO MUECB1 MUEPHO MUEPH1 MUETMP MUESRO MUESR1 NDEP NINV NINVD BB VMAX VOVER July 2002 Strength of poly depletion Threshold voltage of poly depletion VDS dependence of poly depletion Strength of lateral electric field eradient Depletion width of channel contact junction Short channel coefficient 1 Short channel coefficient 2 Short channel coefficient 3 Short channel coefficient 1 for pocket Short channel coefficient 2 for pocket Short channel coefficient 3 for pocket Threshold voltage reduction Mobility reduction Minimum gate width Short channel effect at the STI edge Substrate impurity concentration at the STI edge Width of the high field region at STI Drain voltage for extracting the low field mobility Coulomb scattering Coulomb scattering Phonon scattering Phonon scattering Temperature dependence of phonon scattering Surface roughness scattering Surface roughness scattering Coefficient 1 of effective electric field Coefficient 2 of effective electric field Modification of NINV High field mobility degradation Maximum saturation velocity Velocity overshoot effect VOVERP RPOCK1 RPOCK2 RPOCP1 RPOCP2 CLM1 CLM2 CLM3 SUB1 SUB2 SUB3 Gate current GLEAK1 GLEAK2 GLEAK3 GIDL current GIDL
11. N SCREEN Extract Extract e VDSAT DISABLED VTO PHBA EE G TARGET SELECTION SCREEN Geometry Geometry Geometry Geometry Geometry QUIT Figure 19 Local optimization target selection screen for Stra teg y 37 idvd_saturate_HiSIM Extract Extract 7 VDSAT DISABLED VTO PHBA EE G July 2002 Page 14 Extract Extract z s VDSAT DISABLED VTO BEFABEE G TARGET SELECTION SCREEN Geometry Geometry Geometry Geometry Geometry QUIT Figure 21 Local optimization strategy target selection screen for Strateg y 88 idvd_linear_HiSIM Extract Extract x YDSAT DISABLED VTO PIVABL EB Local Optimization Sequence The following sequence is presented as an advice to obtain a good model extraction procedure It is NOT recommended to run all the sequence at once The user should run each strategy one by one and observe the optimization results after each strategy is completed By running sequentially the sequence the user will be able to repeat some strategies or to come back in the proce dure to obtain a better fit The following sequence should be seen as a hint to achieve a good extraction Rough optimization of technological then mobility parameters idve_ large HiSIM idve_lowMue_HiSIM idvg_ large HiSIM The Simulation Standard extraction of short channel effect parameters idvg_middle_HiSIM idvg_ large HiSIM idvg_middle_HiSIM idvg_short_HiSIM idvg_middle_Hi
12. SIM idvg_short_HiSIM x2 extraction of VDS dependence of short channel effect idvg_highVT_HiSIM idvg highVT2_HiSIM x4 extraction of mobility and velocity parameters idve_lowMue_HiSIM idvg highVD_HiSIM idvd_saturate_HiSIM extraction of resistance parameters idvd_linear_HiSIM Poly Depletion and Quantum Mechanical Effect Direct Extraction UTMOSTIUI now includes a routine dedicated to Poly depletion and Quantum mechanical effect direct extraction This new algorithm can be accessed from INTCAP CGG routine INTCAP is an UTMOST III routine dedicated to MOSFETs Intrinsic capacitance measurement extraction and optimization Description of how to use this routine can be found in UTMOSTILI Extraction manual Vol 1 This algorithm should be applied to a Large and Wide device To access QMExx and PGDxx parameters extraction algorithm in your SPICE MODEL FILE screen HiSIM model should be selected Figure 22 In INTCAP Fitting Variables screen Figure 23 set qme pgd variable to 0 for QME1 2 3 and PGD1 2 parameters extraction 1 for QME1 2 3 parameters extraction only 2 for PGD1 2 parameters extraction only SPICE SCREEN SPICE MODEL FILE SCHEEN Technology SPICE file Yexporthhomesfrancois_localAvORK UTMOST SPICE LEVEL Berkele LEVELS BSIM3 v3 1 LG HSPICE BSIMSv3 1L41 PSPICE LEYELI ELDO HIGH Voltage SPECTRE BSIM3 3 2L6 PROPRIETARY BSIMI3v3 2L41 EK BSIM 4 Mos Lo
13. TCAD Driven CAD Simulation Standard A Journal for Circuit Simulation and SPICE Modeling Engineers BSIM3SOI Version 3 0 Model Released in SmartSpice Inttoduction BSIM3SOI version 3 0 model was released on May 2002 by UC Berkeley This model includes both Partially depleted and Fully depleted models This model is now implemented in SmartSpice and can be selected according to LEVEL selector LEVEL 33 selects BSIM3SOI v3 0 model A new full depletion FD module has been included to provide better fitting to FD SOI devices This can be invoked setting the model parameter SOIMOD 1 The partially depletion PD module is by default identical to latest version of BSIM3SOI PD version 2 2 3 also supported in SmartSpice with previous versions setting LEVEL 29 This can be invoked setting the model parameter SOIMOD 0 New Gate to Channel current Igc and new Gate to Source Drain currents Igs and Igd components have been added in BSIM3SOI v3 0 By default these currents are set to 0 in order to stay compatible with previous version but can be accounted turning on the new selector IGCMOD Gate to Body tunneling current was taken into account in BSIM3SOI v2 PD LEVEL 29 model turning on IGMOD selector In BSIM3SOI v3 0 identical expressions are used for the calculation of this gate tunneling current component but the selector is named IGBMOD now A minor bug has been fixed in the self heating algorithm Implementation
14. VDS 0 Shallow trench isolation version 1 1 0 only HiSIM and SmartSpice HiSIM is available within SmartSpice when LEVEL 111 is specified This model has been implemented using reference versions 1 0 0 and 1 1 1 The user can select one of these version using a selector VERSION Beyond this material SmartSpice provides all the services commonly proposed for MOSFET models Among them are Advanced geometry scaling ACM Simulation performance using VZERO and BYPASS options Friendly diagnostics to help with convergence issues Extrinsic elements such as junction diodes capacitances The Simulation Standard Figure 1 The model card for HiSIM includes the following parameters Technological parameters TOX Oxide thickness XLD Gate overlap length XWD Gate overlap width XPOLYD Difference between gate poly and design length TPOLY Height of the gate poly Si RS Source contact resistance RD Gate contact resistance NSUBC Substrate impurity concentration NSUBP Maximum pocket concentration VFBC Flat band voltage LP Pocket penetration length XJ Junction depth XQY Distance from D junction to maximum electric field Temperature dependence BGTMP1 Bandgap narrowing BGTMP2 Bandgap narrowing Quantum effect QMEI1 Coefficient 1 for quantum mechanical effect QME2 Coefficient 2 for quantum mechanical effect QME3 Coefficient 3 for quantum mechanical effect July 2002 Poly depletion PGD1 PGD2 PGD
15. Yamaguchi K Yamashita N Nakayama HiSIMv1 0 User s Manual STARC 2 Silvaco Intemational UTMOST III Extractions Manual volume 1 MOSFET Modeling routines 3 Silvaco Intemational UTMOST III User s Manual Contacts Hiroshima Universty http home hiroshima u ac jp usd HiSIM shtml Silvaco Intemational http www silvaco com STARC http www starc or jp hisim FIT VARLABLES FITTING VARIABLES Figure 23 INT CAP fitting variables screen Page 15 The Simulation Standard Calendar of Events July August l D 2 3 3 4 4 5 5 6 7 7 8 8 Q 10 IntI W S on Active 10 Matrix amp TFT Tech Tokyo I 11 CS MAX Boston MA 12 Int W S on Active 13 Matrix amp TFT Tech Tokyo 14 12 CS MAX Boston MA 15 IntI W S on Active 10 Matrix amp IFT Tech Tokyo 17 13 CS MAX Boston MA 18 14 19 15 NSREC Phoenix AZ 20 16 NSREC Phoenix AZ 21 17 NSREC Phoenix AZ 22 18 NSREC Phoenix AZ 23 19 NSREC Phoenix AZ 24 20 ZO 2 26 29 27 23 28 24 29 25 30 26 ol a 28 29 30 l For more information on any of our workshops please check our web site at http www silvaco com Bulletin Board Formation of Everest Design Services and Monarch Software Silvaco has spun off two new ventures Everest Design Services Inc and Monarch Software Inc Everest will develop mar ket and sell digital simulation software and software for digital designers Monarch Software Inc will develop market
16. a charge sheet model Ips current is described using only one equation and there fore is continuous over the whole range of operating regions This improves MOSFETs modeling regarding at least two points e Equations are continuous over all operation regions as well as their derivatives This is a key point for today s analog circuits where performance is very much dependent on high order derivatives e Parameter number is dramatically reduced by a factor 5 for the same level of accuracy Parameters are not interdependent anymore making extraction easier Furthermore a set of parameters is valid for all channel lengths July 2002 Surface Potentials HiSIM is based on charge control and charge flow through the channel The inversion layer charge and the depletion layer charge depend on the surface potential along the channel To compute these charges the surface potentials at source side s and dc at drain side are needed These two values are directly dependent on technological parameters They are calculated by solving the Poisson equations Cox Vg b 9 V2Lp IN sup exp B Oso 7 q Po Ppo lexp bso p Oso Vgs exp 8 Ms y Cox VV 0 V2Lp ON sup exp p Os Ves p Osz 7 V 55 nl ee lexpB 5 B Gs V Ves B so Ves zs exp gD v The surface potentials side s and s are distributed in the channel according to the schematic shown in Figure 1 Figure
17. ad Model Ale Summary Print file Delete Model QUIT Figure 22 Spice model selection screen Store Model July 2002 If variable hisim_tox is set to 1 TOX parameter will also be extracted To activate the extraction algorithm when INTCAP CGG characteristic is displayed press Options Fit from the GRAPHICS screen Warning QME and PGD extraction algorithm requires the following parameters to be known precisely LP NSUBP BGTMP1 BGTMP2 Be sure they have been extracted and that the corresponding values are in the Optimized column before using it Conclusion A total of 9 local optimization strategies and one direct extraction routine for HiSIMv1 0 model have been pre sented in this article The local optimizations should not be used without any user s modification Go into each strategy and change the selected geometries in the Geometry Selection Screen according to the available devices and the observation of the VTH dependence on L The user should also check if the region of interest specified in each strategy is properly selected by the criteria defined in the Target selection screen References 1 M Miura Mattausch H Ueno H J Mattaush H Kawano D Kitamaru K Hisa mitsu T Honda S Matsumoto D Miyawaki H Nagakura S Nara D Navaro T Okagaki S Ooshiro Y Shiraga K Suematsu M Suetake M Tanaka Y Tatsumi T Yamaoka S Kumashiro T
18. and sell Place and Route software Everest is incubated by acquiring Everest Design Services LLP Both companies expect to introduce their first products by Q1 of 2003 Second Reunion of Old Timers in Hawaii Old Timers employees with 5 years of service with exceptional performance record and employees with outstanding contribution were invited to the 2nd Hawaii reunion From September 28th to October 5th employees and their families had a good time relaxing and meeting employees from other Silvaco offices Loyalty and longevity is well rewarded at Silvaco The Simulation Standard circulation 18 000 Vol 12 No 7 July 2002 is copyrighted by Silvaco International If you or someone you know wants a subscription to this free publication please call 408 567 1000 USA 44 1483 401 800 UK 81 45 820 3000 Japan or your nearest Silvaco distributor Simulation Standard TCAD Driven CAD Virtual Wafer Fab Analog Alliance Legacy ATHENA ATLAS MERCURY VICTORY VYPER ANALOG EXPRESS RESILIENCE DISCOVERY CELEBRITY Manufacturing Tools Automation Tools Interactive Tools TonyPlot TonyPlot3D DeckBuild DevEdit DevEdit3D Interpreter ATHENA Interpreter ATLAS Interpreter Circuit Optimizer MaskViews PSTATS SSuprem3 SSuprem4 Elite Optolith Flash Silicides MC Depo Etch MC Implant S Pisces Blaze Blaze3D Device3D TFT2D 3D Ferro SiGe SiC Laser VCSELS Quantum2D 3D Luminous2D 3D Giga2D 3D MixedMode2D 3D
19. e 3 Ring oscillator SOIMOD 0 July 2002 A New Surface Potentals Based MOSFET Model HiSIM HiSIM stands for Hiroshima university STARC IGFET Model It has been developed at Hiroshima University starting in 1992 It has been released as version 1 1 0 in July 2002 HISIM and Conventional MOSFET Models HiSIM is interesting because of the way it models channel current Conventional MOSFET models sim plify computation of channel current by splitting calcu lation between a linear dependent region due to strong inversion and a saturation region due to velocity satura tion Discontinuities can appear in IDS in the transi tion region Therefore to avoid these discontinuities extra parameters are used to smooth the transition between the different set of equations These parame ters are not physical they are just needed to correctly fit the device s characteristics Another drawback of common models is the bad modeling of short channel effects For deep sub micron MOSFETs this effect dominates the Ips Vps characteristic Conventional models do not use equations based on physical concepts but add fitting parameters to each modeled effect to account for short channel effect This results in many unphysical fitting parameters and makes parameter extraction difficult The conclusion is that dividing the Ips current into different regions and equations is not correct anymore for short channel transistors HiSIM is based on
20. ence of phonon scattering a MUESRO surface roughness scattering cm Vs Vem MER 2 MUESR1 surface roughness scattering SS 2E15 NDEP coefficient of effective electric field 1 NINV coefficient of effective electric field 0 5 1E Co li VMAX emis aE VOVER em vom 1063 Channel length modulation CMI CLM2 Substrate current SUBI SUB2 SUB3 Gate current OOE 3 NT ke e ININ O i a lt A I il gate current coefficient 1 AV C 7 OE3 ah es 20E6 300E 3 GLEAK2 GLEAK3 gate current coefficient 2 gate current coefficient 3 GIDL1 GIDL2 GIDL3 1 f Noise NFALP NFTRP ratio trap density to attenuation coefficient CIT Capacitance caused by the interface trapped camers Conservation of the symmetry at Vds 0 for Short Channel MOSFETs VZADDO symmetry conservation coefficient GIDL curent coefficient 1 6 GIDL current coefficient 2 1E6 D o contribution of the mobility fluctuation UJ UI im 1E 10E6 m Oo lt lt fb WN O 3 Fcm 10E 3 PZADDO symmetry conservation coefficient 5E 3 Table 1 HiSIMv1 1 default model card Standard short channel effect makes VTH grows with L gate includes devices from 10x0 13 to 10x0 11 This split of while Reverse short channel effect has the opposite influence the L array is valid for low VDS The bigger devices of the L array will be used for VTH dependence on L for high VDS VDS 1V will reverse short channel effect parameters
21. etlist s option which can be invoked setting BYPASS 1 and filename appended with the model s type and the BYPASS 2 In the best case the performance of extension chk For example netlist1 bsim3soi_v2 chk simulations has been improved of 30 Parameter_ Description nits pefut New Model Parameters WESON Vesa ee SMART _ Improvement selector CT 2 New modelparameters are listed in Table 2 LM IN Minimum length for binnin joo 3 3 The four model parameters LMIN LMAX LMAX Maximum length for binning o WMIN dinimunavidtior binning WMIN and WMAX are used for binning to WMAX Maximun width for binning L select a model Moreover a temperature TMIN Minimum temperature for binning d binning capability has been added TMIN and Maximum temperature for binning a TMAX For the bin ning Silvaco has also BULK Default body bulk node name not given added new binned model parameters shown in BACKGATE Default backgate substrate node name not given Table 3 Table 2 SmartSpice Specific parameters July 2002 Page 3 The Simulation Standard The SMART model parameter allows to Silvaco which are not compatible switch on improvements with original Berkeley SMART model parameter has been created as follows model if SMART 0 the original Berkeley model is used with its different versions if SMART gt 0 Silvaco s ACM common equations are used geometry bulk diodes and drain source series re
22. g y 35 idvg_lowMue_HiSIM TARGET SELECTION SCREEN ee ene aero aan i Geometry Geometry Geometry Geometry Geometry QUIT pond DISABLED Peirat DISABLED TARGET SELECTION SCREEN Gp pee e e f A pee iid o e he h f aii i i i l Geometry Geometry Geometry Geometry Geometry QUIT Extract 7 Extract VDSAT BIRABEEG VTO DISABLED Figure 15 Local optimization target selection screen for Strateg y 85 idvg_lowMue_HiSIM Page 13 Strategy 36 idvg_highVD_HiSIM The strategy 36 is used for the high VDS ID VG VB characteristics of all the L array devices The aim is to optimize velocity parameters on saturation region of the curve for all VBS Optimized parameters are VMAX VOVER and VOVERP STRATEGY DEFINITION SCREEN Current jdvg_high D_HiSIM Routine Ey IDNG VB 1 MOVER F WVOvERP M MMAX H 2 I Me A Eo 3 7 al 4 oc WA S aR S ll OULD of Parameters 10 of Steps Rows 10 Figure 16 Local optimization strategy definition screen for Strateg y 86 idvg_highVD_HiSIM The Simulation Standard Target Selection QUIT TARGET SELECTION SCREEN Ee Geometry Geometry Geometry Geometry Geometry QUIT Figure 17 Local optimization target selection screen for Stra teg y 86 idvg_highVD_HiSIM Extract r Extract YDSAT PHMABE EE VTO DISABLED Strategy 37 idvd_saturate HiSIM
23. hown in Table 1 Geometry Selection As mentioned above we have three group of device geometry that will be used separately depending on the kind of parameters that will be extracted The Long and Wide device used for mobility flat band voltage and substrate impurity concentration parameters extraction The split of the L array should be done according to the Vth dependency on the channel length which can be observed through UTMOST validate routine The L array of devices will be split in two parts depending on what kind of short channel parameters will be optimized Run by SILVACO Process CHOS Temp 27 VTH_meas vs L 0 55 T oot T 17 T T 7 T rrr tet Heas Method Vg Id 100 nA W L Wdraw 10 00 Type PMO y VDS 0 050 0 50 tr Y VBS start 0 000 H ayw VBS step 0 250 AAA S 0 45 L if ig w n J gt a Sesi tr cs a f ie T 0 40 SON Me 4 x f P Yk K l t i pa hy hs Ni 4 q r 0 35 L 4 k oo a 2 a 0 30 ees J 0 25 f f r l 1 1 es Te 1 fi ptt 1 L Ll 2 1 0 1 2 10 10 10 10 10 16 44 21 f SEP 3 2 v 18 7 1 Ldraw Microns SILVACO Intemational Figure 1 VIH dependence on L UTMOST routine Validate July 2002 Parameter _ Description tits faut VERSION HiSIM Model version number SmartSpice specific a te Technological parameters rox ommes OOO y T EO mCi w o f gate overap width SOS om Ci XPOLYD_ difference between gate poly and design lengt
24. hs om CC mow reightofthe gatepoys mid RD Draincontactresstance o Z oO oOo o oo Vwa 86 Temperature dependence parameters BG TMP1 bandgap namowing 90 25E 6 BG TMP2 bandgap narowing eV K 2 100E 9 3143 3 3 gt Quantum effect parameters QME1 QME2 QME3 Coefficient for qua ntum mechanical effect 40E 12 300E 12 Coefficient forquantum mechanical effect Coefficient forquantum mechanical effect lt lt l tt Poly depletion effect parameters PGD1 PGD2 PGD3 10E UJ strength of poly depletion threshold voltage of poly depletion Vdsdependence of poly depletion Short Channel effect parameters PARL1 PARL2 depletion width of channel contact junction m sca shovtchannelcoemciene2 O O y 5 rorcnannercoeticem3 Cm o r sorcnannelcoeticent torpet v o r2 morcnanneicoeticem2torponet v o rs ShortchannelcoeficientSforpockst SS vm o Narow channel Threshold voltage reduction poremtm MUEPH2 mobility reduction ee ee WO minimum gate width log cm strength of lateral electric field gradient ii Mobility WJ k UJ 50E cm Vs 300 cm Vis VDSO drain voltage for extractions the low field mobility MUEC BO MUEC B1 Coulomb scattering Coulomb scattering Table continued on page 10 July 2002 Page 9 The Simulation Standard parameter Description uit aut cmv Wem 30063 cn oe 1 5 MUEPH1 phonon scattering MUETMP temperature depend
25. low and high VDS First step optimized flat band voltage VFBC on the Large and Wide device for low and high VDS Second step is used to optimized reverse short channel effect dependency on VDS SCP2 This is done on middle devices of the L array for low and high VDS As mentioned above in geometry selection section the middle group is not the same for low VDS and high VDS Third step is used to optimized standard short channel effect dependency on VDS SC2 Optimizations are performed on short devices for low and high VDS STRATEGY DEFINITION SCREEN Current idvg_high T_HiSIM Routine je IDNG VB 1 ff MFBC i i H f 2 f 5crz 3 f se 4 ry E Hi Wi I 5 P ae ne Rm F of Parameters 10 of Steps Rows 7 Figure 10 Local optimization strategy definition screen for Stra teg y 83 idvg_highVT_HiSIM Target Selection QUIT TARGET SELECTION SCREEN a co Geometry Geometry Geometry Current jdvg_short_HiSIM Routine 2 IDNG VB 1 PARL M sca 8G H 2 PARL Mosa sc H 3 PARL r isa 8c 4 PARL Msa M SG 5 PARL M isc sc of Parameters 110 of Steps Rows 7 Target Selection QUIT Figure 8 Local optimization strategy definition screen for Strateg y 82 idvg_short_HiSIM TARGET SELECTION SCREEN so oo oreren oree oe i i Geometry Geometry Geometry Geometry Geometry QUIT Fig
26. modes in FT_CE routine During the Linear IC or Log IC modes of operation UTMOST automatically iterates the base current and measures the collector current until collector current is within the bias error percentage defined in the setup screen Figure 1 For the low collector currents the majority of the base current will leak to the ground and the bias iteration will fail to reach to the targeted collector current value f aC MEASUREMENT SCREEN Routine Of Setups i Setup 1 Integ Time Medium Pulse Setup FIT VARS Hold Time ms p Delay Timeyms o Bias sweep YBE VCE const MEASUREMENT VARIABLES WCE_start i 3 WCE_points i b fae mje j m jt w N ad Figure 1 FT_CE routine measurement setup screen In order to solve this issue the VBE VCE constant or VBE VCB constant measurement sweep modes were developed for the FT_CE routine If one of these modes are selected the FT_CE routine will search for the bias currents within the previously measured DC bias files These bias files contain the gummel IC and IB data plot data Figure 2 The gummel plot data is automatically stored in a file named bias xxx when data is measured July 2002 Page 17 simulated or retrieved from a logfile using the Gummel routine routine 14 The bias file should be generated using the Gummel routine for each VCE bias that will be used for the FT_CE measurements
27. ocal optimization geometry selection screen for Strateg y 84 idvg_highVT2_HiSIM step 1 amp 2 Strategy 35 idvg_lowMue_HiSIM This one is dedicated to mobility parameters optimiza tion Optimizations are going to be performed on the Current of ID VG on the Large and Wide device Many different iteration are necessary due to the strong correlation of those parameters effects in the different area of the characteristics First step will be used for a rough extraction of MUECB0O MUECB1 MUEPH1 and MUESRI1 in sub threshold region for a low VDS and OV VBS sweep_start sweep_stop 1 Second step will refine MUECB1 in subthreshold region for low VDS and all VBS Third step is used for MUEPH1 optimization this will be done just after threshold region for high VDS and all VBS Fourth step is used for MUESR1 optimization in saturation region for high VDS and all VBS Fifth step refine MUECBO MUECB1 in subthreshold region for low VDS and all VBS Sixth step refines MUEPH1 in just above threshold region for high VDS and all VBS Last step refines MUEPH1 and MUESR 1 together in saturation region for high VDS and all VBS July 2002 LOCAL OPTIMIZATION SCREEN idvg_lowMue_HiSIM Strategy 35 IDVG VB A Vv Define Strategy Select strategy Define Printout PRINT Print File Zexportmomesfrancois_localWORK UTMOSTivyper_datafutmost_ QUIT Figure 14 Local optimization strategy screen for Stra te
28. r 4 f scr Pr Iscps i i i I 5 of Parameters 110 of Steps Rows 7 Target Selection QUIT Figure 6 Local optimization strategy definition screen for Strategy 31 idvg_middle_HiSIM TARGET SELECTION SCREEN BD a ea laa i Geometry Geometry Geometry Geometry Geometry QUIT Extract x Extract VDSAT DINABLED ie DISABLED Figure 7 Local optimization target selection screen for Strategy 31 idvg_middle_HiSIM Strategy 32 idvg_short_HiSIM As the previous ones the strategy 32 will optimize the Current of ID VG characteristics The aim of this strategy is to optimize the short channel parameters PARL2 SC1 and SC3 As standard short channel effect is much more sensible on very small devices the short devices part of the L array will be used for optimization Region of interest is subthreshold region for all VBS and low VDS As with previous strategy several iteration of the same step are required STRATEGY DEFINITION SCREEN Strategy 33 idvg_highVT_HiSIM Strategy 33 aims to take into account VDS influence on the different effects we have studied previously Flat band voltage standard short channel and reverse short channel effects This strategy as the previous ones will perform optimization on the Current of ID VG characteristics Region of interest is sub threshold for all VBS values but this time optimizations are going to be performed at
29. ries down to 0 lum and a unified description of devices characteristics for all bias conditions It has been implemented in Silvaco Spice Simulator SmartSpice and in our current extraction software UTMOST III This article presents an efficient extraction procedure for HiSIMv1 0 parameters using UTMOST III This procedure will lead to a model card accurate for a wide range of geometries It is widely inspired from the one proposed by STARC in its AHiSIM1 0 User s Manual but it has been adapted and optimized for UTMOST III users Data Collection and Initial Parameter The extraction procedure presented in this article requires DC measurement that can be obtained using the BSIM3_MG routine on a Large and Wide device and an L array of devices See articles for BSIM3_MG extraction routine in the previous issues of the Simulation Standard In this case BSIM3_MG should be used as a measurement routine only Following STARC recommendations IDS vs VGS measurements should be performed for VDS 50mV and 1V IDS vs VDS measurements will be performed for VBS OV and 1V For those last characteristics the Voffset value which is used to calculate the first VGstart value Vgstart VTextracted Voffset defaults to 0 2V The recommended number of points per sweep in the BSIM3_MG routine is 51 and the number of VGS steps and VBS steps are 5 In addition to be able to extract Quantum Mechanical Effect parameters and Poly Deple
30. s of this example plusan archive of previous Hints Tips and Solutions www silvaco com The Simulation Standard 9 Your Investment in Sivaco Is SOLID asa Rock While others faltered Silvaco stood SOUD for 15 years Slvaco isNOT forsale and will remain fiercely independent Don t lose sleep as your investment and partnership with Silvaco will only grow Silvaco Japan INTERNATIONAL PERE vase colm USA HEADQUARTERS Sse r Silvaco Intemational Silvaco Taiwan 4701 Patrick Henry Drive twsa les silva co com Building 2 Silvaco Singapore Santa Clara CA 95054 sgsales silvaco com USA Silvaco UK Phone 408 567 1000 uksales silvaco com Fax 408 496 6080 Silvaco France salesGsilvaco com frsales silvaco com www silvaco com Siivaco Germany desales silvaco com Products Licensed through Silvaco or e ECAD
31. sistances BSIM3SOI v3 0 Model Charactenstics File Edit View Options Zoom 7 teaei Bees eth self ree ee 0 0 1 0 7 owithout self heati ing e e B eUT 0 008 0 006 T 9 0 004 0 002 Ea OV 1V 2V 3V vds V Left Zoom Left Left Edit Object Ctrl Lef Highlight Signal Middle Undo Previous Zoom Operation Figure 1 Selfheating effect on output characteristics SOIMO D 0 File Edit View Options Zoom 7 laBel 6 4 4 4 ml al vl el 1 igcmod 0 igcmod igbmod 20p Se O 0V 0 2V 0 4V 0 6V 0 8V 1 0V 1 2V vg A Left Zoom Left Left Edit Object Ctrij Left Highlight Signal Middle Undo Previous Zoom Operation Figure 2 Gate tunneling currents SOIMOD 0 The Simulation Standard Page 4 a eas one er vee Tew cco cca oar cr ac cr x reopy csomn cto asp cow ae PBSWG MJSWG To XB T XDIF XREC xTUN NDIF LDIFO TCJ SWG TPBSWG NTRECF NTRECR Table 3 New binning model parameters References 1 BSIM3SOI PD v2 2 User s Manual 1999 Department of EEC S University of Califomia Berkeley 2 BSIM3SOI FD v2 1 Users Manual 1999 Department of EEC S University of Califomia Berkeley 3 SmartSpice Modeling Manual Volume 3 File Edit View Options Zoom 7 a B s 4 4 ml al vl el Ons Ins 2ns time Left Zoom Left Left Edit Object Ctri Lef Highlight Signal Middle Undo Previous Zoom Operation Figur
32. tectures without influence on the accuracy Continued on page 2 INSIDE A New Surface Potentials Based MOSFET Model HiSIM HISIM version 1 1 Model Released in UTMOST III Calendar of Events Hints Tips and Solutions SILVACO INTERNATIONAL Major Features BSIM3SOI v3 0 has the following new features relative to BSIM3SOI PD v2 1 Real floating body simulation in both C V and I V The body potential is determined by the balance of all the body current components Enhancements in the threshold voltage and bulk charge formulation of the high positive body bias regime An improved parasitic bipolar current model This includes enhancements in the various diode leakage components second order effects high level injection amp early effect diffusion charge equation and temperature dependence of the diode junction capacitance An improved impact ionization current model The contribution from BJT current is also modeled by the parameter FBJTII Instance parameters PDBCP PSBCP AGBCP AEBCP NBC are provided to model the parasitics of devices with various body contact and isolation structures An external body node the 6th node and other improvements are introduced to facilitate the modeling of distributed body resistance Self heating an external temperature node the 7th node is supported to facilitate the simulation of thermal coupling among neighboring devices A unique SOI low frequenc
33. tegies by utilizing the different ALL_DC routines The operation of the local optimization is explained in the UTMOST User Manual Strategy 30 idvg_ large HiSIM This strategy is used for the wide W and long L device only As it can be seen in the figure 3 it will optimize the Current of ID VG characteristics The Wide Wand long L device should be selected in the Geometry Selection Screen figure 5 for each row in this strategy The ID VG characteristics of this device wide W and long L should be present in the graphics screen The first row of the optimization is used for the substrate impurity concentration and the flat band voltage parameters optimization The sweep start is set to land sweep stop to 5 This will ensure that these parameters in row 1 will be optimized for VBS values This Optimization is done only for low VDS We have fixed the current from 1E 12A to 10 of maximum current because the region of interest is the subthreshold region Figures 3 and 4 show that the second row is exactly the same than the first one It is used to iterate this optimization July 2002 Page 11 STRATEGY DEFINITION SCREEN jdvg _larye_HiSIM Routine 2 IDNG VB M MFBC M NSUBC M MFBC M NSUBC 1 2 3 4 5 I Target Selection QUIT Figure 3 Local optimization strategy definition screen for Strateg y 80 idvg_large_HiSIM TARGET SELECTION SCREEN VBS stop Current Min
34. tion effect parameters Intrinsic Gate capacitance vs Vgs should be measured on Large and Wide device The typical number of geometries used for model parameter extraction is 10 There should be a large device with wide W and long L to avoid short channel or narrow width effects to extract the root parameters as mobility parameters substrate impurity concentration and flat band volt age An array of short L devices will be used to extract short channel parameters It has to be noticed that HiSIM includes two kind of short channel The Simulation Standard Page 8 effect parameters One for the standard short channel effect and the other for the reverse short channel effect We will see later in this section how this two effects lead to separate the L array of devices in two parts depending on which parameters need to be optimized Restrictions This article gives a procedure to extract most of HiSIMv1 0 parameters However some effects are not taken into account their corresponding parameters extraction will require another article in a future Simulation Standard Those parameters are Narrow channel Channel length modulation Substrate Gate and GIDL current 1 f Noise parameters Model Parameters To get significant results for an HiSIMv1 0 extraction the initial set of values for HiSIM parameters is important UTMOST III provides you a default model card that should be used as a starting point Detail of this model card is s
35. ure 9 Local optimization target selection screen for Stra teg y 82 idvg_short_HiSIM Extract a s Extract VDSAT DISABLED eS DISABLED July 2002 Page 12 Go e e e E a a E a a A Extract s Extract VDSAT DISABLED DISABLED QUIT Figure 11 Local optimization target selection screen for Strateg y 83 idvg_highVT_HiSIM _ Semet Geometry _Semety Geometry Strategy 34 idvg_highVT2_HiSIM As preceding strategy the aim of strategy 34 is to optimize short channel effect dependency to VDS While strategy 33 was a rough extraction of SC2 and SCP2 this one has a refinement purpose This is obtained by optimizing the Current of ID VG characteristics in subthreshold region for high VDS only The first step optimized SCP2 on middle devices while the second step optimized SC2 on short devices As for previous strategies those steps are iterated Check that short and middle devices groups are the ones defined for high VDS The Simulation Standard Current M iscp2 M Beo M se STRATEGY DEFINITION SCREEN idvg_high T2_HiSIM Routine 2 IDVG B 1 2 3 ff Scr 4 5 of Parameters 10 of Steps Rows 7 Target Selection QUIT Figure 12 Local optimization strategy definition screen for Strate g y 84 idvg_highVT2_HiSIM GEOMETRY SELECTION SCREEN GEOMETRY SELECTION SCREEN 10 00 SET ALL CLEAR QUIT QUIT Figure 13 L
36. v Jo nomo sweotingpoometernromeaue fn ca AIGC Parameter for lgs lgd Igcs Igcd i ae ia 0 43 NMOS 0 31 PMOS BIGC Parameter forlgcsand Igcd F s 2 g 5 0 054 NMOS mV 1 0 024 PMOS CIGC Parameter for lgcsand Igcd 0 075 NMOS 0 03 PMOS AIGSD Parameter for lgsand lgd ie a g 5 0 43 NMOS 0 31 PMOS BIG SD Parameter for lgsand lgd F s 2 g 5 0 054 NMOS mV 1 0 024 PMOS C IG SD Parameter for lgsand lgd 0 075 NMOS 0 03 PMOS DLCIG S D ovenap length for Igs Igd UNT NIG C Parameter for lgs Igd lgcs lgcd PO XEDGE Factor forthe gate oxide thichness in the dource drain ovenap regions Exponent forthe TOX ratio TO XREF Targert oxide ticknessin gate tunnelling Pom 25 O 2 5e 9 TOXQM Equivalent oxide tickness in gate tunnelling ao Table 1 Additional parameters to BSIM3SOI v2 PD and FD for BIM 3S01 v3 0 model O Tl ojojo A The logfile contains the warnings concerning models Fatal errors are always displayed on screen and make and devices as well as the number of fatal errors and the simulation stop A summary is also always clipped parameters It is created when PARAMCHK gt 0 displayed on screen giving the number of fatal errors If the logfile cannot be created lack of disk space no write and clipped parameters issi bs j ill l permissions etc warnings will be sent to screen SmartSpice includes two algorithms for the BYPASS If it is created the logfile is named after the n
37. y noise model including a new excess noise resulting from the floating body effect Width dependence of the body effect is modeled by parameters K1 K1W1 K1W2 Improved history dependence of the body charges with two new parameters FBODY DLCB An instance parameter vbsusr is provided for users to set the transient initial condition of the body potential The new charge thickness capacitance model introduced in BSIM3v3 2 CAPMOD3 is included Gate to Body tunneling current A body halo sheet resistance A minimum width fro thermal resistance calculation A higher limit for exponential functions BSIM3SOI v3 0 has the following new features relative to BSIM3SOI FD v2 2 Supports external body bias and backgate bias a total of 5 external nodes Improved self heating implementation New depletion charge model EBCI introduced for better accuracy in capacitive coupling prediction Single I V expression to guarantee continuities of Ids Gm and Gds and their derivatives for all bias conditions The Simulation Standard New version BSIM3SOI v3 0 includes the binning feature to enhance the model flexibility and fixes some bugs found in the previous BSIM3SOI PD v2 2 3 New features have been added in BSIM3SOI v3 0 model Gate to Channel current component Igc splitted into two components Igcs and Igcd Gate to Source Drain tunneling currents Igs and Igd between the gate and the source drain diffusion
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