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MCS® 51 Microcontroller Family User`s Manual

1. Mode 0 1MHZ 12MHZ X Mode 2 Max 375K 12 MHZ 1 x x Modes 1 3 62 5K 12 MHZ 1 0 2 19 2K 11 059 MHZ 1 0 2 9 6K 11 059 MHZ 0 0 2 4 8K 11 059 MHZ 0 0 2 2 4K 11 059 MHZ 0 0 2 1 2K 11 059 MHZ 0 0 2 137 5 11 986 MHZ 0 0 2 110 6 MHZ 0 0 2 110 12 MHZ 0 0 1 Figure 15 Timer 1 Generated Commonly Used Baud Rates Using Timer 2 to Generate Baud Rates 11 Note then the baud rates for transmit and receive can be simultaneously different Setting RCLK and or In the 8052 Timer 2 is selected as the baud rate genera TCLK puts Timer 2 into its baud rate generator mode tor by setting TCLK and or RCLK in Y2CON Figure as shown in Figure 16 NOTE OSC FREQ IS DIVIDED BY 2 NOT 12 270252 14 Figure 16 Timer 2 in Baud Rate Generator Mode 3 16 intel The baud rate generator mode is similar to the auto re load mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software Now the baud rates in Modes 1 and 3 are determined by Timer 2 s overflow rate as follows Timer 2 Overflow Rate 16 The Timer can be configured for either timer or counter operation In the most typical applications it is configured for timer operation C T2 0 Tim er operation is a little different for Timer 2 when it s being used as a baud rate generator Normally as a timer it would incr
2. FF FO F7 E8 EF EO E7 D8 DF Do D7 88 87 AB AF AO A7 98 9F s EPA SS T s TMOD THO TH Po SP pH PON er Figure 2 SFR Indicates Resident in 8052s not in 8051s Note that not all of the addresses are occupied Unoc cupied addresses are not impiemented on the chip Read accesses to these addresses will in general return random data and write accesses will have no effect User software should not write Is to these unimple mented locations since they may be used in future MCS 51 products to invoke new features In that case the reset or inactive values of the new bits will always be 0 and their active values will be 1 The functions of the SFRs are outlined below ACCUMULATOR ACC is the Accumulator register The mnemonics for Accumulator Specific instructions however refer to the Accumulator simply as A B REGISTER The B register is used during multiply and divide oper ations For other instructions it can be treated as anoth er scratch pad register PROGRAM STATUS WORD The PSW register contains program status information as detailed in Figure 3 STACK POINTER The Stack Pointer Register is 8 bits wide It is incre mented before data is stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the Stack Pointer is initialized to 07H after
3. Reception is initiated by a detected 1 to O transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is imme diately reset and 1FFH is written into the input shift register Resetting the divide by 16 counter aligns its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to look ing for another 1 to 0 transition This is to provide re jection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit regis ter it flags the RX Control block to do one last shift load SBUF and and set RI The signal to load SBUF and RBS and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2
4. hardware generated LCALL pushes the contents of the Program Counter onto the stack but it does not save the PSW and re loads the PC with an address that depends on the source of the interrupt being vectored to as shown be low Vector Source Address 0003H TFO 000BH IE1 0013H TF1 001BH RI TI 0023H TF2 EXF2 002BH Execution proceeds from that location until the RETI instruction is encountered The RETI instruction in forms the processor that this interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted program continues from where it left off Note that a simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress 3 25 External Interrupts The external sources can be programmed to be level ac tivated or transition activated by setting or clearing bit IT1 or ITO in Register TCON If ITx 0 external interrupt x is triggered by a detected low at the INTx pin If ITx 1 external interrupt x is edge triggered In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx then requests the interrupt Since the external interrupt pins are sampled once each machine cycle an input high or low should ho
5. 1 ORL data 2 1 0100 ORL direct lt direct A ORL direct data Bytes Cycles Encoding Operation 3 2 ORL direct direct data 2 62 immediate data intel ORL C lt src bit gt Function Description Example ORL C bit Bytes Cycles Encoding Operation ORL C bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Logical OR for bit variables Set the carry flag if the Boolean value is a logical 1 leave the carry in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Set the carry flag if and only if P1 0 1 7 1 or OV 0 MOV 1 0 LOAD CARRY WITH INPUT PIN P10 ORL 7 OR CARRY WITH THE BIT 7 ORL CARRY WITH THE INVERSE OF OV 2 2 111 0010 ORL E C V bit 2 2 ORL V bit 2 63 intel A 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET POP direct Function Pop from stack Description contents of the internal RAM location addressed by the Stack Pointer is read and the Stack Pointer is decremented by one The value read is then transferred to the directly ad dressed byte indicate
6. Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 ANL A 2 1 ANL A direct 1 1 o101 0110 ANL 2 1 ANL A lt A data 2 1 ANL direct direct A A 2 33 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ANL direct 4 data Bytes 3 Cycles 2 Encoding immediate data Operation ANL direct direct data ANL C lt sre bit gt Function Logical AND for bit variables Description If the Boolean value of the source bit is a logical O then clear the carry flag otherwise leave the carry flag in its current state A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct addressing is allowed for the source operand Example Set the carry flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV 1 0 LOAD CARRY WITH INPUT PIN STATE ANL 7 AND CARRY WITH ACCUM 7 ANL C OV AND WITH INVERSE OF OVERFLOW FLAG ANL Bytes 2 Cycles 2 Encoding bit address Operation ANL C A bit ANL C bit Bytes Cycles 2 Encoding Operation ANL C 0 A 1 bit intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CJNE lt dest b
7. 1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 DJNZ decrement and jump if not zero e g DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of Port X CLR PX Y clear bit Y of Port X SETBPX Y set bit Y of Port X It is not obvious that the last three instructions in this list are read modify write instructions but they are They read the port byte all 8 bits modify the addressed bit then write the new byte back to the latch The reason that read modify write instructions are di rected to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor and interpret it as a O Reading the latch rather than the pin will return the correct value of 1 ACCESSING EXTERNAL MEMORY Accesses to external memory are of two types accesses to external Program Memory and accesses to external Data Memory Accesses to external Program Memory use signal PSEN program store enable as the read strobe Accesses to external Data Memory use RD or WR alternate functions of P3 7 and P3 6 to strobe the memory Refer to Figures 36 through 38 in the Internal Timing section Fetches from
8. 1 O Configurations Figure 4 shows a functional diagram of a typical bit latch and 1 O buffer in each of the four ports The bit latch one bit in the port s SFR is represented as a Type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read a port acti vate the read latch signal and others activate the read pin signal More about that later As shown in Figure 4 the output drivers of Ports O and 2 are switchable to an internal ADDR and ADDR DATA bus by an internal CONTROL signal for use in external memory accesses During external memory ac cesses the P2 SFR remains unchanged but the PO SFR gets 1s written to it Also shown in Figure 4 is that if a P3 bit latch contains a 1 then the output level is controlled by the signal labeled alternate output function The actual P3 X pin level is always available to the pin s alternate input function if any Ports 1 2 and 3 have internal pullups Port O has open drain outputs Each I O line can be independently used as an input or an output Ports 0 and 2 may not be used as general purpose when being used as the ADDR DATA BUS To be used as an input
9. CPL Pl CPL 1 2 will leave the port set to 5BH 01011011B Bytes 1 Cycles 1 Encoding 1011 0011 Operation CPL intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CPL bit Bytes 2 Cycles 1 Encoding bit address Operation CPL bit lt 71 bit DA A Function Decimal adjust Accumulator for Addition Description DAA adjusts the eight bit value in the Accumulator resulting from the earlier addition of two variables each in packed BCD format producing two four bit digits Any ADD or ADDC instruction may have been used to perform the addition If Accumulator bits 3 0 are greater than nine xxxx1010 xxxx1111 or if the AC flag is one six is added to the Accumulator producing the proper BCD digit in the low order nibble This internal addition would set the carry flag if a carry out of the low order four bit field propagat ed through all high order bits but it would not clear the carry flag otherwise If the carry flag is now set or if the four high order bits now exceed nine 1010xxxx 111xxxx these high order bits are incremented by six producing the proper BCD digit in the high order nibble Again this would set the carry flag if there was a carry out of the high order bits but wouldn t clear the carry The carry flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected All of this occu
10. rel INC byte Function Increment Description INC increments the indicated variable by 1 An original value of OFFH will overflow to No flags are affected Three addressing modes are allowed register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins Example Register 0 contains 7EH 011111110B Internal RAM locations and 7FH contain OFFH and 40H respectively The instruction sequence INC RO INC RO INC RO will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding respective ly OOH and 41H INC A Bytes 1 Cycles 1 Encoding Operation INC 1 2 44 intal INC INC INC Rn Bytes Cycles Encoding Operation direct Bytes Cycles Encoding Operation Ri Bytes Cycles Encoding Operation INC DPTR Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 INC 1 2 1 INC direct lt direct 1 direct address 1 1 INC lt RD 1 Increment Data Pointer Increment the 16 bit data pointer by 1 A 16 bit increment modulo 216 is performed an overflow of the low order byte of the data pointer DPL from OFFH to 00H will increment the high order
11. 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RXD More About Modes 2 and 3 Eleven bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On trans 3 20 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 mit the 9th data bit 8 can be assigned the value of 0 or 1 On receive the 9th data bit goes into RB8 in SCON The baud rate is programmable to either or 1 4 the oscillator frequency in Mode 2 Mode 3 may have a variable baud rate generated from either Timer 1 or 2 depending on the state of TCLK and RCLK Figures 19 and 20 show a functional diagram of the serial port in Modes 2 and 3 The receive portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission com mences at S1P1 of the machine cycle
12. 2 Q bit UART fosc 64 or tose 32 3 9 bit UART variable enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then Ri will not be activated if the received 9th data bit 888 is 0 In Mode 1 if SM2 1 than Rt will not be activated if a valid stop bit was not received In Mode 0 SM2 should be 0 enables serial reception Set by software to enable reception Clear by software to disable reception TBS _ is the Sth data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired in Modes 2 and 3 is the 9th data bit that was received in Mode 1 if SM2 0 is the stop bit that was received In Mode 0 RB8 is not used is transmit interrupt fiag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software is receive interrupt flag Set by hardware at the end of the Bth bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see SM2 Must be cleared by software Figure 14 SCON Serial Port Control Register Baud Rates The baud rate in Mode 0 is fixed Mode 0 Baud Rate Oscillator Frequency The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON If SMOD 0 which is the value on reset the baud rate the oscillator frequency I
13. User software should never write Is to unimplemented bits since they may be used in future MCS 51 products IDLE MODE An instruction that sets PCON O causes that to be the last instruction executed before going into the Idle mode In the Idle mode the internal clock signal is gated off to the CPU but not to the Interrupt Timer and Serial Port functions The CPU status is preserved in its entirety the Stack Pointer Program Counter Program Status Word Accumulator and all other reg isters maintain their data during Idle The port pins hold the logical states they had at the time Idle was activated ALE and PSEN hold at logic high levels There are two ways to terminate the Idle Activation of any enabled interrupt will cause PCON O to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruc tion to be executed will be the one following the in struction that put the device into Idle 270252 22 Figure 27 Idle and Power Down Hardware 3 28 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 MSB LSB Gro PD o Position PCON 7 Symbol Name and Function Double Baud rate bit When setto a 1 and Timer 1 is used to generate baud rate and the Serial Port is used in modes 1 2 or 3 Reserved Reserved Reserved Generai purpose flag bit General purpose flag bit Power Down bit Setting this bit activates powe
14. sor a 2 0 et NE STARTBIT 316 RESET ERRE TOP BIT RECEIVE SHIFT 270252 16 Figure 18 Serial Port Mode 1 TCLK RCLK and Timer 2 are Present in the 8052 8032 Only Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission actually commences at SiP1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit 3 19 times are synchronized to the divide by 16 counter not to the write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse oc curs one bit time after that intel As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover after write to SBUF
15. 0 6 A0 C 7 2 66 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET RR A Function Rotate Accumulator Right Description eight bits in the Accumulator are rotated one bit to the right Bit O is rotated into the bit 7 position No flags are affected Example The Accumulator holds the value 5 11000101B The instruction RR A leaves the Accumulator holding the value OE2H 11100010B with the carry unaffected Bytes 1 Cycles 1 Encoding 0000 0011 Operation RR 1 0 6 lt 0 Function Rotate Accumulator Right through Carry flag Description eight bits in the Accumulator and the carry flag are together rotated one bit to the right Bit O moves into the carry flag the original value of the carry flag moves into the bit 7 position No other flags are affected Example Accumulator holds the value OC5H 11000101B the carry is zero The instruction RRC A leaves the Accumulator holding the value 62 01100010B with the carry set Bytes 1 Cycles 1 Encoding 0001 0011 Operation RRC lt An 1 n 0 6 7 lt 2 67 intel SETB lt bit gt Function Description Example SETB C Bytes Cycles Encoding Operation SETB bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Set Bit SETB sets the indicated bit to one SETB c
16. 2 the output buffer holds the value it saw during the previous Phase 1 Consequently the new value in the port latch won t actually appear at the output pin until the next Phase 1 which will be at S1P1 of the next machine cycle See Figure 39 in the Internal Timing section If the change requires a 0 to 1 transition in Port 1 2 or 3 an additional pullup is turned on during S1P1 and S1P2 of the cycle in which the transition occurs This is done to increase the transition speed The extra pullup can source about 100 times the current that the normal pullup can It should be noted that the internal pullups are field effect transistors not linear resistors The pull up arrangements are shown in Figure 5 In HMOS versions of the 8051 the fixed part of the pullup is a depletion mode transistor with the gate wired to the source This transistor will allow the pin to source about 0 25 mA when shorted to ground In parallel with the fixed pullup is an enhancement mode transistor which is activated during 1 whenever the port bit does a 0 to 1 transition During this interval if the port pin is shorted to ground this extra transistor will allow the pin to source an additional 30 mA 2 OSC PERIODS HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 6 A HMOS Configuration The enhancement mode transistor is turned on for 2 osc periods after makes a 0 to 1 transition Vcc 2 OSC PERIODS INPUT e DATA
17. 34H 3 2 0000 immed data15 8 immed data7 0 MOV PTR data s o DPH DPL data 5 3 O data7 9 2 56 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOVC A A lt base reg gt Function Move Code byte Description The MOVC instructions load the Accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned eight bit Accumu lator contents and the contents of a sixteen bit base register which may be either the Data Pointer or the PC In the latter case the PC is incremented to the address of the following instruction before being added with the Accumulator otherwise the base register is not al tered Sixteen bit addition is performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected Example value between O and 3 is in the Accumulator The following instructions will translate the value in the Accumulator to one of four values defined by the DB define byte directive REL_PC INC A MOVC A A PC RET DB 66H DB 779 88H DB 99H If the subroutine is called with the Accumulator equal to 01H it will return with 77H in the Accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the from the table the corresponding number would be added to the Accumulator instead MOV
18. ADD A 99H DA will leave the carry set and 29H the Accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 1 DA contents of Accumulator are BCD IF A3 0 gt 9 V 1 THEN A3 0 A3 9 6 AND IF A gt 9 V KO 11 THEN 47 4 6 2 40 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DEC byte Function Decrement Description The variable indicated is decremented by 1 An original value of 00H will underflow to OFFH No flags are affected Four operand addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Register 0 contains 7FH 01111111B Internal RAM locations 7EH and 7FH contain 00H and 40H respectively The instruction sequence DEC RO DEC DEC GRO will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to OFFH and 3FH DEC A Bytes Cycles 1 Operation DEC E A 1 DEC Rn Bytes 1 Cycles 1 Operation DEC Rn lt Rn 1 2 41 intel DEC direct Bytes Cycles Encoding Operation DEC Bytes Cycles Encoding Operation DIV AB Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S
19. AND INSTRUCTION SET JMP A DPTR Function Description Example Bytes Cycles Encoding Operation Jump indirect Add the eight bit unsigned contents of the Accumulator with the sixteen bit data pointer and load the resulting sum to the program counter This will be the address for subsequent instruc tion fetches Sixteen bit addition is performed modulo 216 a carry out from the low order eight bits propagates through the higher order bits Neither the Accumulator nor the Data Pointer is altered No flags are affected even number from O to 6 is in the Accumulator The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP__TBL MOV JMP JMP TBL AJMP AJMP AJMP AJMP DPTR JMP__TBL A DPTR LABELO LABEL LABEL2 LABEL3 If the Accumulator equals 04H when starting this sequence execution will jump to label LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address 1 2 JMP lt DPTR 2 48 intel JNB bit rel Function Description Example Bytes Cycles Encoding Operation JNC rel Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Jump if Bit Not set If the indicated bit is a zero branch to the indicated address otherwise proceed with the next instruc
20. GUIDE AND INSTRUCTION SET DEC direct lt direct 1 1 1 DEC RD 1 Divide DIV AB divides the unsigned eight bit integer in the Accumulator by the unsigned eight bit integer in register B The Accumulator receives the integer part of the quotient register B receives the integer remainder The carry and OV flags will be cleared Exception if B had originally contained 00H the values returned in the Accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case The Accumulator contains 251 OFBH or 11111011B and B contains 18 12H or 00010010B The instruction DIV AB will leave 13 in the Accumulator or 00001101B and the value 17 11H or 00010001B in B since 251 13 X 18 17 Carry and OV will both be cleared 1 4 ERTTIEIETS DIV 15 Bro A 2 42 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DJNZ lt byte gt lt rel addr gt Function Decrement and Jump if Not Zero Description DJNZ decrements the location indicated by 1 and branches to the address indicated by the second operand if the resulting value is not zero An original value of OOH will underflow to OFFH No flags are affected The branch destination would be computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following inst
21. HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 STATE 5 STATE 6 peje STATE 3 le p P2 P1 2 p 2 1 2 p1 P2 2 1 2 2 270252 31 Figure 38 External Data Memory Write Cycle STATE 5 STATE 6 STATE 1 STATE 21 STATE 3 STATE 4 STATE 5 P1 2 2 2 Pi 2 1 2 1 2 1 2 1 2 P1 P2 P3 P1 P2 INPUTS SAMPLED RST RST MOV PORT SRC OLD DATA NEW DATA MODE 0 Figure 39 Port Operation 270252 32 3 35 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 ADDITIONAL REFERENCES The following application notes and articles are found in the Embedded Applications handbook Order Number 270648 1 AP 125 Designing Microcontroller Systems for Electrically Noisy Environments 2 AP 155 Oscillators for Microcontrollers 3 AP 252 Designing with the 80C51BH 4 AR 517 Using the 8051 Microcontroller with Resonant Transducers 52 5458 Hardware Description
22. READ PORT PIN 270252 7 CHMOS Configuration pFET 1 is turned on for 2 osc periods after makes a 0 to 1 transition During this time pFET 1 also turns on pFET 3 through the inverter to form a latch which holds the 1 pFET 2 is also on Figure 5 Ports 1 And 3 HMOS And CHMOS Internal Pullup Configurations Port 2 is Similar Except That It Holds The Strong Pullup On While Emitting 1s That Are Address Bits See Text Accessing External Memory In the CHMOS versions the pullup consists of three pFETs It should be noted that an n channel FET nFET is turned on when a logical 1 is applied to its gate and is turned off when a logical 0 is applied to its gate A p channel FET pFET is the opposite it is on when its gate sees a O and off when its gate sees a 1 in Figure 5 is the transistor that is turned on for 2 oscillator periods after a O to 1 transition in the port latch While it s on it turns on pFET3 a weak pull up through the inverter This inverter and pFET form a latch which hold the 1 Note that if the pin is emitting a 1 a negative glitch on the pin from some external source can turn off pFET3 causing the pin to go into a float state pFET2 is a very weak pullup which is on whenever the nFET is off in traditional CMOS style It s only about the strength of pFET3 Its function is to restore a 1 to the pin in the event the pin had a 1 and lost it to a glitch Port Loading and Inter
23. XRL A data Bytes Cycles Encoding Operation direct A Bytes Cycles Encoding Operation 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 XRL Y Rn 2 1 0110 10101 direct address XRL A A Y direct 1 1 XRL Y Ri 2 1 0100 XRL lt Y data 2 1 XRL direct direct Y A 2 74 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XRL direct data Bytes 3 Cycles 2 Encoding 0011 immediate data Operation XRL direct direct Y data 2 75 8051 8052 80C51 Hardware Description 8051 8052 80C51 Hardware Description CONTENTS PAGE CONTENTS PAGE PORT STRUCTURES AND OPERATION POWER SAVING MODES OF OPERATION 3 1 intel 8051 8052 AND 80C51 HARDWARE DESCRIPTION INTRODUCTION This chapter presents a comprehensive description of the on chip hardware features of the MCS 51 micro controllers Included in this description are The port drivers and how they function both as ports and for Ports 0 and 2 in bus operations The Timer Counters The Serial Interface The Interrupt System Reset The Reduced Power Modes in the CHMOS devices The EPROM versions of the 8051 8052 and 80C51BH The devices under consideration are listed in Table 1 As it becomes unwieldy to be constantly referring to each of thes
24. a programmable 9th data bit and a stop bit 1 Transmit the 9th data bit 8 in SCON can be assigned the value of O or 1 Or for example the parity bit P in the PSW could be moved into TB8 On re ceive the 9th data bit goes into RB8 in Special Functon Register SCON while the stop bit is ignored The baud rate is programmable to either or the oscillator frequency Mode 3 11 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 in all respects except the baud rate The baud rate in Mode 3 is vari able In all four modes transmission is initiated by any in struction that uses SBUF as a destination register Re ception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 3 14 Multiprocessor Communications Modes 2 and 3 have a special provision for multipro cessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB3 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one
25. a reset This causes the stack to begin at location 08H DATA POINTER The Data Pointer DPTR consists of a high byte DPH and a low byte DPL Its intended function is 3 5 to hold a 16 bit address It may be manipulated as a 16 bit register or as two independent 8 bit registers PORTS 0 TO 3 P1 P2 and are the SFR latches of Ports 0 1 2 and 3 respectively SERIAL DATA BUFFER The Serial Data Buffer is actually two separate regis ters a transmit buffer and a receive buffer register When data is moved to SBUF it goes to the transmit buffer where it is held for serial transmission Moving a byte to SBUF is what initiates the transmission When data is moved from SBUF it comes from the receive buffer TIMER REGISTERS Register pairs TLO TL1 and TH2 TL2 are the 16 bit Counting registers for Timer Coun ters O 1 and 2 respectively CAPTURE REGISTERS The register pair RCAP2H RCAP2L are the Cap ture registers for the Timer 2 Capture Mode In this mode in response to a transition at the 8052 s T2EX pin TH2 and TL2 are copied into RCAP2H and RCAP2L Timer 2 also has a 16 bit auto reload mode RCAP2H and RCAP2L hold the reload value for this mode More about Timer 2 s features in a later section CONTROL REGISTERS Special Function Registers IP TMOD TCON T2CON SCON and PCON contain control and status bits for the interrupt system the Timer Counter
26. above result is due to the carry borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR C instruction SUBB A E Rn 2 70 intel SUBB A direct Bytes Cycles Encoding Operation SUBB A Ri Bytes Cycles Encoding Operation SUBB A data Bytes Cycles Encoding Operation SWAP A Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 SUBB C direct 1 1 SUBB A 2 1 SUBB A A C data Swap nibbles within the Accumulator SWAP A interchanges the low and high order nibbles four bit fields of the Accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are affected The Accumulator holds the value 5 11000101B The instruction SWAP A leaves the Accumulator holding the value 5 01011100B 1 1 1 0100 SWAP 3 0 A74 2 71 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET A lt byte gt Function Description Example A Rn Bytes Cycles Encoding Operation XCH A direct Bytes Cycles Encoding Operation Bytes Cycles
27. being input P1 the program will loop at this point until the P1 data changes to 34H 3 2 11 0101 3 IF lt gt direct THEN lt relative offset lt direct 2 35 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CJNE A data rel Bytes 3 Cycles 2 Encoding 1011 immediate data Operation PC PC 3 IF A lt gt data THEN PC PC relative offset IF A lt data THEN 1 ELSE C 0 CJNE Rn data rel Bytes 3 Cycles 2 Encoding 1011 Irrr immediate data Operation PC 3 IF Rn lt gt data THEN PC PC relative offset IF Rn lt data THEN E 1 C 0 ELSE CJNE Ri data rel Bytes 3 Cycles 2 Encoding 10110111 immediate data Operation PC 3 IF Ri lt gt data THEN relative offset IF Ri lt data THEN 1 C 0 ELSE 2 36 intel CLR A Function Description Example Bytes Cycles Encoding Operation CLR bit Function Description Example CLR C Bytes Cycles Encoding Operation CLR bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Clear Accumulator The Accumulator is cleared all bits set on zero No flags are affected The Accumulator contains 5CH 01011100B The instructio
28. byte DPH No flags are affected This is the only 16 bit register which can be incremented Registers DPH and DPL contain 12H and OFEH respectively The instruction sequence INC DPIR INC DPTR INC DPTR will change DPH and DPL to 13H and 01H 1 2 INC DPTR DPTR 1 2 45 intel MCS9 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JB bit rei Function Jump if Bit set Description the indicated bit is a one jump to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected Example The data present at input port 1 is 11001010B The Accumulator holds 56 01010110B The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label LABEL2 Bytes 3 Cycles 2 Encoding 0010 0000 Operation JB PC PC 3 IF bit 1 THEN PC lt rel JBC bit rel Function Jump if Bit is set and Clear bit Description If the indicated bit is one branch to the address indicated otherwise proceed with the next instruction The bit will not be cleared if it is already a zero The branch destination is comput ed by adding the signed relative displacement in the third ins
29. bytes since no additional instructions are needed to set up the output ports It is possible in some situations to mix the two MOVX types A large RAM array with its high order address lines driven by P2 can be addressed via the Data Pointer or with code to output high order address bits to P2 followed by MOVX instruction using RO or An external 256 byte RAM using multiplexed address data lines e g an Intel 8155 RAM 1 O Timer is connected to the 8051 Port 0 Port 3 provides control lines for the external RAM Ports 1 and 2 are used for normal I O Registers O and 1 contain 12H and 34H Location 34H of the external RAM holds the value 56H The instruction sequence RO A copies the value 56 into both the Accumulator and external RAM location 12H 2 58 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOVX A GRi Bytes 1 Cycles 2 Encoding 1110 001i Operation MOVX gt t 8 A DPTR Bytes Cycles Encoding 1110 0000 Operation MOVX gt 1 8 E MOVX Bytes Cycles Encoding 1111 Operation RD lt A MOVX DPTR A Bytes 1 Cycles 2 Encoding Operation MOVX DPTR lt 2 59 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MUL Function Multiply Description MUL AB multiplies the unsigned eight bit integers in the Accumulator and register The low order byte of the si
30. external Program Memory always use a 16 bit address Accesses to external Data Memory can use either a 16 bit address MOVX GDPTR or an 8 bit address MOVX Ri 3 9 Whenever a 16 bit address is used the high byte of the address comes out on Port 2 where it is held for the duration of the read or write cycle Note that the Port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1s This is during the execution of a MOVX DPTR instruction During this time the Port 2 latch the Special Function Register does not have to contain 1s and the contents of the Port 2 SFR not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the Port 2 SFR will reappear in the next cycle If an 8 bit address is being used MOVX GRi the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle This will facili tate paging In any case the low byte of the address is time multi plexed with the data byte on Port 0 The ADDR DATA signal drives both FETs in the Port 0 output buffers Thus in this application the Port O pins are not open drain outputs and do not require externa pull ups Signal ALE Address Latch Enable should be used to capture the address byte into an external latch The address byte is valid at the negative transition of ALE Then in a write cycle the data byte to
31. following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse oc curs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift regis ter Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeroes This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after write to SBUF Reception is initiated by a detected 1 10 0 transition at RXD For this purpose RXD is sampled a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is imme diately reset and 1FFH is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is
32. four ports in the 8051 are bidirectional Each con sists of a latch Special Function Registers PO through P3 an output driver and an input buffer The output drivers of Ports O and 2 and the input buff ers of Port 0 are used in accesses to external memory In this application Port O outputs the low byte of the 3 6 external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the externa memory address when the address is 16 bits wide Otherwise the Port 2 pins continue to emit the P2 SFR content All the Port 3 pins and in the 8052 two Port 1 pins are multifunctional They are not only port pins but also serve the functions of various special features as listed on the following page intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Port Pin Alternate Function P1 0 T2 Timer Counter 2 external input P1 1 T2EX Timer Counter 2 Capture Reload trigger P3 0 RXD serial input port P3 1 TXD serial output port P3 2 INTO external interrupt P3 3 INT1 external interrupt P3 4 TO Timer Counter 0 external input P3 5 T1 Timer Counter 1 external input P3 6 WR external Data Memory write strobe P3 7 RD externa Data Memory read strobe P1 0 and P1 1 serve these alternate functions only on the 8052 The alternate functions can only be activated if the cor responding bit latch in the port SFR contains a 1 Oth erwise the port pin is stuck at O
33. gt Function Logical Exclusive OR for byte variables Description XRL performs the bitwise logical Exclusive OR operation between the indicated variables storing the results in the destination No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins Example If the Accumulator holds 11000011B and register 0 holds OAAH 10101010B then the instruction XRL A RO will leave the Accumulator holding the value 69H 01101001B When the destination is a directly addressed byte this instruction can complement combina tions of bits in any RAM location or hardware register The pattern of bits to be complement ed is then determined by a mask byte either a constant contained in the instruction or a variable computed in the Accumulator at run time The instruction XRL P1 00110001B will complement bits 5 4 and O of output Port 1 2 78 intel XRL A Rn Bytes Cycles Encoding Operation A direct Bytes Cycles Encoding Operation XRL A Ri Bytes Cycles Encoding Operation
34. not O the receive circuits are reset and the unit goes back to looking for another 1 10 0 transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will pro intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 8051 INTERNAL BUS PHASE 2 CLOCK tosc MODE 2 SERIAL INTERRUPT SMOD 0 SMOD IS PCON 7 AX CLOCK RX CONTROL INPUT SHIFT REG 9 BITS LOAD N SBUF y Le Y ix 8051 INTERNAL BUS LOCK 1 f 1 i 1 1 WRITE TO SBUF 86 DATA Esim aS SHIFT R fil 1 A 1 TRANSMIT TXD SIT J STOP RX 16 RESET RECEIVE 270252 17 Figure 19 Serial Port Mode 2 3 21 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 8051 INTERNAL BUS TIMER 1 TIMER 2 OVERFLOW OVERFLOW 8051 INTERNAL BUS TX LOC WRITE TO SBUF ELO 1414 41 A A 4 1 1 k 1 1 __ DATA S1P1 4 fl 1 TRANSMIT SHIFT Txo STOP BIT TI 716 RESET CLOCK gir DETECTOR STOP RECEIVE SAMPLE TIMES BIT SH RI J 525 f 270252 18 Figure 20 Serial Port Mode 3 TCLK RCLK and Timer 2 are Present in the 8052 8032 Only 3 22 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 As data bits come in from the right 1s shift out to the le
35. pins go into a float state and the other port pins and ALE and are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored after a normal reset is applied THE ON CHIP OSCILLATORS HMOS Versions The on chip oscillator circuitry for the HMOS HMOS I and HMOS II members of the MCS 51 fam ily is a single stage linear inverter Figure 29 intended for use as a crystal controlled positive reactance oscil lator Figure 30 In this application the crystal is oper ated in its fundamental response mode as an inductive reactance in parallel resonance with capacitance exter nal to the crystal intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 23 Figure 29 On Chip Oscillator Circuitry in the HMOS Versions of the MCS 51 Family In general crystals used with these devices typically have the following specifications ESR Equivalent Series Resistance see Figure 31 Co Shunt Capacitance 7 0 pF max Cy Load Capacitance 30 pF 3 pF Drive Level 1mW 270252 24 Figure 30 Using the HMOS On Chip Oscillator ESR In OHMS The crystal specifications and capacitance values and C2 in Figure 30 are not critical 30 pF can be used in these positions at any frequency with good quality crystals A ceramic resonator can be used in place of 4 8 12 16 the crystal in cost sensitive
36. the MCS In the Power Down mode of operation VCC can be 51 devices will present a substantial barrier against reduced to as low as 2 Care must be taken however gal readout of protected software to ensure that VCC is not reduced before the Power Down mode is invoked and that VCC is restored to its normal operating level before the Power Down mode is One Lock Bit Scheme on 8751H terminated The reset that terminates Power Down also frees the oscillator The reset should not be activated The 8751H contams s lock bit which once pro before VCC is restored to its normal operating level grammed denies electrical access by any external and must be held active long enough to allow the oscil means to the on chip Program Memory The effect of lator to restart and stabilize normally less than 10 this lock bit is that while it is programmed the internal msec Program Memory can not be read out the device can not be further programmed and it can not execute ex ternal Program Memory Erasing the EPROM array deactivates the lock bit and restores the device s full EPROM VERSIONS functionality It can then be re programmed The EPROM versions of these devices are listed in Ta ble 4 The 8751H programs at 21V using one The procedure for programming the lock bit is detailed 50 msec PROG pulse per byte programmed This the 8751H data sheet sults in a total programming time 4K bytes of
37. the Stack Pointer by two Program execution continues at the resulting address generally the instruction immediately following an ACALL or LCALL No flags are affected Example Stack Pointer originally contains the value OBH Internal RAM locations and OBH contain the values 23H and O1H respectively The instruction RET will leave the Stack Pointer equal to the value 09H Program execution will continue at location 0123H Bytes 1 Cycles 2 Encoding 0010 0010 Operation RET PC15 8 SP SP SP 1 PC7 9 SP SP SP 1 RETI Function Return from interrupt Description pops the high and low order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed The Stack Pointer is left decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Program execution continues at the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower or same level interrupt had been pending when the RETI instruction is executed that one instruction will be executed before the pending interrupt is processed Example Stack Pointer originally contains the value OBH An interrupt was detected during the instruction ending at location 0122H Interna
38. the port bit latch must contain a 1 which turns off the output driver FET Then for Ports 1 2 and 3 the pin is pulled high by the internal pullup but can be pulled low by an external source Port 0 differs in not having internal pullups The pullup FET in the PO output driver see Figure 4 is used only when the Port is emitting 1s during external memory accesses Otherwise the pullup FET is off Consequent ly PO lines that are being used as output port lines are open drain Writing a 1 to the bit latch leaves both output FETs off so the pin floats In that condition it can be used a high impedance input Because Ports 1 2 and 3 have fixed internal pullups they are sometimes called quasi bidirectional ports When configured as inputs they pull high and will source current IIL in the data sheets when externally pulled low Port O on the other hand is considered true bidirectional because when configured as an in put it floats All the port latches in the 8051 have 1s written to them by the reset function If a O is subsequently written to a port latch it can be reconfigured as an input by writing a to it Writing to a Port In the execution of an instruction that changes the val ue in a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction How ever port latches are in fact sampled by their output buffers only during Phase 1 of any clock period Dur ing Phase
39. with the timing shown in Figure 25 The external reset signal is asynchronous to the internal clock The RST pin is sampled during State 5 Phase 2 of every machine cycle The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin that is for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin While the RST pin is high ALE and PSEN are weakly pulled high After RST is pulled low it will take 1 to 2 machine cycles for ALE and PSEN to start clocking For this reason other devices can not be synchronized to the internal timings of the 8051 Driving the ALE and PSEN pins to 0 while reset is active could cause the device to go into an indetermi nate state The internal reset algorithm writes Os to all the SFRs except the port latches the Stack Pointer and SBUF The port latches are initialized to FFH the Stack Pointer to 07H and SBUF is indeterminate Table 3 lists the SFRs and their reset values The internal RAM is not affected by reset On power up the RAM content is indeterminate Y Y Y Y Y Y M Apr X jocos LI 5 11 OSC PERIODS 19 OSC PERIODS 270252 33 Figure 25 Reset Timing 3 26 intel Table 3 Reset Values of the SFRs ACC 0H BEI PERENNE o 2 HE OH PO P3 FFH TOD _
40. 6 through 39 show when the various strobe and port signals are clocked internally The figures do not show rise and fall times of the signals nor do they show propagation delays between the XTAL signal and events at other pins Rise and fall times are dependent on the external load ing that each pin must drive They are often taken to be something in the neighborhood of 10 nsec measured between 0 8V and 2 0V Propagation delays are different for different pins For a given pin they vary with pin loading temperature VCC and manufacturing lot If the XTAL waveform is taken as the timing reference prop delays may vary from 25 to 125 nsec The AC Timings section of the data sheets do not refer ence any timing to the XTAL waveform Rather they relate the critical edges of control and input signals to each other The timings published in the data sheets include the effects of propagation delays under the specified test conditions intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 STATE 2 5 STATE 4 STATE 1 STATE 2 P1 p2 P1 2 2 1 2 2 p 2 2 p 2 270252 29 Figure 36 External Program Memory Fetches STATE 6 Deu un STATE 4 STATE 5 P1 P2 p1 2 1 22 1 2 1 2 2 pi 2 2 OR OR B Figure 37 External Data Memory Read Cycle 270252 30 3 34 intel
41. C DPTR Bytes 1 Cycles Encoding Operation MOVC A A DPTR MOVC A A PC Bytes Cycles 2 Operation MOVC PC E PC 1 A PC 2 57 MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET intel MOVX lt dest byte gt lt src byte gt Function Description Example Move External The MOVX instructions transfer data between the Accumulator and a byte of external data memory hence the appended to MOV There are two types of instructions differing in whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type the contents of RO or Ri the current register bank provide an eight bit address multiplexed with data on PO Eight bits are sufficient for external 1 0 expansion decoding or for a relatively small RAM array For somewhat larger arrays any output port pins can be used to output higher order address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instruction the Data Pointer generates a sixteen bit address P2 outputs the high order eight address bits the contents of DPH while multiplexes the low order eight bits DPL with data The P2 Special Function Register retains its previous con tents while the P2 output buffers are emitting the contents of DPH This form is faster and more efficient when accessing very large data arrays up to 64K
42. C PC rel 2 69 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SUBB A lt src byte gt Function Description Example SUBB Bytes Cycles Encoding Operation Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the Accumulator leaving the result in the Accumulator SUBB sets the carry borrow flag if a borrow is needed for bit 7 and clears otherwise If was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the carry is subtracted from the Accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or imme diate The Accumulator holds OC9H 11001001B register 2 holds 54H 01010100B and the carry flag is set The instruction SUBB A R2 will leave the value 74H 01110100B in the accumulator with the carry flag and AC cleared but OV set Notice that OC9H minus 54H is 75H The difference between this and the
43. D for byte variables Description ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination 5 a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Ifthe Accumulator holds 11000011B and register 0 holds 55H 01010101B then the instruction ANL will leave 41H 01000001B in the Accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run time The instruction ANL 1 01110011 will clear bits 7 3 and 2 of output port 1 2 32 intel ANL A Rn Bytes Cycles Encoding Operation ANL A direct Bytes Cycles Encoding Operation ANL A Ri Bytes Cycles Encoding Operation ANL A data Bytes Cycles Encoding Operation ANL direct A Bytes Cycles
44. Encoding Operation Exchange Accumulator with byte variable XCH loads the Accumulator with the contents of the indicated variable at the same time writing the original Accumulator contents to the indicated variable The source destination operand can use register direct or register indirect addressing RO contains the address 20H The Accumulator holds the value 3FH 00111111B Internal RAM location 20H holds the value 75H 01110101B The instruction XCH A GRO will leave RAM location 20H holding the values 3FH 00111111B and 75H 01110101B in the accumulator 1 1 XCH 2 Rn 2 1 XCH A direct 1 1 XCH A RI 2 72 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XCHD A Ri Function Exchange Digit Description XCHD exchanges the low order nibble of the Accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the internal RAM location indirectly addressed by the specified register The high order nibbles bits 7 4 of each register are not affected No flags are affi Example contains the address 20H The Accumulator holds the value 36H 00110110B Internal RAM location 20H holds the value 75H 011101018 The instruction XCHD A RO will leave RAM location 20H holding the value 76H 01110110B and 35H 00110101B in the Accumulator Bytes 1 Cycles 1 Operation XCHD Ri3 0 XRL lt dest byte gt lt src byte
45. OV RD data MOV lt dest bit gt lt src bit gt Function Description Example Move bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand One of the operands must be the carry flag the other may be any directly addressable bit No other register or flag is affected The carry flag is originally set The data present at input Port 3 is 11000101B The data previously written to output Port 1 is 35H 00110101B MOV 3 MOV C P3 3 MOV P1 2 C will leave the carry cleared and change Port 1 to 39H 00111001B 2 55 intel MOV C bit Bytes Cycles Encoding Operation MOV bit C Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 MOV C bit 2 2 1001 bit address MOV bit C MOV OPTR data16 Function Description Example Bytes Cycles Encoding Operation Load Data Pointer with a 16 bit constant The Data Pointer is loaded with the 16 bit constant indicated The 16 bit constant is loaded into the second and third bytes of the instruction The second byte DPH is the high order byte while the third byte DPL holds the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once The instruction MOV DPTR 1234H will load the value 1234H into the Data Pointer DPH will hold 12H and DPL will hold
46. __ ___ OH OOH TH TL1 OOH TH2 80582 __7 2 8052 0 RCAP2H 8052 _ RCAP2L 8052 SCON Ek PCON HMOS PCON CHMOS 270252 21 Figure 26 Power on Reset Circuit 3 27 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 POWER ON RESET For HMOS devices when is turned on an automat ic reset can be obtained by connecting the RST pin to through a 10 uF capacitor and to Vss through an 8 2 resistor Figure 26 The CHMOS devices do not require this resistor although its presence does no harm In fact for CHMOS devices the external resistor can be removed because they have an internal pulldown on the RST pin The capacitor value could then be re duced to 1 pF When power is turned on the circuit holds the RST pin high for an amount of time that depends on the capaci tor value and the rate at which it charges To ensure a valid reset the RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles On power up Vcc should rise within approximately ten milliseconds The oscillator start up time will de pend on the oscillator frequency For a 10 MHz crystal the start up time is typically 1 ms For a 1 MHz crystal the start up time is typically 10 ms With the given circuit reducing Vcc quickly to O caus es the RST pin voltage to momentarily fall below However this volta
47. able vertent erasure but to protect the and other on on the various products chip logic Allowing light to impinge on the silicon die while the device is operating can cause logical malfunc When using the encryption array one important factor tion should be considered If a code byte has the value 3 29 intel OFFH verifying the byte will produce the encryption byte value If a large block of code is left unpro grammed a verification routine will display the encryp tion array contents For this reason all unused code bytes should be programmed with some value other than OFFH and not all of them the same value This will ensure maximum program protection Program Lock Bits Also included in the Program Lock scheme are Lock Bits which can be enabled to provide varying degrees of protection Table 5 lists the Lock Bits and their corresponding effect on the micro controller Refer to Table 6 for the Lock Bits available on the various products Erasing the EPROM also erases the Encryption Array and the Lock Bits returning the part to full functionali ty Table 5 Program Lock Bits and their Features Program Lock Bits Protection Type No program lock features enabled Code verify will still be encrypted by the encryption array if programmed MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset and furthe
48. accessing the Timer 2 or RCAP registers in this case More About Mode 0 Serial data enters and exits through RXD TXD out puts the shift clock 8 bits are transmitted received 8 data bits LSB first The baud rate is fixed at Y 2 the oscillator frequency Figure 17 shows a simplified functional diagram of the serial port in Mode 0 and associated timing 3 17 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission The internal timing is such that one full machine cycle will elapse between write to SBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during 53 54 and 55 of every machine cycle and high during 56 51 and 52 At S6P2 of every machine cycle in which SEND 15 active the contents of the transmit shift register are shifted to the right one position As data bits shift out to the right zeroes come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initial ly loaded into the 9th position is just to the left of the MSB and all positions to
49. an operate on the carry flag or any directly addressable bit No other flags are affected The carry flag is cleared Output Port 1 has been written with the value 34H 00110100B The instructions SETB C SETB P1 0 will leave the carry flag set to 1 and change the data output on Port 1 to 35H 00110101B 1101 0011 SETB E 1 2 1 mams SETB bit 1 2 68 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SJMP rel Function Description Example Bytes Cycles Encoding Operation Short Jump Program control branches unconditionally to the address indicated The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it The label RELADR is assigned to an instruction at program memory location 0123H The instruction SIMP RELADR will assemble into location 0100H After the instruction is executed the PC wil contain the value 0123H Note Under the above conditions the instruction following SJMP will be at 102H Therefore the displacement byte of the instruction will be the relative offset 0123H 0102H 21H Put another way an SJMP with a displacement of OFEH would be a one instruction infinite loop 2 2 SJMP PC PC 2 P
50. applications When a ce CRYSTAL FREQUENCY in MHz ramic resonator is used C1 and C2 are normally select 270252 34 ed to be of somewhat higher values typically 47 pF The manufacturer of the ceramic resonator should be Figure 31 ESR vs Frequency consulted for recommendations on the values of these capacitors 3 31 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Frequency tolerance and temperature range are deter mined by the system requirements A more in depth discussion of crystal specifications ce ramic resonators and the selection of values for C1 and C2 can be found in Application Note AP 155 Oscilla tors for Microcontrollers which is included in the Embedded Applications Handbook To drive the HMOS parts with an external clock source apply the external clock signal to XTAL2 and ground XTAL1 as shown in Figure 32 A pullup resis tor may be used to increase noise margin but is op tional if VOH of the driving gate exceeds the VIH MIN specification of XTAL2 270252 25 Figure 32 Driving the HMOS MCS9 51 Parts with an External Clock Source CHMOS Versions The on chip oscillator circuitry for the 80C51BH Shown in Figure 33 consists of a single stage linear inverter intended for use as a crystal controlled posi tive reactance oscillator in the same manner as the HMOS parts However there are some important dif ferences One difference is that the 80C51BH is able to turn o
51. approx imately 4 minutes Two Program Memory Lock Schemes The 8751BH 8752BH and 87C51 use the faster The 8751BH 8752BH and 87C51 contain two Program Quick Pulse programmingTM algorithm These de Memory locking schemes Encrypted Verify and Lock vices program at 12 757 using a series of Bits twenty five 100 us PROG pulses per byte programmed This results in a total programming time of approxi Encryption Array Within the EPROM is an array of mately 26 seconds for the 8752BH 8 Kbytes and encryption bytes that are initially unprogrammed ali 13 seconds for the 87 51 4 Kbytes 1 5 The user can program the array to encrypt the code bytes during EPROM verification The verifica Detailed procedures for programming and verifying tion procedure sequentially XNORs each code byte each device are given in the data sheets with one of the key bytes When the last key byte in the array is reached the verify routine starts over with the first byte of the array for the next code byte If the key Exposure to Light bytes are unprogrammed the XNOR process leaves the code byte unchanged With the key bytes programmed It is good practice to cover the EPROM window with the code bytes are encrypted and can be read correctly an opaque label when the device is in operation This is only if the key bytes are known in their proper order not so much to protect the EPROM array from inad Table 6 lists the number of encryption bytes avail
52. be written appears on Port just before WR is activated and re mains there until after WR is deactivated a read cycle the incoming byte is accepted at Port 0 just be fore the read strobe is deactivated During any access to external memory the CPU writes OFFH to the Port 0 latch the Special Function Regis ter thus obliterating whatever information the Port 0 SFR may have been holding If the user writes to Port O during an externa memory fetch the incoming code byte is corrupted Therefore do not write to Port O if external program memory is used External Program Memory is accessed under two con ditions 1 Whenever signal EA is active or 2 Whenever the program counter PC contains a number that is larger than OFFFH 1FFFH for the 8052 This requires that the ROMless versions have EA wired low to enable the lower 4K 8K for the 8032 program bytes to be fetched from external memory When the CPU is executing out of external Program Memory all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose I O During external program fetches they output the high byte of the PC During this time the Port 2 drivers use the strong pullups to emit PC bits that are 1s TIMER COUNTERS The 8051 has two 16 bit Timer Counter registers Tim er O and Timer 1 The 8052 has these two plus one intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 more Timer 2 All three ca
53. d No flags are affected Example The Stack Pointer originally contains the value 32H and internal RAM locations through 32H contain the values 20H 23H and 01H respectively The instruction sequence POP DPH POP DPL will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H At this point the instruction POP SP will leave the Stack Pointer set to 20H Note that in this special case the Stack Pointer was decremented to 2FH before being loaded with the value popped 20H Bytes 2 Cycles 2 Encoding 0000 Operation POP direct lt SP SP E SP 1 PUSH direct Function Push onto stack Description Stack Pointer is incremented by one The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer Otherwise no flags are affect ed Example entering an interrupt routine the Stack Pointer contains 09H The Data Pointer holds the value 0123H The instruction sequence PUSH DPL PUSH DPH will leave the Stack Pointer set to OBH and store 23H and O1H in internal RAM locations OAH and OBH respectively Bytes 2 Cycles 2 Encoding 0000 Operation PUSH SP SP 1 SP direct intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET RET Function Return from subroutine Description pops the high and low order bytes of the PC successively from the stack decrementing
54. d to after RETI until at least one other instruction has been executed Thus once an interrupt routine has been entered it cannot be re entered until at least one instruction of the interrupt ed program is executed One way to use this feature for single stop operation is to program one of the external interrupts say INTO to be level activated The service routine for the interrupt will terminate with the follow ing code JNB P3 2 Here Till INTO Goes High JB P3 Now Wait Here Till it Goes Low RETI Go Back and Execute One Instruction Now if the INTO pin which is also the P3 2 pin is held normally low the CPU will go right into the External Interrupt routine and stay there until INTO is pulsed from low to high to low Then it will execute RETI go back to the task program execute one instruction and immediately re enter the External Interrupt O rou tine to await the next pulsing of P3 2 One step of the task program is executed each time P3 2 is pulsed 12 OSC PERIODS 55 56 51 2 3 ss ss 56 51 52 53 54 55 56 1 52 3 4 _ INTERNAL RESET SIGNAL SAMPLE RST SAMPLE RST 1 4 RESET The reset input is the RST pin which is the input to a Schmitt Trigger A reset is accomplished by holding the RST pin high for at least two machine cycles 24 oscillator periods while the oscillator is running The CPU responds by generating an internal reset
55. e combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the Accumulator holds 11000011B and RO holds 55H 01010101B then the in struction ORL will leave the Accumulator holding the value 0D7H 11010111B When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be either a constant data value in the instruction or a variable computed in the Accumulator at run time The instruction ORL 1 00110010 will set bits 5 4 and 1 of output Port 1 ORL A Rn Bytes 1 Cycles 1 encoding Operation ORL A A 2 61 intel ORL A direct Bytes Cycles Encoding Operation ORL A Ri Bytes Cycles Encoding Operation ORL A data Bytes Cycles Encoding Operation ORL direct A Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 15919121 ORL lt A V direct 1 1 0100 011i ORL E V Ri 2
56. e devices by their individual names we will adopt a convention of referring to them generically as 8051s and 8052s unless a specific member of the group is being referred to in which case it will be specifically named The 8051s include the 8051AH 80CS1BH and their ROMless and EPROM versions The 80525 are the 8052AH 8032AH and 8752BH Figure 1 shows a functional block diagram of the 8051s and 8052s Table 1 The MCS 51 Family of Microcontrollers 8051AH 8052AH 80C51BH 8031AH 8032AH 80C31BH 8751H 8751BH 8752BH 87C51 Special Function Registers Device ROMiess EPROM ROM 6 bit Name Version Version ix a HMOS A map of the on chip memory area called SFR Special Function Register space is shown in Figure 2 SFRs marked by parentheses are resident in the 8052s but not in the 8051s intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 EGISTER E a lt t i Pcon tz acara saur ik INTERRUPT SERIAL PORT AND TIMER BLOCKS INSTRUCTION REGISTER 10 17 270252 1 Figure 1 MCS 51 Architectural Block Diagram HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51
57. ed The call itself takes two cycles Thus a mini mum of three complete machine cycles elapse between activation of an external interrupt request and the be ginning of execution of the first instruction of the serv ice routine Figure 24 shows interrupt response timings A longer response time would result if the request is blocked by one of the 3 previously listed conditions If an interrupt of equal or higher priority level is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 intel cycles long and if the instruction in progress is RETI or an access to IE or the additional wait time can not be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles SINGLE STEP OPERATION The 8051 interrupt structure allows single step execu tion with very little software overhead As previously noted an interrupt request will not be responded to while an interrupt of equal priority level is still in prog ress nor will it be responde
58. ement every machine cycle thus at the oscillator frequency As baud rate generator however it increments every state time thus at 7 the oscillator frequency In that case the baud rate is given by the formula Modes 1 3 Baud Rate Modes 1 3 Baud Rate Oscillator Frequency 32x 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of RCAP2H and RCAP2L taken as a 16 bit unsigned in teger Timer 2 as a baud rate generator is shown in Figure 16 This Figure is valid only if RCLK TCLK 1 in T2CON Note that a rollover in TH2 does not set TF2 and will not generate an interrupt Therefore the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Note too that if 2 is set a 1 0 0 transition T2EX will set EXF2 but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate generator 2 can be used as an extra external interrupt if desired It should be noted that when Timer 2 is running TR2 1 in timer function in the baud rate generator mode one should not try to read or write TH2 or TL2 Under these conditions the Timer is being incremented every state time and the results of a read or write may not be accurate The RCAP registers may be read but shouldn t be written to because a write might overlap a reload and cause write and or reload errors Turn the Timer off clear TR2 before
59. ervice routine Con dition 3 ensures that if the instruction in progress is RETI or any access to IE or IP then at least one more instruction will be executed before any interrupt is vec tored to The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note then that if an interrupt flag is active but not being responded to for one of the above conditions and is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle is new The polling cycle LCALL sequence is illustrated in Figure 24 Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 24 then in accordance with the above rules it will be vectored to during 5 and C6 without any in struction of the lower priority routine having been exe cuted Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the ap propriate servicing routine In some cases it also clears the flag that generated the interrupt and in other cases it doesn t It never clears the Serial Port or Timer 2 flags This has to be done in the user s software clears an external interrupt or IE1 only if it was transition activated
60. ess The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first incrementing the Stack Pointer by two The high order and low order bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64K byte program memory address space No flags are affected Example Initially the Stack Pointer equals 07H The label SUBRTN is assigned to program memory location 1234H After executing the instruction LCALL SUBRTN at location 0123H the Stack Pointer will contain 09H internal RAM locations 08H and 09H will contain 26H and 01H and the PC will contain 1234H Bytes 3 Cycles 2 Encoding 0001 0010 addr15 addr amp addr7 addrO Operation LCALL PC E PC 3 SP SP 1 SP PC7 9 SP SP 1 SP PC 5 g lt 5 0 LJMP addri6 Function Long Jump Description LJMP causes an unconditional branch to the indicated address by loading the high order and low order bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the full 64K program memory address space No flags are affected Example The label JMPADR is assigned to the instruction at program memory location 1234H The
61. f SMOD 1 the baud rate is the oscillator frequency 3 15 2SMOD Mode 2 Baud Rate X Oscillator Frequency In the 8051 the baud rates in Modes 1 and 3 are deter mined by the Timer 1 overflow rate In the 8052 these baud rates can be determined by Timer 1 or by Timer 2 or by both one for transmit and the other for re ceive intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Using Timer 1 to Generate Baud Rates mode high nibble of TMOD 0010B In that case the baud rate is given by the formula When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Modes 1 3 2sMOD Oscillator Frequency 1 overflow rate and the value of SMOD as fol Baud Rate 12x 256 Modes 1 3 5 One can achieve very low baud rates with Timer 1 by Baud Rate X Timer 1 Overflow Rate leaving the Timer 1 interrupt enabled and configuring the Timer to run as a 16 bit timer high nibble of TMOD 0001B and using the Timer 1 interrupt to The Timer 1 interrupt should be disabled in this appli do a 16 bit software reload cation The Timer itself can be configured for either timer or counter operation and in any of its 3 Figure 15 lists various commonly used baud rates and running modes In the most typical applications it is how they can be obtained from Timer 1 configured for timer operation in the auto reload Baud Rate Reloa gt
62. facing The output buffers of Ports 1 2 and 3 can each drive 4 LS TTL inputs These ports on HMOS versions can be driven in a normal manner by any TTL or NMOS cir cuit Both HMOS and CHMOS pins can be driven by open collector and open drain outputs but note that 0 to 1 transitions will not be fast In the HMOS device if the pin is driven by an open collector output a 0 to 1 transition will have to be driven by the relatively weak depletion mode FET in Figure 5 A In the CHMOS device an input 0 turns off pullup pFET3 leaving only the very weak pullup pFET2 to drive the transition In external bus mode Port 0 output buffers can each drive 8 LS TTL inputs As port pins they require exter nal pullups to drive any inputs intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Read Modify Write Feature Some instructions that read a port read the latch and others read the pin Which ones do which The instruc tions that read the latch rather than the pin are the ones that read a value possibly change it and then rewrite it to the latch These are called read modify write in structions The instructions listed below are read mod ify write instructions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL logical AND e g ANL Pl A ORL logical OR e g ORL P2 XRL logical EX OR e g XRL P3 A JBC jump if bit 1 and clear bit e g JBC
63. ff its oscillator under software control by writing a 1 to the PD bit in PCON Another difference is that in the 80 51 the internal clocking circuitry is driven by the signal at XTAL1 whereas in the HMOS versions it is by the signal at XTAL2 The feedback resistor Ry in Figure 33 consists of paral leled n and p channel FETs controlled by the PD bit such that is opened when PD 1 The diodes D1 and D2 which act as clamps to VCC and VSS are parasitic to the FETs The oscillator can be used with the same external com ponents as the HMOS versions as shown in Figure 34 Typically C2 30 pF when the feedback ele ment is a quartz crystal and C1 C2 47 pF whena ceramic resonator is used To drive the CHMOS parts with an external clock source apply the external clock signal to XTAL1 and leave XTAL2 float as shown in Figure 35 270252 26 Figure 33 On Chip Oscillator Circuitry in the CHMOS Versions of the MCS 51 Family intel 270252 28 Figure 35 Driving the CHMOS MCS 51 Parts with an External Clock Source The reason for this change from the way the HMOS part is driven can be seen by comparing Figures 29 and 33 In the HMOS devices the internal timing circuits are driven by the signal at XTAL2 In the CHMOS devices the internal timing circuits are driven by the signal at XTAL 1 3 33 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 27 INTERNAL TIMING Figures 3
64. ft When the start bit arrives at the leftmost position in the shift register which in Modes 2 and 3 is a 9 bit register it flags the RX Control block to do one last shift load SBUF and and set RI The signal to load SBUF and 8 and to set RI will be generated if and only if the following conditions are met at the time the final shift puise is generated 1 RI 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into and the first 8 data bits go into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to O transition at the RXD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI INTERRUPTS The 8051 provides 5 interrupt sources The 8052 pro vides 6 These are shown in Figure 21 The External Interrupts INTO and INTI can each be either level activated or transition activated depending on bits ITO and IT1 in Register TCON The flags that actually generate these interrupts are bits and IE1 in TCON When an external interrupt is generated the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt 270252 19 Figure 21 MCS 51 Interrupt Sources was transition activated If the interru
65. ge is internally limited and will not harm the device NOTE The port pins will be in a random state until the oscillator has started and the internal reset algorithm has written 1s to them Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location This is because the SFRs spe cifically the Program Counter may not get properly initialized POWER SAVING MODES OF OPERATION For applications where power consumption is critical the CHMOS version provides power reduced modes of operation as a standard feature The power down mode in HMOS devices is no longer a standard feature and is being phased out CHMOS Power Reduction Modes CHMOS versions have two power reducing modes Idle and Power Down The input through which back up power is supplied during these operations is VCC Figure 27 shows the internal circuitry which imple ments these features In the Idle mode IDL 1 the oscillator continues to run and the Interrupt Serial Port and Timer blocks continue to be clocked but the intel clock signal is gated off to the CPU In Power Down PD 1 the oscillator is frozen The Idle and Power Down modes are activated by setting bits in Special Function Register PCON The address of this register is 87H Figure 26 details its contents In the HMOS devices the PCON register only contains SMOD The other four bits are implemented only in the CHMOS devices
66. he Timer overflow rate In the 8052 it is deter mined either by the Timer 1 overflow rate or the Timer 2 overflow rate or both one for transmit and the other for receive Figure 18 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for trans mit receive intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 RXD P3 0 ALT OUTPUT FUNCTION TXD P3 1 ALT OUTPUT FUNCTION RXCLOCK RI START 441111110 RXD P3 0 ALT INPUT FUNCTION 8051 INTERNAL BUS 5182 8 54 2002 82 53 04 9690 6 323334 96 00 e s musa 3182833433 06 828254 96 96 ALE WRITE senn 3672 SHIFT OUT SM gt p ee or TRANSMIT RXD DATA TXD SHIFT CLOCK S3P1 5691 WRITE SCON CLEAR Al PW te J Ce ee SHIFT n n n f n RECEIVE RXD DATA Be poe gt _ TXD SHIFT CLOCK Figure 17 Serial Port Mode 0 270252 15 3 18 intel TIMER 1 OVERFLOW TIMER 2 OVERFLOW y START TXCLOCK RXCLOCK RI RX CONTROL START BIT DETECTOR TX WRITE TO SBUF HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 8051 INTERNAL BUS EE I ZERO DETECTOR SHIFT pata TX CONTROL SEND LOAD SBUF SHIFT 1FFH SINN 8051INTERNAL BUS SEND DATA 1 1 TRANSMIT SHIFT N 1 1 1 N xp X LIEBEN 01 0 D X
67. herwise proceed with the next instruction The branch destination is computed by adding the signed relative dis placement in the second instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally holds The instruction sequence JNZ LABELI INC JNZ LABEL2 will set the Accumulator to 01H and continue at label LABEL2 2 2 0111 0000 JNZ PC lt PC 2 IF 0 THEN rel address PC rel Function Description Example Bytes Cycles Encoding Operation Jump if Accumulator Zero If all bits of the Accumulator are zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative dis placement in the second instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally contains 01H The instruction sequence JZ LABELI DEC A JZ LABEL2 will change the Accumulator to and cause program execution to continue at the instruc tion identified by the label LABEL2 2 2 JZ PC PC 2 IF A 0 THEN PC rel 2 50 intel LCALL addri6 MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Function Long call Description LCALL calls a subroutine located at the indicated addr
68. imer Counter on off Timer 0 overflow Flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine Timer 0 Run contro bit Set cleared by software to turn Timer Counter on oft Symbol Position Name and Significance Interrupt 1 Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed Interrupt 1 Type contro bit Set Cleared by software to specify falling level triggered external interrupts Interrupt O Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed Interrupt O Type control bit Set cleared by software to specify falling edge low level triggered external interrupts Figure 8 TCON Timer Counter Control Register MODE 2 Mode 2 configures the Timer register as an 8 bit Coun ter TL1 with automatic reload as shown in Figure 9 Overflow from TL1 not only sets TF1 but also reloads with the contents of TH1 which is preset by soft ware The reload leaves TH1 unchanged Mode 2 operation is the same for Timer Counter 0 MODE 3 Timer 1 in Mode 3 simply holds its count The effect is the same as setting 0 3 11 Timer O in Mode 3 establishes TLO and THO as two separate counters The logic for Mode 3 on Timer is shown in Figure 10 TLO uses the Timer 0 control bits C T GATE TRO INTO and THO is locked into a timer fu
69. instruction LIMP JMPADR at location 0123H will load the program counter with 1234H Bytes 3 Cycles 2 Encoding 0000 0010 addri5 addrs addr7 addro Operation LIMP PC E 5 2 51 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOV lt dest byte gt lt src byte gt Function Description Example MOV A Rn Bytes Cycles Encoding Operation A direct Bytes Cycles Encoding Operation Move byte variable The byte variable indicated by the second operand is copied into the location specified by the first operand The source byte is not affected No other register or flag is affected This is by far the most flexible operation Fifteen combinations of source and destination addressing modes are allowed Internal RAM location 30H holds 40H The value of RAM location 40H is 10H The data present at input port 1 is 11001010B MOV MOV MOV MOV MOV MOV RO 30H RO lt 30H A GRO A lt 40H Rl lt 40H BRI lt 10H R1 P1 40H lt P2 P1 P2 0CAH leaves the value 30H in register O 40H in both the Accumulator and register 1 10H in register B and OCAH 11001010B both in RAM location 40H and output on port 2 MOV E Rn 2 1 0101 direct address MOV direct MOV A ACC is not a valid instruction 2 52 intel MOV A Ri Bytes Cycles Encoding Operatio
70. intel MCS 51 MICROCONTROLLER FAMILY USER S MANUAL ORDER NO 272383 002 FEBRUARY 1994 intel ADDC A Rn Bytes Cycles Encoding Operation ADDC A direct Bytes Cycles Encoding Operation ADDC A eRi Bytes Cycles Encoding Operation ADDC A data Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 0011 1 ADDC lt 2 1 ADDC A E A direct 1 1 ADDC A R 2 1 0011 immediate data ADDC data 2 31 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET AJMP addr11 Function Absolute Jump Description AJMP transfers program execution to the indicated address which is formed at run time by concatenating the high order five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP Example The label JMPADR is at program memory location 0123H The instruction JMPADR is at location 0345H and will load the PC with 0123H Bytes 2 Cycles 2 Encoding 10 0001 a7 a5 a4 a2 a1 Operation AJMP PC 2 page address ANL lt dest byte gt lt src byte gt Function Logical AN
71. isables it Symbol Position EA 1E 7 Function disables all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit IE 6 reserved IE 5 Timer 2 interrupt enable bit 1E 4 Serial Port interrupt enable bit tE 3 Timer 1 interrupt enable bit IE 2 External interrupt 1 enable bit Timer 0 interrupt enable bit 0 External interrupt 0 enable bit User software should never write 1s to unimplemented bits since they may be used in future MCS 51 products Figure 22 IE Interrupt Enable Register intel Each of these interrupt sources can be individually en abled or disabled by setting or clearing a bit in Special Function Register IE Figure 22 IE contains also a global disable bit EA which disables all interrupts at once Note in Figure 22 that bit position IE 6 is unimple mented In the 8051s bit position 5 is also unimple mented User software should not write 1s to these bit positions since they may be used in future MCS 51 products Priority Level Structure Each interrupt source can also be individually pro grammed to one of two priority levels by setting or clearing a bit in Special Function Register IP Figure 23 A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low pri ority interrupt A high priority interrupt can t be inter rup
72. l RAM locations OAH and OBH contain the values 23H and 01H respectively The instruction RETI will leave the Stack Pointer equal to 09H and return program execution to location 0123H Bytes Cycles 2 Encoding 0011 0010 Operation RETI 15 8 SP SP SP 1 PC7 9 SP SP SP 1 2 65 intel Function Description Example Bytes Cycles Encoding Operation RLC A Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Rotate Accumulator Left The eight bits in the Accumulator are rotated one bit to the left Bit 7 is rotated into the bit O position No flags are affected The Accumulator holds the value 5 11000101B The instruction RL A leaves the Accumulator holding the value 8BH 10001011B with the carry unaffected 1 RL 1 lt 0 6 0 A7 Rotate Accumulator Left through the Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit O position No other flags are affected The Accumulator holds the value 11000101B and the carry is zero The instruction RLC A leaves the Accumulator holding the value 8BH 10001010B with the carry set 1 1 0011 0011 RLC An 1 lt
73. ld for at least 12 oscillator periods to ensure sampling If the external interrupt is transition activated the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag IEx will be set IEx will be automatically cleared by the CPU when the service routine is called If the external interrupt is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deacti vate the request before the interrupt service routine is completed or else another interrupt will be generated Response Time The INTO and levels are inverted and latched into the interrupt flags and 1 at S5P2 of every machine cycle Similarly the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at 55 2 The values are not actually polled by the circuitry until the next machine cycle The Timer O and Timer 1 flags TFO and TF1 are set at S5P2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the re quested service routine will be the next instruction to be execut
74. me Symbol TF2 Position T2CON 7 Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 EXF2 T2CON 6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on 2 and EXEN2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3 TCLK O causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable When set allows a capture or reload to occur as result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX Start stop control for Timer 2 A logic 1 starts the timer Timer or counter select Timer 2 0 Internal timer OSC 12 1 External event counter falling edge triggered Capture Reload flag When set captures will occur on negative transitions at 2 if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or
75. n MOV A data Bytes Cycles Encoding Operation MOV Rn A Bytes Cycles Encoding Operation MOV Rn direct Bytes Cycles Encoding Operation MOV Bytes Cycles Encoding Operation MCS 51 PROGRAMMERS GUIDE AND INSTRUCTION SET 1 1 MOV E Ri 2 1 0111 0100 immediate data MOV data 1 1 MOV Rn A 2 2 MOV Rn lt direct 2 1 MOV Rn data immediate data 2 53 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOV direct A Bytes 2 Cycles 1 Encoding 111110101 direct address Operation MOV direct MOV direct Rn Bytes 2 Cycles 2 Encoding direct address Operation MOV direct Rn MOV direct direct Bytes 3 Cycles 2 Encoding 1000 0101 dir addr src dir addr dest Operation MOV direct lt direct MOV direct Ri Bytes 2 Cycles 2 KEPE TM Operation MOV direct Ri MOV direct data Bytes 3 Cycles 2 Encoding 0111 direct address immediate data Operation MOV direct lt data 2 54 intel MOV eRi A Bytes Cycles Encoding Operation MOV Ri direct Bytes Cycles Encoding Operation MOV Ri data Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 MOV RD 2 2 MOV lt direct 2 1 o111 o01tij M
76. n CLR A will leave the Accumulator set to 00000000B 1 1 CLR 0 Clear bit The indicated bit is cleared reset to zero No other flags are affected CLR can operate on the carry flag or any directly addressable bit Port 1 has previously been written with SDH 01011101B The instruction CLR 12 will leave the port set to 59H 01011001B 1100 0011 CLR lt 0 2 1 CLR bit 0 2 37 intel MCS 51 PROGRAMMERS GUIDE AND INSTRUCTION SET Function Complement Accumulator Description Each bit of the Accumulator is logically complemented one s complement Bits which previ ously contained a one are changed to a zero and vice versa No flags are affected Example The Accumulator contains 5CH 01011100B The instruction CPL A will leave the Accumulator set to 1010001 1B Bytes 1 Cycles 1 Encoding 1111 0100 Operation CPL lt 7 CPL bit Function Complement bit Description bit variable specified is complemented A bit which had been a one is changed to zero and vice versa No other flags are affected CLR can operate on the carry or any directly address able bit Note When this instruction is used to modify an output pin the value used as the original data will be read from the output data latch the input pin Example 1 has previously been written with 5BH 01011101B The instruction sequence
77. n be configured to operate either as timers or event counters In the Timer function the register is incremented every machine cycle Thus one can think of it as count ing machine cycles Since a machine cycle consists of 12 oscillator periods the count rate is Y 2 of the oscillator frequency In the Counter function the register is incremented in response to a 1 10 0 transition at its corresponding external input pin TO T1 or in the 8052 T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incre mented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes 2 machine cycles 24 oscillator periods to recognize a 1 to O transition the maximum count rate is Ya of the oscillator fre quency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle In addition to the Timer or Counter selection Timer 0 and Timer 1 have four operating modes from which to select Timer 2 in the 8052 has three modes of operation Capture Auto Reload and baud rate generator Timer 0 and Timer 1 These Timer Counters are present in both the 3051 and the 8052 The Time
78. nction counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter With Timer O in Mode 3 an 8051 can look like it has three Timer Counters and an 8052 like it has four When Timer O is Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate generator or in fact in any application not requiring an interrupt intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 INTERRUPT 270252 10 Figure 9 Timer Counter 1 Mode 2 8 Bit Auto Reload 1 12 tosc INTERRUPT CONTROL INTERRUPT 270252 11 Figure 10 Timer Counter 0 Mode 3 Two 8 Bit Counters Timer 2 Table 2 Timer 2 Operating Modes snn Mode 16 bit Auto Reload 16 bit Capture Baud Rate Generator off Timer 2 is a 16 bit Timer Counter which is present only in the 8052 Like Timers O and 1 it can operate either as a timer or as an event counter This is selected by bit C T2 in the Special Function Register 2 Figure 11 It has three operating modes capture auto load and baud rate generator which are se lected by bits in TZCON as shown in Table 2 3 12 intel MSB HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 LSB Tre amp x2 exenz
79. ne for Timer 0 TMOD 3 MODE 1 Mode is the same as Mode 0 except that the Timer register is being run with all 16 bits LSB Timer 0 Timer 1 Gating control when set Timer Counter x is enabled only while INTx pin is high and control pin is set When cleared Timer x is enabled whenever control bit is set Timer or Counter Selector cleared for Timer operation input from intemal system clock Set for Counter operation input from Tx input pin Operating Mode 8 bit Timer Counter THx with Tic as 5 bit prescaler 16 bit Timer Counter THx and TLx are cascaded there is no prescaler 8 bit auto reload Timer Counter holds a value which is to be reloaded into each time it overflows Timer 0 TLO is an 8 bit Timer Counter controlled by the standard Timer 0 contro bits THO is an 8 bit timer only controlled by Timer 1 control bits Timer 1 Timer Counter 1 stopped Figure 6 TMOD Timer Counter Mode Control Register 3 10 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 INTERRUPT CONTROL 270252 9 Figure 7 Timer Counter 1 Mode 0 13 Bit Counter MSB LSB ve Tm tes m tro Name and Significance Timer 1 Flag Set by hardware Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine Timer 1 Run control bit Set cleared by software to tum T
80. negative transitions at 2 when EXEN2 1 When either RCLK 10r TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Figure 11 T2CON Timer Counter 2 Control Register In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then Timer 2 is a 16 bit timer or counter which upon overflowing sets bit TF2 the Timer 2 overflow bit which can be used to generate an interrupt If EXEN2 1 then Timer 2 still does the above but with the added feature that a 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively RCAP2L and RCAP2H are new Special Function Registers in the 8052 In addition the transition at 2 causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt The Capture Mode is illustrated in Figure 12 In the auto reload mode there are again two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2L and RCAP2H which are preset by software If EXEN2 1 then Timer 2 still does the above but with the 3 13 added feature that 1 to 0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2 The auto reload mode is illust
81. o the internal RAM during this time but access to the port pins is not inhibited To eliminate the possibility of unexpected outputs at the port pins the instruction following the one that invokes Idle should not be one that writes to a port pin or to external Data RAM POWER DOWN MODE An instruction that sets PCON 1 causes that to be the last instruction executed before going into the Power Down mode In the Power Down mode the on chip oscillator is stopped With the clock frozen all func intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 Table 4 EPROM Versions of the 8051 and 8052 Device EPROM EPROM Time Required to Name Version Bytes Program Entire E um 8051AH 8751H 8751BH Te 210V 1275V 4mimutes ese eros omos 1275 tions are stopped but the on chip RAM and Special Function Registers are held The port pins output the Program Memory LOCKS values held by their respective SFRs ALE and PSEN some microcontroller applications it is desirable that output lows the Program Memory be secure from software piracy Intel has responded to this need by implementing a The only exit from Power Down for the 80C51 is a Program Memory locking scheme in some of the MCS hardware reset Reset redefines all the SFRs but does 51 devices While it is impossible for anyone to guaran not change the on chip RAM tee absolute security against all levels of technological sophistication the Program Memory locks in
82. of several slaves it first sends out an ad dress byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be com ing The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the coming data bytes SM2 has no effect in Mode O and in Mode 1 can be used to check the validity of the stop bit In a Mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received Serial Port Control Register The serial port control and status register is the Special Function Register SCON shown in Figure 14 This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and 8 and the serial port interrupt bits TI and RI intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 13 Figure 13 Timer 2 in Auto Reload Mode MSB LS8 smo Sw sm2 REN ass Where 5 SM1 specify the serial port mode as follows SMO SM1 Mode Description Baud Rate O shiftregister 105 12 1 8 bitUART variable
83. pt was level acti vated then the external requesting source is what con trols the request flag rather than the on chip hardware The Timer 0 and Timer Interrupts are generated by and TF1 which are set by a rollover in their re spective Timer Counter registers except see Timer 0 in Mode 3 When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to The Serial Port Interrupt is generated by the logical OR of RI and TI Neither of these flags is cleared by hard ware when the service routine is vectored to In fact the service routine will normally have to determine whether it was RI or TI that generated the interrupt and the bit will have to be cleared in software In the 8052 the Timer 2 Interrupt is generated by the logical OR of TF2 and EXF2 Neither of these flags is cleared by hardware when the service routine is vec tored to In fact the service routine may have to deter mine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared in soft ware All of the bits that generate interrupts can be set or cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be canceled in software MSB LSB Lea es ers exi exo Enable Bit 1 enables the interrupt Enable Bit 0 d
84. r or Counter function is select ed by control bits C T in the Special Function Register TMOD Figure 6 These two Timer Counters have MSB cate w four operating modes which are selected by bit pairs MO in TMOD Modes 0 1 and 2 are the same for both Timer Counters Mode 3 is different The four operating modes are described in the following text MODE 0 Either Timer in Mode O is an 8 bit Counter with a divide by 32 prescaler This 13 bit timer MCS 48 compatible Figure 7 shows the Mode 0 operation as it applies to Timer 1 In this mode the Timer register is configured as a 13 Bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TF1 The counted input is enabled to the Timer when TR1 1 and either GATE 0 INT 1 Setting GATE 1 allows the Timer to be controlled by external input INT1 to facilitate pulse width measurements TR1 is a control bit in the Special Function Register TCON Figure 8 GATE is in TMOD The 13 Bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are inde terminate and should be ignored Setting the run flag TR1 does not clear the registers Mode 0 operation is the same for Timer 0 as for Timer 1 Substitute TRO TFO and INTO for the correspond ing Timer 1 signals in Figure 7 There are two different GATE bits one for Timer 1 TMOD 7 and o
85. r down operation Idle mode bit Setting this bit activates idle mode operation 1s are written to PD and IDL at the same time PD takes precedence The reset value of PCON is 0XXX0000 In the HMOS devices the PCON register only contains SMOD The other four bits are implemented only in the CHMOS devices User software should never write 18 to unimplemented bits since they may be used in future MCS 51 products PCON 6 PCON 5 PCON 4 PCON 3 PCON 2 PCON 1 PCON O Figure 28 PCON Power Control Register The flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal oper ation or during an 14 For example an instruction that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits The other way of terminating the Idle mode is with a hardware reset Since the clock oscillator is still run ning the hardware reset needs to be held active for only two machine cycles 24 oscillator periods to complete the reset The signal at the RST pin clears the IDL bit directly and asynchronously At this time the CPU resumes program execution from where it left off that is at the instruction following the one that invoked the Idle Mode As shown in Figure 25 two or three machine cycles of program execution may take place before the internal reset algorithm takes control On chip hard ware inhibits access t
86. r programming of the EPROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled P Programmed U Unprogrammed Any other combination of the Lock Bits is not defined Table 6 Program Protection Lock Bits Encrypt Array 87518 LB1 LB2 LB1 LB2 LB1 LB2 LB3 8752BH 87C51 3 30 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 When Lock Bit 1 is programmed the logic level at the EA pin is sampled and latched during reset If the de vice is powered up without a reset the latch initializes to a random value and holds that value until reset 5 activated It is necessary that the latched value of be in agreement with the current logic level at that pin in order for the device to function properly ROM PROTECTION The 8051AHP and 80C51BHP are ROM Protected versions of the 8051AH and 80C51BH respectively To incorporate this Protection Feature program verifica tion has been disabled and external memory accesses have been limited to 4K Refer to the data sheets on these parts for more information ONCETM Mode The ONCE on circuit emulation mode facilitates testing and debugging of systems using the device with out the device having to be removed from the circuit The ONCE mode is invoked by 1 Pull ALE low while the device is in reset and PSEN is high 2 Hold ALE low as RST is deactivated While the device is in ONCE mode the Port O
87. rat ed LCALL is not blocked by any of the following con IP 5 Timer 2 interrupt priority bit Serial Port interrupt priority bit Timer 1 interrupt priority bit 1P 4 1P 3 2 External interrupt 1 priority bit Timer 0 interrupt priority bit 1 0 External interrupt O priority bit User software should never write 1s to unimplemented bits since they may be used in future MCS 51 products Figure 23 IP Interrupt Priority Register If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are re INTERRUPTS ARE POLLED INTERRUPT INTERRUPT GOES LATCHED ACTIVE ditions 1 An interrupt of equal or higher priority level is al ready in progress The current polling cycle is not the final cycle in the execution of the instruction in progress The instruction in progress is RETI or any write to the IE or IP registers 2 3 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condi tion 2 ensures that the instruction in progress will be INTERRUPT ROUTINE 270252 20 This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or Figure 24 Interrupt Response Timing Diagram 3 24 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 completed before vectoring to any s
88. rated in Figure 13 The baud rate generator mode is selected by RCLK 1 and or TCLK 1 It will be described in conjunc tion with the serial port SERIAL INTERFACE The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered Meaning it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both ac cessed at Special Function Register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 12 Figure 12 Timer 2 in Capture Mode The serial port can operate in 4 modes Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted re ceived 8 data bits LSB first The baud rate is fixed at 1 12 the oscillator frequency Mode 1 10 bits are transmitted through TXD or ceived through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is variable Mode 2 11 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first
89. rs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 60H or 66H to the Accumulator depending on initial Accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the Accumulator to BCD nota tion nor does DA A apply to decimal subtraction 2 39 intel Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET The Accumulator holds the value 56H 01010110B representing the packed BCD digits of the decimal number 56 Register 3 contains the value 67H 01100111B representing the packed BCD digits of the decimal number 67 The carry flag is set The instruction sequence ADDC A R3 DA A will first perform a standard twos complement binary addition resulting in the value OBEH 10111110 in the Accumulator The carry and auxiliary carry flags will be cleared The Decimal Adjust instruction will then alter the Accumulator to the value 24H 00100100B indicating the packed BCD digits of the decimal number 24 the low order two digits of the decimal sum of 56 67 and the carry in The carry flag will be set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum 56 67 and 1 is 124 BCD variables can be incremented or decremented by adding 01H or 99H If the Accumulator initially holds 30H representing the digits of 30 decimal then the instruction sequence
90. ruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch nor the input pins Example Internal RAM locations 40H 50H and 60H contain the values 01H 70H and 15H respec tively The instruction sequence DJNZ 40H LABEL__1 DJNZ SOH LABEL 2 DJNZ 60H LABEL__3 will cause a jump to the instruction at label LABEL 2 with the values and 15H in the three RAM locations The first jump was not taken because the result was zero This instruction provides a simple way of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPL P1 7 DJNZ R2 TOGGLE will toggle P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse will last three machine cycles two for DINZ and one to alter the pin DJNZ Rn rel Bytes 2 Cycles 2 Encoding 1105 Operation DINZ PC PO 2 Rn Rn 1 IF Rn gt Oor Rn lt 0 THEN PC PC rel intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DJNZ direct re Bytes 3 Cycles 2 Encoding direct address Operation DINZ PC PC 2 direct direct 1 IF direct gt 0 or direct lt 0 THEN lt PC
91. s and the serial port They are described in later sections MSB HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 LSB L cy ac asi ov L e Name and Significance Carry flag Auxiliary Carry flag For BCD operations Position PSW 7 PSW 6 Symbol FO PSW 5 Flag 0 Available to the user general purposes Register bank select control bits 1 amp O Set cleared by software to determine working register bank see Note Symbol Position PSW 2 PSW 1 PSW O Name and Signiflcance Overflow flag User definable flag Parity flag Set cleared by hardware each instruction cycle to indicate an odd even number of bits in the Accumulator i e even NOTE The contents of RS1 50 enable the working register banks as follows 0 0 Bank O 0 1 Bank 1 1 0 2 1 1 Bank 3 00H 07H 08H OFH 10H 17H 18H 1FH Figure 3 PSW Program Status Word Register ADDR DATA CONTROL ce READ LATCH INT BUS 270252 2 Port 0 Bit READ LATCH 270252 4 C Port 2 Bit INTERNAL 270252 3 Port 1 Bit ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL PULL UP ALTERNATE INPUT FUNCTION 270252 5 D Port 3 Bit Figure 4 8051 Port Bit Latches and 1 0 Buffers See Figure 5 for details of the internal pullup PORT STRUCTURES AND OPERATION All
92. ted by any other interrupt source MSB LSB es Pri Pro exo Priority bit 1 assigns high priority Priority bit 0 assigns low priority Position IP 7 Function reserved reserved IP 6 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 ceived simultaneously an internal polling sequence de termines which request is serviced Thus within each priority level there is a second priority structure deter mined by the polling sequence as follows Source Priority Within Level IEO highest TFO IE1 TF1 RI TF2 EXF2 9 m p Q gt lowest Note that the priority within level structure is only used to resolve simultaneous requests of the same priori ty level The IP register contains a number of unimplemented bits IP 7 and IP 6 are vacant the 8052s and in the 8051s these and 5 are vacant User software should not write 15 to these bit positions since they may be used in future MCS 51 products How Interrupts Are Handled The interrupt flags are sampled at 55 2 of every ma chine cycle The samples are polled during the follow ing machine cycle The 8052 s Timer 2 interrupt cycle is different as described in the Response Time Section If one of the flags was in a set condition at 55 2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appro priate service routine provided this hardware gene
93. the left of that contain zeroes This condition flags the TX Control block to do one last shift and tben deactivate SEND and set TI Both of these actions occur at S1P1 of the 10th machine cycle after write to SBUF Reception is initiated by the condition REN 1 and 0 At S6P2 of the next machine cycle the RX Control unit writes the bits 11111110 to the receive shift register and in the next clock phase activates RE CEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shift ed to the left one position The value that comes in from the right is the value that was sampled at the P3 0 at 55 2 of the same machine cycle As data bits come in from the right 1s shift out to the left When the O that was initially loaded into the right most position arrives at the leftmost position in the shift register it flags the RX Control block to do one last shift and load SBUF At S1P1 of the 10th machine cycle after the write to SCON that cleared RI RE CEIVE is cleared and RI is set More About Mode 1 Ten bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 SCON In the 8051 the baud rate is determined by t
94. tion The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010B The Accumulator holds 56H 01010110B The instruction sequence JNB P1 3 LABELI JNB ACC 3 LABEL2 will cause program execution to continue at the instruction at label LABEL2 3 2 0000 JNB PC PO 3 IF bi 0 THEN PC PC rel Jump if Carry not set If the carry flag is a zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified The carry flag is set The instruction sequence JNC LABEL CPL C JNC LABEL2 will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2 2 2 JNC lt 2 IF 0 lt 2 49 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JNZ rel Function Description Example Bytes Cycles Encoding Operation JZ rel Jump if Accumulator Not Zero If any bit of the Accumulator is a one branch to the indicated address ot
95. truction byte to the PC after incrementing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original data will be read from the output data latch not the input pin Example The Accumulator holds 56H 01010110B The instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 will cause program execution to continue at the instruction identified by the label LABEL2 with the Accumulator modified to 52H 01010010B intel Bytes Cycles Encoding Operation JC rel Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 3 2 0000 JBC PC PC 3 IF bit 1 THEN bit 0 PC rel Jump if Carry is set If the carry flag is set branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice No flags are affected The carry flag is cleared The instruction sequence JC LABELI CPL C JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 2 2 JC PC PC 2 IF O 1 THEN PC PC rel 2 47 intel MCS 51 PROGRAMMER S GUIDE
96. xteen bit product is left in the Accumulator and the high order byte in If the product is greater than 255 the overflow flag is set otherwise it is cleared The carry flag is always cleared Example Originally the Accumulator holds the value 80 50H Register B holds the value 160 OAOH The instruction MUL AB will give the product 12 800 3200 so is changed to 32H 00110010B and the Accumula tor is cleared The overflow flag is set carry is cleared Bytes 1 Cycles 4 Operation MUL A 7 o lt A X B 15 8 NOP Function Operation Description Execution continues at the following instruction Other than the PC no registers or flags are affected Example It is desired to produce a low going output pulse on bit 7 of Port 2 lasting exactly 5 cycles simple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be inserted This may be done assuming no interrupts are enabled with the instruction sequence CLR P2 7 NOP NOP NOP NOP SETB P27 Bytes 1 Cycles Encoding 000010000 Operation 1 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ORL lt dest byte gt lt src byte gt Function Logical OR for byte variables Description ORL performs the bitwise logical OR operation between the indicated variables storing the results in the destination byte No flags are affected The two operands allow six addressing mod
97. yte gt lt src byte gt rel Function Description Example CJNE A direct rel Bytes Cycles Encoding Operation Compare and Jump if Not Equal CINE compares the magnitudes of the first two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction The carry flag is set if the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt otherwise the carry is cleared Neither operand is affected The first two operands allow four addressing mode combinations the Accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant The Accumulator contains 34H Register 7 contains 56H The first instruction in the se quence Brey ee des R7 60H NOT__EQ JC REQ LOW R7 sets the carry flag and branches to the instruction at label NOT__EQ testing the carry flag this instruction determines whether R7 is greater or less than 60H If the data being presented to Port 1 is also 34H then the instruction WAIT WAIT clears the carry flag and continues with the next instruction in sequence since the Accumula tor does equal the data read from P1 If some other value was

MCS® 51 Microcontroller Family User`s Manual

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MCS&reg; 51 Microcontroller Family User`s Manual

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MCS® 51 Microcontroller Family User`s Manual