Home

D. Developing the FPGA VI

1. 6 Alternate Architectures Windows host VI and RT Stand alone FPGA VI controller VI Stand alone FPGA VI and Standalone RT controller RT controller VI VI INVESTICE DO ROZVOJE VZD L V N 9 6 FPGA Functions O Hardware based timing and triggering Low level signal processing INVESTICE DO ROZVOJE VZD L V N Real Time Controller Functions FPGA interaction Configuring Communicating data Controlling Processing data Logging data Communications with remote PC host INVESTICE DO ROZVOJE VZD L V N Windows PC Functions Logging data Accessing databases ntegrating with enterprise systems Providing a human machine User interface HMI and display Supporting supervisory control INVESTICE DO ROZVOJE VZD L V N 1 Controller 3 Controller Slot 2 Captive Screws 4 Raconfigurable Embedded Chassis INVESTICE DO ROZVOJE VZD L V N INVESTICE DO ROZVOJE VZD L V N ki n il JE
2. e Implementing a DMA FIFO with Polling Oto number elements Returns elements to read A is bp Element gt Timeout Ti F B RIOO INVESTICE DO ROZVOJE VZD L V N A F Direct Memory Access Writing multiple channels of data to a DMA FIFO by interleaving Ean Madz AIO r b DMA FIFO Jii P A Mod2jAT1 T write AA Modz AI25 x Element gt Timed Out 29 5 2012 e k I T 4 H ics oi MEC EVROPSK UNIE lud JNE e Reading multiple channels from a DMA FIFO in the host pereo Read FIFO FPGA Target Points to Read RIOO EE Waveform Graph A O Decimate the 1 D array to separate interleaved data Backlog pusz TP INVESTICE DO ROZVOJE VZD L V N BER n ill JE Lossless Application Overflow DMA Full Underflow Check for 50400 y DMA FIFO Read 1 FIFO Full ft gt Number of Elements gt pod MOne a il i gt Timeout ms i FIFO Full Elements Remaining INVESTICE DO ROZVOJE VZD L V N BER On T 5 Overflow too many
3. Avoid race conditions by e Controlling shared resources e Properly sequencing instructions e dentifying and protecting critical sections within your code e Reducing use of variables Initialize shared variables Otherwise they retain values from previous executions or default values of associated front panel objects INVESTICE DO ROZVOJE VZD L V N A A Race Conditions Parallel loops Write Loop running at the same rate as the Read Loop j Multiple Loops vi Front Panel on My Computer Log 13 Multiple Loops vi Block Diagram on My Computer aax File Edit View Project Operate Tools Window Help d c nu 13pt Application Font EARE e5 Random Number STOP Amplitude Number of Loop Iterations Random Number Race Neie Amplitude File Edit View Project Operate Tools Window Help Pla eime Random Number pop b 4 Race n Py Computer M 3 29 6 2012 EE iud MM 187 E UNIE iuf A A Race Conditions Parallel loops Write loop running slower than Read Loop Underflow 13 Multiple Loops vi Front Panel on My Computer 13 Multiple Loops vi Block Diagram on My Computer aax File Edit View Project Operate Tools Window Help 13pt Application Font v for
4. e User1 Switch User defines the behavior of the User1 switch with the RT Read Switch VI in a LabVIEW Real Time embedded application INVESTICE DO ROZVOJE VZD L V N 6 9012 Controller LEDs 1 POWER 2 FPGA 3 STATUS 4 USER INVESTICE DO ROZVOJE VZD L V N Power LED Lit indicates the power supply is adequate and the controller is supplying power to the CompactRIO system FPGA LED Programmable for application debugging or status Refer to LabVIEW Help for information about programming User1 LED Programmatically definable to meet the needs of your application in the RT VI INVESTICE DO ROZVOJE VZD L V N Status LED Off during normal operation ndicates errors by flashing certain patterns Slow continuous flashing The controller is unconfigured Use MAX to configure 2 flashes Software error Reinstall software Use MAX Help 3 flashes Safe Mode DIP switch is in the ON position 4 flashes The controller software has crashed twice without rebooting or cycling power between crashes Controller may be out of memory Review your RT VI Continuous flashing Unrecoverable error Contact NI Continuousl
5. RT Host and Interrupts RT host must acknowledge interrupts Use Wait on IRQ and Acknowledge IRQ methods e IRQ Number s specifies the logical interrupt for which the function waits Timeout ms specifies the number of milliseconds the VI waits before timing out 1 infinite timeout Timed Out returns TRUE if this method has timed out RQ s Asserted returns the asserted interrupts Empty or 1 array indicates that no interrupts were received INVESTICE DO ROZVOJE VZDEL VAN e Acknowledge IRQ method Acknowledges and resets any interrupts that have occurred to their default values Wire after the Wait on IRQ method IRQ Number s specifies the logical interrupt or array of logical interrupts for which the function waits INVESTICE DO ROZVOJE VZD L V N HENCE stop L INVESTICE DO ROZVOJE VZD L V N EVROPSKA UNIE lf INE a Transfers data from FPGA directly to memory on the RT controller through bus mastering Streams large amounts of data Provides better performance than using local FIFO and reading indicators Host processes data while FPGA transfers data to host memory Without DMA processor must read data
6. Reset Button SME Connactor H I 45 Ethamat Port Power Connactor USE Port DIP Switchas H amp 232 Serial Port INVESTICE DO ROZVOJE VZD L V N ki n il JE le NEN 9012 RT Controller Memory Nonvolatile DRAM Nonvolatile memory stores information even when not 128 MB 64 MB powered Used for drivers storing Vis and the Shared Variable Engine DRAM is volatile memory and will be lost on power down Used for allocating memory and running applications INVESTICE DO ROZVOJE VZDEL VAN a D Components Ov Screw Signal Terminals Conditioning d Signal 2 E Conditioning Signal Conditioning k DSUB S Signal Custom Conditioning Sensors Connector Attenuation Digitizers Reconfigurable High Speed amp Actuators Block amp Filters amp Isolation FPGA Bus 29 6 2012 ort 2 I T te S TME EVROPSK UNIE lag E 17 Custom circuitry for per the measurement type Direct connection to Industrial sensors and actuators S Sa Ca Ca Cos Cos Cos Sa S INVESTICE DO RO7VOJE V7D L V N Used with PC based R Series devices Digital 1 Cable 2 A Series Expansion Chassi
7. Basic Example Simple set of code with inputs and outputs Takes 7 clock cycles to execute 5 cycles for the code 2 for the loop If Input 1 for i 0 3 Output 1 5 9 13 INVESTICE DO ROZVOJE VZD L V N Basic Example Pass data to next step of code by using shift registers Takes 5 clock cycles to execute 3 cycles for the code 2 for the loop If Input 1 for i 0 3 e Output 1 5 Output INVESTICE DO ROZVOJE VZDEL VAN lvo Basic Example Can maintain look and feel of original application by using Feedback Nodes in sequence with code Same functionality as a Shift Register Maintains more congruous VI appearance INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE bu t Loop Rate Ticks A Loop Rate Ticks 2 Above Threshold P AA Mod3 AO0 B Analog Input i Analog Input 170 Ticks 2Ticks 38 Ticks 2 Ticks 170 Ticks 2 Ticks l 172 clock cycles 212 clock cycles 5 3 Scaling Analog Output 4 3 us Us 2Ticks 38 Ticks 19 Faster m mm BIER JOY ME INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE luf L EE aim ha Pipelining What to do if your diagram e
8. Deterministic tasks can consume all processor resources Use Wait ms and Wait Until Next ms Multiple VIs to pause deterministic loops and allow non deterministic tasks to execute n Tick Count Wait ms Wait Until To Time St 12 00 01 11207701 Get Date Get Date Date Time Seconds T Time Stam HE Time Delay Elapsed Ti Format Da INVESTICE DO ROZVOJE VZD L V N Wait VI Constant time of execution Execute A Execute B sleep 10 ms Function vi Function B vi Wait vi Wait Until Next Multiple VI Variable time of execution Execute A Execute B sleep until OS timer reaches next multiple of 20 ms Function 4 vi Function B vi Wait Until Next ms Multiple Wait Until Next Multiple vi INVESTICE DO ROZVOJE VZD L V N cM Timed Structures Timed Loop and Timed Sequence Priority Configurable Period 100 ms Acquire 50 ms Loop idle 50 ms LabVIEW executes lower priority tasks during idle time INVESTICE DO ROZVOJE VZD L V N Add a VI under the cRIO target n z INVESTICE DO ROZVOJE VZD L V N File Edit View Project Operate Tools Window Help F fei Project Temperatu
9. To benchmark FPGA VI Speed use Tick Count VIs Reguires additional code for testing Typically removed in final application To benchmark FPGA VI Size analyze the Compile Report Compile Size unknown until entire compile is complete INVESTICE DO ROZVOJE VZD L V N Benchmark the Execution Speed of a VI Use Tick Count VI to determine execution speed Get initial time Execute code Get final time Calculate the difference Code can be removed later Timestamp measurements done in parallel Does not affect execution speed INVESTICE DO ROZVOJE VZD L V N Benchmark the Loop Rate of a VI Loop Rate limited by maximum speed of code in z loop Maximum loop rate limited by code execution time plus 2 ticks 1Tick 1 Clock cycle Clock cycle depends on compile rate Default 40 MHz INVESTICE DO ROZVOJE VZD L V N Benchmark the Loop Rate of a VI Timestamp each iteration Output brs2 Calculate the difference Z Input Code can be removed later Timestamp measurements done in parallel Does not affect execution speed INVESTICE DO ROZVOJE VZD L V N
10. File Edit View Project Operate Tools Window Help ple m 1 Sc bal of 13pt Application Font 1 S fh Random Number Random Number m 1 Race Value Race Value m STOP Random Number PDBL Race Number of Loop Iterations Number of Loop Iterations te v gt EE gt z in i il 9 E e f ai a 188 EVROPSK UNIE Wu A A Race Conditions Parallel loops Write loop running faster than Read Loop Overflow 13 Multiple Loops vi Front Panel on My Computer Jas 13 Multiple Loops vi Block Diagram on My Computer E File Edit View Project Operate Tools Window Help File Edit View Project Operate Tools Window Help P ol 13pt Application Font 25 Tar gt gt AES amp ul 9 ez bal 4 13pt Application Font Random Number Random Number 1 Race Value Race Value mm STOP mm hl Random Number Race Value gt ES mi gt S Race Amplitude Amplitude Number of Loop Iterations Number of Loop Iterations gt Freezers gt 20 5 2012 B3 EVROPSK UNIE lu The level of synchronization needed is application dependent Synchronization is not required in some slower control applications Synchronization is required if you need to acquire data w
11. Disconnect Disconnects from the Compile Server to continue working in LabVIEW Run the VI again to reconnect INVESTICE DO ROZVOJE VZDELAVANI EVROPSK UNIE af 4 Summary Advanced Status Compilation successful Compilation Summary Device Utilization Summary Number of BUFGMUXs 2 out of 16 12 Number of External IOBs 106 out of 484 21 Number of LOCed IOBs 106 out of 106 100 Number of SLICEs 1100 out of 14336 7 Clock Rates Requested rates are adjusted for jitter and accuracy Base clock 40 MHz Onboard Clock Requested Rate 40 408938MHz Theoretical Maximum 83 243153MHz Start Time 8 24 2007 12 11 32 PM m Do not show this message in the Future INVESTICE DO ROZVOJE VZD L V N View Previous Compile Reports Tools FPGA Module Start Local Compile Server Click the Compile List button Compile Status Server Service ID Client Service ID Start Time 2 Temperatu 8C_FPGATarg A7_FPGA_ohniLy7b 7B 8 24 2007 12 11 32 PM Client Name Status Last Update Time localhost Compile Completed 8 24 2007 12 35 09 PM Details GOSS SS wy WSS pis wit io wong CH does not drive any load pins in the design signal does not drive any load pins in the design DRC detected 0 errors
12. V we INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE luf AL 6 e RT VI common tasks Data processing Perform operations not available on the FPGA target Log data Run multiple VIs Control the timing and sequencing of data transfer INVESTICE DO ROZVOJE VZD L V N Common RT Loop Types A time critical loop higher priority floating point control signal processing analysis point by point decision making Normal priority loop executes when time critical loop waits embedded data logging remote panel Web interface Ethernet serial communication INVESTICE DO ROZVOJE VZD L V N A Introduction Windows User Interface Windows RT cRIO Controller Computer Stand alone cRIO Controller FPGA FPGA Usually a Time Critical VI and a Normal Priority Communication VI Stand alone RT CompactRIO Controller FPGA Common RT Configurations 294042012 url EVROPSK UNIE lu BIG 7 w Configuring PXI and a Compact FieldPoint system Real time application design Multithreading Passing data between threads Improving determinism Priority levels Memory management Timed structures
13. Add temporary controls and indicators for debugging if necessary but remove them INVESTICE DO ROZVOJE VZDEL VAN Modular Code Segment code into function blocks subVIs Develop and test blocks independently Takes advantage of parallel execution ability of FPGA INVESTICE DO ROZVOJE VZD L V N Compiling few minutes to several hours Verify logic before compiling LabVIEW bit accurate emulation mode The emulator generates random data Executes logic on the Windows PC Traditional debugging tools are available INVESTICE DO ROZVOJE VZD L V N FPGA Target Properties dialog box Right click the FPGA Target in the Project Explorer window When testing is complete set the FPGA Target to execute VI on the FPGA target General Top Level Clock Component Level IP Conditional Disable Symbols O Execute VI on FPGA Target Execute VI on Development Computer with Simulated 1 0 indom Data for FPGA I O Read as INVESTICE DO ROZVOJE VZDEL VAN FPGA has no user interface Must communicate data fr
14. INVESTICE DO ROZVOJE VZD L V N Getting Started Connect I O modules to Real Time target Install NI Scan Engine on the target Add the target to your LabVIEW project LabVIEW automatically detects modules and create an I O variable for each channel INVESTICE DO ROZVOJE VZD L V N File Edit View Project Operate Tools Window Help w Project Scan Interface Thermocouple Reading lvproj TY My Computer 8 Dependencies i Build Specifications 5 g dio301200052 2 Chassis cRIO 9103 M Modi Slot 1 NI 9211 Ls r 3 NI 9263 amp g MSHESHESHS z 38888 566 one gt oO a 9 a What is an I O Variable A type of shared variable that is tied directly to a physical I O channel Can be used to read write directly to an I O channel File Edit View Project Operate Tools Window Help xo xj s k S al E 31 Project Scan Interface Thermocouple Reading lvproj S gt S My Computer k Dependencies i ks z Build Specifications s 8 5 1 Chassis cRIO 9103 i P Mod1 Slot 1 NI 9211 Mod2 Slot 2 NI 9233 M Mod3 Slot 3 NI 9263 i BP Dependencies LL 7 Build Specifications INVESTICE DO ROZVOJE VZD L V N Creating I O Aliases Provides an extra layer of
15. FPGA RT and PC applications run asynchronously on their own The FPGA can run at nanosecond loop times The RT controller can run at microsecond loop times The Windows PC can run at millisecond loop times This presents problems for communicating data Data can be lost e Data can be read multiple times INVESTICE DO ROZVOJE VZD L V N 6 1 What will the value of the Race Sequence VI be after the first run 2 After the second After the third File Edit View Project Operate Tools Window Help CIN INVESTICE DO ROZVOJE VZD L V N A A Race Conditions A possi b e re S u It A Race Sequence vi Front Panel on My Computer m File Edit View Project Operate Tools Window Help in Race value 30 PS 20 D 15 z 10 5 0 0 Run Number M py compter gt 29462012 As OT aa S M EVROPSK UNIE la j INVESTICE DO ROZVOJE VZD L V N The Race Sequence code has several m problems ET AS e It does not control the Write B sequence of operations WC Will the Readers read value A B or C e There are multiple writers to the shared variable kH Z e The shared variable is un mE E All Readers read value A not initialized
16. 13 Simple Temperature Monitor RT Host vi Front Panel on Temperature Monitor Ivproj JeyEg TEE OE 13 Temperature Monitor FPGA vi Front Panel o Jog DJS amp m ret sorkcatn o 1 2 e Ele Edit View Project Operate Tools Window Help olej 13pt Application Font ox Thermocouple Sample Thermocouple Interval mSec Thermocouple Signal Sample Interval mec 1500 10 00000000000000t gso ex me T T 13 Simple Temperature Monitor RT Host vi Block D 10 00000000000000t Ele Edit View Project Operate Tools Window Help Autozero ole e n g 23 kalR 21 0 oc 13 Temperature Monitor FPGA vi 10 00000000000000t Ele Edit View Project Operate Ic FPGA error out sjej v E gt Thermocouple Sample Interval mSec v emosi Thermocouple Sample Interval msec C 7 H fereratre mortor roin Tero lt s Sample Interval mSec 7 4 Autozero FPGA error out v pas FPGA error out status Autozero a v v Temperature Monkor ivarojicRTO 3012 ig rempersture Monitor IvprojfFPGA Target lt gt FPGA Hostvi lt gt ae INVESTICE DO ROZVOJE VZDELAVANI EVROPSK UNE lf et 78 FPGA Front Panel F P G A h a S i m ite d m e m O ry Hd pm Sample Interva mSec Use simple controls and jo n d cato rs Autozero 0 Use the minimum necessary FPGA error out controls and indicators for programmatic Front panel communication to a host
17. Consists of two parts FIFO part and host part DMA engine transfers data along PCI bus to host memory INVESTICE DO ROZVOJE VZD L V N Show how data is transferred from the FPGA to the host INVESTICE DO ROZVOJE VZD L V N Show how data is transferred from the host to the FPGA e lt Exercises gt CompactRIO Fundamentals Demonstrations INVESTICE DO ROZVOJE VZD L V N Best 8 0 0 0 0 Advanced Code Generation Name Y acc Data Type Target to Host DMA se Data Type Number of Elements Implementation FXP m 8191 Block Memory m Fixed Point Configuration Encoding Signed Minimum O unsigned Word length Maximum 2 S Integer word length Desired delta 4 bits e 9 5367E 7 INVESTICE DO ROZVOJE VZDELAVANI EVROPSK UNIE af 4 e The Number of Elements determines the size of the FPGA part of the FIFO Save resources by choosing the smallest size that is reasonable for your application Compare the rate at which data points are put into the FPGA FIFO to the rate at which the host application will be able to read point
18. INVESTICE DO ROZVOJE VZD L V N Close FPGA VI Reference Stops and resets the FPGA Right click and select Close from the shortcut menu to close the reference without resetting Default is Close and Reset which closes the reference stops the FPGA VI and resets the FPGA Use free label to describe functionality INVESTICE DO ROZVOJE VZD L V N After developing the RT host VI run it Deploying Status Window Deploying nir device conmngset vi 7 9 5 K Deploying nirio DMAReconfigureDriver vi 6 89 K Deploying RT Host Incubator Temperature Monitor vi 1336 91 K Deployment Progress Free Memory 50449 K of 65144 K Total 7796 v CI Close on successful completion INVESTICE DO ROZVOJE VZD L V N Reboot the Conflicts CompactRIO ej TemperatureMonior lvproj Conflict messa mE Right click S SEEN add eMe He PU target Choose Utilities Rebo ot Wait for Power up sequence INVESTICE DO ROZVOJE VZDEL VAN o o NI Example Finder Toolkits and Modules FPGA CompactRIOExamples configured for another target Copy code to your target Open a project where the hardware has been
19. 40 to 70 C INVESTICE DO ROZVOJE VZDEL VAN e Machine Control High speed motion control Real time signal processing and control of power electronics hydraulic systems Custom motion and vision inspection material handling INVESTICE DO ROZVOJE VZD L V N Machine Condition Monitoring Bearing order analysis lubrication monitoring Mobile portable DSA Noise vibration dynamic signal analysis acoustics Distributed Acquisition Central controller with distributed I O nodes over Ethernet wireless INVESTICE DO ROZVOJE VZD L V N ve Automotive 8 Aerospace In Vehicle Data Acguisition Automobiles motorcycles recreational vehicles research aircraft trains Engine and ECU test cells HIL testing of engines and engine controllers sensor simulation using FPGA Rapid Control Prototyping Automotive aerospace control prototyping INVESTICE DO ROZVOJE VZDEL VAN Windows PC Communication Host VI LabVIEW for Windows INVESTICE DO ROZVOJE VZD L V N CompactRIO System Reconfigurable FPGA Inter Thread WESS FPGA NU Communication 7775 7728 1 Interface FPGA VI LabVIEW Real Time
20. Benchmark the Size of a VI Compilation Summary Summary Advanced Status Compilation successful Compilation Summary Device Utilization Summary Number of BUFGMUXs 2 out 16 12 Number of External IOBs 103 out 484 21 Number of LOCed IOEs 103 out 103 100 Number of MULT18X18s 2 out 96 2 Number of RAMB16s 3 out 96 3 Number of SLICEs 2021 out 14336 14 Clock Rates Requested rates are adjusted for jitter and accuracy Base clock 40 MHz Onboard Clock Requested Rate 40 408938MHz Theoretical Maximum 67 308340MHz Po not show this message in the future n z INVESTICE DO ROZVOJE VZDELAVANI EVROPSK UNIE luf These types of optimizations are relatively easy to implement Require no major changes in code architecture Should be basic programming practice for all FPGA VIs Basic Optimizations primarily affect FPGA size INVESTICE DO ROZVOJE VZD L V N Types of Basic Optimizations Limit Front Panel Objects Bitpack Boolean Logic Use Small Data Types Avoid Large Functions Optimize Comparisons Reentrant vs Non Reentrant SubVIs INVESTICE DO ROZVOJE VZD L V N Limit Front Panel Objects Each Front Panel Object on the Top Leve
21. Chassis cRIO 9103 E FPGA Target RIOD cRIO 9103 G Chassis 1 0 J Medi S g Mod2 d Modz aro de Modzjan d Modzjarz d Mod2 ars Modz start i amp Mod2 Stop S g Mod3 f JED Mods Slot 3 NI 9263 EB mode Slot 2 NI 9233 iR Modi Slot 1 Nr 9211 i B 40 MHz Onboard Clock j m Untitled 223 i 35 Dependencies B t Build Specifications 8 Dependencies 1 Build Specifications INMESTICE PO ROZVOJE VZDEL VAN k E Lesson 8 Slides lvproj FPGA Target Ale e P IUU Mod2 Start If you read multiple channels place all in the same node to ensure synchronous reads The I O Node does not return until new data has been acquired f the NI 9233 did not start or stops while the node is waiting the node returns a timeout error You cannot perform other operations such as accessing TEDS info or properties while the NI 9233 is in acquisition mode Data Rate 5 Data Rate Mod2 AA a DMA FIFO Element Timed Out m Timed Out gt EE INMESTICE PO ROZVOJE VZDEL VAN an e NI9233 is internally timed Do not put timing functions in the loop If the loop time is slower than the NI 9233 data rate the I O Node returns an overrun warning and continues to read data The warning indicates one or more p
22. Event response TCP IP communications Verifying timing and memory usage Execution Trace Tool Kit Deploying an application Remote panels RT Wizard INVESTICE DO ROZVOJE VZDEL VAN Ardence Phar Lap Embedded Tool Suite ETS real time or Wind River s VxWorks LabVIEW Real Time Module to develop VIs MS Windows is not a real time OS Deterministic responds reliably to an event or performs an operation within a guaranteed time period INVESTICE DO ROZVOJE VZDEL VAN Jitter Variation in Loop Cycle Time T Loop Cycle Time 1 T Loop Rate Jitter Range l u Desired Loop Time Maximum nm Jitter z a 1 a t m S2 si z a 3 s C x o u o INVESTICE DO ROZVOJE VZDEL VAN Some shared resources can only be accessed by one process at a time These resources can cause jitter SD S SD Running Waiting SD Running After Task 1 finishes Task 2 can proceed GD Waiting Examples I O memory variables and FIFOs non reentrant VIs FPGA does not need to share resources jitter can be as low as 250 picoseconds INVESTICE DO ROZVOJE VZDEL VAN
23. Less chance of engine being unavailable due to crash or user intervention Other computers reading the data do not use resources on target a Project Explorer Temperature Monitor Max i File Edit View Project Operate Tools Window Help l heaixooxlijgim B Project Temperature Monitor Ivproj e H My Computer e 3 Untitled Library 1 I REESE i Dependencies i i Build Specifications IS cRIO 9012 10 0 36 43 Temperature Monitor lvproj My Computer lt INVESTICE DO ROZVOJE VZD L V N ki n il JE K Race Conditions Timing or events or scheduling of tasks may unintentionally affect an output or data value Common problem for Parallel execution Sharing data between tasks Difficult to debug Canreturn the same value 1000s of times Capable of returning a different value at any time Refer to information presented later on avoiding race conditions INVESTICE DO ROZVOJE VZDEL VAN ve Race Conditions Direct Memory Access Buffering and Synchronization Hardware Timed Data FPGA FIFOs Acquisition Handshaking Interrupts Lekcia 8 DATA TRANSFER INVESTICE DO ROZVOJE VZD L V N
24. Loop Timer function vs Wait function Loop Timer function allows code to execute right away during the first iteration Wait function delays the code execution Functions E Programming Timing INVESTICE DO ROZVOJE VZD L V N Thermocouple Sample Interval mSec Ban ModllTCO CER IB Mod1 Autazero B x Host VI starts and stops FPGA INVESTICE DO ROZVOJE VZD L V N When designing an FPGA VI consider communications with an RT or Windows host Host FPGA Interface functions allow you to Establish and terminate communication with the FPGA Download abort reset and run the FPGA Read and write data to the FPGA Wait for and acknowledge FPGA interrupts Read DMA FIFOs direct memory access first in first out buffers INVESTICE DO ROZVOJE VZDEL VAN o 8 rogrammatic Front Panel Communication
25. POST POST Complete 1 Power LED ON 1 Power LED ON io s 2 Status LED OFF 3 User1 LED ON 3 User1 LED OFF INVESTICE DO ROZVOJE VZD L V N DIP switches ON OFF L SAFE MODE L7 CONSOLE OUT IP RESET L NOAPP 7 USER INVESTICE DO ROZVOJE VZD L V N oM Safe Mode Switch Determines whether the embedded LabVIEW Real Time engine launches when the controller boots Normal operation is the OFF position f ON only the essential services required for updating configuration and installing software are loaded Use ON if the software on the controller is corrupted ON required to reformat the drive Refer to MAX Help for more about installing software and reformatting the drive INVESTICE DO ROZVOJE VZD L V N Console Out Switch Serial Communication Serial port Configuration 9 600 bits per second Eight data bits No parity One stop bit No flow control Keep the Console Out switch in the OFF position during normal operation INVESTICE DO ROZVOJE VZD L V N IP Reset Switch ON position and reboot resets the IP address to 0 0 0 0 If on your
26. abstraction from the physical I O channel Created in the Project Explorer Create a new variable on the RT target Modify the Shared Variable Properties dialog box INVESTICE DO ROZVOJE VZDEL VAN a Type li Double I O Alias Enable Network Publishing 29 Double double 64 bit real 15 digit precision Enable Timestamping Aliasing Bind to MO Variable v cRIO 9012 Mod1 a10 ccess Type Acce read only v Custom Scaling You can enable scaling on an I O variable or alias on the Enable Scaling Scaling page of the Shared sec pm m Variable Properties dialog box pem ing Full Scale A 10000000 Engineeri 100 00000 E Raw Zero Scale Engineering Zero Scale Example I O variable nam 8 0 00000 ie O Coerce to Range associated with a thermocouple input Create a Celsius alias and a Fahrenheit alias Scale each alias and use them to display temperature data in both scales INVESTICE DO ROZVOJE VZDEL VAN Bari Fo gt Network Publishing of I O Variables Use to monitor I O values on a host computer or to access an I O variable from a remote target Enable disable network publishing in the Share
27. 1 MS s Single cycle while loops execute at 40 MHz 25 ns Due to parallel processing ability adding additional computation does not necessarily reduce the speed of the FPGA application INVESTICE DO ROZVOJE VZDEL VAN True simultaneous parallel implementation of F A B C and Z X Y M in separate gates on an FPGA F A B C Z X Y M INVESTICE DO ROZVOJE VZD L V N FPGA Development Process No operating system on the FPGA Download and run only 1 VI at a time FPGA can run independently of the host FPGA can store data Add a VI in the FPGA Target activates the FPGA palette INVESTICE DO ROZVOJE VZD L V N V Interactive Front Sia Eee JESTE Panel i E Me Communication u Cum ml Pla PCA Lu Frid Fund m FI TEI IEA IER SI THART Epi ula SUA SEA Trid n a Ve Beir Ni Bhi FPGA VI FPGA VI Front Panel Block Diagram Hast Computer FPGA Target INVESTICE DO ROZVOJE VZDEL VAN FPGA is fast and reliable FPGA has limited space FPGA RTorPC Time critical Data analysis control Acauisition File I O Timing in the User interface FPGA INVESTICE DO ROZVOJE VZDEL VAN Fi
28. 2 Blocking memory map and Access communicates directly with the I O device driver INVESTICE DO ROZVOJE VZD L V N Configuring Scan Mode Settings Open the LabVIEW project Right click on the Real Time Scan Period target and select Properties Imm to show the Real Time CompactRIO Properties dialog box Select Scan Engine from the Category list to display the Sca n Engi ne Pa ge NOTE Configuration on this page will be deployed only if the NI Scan Engine is installed on the target Set the Scan Period ul Network Publishing Period ms and Scan Engine Priority Network Publishing Period ms 100 Scan Engine Priority Above time critical highest u dw INVESTICE DO ROZVOJE VZDEL VAN o e Scan Engine Page Scan Period Period of the NI Scan Engine Network Publishing Period ms How often the target updates published values on the network Should not be faster than the scan period Scan Engine Priority Priority of the NI Scan Engine thread on the Real Time target INVESTICE DO ROZVOJE VZD L V N Scan Period NI Scan Engine executes at regular intervals determined by the scan period Choose a
29. 2 1 Bl NI RIO 3 0 0 Bl unio 3 0 X Uninstall all software 3l August 2005 ist 2008 minimal August 2008 August 2008 an Update BIOS NATIONAL ON NSTRUMENTS Click Next to manually select the individual Features you want to install Contents of current installation DataSocket For LabVIEW Real Time 4 5 5 LabVIEW PID Control Toolkit 8 6 LabVIEW Real Time 8 6 Modbus I O Server 1 5 0 MI Scan Engine 1 0 0 NI RIO 3 0 0 NI RIO IO Scan 1 0 0 MIT Cavid nT 22 dm z EE NEC TONS INVESTICE DO ROZVOJE VZDEL VAN Verify proper installation settings After proper configuration is set click Next to install After install reboot the RT Controller Features Select the Features to install and installed components to uninstall NATIONAL P OANSTRUMENTS a x National Instruments RT Software up DataSocket For LabVIEW Real Time 4 5 5 a 3 LabVIEW Real Time 8 6 GD LabVIEW PID Control Toolkit 8 6 apj Web Server for LabVIEW RT 1 0 0 Modbus IO Server 1 5 0 NI Scan Engine 1 0 0 NI RIO 3 0 0 NI RIO IO Scan 1 0 0 NI Serial RT 3 3 2 NI VISA 4 4 NI VISA Server 4 4 X NI Watchdog 3 0 0 Reinstall the Feature Leave the feature installed Show dependent features Network Variable Engine allows the LabVIEW Real Time target to host I O servers and network publish
30. 80 mV 24 Bit Thermocouple Input Module FPGA I O Node You can use an FPGA I O Node configured for reading with this device Terminals in Software Use the FPGA I O Node to access the following terminals for this device TCx Thermocouple input channel x where x is the number of the channel The NI has TC channels 0 to 3 CIC Cold junction compensation channel For the best accuracy read the CJC channel in the same FPGA I O Node as the thermocouple input channels You must convert the CIC data to temperature Autozero Autozero channel For the best accuracy read the Autozero channel in the same FPGA I O Node as the thermocouple input channels Arbitration This device supports only the Arbitrate if Multiple Reauestors Only option for arbitration You cannot configure arbitration settings for this device Methods This device does not support any methods Module Properties Use the FPGA I O Property Node to access the following properties for this device This device does not support any I O properties EVROPSK UNIE z Bio n Categorized by module Default Naming e HS i Build Specifications Convention x amp fi lt R10 9012 10 0 0 3 e 1 Chassis cRIO 9103 i LU Modi Slot 1 NI 9211 e Scan Mode ModX ChannelY a Slot 2 NI 9233 FPGA Mode ModX oam ModX ChannelY rx Moda Slot 3 NI 9263 i sg 400 je
31. Control can replace eight Boolean Controls Maintains same information using 1 8 as many controls Use functions to still manipulate data in same manner INVESTICE DO ROZVOJE VZD L V N INVESTICE DO ROZVOJE VZDEL VAN Use Small Data Types Eliminate coercion dots Determine necessary input format nsert conversion function ntentional coercion creates a more efficient compile INVESTICE DO ROZVOJE VZD L V N Avoid Large Functions Not all functions are equal Quotient Remainder kat Scale By Power of 2 free if use constant for power m Array Functions should use constants where possible INVESTICE DO ROZVOJE VZD L V N ve Optimize Comparisons e Often comparisons can be replaced with lower level functions Refactor the code with simplified comparisons caercedix i In Range INVESTICE DO ROZVOJE VZD L V N o Optimize Comparisons e Can replace comparison functions with bit logic Easiest to compare power of 2 Must restructure code to change comparison value Same result but us
32. EW nm c Ji FPGA Target RIOD cRIO 9103 LabVI a 2 MM LabVIEW Real Time LabVIEW FPGA J Medi Mod2 Mod3 40 MHz Onboard Clock Modi Slot 1 NI 9211 be Mod2 Slot 2 NI 9233 L M Mods Slot 3 NI 9263 i m FPGA vi i 4 Dependencies d i We Build Specifications i m RT Host vi Dependencies L Build Specifications r 7 w INVESTICE DO RO7VOJE V7D L V N EVROPSK UNIE luf File Edit View Project Operate Tools Window Help 6heaixoox mwaljm eslzsoe S W My Computer Target Folder a Explore Targets and Devicesin i i f Build Specifications Show in Files View Ctrl E Save Save As Save All this Project Mass Compile View Find Items with No Callers Find Missing Items Expand All Collapse All Rename Properties INMESTICE PO ROZVOJE VZDEL VAN k E Existing target or device Finds already configured device Existing device on remote subnet Need to point to target if outside the local network INVESTICE DO ROZVOJE VZD L V N Targets and Devices Existing target or device Discover an existing targets or device s O Existing device on remote subnet Specify a device on a remote subnet by address O New target or device Create a
33. Handling error out Right click the I O Node to show error terminals Error information is useful for debugging and validating data but it uses space on the FPGA and can slow execution INVESTICE DO ROZVOJE VZD L V N Place I O Nodes from palette or Project Explorer File Edit View Project Operate Tools Window Help see Visible Items Help Examples Description and Tip Set Breakpoint FPGA I O Palette Create Replace Find FPGA I O in Project Show Error Terminals Change rite Add Element Remove Element Add New FPGA I O Properties on ee Chassis IJO b Mod2 Mod3 r Mod1 TC1 Mod1 TC2 Mod1 TC3 Mod1 CIC Modi Autozero Temperature Monitor lvproj FPGA Target lt INVESTICE DO ROZVOJE VZD L n z z AVANI E Ex Bd Project Untitled Project 3 I My Computer 8 Dependencies 1 Build Specifications cRIO 9012 10 0 0 3 WE Chassis cRIO 9103 amp j FPGA Target RIOO cRIO 9103 a Chassis 1 0 I Modi i Modi TCO dg Modi TCI di Modi TC2 b p Modi TC3 ode ModijCIC FN Modi jAutozero J Mod2 p Mods E 40 MHz Onboard Clock M Modi Slot 1 NI 9211 M modz Slot 2 NI 9233 1 Mods Slot 3 NI 9263 jej Untitled 1 SP Dependencies iw Build Specifications SP De
34. Instruments ONANSTRUMENTS recommends the Following software sets for your target W l t h O u t 4 Click Next to install the Following recommended software set to the target NI RIO 3 0 0 August 2008 NI RIO 3 0 0 with Scan Engine support Augus NI RIO 3 0 0 minimal August 2008 la e N t N k c W LabVIEW Real Time 8 5 1 e O r NI RIO 3 0 0 minimal August 2008 LabVIEW Real Time 8 6 BB NI RIO 3 0 0 August 2008 dt Va ria es 3X LabVIEW Real Time 8 2 1 INI VISA Server 4 4 B NI RIO 3 0 0 minimal August 2008 B NI RIO 3 0 0 August 2008 IN E i x Dl Custom software installation currently installed T Wa tc h d O B S X Uninstall all software PID Loops uu au vy v I Modbus Communication INMESTICE DO ROZVOJE VZDEL VAN ki n il JE Custom software installation is for advanced applications Uses more nonvolatile memory Only install what is necessary to avoid wasting space Software Selection Select the recommended software set you want to install to the target National Instruments recommends the Following software sets for your target 3 X LabVIEW Real Time 8 6 NI RIO 3 0 0 minimal August 2008 NI RIO 3 0 0 August 2008 NI RIO 3 0 0 with Scan Engine support Augus 3X LabVIEW Real Time 8 5 1 NI RIO 3 0 0 minir Bl NI RIO 3 0 0 Aug 3X LabVIEW Real Time 8
35. Open Add Find Project Items Save Save As Save All this Library Save for Previous Version Find b Show Error Window Deploy Deploy All Undeploy Autodeploy Variables Edit Variables Create Variables Create Bound Variables Export Variables Import Variables Expand All Collapse All Remove from Project Properties New y M Virtual Folder Control Library I O Server Class XControl INVESTICE DO ROZVOJE VZD L V N Shared Variable Properties Dialog box Name Description Name Network Data Type Variable Type Variable1 Variable Type Data Type Network Published M Double Enable Network Publishing EE Double double 64 bit real 15 digit precision Enable Timestamping TJ Enable Aliasing Bind to PSP URL Browse Access Type read only INVESTICE DO ROZVOJE VZDEL VAN Bann INVESTICE DO ROZVOJE VZDEL VAN The target you right click will host the variable There are advantages for hosting on each target Variables on Target Variables on Host Delta filtering can reduce updates and Less memory and processor use on RT network traffic for non buffered shared target LabVIEW DSC features available
36. and 21 warnings Saving II file in toplevel gen ll Creating bit map Saving bit stream in toplevel gen bit Saving bit stream in toplevel gen rbt Creating bit mask Saving mask bit stream in toplevel gen msk Bitstream generation is complete INVESTICE DO ROZVOJE VZD L V N Compile List Server Status Idle EVROPSKA UNIE n z Stop Compile Stop Server OA Configure the target automatic load at power up Resource e g RIOD rio remotesystem RIOQ0 x rio 169 254 0 2 RIO0 Download Bitfile to Flash Device Settings Bitfile to Download Download Bitfile Advanced INVESTICE DO ROZVOJE VZD L V N Run when loaded option 1 Right click the FPGA target in the Project Explorer window and select Properties from the shortcut menu The FPGA Target Properties dialog box appears 2 Place a checkmark in the Run when loaded to FPGA checkbox 3 Click the OK button All FPGA VIs you create for the FPGA target will run when loaded 4 Configure the FPGA target to load the VI automatically when powered on INVESTICE DO ROZVOJE VZDEL VAN What if you want to share the I O workload between the FPGA and the real time processor Need FP
37. configured Open a new project Copy drag the cRIO target to the new project Save the new project and close the original project INVESTICE DO ROZVOJE VZD L V N Continued Open the NI Example Finder project and drag the FPGA VI the RT host VI and all other items in the example project to appropriate locations in the new project Remove any unneeded VIs from the original project Save the new project Update the FPGA VI references in the RT Host Recompile the FPGA VI INVESTICE DO ROZVOJE VZD L V N ac e The new target must support all items A If an item is not supported it appears with this icon Unsupported items could be a n e O Resource Clock Resource FIFO Memory Remove or replace the unsupported item INVESTICE DO ROZVOJE VZD L V N Lekcia 7 WINDOWS PC HOST INVESTICE DO ROZVOJE VZD L V N e Overview Shared Variable Network Communications INVESTICE DO ROZVOJE VZD L V N nteractive Front Panel Communication Works between PC and RT controller like it did between the PC and FPGA s good for
38. data points for buffer may lose data e Acquire data slower e Increase number of elements to read on the host e ncrease the rate that the host reads data e ncrease buffer sizes on FPGA and host INVESTICE DO ROZVOJE VZD L V N Show how an overflow of the DMA FIFO can occur if the RT host VI code is too complex INVESTICE DO ROZVOJE VZD L V N ve Underflow not enough data to read FIFO read times Out Increase timeout Read slower Read smaller sets of elements INVESTICE DO ROZVOJE VZD L V N Show how an underflow occurs when the DMA FIFO tries to read data before it is available INVESTICE DO ROZVOJE VZD L V N Recover data and flush FIFO to find out how much data is remaining jE F amp T DMA FIFO Read Number af Elements Timeout m INVESTICE DO ROZVOJE VZD L V N DMA Flush Buffer subVI FPGA Target RIGO 57 DMA FIFO Read Mumber of Elements Timeout ms Elements Remaining File use dialog refnum out INVESTICE DO ROZVOJE VZDEL VAN ki
39. development and debugging s not deterministic PCruns front panel RT runs block diagram INVESTICE DO ROZVOJE VZD L V N Use Network Communications for deterministic communication between PC and RT Controller Network communication allows you to e Run another VI on the host computer Control the data exchanged which front panel objects get updated and when which components are visible on the front panel Control timing and sequencing of the data transfer Perform additional data processing or logging INVESTICE DO ROZVOJE VZD L V N Shared variables automatically publish data values over an Ethernet network Shared variables communicate between Parallel processes Between VIs Between computers INVESTICE DO ROZVOJE VZD L V N Create Shared Variables from the Project Explorer window Shared Variables must be inside project libraries LabVIEW automatically creates the library with the shared variable inside File Edit view Project Operate Tools Window Help Items Files E My Computer F PP Race PF amp Dependencies L Build Specificatic E 5 cRIO 9012 10 14 ii Project Temperature Monitor lvproj
40. load for cRIO modules Enables you to force the values of I O variables Auto View Location 1110 0 0 21Mod11AIO Current Value 80 15177980630747 New Value INVESTICE DO ROZVOJE VZDEL VAN Forcing Values on I O Variables Causes associated I O EL EE channel to assume the value E m 80 15177980630747 you specify amp Systel Network Items Don t have to stop or change the real time application Holds the specified value until You unforce the variable metes Target is rebooted You force the variable to a different value INVESTICE DO ROZVOJE VZDELAVANI EVROPSK UNIE luf 4 e Forcing Values on I O Variables NI Scan Engine does not update values for a forced variable Unforcing the variable returns control to the scan engine Forced values apply to aliases as well as standard I O variables Forced I O variable forces all associated aliases e Forced alias forces parent I O variable and all of its associated aliases INVESTICE DO ROZVOJE VZD L V N Using the I O Variable on the Block Diagram Drag the I O variable or alias
41. n ill 5 NI 9233 does hardware timed data acquisition Search LabVIEW Help NI 9233 or right click in Project Explorer window 4AI Channels sampled simultaneously and two digital channels start stop Set Data Rate statically or programmatically INVESTICE DO ROZVOJE VZD L V N Name Mod2 Module Type NI 9233 Location 4 Ch 5 V 24 Bit IEPE Analog Input Slot 2 vj Calibration Mode Calibrated m Master Timebase Source 12 8 MHz Timebase gt v C Export 12 8 MHz Timebase Data Rate 50 000151s mj Enable TEDS Support Cancel U Create an NI 9233 Property Node and Data Rate property File Edit View Project Operate Tools Window Help DE e E i view v Operate Tools Window Help 13pt 13pt Application Font Font Visible Iterns Help Examples z je i Property Description and Tip Visible Items Set Breakpoint Help FPGA I O Palette Examples Create Description and Tip Replace Set Breakpoint Find Item in Project FPGA I O Palette Add New FPGA I O Create Show Error Terminals Replace Select Property Change to Write Find Item Add Element Add New FPGA I O Remove Element Show Erro
42. 9103 i im Interrupt RT vi B MEM VI ag Dependencies Eso Yi on gt Virtual Folder m Build Specifications Control RIO Device Setup Library Start FPGA Wizard C Series Modules Add FPGA I O FPGA Base Clock Arrange by Expand All Memory Collapse All Component Level IP Remove from Project Rename Help Properties INVESTICE DO ROZVOJE VZD L V N ki n Li Configure Category n INVESTICE DO ROZVOJE VZDELAVAN Advanced Code Generation z FIFO Type Target Scoped v Data Type Number of Elements Implementation 116 v 1028 Block Memory v Fixed Point Configuration Encoding Range O Signed Minimum Unsigned 0 0000 Ward length Maximum 0 bits a 0 0000 Integer word length Desired delta 0 bits 3 0 0000 EVROPSK UNIE k LL Type Select Target Scoped from the Type pull down menu in the Properties Dialog if you want to use a target scoped FIFO Select Host to Target DMA or Target to Host DMA from the Type pull down menu if you want to use a DMA FIFO INVESTICE DO ROZVOJE VZD L V N Implementation disabled for DMA FIFOs e Flip Flops Use ga
43. B FPGA Target RIOO cRIO 9103 Chassis I O Modi Mod2 Mod3 is 40 MHa Onboard Clock M Modi Slot 1 NI 9211 YR Mode Slot 2 NI 9233 i QP Mod3 Slot 3 NI 9263 i dip DWARF i m Untitled 1 vi L BP Dependenc i i ge Build Specifications s Dependencies CE Build Specifications n z INVESTICE DO ROZVOJE VZD L V N Timed Out Fan Speed Control lvproj FPGA Target lt EVROPSK UNIE luf 1 cag FIFO Write Function Element inputs the data element to be stored Timeout inputs the number of clock ticks the function waits for available space in the FIFO if the FIFO is full The default is O or no wait A value of 1 prevents the function from timing out Timed Out returns TRUE if space in the FIFO is not available before the function completes execution If Timed Out is TRUE the function does not add Element to the FIFO INVESTICE DO ROZVOJE VZD L V N Read a DMA FIFO in the host 1 Open a reference to the FPGA 2 Add an Invoke Method function 3 Choose the Data Read Method File Edit View Project Operate Tools Window Help ole le wl IE Mo os FPGA Interface sene B views Z BE amp S X Open FPGA V Read Write C Inv
44. Do not have to learn VHDL True parallel execution Deterministic INVESTICE DO ROZVOJE VZD L V N Real Time Controller Fixed U Resource Fixed V O Resource Fixed U Resource M Fixed I O Resource Bus Interface Communications between I O FPGA and Controller INVESTICE DO ROZVOJE VZD L V N ki n il JE A C Defining FPGA Logic with LabVIEW Turn the FPGAVI into executable code FPGA Module compiles VI Graphical code translated to VHDL e Xilinx ISE compiler creates circuit from VHDL e Compiler optimizes the implementation Abitstream file results Windows OS I LabVIEW cRIO Bitstream loads at run time Bitstream reloads at 1 Intermediate MM power up y 2 Bit File ra On board flash memory Controller over PCI Bus 29462012 MM 105 FPGA provides Timing Triggering Processing Each fixed I O uses a portion of the FPGA logic The PCI interface also uses a portion of the FPGA logic INVESTICE DO ROZVOJE VZD L V N Multi loop analog PID loop rates exceed 100 kHz on embedded RIO FPGA hardware whereas they run at 30 kHz in real time without FPGA hardware Digital control loop rates execute at up to
45. ESTICE DO ROZVOJE VZD L V N Pipelining Within a loop you can split up your code into different loop iterations to reduce the duration of each iteration Handle different parts of the process flow in parallel within one loop iteration Pass data to next piece of code using shift registers INVESTICE DO ROZVOJE VZD L V N Can maintain look and feel of original application by using Feedback Nodes Same functionality as a Shift Register Maintains more congruous VI appearance INVESTICE DO ROZVOJE VZD L V N Pipelining is a technique you can use to increase the throughput or speed of the FPGA VI Takes advantage of the parallel processing capabilities of the FPGA e By using parallel processing increases the efficiency of sequential code Must divide code into discrete steps Wire inputs and outputs of each step to Feedback Nodes or shift registers INVESTICE DO ROZVOJE VZD L V N B Pipelining Drawbacks Require code to be restructured e Greatly reduced by using Feedback Nodes N cycle delay before valid output data e Where N Discrete Steps Used 1 INVESTICE DO ROZVOJE VZD L V N
46. GA for signal processing on some channels but only single point acquisition from others Using some modules that aren t supported by scan mode with others that are INVESTICE DO ROZVOJE VZDEL VAN File Edit View Project Operate Tools Window Help FPGA mode can be used in conjunction with the scan mode E E Dependencies pob ge Build Specifications on a per module basis Modi Slot 1 NI 9211 Modules can be moved from FPGA mode to scan mode in the LabVIEW project Drag from the FPGA target to the RT target and vice versa i mods Slot 3 NI 9263 j Ba Dependencies L Build Specifications BOUT Depend i g Build Specifications INVESTICE DO ROZVOJE VZD L V N ki m Li Compiling when using both FPGA mode and scan mode Scan mode logic will be compiled along with the LabVIEW FPGA VI into a single FPGA application Space used by the RSI on the FPGA scales with the number of modules using scan mode e f there are no modules running in scan mode then RSI will not be included in the compile INVESTICE DO ROZVOJE VZDEL VAN When to use FPGA mode instead of scan mode Analog acquisition at rates above 1 kHz High speed PID control loops running faster
47. O 9103 i Modi Slot 1 NI 9211 i AIO All NE CompactRIO System Reconfigurable AIS lod2 Slot 2 NI 9233 FPGA AIO All Windows m Normal Priority Time Critical LabVIEW AI Host VI VI s FPGA VI AIS lod3 Slot 3 NI 9263 400 401 AO2 i i it BOS i 87 Dependencies i s Build Specifications Wm LabVIEW for Windows LabVIEW Real Time LabVIEW FPGA r mo BIER S viu INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE iuf i 5 3 Project Explorer Temperature Monito File Edit View Project Operate Tools Window Help 5S x HO Xl Eee ne all Items Files Files t Project Temperature Monitor lvproj a E My Computer i UB Dependencies Build Specifications 5 A cRIO 9012 10 14 0 2 M Chassis cRIO 9103 P El FPGA Target RIOO cRIO 9103 Dev Computer E Chassis IO J Modi Mod2 i Reconfigurable Mod3 FPGA 40 MHz Onboard Clock Modi Slot 1 NI 9211 i Normal Priority i iti T LabVIEW i Mod2 Slot 2 NI 9233 VI tie FPGA VI i Ri Mods Slot 3 NI 9263 i wj Temperature Monitor FPGA vi GS Dependencies B i CE Build Specifications E Dependencies i Build Specifications F amp amp 2 CJ m Wm LabVIEW for Windows LabVIEW Real Time LabVIEW FPGA BEP 7 w INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE luf 4 Th
48. TI VYSOKE s U EN Ea MIN Ne Kw STVO K eru OP Vzd lavani Ray VYC pro konkurenceschopnost m INVESTICE DO ROZVOJE LAUR PL VAN EVROPSK UNIE Z klady pr ce a programovania CompactRIO syst mov pre meracie aplik cie Ing Mgr M rk J n s ANV s r o 29 6 2012 Tato prezentace je spolufinancov na Evropsk m soci ln m fondem a st tn m rozpo tem esk republiky 29 6 2012 P vod do CompactRIO platformy Konfigur cia zariadenia Architekt ra aplik ci Scan mode sn mania d t Pr ca s programovate n m hradlov m po om V voj Real time aplik ci V voj aplik cie na riadiacom po ta i CON O U A UN F Transfer d t INVESTICE DO ROZVOJE VZD L V N 1 Controller 3 JO Module 2 Eight Slot Reconfigurable Embedded Chassis 4 Four Slot Reconfigurable Embedded Chassis cRIO 9102 and cRIO 0104 cRIO 9101 and cRIO 0103 Lekcia 1 VOD DO COMPACTRIO PLATFORMY INVESTICE DO ROZVOJE VZD L V N o o Programmable Automation Controller PAC e Analog and digital I O e Floating point processing e Seamless connectivity Embedded A component in a larger system Headless Operates without a user interface and when the host computer is unavailable Rugged 50 g shock
49. Unsigned Word Length The Integer Word Length The total number of bits number of bits used in the used for the Fixed integer portion of the Fixed Point data Point data INVESTICE DO ROZVOJE VZD L V N e Numeric Representation Examples 18 FXP lt 8 7 gt FXP lt 8 6 gt FXP lt 8 7 gt FXP lt 8 6 gt 1 0 5 0 25 0 5 0 25 Representation deta MinValue Max Value U8 1 0 255 128 0 0 64 32 127 127 5 63 75 63 5 31 75 INVESTICE DO ROZVOJE VZDEL VAN File Edit View Project Operate Visible Items Find Control Hide Control Change to Indicator Change to Constant Description and Tip Numeric Palette Create Data Operations Advanced View As Icon Representation Fixed Point Configuration Appearance DataType DataEntry Display Format Documentation Representation Fixed Point Configuration Encoding Range Signed Minimum Unsigned Word length 10 bits a Integer word length 6 bits e I Include overflow status Values on the Data Entry tab have changed INMESTICE PO ROZVOJE VZDEL VAN an Overflow occurs when the result of an ope
50. a and writes True to Data Available When Data Available is True host reads data After data is read host writes True to Data Received FPGA loop iterates when Data Received is True INVESTICE DO ROZVOJE VZD L V N e Communicate over a physical hardware line FPGA Interrupts send a trigger to the host Eliminate polling Allow host to perform other operations while waiting for the Interrupt signal INVESTICE DO ROZVOJE VZD L V N File Edit View Project Operate Tools Window Help Beren For Functions Programming gt a m Structures Array ray m P T Numeric Boolean E lena g Timing FPGA I O Addons Favorites Occurrences Select a VI D First Call Interrupt Interrupt lvproj FPGA Target lt INVESTICE DO ROZVOJE VZD L V N IRC Number n Error m Wait Until Cleared LTE A e IRO Number specifies which logical interrupt 0 31 to assert The default is O e Wait Until Cleared specifies if this VI waits until the host VI acknowledges the logical interrupt The default is FALSE INVESTICE DO ROZVOJE VZD L V N
51. ation is in the project Save the Project i m Mod3 Slot 3 NI 9263 i i ba 400 i M AOI i B AOZ i Z AOS Le eee L ES Build Specifications INVESTICE DO ROZVOJE VZD L V N o 8 Change Properties of a Module 1 Can configure O s b Slot 2 M Alias in Project INVESTICE DO ROZVOJE VZDEL VAN E e Hide Locate gt M Back Forward Options Contents Index Search Fa Type in the word s to search for 9211 Select topic Found 17 Tie gt Location Rank Timing Considera NI DAQ Buffered DMA In FPGA Converting NI 932 Compac Default Input Out NI DAQ u gt FPGA Wizard Su C Series Module Temperature Fun Supported Devic Internal Channels Converting and C Temperature Con USB DAQ Physic C Series Module Series Physical Detecting Out of Internal Channels FPGA Compac FPGA NI DAQ NI DAQ Compac FPGA NI DAQ Compac NI DAQ Compac NI DAQ A Search previous results Match similar words C Search titles only INVESTICE DO ROZVOJE VZD L n z AVANI Module specific information in LabVIEW Help NI 9211 FPGA Interface CompactRIO 4 Channel
52. capability Otherwise you need to ask your network administrator for the appropriate IP settings Obtain an IP address automatically Use the following IP address IP address 169 254 0 1 Subnet mask 255 255 0 Obtain DNS server address automatically Use the following DNS server addresses Preferred DNS server Alternate DNS server File Edit view Tools Help Configuration S a My System gl Data Neighborhood D Reboot A Lock KY Refresh apply Identification a Devices and Interfaces 8 Historical Data 4 Scales 5 Software Serial Number 01 Model cRIO 9012 Obtain an IP address automatically MAC Address 00 80 2f 11 14 67 IP Settings 354EF3 Use the following IP address To Del Name cRIO 93012 c M 1v1 Drivers se mote Systems fi cRI0 9012 a Devices and Interfaces System State Connected Running IP Address 10 0 0 3 SubnetMask 255 255 0 0 omment 181 Rroo Serial amp Parallel Al Software Gateway nl osm O C Password protect Resets Halt system if TCP IP fails Taj Network Settings E System Settings INVESTICE DO ROZVOJE VZDEL VAN Connec
53. d Components INVESTICE DO ROZVOJE VZD L V N Programmable interconnect switches and wires route signals in an FPGA Switches are known as Register Flip Flops Flip Flops pass data on a rising edge of the clock Compiled LabVIEW code produces a Look up Table LUT that defines outputs from all possible input values to a logic function The LUT defines the interconnections between configurable logic blocks CLBs INVESTICE DO ROZVOJE VZDEL VAN Implements a VI that calculates a value for F from inputs A B C and D where F CD A B Interconnect Resources LO Cells fie A x B C x D Luci Blacks INVESTICE DO ROZVOJE VZDEL VAN 6 Greatly simplifies arithmetic on the FPGA e Simplifies computations e Size and speed advantages of integer math Must configure the appropriate range when using fixed point math INVESTICE DO ROZVOJE VZD L V N e Encoding Word Length and Integer Word Length Context Help Data type of wire FRA Numeric fixed point lt 10 6 0 000000E 0 6 333750E 1 6 250000E 2 eEncoding Fixed Point numbers are either Signed or
54. d Variable Properties dialog box INVESTICE DO ROZVOJE VZDEL VAN ve I O Variable Access Methods LabVIEW adds I O variables to a global scan engine memory map and updates all values concurrently Two access methods Scanned I O access e Direct I O access Right click on the I O variable and select either Change to Scanned or Change to Direct depending on the current state of the variable INVESTICE DO ROZVOJE VZDEL VAN RM a aa Scanned I O Access Default setting for each I O variable Use for groups of I O channels that update at a single rate Uses scan engine memory map to perform non blocking I O reads and writes For each read the scan engine returns the most recent value stored in the memory map VO Variables Hardware I O Global Scan Engine Channels Memory Map VO Module 1 VO Module 2 Block Memory Access Transfer JQ C WN PTS ed k Pr aono INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE bu t Direct I O Access Use for single point local I O channels with rates VO Variables Hardware VO asynchronous to the scan Channels VO Module 1 period Bypasses the scan engine VO Module
55. dress from DHCP Server Select Obtain IP address from DHCP server Click Apply Allocate on each reboot New address might not the be the same You must check the address frequently To avoid this use a static IP Some DHCP servers are not compatible Returns 0 0 0 0 after three failed attempts INVESTICE DO ROZVOJE VZD L V N Static IP Address Crossover Cable requires PC and CompactRIO set to Static IP Address e Control Panel Network Connections Local Area Connection Internet Protocol Properties Connect using HB Broadcom Ne treme 57xx Gigabit C This connection uses the following items a File and Printer Sharing for Microsoft Networks da QoS Packet Scheduler m am Uninstall f Description Transmission Control Protocol Intemet Protocol The default wide area network protocol that provides communication across diverse interconnected networks C Show icon in notification area when connected Notify me when this connection has limited or no connectivity INVESTICE DO ROZVOJE VZD L V N Display Configuration Tree Network Settings Help Simultaneously RIO 9012 Measurement amp Automation Explorer File Edit View Tools Help Configuration D Reboot Q Lock KY Refresh Ap
56. ed variables This component requires that the target have at least 32MB total memory Version on the remote target 1 5 0 Available version s on the host 1 5 0 s wa unu v This feature will be installed on the remote target INVESTICE DO ROZVOJE VZDEL VAN Use FTP to display software on CompactRIO Can check Modified column to see last update l ftp 10 0 0 3 File Edit View Favorites Tools Help G Back v gt d Search Key Folders 231 a Address E ftp 10 0 0 3 Other Places Internet Explorer a My Documents a My Network Places Name Size B ni rt tmp Dri rt ini 3 46 KB niwebserver conf 35 bytes E persist pal 0 bytes Type File Folder File Folder Configuration Settings CONF File PAL File v Go Modified 6 18 2008 9 44 PM 7 6 2008 8 33 PM 6 26 2008 7 59 PM 6 18 2008 10 00 PM 6 18 2008 9 19 PM INVESTICE DO ROZVOJE User Anonymous Internet E i 5 73 rmm VZD L V N Baa A i M Lekcia 3 ARCHITEKT RA APLIK CI INVESTICE DO ROZVOJE VZD L V N LL j Create a Project e Add the CompactRIO Target INVESTICE DO ROZVOJE VZD L V N Getting Started m File Operate Tools Help ta LabVIEW 8 a 6 Licensed for Professional Version Ne
57. es half the FPGA resources and executes almost twice as fast Number To Boolean Arra EcLon INVESTICE DO ROZVOJE VZDELAVANI Reentrant vs Non Reentrant SubVIs VI Type FPGA Speed FPGA Utilitization Non Slower Each call to the subVI Lower Only one instance of the reentrant waits until the previous call ends subVI exists on the FPGA Reentrant Faster Multiple calls to the same Higher Each instance of the subVI run in parallel subVI uses space on the FPGA INVESTICE DO ROZVOJE VZDEL VAN Reentrant vs Non Reentrant SubVIs By default Vls created under an FPGA target are reentrant To make a subVI non reentrant change VI Properties Multiple copies of reentrant VIs allow for quick creation of similar code INVESTICE DO ROZVOJE VZD L V N e e Dataflow within the FPGA Parallel Operations Pipelining Single Cycle Timed Loops Combining Optimizations INVESTICE DO ROZVOJE VZD L V N Dataflow within the FPGA Each function or VI takes a minimum of 1 clock tick Functions can run in parallel Some dependent functions must run in sequence Application can only run as quickly as the su
58. from the Project Explorer window onto your LabVIEW Real Time or host VI block diagram Use the placed I O variable to read from or write to the I O channel programmatically INVESTICE DO ROZVOJE VZD L V N EF Proje t Explorer Scan Interface Th Joe M Untitled 1 vi Block Diagram on Scan In File Edit Yiew Project Operate Tools Window Help l heaixooxJiwuim es Ej Project Scan Interface Thermocouple Reading lvproj S Q My Computer i SP Dependencies Build Specifications Be i cR10 9012 10 0 0 2 B ME Chassis cRIO 9103 i M Modi Slot 1 NI 9211 I i i a C AB Modz Slot 2 NI 9233 6 M Mods Slot 3 NI 9263 jm Untitled 1 vi i 87 Dependencies m Build Specifications NI Scan Engine Vls Installed with LabVIEW Real Time Synchronize to Scan Engine Get Scan Engine Period Set Scan Engine Period Get Scan Engine Mode Set Scan Engine Mode Forcing Subpalette Faults Subpalette Functions EJ As ii ES INVESTICE DO ROZVOJE VZD L V N Forcing VIs Disable Variable Forcing Enable Variable Forcing Force Variable Unforce Variable Faults Vls Get Fault List Set Fault Clear Fault Clear all Faults INVESTICE DO ROZVOJE VZD L V N Functions EJ A search S
59. ith a known rate and transfer all data without loss Buffer An area of computer memory where multiple data items are stored Synchronization Tasks occur at the same time or in unison using clock triggers or events f gt 1 U e EVROPSK UNIE lud 44 LL IE INVESTICE DO RO7VOJE V7D L V N 9 6 Methods Handshaking Interrupts Direct Memory Access INVESTICE DO ROZVOJE VZD L V N FIFO First in first out buffer The first data item written to memory is the first item read and removed from memory VI Scoped A single FIFO transfers data between multiple loops in the same VI Target Scoped A single FIFO transfers data between loops on multiple Vis running on the same target DMA A single FIFO transfers data to and from RT VIs by directly accessing memory INVESTICE DO ROZVOJE VZDEL VAN Create Target Scoped or DMA FIFOs from the Project Explorer window File Edit View Project Operate Tools Window Help Pom bo xi ae gt Fal we i Project Interrupt lvproj S W My Computer PoE Dependencies f Build Specifications amp fii cRIO 9012 10 0 0 3 P M Chassis cRIO 9103 _ B FPGA Target RIO cRIO
60. l VI must have logic to interact with the host VI Each read and write from the host to the FPGA is broken down into 32 bit packets to transfer across the bus INVESTICE DO ROZVOJE VZD L V N Limit Front Panel Objects Avoid using Arrays on the Front Panel Compile fails if more bytes in array than are available in RAM 1M Gate FPGA 81 920 3M Gate FPGA 196 608 If only enough time to do 1 optimization do this optimization INVESTICE DO ROZVOJE VZDEL VAN Limit Front Panel Objects Avoid using Arrays on the Front Panel Can quickly use large amounts of FPGA size Each bit in the array uses its own flip flop on the FPGA Count Ticks INVESTICE DO ROZVOJE VZD L V N LUT 1D Replace Large Front Panel Array Controls with Look Up Table VI Provides a general purpose block of initialized memory Limit Front Panel Objects Use look up tables to store waveforms for Signal generation Model nonlinear systems Arithmetic computations Replace the array with a DMA FIFO to stream data INVESTICE DO ROZVOJE VZD L V N ve Bitpack Boolean Logic Display data in integer as binary data U8 Numeric
61. le Edit View Project Operate Tools gt Sa XH Xl ere Re Fall i Project Temperature Monitor lvproj 5 E My Computer i BP Dependencies Build Specifications b cRIO 9012 10 14 0 2 E FPGA Target RIOO cRIO 9103 me 1 i Dependencies Ls 1 Build Specifications n INVESTICE DO ROZVOJE VZD L V N i RIO Device Setup Add Start FPGA Wizard Arrange by Expand All Collapse All Remove From Project Rename F2 Help Properties Virtual Folder Control Library C Series Modules FPGA I O FPGA Base Clock FIFO Memory Lael Vis under the FPGA target inherit the FPGA Function Palette Many palettes are similar to LabVIEW for Windows except the FPGA I O and FPGA Math 8 Analysis Palettes Functions E3 Programming Structures z gt Mumeric FPGA Math amp Synchronization INVESTICE DO ROZVOJE VZD L V N FPGA I O palette Provide communication with I O modules Functions E Programming L FPGA 1 0 TO Made If Constant 110 Method I nun Tur TI Property Select a VI INVESTICE DO ROZVOJE VZD L V N FPGA Math amp Analysis Keep calculations as simple a
62. local subnet and the IP Reset switch is ON the controller appears in MAX with IP address 0 0 0 0 Configure a new IP address for the controller in MAX ON unlocks a controller that was locked in MAX Keep the IP Reset switch in the OFF position during normal operation INVESTICE DO ROZVOJE VZD L V N Restore Defaults f the controller is not able to communicate with the network Changesthe IP address subnet mask DNS address and gateway to 0 0 0 0 e Does not affect power on defaults watchdog settings or VIs To restore defaults Move the IP Reset DIP switch to the ON position Push the Reset button to cycle power to the controller The Status LED flashes once indicating that the controller IP address is unconfigured Move the IP Reset switch to the OFF position INVESTICE DO ROZVOJE VZD L V N o 2 BeB 9 No App Switch ON prevents a LabVIEW startup application from running when the controller powers on To permanently disable the application from running at power up disable it in LabVIEW To run an application when the controller powers on push the No App switch to the OFF position and configure the application in LabVIEW to launch when the controller powers on INVESTICE DO ROZVOJE VZDEL VAN
63. lose and Reset INVESTICE DO ROZVOJE VZD L V N VI scoped FIFO with Programmatic Front Panel Communication 1 I O writes to FIFO and notifies host 2 Transfer loop reads FIFO and passes data to host using Front Panel Communication 3 Host acknowledges transfer and transfer loop sends another data value RT Host FPGA Data Flow Notifier INVESTICE DO ROZVOJE VZD L V N Separate I O and data transfer to speed I O Top loop acauires data Transfer loop reads FIFO and passes data to host using Front Panel Communication INVESTICE DO ROZVOJE VZD L V N 9 6 Clear Method Use the Clear Method to empty a target or Vl scoped FIFO Or call Reset VI method from host INVESTICE DO ROZVOJE VZD L V N Handshaking Checking that a receiving device is ready to receive or a transmitting device is ready to transmit e Host uses Boolean controls and indicators data available and data read flags on the target to coordinate operations e Requires polling INVESTICE DO ROZVOJE VZD L V N FPGA acquires dat
64. m of items in a sequence While Loops have a 2 clock tick overhead f prior slide was in a loop Required 3 clock ticks plus 2 clock ticks for loop Max Rate 40 MHz 5 8 MHz INVESTICE DO ROZVOJE VZD L V N Parallel Operations Graphical programming promotes parallel code architectures LabVIEW Windows and Real Time serialize execution LabVIEW FPGA implements truly parallel execution INVESTICE DO ROZVOJE VZD L V N Parallel Operations Two parallel loops with different sampling rates Run in parallel because there are no shared resources between the two loops 29 6 2012 Parallel Operations Looprates limited by longest path 38 Ticks luSec AO takes about 35 ticks DI takes 1 tick HW Specific DI limited by AO when in same loop Mod3 AO1 i EXPE P AA Mod3 401 INVESTICE DO ROZVOJE VZD L V N Parallel Operations 38 Ticks 1uSec Loop rates limited by longest path AO takes about 35 ticks DI takes 1 tick HW Specific Separate functions to allow DI to run independent of AO This allows DI to be sampled 10 times faster by using a separate loop INV
65. n a reference to the FPGA target before you can communicate between the host VI and the FPGA VI Configure for Open or Open and Run Use free label to describe functionality INVESTICE DO ROZVOJE VZD L V N Invoke Method Invokes method or action from a host VI Methods download abort run wait for and acknowledge interrupts read DMA FIFOs write DMA FIFOs INVESTICE DO ROZVOJE VZD L V N Read Write Control Reads a value from or writes a value to a control or indicator in the FPGA VI on the FPGA target Thermacouple Signal k Thermocouple Sample Interval mSec FPiA error aut k nn Ka Thermocouple Signal A Thermocouple 3 le a Target Thermocouple gt mSec Signa Sample Interval mSec Le l i i FPGA error out AN bes INVESTICE DO ROZVOJE VZD L V N Upcast Converts an FPGA Vl specific reference to a more generic reference Enables using common code to interact with different FPGA Vls The FPGA targets must be of the same class You cannot use this LULU with DMA FIFOs Function i i R RAR Se error out Opens and runs either Add Subtract or Multiply VI on FPGA
66. new target or device by type Targets and Devices Real Time CompactRIO cRIO 9012 Real Time Desktop Real Time PXI Real Time Single Board RIO ith gt New Target or Device Great for testing of equipment before it is in hand Must choose each component individually as it will be set up in final configuration cRIO Controller FPGA Target CSeries Modules on temperature Targets and Devices Existing target or device Discover an existing target s or device s O Existing device on remote subnet Specify a device on a remote subnet by address New target or device Create a new target or device by type Targets and Devices ja Networked Computer Device cRIO 9002 cRIO 9004 cRIO 9012 cRIO 9014 cRIO 9072 cRIO 9073 ss cRIO 9074 Real Time Desktop a Real Time PXI Real Time Single Board RIO v 2 INVESTICE DO ROZVOJE VZDEL VAN File Edit View Project Operate Tools Window Help Verify and Save the Project Add the CompactRIO device al ar a e Select a programming mode T Pa omine Po Build Specifications Scan mode s fi cRIO 9012 10 0 0 3 e E Chassis cRIO 9103 i Li Modi Slot 1 NI 9211 FPGA When all desired inform
67. oints were missed When reading from multiple modules in the same loop and the non NI 9233 is slower either reduce the NI 9233 rate or use two loops Data Rate Mod2 A 3 Data Rate T INVESTICE DO ROZVOJE VZD L V N Timed Out Timed Out LO Ez Stop Ca Optimization Techniques Benchmarking FPGA VIs Basic Optimizations Architectural Optimizations Advanced Optimizations DODATOK FPGA OPTIMALIZ CIA INVESTICE DO ROZVOJE VZD L V N FPGA VIs are limited primarily in two areas Speed Execution rate too slow for specifications Size Requires too much space on the FPGA Uses so much RAM that it will not compile To increase speed and reduce size optimize FPGA code INVESTICE DO ROZVOJE VZD L V N e Some techniques sacrifice speed for size and vice versa e Can use multiple techniques in one VI FPGA Optimization Speed Technigue Limit Font Panel Objects Use Small Data Types Avoid Large VIs X x X X X Use Non reentrant subVIs Use Reentrant subVIs Use Parallel Operations Use Pipelining x X X X Use Single Cycle Timed Loops INVESTICE DO ROZVOJE VZDEL VAN
68. oke Method Close FPGA V Advanced Configure Run Start Abort Reset Stop Wait on IRQ Acknowledge IRQ Download Get FPGA VI Execution Mode Mount SD Card Read TEDS Unmount SD Card 3 i t INVESTICE DO ROZVOJE VZD L V N e Read a DMA FIFO in the Host Number of Elements determines the number of elements to read in each iteration Function completes when elements are read or when timeout is reached m ER DMA FIFO Read Number of Elements k Timeout ms Same overhead for reading a large number as a small number of elements So read more elements if host is too slow Timeout length of time to wait before timeout Default is 5 000 ms 1 indefinite wait Data returns data read Elements Remaining indicates elements remaining in the host part of the DMA FIFO INVESTICE DO ROZVOJE VZDEL VAN Implementing a DMA FIFO with blocking A User specifies number of elements DMA Engine attempts to transfer within the Timeout INVESTICE DO ROZVOJE VZD L V N DMAFIFO dib Write Timeout Element Timeout Count Ticks Timed Out Flat Sequence Structure LES INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE al t1 45
69. om FPGA to Host PC Requires no additional programming Front Panel displayed on Host PC Block Diagram executes on FPGA as compiled Communication layer shares all control and indicator values Cannot use debugging tools when running FPGA VI Test with Emulator first or add indicators as probes INVESTICE DO ROZVOJE VZDEL VAN Me NEN BE IE Open Filtered Isolated TC3 Impedance Thermocouple Differential ADC t Detection Amplifier o INVESTICE DO ROZVOJE VZD L V N Bere n il JE Generating intermediate Files This may take a Few minutes Stage 4 of 6 Processing diagrams Total Click the Run button Converts graphical code to VHDL Generates intermediate files INVESTICE DO ROZVOJE VZD L V N Client ID Temperatu 8C_FPGATarg A7_FPGA_ohniLy7b 7B Status Compile Request Received Updates the client with the latest information from the server Disconnects from the Compile Server while the VI continues to compile To reconnect to the Compile Server right click the VI in the target and select Reconnect to Compilation or click the Run button on the VI Stop Compilation Stops the compilation on the Compile Server and closes the client
70. pendencies 1 Build Specifications Project 3 FPGA Target lt m EVROPSK UNIE OA Loop Timer Function U i Times loop rate IY Programming Timing Wait Adds explicit delay i a Tick Count Pulse length control Tick Count Returns current value of FPGA clock Benchmark loop rates Create custom timers INVESTICE DO ROZVOJE VZD L V N Records current time as initial time during first iteration FPGA error out Thermocouple Sample Interval mSec No delay for Loop Timer then reads channels Second execution adds timer E count to initial time and waits until count has elapsed Subsequent iterations match desired timing synchronization INVESTICE DO ROZVOJE VZD L V N ve Configure Loop Timer T Configure Loop Timer E9 itc Counter Units Counter Units E Ticks clock cycles 40 MHz size of internal counter HSec microseconds E ij mSec milliseconds Size of Internal Counter 8 16 or 32 bit maximum time a timer can track To save space on the FPGA use the smallest Size of Internal Counter possible INVESTICE DO ROZVOJE VZDEL VAN ve
71. period long enough to accommodate both the scan itself and application logic Scan Pariad Scan Period Application Lagic Application Lagic oe Start of End of Start of End of Start of Scan Scan Scan Scan Scan INVESTICE DO ROZVOJE VZDEL VAN Configuring Digital I O Modules Scan mode adds functionality to any 8 channel digital C Series ma A module U r Counter Quadrature encoder e PWM truc No programming required Settings are configured from the LabVIEW project but rur on the FPGA for accuracy and speed INVESTICE DO ROZVOJE VZDEL VAN 4294967296 What is the NI Distributed System Manger GJ NI Distributed System Manage File Actions View Help Auto View Provides a central location for monitoring systems on Forcing the network and managing published data teen rete meas M Provides test panels for CompactRIO modules INVESTICE DO ROZVOJE VZD L V N Test Panel Usage Read write data directly to the I O variables Gives visibility into memory usage and processor
72. ply 329 Hide Help a My System Al a gl Data Neighborhood Identification IP Settings G eak jesi al aj Devices and Interfaces Model cRIO 9012 Obtain an IP address automatically 3 Historical Data Serial Number 01354EF3 Use the following IP address 4 Scales Software MAC Address 00 80 2f 11 14 67 To Default i IVI Drivers Name cRID 9012 Configuration Complete the following steps to configure your remote system fo All E 1 1 Module For a more complete O a Remote Systems System State Connected Running IP Address 10 0 0 3 explanation of these steps refer to E RIO 9012 the LabVIEW Real Time Target Subnet Mask 255 255 0 0 Confiquration Tutorial Comment LI Gateway i 1 Bootinto LabVIEW Real Time DNS Server E 2 Confiqure Network Settings A a 3 Install Softw C Password protect Resets Halt system if TCP IP fails iv 4 Confiqure I O M z m a E31 Network Settings GS System Settings Ez al Connected Running z EVROPSK UNIE lud INVESTICE DO ROZVOJE VZD L V N Static IP Address with Crossover Set IP to desired address INVESTICE DO ROZVOJE VZD L V N General You can get IP settings assigned automatically if your network supports this
73. r Terminals Chassis I O b Modi Mod2 gt Change to Write Module ID b Mod3 Add Element Serial Number Modi Remove Element Vendor ID Moo Select Item Mod3 INVESTICE DO ROZVOJE VZDEL VAN ki On 4 o 8 The NI 9233 Data Rate Control e Custom Ring e Strict Type n INVESTICE DO ROZVOJE VZDELAVAN Edit View Project Operate Tools Window Help 4 Strict Type Def w 13pt Application Font r tar Tr 65 z Data Rate i3 Ring Properties Data Rate A J 50 000 KS s NI 9233 Appearance Data Range Format and Precision FPGA Target C Sequential values Items 50 000 KS s NI 9233 33 333 K5 s NI 9233 25 000 KS s NI 9233 16 667 KS s NI 9233 12 500 KS s NI 9233 10 000 KS s NI 9233 8 333 KS s MI 9233 7 143 KS s NI 9233 Allow undefined values at run time Values z 3 34 35 36 37 30 39 Edit Items Documentation Move Down e P 4 a gt EVROPSK UNIE lud 4 LL IE Drag the Start and Stop items from the Project Explorer window n File Edit view Project Operate Tools Window Help x a Untitled 223 Block Diag Jog B fi Project Lesson 8 Slides lvproj M My Computer OW Dependencies Build Specifications i cR10 9012 10 0 0 3
74. ramming FE FPGA Math amp Synchronization Advanced VI Scoped Me Memory Write Memory Read IST IST Pi Ex VI Scoped FI FIFO Write FIFO Read FIFO Clear INVESTICE DO ROZVOJE VZD L V N ki n ill JE Place an FPGA FIFO Write or Read from the Functions palette Wie Right click the object and fined Ou A choose Select FIFO our Associates node with a c defined FIFO bid amp FIFO Palette Replace gt Show Error Terminals Find Item in Project Add New FIFO INVESTICE DO ROZVOJE VZD L V N ki n 4 FIFO 4Ib write FPGA FIFO Write Terminals I Timeout Element Inputs the data element to store Ime EE Timeout Sets number of ticks the function waits for space if the FIFO is full O default no wait 1 prevents timeout Timed Out Is True if FIFO is not available Does not overwrite Does not add new element Can be lossy INVESTICE DO ROZVOJE VZD L V N Resetting a FIFO FIFOs reset when the VI stops and restarts using the development machine To reset programmatically Use the Invoke Method function Or Use the Close FPGA VI function configured to C
75. ration is outside the range of values that the output type can represent Rounding occurs when the precision of the input value or the result of an operation is greater than the precision of the output type INVESTICE DO ROZVOJE VZDEL VAN Configuring Fixed Point Functions Appearance Output Configuration Representation C Adapt to source _ Fixed Point Configuration Rounding mode Overflow mode Round Half Even Encoding Signed unsigned Word length Mb 8 Integer word length 7 bits C Include overflow status Minimum 0 0000 Maximum 127 8750 l Desired delta 0 0625 Selecting an Overflow and Rounding Mode Use same format for all related functions Mixing fixed point configuration types can cause data loss File Edit View Project Operate Tools Window Help o n 13pt Application Font Numeric Numeric 2 131 252 File Edit View Project Numeric Numeric 2 FXF k HXP Unsigned Unsigned 16 bit word length 16 bit word length 6 bit Integer word length 10 bit Integer word length v Untitled Project 1 FPGA Target Emulator Untitled Project 1 FPGA Target Emulator lt gt INVESTICE DO ROZVOJE VZDEL VAN FPGA Module
76. re Monitor lvproj amp Ej My Computer i de 87 Dependencies FB 6003012 10003 Q Chassis cRIO 91 i 3 is FPGA Target F i 80 Chassis 1 0 40 MHz Ont Modi Slot Mode Slot Mod3 Slot im Temperatur 4 Dependenci i i pe Build Specifi j amp Dependencies i 7 Build Specification 1 Build Specifications Connect Disconnect Utilities Add Virtual Folder Deploy Deploy All Arrange by Expand All Collapse All Remove from Project Rename F2 Help Properties Control Library Variable I O Server Targets and Devices UN ve FPGA Interface Functions Palette Establish and terminate T Search S View Miei Y communication with the FEE FPGA VI B Open FPGA V Read Write C Invoke Method Download abort i e and run the FPGA VI on the Close FPGA W Advanced FPGA target Read and write data to the FPGA VI Wait for and acknowledge FPGA VI interrupts Read DMA FIFOs INVESTICE DO ROZVOJE VZDEL VAN Open FPGA VI Reference Opens a reference to the FPGA VI or bitfile and FPGA target FPi3A Target RIO Select VI and target in the shortcut menu Or specify target with the resource name input Right click and choose show resource name input Must ope
77. ree levels indented 1 2 INVESTICE DO ROZVOJE VZD L V N ki n ill JE Pr O j e ct File Edit View Project Operate Tools Window Help My Computer hy Example lvproj and RT E w Ti Hierarc E Fu Dependencies FPG A i gs Build Specifications m cRIO 9012 10 0 0 3 S o m Chassis cRIO 9103 i isi FPGA Target RIOD cRIO 9103 i E Dependencies k 7 Build Specifications Vis reside under File Edit View Project Operate Tools Window Help their target amp led Project Hierarchy Example lyproj 5 aid Computer as Danendendes Build Specifications s cRIO 9012 10 0 0 3 gt Chassis cRIO 9103 i B FPGA Target RIOO cRIO 9103 JJ Chassis 1 0 c J Modi A Mod2 e a Mod3 i iy 40 MHz Onboard Clock D Mod Slot 1 NI 9211 B Mod Slot 2 NI 9233 ie Mod3 Slot 3 MI 9263 Dependencies i ee Build Specifications i ndencies A d Build Specifications INVESTICE DO ROZVOJE VZD L V N Reconfigurable FPGA 3 Project Explorer Hierarchy Example lvproj File Edit View Project Operate Tools Window Help Windows Sa LabVIEW ag l x b S bk ER d on oe 5 HostVI Y 1 io FPGA VI Items Files k Project Hierarchy Example lvproj S Hj My Computer POL im Windows Host vi S Dependencies J Build Specifications E cRIO 9012 10 0 0 3 M Chassis cRIO 9103
78. ress 10 0 0 3 Subnet Mask Gateway a DNS Server gt gt C Password protect Resets Halt system if TCP IP fails Comment 1 Network Settings RE System Settings Connected Running INVESTICE DO ROZVOJE VZDELAVANI EVROPSK UNIE af 4 B P Address Subnet Mask Gateway DNS Address INVESTICE DO ROZVOJE VZD L V N Static IP Address File Edit View Tools Help Configuration a My System Bl Data Neighborhood l Devices and Interfaces Historical Data 4 Scales D Software iij IVI Drivers a Remote Systems E eR10 9012 System State Comment Reboot Lock KY Refresh Apply lt show Help Identification Model cRIO 9012 O Obtain an IP address automatically Serial Number 01354EF3 Use the following IP address MAC Address 00 80 2f 11 14 67 2 De IoDetauk Name cRIO 9012 IP Settings IP Address Subnet Mask Connected Running If a Gateway and DNS are Gateway DNS Server not available leave them INVESTICE DO ROZVOJE VZD L C Password protect Resets EVROPSK UNIE luf V N o ee Automatic IP Ad
79. s 3 JO Module INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE bu t 9 A G Accessories Industrial enclosures Flat panel touch screen industrial computers Power supplies 29 6 2012 1 Hardware ships with User Manual Getting Started Guide Installation Guide Can search for updated manuals online ni com manuals All product listings on ni com contain links Data Sheets and manuals INVESTICE DO ROZVOJE VZD L V N NI cRIO 9012 Real Time Controller with 64 MB DRAM 128 MB Storage Embedded controller runs LabVIEW Real Time for deterministic control data logging and analysis 400 MHz processor 128 MB nonvolatile storage 54 MB DRAM memory 10 1 0OBaseT Ethernet port with embedded Web and file servers with remote panel user interface Full speed USB host port for connection to USB flash and memory devices RS232 serial port for connection to peripherals dual 9 to 35 VDC supply inputs 40 to 70 C operating temperature range g A vata Sheet Specifications a Configure System Additional Product Information s Manuals 2 5 Dimensional Drawings 4 Product Certifications 2 A Data Sheet Power on Self Test Power on Self Test
80. s out INVESTICE DO ROZVOJE VZD L V N Specify the size or depth of the RT host part of the FIFO Configure Method Host computer DMA FIFO size 2 X FPGA DMA FIFO size if unconfigured Consider longest delay and configure sizes large enough so they do not fill INVESTICE DO ROZVOJE VZD L V N e If the FIFO number of elements is too small and FIFO fills Acquire slower ncrease number of elements to read on host Increase FIFO host buffer sizes INVESTICE DO ROZVOJE VZD L V N e FIFO number of elements is too large Other functions on the FPGA cannot use the memory Other functions on the host cannot use the memory INVESTICE DO ROZVOJE VZD L V N Drag FIFO from Project Explorer window Project Explorer Fan Speed Control lv PI x M Untitled 1 vi Block Diagram on Fan File Edit View Project Operate Tools Window Meo m Hi File Edit View Project Operate Tools Window Help Poea xDox eH m Fal 8 ii Project Fan Speed Control lvproj amp E My Computer ki Dependencies Build Specifications 3 5 cRIO 9012 10 0 36 43 tH GJ SubWIs Local Chassis cRIO 9103 i
81. s possible to preserve space on FPGA Functions EJ Programming L FPGA Math amp Analysis INVESTICE DO ROZVOJE VZDEL VAN By Modi Too FPGA I O items connect I O to the FPGA logic Each FPGA I O item has a type like analog or digital FPGA VIs can have multiple types of I O items INVESTICE DO ROZVOJE VZD L V N FPGA I O terms Terminal a hardware connection on a CompactRIO module Channel a logical representation in LabVIEW FPGA of a terminal Alias a name assigned by the developer to a particular channel INVESTICE DO ROZVOJE VZD L V N Madi DIO Digital I O mm Individual Lines Boolean data type Ports collection of 8 lines U8 data type 1 bit per line e Digital I O can write or read Disable with I O Method Node before switching between and O INVESTICE DO ROZVOJE VZD L V N Analog I O Data Type 132 Al Converts binary representation of the voltage to a signed integer e AO Writes the binary representation of the voltage to the D A converter INVESTICE DO ROZVOJE VZD L V N e Error
82. se AO1 AOZ i WX AOS ew endende i Build Specifications INVESTICE DO ROZVOJE VZD L V N Eek n il JE Lekcia 4 SCAN MODE SN MANIA D T INVESTICE DO ROZVOJE VZD L V N e What is CompactRIO Scan Mode Using CompactRIO Scan Mode NI Distributed System Manager Programming with CompactRIO Scan Mode INVESTICE DO ROZVOJE VZD L V N Enables access to I O modules directly in LabVIEW Real Time and host applications without FPGA programming Powered by two technologies RIO Scan Interface RSI NI Scan Engine INVESTICE DO ROZVOJE VZD L V N Uses Allows you to get an application up and running quickly Applications with synchronous I O updates at rates up to 1 kHz Add counter PWM or quadrature encoder functionality to any eight channel digital C Series module INVESTICE DO ROZVOJE VZD L V N Reguirements Controller e VxWorks Real Time Operating System 2M gate FPGA Examples NI 9012 9014 9073 9074 Not supported Pharlap controllers NI 9002 9004 Supported backplanes Examples 9103 9104 9073 9074
83. ted Running EVROPSK UNIE luf e f you do not see the chassis under devices and interfaces Check the hardware connections Refresh the Configuration tree F5 INVESTICE DO ROZVOJE VZD L V N 3 Software Measurement tt Automation Explorer m ole File Edit View Tools Help Configuration sl Add Remove Software 29 Show Help a My System s Data Neighborhood E a Devices and Interfaces a Softwa re S Historical Data 44 Scales E Software l 11 Drivers a Remote Systems What is Software Software displays the National Instruments software components installed on a LabVIEW Real Time target E ER b RR RH What do you want to do View my software information s Install software M D 9 515 For more information about using your NI products refer to your product specific help located on the Help Help Topics menu item You can also access NI product help from within MAX help which you can launch from the Help menu or by pressing F12 Submit feedback on this topic z INVESTICE DO ROZVOJE VZDELAVANI EVROPSK UNIE lu Default is to install minimal software necessary Good for simple TII a p p C ad t O n S at software set you want to install to the target National
84. tes on the FPGA to provide the fastest performance Recommended only for very small FIFOs 100 bytes e Look up Tables Store data in look up tables available on the FPGA 2 per slice Recommended only for small FIFOs 300 bytes Allocate the FIFO in user block memory to preserve FPGA space for your VI e 80 kB on a 1M gate FPGA e 192 kB on a 3M gate FPGA INVESTICE DO ROZVOJE VZD L V N Number of Elements Number of elements FIFO can hold Maximum depends on the Implementation that has been selected and the amount of space available on the FPGA for the implementation INVESTICE DO ROZVOJE VZD L V N File Edit View Project Operate Tools Window Help plej enr eee 11 Functions Programming gt ba Structures fal gt o Timing mr ER FPGA Math amp Addons Favorites Select a VI PGA I O Gg dik Synchronization Memory amp FIFO Advanced VI Scoped FI FIFO Write FIFO Read FIFO Clear INVESTICE DO ROZVOJE VZD L V N Put data into the FIFO with the FIFO Write function Retrieve data with the FIFO Read function File Edit View Project Operate Tools Window Help wr uu Prog
85. than 1 kHz Custom hardware analysis is required Hardware based signal processing is required O modules used are not supported by scan mode e g DSA modules Need to offload processing from the real time controller INVESTICE DO ROZVOJE VZDEL VAN Performance tradeoffs of using scan mode instead of FPGA Specialty digital functionality in scan mode only supports up to 1 MHz counters vs the 20 MHz counters achievable on FPGA NI Scan Engine uses system resources FPGA space requirements Minimum of two DMA channels needed e System memory resources used CPU time scales with the scan period INVESTICE DO ROZVOJE VZDEL VAN Lekcia 6 REAL TIME CONTROLLER INVESTICE DO ROZVOJE VZD L V N A Introduction E Developing an RT Host VI B LabVIEW Real Time F Rebooting the CompactRIO Applications RT Controller e C Development Course E Reusing Code in Multiple Targets e D Deterministic Operating Systems E Timing Methods INVESTICE DO ROZVOJE VZD L V N CompactRIO System Reconfigurable FPGA Windows asas obc mrd Time Critical LabVIEW HostVI Ya Interface VI FPGA VI Enterprise LabVIEW for Windows LabVIEW Real Time LabVIEW FPGA
86. tput Most HW Nested loops Any that require more than a single clock cycle to execute Shared resources Arbitration Loop Timer Wait Combinatorial path length becomes critical May require combining optimizations INVESTICE DO ROZVOJE VZD L V N 7 licks 1 Tick 512 out of 5120 Slices 1096 454 out of 5120 Slices 8 INVESTICE DO ROZVOJE VZD L V N SCTL limited by propagation delays through the FPGA circuitry If total combinatorial path propagation takes longer than 1 clock cycle compile fails Try to reduce path as much as possible before using SCTL INVESTICE DO ROZVOJE VZD L V N
87. w To LabVIEW al Blank VI C amp Empty Project Real Time Project Getting Started with LabVIEW LabVIEW Fundamentals Guide to LabVIEW Documentation More LabVIEW Help Upgrading LabVIEW e Automatic Block Diagram Clean Up Browse Quick Drop Properties of Multiple Objects List of All New Features Web Resources Discussion Forums Training Courses LabVIEW Zone Examples FPGA Project A Find Examples INVESTICE DO ROZVOJE VZDELAVANI aooaa T r UNE Two programming modes available Scan Interface LabVIEW FPGA Interface Select the programming mode you want to start programming your selected system s with Programming Mode Scan Interface The Scan Interface enables you to use C Series modules directly from LabVIEW Real Time LabVIEW FPGA Interface The LabVIEW FPGA Interface enables you to use C Series modules from LabVIEW FPGA VIS Note Selecting LabVIEW FPGA Interface mode stops any Scan Interface mode applications running on the system s INMESTICE DOVROZVOIE VZDEL VAN ki n il JE File Edit View Project Operate Tools Window Help FP G A IS h an dl e d mms res PEDES behind the scenes k Project Temperature Monitor Ivproj E My Computer SP Dependencies i x Build Specifications 5 fii RI0 9012 10 0 0 3 M1 Chassis cRI
88. xecutes too slowly 12 clock cycles 1 2 34 5 6 7 8 9 10 1112 LA iso DIOD F 29 0 2012 tidie HU ae k Or NOV INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE bu t e Pipelining Shorten the longest path 9 clock cycles Fositior M F S 051 r i we 4 FFs F INVESTICE DO ROZVOJE VZDEL VAN Pipelining 2 3 4 56 Watch out for pipeline FF ddsseadsenadkedudaandeensteua Gasseanan i effects including FFs ms increased latenc B iE y M j 7 boa gt rie 6 clock cycles US pes P FFs FFs INVESTICE DO ROZVOJE VZD L V N 2946 2012 But can we go faster 283 o o PROM ONO Single Cycle Timed Loop SCTL Can use a Single Cycle Timed Loop to turn this 12 clock cycle While Loop INVESTICE DO ROZVOJE VZD L V N EVROPSK UNIE bu t B o 4 B Do 4 F W TTE INVESTICE DO ROZVOJE VZD L V N Loop contents execute in a single clock period Some VIs and functions cannot be used in the loop at all Analog input analog ou
89. y lit The flash memory card is corrupt Reformat the hard drive on the controller Refer to MAX Help KINE SSL CENE ROZVOJE VZDEL VAN Lekcia 2 KONFIGUR CIA ZARIADENIA INVESTICE DO ROZVOJE VZD L V N e e Detect the Remote Target Configure Network Settings View Devices and Interfaces e Add Remove Software INVESTICE DO ROZVOJE VZD L V N nstall NI RIO software from the shipping CD Connect CompactRIO to PC with crossover Ethernet cable or to a network Power up CompactRIO Not configured CompactRIO Status light blinks slowly Open MAX Start Programs National Instruments Remote Systems in MAX Devices connected over the Ethernet INVESTICE DO ROZVOJE VZD L V N File Edit View Tools Help Configuration l Reboot 9 Lock K Refresh Apply 2 Show Help a My System sl Data Neighborhood Identification IP Settings ap Devices and Interfaces Model cRIO S3012 Obtain an IP address automatically Historical Data Serial Number 01354EF3 o Te VA Ais 44 Scales 5 Software MAC Address 00 80 21 11 14 67 To Default Name cRIO 9012 System State Connected Running IP Add
90. z vien TH gt Programming v Measurement I O L NI Scan Engine L Forcing EEE E3 Functions pre b Programming w Measurement IO a L NI Scan Engine L Faults e Synchronization of LabVIEW Code to NI Scan Engine Two methods e Synchronize to Scan Engine vi e Synchronize Timed Structure to the scan engine Use the Synchronize to Scan Engine timing source INVESTICE DO ROZVOJE VZD L V N Lekcia 5 PR CA S PROGRAMOVATELN M HRADLOVYM POLOM INVESTICE DO ROZVOJE VZD L V N A Introduction B Fixed Point Math C Defining FPGA Logic with LabVIEW D Developing the FPGA VI E Testing with the Development Machine E Interactive Front Panel Communication F Wiring the Modules G Compiling the FPGA VI H Downloading to Flash Memory I Using LabVIEW FPGA with CompactRIO Scan Mode INVESTICE DO ROZVOJE VZD L V N e An FPGA is a chip that can be reconfigured with software e FPGAs are used in NI R Series DAQ Compact Vision and CompactRIO e An FPGA replaces millions of logic gates INVESTICE DO ROZVOJE VZD L V N CONFIGURABLE LOGIC BLOCK CLB FPGA Layout an

D. Developing the FPGA VI

Contents

Download Pdf Manuals

Related Search

Related Contents