TTC/TTS Tester (TTT) Module User Manual
Contents
1. 2 36 005 08 00 30 F3 00 05 192 168 2 36 006 08 00 30 F3 00 06 192 168 2 38 007 08 00 30 F3 00 07 192 168 2 39 008 08 00 30 F3 00 08 192 168 2 40 009 08 00 30 F3 00 09 192 168 2 41 010 08 00 30 F3 00 0a 192 168 2 42 Table 2 IP and MAC Addresses both volatile program to FPGA and non volatile program to SPI Flash programming using the provided bit and mes files 3 9 Legacy TTS LVDS RJ 45 In the default mode set by writing 0x0 to bits 8 to 11 in the TTTControlReg address 0x2 register the LVDS channels act as follows e The Channel A and Channel B Tx LVDS RJ 45 connectors echo the TTS state being received the Channel A and B fibers e All LVDS Rx channels are turned off In legacy mode set by writing 0x1 to bits 8 to 11 in the TTTControlReg Address 0x2 register the channels act as follows e The Channel A Rx LVDS connector receives the TTS state Fiber TTS messages are ignored e Channel A Tx continues to output the fiber TTS states as in default mode 3 10 Error Counters Internal error counters are present for the Channel A and B fiber broadcast errors and Ethernet frame errors The addresses can be seen in Table 3 CHxFiberErrors_SingleBit shows single bit errors which have been corrected with the hamming code and CHxFiberErrors MultiBit shows multi bit and frame errors which were uncorrectable The EthFrameErrors 0x7 register shows ethernet frame errors which in2. 5 LHC Clock Input This input provides the option to substitute an external clock for the on board 40 079 MHz crystal It must be selected by writing a 1 to bit 2 of register 0x2 TTTControlReg 3 6 Optical Fiber Transceivers Two SFP cages are provided for optical fiber transceivers For compatibility wit the TTC system it is recommended to use SFP transcievers compatible with the ATM network protocol 3 6 1 TTC Protocol The SFP transceivers process biphase mark encoded bit streams using the protocol specified for the CERN TTC system The biphase mark encoding scheme is illustrated in Figure 5 Two bits called channels A B are transmitted each clock cycle Channel A indicates that an L1A is present while channel B is used to carry serial data as detailed in Figure 6 Channel B sends 1 s continuously when idle with a 1 0 transition representing the start of a frame Various types of frames are documented for the TTC system but the only type used by this board is the Broadcast Command frame An 8 bit command is transmitted with the values of the bits shown in Fig 6 lt 24 9501ns gt A Channel B Channel 0 Unlimited string length when idle String length gt 10 illegal switch phase Figure 5 TTC Low Level Encoding 3 6 2 SFP Transmitter The transmitters simulate the output of the TTC system The A channel is used to carry L1A generated internally or received from the NIMO input The B chan
3. generated periodically or at pseudo random intervals BCO with correct spacing every 3563 clocks CMS trigger rules observed programmable TTS buffer status respected e Receive and process TTS status from AMC13 on optical fiber Use to modulate trigger rate for internally generated L1A Translate to legacy TTS FMM output on RJ 45 connector JTAG connector 5V power in Jumpers center NIM Inputs a MU Out In Out In TTC TTS LEDs New A B External clock in L1A out NIM BCO out NIM TTS Interface Fiber to Legacy AMC13 Ethernet 10 100 Figure 1 Board Overview with Connectors Illustration 1 shows an overview of the board with connectors and controls Detailed information is in the Hardware Description section 2 Quick Start Guide Connect a 5V power supply to the power connector J9 Use the supplied wall transformer or make your own cable center terminal is positive The board should provide the following functions without any software intervention e The BCO nim output should provide a 75ns three clock cycles wide pulse at the LHC orbit frequency e Both TTC fiber outputs transmitter on SFP should provide a valid TTC bit stream with BCO encoded every 88us e The TTS state received from the AMC13 on the SFP receivers should be output as LVDS on the RJ 45 outputs e The NIMO input should generate a L1A on both TTC outputs when a falling edge is seen In order to
4. over an 100Mb Full Duplex ethernet connection All ethernet transactions are handled by the IPBus v1 3 Firmware Core For more information on software configuration please see the Software Configuration section I P addresses are set by jumper on the PC board as shown in Table 2 For reference on how the jumpers are set up see the section Jumpers Setting the Serial Number In addition to being used by the software to configure the TTT the ethernet can be used to write to the flash on the TTT Writing to the flash over IPBus allows for firmware updates to be carried out without a JTAG programming device Information on how to do this is available in the Software Configuration section This is only valid for non volatile programming and the old software version will be overwritten 3 8 JTAG Port A JTAG at site J1 is provided as a standard 1 inch header The signal names are marked TMS TDI etc on the TTT board This particular JTAG pinout is meant for use with the Digilent HS 1 JTAG programmer for Xilinx chips However another JTAG programmer which is compatible with the Xilinx ISE software or known to be compatible with Xilinx 6 series chips may also work but will receive no user support This port can be used for Serial Number MAC Address IP Address 000 08 00 30 F3 00 00 192 167 2 32 001 08 00 30 F3 00 01 192 168 2 33 002 08 00 30 F3 00 02 192 168 2 34 003 08 00 30 F3 00 03 192 168 2 35 004 08 00 30 F3 00 04 192 168
5. 03c0 0x00000400 Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff 0x00000001 0x00000002 0x00000004 0x00000008 0x00000010 Oxffffffff 0x00000001 0x00000002 Oxffffffff 0x00000001 0x00000002 0x00000004 0x00000008 0x00000080 10 R W R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 3 continued from previous page Description 32 bit counter for Ethernet frame errors 3563 delay to first trigger BX per orbit nom number of orbits with triggers spacing of LiA within orbit number of LiA per orbit time between repeats in orbits Select byte to read Fifo data Fifo Word Count Trigger Count Counter Mux Select coutner to read 0 3 Rule violation 1 4 random threshold no more than 1 trig N Bx no more than 2 trig N Bx no more than 3 trig N Bx no more than 4 trig N Bx select orbit signal clock phase delay responding to BSY OFW sample TTS when n and BcN NIM TTS output at this BcN NIM TTS prescale not impl yet Control Register enable burst gt 1 trigger per orbit enable repeats enable back pressure enable random triggers disable blankking of L1A in orbit gap Status Register Fifo Empty Fifo Full Action Register bit O LiA enable bit 1 adva
6. 0x00000001 Oxffffffff Oxffffffff 0x00000004 0x00000008 0x000000f0 0x00000f00 0x80000000 Oxffffffff 0x00000002 0x20000000 Oxffffffff Oxffffffff Ox0000ffff Oxffff0000 Oxffffffff Ox0000ffff Oxffff0000 R W WI V W R W R W R W R W R W R W R W R W R W R W Description Format YYYYMMDD where Ylear M onth and Dlay Firmware Version ID same as VERSION maintains backwards compatibility Ox1 read write Read to get Memory Read Fifo Empty Status Flash Busy Flash command register Control Reg Write to 1 to change clock source to LHC Clock Write to 1 to disable BCO s on all output streams Sets NIM modes the controls are as follow write 1 to bit O to switch to receiver mode Sets LVDS modes WRite to 0x1 to have TTS State come from the Channel A LVDS port Triggers rst_n in the firmware which causes a full reset Action Register Write 1 to send Bcast Command auto resets to 0 Write to 1 to reset error counters auto resets to 0 Load Broadcast command into the lower 8 bits the remaining bits do not matter Send using TTTActionReg bit 1 Counts single and multi bit errors on the Channel A fibers broadcast commands Counts single bit errors on the Channel A fiber Counts multi bit errors on the Channel A fiber Counts single and multi bit errors on the Channel B fi
7. TTC TTS Tester TTT Module User Manual Eric Hazen hazen bu edu Christopher Woodall cwoodall bu edu Charlie Hill chill90 bu edu June 3 2013 Contents 1 Overview 2 Quick Start Guide 3 Hardware Description 3 1 Jumpers Setting the Serial Number ee ee ee 3 2 LED Arrangement sche acon a Aa Wy Spe ae a A ee ee a dd 3 3 NIM Outputs ses bd a So Sok eae ee Raw eS eld Ree eho ae BA 3A NIM Inputs 04 5 0 ve A eA GR EP ae ee A a ae 3 9 LHC Glock Input ad aye in Gekko a PE a teats Gd A ENS 3 6 Optical Fiber lransceivers 2 0000 a a Be OR Sb ee ee ea ba ed A 30 17 TEC Protocol cs Aca elt babe PED ee ee ee aes Ge eR eee eee ee hed 3 6 2 OEP Transmitter 02 4 Soh A A Rok AA a So Bee Be PO BOA eaa Y 3 0 3 SEP Receiver volvia ee ed ae hee EOD OE Rhee RRS 3 1 Ethernet Interface xs a a Son ooh Boles Be ele ES Se be ye ew ob 38 JT AG POT oe ak osc Seth a Be Ace BO Gow oe a al a one Bo be Qo ee ee Y 3 9 Legacy TTS LVDS RJ 45 2 aea 3 10 Error Counters bona wee a E ee ae Aa ee ee SD EA ee a ie ee ee ee 4 Software Configuration 5 IPBus Registers 1 Overview This document describes a module developed at Boston University for use in CMS test stands especially those based on MicroTCA using the AMC13 module for clock trigger DAQ functions The TTC TTS Tester Module TTT performs the following functions e Generate simulated TTC signals on two optical fiber outputs with LIA
8. bers broadcast commands Counts single bit errors on the Channel B fiber Counts multi bit errors on the Channel B fiber Continued on next page Name EthFrameErrors TTSOrbitLength TTSTrigStart TTSOrbitMax TTSL1ASpacing TTSL1APer0rbit TTSRepeatPeriod TTISFifoByte TTSFifoByte_FifoData TISFifoByte_FifoWordCnt TTSFifoByte_TriggerCnt TTISFifoByte_CounterMux TTSCounterByte TTSRateSet TTSRulei TTSRule2 TTSRule3 TTSRule4 TTSC1kSel TTSSetBPDelay TTSBPSampleMask TISTTCBxNum TISTTCCmdPrescale TTSControlReg TTSControlReg_enBurt TTSControlReg_enRepeats TTSControlReg_enBP TTSControlReg_enRandTrig TTSControlReg disableBlanking TISStatusReg TISStatusReg FifoEmpty TTSStatusReg FifoFull TTSActionReg TTSActionReg_LiAen TTSActionReg_advanceFifo TTSActionReg captureTrigCnt TTSActionReg genNewRand TTSActionReg_ RST Address 0x00000007 0x00000100 0x00000101 0x00000102 0x00000103 0x00000104 0x00000105 0x00000106 0x00000106 0x00000106 0x00000106 0x00000106 0x00000107 0x00000108 0x00000109 0x0000010a 0x0000010b 0x0000010c 0x0000010d 0x0000010e 0x0000010f 0x00000110 0x00000111 0x00000112 0x00000112 0x00000112 0x00000112 0x00000112 0x00000112 0x00000113 0x00000113 0x00000113 0x00000114 0x00000114 0x00000114 0x00000114 0x00000114 0x00000114 Bit Mask Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Oxffffffff Ox0000000f 0x00000030 0x0000
9. cludes CRC mismatches and general ethernet frame problems The error counters can be reset by writing 1 to bit 29 in TTTActionReg 4 Software Configuration For now please referenc Charlie Hill s TTT software documentation A software quickstart guide is coming As of now the supported release will by based on PyChips not HAL due to problems with the 100Mb s TTT ethernet connection 5 IPBus Registers Table 3 documents all of the registers in the TTT and a basic description some registers have further documentation sections when required Name VERSION FirmwareVersionID STATUS FLASH MemoryRead FLASH_FIFOempty FLASH_BUSY FLASH_CMD TTTControlReg TTTControlReg_ClkSel TTTControlReg DisableBCO TTTControlReg NimModes TTTControlReg_NimModes TTTControlReg Reset TTTActionReg TTTActionReg SendBcastCmd TTTActionReg ErrCntRst TTTBcastCmd CHAFiberErrors CHAFiberErrors_SingleBit CHAFiberErrors MultiBit CHBFiberErrors CHBFiberErrors_SingleBit CHBFiberErrors MultiBit Table 3 Address 0x00000000 0x00000000 0x00000001 0x00000001 0x00000001 0x00000001 0x00000001 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000003 0x00000003 0x00000003 0x00000004 0x00000005 0x00000005 0x00000005 0x00000006 0x00000006 0x00000006 TTT Register Table Bit Mask Oxffffffff Oxffffffff Oxffffffff 0x00000004 0x00000002
10. he DCM is locked and reliable operation can be expected e R1 indicates that power is being applied to the board e G0 3 indicate the Serial Number IP and MAC address that is currently set e G4 7 indicate the current TTS state being sent to the Ch A Fiber LED Functions inside of the VERIFY firmware are described in the TTT Hardware Verification Procedure section of this document 3 3 NIM Outputs The NIM outputs can be seen in Figure 1 and are labeled as BCO J5 LIA J4 NIMO J18 aux BCO and NIM1 J19 aux L1A Modes for NIM outputs can be selected using TTTControlRegister bits 4 to 7 In the default mode TTTControlRegisters 7 4 0x2 set to 0x0 e J5 will output BCO generated internally on the TTT e J4 will output the L1As being generated by the TTT as setup by the software see the Software Configuration Section In the receiver mode TTTControlRegisters 7 4 0x2 set to 0x1 e J5 and J4 will output the BC0s and L1As received on Fiber Channel A e J18 and J19 will output the BCOs and L1As received on Fiber Channel B 3 4 NIM Inputs The NIM inputs can be seen in Figure 1 and are labeled NIM_INO J20 NIM_IN1 J21 NIM_IN2 J22 and NIM_IN3 J23 The default mode only utilizes NIM_INO which looks for falling edges and generates a single L1A Currently no other features or configurations are available for the NIM Inputs but a configuration register has been made available for future modes TTTNimInConfig 3
11. nce TTS FIFO to next word bit 2 capture trigger count for readout bit 3 generate new random number Dit V Teet Continued on next page Name TTSDataReg FLASH_WBUF FLASH_RBUF Table 3 continued from previous page Address 0x00000115 0x00001000 0x00001080 Bit Mask Oxffffffff Oxffffffff Oxffffffff 11 R W R R W R W Description Where data selected by TTSFifoByte is presented Write flash Read flash
12. nel sends broadcast commands such as those shown in Table 1 BCR BCO is sent every orbit 3563 clocks Other broadcast commands may be sent under software control Typically to start a data collection run on a test stand the sequence OCR ECR would be sent with L1A disabled before the start of data taking General Frame Idle Start Stop Broadcast Command Data L BcN Reset EvN Reset CMD Data 0 CMD Data 1 CMD Data 2 CMD Data 3 Test CMD O Test CMD 1 Figure 6 TTC Frame and Broadcast Command Format Value Acronym Name 00101000 0x28 OCR Orbit Count Reset 00000010 0x02 ECR Event Count Reset 00000001 0x01 BCR a k a BCO Bunch Count Reset Table 1 TTC Broadcast Commands Send Processed by TTT 3 6 3 SFP Receiver The SFP Receiver receives a bitstream from the AMC13 module which carries TTS and local trigger information The TTC protocol is currently used A broadcast command is sent periodically by the AMC13 in which the upper 4 bits represent the current TTS state Channel A is used for local L1A generated in the AMC13 The TTS state is output to the corresponding RJ 45 connector and also used to modify the operation of the internal L1A generator If the TTS signals represent any state other than Ready the L1A will be halted until the state returns to Ready 3 7 Ethernet Interface The ethernet interface seen in Figure 1 can be used to comunicate between the TTT board and a computer
13. use the board in receiver mode where the Channel A and Channel B SFP connectors output BCO0 s and take the received messages and output the L1A s and BCO0 s on the associated NIM outputs you need to write 0x10 to the TTTControlReg Address 0x2 Please refer to Figure 1 for location More detailed information can be found in the section NIM Outputs 3 Hardware Description Figure 2 is a basic interface diagram nmo OH nmi OH nm2 OH nms OH NIM L1A out NIM BCO out Spare NIM 2 out Spare NIM 3 out Ext CLK o4 CA LVDS RJ45 AA E Flash 10 100 Ethernet Figure 2 TT T Block Diagram with all connectors noted 3 1 Jumpers Setting the Serial Number The TTT board provides 4 GPIO pins on J14 surrounded by 3 3V J3 and GND J17 These 4 GPIO pins go to pins P35 P32 P30 and P39 on the Spartan 6 and are used to set the serial number Each board is assigned and shipped with a serial number in a 4 bit number space where each bit of the serial number corresponds to one jumper as indicated in Figure 3 The jumper setting of 0 is reserved for verification mode gt Q 3 amp 2 SN 0 SN 1 SN 2 SN 3 To Buttons Figure 3 Configuration for Settings Jumpers 3 2 LED Arrangement Figure 4 shows the LED arrangement on the front of the TTT In the default power on mode of operation the LEDs indicate the following Figure 4 LED Arrangement and Association e When RO is solid t
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