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1. In other words it qoute be useful to have some programable gain amplifiers The programable amplifiers should acer all the specifications of the tada wura AD except that the gain would be controlled by the computer rather than by resistors suggested method of achieving MEETS gain amplifier using an op amp and a set of analog switches is shown in Figure 3 2 This amplifier a standard D A converter op amp acts as a summer and the transfer function can be expressed as Vout Rg bg 2by 4b2 2 bq Vin Ry where the b s are binary digits 1 or 0 above equation shows that the gain of the amplifier is directly proportional to the binary weighted sum of a set of binary digits or in other words a binary number The maximum gain is V R Vin T Ry The values of Rg and determine the value of the maximum gain programably loaded register 38 In the actual realization of the programable amplifier of Figure 3 1 it would be desirable to have the outputs of the analog switches buffered This is because the internal resistance of the analog switches could mak the selection of the resistor values difficult or impossible Doing this would aiso raise the input impedence of the programable amplifier If quad op amp chips were used such LM325 s very few chips wouid be added to the circuit Eight bits of resol tion would meet the requirements f2. THE SECOND FILE IS FOR CHANNEL 14 BYTE 15 12 ASCII THE THIRD FILE 15 FOR ASCII CHANNEL 10 157127127200 MSG43 15 12 ASCII ON THE ANALOG COMPUTER HITZ 4 ASUII RESET THE VALUES BYTE 15 12 SETTLE IN AND HIT BBC LL NEXT INPUT A LINEFEED TO BYTE 15 12 START THE SOLUTION BYTE 157127127200 MSGS ASCII THE SOLUTION HAS BEEN ASCII BY FROGRAM CONTROL OR DUE TO BYTE 15 12 ASCII OVER RANGE INTERRUPT BYTE 12 15 ASCII THE END VALUES OF ALL AMFLIF IERS ARE STORED IN THE BYTE 15 12 ASCII OUTFUT FILE ASSIGNED TO CHANNEL 10 BYTE 15 12 12 200 80 EVEN MSG6 ASCII THE TEST VOLTAGE HAS BEEN 5 TO RESTART THE Z 13712 ASCII SOLUTION INPUT Y 7 BYTE 195 132 ASCII TO STOP THE SOLUTION HIT ZANY OTHER 15 12 12 200 EVEN START 10 11 12 13 14 REFERENCES Peterson Gerald R Basic Analog Computation New York N Y The Macmillan Conpsuys 1967 Hyndman D E Analog and Hybrid Computing New York N Y Pergamon Press 1970 Kochenburger Ralph J Computer Simulation of Dynamic Systems Englewood Cliffs N J Prentice Hall Inc 1972 Geral
3. NTR23 170402 2 MOV 4 4 ASL R2 SUB R1 R2 BGT GRTH NEG R2 PRINT FRIGHT FSFACE RETRN ORTH SFACE ROL R2 ROL R2 ROL R2 ROL R2 LOOPS ROL R2 ROL R2 ROL R2 ROL R2 MOV R2 R3 ROR R2 50 A D VECTOR CHANGE A D CHANNEL FALL CHANNELS TESTED RESTART IF DONE START CONVERSION WAIT FOR INTERRUFT NEXT CHANNEL IN VOLTAGE GETS INPUT SALT 4000 TO R1 TO INTERRUFT ROUTINE TO CHECK CHANNELS 11 15 QUTPUT CALIBRATING INSTRUCTIONS 2 GETS A I INPUT sLOAD 4 INTO RLB SUBTRACT Ri FROM R2 IF POSITIVE NEGATE R2 THE WORE RIGHT THE PRINTER BRANCH TO SPRINT THE WORD LEFT SON THE R2 FOUR TIMES IN ORDER SET IT TG BE AS ASCII CHARACTERS lt gt Cab R2 TO RS R2 HEAD LEFT RIGHT c SPACE RICE 370 3 BISE 460 gt 7R3 RS 4 ER LOOFS SPACE BITE 1393212 88012 HIT EVEN ASCII ASCIZ 15 EVEN ASCII LER 200 EVEN 200 7 SEVEN START CHANNEL 11 CHANNEL 14 RIGHT 5L CHA NGE R3 T
4. MONTANA STATE UNIVERSITY Improving an analog computer by adding digital electronics and a digital computer interface by Robert Joseph Horning A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in Electrical Engineering Montana State University O Copyright by Robert Joseph Horning 1979 Abstract The following thesis discusses some possibilities of improving an analog computer by adding digital circuitry and an interface to a digital computer The thesis work involved modifying an Electronic Associates Inc TR 48 analog computer and interfacing it to a Digital Equipment Corporation PDP11 03 digital computer Hardware built as part of the thesis includes circuitry to detect when one of the amplifiers in the analog computer is about to go out of range circuitry which gives the digital computer the ability to input the output voltage of any amplifier and circuitry that allows the digital computer to stop and start the analog computer A real time clock was also built and added to the digital computer as part of the thesis work All of the hardware implemented is described in detail in the thesis The thesis also describes an example problem that demonstrates the capabilities of the implemented system The example problem shows that an analog computer can be greatly improved by adding digital circuitry and a digital computer interface The thesis discusses some additional hardware that could be
5. BDR12H13 BDR7H BDR6H BDR5H BDR4H Figure B 2c Real Time Clock Schematics 61 SELC A C 512 Vector R NV 4 5 c7 ET 13 9 07 pll v rie 4 9 BDINH SELC B c7 13 ol 7 bli 4 DATAOB c8 DATAO Figure B 2d Real Time Clock Schematics 4 2 switch ys eal 5 36 7 DIP Figure B 2e TUE ROLE DIP 17 62 DIP 10 DIP 11 DIP 12 DIP 13 DIP 14 DIP 15 DIP 16 57478 5 1 9 clock 53 14 54 10 ss 2 mE G Real Time Clock Schematics APPENDIX C 64 Circuit Description and Schematics for Oyer Range Circuitry This appendix gives a description of the over range detection circuitry along with schematics See Section 2 7 for a description of how to use the The circuitry in Figure 1 is repeated three times The one shown monitors amplifiers through 15 The other two monitor 16 through 31 and 32 through 47 The LM324 s are used as buffers so that the amplifiers of the analog computer are not loaded The voltages are divided by two at this point nize One of the sixteen amplifiers ez a to a comparator through the use of 4016 analog switches Figure 1 shows how through SEL15 are selected of the Sixteen lines is selected by use of a 74154 4 to 6 line
6. FOR THE DATA TO BE QUTFUT gt gt gt 10000 44 561 CSIGEN DEVSFPC 0EFEXT y FO BIS 410000544 CLR R3 CLR BLOCK PEBUFFER IS THE ADDRESS OF THE BUFFER FOR 0 CHANNEL 15 THE BUFFER IS CLEARED BY THE USE OF AUTO INCREMENT MODE SOF ADDRESSING td BUFCLR RUFFER R1 E BLO CLRLP BUFFERyR1 73 U IS THE ADDRESS OF THE BUFFER FOR CHANNEL 10 IS CLEARED MOV CLRLP3 CLR R4 R4 tRUFEDS BLO CLRLFS 4BUF2 IS THE ADDRESS OF THE BUFFER FOR CHANNEL 14 IT IS CLEARED HERE MOV 2 CLRLP2 CLR CMF R4 TBUE E D2 BLO CLRLF2 BUF27R4 SET THE OVER RANGE INTERRUFT lt gt gt 2 300 100 302 SET THE A D STATUS REGISTER AND INTERRUPT VECTOR 7520 8 170400 FINTR 24400 100704402 THE REAL TIME CLOCK BUFFER AND WAIT SFOR A LINEFEED TO START THE SOLUTION 226 08 170422 504 START THE ANALOG COMPUTER BY FULSING THE RIT 74 gt 100000 08 167772 CLR 167772 START THE REAL TIME CLOCK ANI ENABLE THE SOVER RANGE CIRCUITRY 4 wp gt 4315804170420
7. 4 4 2 4 6 6 8 c 09 5 81 LIST OF TABLES Page Table 2 1 Real time clock status register bit assignment 15 Table 2 2 Over range test circuitry status register bit assignment 23 LIST OF FIGURES Page Figure 2 1 System Block Diagram 7 Figure 2 2 Locations of switches tabs and jumpers on the real time clock 0 8 er e eo eo roh om o9 on n 16 Figure 2 3 Setting address to the status register 2 18 Figure 2 4 Setting the interrupt vector for the status register 18 Figure 2 5 Block diagram of over range detection circuitry 22 Figure 2 6 5e7t represented in block diagram form and its analog computer realization sos e soe er os ooo 27 Figure 2 7 55 2 1 29 Figure 3 1 16 channel D A converter 34 Figure 3 2 Programable gain amplifier ee 37 Figure 3 3 Programable analog switches 39 Figure 1 Real time clock circuit layout s e e s s s e s e s o 57 Figure B 2 Real time clock schematics 58 Figure C 1 Over range detection circuitry schematics 66 ABSTRACT The following thesis discusses some possibilities of improving an analog computer by adding digital circuitry and an interface to a digi tal computer The thesis work involved modifying an Associates Inc TR 48 analog c
8. CALLED WHEN AN SOVER RANGE INTERRUPT OCCURS THE A D CONVERTER STATUS REGISTER IS CLEARED AND THE INTERRUFT FOR THE OVER RANGE CIRCUITRY IS 76 5 3 INTR2 CLR 170400 CLR 04147770 RTI THIS INTERRUPT ROUTINE IS CALLED WHEN THE SOLUTION IS BEING STOPPED AND AMPLIFIER S VOLTAGES ARE BEING REAL IN THE OVER RANGE MULTIPLEXER ADDRESS IS INCREMENTED ANI THE VALUE IN THE A D CONVERTER BUFFER IS STORED INTR3 INC 167772 MOV 24170402 RTI THIS INTERRUFT ROUTINE IS USED TO ACQUIRE IT ALSO CHECKS THE DATA FOR THE TEST VOLTAGE STOPS THE SOLUTION IF IT IS gt lt gt gt THE A D BUFFER IS READ TO THE TEST VOLTAGE IF IT IS LOUER BRANCH TO INTR 170402 2 2 0 5 BLE CNTUE HIGHER HALT THE ANALOG COMFUTER SAVE THE A D CONVERTER STATUS REGISTER CLEAR A D CONVERTER AND REAL TIME CLOCK STATUS REGISTERS 3 0 400 814167772 170400 5 CLR 24170400 CLR 8141170420 LOAD TEST WITH A HIGH VALUE SO THAT THE TEST 77 WILL NOT BE FOSITIVE AGAIN MOV 10000 TEST MSGS WAIT FOR A CHARACTER TO FROM THE CONSOLE PRINT 504 CLR 843177560 LOOF 04177560 BEL DDE READ IN THE CHARACTER COMPARE IT TO IF IT IS NOT BRANCH TO RETURN
9. MOV 100 0 167770 ow S WAIT FOR AN INTERRUPT FROM EITHER THE CONVERTER OR THE OVER RANGE CIRCUITRY WAIT WAIT y RIF THE FROGRAM IS TO STOF THE A D CONVERTER STATUS REGISTER WILL ZERO gt 170400 9 BNE WAIT THE SOLUTION IS TO BE STOFFED 5 NEW FREQUENCY THE TIMER ANI CHANGE THE A D INTERRUFT VECTOR 20 0 170420 TINTR3 03400 0840 BUF3 INTO R4 TO USE IN AUTO INCREMENT TO SAVE THE AMPLIFIER OUTPUTS 4 THE OVER RANGE CIRCUITRY MULTIPLEXER ADDRESS ZERO RESET REAL TIME CLOCK BUFFER SET A D STATUS REGISTER AND ENABLE THE REAL TIME CLOCK MOV 6007 167772 75 300 170422 MOV 5120 0 170400 INC 170420 WAIT FOR AN INTERRUFT FROM THE A O CONVERTER lt gt w WAIT23 WAIT TO SEE IF THE OUTPUTS OF ALL THE AMPLIFIERS HAVE BEEN STORED 3 660 0 167772 ENE WAIT2 SALL THE AMPLIFIER OUTFUTS HAVE BEEN STORED CLEAR THE A D CONVERTER AND REAL TIME CLOCK ISTATUS REGISTERS CLR 84170400 CLR 831170420 QUTFUT THE BUFFER CONTENTS TO DISK lt gt WRITW FAREA 0 s 400 BLOCK CLOSE 40 SWRITU 2 1 0 2 400 BLOCK CLOSE 1 AREAS 2 fRUFS 400 BLOCK CLOSE 2 565 TO MONITOR 3 THIS INTERRUFT ROUTINE IS
10. in Figure 2 7 Notice that the A D converter output had to be taken off a separate op amp buffer from the actual output This is be cause of the relatively low input impedences of channels 11 through 15 the divide by two channels See Section 2 4 for the explanation of why this is so When channels 11 through 15 are used they must not be put in parallel with or hooked to the output of one of the analog computer potentiometers After the problem was set up on the analog computer the program on the digital computer was run This program first asks the operator for the name of the two disk files in which the data from channels 14 and 15 are to be stored and the name of the file in which the outputs of the amplifiers are to be stored if there is an over range interrupt The operator is then instructed through the console terminal to put the analog computer in RESET mode let it settle and then put itin OPERATE mode When a linefeed character is input on the console the solution is started The digital computer samples each output every 03 seconds The samples are stored and checked to see if they are over eight volts When one is over eight volts the solution is stopped i e theanalog computer is put in HOLD mode and the operator is asked if the solution Should be continued If the response is positive the analog computer 18 put in OPERATE mode and the solution is continued 29 unit i 1 en channel 14 a block diagr
11. inputs are buffered through 8640 receiver chips The address is compared Figure B 2a to the address set in the DIP switches Figure B 2e 54 Next the CPU asserts BSYNKL address match occurs a flip flop is set If there is no match nothing is done and the timer board will not react to the assertions of the signals mentioned below Add ress bits AQ and Al are saved If the CPU is outputing data the BWBNL line is asserted at the same time that the BSYNKL line is asserted The CPU will then remove the data from the data address lines If the CPU is outputing data it loads the data on the data address lines and clears BWBNL if a word is being written leaves it set if a byte is being output Next the CPU will assert BDOUTL The timing board uses the BWBNL along with AQ and Al to decide which byte of which register is to be written into Figure B 2a The assertion of the BDOUTL line will cause the data to be loaded into the proper register and buta If data are to be input to the CPU the CPU will assert BDINL after clearing the address from the data address lines The right register is loaded through the use of the logic shown in Figure B 2d and 74153 multiplexer chips Figure B 2b The same chips multiplex the interrupt vector when it is to be output The multiplexers are only used on the lower byte because only one bit in the upper byte is used by the status register and none by the interrupt vector A separat
12. occupy the positions from 5 to 11 Bit 12 is used to load the multiplexer address buffer bit 13 enables the multiplexer and bit 14 loads the A D input buffer Notice that ali the inputs o the sample and holds are tied to gether and thus no analog signal multiplexing is necessary Some buffering might be needed on the multiplexer output if the sample inputs on the sample and hold circuits are not TTL compatible The D A input buffer could be eliminated by requiring that the multiplexer buffer be loaded first and the D A converter allowed to Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 34 bits 0 4 multiplexer buffer multiplexer load enable 16 samples signals analog output l6 sample and hold INIRE circuits oi 16 outputs Figure 3 1 16 channel D A converter 35 settle before the multiplexer enable bit was set However this would lead to programing inefficiencies and is not recommended The number of D A channels could be easily increased simply by adding more and holds and making the multiplexer larger With the ability to set the initial conditions on the analog com puter using the digital computer it becomes desirable to have the ability to put the autos computer in RESET mode using the digital computer This would give the digital computer the capability of load ing the initial condit
13. of boundary value differential equations using the shooting method could be solved automatically 2 4 There are many more ways in which a digital computer might enhance an analog computer but only the above will be discussed in this thesis The next chapter will describe the circuits that were actually built and the software that was written Chapter Three will describe the hardware and software that would have to be implemented in order to obtain ali the capabilities mentioned above Chapter II THE IMPLEMENTED SYSTEM 2 1 Introduction This chapter gives the description of all the designs that were actually implemented as part of the project first gives brief description of the two computers that were used in the project These are the Electronic Associates Inc TR 48 Analog Computer and the Digital Equipm nt Corporation s PDP11 03 Next the hardware that was added to the two computers is discussed This includes two boards that were purchased for the PDP11 03 and one that was designed and built by the author The two boards purchased were an analog to digital con verter and a 16 bit parallel I O board The custom board was a programable real time clock Equipment added to the TR 48 analog com puter includes an interface to the digital computer and circuitry to place the analog computer in the HOLD mode and then signal the digital emcee to take action when an amplifier is about to go out of range In the f
14. on disk and alert the operator to correct the problem The solution need not be started over because ie stored values can be used as initial conditions when the problem is re scaled However it must be remembered to also rescale the initial conditions The program that was written uses all the capabilities mentioned above it does tee Selye a practical problem on the analog computer but it does demonstrate how the equipment is deca The program only uses a few op amps of the analog computer Two simple functions are realized They are a d clining exponential and a rising exponential The declining exponential has a time constant of one second and initial condition of five volts The block diagram as used in feed back control theory for the function and vig analog computer wiring diagram are shown in Figure 2 6 See reference 8 for more informa tion on feedback control theory and reference 1 for nformation on the symbols used in analog computer wiring S The rising exponential was given a time constant of 75 seconds and an initial condition was chosen to be one volt These values were 27 5 1 u t A D Channel 15 a block diagram form channel 15 computer wiring diagram 2 6 5 represented in block diagram form and computer realization 28 chosen so that the integrator would go out of range after about three seconds The block diagram and the analog computer wiring diagram are given
15. re quest is granted the device sends to the processor a vector address that points to the location in memory of the interrupt servicing routine thus eliminating the need for device polling on the occurrence of an interrupt PDP11 03 uses a software stack to store return addresses for interrupt routines and subroutine calls This makes it quite simple to write transparent interrupt routines and subroutines which will automatically sequence correctly 2 4 ADV11 A Analog to Digital Converter In order to monitor the solution to a probiem on the analog compu ter the digital computer must be provided with an analog to digital to D converter was decided that the ADVII A to D converter 10 built by Digital Equipment Corporation was adequate for the job The ADVI1 A is a 12 bit converter and uses a successive approximation tech nique to make the conversion multiplexes sixteen single ended or eight quasi differential analog channels The to D converter can operate in single ended mode or quasi differential mode It is not true differential in that it does the A to D conversion on one line and then does the to D conversion on the other line and takes the difference The single ended mode was selected because the computers are in close proximity one another so that the noise picked up in the cable would be negligible compared to the noise picked up in the patch board The currents in the
16. E FROGRAM C ON THE ANALOG COMPUTER SET UF A DECAYING EXFONENTIAL ANI AN INCREASING EXPONENTIAL CONNECT THE OUTPUTS OF THESE FUNCTIONS STO CHANNELS 14 15 OF THE A D CONVERTER S CONNECT THE ANALOG OUTPUT OF THE OVER RANGE TEST CIRCUITRY TO CHANNEL 10 OF THE A D CONVERTER IRUN THE PROGRAM FOLLOW THE INSTRUCTIONS QUTFUT ON THE PRINTER THE FROGRAM FLOW LIII THE OUTFUT FILES FOR EACH OF THE THREE CHANNELS BEING USED ARE SET 256 SWORO BUFFERS FOR EACH CHANNEL ARE CLEARED THE INTERRUPT VECTORS FOR THE A D CONVERTER SAND THE OVER RANGE TEST CIRCUITRY ARE SET SUP C INTR ANI INTR2 THE SOLUTION IS STARTED VOLTAGES ARE READ ON CHANNELS 14 15 OF THE A T EVERY 03 SECONDS THESE VOLTAGES COMPARED TEST VOLTAGE S 44 VOLTS SIF THE TEST VOLTAGE IS EXCEEDED THE OPERATOR 315 ASKED IF THE SOLUTION IS TO CONTINUE SIF THE PROGRAM IS TO CONTINUE IT WILL RUN PUNTIL AN OVER RANGE INTERRUPT THIS TIME ALL THE AMPLIFIER VOLTAGES SARE REAL IN LASTLY THE THREE BUFFERS ARE OUTPUT TO DISK y OR RO XO R1 1 R2 2 R3 3 R4 4 RS 45 6 R7 47 MCALL CSIGEN URITUs EXIT CLOSE PRINT 2 se 3SET THE TEST VOLTAGE TO 5 44 AND HALT THE 00 COMPUTER H START amp 040 5 MOV 400 08 167772 THE FOLLOWING FOUR LINES SET UP THE FILES
17. If both the Auto Hold bit and the Auto Operate bit are set the analog computer will stay in HOLD mode Also if the Auto Operate bit is set while an op amp is over range the analog computer will stay in OPERATE mode and the overload circuitry will not generate an interrupt to the digital computer Normally when the Auto Operate bit is used to start the solution it will be set and immediately cleared It was decided that the Auto Operate bit would have priority over the vers range circuitry so that the user could by pass the over range circuitry if he desired There is also a manually switch on the front panel of the over range circuitry which will give control of the analog computer back to the user This switch te located on the front of the case of the over range detection circuitry The over range Re circuitry provides a link between the analog computer and the digital computer This interface can be used in any way desired but was meant to be used in the following way 25 The digital computer uses the console terminal to instruct the operator to put the analog computer in RESET mode Next the digital computer sets bit 8 of the control status register the Auto Hold bit This does not affect the mode of the analog computer because the HOLD mode is accomplished by disabling the OPERATE mode and thus Auto Hold only has effect when the analog computer is in OPERATE mode Next the operator is instructed to put
18. O ASCII CHARACTER OUTFUT CHARACTER SIF DONE RETURN 100 5 QUTFUT A SFACE RETURN TO PROGRAM THE LINEFEED KEY TO START TEST CHANNEL 12 CHANNEL CHANNEL 15 7 APPENDIX 53 Circuit Description and Schematics for the Real Time Clock This appendix describes how the PDP11 03 uses the bus signals to control the real time clock See Section 2 6 for information on how to use the real time clock In the schematics all inputs that start with a B and end with an L are inputs from the PDP11 03 bus All other labeled inputs can be found as outputs somewhere in the schematics Figure 1 shows the layout of the board Each chip is labeled to identify it The schematics of the board are given in Figures B 2a through B 2e All components are labeled with the chip so that their physical location can be located by use of Figure 1 The pin numbers of all inputs and outputs to components TN also labeled All resistor values are in kilo Ohms Power supply leads are not labeled These can be found by use of any TTL data book The circuits work in the following way The CPU will put the address on the data address lines BDAR through BDRI5 are shared as data and address lines and also assert line BBS7L if a device is being addressed All signals on the bus are ground true The data address lines are buffered through 8641 transceiver chips All other bus
19. OPERATE mode and the solution is generated At any time during the run of the program the computer may be put in HOLD mode this mode the solution is Stopped and conditions can be changed or observed and the problem restarted When an op amp goes out of its linear range on the analog com puter an indicator light goes on telling which amplifier is out of range The problem with this is that the light does not come on until the amplifier has been out of range for a few seconds and thus the problem must be restarted from the beginning When a digital computer is used to solve differential equations numerical methods are used to approximate the solution Methods such as Runge Kutta and Adams Molton when used with a small enough step Size can get very nearly exact solutions to differential equations 4 On the other hand an analog computer cannot be expected to have more than about one per cent accuracy 4 A digital computer also has the advantage of having a greater dynamic range One of the big advantages that a digital computer has over an analog computer is greater ease in programming and the problem Modern hybrid computers have alleviated this problem through the use of FORTRAN type programs that set up the through the digital portion and through the implementation of auto patching There are three main advantages to using an analog computer The first is that once the problem is set u
20. Pui SE is that these have the highest S and the real time clock should have a high priority since time is critical for good results If it is desired the regular power supply to power Fic rcl time clock the jumper should be removed from module pin 1 and installed between jumpers 1 and 2 For the locations of jumpers 1 and 2 see Figure 2 2 2 7 The Over Range Test Circuitry One of the main problems with an analog computer is that the op amps go out of linear range This problem is exacerbated because it is difficult to tell exactly when an amplifier goes out of range Conse quently when to a problem goes out of range the programmer must rescale the problem and start over from the beginning To allevi ate this problem circuitry was added to the analog computer to sense when any amplifier was about to go out of range When amplifier approaches an out of range condition the analog computer is automatical 20 ly put in HOLD mode and the digital commutes is signalled to take ac tion It is assumed that the digital computer will read the values of all amplifiers and pass the information to either the user or automatic rescaling routine The schematics for the over range detec tion circuitry are given in Appendix C along with a description of the circuitry description of how the circuitry operates and how it E programed is given here is obvious that multiplexing is necess
21. THE CONVERTER STATUS REGISTER HAS BEEN CLEARED THUS THE SOLUTION WILL 0 177562 5 MOV 100 02 177569 5 331 ENE RETURN 7 THE SOLUTION IS TO CONTINUE RESET THE A T STATUS REGISTER AND PULSE THE 6UTO BIT OF THE OVER RANGE CIRCUITRY TO RESTART THE SOLUTION THE REAL TIME CLOCK 15 ALSO RESTARTED MOV SAVE 170400 MOV 100000 08 167772 CLR 167772 MOV 317 170420 5 5 TO SEE WHAT CHANNEL THE DATA CAME FROM SIF FROM CHANNEL 15 BRANCH FIRST 5 CNTUE Z 170400 7520 BEQ FIRST CHANGE THE CHANNEL ANI STORE THE AZI CONVERTER BUFFER REGISTER IN THE BUFFER FOR CHANNEL 14 INCE 170401 2 4 RR RETURN CHANGE THE CHANNEL STORE THE A D CONVERTER BUFFER REGISTER IN THE BUFFER FOR CHANNEL 15 9 FIRST MOV 2 1 DECR 043170401 RETURN RTI BUFFERS T1000 BUFEND DEFEXT 0 BLOCK AREAS BUF21 2 2 2 BUF 31 BUFED3 DEFXS31 AREA31 79 SAVE 0 1 ASCII INPUT THE NAMES OF THE THREE 5 OUTFUT FILES IN THE FOLLOWING WAY BYTE 195212712 ASCII OUXLIFNAM1 2 ASCII 1 BYTE 1512712 THE FIRST FILE IS FOR ASCII CHANNEL 15 7 BYTE 15 12
22. added to the system It is concluded that giving the digital computer complete control of the analog computer would be unfeasible except for special purpose systems because of the tremendous amount of software that would have to be written on the digital computer STATEMENT OF PERMISSION TO COPY In presenting this thesis in partial fulfillment of the requirements for an advanced degree at Montana State University I agree that the Library shall make it freely B for inspection further agree that permission for extensive copying of this thesis for Renaat purposes may be granted by my major professor or in his absence by the Director of Libraries It is understood that any copying or publication of this thesis for financial gain shall not be allowed without my written permission Signature Date 2 Ha IMPROVING AN ANALOG COMPUTER BY ADDING DIGITAL ELECTRONICS AND A DIGITAL COMPUTER INTERFACE by ROBERT JOSEPH HORNING A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in Electrical Engineering Approved ate Committee 240 252 Head Major Department 24 Graduate MONTANA STATE UNIVERSITY Bozeman Montana June 1979 TABLE OF CONTENTS Page I INTRODUCTION i 1 1 Introduction S ne TIPP i 1 2 Comparison of tha Two Types of Mac
23. am form channel 14 75 b analog computer wiring diagram 2 Figure 2 7 72 30 When an op amp goes out of range because of the rising exponen tial the solution is stopped the values of all the op amps are stored and a message is set to the console At this point exponential curve fits were done on the input data The fits showed the input data to match the modeled exponentials quite well The highest error was within one half per cent of the expected value Chapter SUGGESTED ADDITIONS TO THE SYSTEM 3 1 Introduction The system s it now exists can digitally monitor the solution and automatically stop or start the solution What the system lacks in hardware is the capability of using the digital computer to affect the solution on a real time basis and the capability of digitally restart ing the problem with new initial conditions that were determined and set by the digital computer Section 3 2 will discuss hardware that can be implemented to give the system the capabilities mentioned above In order to completely exploit the system a large amount of soft ware must be written Section 3 3 will discuss some software goals that if met would give much of the work now done by the user to the digital computer 3 2 Suggested Hardware Additions The hardware needed to complete the system as discussed in the introduction of this chapter would probably cost about the same
24. ary in the design because there are sixteen channels on the A to D converter and forty eight op amps must be monitored Also it is desirable to have as many channels available as is possible for data acquisition Another con sideration is that the converter can only sample at about 30 KHz which diede that if it were desirable to check each amplifier at a frequency of 500 Hz the digital computer would have very little time to do anything else Three comparators were each multiplexed to sixteen op amps through a set of analog switches The analog switches were controlled by a 4 to 16 line decoder which was driven by a 4 bit loadable counter The circuitry can be run in two modes In the usual mode the up counter counts at a frequency of a little over 10 KHz This causes each op amp to be checked for over range condition at a rate of about 625Hz The sampling frequency was determined by the slew rate of the op amps driv ing the analog switches used for multiplexing an op amp is about to go out of range the analog computer will be put in HOLD mode auto 21 matically and the digital computer alerted In the other mode the digital computer will disable the 10 KHz clock and load a value into the counter This value selects which three ampli fiers are multiplexed into the comparators The inputs to each of the comparators are also multiplexed through a set of analog switches These three analog switches are controlle
25. buffer register was used to control the digital circuitry will be d scribod Section 2 7 For a more detailed deseription of the DRVIl board see wefevonce 6 2 6 The Real Time Clock In order to do data acquisition or real time control using a digital computer it is necessary to have samples accurately spaced Thus there was a need for a programable real time clock A clock could have been purchased from Digital Equipment Corporation but the only one available had more features than were and also took two siots on the PDP11 03 backplane where a custom board would take only one siot It was also decided that the real time clock would be more economical to build than to buy Since this board was built as part of this 14 thesis a detailed description of its use is given here Appendix has a detailed description of how the board is put together along with schematics for the board The real time clock has a buffer register and a status register The buffer register is loaded with a negative number in Bist complement form When the clock is enabled he buffer is loaded into a of counters The M frequency is determined by three bits of the status register When the counter overflows the overflow flag of the status register is set a pulse is E E EE tab this be used to start the A G and the buffer is loaded into the counters again If the interrupt enable bit is set
26. cable are very small compared to the currents in the patch wires The analog input range is between 5 12 volts and 5 12 volts The ADV11 A takes up two address locations on the PDP11 03 bus One location is a buffer that holds the results of the conversion The other location is a 16 bit status register which is used to control the converter and to monitor its status For a complete description of the status register see reference 6 Only the features of the status register used in the designs for this thesis are discussed below to D Start This is a bit that is set by program control and causes the ADVII A to start a conversion External Start Enable This bit is set by program control and allows an external signal to cause conversion to start The external signal must be provided to a tab on the 11 board and conversion 11 starts a high to low transition of this signal to D Done This bit is set by the ADV11 A when a conversion is done and the result is ready in the buffer When the buffer is read the D Done bit is automatically cleared Done Interrupt Enable This bit is set by program control and causes the 11 to generate an interrupt request when a convssofon is done i e when A to D Done is set Multiplexer Address This is a set of four bits set by program control that give the channel address on which the conversion is to be made to D Error This bit is s
27. d Curtis F Applied Numerical Analysis Reading Mass Addison Wesley Publishing Company 1973 1 5111 PDP11 03 Processor Handbook Maynard Mass Digital Equipment Corporation 1975 0 1 1 KWVLI A ADV11 A DRV11 User s Manual lst Sis Maynard Mass Digital Equipment Corporation 1976 Microcomputer Handbook Mass Digital Equipment Corporation 1976 _ D Azzo John J and Houpis Constantine H Linear Control System Analysis and Design Conventional and Modern New York N Y McGraw Hill Book Company 1975 Analog Switches and Their Applications Santa Clara Calif Siliconix Incorporated 1976 Recent IC Announcements Computer Magazine Los Angeles Calif Institute of Electrical and Electronics Engineers Volume 10 Number 12 December 1977 p 140 TR 48 Analog Computer Operators Manual Long Branch N J Electronic Associates Inc 1963 TR 48 Maintenance Manual Drawings Volume I Long Branch N J Electronic Associates 1964 TR 48 Maintenance Manual Long Branch N J Electronic Associates Inc 1964 11 System Reference Manual Maynard Mass Digital Equipment Gorporation 1976 STATE UNIVEI 0014358 5378 Horning Robert Josenh H783 Improving an analog 2 computer by adding digital electronics and digita cormuter interface
28. d by the digital computer The outputs of this multiplexer will normally be connected to one of the channels of the t D converter banana plug connector In summary this allows the digital computer to obtain the value of the output of any 55 amp block diagram of the analog multiplexer is shown in Figure 2 5 The of the digital computer from the checking circuitry was by the use of the DRV11 16 bit parallel input output board deaciibad fn Section 2 5 The buffer of the parallel board was used as a control status register for the overload checking circuitry The way this control status register is used is shown in Table 2 2 The use of the control status register must be clarified Using the multiplexer address along with the load bit permits access to the output of any op amp while the problem is running Howevet caution must be used when this is done because when the over range circuitry is in the load mode only the amplifier being observed is being checked for over range the counter is disabled Normally the load mode is only used when the analog computer is in HOLD mode Multiplexer 22 E Analog Output Analog Multiplexer p Analog Comparato 1 Comparator M Digital Analog Control Multiplexer Circuitry VEN an P Comp
29. demultiplexer The LM324 s in Figure are used as level converters In order to minimize leakage in the ana log switches they are switched at levels close to but not exceeding the power supply voltages The LM324 s convert the TTL levels to 14 for low and 14 for high Zener diodes are used to clamp this to about t7 volts The 74154 E has its inputs supplied by a 74193 loadable counter If bit 7 of the DRV11 parallel board is set the 74193 is loaded with bits through 3 of the DRV11 parallel board This allows the digital computer to look at a specific amplifier output If bit 7 65 is zero the 74193 is counted by use of a LM555 timer chip This causes the amplifiers to be scanned Bits 4 and 5 of the DRV1l parallel board are used to multiplex one of the three sets of multiplexers output into a single analog out put Figure 1 Each of the three multiplexer outputs Compl Comp2 Comp3 is brought into magnitude comparators Each magnitude comparator is realized by the use of two sections of a LM339 quad comparator Figure C 1c outputs are open collector and are stia The transistor and diode circuit of Figure 1 is used to convert the LM339 outputs to TTL levels If an over range is detected and bit 15 of DRV11 parallel board is not set a flip flop is cleared This caes an interrupt to It also causes the analog computer to go in HOLD This is done by removing n
30. e bus driver is used for this one bit After the data are loaded or output the real time clock asserts BRPLYL 11 signals output except data are asserted using 8881 55 chips These chips are capable of driving the required 70mA BRPLYL and the data address lines are cleared when the CPU clears BSYNCL The interrupt request and acknowledge logic is shown in Figure B 2d This circuitry does nothing if 56 the interrupt enable bit is not set When 56 is set a clock overflow Figure 2 will cause the real time clock to assert BIREOL the interrupt request line When the CPU acknowledges an interrupt request it will assert BIAKIL If the real time clock did not request an interrupt it will pass the signal down the daisy chain by asserting BIAKOL If the real dum clock did request an interrupt it will set a flip flop Next the CPU will assert BDINL This will cause the real time clock to load its interrupt vector onto the data address lines and to assert BRPLYL When the CPU clears BDINL the real time clock clears BSYNCL and the data address lines The counter will always be loaded with the contents of the buffer register until SO is set Figure B 2c When 50 is set the counters are counted up by the clock The clock frequency is determined by 3 54 and 55 These lines are used by a 74151 multiplexer to select one of eight frequencies Figure B 2e When an overflow occurs in the counter the counter is reloaded bit S7 is
31. e dividers On these channels this lowers the input impedence to the to D converter to 10 K Ohm This is acceptable because of the low output impedence of the op amps on the analog computer However caution should be taken if the distribution panel is used elsewhere The problem could be corrected by adding op amp buffers to the inputs of these channels contains the listing of a program that will assist the user in calibrating the voltage dividers on the distribution panel along with directions on how to use the program For more information on the ADV11 A board and information on how to program it see reference 6 2 5 The DRV11 16 Bit Parallel Board In order to communicate with the digital circuitry that was added to the analog computer a DRV11 16 bit parallel input output board was 13 purchased from Digital Equipment d The DRV11 was used 1 for output Therefore the input d could be used for some Spee purpose The DRV11 has an output buffer an input buffer and a status regis ter The status register has two request flags that can be set by the circuitry with which the computer is communicating It also has interrupt enable bit for each of these flags When the interrupt enable bit is set and the corresponding request flag set the DRVI1 will generate an interrupt request Lastly the 08711 status register bud two flags which are set and cleared under program control How the output
32. e problem The software is a large enough problem to make the complete hybridization of an analog computer unfeasible It is shown however that an analog computer can be improved through the use of a digital computer digital Particular advantages were readily apparent in output data collection and presenta tion The ability to prevent the problem from going over range and the ability to acquire data in digital form were added to the C without undue expense and without the need to develop extensive soft ware Finally although a PDP11 03 microcomputer is used in this system a much smaller and more compact system could be realized using a micro computer such as the Billings Microsystem System which employs a 2804 microprocessor display floppy disks and input output processor all in a single terminal 4 2 Suggested Future Projects This section gives some ideas on improving the system without completely hybridizing it 46 Although the sample program is easy to adapt to any problem it would be desirable to have a program that required no manipulations to work on any problem to the limits of the hardware Such a program would have inputs such as number of A D channels needed sampling rates for A D channels used how long to run the problem and on what condition to stop che prokla It would be desirable to have a program that converted the data from the binary representation used by the A D c
33. egative voltage that is ap plied to a relay The transistor used to switch this voltage is isolated from the rest of the circuit by an optical isolater the relay is very noisy The transistor used to put the analog computer in HOLD can be bypassed by use of the bypass switch If bit 8 is set the analog computer will be put in HOLD but no interrupt will be requested 66 re SEL14 15 4 bnc rtm sumo COMP 1 Figure C la Over Range Detection Circuitry Schematics 67 5V SEL12 SEL13 SELI4 SEL15 SELO8 SEL 9 SELI SEL11 74193 Bit 3 Bit Bit 1 SEL 4 SEL 5 SEL 6 SEL 7 Bit 5V 0 SEL SEL 1 SEL 2 SEL 3 ics itry Schemat ircu Over Range Detection C Figure C 1b 68 T S Lx gt 14 Ir amm 5V 3 LL 2 met s 51 lap x roe 13 c Be analog output Figure 1 Over Range Detection Circuitry Schematics APPENDIX D 70 Program Listing for Demonstration Program Following is the program used to demonstrate the use of the system The program is well documented and demonstrates ali the capabilities of the system FL 9 THE FOLLOWING FROGRAM IS TEST PROGRAM SFOR THE INTERFACE BETWEEN THE 11 03 SAND THE TR 48 ANALOG COMPUTER SETTING UF TH
34. ess than or equal to one To leave the program hit control 49 7 THE FOLLOWING FROGRAM IS USED TO CALIBRATE THE SAZO CONVERTER DISTRIBUTION FANEL CHANNELS 11 THROUGH 15 ARE DIVIDED BY TWO CHANNELS ANI SEACH HAS THAT IS USED CALIBRATE THE CHANNEL L TO USE THIS PROGRAM AFFLY FIVE VOLTS CHANNELS 10 THROUGH 15 THE FROGRAM 3READS THE VALUE OF THE VOLTAGE AT EACH OF THESE CHANNELS CALCULATES HOW EACH MUST BE TURNED IN ORDER TO MAKE THE VOLTAGES CHANNELS 11 THROUGH 15 EQUAL TO HALF THE VOLTAGE AT CHANNEL 10 THE PROGRAM UNTIL ALL VALUES OUTPUT TO THE 3FRINTER ARE EQUAL TO 1 TO GET BACK TO THE MONITOR HIT CONTROL C lt gt lt gt RO ZO 1 71 R2 42 R3 43 RA X4 RSA R amp 446 R7zX7 MCALL FRINT TTYINs U2 TTYOUT 2 START CLR 402 MSG WAIT LOOF1 56 SFOR LINEFEED TO BE THE HEADING SFACE 5 FINTRI1 2400 SET THE VECTOR MOY 5100 170400 sSET A D STATUS REG INC 04170400 CONVERSION WAIT SWAIT FOR INTERRUPT MOV INTR2 9 C 400 100 2 INCE 170401 TSTE 170401 LOOF I INC 170400 WALT BR LOOF2 INTERRUFT ROUTINE TO READ CHANNEL 10 INTR1 MOV 170402 1 ADL 4000 1 RTI gt a lt gt
35. et by the ADV11 A for of three reasons It is Sor if an external start is attempted before the chan nel multiplexer has had time to settle is set if an attempt is made to start a conversion when a conversion is in progress Finally it is set by failing to read the results of a previous conversion be fore the end of the current conversion Error Interrupt Enable This bit is set by program control and causes the ADVII A to generate an interrupt request when the A to D Error bit has been set When using the ADVI1 A the programmer must be careful not to start a conversion for nine microseconds after the channel multiplexer address has been set The multiplexer must be given this amount of time to settle The conversion time of the 40 11 is thirty two microseconds 12 When interrupt I O is used a through put rate of about 32 KHz is obtained if all the G Rang are made on one channel If the input channel is changed between every conversion nine microseconds must be added to the conversion time thus dropping the through put rate to about 25 KHz It was necessary to build a distribution panel for the A to D converter Because the ADV11 A has an input range from 5 12 to 5 12 and the TR 48 analog computer has a range from 10 to 10 volts it is desirable that some of the channels on the to D converter have divide by two voltage dividers This was done to the top five channels 10 15 by inserting 10 K Ohm voltag
36. f range would be adiustad td prevent it from going out of range Data being acquired must also be rescaled The condition of an ampli fier output being scaled too low must also be checked The error of the amplifiers is a percentage of full scale so small have the isses per cent error 2 It may be necessary to calculate new initial conditions and restart the problem This would be necessary in boundary value prob lems in which the shooting method was used 3 It may be necessary to change the gains of various blocks in the problem being solved The software may have to rescale in both amplitude and time when this is done example of this would be in the simulation of adaptive control systems 4 The problem may be reconfigured by the use of analog switches This might be necessary in the simulation of nonlinear relay type problems 5 Lastly it may be necessary to stop the solution and store the end conditions This might be done because the solution is finished or has gone unstable The tasks listed above are only a part of the software problem 45 The digitally set inputs must be controlled Data must still be ac quired and stored Also it would be highly desirable to have soft ware to help set up the problem This is especially true with the digitally controlled components of the system In conclusion it appears that the major obstacle to overcome in completely hybridizing an analog computer is the softwar
37. for components and be about the same size as the hardware discussed in Chapter II The most desirable piece of hardware that could be added to the system would be a digital to analog D A converter The D A converter would give the system the capability of automatically setting the initial conditions of the integrators and the capability of enabling 32 the digital computer to change inputs to the problem as the solution progressed The D A converter should have at the very least channels This would give fourteen channels to set the initial conditions in each of the integrators and leave two channels to use as real time inputs to the solution DIA converter would preferably have twelve bits of in order to match the resolution of the analog to digital converter The speed of the D A converter should be faster than thirty microseconds the speed of the A D converter The range of the convert er should be between 10 and 410 volts to match the range of the analog computer Digital Equipment Corporation has available a D A converter built for the PDP11 03 that meets all the requirements except d has only four channels One of these channels could be multiplexed into sixteen sample and hold circuits to meet the requirement of having at least sixteen channels However with just a little more effort and lot less expense a 16 bit parallel board can be used to give the digital computer control of circuit
38. hines ERE SKEL 2 1 3 Advantages of Combining an Analog and a Digital Computer 2225505 5 URL Tes AT 4 II THE IMPLEMENTED SYSTEM 454 ea 5 6 Introduction s e ss 50 o 55 6 The Analog Computer s s s s s es esoe we wo 6 9 9 A BS POS PS KA P9 DN fe Ul Co 9 Digital Computer e s e s we oe The ADVII A Analog to Digital Converter The DRV11 16 Bit Parallel Board 12 The Real Time 13 The Over Range Test Circuitry 19 A Program to Demonstrate the System eo 25 III SUGGESTED ADDITIONS TO THE SYSTEM 31 3 1 Introduction PCM X Dr 31 3 2 Suggested Hardware Additions rn 31 3 3 Suggested Software Projects e s soos sos oo 40 IV CONCLUSION E oss ee de 43 4 1 A Summary of the Thesis dome N sema dr Cm dax URS ee 43 4 2 Suggested Future Projects s soso e 45 APPENDIX A The A D Converter Distribution Panel Calibration Program 47 APPENDIX B Circuit Description and Schematics for the Real Time Clock ue eol Vue sa D De C DOS DIOS ES 52 APPENDIX C Circuit D scription and Schematics for Over Range Circuitry 63 APPENDIX D i Program Listing for Demonstration Program 69 REFERENCES
39. in the status register the real time clock will generats an interrupt request If the overflow flag of the status 15 not cleared by the time that a occurs an error flag is Sure Table 2 1 summarizes how the bits of the status register are used The bits are numbered to 15 from right to left The time base for the real time clock is a 2 MHz crystal oscillator which when divided by two the needed 1 MHz signal The 1 MHz signal is divided by ten four times to give the other needed frequencies When an external frequency is to be used with the counter the sig nal shouid be connected to connector tab A Sea 2 2 for the location of connector tab The external input is TTL compatible and consists of one TTL unit load When an overflow occurs a pulse will be generated on connector tab B 15 Table 2 1 Real time clock status register bit assignment Clock Enable set or cleared under program control and causes the buffer to be loaded into the counter and counting to start Bits 3 4 M3 Counting Frequency determines the rate at which the counter counts 000 does not count 001 1 MHz 010 100 KHz 011 10 KHz 100 1 KHz 101 100 Hz 110 external 111 Line 60 Hz causes the real time clock to request an interrupt when an overflow occurs S Bit 1 Overflow Flag set by real time clock when an Bit 6 Interrupt Enable set by program control and i i o
40. inal section of this chapter software that was written to demonstrate the use of the system is described A block diagram showing how the different parts of the system are interconnected is shown in Figure 2 l 2 2 The Analog Computer The TR 48 is a general purpose analog computer that was built in the early 1960 s The TR 48 has forty eight op amps of which fourteen Real Time interfaced Clock directly to bus PDP11 03 Digital Computer clock overflow start conversion line A ra ara ae eR ra interfaced A D directly to bus Converter 15 one analog line analog 16 TE control interrupt lines request line TR 48 Analog Computer 48 amplifier over range outputs check circuitry operate halt control line Figure 2 1 System Block Diagram 8 may be used integrators It also has a number of other functional blocks such as comparators multipliers and diode function generators but these have no significant effect on the designs presented in this thesis The linear range of the op amps is from minus ten volts to plus ten volts There are six modes of operation on the TR 48 analog computer 1 The POTSET mode is used to set up the problem by applying ten volts across the E so that they cun be set to the desired values 2 The SLAVE mode is used it is desired to run beo TR 48 computers in parallel 3 The REP OP mode or re
41. ions and then starting the problem Giving the digital computer control of the RESET mode is quite easy The same type of circuitry that allowed it to control the OPERATE mode can be used See Appendix C It is recommended that the control of the RESET mode be given a bit in the status register of the over range detection circuitry This is because the OPERATE mode control and HOLD mode control bits are in this register and all the mode control bits should be in the same place It would probably be desirable to build circuitry to prevent a programmer from inadvertently putting the analog computer in both OPERATE mode and RESET mode simultaneously This can be done by ANDing the Auto Reset bit with the complement of OPERATE signal to form the effective Auto Reset signal It must be remembered that the analog com puter can be in OPERATE mode even if the Auto Operate bit is not set The correct signal to use for the ANDing is pin 5 of the 7575 chip shown in the schematics of Appendix C 36 For the system described to this point the digital computer com pletely controls the operation of the analog computer and can change initial conditions and inputs However the digital computer cannot automatically change the dynamics of the problem If ior T a particular problem it is known that one of the amplifiers will even tually go out of range it would be desirable to be able to rescale that particular amplifier
42. omputer and interfacing it to a Digital Equipment Corporation PDP11 03 digital computer Hardware built as part of the thesis includes circuitry to detect when one of the ampli fiers in the analog computer is about to go out of range circuitry which gives the digital computer the ability to input the output voltage of any amplifier and circuitry that allows the digital computer to stop and start the analog computer real time clock was also built added to the digital computer as part of the thesis work 11 of the hardware implemented is described in detail in the thesis The thesis also describes an example problem that demonstrates the capa bilities of the implemented system The example problem shows that an analog computer can be greatly improved by adding digital circuitry and a digital computer interface The thesis discusses some additional hardware that could be added to the system is concluded that giving the digital computer compiete control of the analog computer would be unfeasible except for special purpose systems because of the tremendous amount of software that would have to be written on the digital computer Chapter I INTRODUCTION 1 1 Introduction The purpose of this thesis is to demonstrate that a small analog computer when augmented with a small digital microcomputer can be turned into a much more versatile computer tool The thesis does not attempt to produce an end product comparable wi
43. onverter to the actual units of the system being simulated This would have for inputs scaling factors and the output files from a solution run It would also be desirable for this DEOEPHU have plotting capabilities Although it would most likely be unfeasible to implement the complete hybrid system suggested in Chapter III it might be useful to use some of the hardware suggested to implement a special purpose system For example if a complex system one using a large percentage of the analog computer components was being simulated and it was desired to develop a digital controller for the system it would be desirable to have a D A converter The additional software required wouid oniy involve software to realize the controller APPENDIX 48 The A D Converter Distribution Panel Calibration Program In order to run this calibration program jumper together channels 10 through 15 of the distribution panel Next apply about five volts to these jumpered Dunne and run the program The name of the Load Module is PNLTS SAV The program will compare channeis 11 through 15 to channel 10 and instruct the user which way to turn the on the distribution panel The number given for each chinni by the program can be used to esti mate how many times the particular pot should be turned number by two to get the estimate The program should be run until all numbers output are l
44. or most problems If this were the case each amplifier would require an 8 bit buffer two quad analog switch chips two quad op amp chips nine precision resistors and an op amp for the summer It might also be necessary to buffer the outputs of the buffer to drive the controls of the analog switches properly sixteen bit parallel board could be used to load the buffer register With multiplexing the same parallel board could be used to load the buffers of any number of programable gain amplifiers The system could also be reconfigured by the digital computer by the use of programable analog switches This would be rather simple and they could be programed using the same parallel board that would control the programable gain amplifiers The outputs would have to be buffered in order to eliminate the effects of the resistance in the analog switches Figure 3 3 shows a suggested design for the program controlled analog switches If the system were configured with all of the components discussed 39 out control buffer ing in in Figure 3 3 Programable analog switches 40 to this point a very versatile hybrid machine would be obtained How ever one essential element is missing from the system is th Ea eg The hext section will discuss some software that could be written to take advantage of the system 3 3 Suggested Software Projects The development of the sof
45. p it will run faster The Second advantage is that the problem can be set up so that there is a one to one correspondence between the different blocks of the system being simulated and the components of the analog computer Finally it is not necessary to learn numerical analysis as is necessary to understand a digital algorithm 1 3 Advantages of Combining an Analog and a Digital Computer In recent years prices of digital circuitry and digital computers have dropped to the point where it has become feasible to incorporate digital circuitry and a computer interface into most electrical equip ment of any complexity A digital computer can be used to control and monitor an analog computer The outputs can be monitored and results stored so that curve fits can be done on the data later off line The digital com 5 puter can also be used to monitor the op amps to check when they are about to go out of range and to put the analog E in HOLD fore the solution becomes incorrect because of non linearity in the op amps When this occurs the digital computer can indicate the action to be taken by de Programmer in order to stop the analog com puter from going out of range or perform the necessary operation if digital control circuits are part of the system The digital computer can also be used to do an automatic static check and to set up initial conditions on the this were done iterative problems such as solution
46. petitive operation mode is used when it is desired to display the solution eo system with a small time constant on an oscilloscope The problem will be restarted at a predetermined rate With the introduction of a good storage oscilloscope this mode is not as essential as it once was 4 The RESET mode causes the intial conditions to be loaded into the integrators It is used to make static checks and to start a problem 5 In the OPERATE mode the problem is being uu reer programmer will put the computer in RESET mode and then OPERATE mode 6 HOLD mode suspends the solution 11 the op amps will hold their values when the HOLD mode is entered The designs in this thesis will give the digital computer and 9 digital circuitry control of the OPERATE RESET and HOLD modes 2 3 The Digital Computer The PDP11 03 is a 16 bit microcomputer system with 28K words of memory and a dual floppy disk has extensive software including a monitor an editor for building files file handling programs a FORTRAN compiler and a macro assembler The PDP11 03 treats all input output devices as memory locations This makes it quite easy to add new boards to the system Input output modules occupy the addresses from 28K to 32K Daisy chained grant signals provide a priority structur d interrupt I O 5 Priority is determined by the physical loca tion of devices on the backplane When I O device s interrupt
47. restart the problem This same rou tine would acquire the end conditions and pass them to a file second routine probably written in FORTRAN could read the file and calculate the new estimated initial conditions and pass this information to a second file The original routine could be restarted It would read in the new initial conditions load them into the analog computer aud start another iteration This would continue until the required toler ance was met The FORTRAN routine would also check to SE that the solution is remaining stable The most difficult BS problems would be ones which would reconfigure the system However there are particular problems that could take advantage of this capability without too much effort An example is the simulation of a system that varies with time The hybrid system could be used to develop an adaptive controller for such system One of the main goals in developing software for a system of this type should be to make it general purpose and easy to use Any soft ware developed for the system should be developed with the idea of making the system easier to program Chapter CONCLUSION 4 1 A Summary of the Thesis Ihis thesis illustrates that an analog computer can be made a more useful tool through the implementation of digital circuitry and an interface to a digital computer The hardware Built gave the digital computer the capability of monitoring the analog comp
48. ry that contains the mere se and the sample and holds along with a D A converter D A converter chip that meets all the specifications can be purchased for under twenty dollars 10 The output of the D A converter would be multiplexed to the inputs of the sample and hold circuits in much the same way that the analog computer op amp outputs multi plexed to the A D converter However it should not be necessary to 33 multiplex the actual analog signal as will be shown in the suggested design Sample and hold chips could be purchased or the and holds could be realized with op amps and analog switches Reference 9 gives some examples of sample and hold circuits realized with op amps and analog switches With only sixteen bits to work with on the status register the output buffer of the parallel board it is to share gene bits This is because twelve bits are needed for the data input to the D A converter and four bits for the multiplexer This leaves none for control The data bits for the D A and the multiplexer rs could be shared This leaves four bits for control could be used to load the buffer for the D A 352 could load the multiplexer address one could enable the multiplexer and one daila be feft as a spare A suggested design is shown in Figure 3 1 Bits through 4 are shared by both the D A buffer and the multiplexer address buffer The remaining bits of the D A buffer
49. set and a signal is sent to the interrupt logic second overflow occurs before S7 is cleared 512 is set 56 When the PDP11 03 system is brought up it will assert BINTLL This will clear the buffer and status registers DLL 7490 C 010 2 MHz Crystal gt gt 7474 Figure B 1 7490 di ae NT C10 7474 C9 7408 C8 7402 C7 7400 CB 57 es B10 7402 89 8640 B5 74153 pnan 11 7590 A10 7490 A9 74151 A8 7402 A7 74193 74175 NANESE TRENT 2 75175 OOE iste 1 Al 8641 Real Time Clock Circuit Layout 5 p LBUFL uu ay PC S 6 5 9 8 19 1 o d 9 gt 12v 11 A8 3 aran 5 6 10 Figure B 2a Real Time Clock Schematics 59 13 B6 12 10 12 L BDRISL BDR15H B7 4 4 ME Td SDRI4L qz 5641 5 571 BDR13L T4 BDR13H 192 B6 BDRI2L p BDR12H DIP 23 DIP 22 DIP 21 74153 1 Data SELC Data B Figure B 2b Real Time Clock Schematics INQRL i TAB B 12 71815 kall 74175 BDR14H BDRI3H 2 in d
50. th a modern commercial hybrid computer but shows that our existing analog computer can be considerably enhanced in its capabilities by the addition of a digital computer and interface The following section gives a brief description of how an analog computer and a digital computer solve differential equations It also discusses some of the advantages and dissidvantuves of each procedure Section 1 3 discusses some of the advantages that might be gained by interfacing an analog computer to a digital computer while still operating primarily in the analog mode Chapter Two gives a more detailed description of the circuits designed and built and the software actually written Chapter Three discusses some suggested projects includes Some designs that were not actually implemented Chapter Four gives some conclusions that were arrived at as a result of the research 2 1 2 Comparison of the Two Types of Machines Analog computers are primarily used to simulate systems that can be described by a set of differential equations In sare ERE BER rela tionships the outputs of electrical systems to the inputs can be represented by differential equations It is possible to adjust the components of a mechanical system so that it may be represented by the same differential equations as a given electrical system with all the variables of the mechanical system represented by voltages The primary component of an analog computer system is
51. the analog computer in OPERATE mode and to signal the digital computer that this has been done by use of the console terminal The digital computer will then clear the Auto Hold bit and pulse the Auto Operate bit This will start the solution If amp goes over range the analog computer is put in HOLD mode by disabling the OPERATE mode relay and the digital computer receives an interrupt The interrupt routine will store all the voltage values of the op amps and instruct the operator to take action 2 8 A Program to Demonstrate the System The previous sections of this chapter described all the hardware that was constructed as part of this thesis This section will summa rize the system that is now available and describe the program that was written to demonstrate how the system can be used A listing of the program is given in Appendix D Basically what exists is an analog computer being monitored and partially controlled by a digital computer block diagram of the system is shown in Figure 2 1 The digital computer is capable of 26 acquiring data from the analog computer and deciding if the solution should be stopped Data can be stored on disk to be evaluated after the solution has been vids The solution will be stopped if an op amp attempts to go out of range When this happens the digital computer is alerted to take action The digital computer can read in the values of all the amplifiers deste them
52. the interrupt vector is deter mined The interrupt vector points to an address in memory that contains the address of the interrupt service routine The program counter will be loaded with the address of the interrupt service routine when an inter rupt is granted to the real time clock The address following the new program counter address contains the new status word The old program counter and status word are pushed onto G stack Only the bottom byte of the vector address can be set by the switches and thus the location of the interrupt vector must be in the bottom 128 words of memory The 18 57 56 55 11 52 S1 88 St SWI SW2 Switch on 0 Switch off 1 Figure 2 3 Setting address to the status register 5 54 S3 82 81 SW1 Switch on 0 Switch off 1 Figure 2 4 Setting the interrupt vector for the status register 19 PDP11 03 operating system leaves the lower part of memory paz interrupt vectors It is recommended that the vector address for the real time clock be set to octal 370 byte address because this address is not used by any existing devices The five volt power supply on the PDP11 03 was loaded limit thus necessary to use an extra five volt power The extra power supply was connected to the first four slots following the CPU board pin 01 See reference 7 page 303 for location of duds ein The reason the top
53. the operational amplifier op amp With resistive feedback the 25 amp acts as voltage summing amplifier With capacitive feedback the output is the integral of the sum of the inputs The op amp can also be made to differentiate ut Esa are highly susceptible to noise and thus are seldom used There are other components that are present in most analog computers but these will not be discussed here For more information on the components of an analog ue PN See references 1 2 and 3 The solution to a problem on an analog computer is a voltage observable on an oscilloscope or voltmeter or recorded on an XY plotter The solution may be real time or it may be scaled in time For problems with small time constants time is slowed down by igna creasing the time constants in the analogous electrical system For probiems with large time constants time is speeded up by decreasing 3 the time constants in the analogous electrical system Usually the amplitude must also be scaled in order to stay in the linear range of the op amps For more information on time and amplitude scaling see reference 1 The analog computer is controlled manually The problem is first wired on a patch board this is where the bulk of the work is in pro graming an analog computer Next the computer is put in RESET mode and a static check is made i e the initial conditions are checked for validity Finally the computer is put in
54. tine could reset the gain of the amplifier and restart the program If it in volved one of the analog computer op amps it could notify the operator to reset the gain or gains would be desirable to have this routine keep track of how the acquired data must be scaled and to pass this information on to a data reduction routine The data reduction routines would usually be run Bree R tion of the problem and would normally be written in FORTRAN The real time routine might be written in assembly language because of can Programing in FORTRAN has the advantage of being to program and provides access to canned programs The data reduction routines would do things like convert the data to the proper units plot the data and do curve fits on the data type of problem that has been briefly mentioned but expounded upon is the iterative type problem Boundary value problems are of this sort In this type of problem some of the initial conditions are known and some of the end conditions are known The unknown initial condi tions are guessed and the solution run The computed end conditions are compared to the known end conditions and this information is used to estimate new initial conditions This procedure continues until some tolerance is met It would be desirable to have a real time 42 routine to load the initial conditions using the D A Gn pa and to reset the computer and then
55. tware necessary to fully exploit the hardware developed in this thesis would be an immense job However just as the hardware was only partially and still resulted in a useful system the software could be partially developed nd still be useful This section suggests some software projects that might b undertaken in order to enhance the system One of the main tasks of the digital computer is that of data acquisition This task must be performed in a real time mode and thus very little should be done as far as data reduction such as converting the voltages to the simulated var ables while data is being acquired However if a large amount of data is being input on the order of 100 000 samples or more it might desirable to compress the data Since the data has twelve bits of resolution and the word length of the computer is sixteen bits it is possible to store four words of data in three computer words This increases the problem of programing but saves twenty five per cent in storage space Another problem that must not be overlooked is that of what to do when the Bolution is rescaled When the solution is restarted it must be remembered that new data 41 is to be multiplied by a different scale factor When it becomes necessary to rescale the problem it would be pos sible to have a software routine that would do the rescaling the rescaling involved a programable gain amplifier the rou
56. uter Interface Loadable 16 Bit Counter Figure 2 5 l Block diagram of over range detection circuitry 23 Table 2 2 Over range test circuitry status register bit assignment Bits 0 5 Multiplexer Address The bits 0 through 3 are loaded into the counter when the load bit is set Bits 4 and 5 are used to multiplex one of the three comparators inputs to the Analog to Digital Converter Bit 7 Load Bit Set by program control When set it will disable the 10 KHz clock and load the multiplexer address into the counter Bit 8 Auto When set by program control the analog computer is automatically put in HOLD mode Bits 9 14 Not used Biets Auto Operate When set by program control the analog computer will automatically be put in OPERATE mode E 5 H f i i 24 The voltage detected by the A D converter is half the voltage of the op amp being monitored because the A D converter has a range from 5 12 to 5 12 volts while the op amps have a range of 10 to 10 volts Also the analog switches used can only handle a differential of 15 volts In the design the analog switched between 6 volts and 6 volts or a 12 volt differential When using the over range detection circuitry to read in voltages the user must be sure to give the multiplexer time to settle At least 100 microseconds should be allowed
57. uter for over range some other condition and acquiring data The digital computer could stop and start the solution but had no capability of actually entering into the problem solution The program in Appendix D demonstrates all the capa bilities of the This program can be used to acquire data and monitor for over range conditions for any problem run on the TR 48 analog computer with little or no modification Saoz modifications would be required if data were to be acquired from more than two ampli fiers The program is documented quite extensively Therefore m di fications should not be grear problem The digital computer can start and stop the solution but has no capability of actually entering into the problem solution This limi tation makes the hardware relatively easy to use The hardware described in Chapter III would give the digital computer the ability to interact in and reconfigure the problem The hardware could be built without great expense i e it could be realized with Beand rd and linear components However the software requirements for the system 44 would be extensive For the noninteractive system the softwate only checked for some condition he solution when this condition was met Jun interactive system the software must choose among a number of alternatives Some of the possibilities are listed below 1 The problem may have to be rescaled An amplifier about to go out o
58. verflow occurs and cleared by program control Bit 12 Error Flag set by real time clock when an overflow occurs while bit 7 is still set Cleared when bit 7 is cleared 16 Tab B Tab A 8 1 SW2 8 1 power jumpers SW1 1 1 36 Figure 2 2 Locations of switches tabs and jumpers on the real time clock 17 See Figure 2 2 for the location of connector tab B This external out put is TTL compatible and capable of driving about eight TTL unit loads The External Start on the analog to digital converter presents five TTL unit loads It is assumed that connector tab will be connected to the External Start on the to D converter The address of the status register is determined by the settings of the DIP switches 7 and 8 on SWl and 1 through 7 of 592 See Figure 2 2 for the locations 5 1 and SW2 The address of the buffer register is the address of the status Xact tar pius two It is two greater than the address register is because the PDP11 03 has byte 8 bits addressing and thus 16 bit words have even ber addresses Figure 2 3 shows how the address is determined Notice that the address is in the top 8K bytes of memory Digital Equipment Corporation recommends that the real time clock set to the octal address 170420 The interrupt vector is determined by the settings of switches 1 through 5 of SW2 Figure 2 4 shows how
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