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Correction for Incorrect Description Notice RL78/G13 Descriptions in

1. Standby release signal N Status of CPU Operating mesel HALT mode Wait Note li Operating mode High speed system clock Oscillation High speed on chip oscillator clock or subsystem clock Notes 1 For details of the standby release signal see Figure 16 1 2 Wait time for HALT mode release e When vectored interrupt servicing is carried out Main system clock 15 to 16 clock Subsystem clock RTCLPC 0 10 to 11 clock Subsystem clock RTCLPC 1 11 to 12 clock e When vectored interrupt servicing is not carried out Main system clock 9 to 10 clock Subsystem clock RTCLPC 0 4 to 5 clock Subsystem clock RTCLPC 1 5 to 6 clock RENESAS Page 60 of 70 RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect descriptions of STOP mode release time revised p 864 865 Incorrect Figure 18 5 STOP Mode Release by Interrupt Request Generation 1 2 1 When high speed system clock X1 oscillation is used as CPU clock Interrupt request STOP instruction Y Standby release signal A UN Normal operation Oscillation Normal operation high speed stabilization time high speed Status of CPU Oo system clock STOP mode set by OSTS Je E system clock High Speed Oscillates Oscillation stopped Oscillates System clock X1 oscillation Note Wait time for STOP mode releas e High s d system clock X1 oscillation 3
2. Omitted Correct 4 When AVREF Internal reference voltage ADREFP1 1 ADREFPO 0 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 2 4 V Vpn lt 5 5 V Vss EVsso EVss1 0 V Reference voltage Vacr Reference voltage AVREFM 0 V HS high speed main mode Parameter Conditions Resolution Conversion time 8 bit resolution 24VxVppx5 5V Notes 1 4 8 bit resolution 24V xVpp x 5 5V Zero scale error Integral linearity error e 8 bit resolution 2 4V lt VpD lt 5 5V Differential linearity error Note 1 8 bit resolution 24V lt VDD lt 5 5V Reference voltage VBGR Reference voltage AVREFM Analog input voltage VAN Omitted Re Page 52 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 14 Condition of Temperature sensor characteristics in Electrical Specifications chapter section 29 7 2 added page 1036 Incorrect 29 7 2 Temperature sensor characteristics Ta 40 to 85 C 2 4 V lt EVopo EVon1 lt Von lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions Temperature sensor output voltage Vrweszs Setting ADS register 80H TA 25 C Reference output voltage Vconst Setting ADS register 81H Temperature coefficient Fvrmes Temperature sensor that depends on the temperature Operatio
3. If using AVREFM as the side reference voltage source of the A D converter do not select ANI1 as an A D conversion channel If ADISS is set to 1 the internal reference voltage 1 45 V cannot be used for the side reference voltage source When entering STOP mode or HALT mode while the CPU is operating on the subsystem clock do not set ADISS to 1 When setting ADISS to 1 the current value of the A D converter reference voltage current laprer shown in 29 4 2 Supply current characteristics is added Re Page 23 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 7 Incorrect descriptions of maskable interrupt request acknowledgement operation revised Revised incorrect description of time from generation of maskable interrupt until servicing in Table 16 4 page 842 Incorrect 16 4 1 Maskable interrupt request acknowledgment Omitted Table 16 4 Time from Generation of Maskable Interrupt Until Servicing equest is generated j be Remark 1 clock 1 fc k fcu CPU clock Correct 16 4 1 Maskable interrupt request acknowledgment Omitted Table 16 4 Time from Generation of Maskable Interrupt Until Servicing Note Maximum time does not apply when an instruction from the internal RAM area is executed Remark 1 clock 1 fc k fcu CPU clock Re Page 24 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Figure 16 9 Incorrect description of interrupt r
4. RESET Normal operation Save processing Normal operation Operation status LVIF flag LVISEN flag set by software LVIOMSK flag LVIMD flag Cleared by software Note 3 LVILV flag y Cleared b software Note 2 LVIRF flag LVD reset signal POR reset signal Internal reset signal LVIIF flag Page 33 of 70 RENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 After an interrupt is generated perform the processing according to figure 21 7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode 3 After a reset is released perform the processing according to figure 21 8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode Remark Vror POR power supply rise detection voltage Vppr POR power supply fall detection voltage R Page 34 of 70 sKENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct Figure 21 6 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation Option Byte LVIMDS1 LVIMDSO 1 0 2 2 When a condition of Vop is VDD lt VLVIH after releasing the mask a reset is generated because of LVIMD 1 reset mode Supply voltage VoD ViviH Vivit Vpor 1 51 V TYP VPbR 1 50 V TYP LVIMK flag set by software Cleared by software Wait for stabilization by software
5. 20 24 25 30 32 pin products PO1 ANI16 pin 2 20 24 25 30 32 pin products POO ANI17 pin Omitted Correct Figure 22 16 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVrerm pin Omitted 1 Setting prohibited 0 Temperature sensor output 3 Internal reference voltage output 1 45 V e Other than the above Setting prohibited Notes and cautions are listed on the next page Notes 1 20 24 25 30 32 pin products PO1 AN116 pin 2 20 24 25 30 32 pin products POO ANI17 pin 3 This setting value can be selected only in HS high speed main mode Omitted Re Page 45 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 13 Conditions of A D converter characteristics in Electrical specifications chapter section 29 7 1 added Condition of 1 When AVREF AVREFP ANIO AVREF AVREFM ANM target ANI pin ANI2 to ANI14 added page 1032 Incorrect 1 When AVREF AVREFP ANIO ADREFP1 0 ADREFPO 1 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANI2 to ANI14 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss 0 V Reference voltage AVREFP Reference voltage AVrerm 0 V Parameter Conditions Resolution Notes a 10 b
6. Re Page 66 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 20 Caution of when using SNOOZE mode in serial array unit added Explanations of SNOOZE mode related to CSI added p 631 633 Incorrect Omitted Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes be sure to set the STm0 bit to 1 and clear the SEm0 bit to stop the operation Correct Omitted Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes set the STm0 bit to 1 clear the SEm0 bit and stop the operation And after completion the receive operation also clearing SWCm bit to 0 SNOOZE mode release Explanations of SNOOZE mode related to UART added p 658 659 661 Incorrect Omitted Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes be sure to set the STm1 bit to 1 and clear the SEm1 bit to stop the operation Correct Omitted Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes set the STm1 bit to 1 clear the SEm1 bit and stop the operation And after completion the receive operation also clearing SWCm bit to 0 SNOOZE mode release Re Page 67 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 21 Explanations of data flash in flash memory chapter added p 938 Incorrect An overview of
7. Reset signal generation clears this register to OOH Re Page 6 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect description of minute count register MIN in real time clock deleted Incorrect 6 Minute count register MIN The MIN register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of minutes It counts up when the second counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the second count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 00 to 59 to this register in BCD code If a value outside the range is set the register valu returns to the normal value after 1 period The MIN register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 6 Minute count register MIN The MIN register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of minutes It counts up when the second counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the second count register overflows while this register is being written this register ignores the overflow and is set to the value
8. stabilization wait time Set the LVIMD bit to 0 to set interrupt mode m N 0 Set the LVISEN bit to 0 to enable voltage detection p Normal operation Remark fiL Low speed on chip oscillator clock frequency Re Page 38 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 10 Added common item for all RL78 G13 products in 29 4 2 Supply current characteristics of Electrical specifications page 1005 Incorrect 4 Common to RL78 G13 all products TA 40to 85 C 1 6 V x EVpbo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V Sms T cm TR S9 WK OT RTC operating Notes 1 2 Ifsug 32 768 kHz Real time clock operation Lo pep 1 current Interval timer operation Watchdog timer N fiL 15 kHz 0 22 operating current A D converter DIES When conversion Normal mode AVREFP VDD 5 0 V operating at maximum Low voltage mode AVREFP VDD 3 0 V 0 5 0 7 current speed Temperature sensor operating current LVD operating current BGO operating ipgo 59 2 50 1220 mA current Note Omitted Correct 4 Common to RL78 G13 all products TA 40 to 85 C 1 6 V x EVbDo EVDD1 lt VpD lt 5 5 V Vss EVsso EVss1 0 V Ere m preme eee e Eme Watchdog timer fiL 15 kHz 0 22 operating E TEE A D converter lane When conversion Normal mode AVREFP VoD 5 0V mode AVREFP VoD 5 0 V operating OE maximum L
9. 1 Low prohibited YO sous 25us fows 1 1 Voltage 37 5 hs fcuk 6 2 Setting 31 25 us gt eo prohibited fcuk 5 prohibite Lo S us 2945 prohibited fcud4 50 us 25us Setting foux 2 prohibited Page 16 of 70 RENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Incorrect Table 11 3 A D Conversion Time Selection 7 8 7 1 8 V lt VDD lt 27 V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 ADMO FR1 Mode FR2 FRO LV1 LV0 Normal 1 Normal 2 Low Voltage 1 Low Voltage 2 Note Omitted Conversion Time Selection fcLK 16 MHz Note fcCLK 8 MHz fcLKk 4 MHz Setting prohibited Setting prohibited prohibited prohibited prohibited prohibited Setting Setting prohibited Setting prohibited prohibited prohibited prohibited prohibited Setting Setting prohibited prohibited Setting hs prohibited mue s us Setting Setting Setting 2 prohibited prohibited Setting Setting 2 prohibited prohibited Setting us prohibited us 54 us Setti 54us 2zps 9 prohibited Setting Setting x prohibited prohibited Setting Setting nd prohibited prohibited RENESAS Date April 6 2012 Conversion Clock fab fc k 64 feik 32 fcLk 16 fcuk 8 fcuk 6 fcuk 5 fcuk 4 fcuk 2 fclk 64 fc
10. Date April 6 2012 1 Descriptions of related information according to discontinued development of 64 pin TQFP 7 x 7 package deleted Order information of 64 pin Incorrect lastic TQFP 7 x 7 deleted page 4 Data flash Part Number Mounted Not mounted N ot mounted Not mounted 64 pin plastic LQFP 12x12 64 pin plastic LQFP fine pitch 10 x 10 64 pin plastic TQFP fine pi x Not mounted 64 pin plastic FBGA 4 x 4 Omitted RSF100LCAFA R5F100LDAFA R5F100LEAFA R5F100LFAFA RSF100LGAFA R5F100LLAFA R5F101LCAFA R5F101LGAFA R5F101LLAFA R5F100LCAFB R5F100LGAFB R5F100LLAFB R5F101LCAFB R5F101LGAFB R5F101LLAFB R5F100LHAFA R5F101LDAFA R5F101LHAFA R5F100LDAFB R5F100LHAFB R5F101LDAFB R5F101LHAFB R5F100LJAFA R5F101LEAFA R5F101LJAFA R5F100LEAFB R5F100LJAFB R5F101LEAFB R5F101LJAFB R5F100LKAFA R5F101LFAFA R5F101LKAFA R5F100LFAFB R5F100LKAFB R5F101LFAFB R5F101LKAFB RSF100LCAFC RSF100LDAFC RSF100LEAFC RSF100LEAFC R5F100LGAFC R5F100LHAFC R5F100LJAFC RS5F100LCABG R5F100LDABG R5F100LEABG R5F100LFABG R5F100LGABG R5F100LHABG R5F100LJABG R5F101LCABG R5F101LDABG R5F101LEABG R5F101LFABG R5F101LGABG R5F101LHABG R5F101LJABG RENESAS Page 3 of 70 RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct Data flash Part Number Omitted R5F100LCAFA R5F100LDAFA R5F100LEAFA R5F100LFAFA M
11. When LVD of Reset processing time when RESET input Reset processing time 387 to 674 ws When LVD is used 155 to 360 us When LVD of Correct Reset processing time of reset by POR when the power is turned on Reset processing time 497 to 720 ws When LVD is used 265 to 407 ws When LVD off Reset processing time when HALT reset or STOP reset or RESET input Reset processing time 388 to 673 ws When LVD is used 156 to 360 us When LVD off RENESAS Page 59 of 70 RENESAS TECHNICAL UPDATE TN RL A001C E Date Incorrect descriptions of HALT mode release time revised p 860 Incorrect Figure 18 3 HALT Mode Release by Interrupt Request Generation Interrupt HALT request instruction Standby release signal April 6 2012 Status of CPU Operating model HALT mode l Wait Note i Operating mode High speed system clock Oscillation High speed on chip oscillator clock or subsystem clock Not Wait time for HALT mode release e When vectored interrupt servicing is carried out Main system clock 13 to 15 clock ubsystem clock RTCLPC z 0 8 to 10 clock ubsystem clock RTCLPC z 1 9 to 11 clock e When vectored interrupt servicing is not carried out Main system clock 8 to 9 clock ubsystem clock RTCLPC 0 3 to 4 clock ubsystem clock RTCLPC 1 4to 5 clock Correct Figure 18 3 HALT Mode Release by Interrupt Request Generation Interrupt HALT request instruction
12. page 1033 Incorrect 2 When AVREF AVnErFP ANIO ADREFP1 0 ADREFPO 1 AVREF AVREFM ANI1 ADREFM 1 target ANI pin ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage AVREFP Reference voltage AVREFM Parameter Conditions Resolution Gi 10 bit resolution 1 8 V lt VpD lt 5 55V AVRerp Voo 1 6V lt Vpp lt 5 5V Overall error Conversion time Zero scale errorNotes 1 2 Full scale errorNetes 1 2 Omitted Integral linearity error e Differential linearity error Reference voltage AVREFP Analog input voltage VAIN 24V lt Vop lt 5 5 V Omitted Re Page 48 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct 2 When AVREF AVREFP ANI0 ADREFP1 0 ADREFPO 1 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage AVREFP Reference voltage AVREFM Parameter Conditions Resolution ee 10 bit resolution 1 8 V lt VDD lt 5 5V AVRerp Vpp 1 6V lt Vpp lt 5 5V Overall error Conversion time Zero scale errorNotes1 Full scale errorNetes 1 2 Omitted Integral linearity error e 1 Differential linearity err
13. software 400 us or 5 clocks of fiL 1 TL Normal Save Operation status __RESET operaton processng RESET JNormaloperaton RESET Save processing E Cleared LVIF flag LVISEN flag set by software LVIOMSK flag Cleared by LVILV flag Software Note 3 Cleared by LVIRF flag software Note 2 LVIMD flag LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag Re Page 35 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 After an interrupt is generated perform the processing according to figure 21 7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode 3 After a reset is released perform the processing according to figure 21 8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode Remark Vror POR power supply rise detection voltage Vppr POR power supply fall detection voltage Re Page 36 of 70 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Figure 21 7 Processing Procedure After an Interrupt Is Generated INTLVI generated Sese LVD reset generated Normal operation RENESAS Perform required save processing Set the LVISEN bit to 1 to mask voltage detection LVIOMSK 1 Set the LVILV bit to 0
14. Electrical specifications chapter section 29 4 2 is the same for all RL78 G13 Group products Explanations when using temperature sensor and internal reference voltage 1 45 V of A D converter added Explanations when using temperature sensor and internal reference voltage 1 45 V of A D test function in Safety functions chapter added Conditions of A D converter characteristics 13 in Electrical specifications chapter section 29 7 1 added Applicable Item Rev 1 00 After Rev 2 00 No O c N Condition of Temperature sensor 14 characteristics in Electrical specifications chapter section 29 7 2 added Industrial applications and extended temperature products released Incorrect descriptions of recommended connection of unused pins of P60 to P63 in table2 3 in pin functions chapter revised Incorrect descriptions of 7 4 2 Shifting to HALT STOP mode after starting operation in real time clock chapter revised Incorrect descriptions of reset processing time standby mode release time revised mode in A D converter chapter added serial array unit chapter added Explanations of data flash in flash memory chapter added Spec of on chip oscillator characteristics in electrical specifications chapter confirmed N Note No 15 to 23 bold text are the corrections added in this notice Remarks v Corrected Items should be corrected Re Page 2 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E
15. STOP mode or HALT mode while the CPU is operating on the subsystem clock do not set ADREFP 1 to 1 When selecting internal reference voltage ADREFP1 ADREFPO 1 0 the current value of A D converter reference voltage current laprer shown in 29 4 2 Supply current characteristics is added Re Page 22 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Note on analog input channel specification register ADS added page 497 Incorrect Figure 11 11 Format of Analog Input Channel Specification Register ADS 2 2 Address FFF31H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 Omitted Cautions 1 Be sure to clear bits 5 and 6 to 0 Omitted If using AVREFP as the side reference voltage source of the A D converter do not select ANIO as an A D conversion channel If using AVREFM as the side reference voltage source of the A D converter do not select ANI1 as an A D conversion channel If ADISS is set to 1 the internal reference voltage 1 45 V cannot be used for the side reference voltage source Correct Figure 11 11 Format of Analog Input Channel Specification Register ADS 2 2 Address FFF31H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADS ADISS o ADS4 ADS3 ADS2 ADS1 ADSO Omitted Cautions 1 Be sure to clear bits 5 and 6 to 0 Omitted If using AVREFP as the side reference voltage source of the A D converter do not select ANIO as an A D conversion channel
16. clock Figure 18 5 STOP Mode Release by Interrupt Request Generation 2 2 2 When high speed system clock external clock input is used as CPU clock Interrupt request STOP instruction Standby release signal STOP mode release tuime ete Normal operation Normal operation high speed Supply of the high speed high sp i Wait high sp Status of CPU system clock STOP mode clock is stoppe system clock High speed system clock external clock input Oscillates Oscillation stopped Oscillates 3 When high speed on chip oscillator clock is used as CPU clock Omitted Not STOP mode release time e High speed system clock external clock input 19 1 to 31 98 us e High speed on chip oscillator clock 19 1 to 31 Re Page 61 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct Figure 18 5 STOP Mode Release by Interrupt Request Generation 1 2 1 When high speed system clock X1 oscillation is used as CPU clock Interrupt request STOP instruction STOP mode release time Note2 Normal operation Normal operation high speed Supply of the high speed Wait Standby release signal Note 1 Status of CPU system clock STOP mode clock is stopped system clock High speed Oscillates Oscillation stopped Oscillates System clock X1 oscillation Notes 1 For details of the standby release si
17. elapsed after setting the RTCE bit to 1 see Figure 7 18 Example 1 e Checking by polling the RWST bit to become 1 after setting the RTCE bit to 1 and then setting the RWAIT bit to 1 Afterward setting the RWAIT bit to 0 and shifting to HALT STOP mode after checking again by polling that the RWST bit has become 0 see Figure 7 18 Example 2 Figure 7 18 Procedure for Shifting to HALT STOP Mode After Setting RTCE bit to 1 Example 1 Example 2 a em Sets to counter operation Sets to counter operation start start Sets to stop the SEC to YEAR Waiting at least for 2 counters reads the counter frtc clocks value write mode Checks the counter wait status HALT STOP instruction execution Shifts to HALT STOP mode i Sets the counter operation HALT STOP instruction Shifts to HALT STOP mode eaxecution Pes Re Page 58 of 70 s lt E NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 18 Incorrect descriptions of reset processing time standby mode release time revised Incorrect descriptions of reset processing time revised p 308 861 866 871 872 883 884 Incorrect Reset processing time of reset by POR when the power is turned on Reset processing time 387 to 720 ws When LVD is used 155 to 407 us When LVD of Reset processing time when HALT reset or STOP reset Reset processing time 387 to 720 ws When LVD is used 155 to 407 us
18. in Safety functions chapter section 22 3 8 added Explanation of Figure 22 15 A D test register ADTES added page 917 Incorrect 1 A D test register ADTES Figure 22 15 Format of A D Test Register ADTES Address F0013H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES1 ADTESO A D conversion target 0 0 This i ifi i log i ificati i ADS AVREFM 1 1 AVREFP Other than the above Setting prohibited Correct 1 A D test register ADTES Figure 22 15 Format of A D Test Register ADTES Address F0013H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES1 ADTESO A D conversion target ANIxx This is specified using the analog input channel specification register ADS AVREFM 1 1 AVREFP Other than the above Setting prohibited Note The temperature sensor output and internal reference voltage output 1 45 V can be selected only in HS high speed main mode Re Page 44 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect Figure 22 16 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVrerm pin Omitted 1 Setting prohibited 0 Temperature sensor output Internal reference voltage Other than the above Setting prohibited Notes and cautions are listed on the next page Notes 1
19. of ADREFP1 and ADREFPO 3 Stabilization wait time A 4 Set ADCE 1 5 Stabilization wait time B o 1 and 0 the setting i anged to A L set to 0 and 0 or 0 and 1 A needs no wait and B 1 x s When ADREFP1 and ADREFPO are set to 1 and 0 respectively A D conversion cannot be performed on the temperature sensor output Be sure to perform A D conversion while ADISS 0 Specification of the SNOOZE mode Do not use the SNOOZE mode function Use the SNOOZE mode function When there is a hardware trigger signal in the STOP mode the STOP mode is exited and A D conversion is performed without operating the CPU the SNOOZE mode e The SNOOZE mode function can only be specified when the high speed on chip oscillator clock is selected for the CPU peripheral hardware clock fc k If any other clock is selected specifying this mode is prohibited e Using the SNOOZE mode function in the software trigger mode or hardware trigger no wait mode is prohibited e Using the SNOOZE mode function in the sequential conversion mode is prohibited Re Page 64 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct 4 A D converter mode register 2 ADM2 Omitted ADREFP1 ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Vpn Supplied from P20 AVRerp ANIO Supplied from the internal reference voltage 1 45 V Note 1 Setting prohibite
20. written Set a decimal value of 00 to 59 to this register in BCD code The MIN register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Re Page 7 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect description of hour count register HOUR in real time clock deleted page 440 Incorrect 7 Hour count register HOUR The HOUR register is an 8 bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 decimal and indicates the count value of hours It counts up when the minute counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the minute count register overflows while this register is being written this register ignores the overflow and is set to the value written Specify a decimal value of 00 to 23 01 to 12 or 21 to 32 by using BCD code according to the time system specified using bit 3 AMPM of real time clock control register 0 RTCCO If the AMPM bit value is changed the values of the HOUR register change according to the specified time system If a value outside the range is set the register value returns to the normal value after 1 period The HOUR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 12H However the value of this register is 00H if the AMPM bit bit
21. 1 6 V lt VDD lt 1 8 V When there is stabilization wait time hardware trigger wait mode Conversion Time Selection fcLK fcLKk 4 MHz 8 MHz Normal Setting x x 1 prohibited A D Converter Mode Gizl 0 Gizl Conversion Clock fan Setting i MENE Normal Setting x x x 1 _ x 2 prohibited Setting prohibited Low Voltage 1 Setting prohibited Setting prohibited Low Voltage 2 Setting prohibited Note Omitted Setting prohibited Setting prohibited Setting prohibited Setting prohibited prohibited Setting prohibited Setting prohibited RENESAS Setting prohibited prohibited prohibited Setting prohibited Setting prohibited prohibited prohibited fcuk 64 fcuk 64 Page 21 of 70 RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 6 Note when entering A D converter standby mode added Note on A D converter mode register 2 ADM2 added page 493 Incorrect 4 A D converter mode register 2 ADM2 Omitted Caution Only rewrite the value of the ADM2 register while conversion operation is stopped which is indicated by the ADCS bit of A D converter mode register 0 ADMO being 0 Correct 4 A D converter mode register 2 ADM2 Omitted Cautions 1 Only rewrite the value of the ADM2 register while conversion operation is stopped which is indicated by the ADCS bit of A D converter mode register 0 ADMO being 0 2 When entering
22. 101LGAFC R5F101LHAFC R5F101LJAFC 64 PIN PLASTIC TQFP 7x7 Under development Correct Applicable page deleted Re Page 5 of 70 s lt E NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 2 Incorrect descriptions of count registers in real time clock deleted Incorrect description of second count register SEC in real time clock deleted page 439 Incorrect 5 Second count register SEC The SEC register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of seconds It counts up when the sub count register overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks fRTC later Set a decimal value of 00 to 59 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The SEC register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 5 Second count register SEC The SEC register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of seconds It counts up when the sub count register overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks fRTC later Set a decimal value of 00 to 59 to this register in BCD code The SEC register can be set by an 8 bit memory manipulation instruction
23. 150 to P156 1 6 V lt Voo lt 5 5 V Total of all pins PETTEE When duty 70 Note 3 Notes 1 Value of current at which the device operation is guaranteed even if the current flows from the EVppo EVpp1 Voo pins to an output pin Omitted Correct 29 3 1 Pin characteristics TA 40 to 85 C 1 6 V x EVppo EVpp1 lt Vpn lt 5 5 V Vss EVsso EVss1 0 V Conditions Output current Per pin for POO to PO7 P10 to P17 1 6 V lt EVbppo 5 5 V high te 1 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Omitted Total of all pins 1 6 V lt EVono lt 5 5 V When duty E 709 Note 3 Per pin for P20 to P27 P150 to P156 1 6 V lt Voo lt 5 5 V Total of all pins a When duty 709 Note 3 Notes 1 Value of current at which the device operation is guaranteed even if the current flows from the EVppo EVpp1 Von pins to an output pin Omitted The applied current for the products for industrial application R5F100xxDxx R5F101xxDxx is 100 mA Re Page 55 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 16 Incorrect descriptions of recommended connection of unused pins of P60 to P63 in table 2 3 in pin functions chapter revised p 93 Incorrect Table 2 3 Connection of Unused Pins 128 pin products 2 4 Pi
24. 3 Incorrect 11 7 4 Setup when using temperature sensor example for software trigger mode and one shot conversion mode Figure 11 35 Setup When Using Temperature Sensor Omitted Note Depending on the settings of the ADRCK bit and ADUL ADLL register there is a possibility of no interrupt signal being generated In this case the results are not stored in the ADCR ADCRH registers Correct 11 7 4 Setup when using temperature sensor example for software trigger mode and one shot conversion mode Figure 11 35 Setup When Using Temperature Sensor Omitted Note Depending on the settings of the ADRCK bit and ADUL ADLL register there is a possibility of no interrupt signal being generated In this case the results are not stored in the ADCR ADCRH registers Caution This setting can be used only in HS high speed main mode Re Page 42 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Explanation of 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins in 11 10 Cautions for A D Converter added page 530 Incorrect 11 10 Cautions for A D Converter 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins Observe the rated range of the ANIO to ANI14 and ANI16 to ANI26 pins input voltage If a voltage of Voo and AVrerp or higher and Vss and AVREFM or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In
25. 3 of the RTCCO register is set to 1 after reset Correct 7 Hour count register HOUR The HOUR register is an 8 bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 decimal and indicates the count value of hours It counts up when the minute counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the minute count register overflows while this register is being written this register ignores the overflow and is set to the value written Specify a decimal value of 00 to 23 01 to 12 or 21 to 32 by using BCD code according to the time system specified using bit 3 AMPM of real time clock control register 0 RTCCO If the AMPM bit value is changed the values of the HOUR register change according to the specified time system The HOUR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 12H However the value of this register is 00H if the AMPM bit bit 3 of the RTCCO register is set to 1 after reset Re Page 8 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect description of day count register DAY in real time clock deleted page 442 Incorrect 8 Day count register DAY The DAY register is an 8 bit register that takes a value of 1 to 31 decimal and indicates the count value of days It counts up when the hour counter over
26. DD lt 3 6 V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 Conversion Time Selection ADMO CLK fcLk fcLK fcLk fcLk FR2 FR1 FRO LV1 LV0 2 MHz 4 MHz 8 MHz 16 MHz 32 MHz i 54 us Setti Setting pan i idi etting a ibi prohibited Prt 54ns 27 us fax 32 Setting 54 27 135us fote k 16 Normal Settng prohibited 54 27 5 6 75 ns orma 1 40 5us 20 25 us 10 125 us 5 0625 us fcuw6 3375yus 16 875 us 8 4375 us foux 5 6 75 us prohibited 54 us 27us 13 5 us HS Setting foux 2 prohibited Conversion Clock faD N Gi E o Setting Seting 50 us fou64 Settin 9 prohibited 9 prohibited 5D SES prohibited us cu Setting 50 us 25 us 12 5 us fcu 16 eting rohibited Normal prohibited ner Bes aus 2 37 5 us 18 75 hs 9 375 us 4 6875 us fcuw6 3125 us 15 625 us 7 8125 us faxl5 prohibited 50 us 25us 125ygs 6 25us Setting feux 2 prohibited Setting S9 54 us fcud64 Setting hibited prohibited prohibited P9 99 54ns 27ns foun 32 Settin Po 54hs 27 ys fcuw16 Low Ing prohibited 54 27 faxl 1 prohibited HS us cu Voltage 40 5 us fcLk 6 3375 us Setting S tows 54 Setting rohibited prohibited EUR S IDI 0 H prohibited P in 54 us 2zus Set ng fcux 2 prohibited i S fcud64 Setting 9 prohibited prohibited prohibited 50 us fcix 32 Setting Setting 50 hs 25 us fcu 16
27. Date April 6 2012 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document x Caledory MPU MCU Nas TN RL A001C E Rev 3 00 Correction for Incorrect Description Notice Information Title RL78 G13 Descriptions in the Hardware Users Manual Cat Technical Notification Rev 1 00 Changed ategory Lot No Applicable RL78 G13 Group Reference Product R5F100xxx R5F101xxx RL78 G13 User s Manual Hardware D t Rev 1 00 All lot ocument R01UH0146EJ0100 Sep 2011 This document describes misstatements found in the RL78 hardware user s manual Rev 1 00 RO1UH0146EJ0100 Corrections User s Manual Applicable Page Applicable Item Contents Pages 5 988 Industrial applications and extended temperature Bisducte reloaded products released Incorrect descriptions of recommended connection inc rrectdesciibtions Page 93 of unused pins of P60 to P63 in table2 3 in pin p revised functions chapter revised Incorrect descriptions of 7 4 2 Shifting to Page 449 HALT STOP mode after starting operation in real time clock chapter revised Pages 308 860 Incorrect descriptions of reset processing Incorrect descriptions revised Incorrect descriptions 861 864 to 867 z c 871 872 883 884 time standby mode release time revised revised Pages 493 494 Explanations of when using SNOOZE mode in A D Explanations add
28. Oscillators Parameters Conditions High speed on chip 1 8 V lt Vio lt 5 5 V 32 MHz selected 31 52 Note oscillator clock frequency 24 MHz selected 23 64 Omitted 1 6 V lt Voo lt 1 8 V 32 MHz selected 30 24 32 00 24 MHz selected 22 68 24 00 Omitted Note This only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time 29 2 2 On chip oscillator characteristics TA 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Oscillators Parameters Conditions High speed on chip oscillator clock frequency High speed on chip oscillator 20 to 85 C 1 8 V lt Vpp lt 5 5 V clock frequency accuracy EUN 40 to 20 C 1 8 V lt Vpp lt 5 5 V 1 6 VxVop 1 8 V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits 0 to 3 of option byte 000C2H 010C2H and bits 0 to 2 of HOCODIV register 2 This indicates the oscillator characteristics only Refer to AC Characteristics for instruction execution time Re Page 69 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Issued Document History RL78 G13 Incorrect description notice issued document history Document Number TN RL A001A E TN RL A001B E
29. TN RL A001C E Issue Date Dec 5 2011 Dec 21 2011 Mar 27 2012 Description First edition issued Incorrect descriptions of No 1 to No 10 revised Rev 2 00 issued Revisions of No 11 to No 14 incorrect descriptions added Rev 3 00 issued Revisions of No 15 to No 22 incorrect descriptions added This notification Re Page 70 of 70 sE NESAS
30. addition the converted values of the other channels may also be affected When internal reference voltage 1 45 V is selected reference voltage source for the side of the A D converter do not input internal reference voltage or higher voltage to a pin selected by the ADS register However it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage Correct 11 10 Cautions for A D Converter 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins Observe the rated range of the ANIO to ANI14 and ANI16 to ANI26 pins input voltage If a voltage of Voo and AVrerp or higher and Vss and AVREFM or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected When internal reference voltage 1 45 V is selected reference voltage source for the side of the A D converter do not input internal reference voltage or higher voltage to a pin selected by the ADS register However it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage Caution The internal reference voltage 1 45 V can be selected only in HS high speed main mode Re Page 43 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 12 Explanations of A D test function
31. alue of 1 to 12 decimal and indicates the count value of months It counts up when the day counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the day count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 12 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The MONTH register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Correct 10 Month count register MONTH The MONTH register is an 8 bit register that takes a value of 1 to 12 decimal and indicates the count value of months It counts up when the day counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the day count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 12 to this register in BCD code The MONTH register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Re Page 11 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect description of year count regis
32. clock deleted page 443 Incorrect 9 Week count register WEEK The WEEK register is an 8 bit register that takes a value of 0 to 6 decimal and indicates the count value of weekdays It counts up in synchronization with the day counter When data is written to this register it is written to a buffer and then to the counter up to 2 clocks fRrc later Set a decimal value of 00 to 06 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The WEEK register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 9 Week count register WEEK The WEEK register is an 8 bit register that takes a value of 0 to 6 decimal and indicates the count value of weekdays It counts up in synchronization with the day counter When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Set a decimal value of 00 to 06 to this register in BCD code The WEEK register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Re Page 10 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect description of month count register MONTH in real time clock deleted page 444 Incorrect 10 Month count register MONTH The MONTH register is an 8 bit register that takes a v
33. d e When ADREFP1 or ADREFPO bit is rewritten this must be configured in accordance with the following procedures 1 Set ADCE 0 2 Change the values of ADREFP1 and ADREFPO 3 Stabilization wait time A 4 Set ADCE 1 5 Stabilization wait time B When ADREFP1 and ADREFPO are set to 1 and 0 the setting is changed to A 5 ws B 1 ws When ADREFP1 and ADREFPO are set to 0 and 0 or 0 and 1 A needs no wait and B 1 4 s After 5 stabilization time start the A D conversion When ADREFP1 and ADREFPO are set to 1 and 0 respectively A D conversion cannot be performed on the temperature sensor output and internal reference voltage output Be sure to perform A D conversion while ADISS 0 Specification of the SNOOZE mode Do not use the SNOOZE mode function Use the SNOOZE mode function When there is a hardware trigger signal in the STOP mode the STOP mode is exited and A D conversion is performed without operating the CPU the SNOOZE mode The SNOOZE mode function can only be specified when the high speed on chip oscillator clock is selected for the CPU peripheral hardware clock fc k If any other clock is selected specifying this mode is prohibited Using the SNOOZE mode function in the software trigger mode or hardware trigger no wait mode is prohibited Using the SNOOZE mode function in the sequential conversion mode is prohibited When using the SNOOZE mode function specify a hardware trigger interval of a
34. ed 526 converter chapter added p Pages 631 633 Caution of when using SNOOZE mode in serial 658 659 661 array unit chapter added Caution added Page 938 HR of data flash in flash memory chapter Explanations added Page 983 Spec of on chip oscillator characteristics in electrical Spec confirmed specifications chapter confirmed Incorrect Bold with underline Correct Gray hatched Document Improvement The above corrections will be made for the next revision of the hardware user s manual around March 2012 Contact a Renesas Electronics sales department details on the publishing schedule c 2012 Renesas Electronics Corporation All rights reserved Page 1 of 70 aQENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Corrections in the hardware user s manual OT Document No ROTUH0146JJ0200 ROTUH0146EJ0200 Incorrect descriptions of 64 pin plastic TOFP 7 x 7 deleted KE El ME real time clock deleted Explanations of interval timer control register ITMC added Explanations of timing chart when A D voltage comparator is used added Incorrect descriptions of A D conversion time selection there is stabilization wait time 6 8 to 8 8 revised standby mode added Incorrect descriptions of maskable interrupt request acknowledgment operation Incorrect descriptions of voltage detector LVD timing chart revised LVD interrupt and reset mode revised Number 4 of Supply current characteristics in
35. eference voltage Vss Parameter Conditions Resolution Overall errorNoetes 1 2 10 bit resolution 1 8V lt VDpD lt 5 5V 1 6V lt Vpp lt 5 5V Conversion time Zero scale error s 1 2 Omitted Full scale error 1 2 Integral linearity error e Differential linearity error Note 1 Analog input voltage ANIO to ANI14 ANI16 to ANI26 24V lt Vpp lt 5 5V HS mode Omitted Re Page 51 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Condition of 4 When AVREF Internal reference voltage AVREF AVREFM ANI1 target ANI ANIO to ANI14 ANI16 to ANI26 added page 1035 Incorrect 4 When AVREF Internal reference voltage ADREFP1 1 ADREFPO 0 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 1 6 V x EVppo EVpp1 x Von x 5 5 V Vss EVsso EVss1 0 V Reference voltage Vacr Reference voltage AVrerm 0 V Parameter Conditions Resolution Conversion time 8 bit resolution 2 4 V lt VoD lt 5 5 V Zero scale errorNotes 1 2 8 bit resolution 2 4 V lt VDD lt 5 5V Integral linearity errorNoete 8 bit resolution 2 4 V lt VDD lt 5 5 V Differential linearity error ete 8 bit resolution 2 4V lt VpD lt 5 5V Reference voltage VBGR Reference voltage AVREFM Analog input voltage VAN
36. equest acknowledgment timing maximum time revised page 844 Incorrect Figure 16 9 Interrupt Request Acknowledgment Timing Maximum Time 6 clocks 6 clocks i PSW and PC saved interrupt servicing CPU processing Instruction RET instruction jump to interrupt OG servicing prog xxIF MEN FRE 14 clocks Remark 1 clock 1 fcik fcu CPU clock Correct Figure 16 9 Interrupt Request Acknowledgment Timing Maximum Time 8 clocks 6 clocks A Instruction immediately PSW and PC saved Interrupt servicing m 16 clocks Remark 1 clock 1 fc k fcuk CPU clock Re Page 25 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 8 Incorrect descriptions of voltage detector LVD timing chart revised Figure 21 4 Incorrect descriptions of timing of voltage detector internal reset signal generation revised page 894 Incorrect Figure 21 4 Timing of Voltage Detector Internal Reset Signal Generation Option Byte LVIMDS1 LVIMDSO 1 1 Supply voltage Voo Vivi VPOR 1 51 V TYP VPpR 1 50 V TYP LVIMK flag set by software LVISEN flag T ME E LVIF flag E MN cleared LVIOMSK flag LVIMD flag LVILV flag LVIRF flag LVD reset signal Cleared by Cleared by 1 Cleared by 1 software l software software 1 POR reset signal Internal reset signal Notes 1 The LVIMK flag is set to 1 by reset s
37. ernal reset signal Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 LVIRF flag is bit 0 of the reset control flag register RESF The LVIRF flag ma come 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION Re Page 28 of 70 s lt E NESAS Date April 6 2012 RENESAS TECHNICAL UPDATE TN RL A001C E c 2 0 t 0 O t S CD en 5 E 0 2 Ve c wi 0 O po O o 2 0 a oO D o 2 O gt Yy o D amp He N o 3 D LL 0 1 Option Byte LVIMDS1 LVIMDSO Supply voltage VoD Vpor 1 51 V TYP VEDR 1 50 V TYP c r d LVIMK flag interrupt mask set by software Cleared by software LVIF flag LVIMD flag LVILV flag LVIIF flag LVD reset signal POR reset signal Internal reset signal The LVIMK flag is set to 1 by reset signal generation Note Page 29 of 70 RENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 9 Incorrect description of voltage detector LVD interrupt and reset mode revised Incorrect description of when used as interrupt and reset mode revised page 897 Incorrect 21 4 3 When used as interrupt and reset mode e When starting operation Specify the operation mode the interrupt and r
38. eset LVIMDS1 LVIMDSO 1 0 and the detection voltage Vivi ViviL by using the option byte 000C1H 010C1H Omitted ution The LVIRE flag may become 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION Correct 21 4 3 When used as interrupt and reset mode e When starting operation Specify the operation mode the interrupt and reset LVIMDS1 LVIMDSO 1 0 and the detection voltage Vivi ViviL by using the option byte 000C1H 010C1H Omitted Figures 21 6 shows the timing of voltage detector reset signal and interrupt signal generation Perform the processing according to figure 21 7 Processing procedure after an interrupt is generated and figure 21 8 Initial setting of interrupt and reset mode Re Page 30 of 70 sE NESAS Date April 6 2012 RENESAS TECHNICAL UPDATE TN RL A001C E eneration revised c O 2 il un o xe c c LZ 7 2 o o o o xe o o gt o E o c o 5 o 7 o xe o o pn p o o Incorrect Figure 21 6 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation Option Byte LVIMDS1 LVIMDSO 1 0 Supply voltage VoD LVIMK flag set by software N Cleared by software Normal Normal operation operation Operation status Save processing LVIF flag LVISEN flag set by software LVIOMSK fla
39. flows This counter counts as follows Omitted When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the hour count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 31 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The DAY register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Correct 8 Day count register DAY The DAY register is an 8 bit register that takes a value of 1 to 31 decimal and indicates the count value of days It counts up when the hour counter overflows This counter counts as follows Omitted When data is written to this register it is written to a buffer and then to the counter up to 2 clocks fRTc later Even if the hour count register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 01 to 31 to this register in BCD code The DAY register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 01H Re Page 9 of 70 s lt E NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect description of week count register WEEK in real time
40. g LVIMD flag LVILV flag LVIRF flag Cleared LVD reset signal Cleared by software Cleared by software POR reset signal Internal reset signal LVIIF flag Page 31 of 70 RENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 LVIRE flag is bit 0 of the reset control flag register RESF The LVIRE flag may become 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION Remark Vror POR power supply rise detection voltage Vppr POR power supply fall detection voltage R Page 32 of 70 sKENESAS Date April 6 2012 RENESAS TECHNICAL UPDATE TN RL A001C E e oO RI o o O es En 0 o 2 o Oo e c E 0 o o na o O o o a o e E o gt o c E G N o ES gt 2 LL e e 1 o ip Q gt Z D Q gt Z o Ss m c Q If a reset is not generated after releasing the mask determine that a condition of VD becomes VDD gt VLVIH clear LVIMD and the MCU returns to normal operation Supply voltage VoD Vpor 1 51 V TYP VPoR 1 50 V TYP LVIMK flag set by software are Cleared by software Cleared by softw Wait for stabilization by software 400 hs or 5 clocks of fiL Note 3 Normal operation
41. gnal see Figure 16 1 2 STOP mode release time Supply of the clock is stopped 18 96 ws to whichever is longer 28 95 ws and the oscillation stabilization time set by OSTS Wait e When vectored interrupt servicing is carried out 10 to 11 clocks e When vectored interrupt servicing is not carried out 4 to 5 clocks Figure 18 5 STOP Mode Release by Interrupt Request Generation 2 2 2 When high speed system clock external clock input is used as CPU clock Interrupt request STOP instruction Standby release signal Note 1 STOP mode release time ete Normal operation m Normal operation high speed Supply of the high speed 4 Wait Status of CPU system clock STOP mode clock is stopped system clock High Speed Oscillates Oscillation stopped Oscillates System clock X1 oscillation 3 When high speed on chip oscillator clock is used as CPU clock Omitted Notes 1 For details of the standby release signal see Figure 16 1 2 STOP mode release time Supply of the clock is stopped 19 08 to 32 99 ws Wait e When vectored interrupt servicing is carried out 7 clocks e When vectored interrupt servicing is not carried out 1 clock Re Page 62 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Explanations of SNOOZE mode shift time added p 867 Incorrect 18 2 3 SNOOZE mode 1 SNOOZE mode setting and operating statuses Omitted Cor
42. he four hannels the clock request signal remains at the high level and the A D converter switches from the SNOOZE mode to the normal eration mode To stop the high speed on chi cillator clock supplied while in the NOOZE mode clear bit 2 AWC of A D converter mode register 2 ADM2 to 0 Doing this sets the clock request signal an internal signal to the low level and stops the supply of the high speed on chi scillator clock Correct 1 If an interrupt is generated after A D conversion ends Omitted e While in the select mode When A D conversion ends and an A D conversion end interrupt request signal INTAD is generated the A D converter returns to normal operation mode from SNOOZE mode At this time be sure to clear bit 2 AWC 0 SNOOZE mode release of the A D converter mode register 2 ADM2 If the AWC bit is left set to 1 A D conversion will not start normally in the subsequent SNOOZE or normal operation mode e While in the scan mode If even one A D conversion end interrupt request signal INTAD is generated during A D conversion of the four channels the clock request signal remains at the high level and the A D converter switches from the SNOOZE mode to the normal operation mode At this time be sure to clear bit 2 AWC 0 SNOOZE mode release of A D converter mode register 2 ADM2 to O If the AWC bit is left set to 1 A D conversion will not start normally in the subsequent SNOOZE or normal operation mode
43. his setting value can be selected only in HS high speed main mode Omitted Re Page 40 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 input channel specification register ADS added Incorrect Figure 11 11 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVrerm pin Setting prohibited Temperature sensor output Internal reference voltage Other than the above Setting prohibited 1 20 24 25 30 32 pin products PO1 ANI16 pin 2 20 24 25 30 32 pin products POO ANI17 pin Correct Figure 11 11 Format of Analog Input Channel Specification Register ADS 1 2 O Select mode ADMD 0 ADSO Analog input Input source channel P20 ANIO AVnere pin P21 ANI1 AVrerm pin Omitted 1 Setting prohibited 0 Temperature sensor output Internal reference voltage output 1 45 V e Other than the above Setting prohibited Notes 1 20 24 25 30 32 pin products PO1 ANI16 pin 2 20 24 25 30 32 pin products POO ANI17 pin 3 This setting value can be selected only in HS high speed main mode Re Page 41 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Explanation of 11 7 4 Setup when using temperature sensor added page 52
44. ignal generation 2 LVIRF flag is bit 0 of the reset control flag register RESF The LVIRF flag may become 1 from the beginning due to the power on waveform For details of the RESF register see CHAPTER 19 RESET FUNCTION Re Page 26 of 70 s lt E NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct Figure 21 4 Timing of Voltage Detector Internal Reset Signal Generation Option Byte LVIMDS1 LVIMDSO 1 1 Supply voltage VoD Vii VPoRz 1 51 V TYP VPDR 1 50 V TYP Cleared LVIF flag LVIMD flag i i 1 1 Not cleared Not cleared LVILV flag T Not cleared Not cleared LVIRF flag RESF register LVD reset signal Cleared by Cleared by software i software POR reset signal Internal reset signal Re Page 27 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Figure 21 5 Incorrect description of voltage detector internal interrupt signal generation timing revised page 896 Incorrect Figure 21 5 Timing of Voltage Detector Internal Interrupt Signal Generation Option Byte LVIMDS1 LVIMDSO 0 1 Supply voltage Von Vivi VPOR 1 51 V TYP VPDR 1 50 V TYP LVIMK flag set by software Cleared by Software LVISEN flag Cleared LVIF flag LVIOMSK flag LVIMD flag LVILV flag INTLVI LVIIF flag LVIRF flag LVD reset signal Cleared by software POR reset signal Int
45. it resolution 1 8 V lt VpD lt 5 5V AVRerp Vpp 16V Vop 5 5 V Overall error Conversion time Zero scale errorNotes 1 2 Omitted Full scale error e 1 2 Integral linearity error e Differential linearity error Note 1 Reference voltage AVREFP Analog input voltage VAN VBGR 24V lt Vop lt 5 5 V Omitted Re Page 46 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct 1 When AVREF AVrerP ANIO ADREFP1 0 ADREFPO 1 AVREF AVREFMANI1 ADREFM 1 target ANI pin ANI2 to ANI14 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage AVREFP Reference voltage AVrerm 0 V Parameter Conditions Resolution ee 10 bit resolution 1 8V lt VDpD lt 5 5V AVRerp Vpp 1 6V lt Vpp lt 5 5V Overall error Conversion time Zero scale errorNotes 1 2 Omitted Full scale error e 1 Integral linearity error e Differential linearity error Note Reference voltage AVREFP Analog input voltage VAN VBeGR 2 4V lt Vpp lt 5 5V HS mode Omitted Re Page 47 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Condition of 2 When AVREF AVREFP ANIO AVREF AVREFM ANI1 target ANI pin ANI16 to ANI26 added
46. k 2 Note Omitted Re Page 18 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct Table 11 3 A D Conversion Time Selection 6 8 6 2 7V lt VDD lt 3 6 V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 Conversion Time Selection ADMO CLK fcLk fcLK CLK fcLk FR2 FR1 FRO LV1 LV0 2 MHz 4 MHz 8 MHz 16 MHz 32 MHz i 54 us Setti Sening n i nd etting ns ibi prohibited DS 54ns 27 us fy32 Setting 54 us 27 hs fcuw 16 40 5us 20 25 hs 10 125 us 5 0625 us fcuw6 Conversion Clock fAD 3375us 16 875 us 8 4375 hs fcuw5 6 75 us prohibited 54 us 27us 13 5 us HS Setting foux 2 prohibited Setting prohibited Setting Setting prohibited prohibited 29s tena Setting 50us 25us fcuk 16 etting a 375us 1875us 9 375 us 4 6875 us fax 6 3125 us 15 625 us 7 8125 us fads prohibited 50 us 25us 125us 625ys Setting foux 2 prohibited Settin Setting 9 42us foux 64 Setting oe prohibited prohibited 21 ii prohibited 42 us us CL Setting Wis 42 us 21 us fcud 16 prohibited 1 boul prohibited 42 us 21 us fcu 8 31 5 us fcuk 6 Settin 26 25 hs Setting hes fcud5 Setting prohibited prohibited 21 uS prohibited fouxl4 42 us 21 us Setting isl prohibited Setting Setting SS ps fcuw64 Setting ne prohibited prohibited 38 us 19 m
47. n Name I O Circuit Type Recommended Connection of Unused Pins Omitted P60 SCLAO Input Independently connect to EVppo EVpp or EVsso EVss P61 SDAAO via a resistor P62 SCLA1 Output Leave open P63 SDAA1 P64 TI10 TO10 P65 TI 1 TO11 P66 TI12 TO12 P67 T113 TO13 Correct Table 2 3 Connection of Unused Pins 128 pin products 2 4 Pin Name I O Circuit Type Recommended Connection of Unused Pins Omitted P60 SCLAO Input o Independently connect to EVppo EVpp or EVsso EVss P61 SDAAO via a resistor Output Set the port s output latch to 0 and leave the pins open or set the port s output latch to 1 and independently P63 SDAA1 connect the pins to EVopo and EVpp1 or EVsso and EVss via a resistor P62 SCLA1 P64 TI10 TO10 Input Independently connect to EVppo EVpp1 or EVsso EVss1 P65 TI11 TO11 via a resistor Output Leave open P66 TI12 TO12 P67 T113 TO13 Re Page 56 of 70 s lt E NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 17 Incorrect descriptions of 7 4 2 Shifting to HALT STOP mode after starting operation in real time clock chapter revised p 449 Incorrect 7 4 2 Shifting to STOP mode after starting operation Perform one of the following processing when shifting to STOP mode immediately after setting the RTCE bit to 1 However after setting the RTCE bit to 1 this processing is not required when shifting
48. n stabilization wait time tame Correct 29 7 2 Temperature sensor characteristics Ta 40 to 85 C 2 4 V lt Voo lt 5 5 V Vss EVsso EVss 0 V HS high speed main mode Parameter Conditions Temperature sensor output voltage Vrweszs Setting ADS register 80H TA 25 C Reference output voltage Vconst Setting ADS register 81H Temperature coefficient FvrvPs Temperature sensor that depends on the temperature Operation stabilization wait time tame Re Page 53 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 15 Industrial applications and extended temperature products released Industrial applications and extended temperature products released Page 54 of 70 RENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 IOH spec of products for industrial application in DC characteristics of ELECTRICAL SPECIFICATIONS added p 988 Incorrect 29 4 1 Pin characteristics TA 40 to 85 C 1 6 V x EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Conditions Output current Per pin for POO to P07 P10 to P17 1 6 V lt EVbppo lt 5 5 V high P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Omitted Total of all pins 1 6 V lt EVppo lt 5 5 V When duty 709 Note 3 Per pin for P20 to P27 P
49. or 1 Reference voltage AVREFP Analog input voltage VAN 24V lt Vpp lt 5 5V HS mode Omitted Re Page 49 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Condition of 3 When AVREF VDD AVREF VSS target ANI pin ANIO to ANI14 ANI16 to ANI26 added page 1034 Incorrect 3 When AVREF Voo ADREFP1 0 ADREFPO 0 AVrer Vss ADREFM 0 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpn1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage Vpn Reference voltage Vss Parameter Resolution Conditions Overall errorNoetes 1 2 10 bit resolution 1 8 V lt Voo lt 5 5 V 1 6 V lt VoD lt 5 5 V Conversion time Zero scale errorNotes 1 2 Full scale error 1 2 Integral linearity error e Differential linearity error 1 Omitted Analog input voltage ANIO to ANI14 ANI16 to ANI26 24V lt Von lt 5 5 V Omitted Re Page 50 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct 3 When AVREF Voo ADREFP1 0 ADREFPO 0 AVREF Vss ADREFM 0 target ANI pin ANIO to ANI14 ANI16 to ANI26 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Reference voltage Voo R
50. ounted R5F100LGAFA R5F100LHAFA R5F100LJAFA R5F100LKAFA R5F100LLAFA 64 pin plastic LQFP 12x12 R5F101LCAFA R5F101LDAFA R5F101LEAFA R5F101LFAFA ot R5F101LGAFA R5F101LHAFA R5F101LJAFA R5F101LKAFA mounted R5F101LLAFA R5F100LCAFB R5F100LDAFB R5F100LEAFB R5F100LFAFB Mounted R5F100LGAFB R5F100LHAFB R5F100LJAFB R5F100LKAFB N 64 pin plastic LQFP fine pitch RSF100LLAFB R5F101LLAFB i R5F100LCABG R5F100LDABG R5F100LEABG R5F100LFABG ounte R5F100LGABG R5F100LHABG R5F100LJABG 64 pin plastic FBGA 4 x 4 i o Not R5F101LCABG R5F101LDABG R5F101LEABG R5F101LFABG mounted 10 x 10 R5F101LCAFB R5F101LDAFB R5F101LEAFB R5F101LFAFB ot R5F101LGAFB R5F101LHAFB R5F101LJAFB R5F101LKAFB mounted R5F101LGABG R5F101LHABG R5F101LJABG Re Page 4 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Pin configuration of 64 pin plastic TQFP 7 x 7 deleted page 17 Incorrect 1 3 11 64 pin products 64 pin plastic LQFP 12 x 12 64 pin plastic LQFP fine pitch 10 x 10 64 pin plastic TQFP fine pitch 7 x 7 Omitted Correct 1 3 11 64 pin products 64 pin plastic LQFP 12 x 12 64 pin plastic LQFP fine pitch 10 x 10 Omitted Package drawings of 64 pin plastic TQFP 7 x 7 deleted page 1055 Incorrect R5F100LCAFC R5F100LDAFC R5F100LEAFC R5F100LFAFC R5F100LGAFC R5F100LHAFC R5F100LJAFC R5F101LCAFC R5F101LDAFC R5F101LEAFC R5F101LFAFC R5F
51. ow voltage mode AVREFP VDD 3 0 V icant Io NIE A D converter ADREF reference voltage current Temperature sensor operating current LVD operating T current BGO operating ipgo 35 current Note Omitted Re Page 39 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 11 Explanations when using temperature sensor and internal reference voltage 1 45 V of A D converter added Explanation of Figure 11 7 A D converter mode register 2 ADM2 added page 493 Incorrect Figure 11 7 Format of A D Converter Mode Register 2 ADM2 1 2 Address F0010H After reset 00H R W Symbol 7 6 5 4 lt 3 gt lt 2 gt 1 0 ADM2 ADREFP1 ADREFPO ADREFM ADRCK awc o ADTYP ADREFP1 ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Vpn Supplied from P20 AVRerp ANIO Supplied from the internal reference voltage 1 45 V Setting prohibited Omitted Omitted Correct Figure 11 7 Format of A D Converter Mode Register 2 ADM2 1 2 Address F0010H After reset 00H R W Symbol 7 6 5 4 lt 3 gt lt 2 gt 1 lt 0 gt ADM2 ADREFP1 ADREFPO ADREFM ADRCK awc o ADTYP ADREFP1 ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Vpn Supplied from P20 AVrerr ANIO Supplied from the internal reference voltage 1 45 V Setting prohibited Omitted Note T
52. prohibited i us cL Bug oe 38us 19ys fex 46 prohibited LOW prohibited 38 us 19 hs fox 8 1 1 Voltage 2 cece foux 6 Setting 23 75us T Setting prohibited fork 5 o prohibited 1995 prohibited fcud4 38 us 19 us Setting um prohibited Page 19 of 70 RENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct Table 11 3 A D Conversion Time Selection 7 8 7 1 8V lt VpD lt 2 7V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 ADMO Conversion Time Selection fCLK fcLk fcLk fcLk fcLk fcLK o FR2 FR1 FRO tvi iv Vede 1 MHz 2 MHz 4 MHz 8 MHz 16 MHz 32 MHz Normal X X X 1 Setting prohibited Normal x X X 1 2 Setting prohibited Setti Setting 9 42us fcuo64 Setting prohibited prohibited Setting pone 42 us Mus hs 10416 prohibited Low prohibited 42 us 21 ps fcLk 8 Voltage 1 31 5 us fcu 6 26 25 us 42us 21us foul4 s s prohibited Setti mee NE 9 fcud2 prohibited o Lr e a Setting Setting 38 us fcuW 64 Setting prohibited prohibited prohibited foux 32 Mes zu 4 4 Low prohibited fcuk 8 Voltage 2 feik 6 i feik 5 19 us prohibited prohibited fcuk 4 prohibited Note Omitted Re Page 20 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct Table 11 3 A D Conversion Time Selection 8 8 8
53. rect 18 2 3 SNOOZE mode 1 SNOOZE mode setting and operating statuses Omitted In SNOOZE mode transition wait status to be only following time From STOP to SNOOZE HS High speed main mode 18 96 to 28 95 ws LS Low speed main mode 20 24 to 28 95 ws LV Low voltage main mode 20 98 to 28 95 ws From SNOOZE to normal operation e When vectored interrupt servicing is carried out HS High speed main mode 6 79 to 12 4 ws 7 clocks LS Low speed main mode 2 58 to 7 8 us 7 clocks LV Low voltage main mode 12 45 to 17 3 us 7 clocks e When vectored interrupt servicing is not carried out HS High speed main mode 6 79 to 12 4 ws 1 clock LS Low speed main mode 2 58 to 7 8 ws 1 clock LV Low voltage main mode 12 45 to 17 3 us 1 clock Re Page 63 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 19 Explanations of when using SNOOZE mode in A D converter chapter added Explanations of A D converter mode register 2 ADM2 added p 493 494 Incorrect 4 A D converter mode register 2 ADM2 Omitted ADREFP1 ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Vpn Supplied from P20 AVRerp ANIO Supplied from the internal reference voltage 1 45 V 1 Setting prohibited When ADREFP1 or ADREFPO bit is rewritten this must be configured in accordance with the following procedures 1 Set ADCE 0 2 Change the values
54. rrect Figure 11 4 Timing Chart When A D Voltage Comparator Is Used A D voltage comparator enables operation AID voltage comparator Y aw Conversion Conversion Conversion Conversion a standby MES operation standby stopped Software trigger mode 4 Note 1 t 1 is written 0 is written to ADCS to ADCS ADCS Conversion Trigger JL malin Conversion Conversion standby Standby operation standby 7 stopped Hardware trigger no waitmode DCS a 1 is written 0 is written Conversion Conversion Conversion Conversion i standby operation standby stopped Hardware trigger ADCS wait mode 0 is written to ADCS Note 1 Omitted 2 The following time is the maximum amount of time necessary to start conversion ADMO Conversion FR2 Clock Software trigger mode Hardware trigger wait mode fap Hardware trigger no wait mode lol ww lola wee a halal sue lal we 7 O jojo ola mus rr ala Remark fcLK CPU peripheral hardware clock frequency 1 1 1 1 1 1 1 RE Page 15 of 70 sKENESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 5 Incorrect descriptions of Table 11 3 A D Conversion Time Selection 6 8 to 8 8 when there is stabilization wait time pages 489 to 491 Incorrect Table 11 3 A D Conversion Time Selection 6 8 6 2 7V lt V
55. t least shift time to SNOOZE mode Nore A D power supply stabilization wait time A D conversion time 2 fci clock Even when using SNOOZE mode be sure to set the AWC bit to 0 in normal operation mode and change it to 1 just before shifting to STOP mode Also be sure to change the AWC bit to 0 after returning from STOP mode to normal operation mode If the AWC bit is left set to 1 A D conversion will not start normally in spite of the subsequent SNOOZE or normal operation mode Refer to From STOP to SNOOZE in 18 2 3 SNOOZE mode Re Page 65 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Explanations of SNOOZE mode related to A D converter added p 526 Incorrect 1 If an interrupt is generated after A D conversion ends Omitted e While in the select mode After A D conversion ends and the A D conversion end interrupt request signal INTAD is generated the clock request signal remains at the high level and the A D converter switches from the SNOOZE mode to the normal operation mode To stop the high speed on chip oscillator clock supplied while in the SNOOZE mode clear bit 2 AWC of A D converter mode register 2 ADM2 to 0 Doing this sets the clock request signal an internal ignal to the low level and stops the supply of the high speed on chip oscillator clock e While in the scan mode If even one A D conversion end interrupt request signal INTAD is generated durin D conversion of t
56. ten value of the RINTE bit is reflected or wait that more than one clock of the count clock has elapsed after returned from standby mode Then enter standby mode 4 Only change the setting of the ITCMP11 to ITCMPO bits when RINTE 0 However it is possible to change the settings of the ITCMP11 to ITCMPO bits at the same time as when changing RINTE from 0 to 1 or 1 to O Re Page 13 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 4 Added Explanations of timing chart when A D voltage comparator is used page 483 Incorrect Figure 11 4 Timing Chart When A D Voltage Comparator Is Used 1 A D voltage comparator enables operation ADCE A D voltage comparator Conversion stopped Conversion Conversion Conversion standby operation standby Software ancs trigger mode Note t 1 is written 0 is written to ADCS to ADCS Conversion stopped Conversion Trigger Conversion Conversion standby standby operation standby Hardware trigger ADCS no wait mode Note Hardware trigger detection i 1 is written 0 is written to ADCS to ADCS Conversion Stabilization Conversion Conversion Conversion 7 standby waittims operation standby 7 stopped Hardware trigger ADCS i wait mode 1 i Hardware trigger 0 is written detection to ADCS Note Omitted Re Page 14 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Co
57. ter YEAR in real time clock deleted page 444 Incorrect 11 Year count register YEAR The YEAR register is an 8 bit register that takes a value of 0 to 99 decimal and indicates the count value of years It counts up when the month count register MONTH overflows Values 00 04 08 92 and 96 indicate a leap year When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the MONTH register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 00 to 99 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period The YEAR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Correct 11 Year count register YEAR The YEAR register is an 8 bit register that takes a value of 0 to 99 decimal and indicates the count value of years It counts up when the month count register MONTH overflows Values 00 04 08 92 and 96 indicate a leap year When data is written to this register it is written to a buffer and then to the counter up to 2 clocks frtc later Even if the MONTH register overflows while this register is being written this register ignores the overflow and is set to the value written Set a decimal value of 00 to 99 to this regis
58. ter in BCD code The YEAR register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Re Page 12 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 3 Caution of interval timer control register ITMC in 12 bit interval timer added Incorrect 3 Interval timer control register ITMC Omitted Cautions 1 Before changing the RINTE bit from 1 to 0 use the interrupt mask flag register to disable the INTIT interrupt servicing When the operation starts from 0 to 1 again clear the ITIF flag and then enable the interrupt servicing 2 The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit 3 Only change the setting of the ITCMP11 to ITCMPO bits when RINTE 0 However it is possible to change the settings of the ITCMP11 to ITCMPO bits at the same time as when changing RINTE from 0 to 1 or 1 to 0 Correct 3 Interval timer control register ITMC Omitted Cautions 1 Before changing the RINTE bit from 1 to O use the interrupt mask flag register to disable the INTIT interrupt servicing When the operation starts from 0 to 1 again clear the ITIF flag and then enable the interrupt servicing 2 The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit 3 When setting the RINTE bit after returned from standby mode and entering standby mode again confirm that the writ
59. the data flash memory is provided below The data flash memory can be written to by using the flash memory programmer or an external device Programming is performed in 8 bit units Blocks can be deleted in 1 KB units The only access by CPU instructions is byte reading reading four clock cycles Omitted Correct An overview of the data flash memory is provided below The data flash memory can be written to by using the flash memory programmer or an external device Programming is performed in 8 bit units Blocks can be deleted in 1 KB units The only access by CPU instructions is byte reading 1 clock cycle wait 3 clock cycles Omitted When data flash is accessed the CPU waits for three clock cycles Re Page 68 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 22 Spec of On chip oscillator characteristics in electrical specifications chapter confirmed p 983 Incorrect 29 3 2 On chip oscillator characteristics TA 20 to 85 C 1 6 V x EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Oscillators Parameters Conditions High speed on chip 1 8 V lt Voo lt 5 5 V 32 MHz selected 31 68 Note oscillator clock frequency 24 MHz selected 23 76 Omitted 1 6 V lt Voo lt 1 8 V 32 MHz selected 30 40 32 00 24 MHz selected 22 80 24 00 Omitted TA 40 to 85 C 1 6 V lt EVppo EVpp1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V
60. to STOP mode after the INTRTC interrupt has occurred e Shifting to STOP mode when at least two input clocks frtc have elapsed after setting the RTCE bit to 1 see Figure 7 18 Example 1 e Checking by polling the RWST bit to become 1 after setting the RTCE bit to 1 and then setting the RWAIT bit to 1 Afterward setting the RWAIT bit to O and shifting to STOP mode after checking again by polling that the RWST bit has become O0 see Figure 7 18 Example 2 Figure 7 18 Procedure for Shifting to STOP Mode After Setting RTCE bit to 1 Example 1 Example 2 a m a Sets to counter operation Sets to counter operation start start Sets to stop the SEC to YEAR RWAIT 1 counters reads the counter value write mode N RWST 1 Checks the counter wait status o Yes RWAIT 0 Sets the counter operation gt e meer Yes STOP i Waiting at least for 2 frtc clocks Re Page 57 of 70 sE NESAS RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Correct 7 4 2 Shifting to HALT STOP mode after starting operation Perform one of the following processing when shifting to HALT STOP mode immediately after setting the RTCE bit to 1 However after setting the RTCE bit to 1 this processing is not required when shifting to HALT STOP mode after the INTRTC interrupt has occurred e Shifting to HALT STOP mode when at least two input clocks frtc have
61. to set the high voltage detection level VLVIH Set the LVISEN bit to 0 to enable voltage detection The MCU returns to normal operation when internal reset by voltage detector LVD is not generated since a condition of VDD becomes VoD gt VLVIH Set the LVISEN bit to 1 to mask voltage detection LVIOMSK 1 Set the LVIMD bit to 0 to set interrupt mode Set the LVISEN bit to 0 to enable voltage detection Page 37 of 70 RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Figure 21 8 Explanations of initial setting of interrupt and reset mode added When setting an interrupt and reset mode LVIMDS1 LVIMDSO 1 0 voltage detection stabilization wait time for 400 us or 5 clocks of flL is necessary after LVD reset is released LVIRF 1 After waiting until voltage detection stabilizes 0 clear the LVIMD bit for initialization While voltage detection stabilization wait time is being counted and when the LVIMD bit is rewritten set LVISEN to 1 to mask a reset or interrupt generation by LVD Figure 21 8 shows the procedure for initial setting of interrupt and reset mode Figure 21 8 Initial Setting of Interrupt and Reset Mode Power supply started Reset source Refer to Figure 21 9 Checking reset source determined Check internal reset generation by LVD circuit Set the LVISEN bit to 1 to mask voltage detection LVIOMSK 1 Voltage detection Count 400 us or 5 clocks of fiL by software
62. uk 32 fcLk 16 fcuk 8 fcuk 6 fcuk 5 fcuk 4 fcuk 2 fcLk 64 fcLk 32 fc x 16 fcuk 8 fcuk 6 fcuk 5 fcuk 4 fcuk 2 fcLk 64 fcux 32 fc x 16 fcuk 8 fcuk 6 fcuk 5 fcuk 4 fcuk 2 Page 17 of 70 RENESAS TECHNICAL UPDATE TN RL A001C E Date April 6 2012 Incorrect Table 11 3 A D Conversion Time Selection 8 8 8 1 6V lt Vpp lt 1 8V When there is stabilization wait time hardware trigger wait mode A D Converter Mode Register 0 Conversion Time Selection ADMO fcLK fcLK fcLKk FR2 FR1 FRO LV1 LV0 16 MHz 4 MHz 8 MHz Conversion Clock fAD Note 2 fcLx 64 feud 32 fou 16 Normal Setting Setting fc 8 1 prohibited prohibited prohibited prohibited prohibited prohibited fctw6 fcLk 5 fcuk 4 fcu 2 feu 64 feud 32 fcuk 16 Normal Setting Setting Setting fcu 8 2 prohibited prohibited prohibited prohibited prohibited prohibited fcu 6 ferk 5 fcuk 4 fcuk 2 Setti Setting 9 408 ps fcud64 Setting prohibited prohibite Setting prohibited 108 us ferk 32 prohibited fcuw16 Low Setting fctxw8 Voltage 1 Setting prohibited fc 6 Setting 2 Setting prohibited fok 5 AK prohibited Setting prohibited feud 4 Setting prohibited prohibited fcuk 2 fcuk 64 Setting Setting prohibited feud 32 prohibited feux 16 Setting fctk 8 prohibited fc x 6 Setting prohibited fcuk 5 Setting prohibited prohibited feLk 4 prohibited Setting prohibited fci

Correction for Incorrect Description Notice RL78/G13 Descriptions in

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