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Errata Sheet NG for P11

1. 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description write TBUF before the end of the last transmission end of the acknowledge bit is reached USIC 1 016 Transmit parameters are updated during FIFO buffer bypass Transmit Control Information TCI can be transferred from the bypass structure to the USIC channel when a bypass data is loaded into TBUF Depending on the setting of TCSR register bit fields different transmit parameters are updated by TCI When SELMD 1 PCR CTR 20 16 is updated by BYPCR SELO applicable only in SSC mode When WLEMD 1 SCTR WLE and TCSR EOF are updated by BYPCR BWLE When FLEMD 1 SCTR FLE 4 0 is updated by BYPCR BWLE When HPCMD 1 SCTR HPCDIR and SCTR DSM are updated by BHPC When all of the bits are 0 no transmit parameters will be updated However in the current device independent of the xxMD bits setting the following are always updated by the TCI generated by the bypass structure when TBUF is loaded with a bypass data WLE HPCDIR and DSM bits in SCTR register EOF and SOF bits in TCSR register PCR CTR 20 16 applicable only in SSC mode Workaround The application must take into consideration the above behaviour when using FIFO buffer bypass WDT X 002 Clearing the Internal Flag which Stores Preceding WDT Reset Request The information that the WDT has already been exceeded once is stored in a
2. 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description 003 2 2 0 and P10 12 0 Switch to Input During the execution of an Application Reset and Debug Reset the pins P2 2 0 and P10 12 0 are intermediately switched to input These pins return to their previous mode approximately 35 system clock cycles after the application reset counter has expired approx 0 6 us with default reset delay at 80 MHz If such a pin is used as output make sure that this short interruption does not lead to critical system conditions Workaround External pull devices can be added to have a defined level on these pins during Application and Debug Reset RESET X 004 Sticky Register Access Trap forces device into power save mode after reset The system control unit SCU provides trap generation to respond to certain system level events or faults Certain trap sources maintain sticky trap flags which are only cleared explicitly by software or by a power on reset These sticky trap flags are contained in the SCU register DMPMIT In case the Register Access Trap flag DMPMIT RAT becomes set but is not cleared before a debug internal application or application reset occurs then the microcontroller will reset but will fail to start up correctly The microcontroller start up software will detect that the sticky trap flag is set and will force the device into power save mode
3. 16 32 Bit Architecture XC2200H Derivatives 16 32 Bit Single Chip Microcontroller with 32 Bit Performance XC2000 Family High Line Errata Sheet V1 6 2013 03 Microcontrollers Edition 2013 03 Published by Infineon Technologies AG 81726 Munich Germany 2013 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the
4. Errata Sheet 73 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description 6 4 Documentation Updates EBC X D001 Visibility of Internal LXBus Cycles on External Address Bus EBC chapter Access Control to LXBus Modules receives the following correction In the first paragraph the term read mode is replaced by tri state mode The following is added Despite the above mentioned measures accesses to internal LXBus modules are to some extent reflected on the non multiplexed address pins A 23 0 of the external bus 1 During an internal LXBus access the external address bus is tri stated The switch to tri state mode occurs in the same cycle as the internal LXBus access This may induce residual voltage which can lead to undefined logic levels on the address bus pins Those in turn can cause unwanted switching activity on attached device input stages Therefore attached devices should be equipped with an input hysteresis filter to avoid unwanted switching activity 2 After an internal LXBus access is completed the address of the location accessed last on the LXBus becomes visible on the external address bus unless an external bus cycle immediately follows the LXBus cycle Due to this behavior switching activity on the address bus can be observed even if no external access is active Note A functional impact due to this behavior is not expected becau
5. Onan tale EEE AEE 60 ECC en 60 FlexRay 004 Eu ru e deus s 60 FlexR y AL H005 sisse Renee ee aes 61 FlexRay 006 61 FlexRay ALHO007 ee ERR 61 Fl xRay 009 2 5 62 GOPT12 ALHO01 EE PER Tq EP 62 GPT12b X H002 sik ende Rum a RR es 63 INT X HOO ien nee voce cee eee 64 INT X HO0A eee iaceo Rn de 64 MultiCAN 005 65 MultiCAN 006 65 MultiCAN 007 65 008 66 MultiCAN 2 dc RR Se eek eae 66 MultiCAN 003 67 MultiCAN 004 67 OCDS 003 68 1 4 68 _ 0 declined store 70 RIC X HO09 ello Rliscesemee mM eR br e 70 Errata Sheet 5 V1 6 2013 03 er 2200 Derivatives Infineon XC2000 Family Hi
6. are trademarks of Infineon Technologies AG We Listen to Your Comments Is there any information in this document that you feel is wrong unclear or missing Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Errata Sheet 7 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line 2 General General This Errata Sheet describes the deviations of the XC2200H Derivatives from the current user documentation Each erratum identifier follows the pattern Module Arch TypeNumber Module subsystem peripheral or function affected by the erratum Arch microcontroller architecture where the erratum was firstly detected Al Architecture Independent CIC Companion ICs TC TriCore X XC166 XE166 XC2000 Family XC8 XC800 Family none C166 Family Type category of deviation none Functional Deviation P Parametric Deviation H Application Hint D Documentation Update Number ascending sequential number within the three previous fields As this sequence is used over several derivatives including already solved deviations gaps inside this enumeration can occur This Errata Sheet applies to all temperature and frequency versions and to all memory size variants of this device unless explicitly noted otherwis
7. Detailed Errata Description FlexRay Al 087 After reception of a valid sync frame followed by a valid non sync frame in the same static slot the received sync frame may be 10 nored Description If in a static slot of an even cycle a valid sync frame followed by a valid non sync frame is received and the frame valid detection prt frame decoded on X of the DEC process occurs one sclk after valid frame detection of FSP process fsp val syncfr chx the sync frame is not taken into account by the CSP process devte xxs reg Scope The erratum is limited to the case where more than one valid frame is received in a static slot of an even cycle Effects In the described case the sync frame is not considered by the CSP process This may lead to a SyncCalcResult of MISSIMG TERM error flag SFS MRCS set As a result the POC state may switch to NORMAL PASSIVE or HALT or the Startup procedure is aborted Workaround Avoid static slot configurations long enough to receive two valid frames FlexRay AL088 A sequence of received WUS may generate redundant SIR WUPA B events Description If a sequence of wakeup symbols WUS is received all separated by appropriate idle phases a valid wakeup pattern WUP should be detected after every second WUS The E Ray detects a valid wakeup pattern after the second WUS and then after each following WUS Errata Sheet 30 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Fami
8. Detailed Errata Description The erratum is limited to noise that is seen only locally and that is detected in the time window between the end of a dynamic frame s DTS and idle detection CHIRP on X Effects In the described case the faulty node may not stop slot counting and may continue to transmit dynamic frames This may lead to a frame collision in the current dynamic segment Workaround None FlexRay 1 097 Loop back mode operates only at 10 MBit s Description The looped back data is falsified at the two lower baud rates of 5 and 2 5 MBit s Scope The erratum is limited to test cases where loop back is used with the baud rate prescaler PRTC1 BRP 1 0 configured to 5 or 2 5 MBit s Effects The loop back self test is only possible at the highest baud rate Workaround Run loop back tests with 10 MBit s PRTC1 BRP 1 0 008 FlexRay 1 098 Suspend Mode is not functional Description Errata Sheet 37 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description The applied kernel mode KSCFG SUMCFG 2 Stop Mode 0 in suspend state will not be performed The module proceeds its communication and the module clock is not switched off Workaround To keep a smooth FlexRay communication ongoing the FlexRay controller will go to halt state at the end of the communication cycle If the FlexRay controller is in NORMAL ACTIVE or NORMAL
9. High Line Detailed Errata Description SWD_X P002 Supply Watchdog SWD Supervision Level in Data Sheet The Supply Watchdog SWD Supervision Level Vgywp tolerance boundaries for 5 5 V are changed from 0 15 V to 0 30 V Errata Sheet 57 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description 6 3 Application Hints ADC _AI H002 Minimizing Power Consumption of an ADC Module For a given number of A D conversions during a defined period of time the total energy power over time required by the ADC analog part during these conversions via supply is approximately proportional to the converter active time Recommendation for Minimum Power Consumption In order to minimize the contribution of A D conversions to the total power consumption it is recommended 1 to select the internal operating frequency of the analog part near the maximum value specified in the Data Sheet and 2 to switch the ADC to a power saving state via ANON while no conversions are performed Note that a certain wake up time is required before the next set of conversions when the power saving state is left Note The selected internal operating frequency of the analog part that determines the conversion time will also influence the sample time ts The sample time ts can individually be adapted for the analog input channels via bit field STC 12 X H0
10. Documentation Updates 24 Detailed Errata Description 25 Functional Deviations 2 2 2 2 25 BROM 006 ie Ro sane ea ee 25 BSL CAN 001 54 4545 vig stes du dud eee ead 25 002 nina Shire deka meee et etree cate eae 26 002 44444 rnr bei daw enh 27 pu 27 ESR X004 i gee ceed od qe ver ere 29 FlexRay 1 087 30 FlexRay_Al 088 30 FlexRay_Al 089 31 FlexRay AL090 eceu osse alee m e ee eee 32 FlexRay AL091 ros 35425 Se ke Rap PROF Rn 33 FlexRay 092 mess nae RR Rd DE ER RE 33 FlexRay AL099 iocis egeret rcg Seared EE ete eae 34 FlexRay 094 cce cose esos RR RR URB Eur 35 FlexRay AL095 2 2 35 FlexRay_Al 096 eccesso ee Ro eg Rn ER 36 FlexRay 097 2 222222 22424 4 ERR 37 FlexRay 1098 2 222 2 37 FlexRay 099 2 2 22 2 38 FlexRay 1 100 39 AL101 oe adie ei em x eR Eee 40 ElexRay AL102 2 21 i
11. Functional Deviation XC22xxH EES AA ES AA ES AA all AB FlexRay_Al 095 FlexRay_Al 096 FlexRay_Al 097 FlexRay_Al 098 1 099 FlexRay_Al 100 FlexRay_Al 101 FlexRay_Al 102 FlexRay_Al 103 FlexRay_X 001 GPT12E_X 002 OCDS_X 003 PAD_X 001 PARITY_X 001 RESET_X 003 RESET_X 004 SCU_X 012 StartUp 002 StartUp X 003 USIC Al 004 USIC 1 005 OK X X X x X X KI I K K OK OK Errata Sheet 12 V1 6 2013 03 au ee XC2200H Derivatives Infineon XC2000 Family High Line Errata Device Overview Table 2 Errata Device Overview Functional Deviations cont d x N N Functional 2 Deviation 355 nT lt 5 USIC Al 016 X X WDT X 002 X X 1 From EES ES AA step to ES AA ES AB AB step 2 errata have been fixed 2 Valid for all AB steps encloses ES AB and AB step Errata Sheet 13 V1 6 2013 03 au ee XC2200H Derivatives Infineon XC2000 Family High Line Errata Device Overview 4 2 Deviations from Electrical and Timing Specification Table 3 shows the dependencies of deviations from the electrical and timing specification in the derivatives Table 3 Errata Device Overview Deviations from Electrical and Timing Specification x N N ACIDC ADC 2 Deviation mS
12. SWD X H001 X X StartUp X H001 X X USIC AI H001 X X USIC AI H002 X X USIC AI H003 X X 1 From EES ES AA step to ES AA ES AB AB step 2 errata have been fixed 2 Valid for all AB steps encloses ES AB and AB step Errata Sheet 16 V1 6 2013 03 au ee XC2200H Derivatives Infineon XC2000 Family High Line Errata Device Overview 4 4 Documentation Updates Table 5 shows the dependencies oft documentation updates in the derivatives Table 5 Errata Device Overview Documentation Updates x x N N Documentation 2 Updates E 555 oT lt EBC X D001 X X ECC X D002 X X RESET X D001 X X 1 From EES ES AA step to ES AA ES AB AB step 2 errata have been fixed 2 Valid for all AB steps encloses ES AB and AB step Errata Sheet 17 V1 6 2013 03 om XC2200H Derivatives Infineon XC2000 Family High Line Short Errata Description 5 Short Errata Description This chapter gives an overview on the deviations and application hints Changes to the last Errata Sheet are shown the column Chg 5 1 Functional Deviations Table 6 shows a short description of the functional deviations Table 6 Functional Deviations Functional Short Description Chg Pg Deviation BROM_TC 006 Baud Rate Detection for CAN Bootstrap New 25 Loader BSL_CAN_X 001 Quartz Crystal Settling Time after PORST 25 too Long for CAN Boo
13. as this register is not modified by hardware Errata Sheet 59 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description 6 001 Modifications of Bit MODEN in Register CCU6x_KSCFG For each module setting bit MODEN 0 immediately switches off the module clock Care must be taken that the module clock is only switched off when the module is in a defined state e g stop mode in order to avoid undesired effects in an application In addition fora CCU6 module in particular if bit MODEN is changed to 0 while the internal functional blocks have not reached their defined stop conditions and later MODEN is set to 1 and the mode is not set to run mode this leads to a lock situation where the module clock is not switched on again ECC X H001 ECC Error Indication Permanently Set The ECC error flag of the ECCSTAT register for the DPRAM DSRAM PSRAM and SBRAM can not be cleared if a memory location with an ECC error is selected and the ECC is enabled The memory can be selected by an active or by the latest read or write access Workaround Select a memory location without ECC error in the respective memory e g make a read to another address and then clear the ECC error flag Be aware that the new selected address may also have an ECC error FlexRay 004 Only the first message be received in External Loop B
14. within an ISR Workaround 3 Some applications may not want to use or rely on the interrupt logic in conjunction with a WDT overflow event The proposed remedy in this case is to initiate a Power Reset to clear the internal flag by changing the settings of the active Supply Watchdog SWD as follows 1 Disable SFR protection 2 Write the inverted value of bit LxALEV to register SWDCONO where x stands for the number of the comparator which currently would trigger a Power Reset In doing so a Power Reset for VDDI 1 and VDDI M will be activated clearing the internal flag The application may store information on preceding WDT events in the Standby SRAM This can be done any time after the WDT reset without timing limitations or the need to use the interrupt logic Errata Sheet 54 V1 6 2013 03 er 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description Note Although the supply for the DPRAM DSRAM and PSRAM will be switched off during the active reset phase it depends on the external buffer capacitance at the VDDI_1 pins the actual system clock frequency and the environmental conditions whether the content of these RAMs will be preserved in this case or not However the Standby RAM itself is not cleared upon this reset Errata Sheet 55 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description 6 2 Deviations fro
15. 1 Port 3 0 DISABLED DISABLED Input 2 Port 10 0 OK OK Input 3 Port 1 0 OK DISABLED Errata Sheet 27 V1 6 2013 03 2200 Derivatives 2000 Family High Line Cafineon Detailed Errata Description Table 10 Tables for XC2297H XC229xH ESREXCONT1 cont d ESREXCON1 ESR1 XC2297H XC229xH selection Port Input 4 Port 1 2 OK DISABLED Input 5 Port 2 1 OK OK Input 6 Port 6 1 OK OK Input 7 Port 11 0 DISABLED DISABLED Input 8 Port 4 1 OK DISABLED Input 9 Port 10 4 OK OK Input 10 Port 2 5 OK OK Input 11 Port 0 0 OK DISABLED Table11 Tables for XC2297H and XC229xH ESREXCON2 ESREXCON2 ESR2 XC2297H XC229xH selection Port Input 0 Port 2 3 OK OK Input 1 Port 7 0 OK OK Input 2 Port 10 14 OK OK Input 3 Port 1 1 OK DISABLED Input 4 Port 1 3 OK DISABLED Input 5 Port 2 2 OK OK Input 6 Port 2 6 OK OK Input 7 Port 2 7 OK OK Input 8 Port 0 4 OK DISABLED Input 9 XTAL1 OK OK Input 10 Port 4 5 DISABLED DISABLED Input 11 Port 10 8 OK OK Errata Sheet 28 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description ESR X 004 Wrong Value of SCU_RSTCONx Registers after ESRy Applica tion Reset SCU RSTCONx registers are reset only by Power On but they may be wrongly affected after a second application reset requested by an ESRy pin This may lead to the SCU_RSTC
16. 355 oT lt 5 FLASH_X P001 X X SWD X P001 X SWD X P002 X X 1 From EES ES AA step to ES AA ES AB AB step 2 errata have been fixed 2 Valid for all AB steps encloses ES AB and AB step Errata Sheet 14 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Errata Device Overview 4 3 Application Hints Table 4 shows the dependencies of application hints in the derivatives Table 4 Errata Device Overview Application Hints I N N Hint 2 i338 oT lt ADC_AI H002 CAPCOM12 001 CC6 X H001 ECC X H001 FlexRay_Al H004 FlexRay_Al H005 FlexRay_Al H006 FlexRay_Al H007 FlexRay_Al H009 GPT12 001 GPT12E_X H002 002 004 MultiCAN_AI H005 MultiCAN_AI H006 MultiCAN_AI H007 MultiCAN AI H008 MultiCAN TC H002 MultiCAN TC H003 X X X X X X X X X X xx X X X X X X X OK Errata Sheet 15 V1 6 2013 03 Cinfineon XC2200H Derivatives XC2000 Family High Line Errata Device Overview Table 4 Errata Device Overview Application Hints cont d x N N Hint 444 oO T lt 7 MultiCAN 004 OCDS X H003 X X PVC X H001 X X RESET X H003 X X RTC X H003 X X SCU X H009 X X
17. Disable the trim interrupt source SCU_INTDIS WUTI Errata Sheet 70 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description 2 Clear the trim interrupt request flag by writing to INTCLR WUTI 3 Clear the selected SCU request flag default is ScU_1IC IR SWD X H001 Application Influence on the SWD The internal Supply Watchdog SWD monitors the external supply voltage of the pad I O domain Vpppg which is connected to the device Therefore adjustable threshold levels are defined over the complete supply voltage range These limits are also influenced by system environment and may deviate due to external influences slightly from the values given in the Datasheet Independent of the SWD is the internal start up and operation protected by the PVC which monitor the core voltage StartUp X H001 EBC is not Disabled in Fast Startup Mode The pin assignment to the External Bus Controller EBC is disabled after start up in all modes that do not need the external bus explicitly i e in all modes but External Start The special Fast Startup Mode FSM which can be entered in conjunction with Standby Mode 1 is an exception from this rule If the user executed code in FSM and needs one pin or some pins which can be assigned to EBC the user code must first disable this assignment by setting EBCMODO EBCDIS 1g Afterwards all the EBC pins are available to the user software as GPIOs
18. LEV2V in register SCU PVCMCONO The default value of LEV1V is used to generate a reset request in the case of low core voltage LEV2V can generate an interrupt request at a higher voltage to be used as a warning Due to variations of the tolerance of both the Embedded Voltage Regulators EVR and the PVC levels this interrupt can be triggered inadvertently even though the core voltage is within the normal range It is therefore recommended not to use this warning level LEV2V can be disabled by executing the following sequence 1 Disable the PVC level threshold 2 interrupt request SCU PVCMCONO L2INTEN Disable the PVC interrupt request flag source SCU_INTDIS PVCMI2 Clear the PVC interrupt request flag source 5 0 DMPMITCLR PVCMI2 Clear the PVC interrupt request flag by writing to SCU INTCLR PVCMI2 Clear the selected SCU request flag default is 5 0 11C IR Errata Sheet 69 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description RESET 003 How to Trigger a PORST after an Internal Failure There is no internal User Reset that restores the complete device including the power system like a Power On Reset In some applications it is possible to connect ESR1 or ESR2 with the PORST pin and set the used ESR pin as Reset output With this a WDT or Software Reset can trigger a Power On Reset A detailed description is in the Application Note
19. frame overflow flag EIR SFO may be 35 set if slot counter is greater than 1024 FlexRay_Al 095 Register RCV displays wrong value 35 FlexRay_Al 096 Noise following a dynamic frame that 36 delays idle detection may fail to stop slot FlexRay_Al 097 Loop back mode operates only at 10 MBit s 37 FlexRay 1 098 Suspend Mode is not functional 37 FlexRay_Al 099 Erroneous cycle offset during startup after 38 abort of startup or normal operation FlexRay_Al 100 First WUS following received valid WUP 39 may be ignored FlexRay 1 101 READY command accepted in READY 40 state FlexRay_Al 102 Slot Status vPOC SlotMode is reset 40 immediately when entering HALT state FlexRay_Al 103 Received messages not stored in Message New 41 RAM when in Loop Back Mode X 001 Trigger User Reset after Power On New 40 12 X 002 Effects of GPT Module Microarchitecture 42 Errata Sheet 19 V1 6 2013 03 e H XC2200H Derivatives Infineon XC2000 Family High Line Short Errata Description Table 6 Functional Deviations cont d Functional Short Description Chg Pg Deviation OCDS X 003 Peripheral Debug Mode Settings cleared 43 by Reset PAD X 001 Additional Edges in the Input Signal New 44 PARITY X 001 PMTSR Register Initialization 48 RESET X 003 P2 2 0 and P10 12 0 Switch to Input 49 RESET X 004 Sticky Register Access Trap forces New 49 device into power save mode after reset SCU
20. is entered after NORMAL_ACTIVE state was left by FREEZE or HALT command Effects Received messages are not stored in Message RAM because acceptance filtering is not started Workaround Leave HALT state by hardware reset FlexRay X 001 Trigger User Reset after Power On After Power On the FlexRay Interrupt Request Flags e g FR_OIC IR are sometime set erroneous After interrupt enabling e g FR OIC IE andifthe corresponding Interrupt Request Flag is set the interrupt routine will be called Workaround Trigger a Functional User Reset i e Debug Reset Internal Application Reset or Application Reset by software and after that the FlexRay module is correct installed Errata Sheet 41 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description GPT12E X 002 Effects of GPT Module Microarchitecture The present GPT module implementation provides some enhanced features e g block prescalers BPS1 BPS2 while still maintaining timing and functional compatibility with the original implementation in the C166 Family of microcontrollers Both the GPT1 and GPT2 blocks use a finite state machine to control the actions within each block Since multiple interactions are possible between the timers T2 T6 and register CAPREL these elements are processed sequentially within each block in different states However all actions are normally completed within one basic clock cycl
21. on the CAN receive inputs This double synchronization delays the receive data by 2 module clock cycles If the MultiCAN is operating at a low module clock frequency and high CAN baudrate this delay may become significant and has to be taken into Errata Sheet 66 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description account when calculating the overall physical delay on the CAN bus transceiver delay MultiCAN TC H003 Message may be discarded before transmission STT mode If MOFCRn STT 1 Single Transmit Trial enabled bit TXRQ is cleared TXRQ 0 as soon as the message object has been selected for transmission and in case of error no retransmission takes places Therefore if the error occurs between the selection for transmission and the real start of frame transmission the message is actually never sent Workaround In case the transmission shall be guaranteed it is not suitable to use the STT mode In this case MOFCRn STT shall be 0 MultiCAN TC H004 Double remote request Assume the following scenario A first remote frame dedicated to a message object has been received It performs a transmit setup is set with clearing NEWDAT MultiCAN starts to send the receiver message object data frame but loses arbitration against a second remote request received by the same message object as the first one NEWDAT will be set When
22. safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered 113 16 32 Bit Architecture XC2200H Derivatives 16 32 Bit Single Chip Microcontroller with 32 Bit Performance XC2000 Family High Line Errata Sheet V1 6 2013 03 Microcontrollers er 2200 Derivatives Infineon XC2000 Family High Line Table of Contents 1 2 3 4 4 1 4 2 4 3 4 4 5 5 1 5 2 5 3 5 4 6 6 1 History List Change Summary 7 General ERI EY LEE E 8 Current Documentation 10 Errata Device Overview 11 Functional Deviations 11 Deviations from Electrical and Timing Specification 14 Application Hints 15 Documentation Updates 17 Short Errata Description 18 Functional Deviations 18 Deviations from Electrical and Timing Specification 21 Application Hints 22
23. 01 Enabling or Disabling Single Event Operation The single event operation mode of the 1 2 unit eliminates the need for software to react after the first compare match when only one event is required within a certain time frame The enable bit SEEy for a channel CCy is cleared by hardware after the compare event thus disabling further events for this channel One Channel in Single Event Operation As the Single Event Enable registers CC1 SEE 2 SEE are not located in the bit addressable SFR address range they can only be modified by instructions Errata Sheet 58 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description operating on data type WORD This is no problem when only one channel of a CAPCOM unit is used in single event mode Two or more Channels in Single Event Operation When two or more channels of a CAPCOM unit are independently operating in single event mode usually an OR instruction is used to enable one or more compare events in register CCn_ SEE while an AND instruction may be used to disable events before they have occurred In these cases the timing relation of the channels must be considered otherwise the following typical problem may occur Inthe Memory stage software reads register CCn SEE with bit SEEy 1g event for channel CCy has not yet occurred Mean
24. AP16103 X H003 Changing the RTC Configuration The count input clock for the Real Time Clock module RTC can be selected via bit field RTCCLKSEL in register RTCCLKCON Whenever the system clock is less than 4 times faster than the RTC count input clock fsys lt 4 Asynchronous Mode must be selected bit RTCCM 1 in register RTCCLKCON To assure data consistency in the count registers T14 RTCL RTCH the RTC module must be temporarily switched off by setting bit MODEN 0 in register KSCCFG before register RTCCLKCON is modified i e whenever changing the operating mode Synchronous Asynchronous Mode in bit RTCCM or changing the RTC count source in bit field RTCCLKSEL In case power domain DMP 1 is switched off it is not required to switch the RTC to Asynchronous Mode since it will receive a reset in any case SCU X H009 WUCR TTSTAT can be set after a Power Up After power up the wake up clock fwy is selected for the Wake Up Timer WUT In this case the trim interrupt trigger cannot be used because the WUT trim trigger status bit WUCR TTSTAT might become set erroneously This happens sporadically and is therefore difficult to find in the development phase of an application If the trim interrupt trigger is enabled this may lead to unintended SCU interrupts that may also block other interrupt sources see INT_X H004 This can be avoided by executing the following sequence 1
25. C2000 XE166 devices allow the user to select between a number of debug interface options including type JTAG DAP and pin assignment The primary selection is done by configuration pins upon power on where one of the supported options is to install the debug interface according to the value taken from dedicated locations in user Flash C001F0 C001F3 This option is selected by configuration pin values HWCFG xxxxx111g code start from internal Flash or 1100000 code start from external memory The other configurations directly selecting a debug mode work correctly The start up procedure reads the dedicated locations in Flash too early before Flash redundancy is installed which can lead to an unrecoverable read error and terminate the boot process if the block from 1 to COO1FF is programmed by the user A limited number of devices are affected a rough estimation is below 1 from the production and the mis behavior is constant That means any device is either always error free or always failing if no programming of the block from C001F0 to COO1FF is done after the last power on Note that only the two mentioned modes upon power on and only the read from dedicated locations during start up are affected but not in general Flash and debug interface functionality Errata Sheet 51 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description Workar
26. CAN TC H003 Message may be discarded before 67 transmission in STT mode MultiCAN TC H004 Double remote request 67 OCDS X H003 Debug Interface Configuration by User 68 Software PVC X H001 PVC Threshold Level 2 Upd 68 ate RESET X H003 How to Trigger a PORST after an Internal 70 Failure RTC X H003 Changing the RTC Configuration 70 SCU 009 WUCR TTSTAT can be set after a Power 70 Up SWD X H001 Application Influence on the SWD 71 StartUp X H001 EBC is not Disabled in Fast Startup Mode 71 USIC_AI H001 FIFO RAM Parity Error Handling 71 USIC_AI H002 Configuration of USIC Port Pins New 72 USIC_AI H003 PSR RXIDLE Cleared by Software New 73 Errata Sheet 23 V1 6 2013 03 au 524540 2200 Derivatives Infineon XC2000 Family High Line Short Errata Description 5 4 Documentation Updates Table 9 gives a short description of the documentation updates Table 9 Documentation Updates Documentation Short Description Chg Pg Updates EBC_X D001 Visibility of Internal LXBus Cycles on New 74 External Address Bus ECC_X D002 Initialization of the Read Control Logic 74 RESET X D001 Reset Types of Trap Registers 75 Errata Sheet 24 V1 6 2013 03 au 524540 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description 6 Detailed Errata Description This chapter provides a detailed description for each erratum If applicable a workaround is suggested 6 1 F
27. NIT 0 60 0 1 EWRN BOFF INIT REC 0x0 TEC 0x0 ALERT INIT 0 60 REC 0x60 EWRN Figure 6 Alert Interrupt Behavior in case of Bus Off When the threshold for error warning EWRN is reached default value of Error Warning Level EWRN 0x60 then the EWRN interrupt is issued The bus off BOFF status is reached if TEC gt 255 according to CAN specification changing the MultiCAN module with REC and TEC to the same value 0 1 setting the INIT bit to 15 and issuing the BOFF interrupt The bus off recovery phase starts automatically Every time an idle time is seen REC is incremented If REC 0x60 a combined status EWRN BOFF is reached The corresponding interrupt can also be seen as a pre warning interrupt that the bus off recovery phase will be finished soon When the bus off recovery phase has finished 128 times idle time have been seen on the bus EWRN and BOFF are cleared the ALERT interrupt bit is set and the INIT bit is still set MultiCAN AI H008 Effect of CANDIS on SUSACK When a CAN node is disabled by setting bit NCR CANDIS 1g the node waits for the bus idle state and then sets bit NSR SUSACK 1 However SUSACK has no effect on applications as its original intention is to have an indication that the suspend mode of the node is reached during debugging MultiCAN TC H002 Double Synchronization of receive input The MultiCAN module has a double synchronization stage
28. ONx register values being set to zero which could unexpectedly disable reset sources within the user application The conditions which lead to this behavior are 1 First an application reset by SW software CPU Central Processing Unit MP Memory WDT Watchdog Timer or ESRy External Service Request y occurs 2 Following this an application reset on an ESRy pin occurs 3 If the above mentioned ESRy reset occurs during a critical time window of the SSW startup software then it s possible that the application will operate with the wrong SCU RSTCONx register value The critical time window occurs when the SSW is writing the SCU_RSTCONx registers and at the same time the ESRy reset request is processed by the reset circuitry The width of this critical window f i window IS less than 13 cycles Application Reset E T toritical window 11 Reset by ESRy pin 1 1 1 I ssw Start of Write Start of End of S ssw RSTCON SSW SSW I 11 Application Application Software Runs Runs Fog i A ESR X 004 Fig 1 Figure 1 Critical application reset sequence Workaround e Initialize 5 0 RSTCONx registers by user software after any reset or assure that a second application reset request with an ESR pin does not occur during the critical time window Errata Sheet 29 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line
29. PVC Threshold Level 2 The Power Validation Circuits PVCM PVC1 compare the supply voltage of the respective domain DMP_M DMP_1 with programmable levels LEV1V LEV2V in register SCU_PVCMCONO or 5 0 PVC1CONO The default value of LEV1V is used to generate a reset request in the case of low core voltage Errata Sheet 68 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description LEV2V can generate an interrupt request at a higher voltage to be used as a warning Due to variations of the tolerance of both the Embedded Voltage Regulators EVR and the PVC levels this interrupt can be triggered inadvertently even though the core voltage is within the normal range It is therefore recommended not to use this warning level LEV2V can be disabled by executing the following sequence 1 Disable the PVC level threshold 2 interrupt request SCU PVCMCONO L21NTEN and SCU PVC1CONO L2INTEN 2 Disable the PVC interrupt request flag source 5 0 INTDIS PVCMI2 and SCU INTDIS PVC1I2 3 Clear the PVC interrupt request flag source SCU DMPMITCLR PVCMI2 and SCU DMPMITCLR PVC1I2 4 Clear the PVC interrupt request flag by writing to SCU_INTCLR 2 and SCU INTCLR PVC1I2 5 Clear the selected SCU request flag default is 5 0 11IC IR The Power Validation Circuits PVCM compare the supply voltage of the respective domain DMP M with programmable levels LEV1V and
30. RP coincides with the action point after detection of a valid frame Description If a valid sync frame is received before the action point and additionally noise or a second frame leads to a STRP coinciding with the action point an incorrect deviation value of zero is used for further calculations of rate and or offset correction values Scope The erratum is limited to configurations with an action point offset greater than static frame length Effects In the described case a deviation value of zero is used for further calculations of rate and or offset correction values This may lead to an incorrect rate and or offset correction of the node Workaround Configure action point offset smaller than static frame length FlexRay 1 092 Initial rate correction value of an integrating node is zero if pMicrolnitialOffsetA B 0x00 Description The initial rate correction value as calculated in figure 8 8 of protocol spec v2 1 is zero if parameter pMicrolnitialOffsetA B was configured to be zero Scope The erratum is limited to the case where pMicrolnitialOffsetA B is configured to Zero Errata Sheet 33 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description Effects Starting with an initial rate correction value of zero leads to an adjustment of the rate correction earliest 3 cycles later see figure 7 10 of protocol spec v2 1 In a worst case scen
31. X 012 Wake Up Timer RUNCON Command New 50 StartUp X 002 JTAG pos E DAP pos 3 after Wake Up 50 from Stand By Mode StartUp X 003 Debug Interface Configuration from Flash New 51 can Fail Upon Power On USIC Al 004 Receive shifter baudrate limitation 52 USIC AI 005 Only 7 data bits are generated mode 52 when TBUF is loaded in SDA hold time USIC 1 016 Transmit parameters are updated during New 53 FIFO buffer bypass WDT X 002 Clearing the Internal Flag which Stores 53 Preceding WDT Reset Request Errata Sheet 20 V1 6 2013 03 Cafineon XC2200H Derivatives XC2000 Family High Line Short Errata Description 5 2 Deviations from Electrical and Timing Specification Table 7 shows a short description of the electrical and timing deviations from the specification Table 7 Deviations from Electrical and Timing Specification AC DC ADC Short Description Chg Pg Deviation FLASH_X P001 Test Condition for Flash parameter NER in New 56 Data Sheets SWD_X P001 Supply Watchdog Level VSWD_min too 56 Low SWD_X P002 Minimizing Power Consumption of an New 57 ADC Module Errata Sheet 21 V1 6 2013 03 om H XC2200H Derivatives Infineon XC2000 Family High Line Short Errata Description 5 3 Application Hints Table 8 shows a short description of the application hints Table 8 Application Hints Hint S
32. _PASSIVE state the controller goes to POC HALT state by setting SUCC1 CMD 0110 In any other state the command will not be accepted SUCC1 CMD 0000 COMMAND FlexRay 1 099 Erroneous cycle offset during startup after abort of start up or normal operation Description An abort of startup or normal operation by a READY command near the macotick border may lead to the effect that the state INITIALIZE SCHEDULE is one macrotick too short during the first following integration attempt This leads to an early cycle start in state INTEGRATION COLDSTART CHECK INTEGRATION CONSISTENCY CHECK As a result the integrating node calculates a cycle offset of one macrotick at the end of the first even odd cycle pair the X states INTEGRATION COLDSTART CHECK or INTEGRATION_CONSISTENCY_CHECK and tries to correct this offset If the node is able to correct the offset of one macrotick pOffsetCorrectionOut gt gt gdMacrotick the node enters NORMAL_ACTIVE with the first startup attempt If the node is not able to correct the offset error because pOffsetCorrectionOut is too small pOffsetCorrectionOut lt gdMacrotick the node enters ABORT STARTUP and is to try startup again The next second startup attempt is not effected by this erratum Errata Sheet 38 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description Scope The erratum
33. ack mode If the loop back TXD to RXD will be performed via external physical transceiver there will be a large delay between TXD and RXD A delay of two sample clock periods can be tolerated from TXD to RXD due to a majority voting filter operation on the sampled RXD Only the first message can be received due to this delay To avoid that only the first message can be received a start condition of another message idle and sampling 0 gt low pulse must be performed The following procedure can be applied at one or both channels Errata Sheet 60 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description wait for no activity TEST1 A0x 0 gt bus idle e set Test Multiplexer Control to Test Mode TEST1 TMC 2 simultaneously TXDx TXENx 0 e wait for activity TEST1 AOx 1 gt bus not idle set Test Multiplexer Control back to Normal signal path TEST1 TMC 0 wait for no activity TEST1 A0x 0 gt bus idle Now the next transmission can be requested FlexRay AI H005 Initialization of internal RAMs requires eray bclk cycle more The initialization of the E Ray internal RAMs as started after hardware reset or by CHI command CLEAR RAMS SUCC1 CMD 3 0 1100 takes 2049 eray_bclk cycles instead of 2048 eray_bclk cycles as described in the E Ray Specification Signalling of the end of the RAM initialization sequence by t
34. ario if the whole cluster is drifting away too fast the integrating node would not be able to follow and therefore abort integration Workaround Avoid configurations with pMicrolnitialOffsetA B equal to zero If the related configuration constraint of the protocol specification results pMicrolnitialOffsetA B equal to zero configure it to one instead This will lead to a correct initial rate correction value it will delay the startup of the node by only one microtick 1 093 Acceptance of startup frames received after reception of more than gSyncNodeMax sync frames Description If a node receives in an even cycle a startup frame after it has received more than gSyncNodeMax sync frames this startup frame is added erroneously by process CSP to the number of valid startup frames zStartupNodes The faulty number of startup frames is delivered to the process POC As a consequence this node may integrate erroneously to the running cluster because it assumes that it has received the required number of startup frames Scope The erratum is limited to the case of more than gSyncNodeMax sync frames Effects In the described case a node may erroneously integrate successfully into a running cluster Errata Sheet 34 V1 6 2013 03 m 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description Workaround Use frame schedules where all startup frames are placed in the first sta
35. atives Infineon XC2000 Family High Line Detailed Errata Description When counts down and value x gt reload value is read from value x should be replaced with the reload value for further calculations Alternatively if the intention is to identify the overflow underflow of T3 the T3 interrupt request may be used 2 Reload of from T2 with setting BPS1 01 and 000 When T2 is used to reload in the configuration with 51 01g and 000 fastest configuration highest resolution of the reload of is performed with a delay of one basic clock cycle Workaround 1 To compensate the delay and achieve correct timing increment the reload value in T2 by 1 when T3 is configured to count up decrement the reload value in T2 by 1 when T3 is configured to count down Workaround 2 Alternatively use T4 instead of T2 as reload register for T3 In this configuration the reload of T3 is not delayed i e the effect described above does not occur with T4 OCDS X 003 Peripheral Debug Mode Settings cleared by Reset The behavior run stop of the peripheral modules in debug mode is defined in bitfield SUMCFG in the KSCCFG registers The intended behavior is that after an application reset has occurred during a debug session a peripheral re enters the mode defined for debug mode For some peripherals the debug mode setting in SUMCFG is erroneously set to normal mode upo
36. e Note This device is equipped with a C166S V2 Core Some of the errata have workarounds which are possibly supported by the tool vendors Some corresponding compiler switches need possibly to be set Please see the respective documentation of your compiler For effects of issues related to the on chip debug system see also the documentation of the debug tool vendor Errata Sheet 8 V1 6 2013 03 m 2200 Derivatives Infineon XC2000 Family High Line General Some errata of this Errata Sheet do not refer to all of the XC2200H Derivatives please look to the overview Table 2 for Functional Deviations Table 3 for Deviations from Electrical and Timing Specification Table 4 for Application Hints Table 5 for Documentation Updates Errata Sheet 9 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Current Documentation 3 Current Documentation The Infineon XC2000 Family comprises device types from the XC2200 group the XC2300 group and the XC2700 group The XC22xxH device types belong to the XC2200 group Device XC22xxH Marking Step EES AA ES AA ES AA ES AB AB Package PG LQFP 144 PG LQFP 176 This Errata Sheet refers to the following documentation e XC2200H Derivatives User s Manual e 228 Data Sheet e 229 Data Sheet e 2297 Data Sheet Documentation Addendum if applicable Make sure you always use the corresponding documentation
37. e The GPT2 state machine has 4 states 2 states when BPS2 01 and processes T6 before T5 The GPT1 state machine has 8 states 4 states when 51 01 and processes the timers in the order T2 all actions except capture T4 T2 capture In the following two effects of the internal module microarchitecture that may require special consideration in an application are described in more detail 1 Reading T3 by Software with T2 T4 in Reload Mode When T2 or T4 are used to reload T3 on overflow underflow and T3 is read by software on the fly the following unexpected values may be read from T3 when is counting up 0000 0001 may be read from T3 directly after an overflow although the reload value in T2 T4 is higher 0001 may be read in particular if BPS1 01g and 000g e when is counting down FFFF or FFFE may be read from directly after an underflow although the reload value in T2 T4 is lower FFFE may be read in particular if BPS1 01 and 000 Note All timings derived from T3 in this configuration e g distance between interrupt requests PWM waveform on etc are accurate except for the specific case described under 2 below Workaround When counts up and value x lt reload value is read from T3 value x should be replaced with the reload value for further calculations Errata Sheet 42 V1 6 2013 03 2200 Deriv
38. e The erratum is limited to the READY state Effects Flag CCSV CSTI is set Cold starting needs to be enabled by POC command ALLOW_COLDSTART SUCC1 CMD 10018 Workaround None 1 102 Slot Status vPOC SlotMode is reset immediately when entering HALT state Description When the protocol engine is in the states NORMAL_ACTIVE or NORMAL_PASSIVE a HALT or FREEZE command issued by the Host resets vPOC SlotMode immediately to SINGLE slot mode CCSV SLM 1 0 50058 According to the FlexRay protocol specification the slot mode should not be reset to SINGLE slot mode before the following state transition from HALT to DEFAULT_CONFIG state Scope The erratum is limited to the HALT state Effects The slot status vVPOC SlotMode is reset to SINGLE when entering HALT state Errata Sheet 40 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description Workaround None FlexRay 1 103 Received messages not stored in Message RAM when Loop Back Mode After a FREEZE or HALT command has been asserted in NORMAL_ACTIVE state and if state LOOP_BACK is then entered by transition from HALT state via DEF_CONFIG and CONFIG it may happen that acceptance filtering for received messages is not started and therefore these messages are not stored in the respective receive buffer in the Message RAM Scope The erratum is limited to the case where Loop Back Mode
39. e protocol or due multiple sampling of the hardware USIC CAN Others Errata Sheet 45 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description Workaround for Input Capture Conditions 1 Workaround for all Affected Applications Use rising edges with faster rising slope f than defined in Table 12 2 Workaround for CCU6 2 and GPT Inputs No generic solution is available for these applications Add or switch to a software solution For example the software could check whether the measured signal values are in the expected range 3 Workaround for Port Inputs 1 The captured time interval value should be checked whether it is in a reasonable range 2 The input pin should be read several times and a majority decision may be made to decide whether the edge was correct or erratic Only if 1 and 2 indicate that the edge was reliable the captured value should be used for further calculations Otherwise a substituted extrapolated value might be used 4 Workaround for Interrupt Inputs 4 1 Falling Edge Detection Approach 1 Measure the time interval since the last interrupt shown as in tintervai in Figure 3 below and check that it is in the expected time range In the example an erratic edge would cause the measured time interval erratic interval t0 be approximately 50 of the expected value 2 The state of the input pin that caused t
40. for this device available in category Documents at www infineon com xc2200 The specific test conditions for EES and ES are documented in a separate Status Sheet Note Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only Errata Sheet 10 V1 6 2013 03 om H XC2200H Derivatives Infineon XC2000 Family High Line Errata Device Overview 4 Errata Device Overview This chapter gives an overview of the dependencies of individual errata to devices and steps An X in the column of the sales codes shows that this erratum is valid 4 1 Functional Deviations Table 2 shows the dependencies of functional deviations in the derivatives Table 2 Errata Device Overview Functional Deviations XC22xxH Functional Deviation EES AA ES AA ES AA all AB BROM_TC 006 BSL_CAN_X 001 002 ESR_X 002 ESR_X 003 ESR_X 004 FlexRay_Al 087 FlexRay_Al 088 FlexRay_Al 089 FlexRay_Al 090 FlexRay_Al 091 FlexRay_Al 092 FlexRay_Al 093 FlexRay_Al 094 X X X X OK x OK X X X OK OK x xx Errata Sheet 11 V1 6 2013 03 e H XC2200H Derivatives Infineon XC2000 Family High Line Errata Device Overview Table 2 Errata Device Overview Functional Deviations cont d
41. gh Line SOU X HOOO RU AUR Te es ae 70 SWD eh PRSE 71 otartUp X MOOT d see 71 1 516 1 3001 5 occ sre Pee eek 71 USIC ALH002 cmm RE Reb Uk art e tea dee 72 USIC ALHOOS securis E Ree he REID rs 73 6 4 Documentation Updates 74 12001 24 01 74 ECC2X D002 74 RESET 001 52 2 2 222222 75 Errata Sheet 6 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line History List Change Summary 1 History List Change Summary Table 1 History List Version Date Remark 1 0 30 09 2008 new Errata Sheet 1 1 30 01 2009 1 2 13 03 2009 new Marking Step ES AA added to Errata Sheet new Errata Sheet layout 1 3 01 03 2010 Errata No 01714AERRA new Marking Step ES AA added to Errata Sheet 1 4 29 06 2010 Errata No 01809AERRA new Marking Step ES AB and XC2297H Data Sheet added to Errata Sheet 1 5 23 09 2010 Errata No 01877AERRA new Marking Step AB added to Errata Sheet 1 6 22 03 2013 Errata No 02532AERRA 1 Errata changes to the previous Errata Sheet are marked in Chapter 5 Short Errata Description Trademarks C166 M TriCore DAVE
42. he interrupt could be read several times in the interrupt service routine and a majority decision made to check if the input pin really is at a low level to determine whether this is a genuine falling edge interrupt or whether the interrupt was triggered by a spike generated by a slow rising edge Errata Sheet 46 V1 6 2013 03 om H XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description 1 1 0 7 Vppp Input Signal Internal Signal hBIzl2 mWxL l 1 1 1 I FEES 1 1 Unexpected Edges y terratic interval tinterval PAD_X 001 Fig 2 Figure 3 Falling Edge Detection Approach Only if 1 and or 2 indicate that the edge was reliable should the rest of the interrupt service routine be executed 4 2 Rising Edge Detection Approach In case of rising edge detection multiple interrupts would be generated when the spike occurs The time interval since the last interrupt can be measured if it is very small compared to the expected value this would indicate a spike and the interrupt should be ignored 0 7 Vopp en Input Signal ee l Internal Signal ee terratic interval tinterval PAD_X 001 Fig 3 Figure 4 Rising Edge Detection Approach If the time between the
43. hort Description Chg Pg ADC_AI H002 Minimizing Power Consumption of an 58 ADC Module 12 001 Enabling or Disabling Single Event 58 Operation 6 001 Modifications of Bit MODEN Register 60 CCU6x_KSCFG 001 ECC Error Indication Permanently Set 60 FlexRay_Al H004 Only the first message can be received in 60 External Loop Back mode FlexRay_Al H005 Initialization of internal RAMs requires 61 one eray_bclk cycle more FlexRay_Al H006 Transmission in ATM Loopback mode 61 007 Reporting of coding errors via 61 TEST1 CERA B FlexRay_Al H009 Return from test mode operation 62 GPT12_AI H001 Modification of Block Prescalers BPS1 New 62 and BPS2 GPT12E_X H002 Reading of Concatenated Timers 63 002 Increased Latency for Hardware Traps 64 004 SCU Interrupts Enabled After Reset 64 MultiCAN_AI HO05 TxD Pulse upon short disable request 65 MultiCAN_AI H006 Time stamp influenced by 65 resynchronization MultiCAN AI H007 Alert Interrupt Behavior in case of Bus New 65 Off MultiCAN_AI H008 Effect of CANDIS on SUSACK New 66 MultiCAN TC H002 Double Synchronization of receive input 66 Errata Sheet 22 V1 6 2013 03 om 5 XC2200H Derivatives Infineon XC2000 Family High Line Short Errata Description Table 8 Application Hints cont d Hint Short Description Chg Pg Multi
44. ing sync frames cause the node to enter NORMAL_PASSIVE state use higher level application software to leave this state and to initiate a re integration into the cluster HALT state can also be used instead of NORMAL_PASSIVE state by setting pAllowHaltDueToClock to true FlexRay 1 090 Flag SFS MRCS is set erroneously although at least one valid sync frame pair is received Description If in an odd cycle 2c 1 after reception of a sync frame in slot n the total number of different sync frames per double cycle has exceeded gSyncNodeMax and the node receives in slot n 1 a sync frame that matches with a sync frame received in the even cycle 2c the sync frame pair is not taken into account by CSP process This may cause the flags SFS MRCS and EIR CCF to be set erroneously Scope The erratum is limited to the case of a faulty cluster configuration where different sets of sync frames are transmitted in even and odd cycles and the total number of different sync frames is greater than gSyncNodeMax Effects In the described case the error interrupt flag EIR CCF is set and the node may enter either the POC state NORMAL PASSIVE or HALT Workaround Correct configuration of gSyncNodeMax Errata Sheet 32 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description FlexRay 1 091 Incorrect rate and or offset correction value if second Secondary Time Reference Point ST
45. intended interrupt source So for all SCU interrupt sources which will not be used make sure to disable the interrupt source SCU INTDIS and clear any pending request flags SCU_xIC IR before enabling interrupts in interrupt controller MultiCAN AI HO05 TxD Pulse upon short disable request If a CAN disable request is set and then canceled in a very short time one bit time or less then a dominant transmit pulse may be generated by MultiCAN module even if the CAN bus is in the idle state Example for setup of the CAN disable request KSCCFG MODEN 0 and then KSCCFG MODEN 1 Workaround Set all INIT bits to 1 before requesting module disable MultiCAN AI HO06 Time stamp influenced by resynchronization The time stamp measurement feature is not based on an absolute time measurement but on actual CAN bit times which are subject to the CAN resynchronization during CAN bus operation The time stamp value merely indicates the number of elapsed actual bit times Those actual bit times can be shorter or longer than nominal bit time length due to the CAN resynchronization events Workaround None MultiCAN AI H007 Alert Interrupt Behavior in case of Bus Off The MultiCAN module shows the following behavior in case of a bus off status Errata Sheet 65 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description REC 0x1 TEC 0x1 BOFF I
46. is limited to applications where READY command is used to leave STARTUP NORMAL_ACTIVE or NORMAL_PASSIVE state Effects In the described case the integrating node tries to correct an erroneous cycle offset of one macrotick during startup Workaround With a configuration of pOffsetCorrectionOut gt gt gdMacrotick 1 cClockDeviationMax the node will be able to correct the offset and therefore also be able to successfully integrate FlexRay 1 100 First WUS following received valid WUP may be ignored Description When the protocol engine is in state WAKEUP LISTEN and receives a valid wakeup pattern WUP it transfers into state READY and updates the wakeup status vector CCSV WSV 2 0 as well as the status interrupt flags SIR WST and SIR WUPA B the received wakeup pattern continues the protocol engine may ignore the first wakeup symbol WUS following the state transition and signals the next SIR WUPA B at the third instead of the second WUS Scope The erratum is limited to the reception of redundant wakeup patterns Effects Delayed setting of status interrupt flags STR WUPA B for redundant wakeup patterns Workaround None Errata Sheet 39 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description FlexRay 1 101 READY command accepted in READY state Description The E Ray module does not ignore a READY command while in READY state Scop
47. l state machines to their initial state Note The E Ray test modes are mainly intended to support device testing or FlexRay bus analyzing Switching between test modes and regular operation is not recommended GPT12 ALH001 Modification of Block Prescalers BPS1 and BPS2 The block prescalers BPS1 and BPS2 controlled via bit fields T3CON BSP1 and T6CON BPS2 determine the basic clock for the GPT1 and GPT2 block respectively After reset when initializing a block prescaler BPSx to a value different from its default value 00g it must be initialized first before any mode involving external trigger signals is configured for the associated GPTx block These modes include counter incremental interface capture and reload mode Otherwise unintended count capture reload events may occur In case a block prescaler BPSx needs to be modified during operation of the GPTx block disable related interrupts before modification of BPSx and afterwards clear the corresponding service request flags and re initialize those registers T2 T4 in block GPT1 and T5 T6 CAPREL in block GPT2 that might be affected by an unintended count capture reload event Errata Sheet 62 V1 6 2013 03 2200 Derivatives XC2000 Family High Line om Infineon Detailed Errata Description 12 002 Reading of Concatenated Timers For measuring longer time periods a core timer T3 or T6 may be concatenated with an auxiliary timer T2 T4
48. lii gp eL 5440 ri E 40 FlexR y AL103 41 Errata Sheet 4 V1 6 2013 03 er 2200 Derivatives Infineon XC2000 Family High Line FlexRay X 001 41 GPITT2E 20002 4 ped Ee X he 42 OCDS 003 5 5 Mae ee eee Lae wees 43 PAD X 001 iiu hen s eon eae ae 44 PARITY X001 cmm epu eee 48 003 49 004 sack poate eae es 49 SGU 012 50 002 50 StartUp 003 2222 2 242 2 51 11516 5 1 004 ieget eet 52 07516 1 005 eR ee De ea ee 52 1516 1 016 25 40055 vict e i dus 53 WDT X 002 oes eei kot Tuc ele 53 6 2 Deviations from Electrical and Timing Specification 56 FLASH XCPOO01 Lucus eu See 56 SWD ea Ree ee 56 SWD X 57 6 3 Application Hints ssi ee ca Pea 65 58 002 58 12 001 58 CO
49. ly High Line Detailed Errata Description Scope The erratum is limited to the case where the application program frequently resets the appropriate SIR WUPA B bits Effects In the described case there are more SIR WUPA B events seen than expected Workaround Ignore redundant SIR WUPA B events FlexRay AL089 Rate correction set to zero in case of SyncCalcRe SsultZMISSING TERM Description In case a node receives too few sync frames for rate correction calculation and signals a SyncCalcResult of MISSING TERM the rate correction value is set to zero instead to the last calculated value Scope The erratum is limited to the case of receiving too few sync frames for rate correction calculation SyncCalcResult MISSING TERM in an odd cycle Effects In the described case a rate correction value of zero is applied in NORMAL ACTIVE NORMAL PASSIVE state instead of the last rate correction value calculated in NORMAL ACTIVE state This may lead to a desynchronisation of the node although it may stay in NORMAL ACTIVE state depending on gMaxWithoutClockCorrectionPassive and decreases the probability to re enter NORMAL ACTIVE state if it has switched to NORMAL PASSIVE pAllowHaltDueToclock false Errata Sheet 31 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description Workaround It is recommended to set gMaxWithoutClockCorrectionPassive to 1 If miss
50. m Electrical and Timing Specification FLASH X P001 Test Condition for Flash parameter Ng in Data Sheets The Flash endurance parameter Ner Number of erase cycles for 15000 cycles is documented with a wrong Test Condition The Test Condition states today 2 5 years Valid for up to 64 user selected sectors data storage In fact the amount of Flash memory validated for this cycling rate is more limited and the Test Condition must therefore state the following gp12 5 years Valid for Flash module 6 up to 64 kbytes Note The related use case for this parameter is data storage with high cycling rate in general and EEPROM emulation in particular For these applications concurrent operation of data storage to and program execution from Flash is assumed Refer also to parameter Npp SWD X P001 Supply Watchdog Level Vsy min too Low The supply watchdog SWD has a built in hysteresis In the affected products this hysteresis is increased This leads to a decreased lower level i e the threshold is lower than selected e g lt 4 5 V for SWDCON LEVxV 1001 or lt 3 0 V for SWDCON LEVxV 00015 The functionality of the on chip modules is not affected as it is ensured by the power validation circuits PVC The IO timing can be marginally slower if Vppp is below the specified minimum value Workaround None Errata Sheet 56 V1 6 2013 03 m 2200 Derivatives Infineon XC2000 Family
51. n internal flag In contrary to the documentation that this flag can be cleared by writing a 1 to bit WDTCS CLRIRF at any time clearing of the internal flag is only possible when the WDT is in Prewarning Mode Errata Sheet 53 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description Workaround 1 Applications following the proposal of Application Note AP16103 section Using ESR pins to trigger a PORST reset to trigger a Power on Reset upon a WDT event will find the internal flag cleared upon the Power on Reset and thus will have no issue with this limitation Workaround 2 In case the WDT triggers a User Reset upon a WDT overflow the internal flag will not be cleared by the reset itself Any further overflow of the WDT will lead to a permanent reset of the device Applications which intentionally let the WDT exceed once e g in conjunction with an initial self test might want to have the internal flag cleared to prevent a permanent reset upon a real WDT overflow If the internal flag shall be cleared by software this must be done as a reaction on a WDT overflow in the time frame the WDT is Prewarning Mode before the permanent User Reset will be triggered The CPU is notified upon the WDT entering Prewarning Mode by issuing an interrupt request The application can react on this request and clear the internal flag now by writing a 1g to bit WDTCS CLRIRF e g
52. n any reset instead upon a debug reset only It remains in this state until SUMCFG is written by software or the debug system Some peripherals will not re enter the state defined for debug mode after an application reset GPT12 2 and MultiCAN will resume normal operation like after reset i e they are inactive until they are initialized by software Errata Sheet 43 V1 6 2013 03 au 524540 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description In case the RTC has been running before entry into debug mode and it was configured in SUMCFG to stop in debug mode it will resume operation as before entry into debug mode instead All other peripheral modules i e ADC CCU6 and USIC will correctly re enter the state defined for debug mode after an application reset in debug mode For Flash and CPU bitfield SUMCFG must be configured to normal mode anyway since they are required for debugging Workaround None 001 Additional Edges in the Input Signal The digital input and l O pins are designed using Schmitt trigger input structures with hysteresis Even with this structure it is possible that very slow rising edges may generate spikes resulting in unexpected additional edges at the input signal The next picture Figure 2 is an example for a slow input signal with spikes shown on the slow rising input signal Input Internal Signal Unex
53. ock Cycles Setting of BPS1 BPS1 01 1 00 51 11 51 10 Required Number of 8 16 32 64 System Clocks Setting of BPS2 BPS2 01 52 00 52 11 52 10 Required Number of 4 8 16 32 System Clocks Errata Sheet 63 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description In case the required timer resolution can be achieved with different combinations of the Block Prescaler BPS1 BPS2 and the Individual Prescalers TxI the variant with the smallest value for the Block Prescaler may be chosen to minimize the waiting time E g in order to run at fsys 512 select BPS2 00 6 1115 and insert 8 NOPs or other instructions to ensure the required waiting time before reading Timer high the second time INT X H002 Increased Latency for Hardware Traps When a condition for a HW trap occurs i e one of the bits in register TFR is set to 15 the next valid instruction that reaches the Memory stage is replaced with the corresponding TRAP instruction In some special situations described in the following a valid instruction may not immediately be available at the Memory stage resulting in an increased delay in the reaction to the trap request 1 When the CPU is in break mode e g single stepping over such instructions as SBRK or BSET TFR x where one of the trap flags in register TFR will have no immediate effect un
54. or T5 of the same timer block In this case the core timer contains the low part and the auxiliary timer contains the high part of the extended timer value When reading the low and high parts of concatenated timers care must be taken to obtain consistent values in particular after a timer overflow underflow e g one part may already have considered an overflow while the other has not This is a general issue when reading multi word results with consecutive instructions and not necessarily unique to the GPT module microarchitecture The following algorithm may be used to read concatenated GPT timers represented by Timer high for auxiliary timer here T2 and Timer low for core timer here T3 In this example the high part is read twice and reading of the low part is repeated if two different values were read for the high part read Timer high temp T2 read Timer low T3 e wait two basic clock cycles to allow increment decrement of auxiliary timer in case of core timer overflow underflow see Table 13 below read Timer high T2 if Timer high is not equal to Timer high temp read Timer low T3 After execution of this algorithm Timer high and Timer low represent a consistent time stamp of the concatenated timers The equivalent number of system clock cycles corresponding to two basic clock cycles is shown in the following Table 13 Table 13 Equivalent Number of System Clock Cycles Required to Wait for Two Basic Cl
55. or with their alternate functions USIC AI H001 FIFO RAM Parity Error Handling A false RAM parity error may be signalled by the USIC module which may optionally lead to a trap request if enabled for the USIC RAM under the following conditions e areceive FIFO buffer is configured for the USIC module and after the last power up less data elements than configured in bit field SIZE have been received in the FIFO buffer and e the last data element is read from the receiver buffer output register OUTRL i e the buffer is empty after this read access Errata Sheet 71 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description Once the number of received data elements is greater than or equal to the receive buffer size configured in bit field STZE the effect described above can no longer occur To avoid false parity errors it is recommended to initialize the USIC RAM before using the receive buffer FIFO This can be achieved by configuring a 64 entry transmit FIFO and writing 64 times the value 0 0 to the FIFO input register INOO to fill the whole FIFO RAM with OxO USIC AI H002 Configuration of USIC Port Pins Setting up alternate output functions of USIC port pins through registers before enabling the USIC protocol CCR MODE 0001 0010p 0011 or 01005 might lead to unintended spikes on these port pins To avoid the unintended spike
56. ound 1 Do not program the page from C00180 to COO1FF This provides an erased error free flash read during start up without installed flash redundancy of DBGPRR register value which allows start up from internal external memory and JTAG position A 2 fthese start up configurations are used during development a device that does not start up in the desired debug configuration should be replaced by another device 3 Alternatively select a debug interface not from Flash data but directly using configuration pins refer to the User s Manual With this it is not possible to start from external memory nor is JTAG position A available USIC 1 004 Receive shifter baudrate limitation If the frame length of SCTRH FLE does not match the frame length of the master then the baudrate of the SSC slave receiver is limited to f 2 instead or Toys Workaround None USIC AL005 Only 7 data bits are generated mode when TBUF is loaded in SDA hold time When the delay time counter is used to delay the data line SDA HDEL gt 0 and the empty transmit buffer TBUF was loaded between the end of the acknowledge bit and the expiration of programmed delay time HDEL only 7 data bits are transmitted With setting HDEL 0 the delay time will be type 4 x 1 delay approximately 60ns 80MHz Workaround Do not use the delay time counter i e use only HDEL 0 default or Errata Sheet 52 V1 6 2013 03
57. p X 002 JTAG pos E DAP pos 3 after Wake Up from Stand By Mode Upon wake up from stand by mode the debug interface is configured according to the start up configuration selected lastly before entering stand by mode If the start up configuration of a 176 pin device is debug port JTAG pos E DAP pos 3 the selection between JTAG and DAP is done also in the stand by wake up phase like upon power on reset The DAP1 3 TDO E pin level is evaluated and therefore a fixed level must be applied to this pin by the tool Since a debugger cannot detect stand by mode there is no feasible way to support debugging via JTAG E DAP 3 pins across stand by wake up phases for this start up configuration CFG pins P10 6 0 0100000 Errata Sheet 50 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description Workaround The alternative solution is to use Internal Start from Flash with Debug Interface from Flash CFG pins P10 6 0 111 or External Start with Debug Interface from Flash CFG pins P10 6 0 11000005 and store the following DBGPRR content at address 001 0 1 00 for pos 1800 for DAP pos 3 Note FSM Fast Startup Mode is not affected by this issue StartUp X 003 Debug Interface Configuration from Flash can Fail Upon Power On This erratum only affects devices with a Date Code before G1203 i e digit value lt 1203 X
58. pected Edges gt a 001 Fig 1 Se I 1 I Figure 2 Example for a Slow Input Signal Errata Sheet 44 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description The first rising edge in Figure 2 of the internal signal is always valid The edges which are marked with Unexpected Edges must be ignored Measurements have shown that a spike can be generated under the following conditions Table 12 Conditions for Additional Edges in the Input Signal Parameter Symbol Typ Value Unit Note Digital supply voltage ppp 4 50 5 5 Upper Voltage Range Junction Temperature full range System frequency 152 MHz Rising Slope f 21 Hs The reaction to this spike generation strongly depends on the application hardware software internal and external noise Although it is not possible to define how the application will react in all cases it is possible to categorize how applications are typically affected as shown below Applications which can be affected by a spike CCU6 CAPCOM2 and GPT inputs e Port inputs Interrupts input Applications which should not be affected by a spike due to faster rising slope t which is necessary for the application due the interfac
59. r settling time ECC X 002 Incorrect ECC Error Indication for DPRAM Under certain conditions the ECC error flag for the dual port memory DPRAM may indicate an error when none exists Conditions under which ECC error is incorrectly indicated ECC memory protection has been selected for DPRAM SCU MCHKCON SELDP 0 e The ECC check is enabled for DPRAM 5 0 1 A concurrent read and write access is made to the same byte or word in the DPRAM possible due to instruction pipeline Under the above conditions an ECC error may be indicated for DPRAM flag SCU ECCSTAT DP 1 although there is no error in DPRAM It should be noted that despite the incorrect ECC error indication the data are delivered error free and the ECC logic still functions correctly correcting data single bit errors if present There is no data corruption in this case The ECC bits that were written are generated correctly as well as check and correction is not affected for that was read This problem is limited to the DPRAM All other SRAM memories cannot perform concurrent read and write accesses and therefore cannot have this issue Workaround Use parity protection for DPRAM SCU_MCHKCON SELDP 1 Single bit errors will be correctly indicated by parity logic but will not be corrected Errata Sheet 26 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Er
60. ransition of MHDS CRAM from 1 to Og is correct 006 Transmission in ATM Loopback mode When operating the E Ray in ATM Loopback mode there should be only one transmission active at the same time Requesting two or more transmissions in parallel is not allowed To avoid problems a new transmission request should only be issued when the previously requested transmission has finished This can be done by checking registers TXRQ1 2 3 4 for pending transmission requests FlexRay ALH007 Reporting of coding errors via TEST1 CERA B When the protocol engine receives a frame that contains a frame CRC error as well as an FES decoding error it will report the FES decoding error instead of the CRC error which should have precedence according to the non clocked SDL description Errata Sheet 61 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description This behaviour does not violate the FlexRay protocol conformance It has to be considered only when TEST1 CERA B is evaluated by a bus analysis tool FlexRay 1 009 Return from test mode operation The E Ray FlexRay IP module offers several test mode options e Asynchronous Transmit Mode Loop Back Mode RAM Test Mode O Test Mode To return from test mode operation to regular FlexRay operation we strongly recommend to apply a hardware reset via input eray reset to reset all E Ray interna
61. rata Description ESR X 002 ESREXSTAT1 and ESREXSTAT2 Status Bits can be Cleared af ter a Write Access During a write access to any register bits in registers ESREXSTAT1 2 can be cleared inadvertently ESREXSTAT1 2 store event s that can trigger various ESR functions Workaround 1 Make sure that the trigger signals are still active when the associated service routine runs so the trigger source can be evaluated by software 2 Disable write access to registers CLRESREXSTAT1 2 by clearing bit 8 at word address 00 F008 Use a read modify write sequence for this purpose to exclude other bits from this modification To clear the status bits write access to registers CLRESREXSTAT1 2 can be enabled by setting bit 8 at word location 00 F008 Use a read modify write sequence for this purpose to exclude other bits from this modification Write access is enabled by default ESR 003 Some Alternate ESRx Inputs Disabled Stand By Mode The ESR1 and ESR2 inputs can be mapped to alternate input ports Mappings are controlled by the ESREXCON1 and ESREXCON2 registers When in stand by mode the input port mappings marked DISABLED in the following table are switched off Consequently these ports can not be used as wakeup trigger inputs Table 10 Tables for XC2297H and XC229xH ESREXCON1 ESREXCON1 ESR1 XC2297H XC229xH selection Port Input 0 Port 2 4 OK OK Input
62. rising signal edge and the rising edge caused by a spike terratic S less than the ISR service time a workaround would be to clear the Errata Sheet 47 V1 6 2013 03 au 524540 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description interrupt request IR flag before the return from interrupt is done The clearing of the IR flag will avoid a further erratic interrupt The preferred solution for interrupt handling is to use the rising edge detection 4 3 Rising Edge and Falling Edge Detection Approach The rising edge detection workaround works also if both edges are used as trigger for interrupt and the following conditions are valid erratic interval 55 interval r and lt lt f erratic interval interval f 1 1 0 7 Vope Input Signal 0 3 Voop 4 4 1 1 d 1 1 cd 1 Internal Signal mmm mmm mmm 1 terratic interval p tinterval 5 Rising Edge and Falling Edge Detection Approach tinterval f PAD_X 001 Fig 4 PARITY 001 PMTSR Register Initialization The PMTSR register content after start up is 0100 meaning the parity logic for SBRAM is not in standard mode of operation Workaround If parity will be used as Memory Control mechanism for SBRAM it must be enabled by initializing the PMTSR register with 8000 Errata Sheet 48 V1 6 2013 03
63. s either of the following two sequences can be used to enable the protocol Sequence 1 Write the initial output value to the port pin through _ Enable the output driver for the general purpose output through Pn IOCRx Enable USIC protocol through CCR MODE Select the USIC alternate output function through IOCRx Sequence 2 Enable USIC protocol through CCR MODE Enable the output driver for the USIC alternate output function through Pn IOCRx Similarly after the protocol is established switching off the USIC channel by reseting CCR MODE directly might cause undesired transitions on the output pin The following sequence is recommended Write the passive output value to the port pin through OMR Enable the output driver for the general purpose output through Pn IOCRx Disable USIC protocol through CCR MODE Errata Sheet 72 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description USIC_AI H003 PSR RXIDLE Cleared by Software If PSR RXIDLE is cleared by software the USIC is not able to receive until the receive line is detected IDLE again see User s Manual chapter Idle Time For UART based busses with higher traffic e g LIN it is possible that sometimes the next frame starts sending before PSR RXIDLE is set 1 by hardware again This generates an error A solution is that the PSR RXIDLE bit is not cleared in software
64. se external bus control signals are held inactive during the internal LXBus access ECC X D002 Initialization of the Read Control Logic In chapter ECC Error Handling 8 14 3 of the User s Manual version 1 1 the following note should be added Note The state of the read control logic must get cleared after initialization of a RAM with ECC enabled This is achieved with a read operation from one Errata Sheet 74 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description location in each of the RAMs which was initialized before This read operation must get executed before enabling the corresponding ECC trap RESET X D001 Reset Types of Trap Registers The reset type of SCU registers TRAPDIS TRAPSET TRAPNP and TRAPNP1 is an Application Reset In the next revision of the user s manual the reset type of this registers will be changed from a Power on Reset to an Application Reset Errata Sheet 75 V1 6 2013 03
65. ster RCV should be updated with this value Erroneously RCV RCV 11 0 holds the calculated value in the range pClusterDriftDamping pClusterDriftDamping instead of zero Scope The erratum is limited to the case where the calculated rate correction value is in the range of pClusterDriftDamping pClusterDriftDamping Effects The displayed rate correction value RCV RCV 11 0 is in the range of pClusterDriftDamping pClusterDriftDamping instead of zero The error of the displayed value is limited to the range of pClusterDriftDamping pClusterDriftDamping For rate correction in the next double cycle always the correct value of zero is used Workaround A value of RCV RCV 11 0 in the range of pClusterDriftDamping pClusterDriftDamping has to be interpreted as zero FlexRay 1 096 Noise following a dynamic frame that delays idle detec tion may fail to stop slot Description If in case of noise the time between potential idle start on X and CHIRP on see Protocol Spec v2 1 Figure 5 21 is greater than gdDynamicSlotldlePhase the E Ray will not remain for the remainder of the current dynamic segment in the state wait for the end of dynamic slot rx Instead the E Ray continues slot counting This may enable the node to further transmissions in the current dynamic segment Scope Errata Sheet 36 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line
66. the appropriate message object data frame triggered by the first remote frame wins the arbitration it will be sent out and NEWDAT is not reset This leads to an additional data frame that will be sent by this message object clearing NEWDAT There will however not be more data frames than there are corresponding remote requests Errata Sheet 67 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description remote CAN Bus request remote data data request loss of arbitration data MultiC AN object m data set data l object p object clear clear set clear NEWDAT NEWDAT NEWDAT by HW by HW by HW Figure7 Loss of Arbitration OCDS X H003 Debug Interface Configuration by User Software If the debug interface must be re configured the sequence of actions to follow is activate internal test logic reset by installing SCU DBGPRR TRSTGT 0 disable debug interface by installing SCU_DBGPRR DBGEN 0 install desired debug interface configuration in 5 0 DBGPRR 11 0 activate pull devices if internal will be used by installing Px IOCRy accordingly 5 enable debug interface by installing 5 0 DBGPRR DBGEN 1 6 release internal test logic reset by installing 5 0 DBGPRR TRSTGT 1 BONS These steps must be performed as separate sequential write operations 001
67. tic slots gSyncNodeMax should be configured to be greater than or equal to the number of sync frames in the cluster FlexRay Al 094 Sync frame overflow flag EIR SFO may be set if slot counter is greater than 1024 Description If in the static segment the number of transmitted and received sync frames reaches gSyncNodeMax and the slot counter in the dynamic segment reaches the value cStaticSlotIDMax gSyncNodeMax 1023 gSyncNodeMax the sync frame overflow flag EIR SFO is set erroneously Scope The erratum is limited to configurations where the number of transmitted and received sync frames equals to gSyncNodeMax and the number of static slots plus the number of dynamic slots is greater or equal than 1023 gSyncNodeMax Effects In the described case the sync frame overflow flag EIR SFO is set erroneously This has no effect to the POC state Workaround Configure gSyncNodeMax to number of transmitted and received sync frames plus one or avoid configurations where the total of static and dynamic slots is greater than cStaticSlotIDMax FlexRay 1 095 Register RCV displays wrong value Description Errata Sheet 35 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description If the calculated rate correction value is in the range of pClusterDriftDamping pClusterDriftDamping vRateCorrection of the CSP process is set to zero In this case regi
68. til the next instruction enters the Memory stage of the pipeline i e until a further single step is performed 2 When the pipeline is running empty due to mispredicted branches and a relatively slow program memory with many wait states servicing of the trap is delayed by the time for the next access to this program memory even if vector table and trap handler are located in a faster memory However the situation when the pipeline prefetcher are completely empty is quite rare due to the advanced prefetch mechanism of the 1665 V2 core INT X H004 SCU Interrupts Enabled After Reset Following a reset the SCU interrupts are enabled by default register SCU INTDIS 0000 This may lead to interrupt requests being triggered in the SCU immediately even before user software has begun to execute In the SCU multiple interrupt sources are ORed to a common interrupt node of the CPU interrupt controller Due to the ORing of multiple interrupt sources only one interrupt request to the interrupt controller will be generated if multiple sources at the input of this OR gate are active at the same time If user software enables an interrupt in the interrupt controller SCU x1C which shares the Errata Sheet 64 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description same node as the SCU interrupt request active after reset it may lead to the effect of suppressing the
69. tstrap Loader ECC_X 002 Incorrect ECC Error Indication for DPRAM 26 ESR_X 002 ESREXSTAT1 and ESREXSTAT2 Status 27 Bits can be Cleared after a Write Access ESR X 003 Some Alternate ESRx Inputs Disabled New 27 Stand By Mode ESR X 004 Wrong Value of SCU RSTCONx Registers New 29 after ESRy Application Reset FlexRay_Al 087 After reception of a valid sync frame 30 followed by a valid non sync frame in the same static slot the received sync frame may be ignored FlexRay_Al 088 A sequence of received WUS may 30 generate redundant SIR WUPA B events FlexRay_Al 089 Rate correction set to zero in case of 31 SyncCalcResultMISSING TERM FlexRay_Al 090 Flag SFS MRCS is set erroneously 32 although at least one valid sync frame pair is received Errata Sheet 18 V1 6 2013 03 2200 Derivatives 2000 Family High Line Cafineon Short Errata Description Table 6 Functional Deviations cont d Functional Short Description Chg Pg Deviation FlexRay_Al 091 Incorrect rate and or offset correction 33 value if second Secondary Time Reference Point STRP coincides with the action point after detection of a valid frame FlexRay_Al 092 Initial rate correction value of an 33 integrating node is zero if pMicrolnitialOffsetA B 0x00 FlexRay AI 093 Acceptance of startup frames received 34 after reception of more than gSyncNodeMax sync frames FlexRay_Al 094 Sync
70. unctional Deviations BROM 006 Baud Rate Detection for CAN Bootstrap Loader In a specific corner case the baud rate detected during reception of the initialization frame for the CAN bootstrap loader may be incorrect The probability for this sporadic problem is relatively low and it decreases with decreasing CAN baud rate and increasing module clock frequency Workaround If communication fails the host should repeat the CAN bootstrap loader initialization procedure after a reset of the device BSL X 001 Quartz Crystal Settling Time after PORST too Long for CAN Bootstrap Loader The startup configuration of the CAN bootstrap loader when called immediately after PORST limits the settling time of the external oscillation to 0 5 ms For typical quartz crystal this settling time is too short The CAN bootstrap loader generates a time out and goes into Startup Error State Workaround For low performance CAN applications a ceramic resonator with settling time less than 0 5 ms can be used An alternative is the Internal Start from on chip Flash memory as startup mode after PORST Then switch the system clock to external source and trigger a software reset with CAN bootstrap loader mode selected Now the Errata Sheet 25 V1 6 2013 03 XC2200H Derivatives Infineon XC2000 Family High Line Detailed Errata Description device starts with a CAN bootstrap loader without limitation of the oscillato
71. while event for CCy occurs and bit SEEy is cleared to 0 by hardware e Inthe Write Back stage software writes CCn SEE with bit SEEx 1g intended event for CCx enabled via OR instruction and bit SEEy 7 1g e as inverse procedure software writes CCn SEE with bit SEEx Og intended event for CCx disabled via AND instruction and bit SEEy 1 In these cases another unintended event for channel CCy is enabled To avoid this effect one of the following solutions depending on the characteristics of the application is recommended to enable or disable further compare events for CAPCOM channels concurrently operating in single event mode Modify register SEE only when it is ensured that no compare event in single event mode can occur i e when SEE 0x0000 or Modify register SEE only when it is ensured that there is a sufficient time distance to the events of all channels operating in single event mode such that none of the bits in SEE can change in the meantime or e Use single event operation for one channel only i e only one bit SEMx may 1g and or Use ofthe standard compare modes and emulate single event operation for a channel CCs by disabling further compare events in bit field MODs in register CCn Mz in the corresponding interrupt service routine Writing to register CCn Mz is uncritical
72. with DMP 1 shut down and DMP M powered Workaround In response to the trap event software must explicitly clear the sticky trap flag using the SCU register DMPMITCLR before executing a debug internal application or application reset Note that this workaround does not address unexpected debug internal application or application resets which occur between the sticky trap event and Errata Sheet 49 V1 6 2013 03 2200 Derivatives Infineon XC2000 Family High Line Detailed Errata Description the clearing of the sticky flags by software To keep this exposure period as short as possible it is recommended to clear the flag early in the trap routine Note Register DMPMITCLR is protected by the register security mechanism after execution of the EINIT instruction and must be unlocked before accessing SCU_X 012 Wake Up Timer RUNCON Command The Wake Up Timer can be started and stopped by the WUCR RUNCON bit field Under the precondition that the Wake Up Timer is configured to stop when reaching zero WUCR ASP 1g and if two Wake Up Timer commands are executed successively e g start is directly followed by stop then the second command will be ignored and will not change the state of the Wake Up Timer Workaround After executing the first command wait at least 4 Wake Up Timer cycles before writing again to the WUCR RUNCON bit field and requesting the second command StartU

Errata Sheet NG for P11

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