HI5905EVAL2 User Guide
Contents
1. 0000000000000 0000000000000 FIGURE 13 HI5905EVAL2 EVALUATION BOARD GROUND PLANE LAYER LAYER 2 055 0000000000000 0000000000000 0000000000000 OSS 0 0 0 0 0 0 0 0 0 0 0 0 0 060 OO QOO OO OOCOOO 0000000000000 OQOOOOOOOOOO000 00000000000 0 0 0 0 0 0 0 0 0 0 0 FIGURE 14 HI5905EVAL2 EVALUATION BOARD POWER PLANE LAYER LAYER 3 3 7 intersil Application Note 9785 Appendix A Board Layout Continued 5555500555555 055 0000000000006 5000000000000 000000000000 0000000000000 5000000000000 200 000000000000 0V OR 0000000000000 0 0 0 0 0 0 0 0 0 0 0 0 9 65 n il OSO OSO 000000000 0000 0000 FIGURE 15 HIB5905EVAL2 EVA2. 15 AGND Analog Ground 37 D1 Data Bit 1 Output 16 AVcc Analog Supply 5 0V 38 Data Bit 0 Output LSB 17 NC No Connection 39 NC No Connection 18 D13 Data Bit 13 Output MSB 40 CLK Input Clock 19 D12 Data Bit 12 Output 41 1 Digital Supply 5 0V 20 D11 Data Bit 11 Output 42 DGND1 Digital Ground 21 D10 Data Bit 10 Output 43 DVcc4 Digital Supply 5 0V 22 NC No Connection 44 NC No Connection All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site www intersil com 3 16 intersil
3. 805 Case flash converter a four bit digital to analog converter and an amplifier with a voltage gain of 8 follow the S H circuit with 7 10uH Ferrite Bead the fourth stage being only a 4 bit flash converter Each J1 J2 2 SMA Straight Jack PCB converter stage in the pipeline will be sampling in one Mount phase and amplifying in the other clock phase Each 5 5 Protective Bumper individual sub converter clock signal is offset by 180 JP1 CTI degrees from the previous stage clock signal with the result that alternate stages in the pipeline will perform the JPH1 1 1 2 Header Jumper same operation The output of each of the three identical P1 1 2x17 Header four bit subconverter stages is a four bit digital word 2 3 4 4 TestPoint containing a supplementary bit to be used by the digital error correction logic The output of each subconverter U1 1 Intersil HIS9OSIN 14 Bit 5 stage is input to a digital delay line which is controlled by MSPS A D Converter the internal clock The function of the digital delay line is to U4 1 Ultrafast Voltage time align the digital outputs of the three identical four bit Comparator subconverter stages with the corresponding output of the U2 U3 2 Octal D type Flip flop fourth stage flash converter before inputting the sixteen bit result into the digital error correction logic The digital error 3 13 intersil Application Note 9785 correction logic uses the supplementary bits to correct any er
4. At the falling H5 R6 2 14 99 1 10W edge of the input analog signal is sampled on the bottom 805 Chip 1 plates of the sampling capacitors In the next clock phase 2 R7 1 49 90 1 10W the two bottom plates of the sampling capacitors are 805 Chip 1 connected together and the holding capacitors are switched to R8 R9 R10 R11 R20 5 2490 1 10W the amp output nodes The charge then redistributes 805 Chip 196 between Cs completing one sample and hold cycle 1 Trim Pot The output of the sample and hold is a fully differential USUS USERS sampled data representation of the analog input The circuit C22 C24 C27 C29 C31 10WVDC 20 EIA eas not only performs the sample and hold function but can also C33 C35 C39 C41 C42 convert a single ended input to a fully differential output for C44 C46 the converter core During the sampling phase the pins C1 C2 C4 C6 C7 C8 28 Cer 50WVDC see only the on resistance of the switches and Cs The C9 C11 C13 C14 C15 10 805 Case Y5V relatively small values of these components result in a typical C17 C20 C21 C23 C25 Dielectric full power input bandwidth of 100MHz for the converter 5 E 2 22 As illustrated the 5905 Functional Block Diagram and C45 C47 the timing diagram contained in Figure 18 three identical m AIR pF Cer Cap 50WVDC pipeline subconverter stages each containing a four bit 10
5. voltages is made available to the user to help simplify circuit design when using a differential input This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature The DC voltage source has a temperature coefficient of about 200ppm C The difference between the converter s two internally generated voltage references is 2V For the AC coupled differential input Figure 1 if is 2Vp p sinewave with ViN being 180 degrees out of phase with the converter will be at positive full scale when the Viy input is at Vpc 1V and the input is at Vpc 1V Vip Viy 2V Conversely the ADC will be at negative full scale when the Viy input is equal to 1V and is at 1V Vint Viy 2V It should be noted that overdriving the analog input beyond the 2 0 fullscale input voltage range will not damage the converter as long as the overdrive voltage stays within the converters analog supply voltages In the event of an overdrive condition the converter will recover within one sample clock cycle 45V 5V Vint A Vin 2 0Vp p VDC 4 0V FIGURE 24A VIN k Viy un 2 0Vp p 1 0V lt VDC lt 4 0V FIGURE 2B Vint Vin 2 0Vp p VDC 1 0V OV ov FIGURE 2C FIGURE 2 DIFFERENTIAL ANALOG INPUT COMMON MODE VOLTAGE RANGE Evaluation Board Layout and Powe
6. 0000 SVAN o o oo pe OG G ER 65 C 600 0000000000000 o e o o o o 000 0000000000000 ooo 0000000000000 ooo 0000000000000 0000000000000 o g eve O00 0000000000000 u15805E VAL 0000000000000 REV S N 0000000000000 o o o ANALOG PROTO FIGURE 11 5905 2 EVALUATION BOARD PARTS LAYOUT NEAR SIDE 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0 0 0 SS RO 0 OOOOOOOOOO0000 0000000000000 0 0 0 0 0 0 0 0 0 0 0 0 O FIGURE 12 HI5905EVAL2 EVALUATION BOARD COMPONENT NEAR SIDE LAYER 1 3 6 intersil Application Note 9785 Appendix A Board Layout Continued 0000000000000 0000000000000 0000000000000 0
7. 4 intersil Application Note 9785 5905 Functional Block Diagram w kid CLOCK o CLK Vi 9 VIN STAGE 1 4 BIT 4 BIT FLASH DAC DVcc2 9 D13 MSB o D12 o D11 o D10 o D9 o D8 STAGE 4 4 BIT 4 BIT FLASH DAC STAGE 5 o D7 o D6 DIGITAL DELAY o D5 z o tt tc o o lt 9 a 04 o D3 o D2 o Di o DO LSB 9 DaNp2 tas 2 2 FLASH Denni 3 15 intersil Application Note 9785 Appendix E Pin Descriptions PIN NAME DESCRIPTION PIN NAME DESCRIPTION 1 NC No Connection 23 NC No Connection 2 NC No Connection 24 D9 Data Bit 9 Output 3 DGND1 Digital Ground 25 D8 Data Bit 8 Output 4 NC No Connection 26 Digital Ground 5 AVcc Analog Supply 5 0V 27 DVcce2 Digital Supply 5 0V 6 AGND Analog Ground 28 NC No Connection 7 NC No Connection 29 D7 Data Bit 7 Output 8 NC No Connection 30 D6 Data Bit 6 Output 9 VINt Positive Analog Input 31 D5 Data Bit 5 Output 10 VIN Negative Analog Input 32 D4 Data Bit 4 Output 11 DC Bias Voltage Output 33 D3 Data Bit 3 Output 12 NC No Connection 34 NC No Connection 13 VROUT Reference Voltage Output 35 NC No Connection 14 VRIN Reference Voltage Input 36 D2 Data Bit 2 Output
8. 5VAIN are the analog supplies and are returned to AGND Table 1 lists the operational supply voltages typical current consumption and the evaluation board circuit function being powered Single supply operation of the converter is possible but the overall performance of the converter may degrade TABLE 1 HI5905EVAL2 EVALUATION BOARD POWER SUPPLIES POWER NOMINAL CURRENT FUNCTION S SUPPLY VALUE TYP SUPPLIED 5VAIN 5 0V 5 80mA Op Amps A D AVcc 5VAIN 5 0V 5 30mA Op Amps 5VDIN 5 0V 5 3 60mA CLK Comparator Inverter 00 013 D FF s 5VD1IN 5 0V 5 14mA A D DVcc4 5VD2IN 5 0V 5 6mA A D 5VDIN 5 0V 5 3mA CLK SINEWAVE CLK 92 Sample Clock Driver Timing and I O In order to ensure rated performance of the HI5905 the duty cycle of the sample clock should be held at 50 5 It must also have low phase noise and operate at standard TTL levels A voltage comparator U3 with TTL output levels is provided on the evaluation board to generate the sampling clock for the HI5905 when a sinewave lt 3V squarewave clock is applied to the CLK input J2 of the evaluation board A potentiometer VR1 is provided to allow the user to adjust the duty cycle of the sampling clock to obtain the best performance from the ADC and to allow the user to investigate the effects of expected duty cycle variations on the performance of the converter
9. CY MHz INPUT FREQUENCY MHz FIGURE 5 EFFECTIVE NUMBER OF BITS ENOB vs INPUT FIGURE 6 TOTAL HARMONIC DISTORTION THD vs INPUT FREQUENCY FREQUENCY 75 90 80 65 5 2 a 70 z 5 5 55 60 45 1 10 100 904 10 100 INPUT FREQUENCY MHz INPUT FREQUENCY MHz FIGURE 7 SINAD vs INPUT FREQUENCY FIGURE 8 SECOND HARMONIC DISTORTION 2HD vs INPUT FREQUENCY 75 80 65 70 o 5 5 5 55 60 45 50 1 10 100 1 10 100 INPUT FREQUENCY MHz INPUT FREQUENCY MHz FIGURE 9 SNR vs INPUT FREQUENCY FIGURE 10 THIRD HARMONIC DISTORTION 3HD vs INPUT FREQUENCY 3 5 intersil Application Note 9785 Appendix A Board Layout o F84 9 swen o fo e o 0000000000000 E 0000000000000 a 5 TE W EE o oa R9 0000000000000 999 Q0 0000000000000 059 eRe c25 0000000000000 955 5VDINQOO Ph ae 5 DIGITAL PROTO 000 o E X D of fo a H 5 000 5 g 9 91 9 o o 900 SEK oe 288 o CET 9 o cop 02 2 Lie re4 6 55 T 20000 a 000 ANALOG N Q o ek OTS Bs 559 2 FB7 Hs dur d o 1
10. F Tr E5 E6 FB3 apes uF 5Vp4 9 AID DV L c31 C32 cc Ja E7 E8 FB4 T uF 5Vp2 A D DVcca FB5 5Vp R COMPARATOR C36 penunuo5 68 6 910N Application Note 9785 Appendix C Parts List REFERENCE REFERENCE DESIGNATOR QTY DESCRIPTION DESIGNATOR QTY DESCRIPTION 1 Printed Wiring Board 05 06 2 R16 R19 2 100 1 10W U7 1 Hex Inverter 805 Chip 196 P2 64 Pin Eurocard RT Angle R17 R18 2 4990 1 10W Receptacle 805 Chip 196 Ai 5620 140W Appendix D HI5905 Theory of Operation 805 Chip 1 The HI5905 is a 14 bit fully differential sampling pipelined A D R14 1 1 10W converter with digital error correction Figure 17 depicts the 805 Chip 196 internal circuit for the converters front end differential in R15 1 22 10 1 10W differential out sample and hold S H The sampling switches 805 Chip 1 are controlled by internal sampling clock signals which consist R2 R3 1000 1 10W of two phase non overlapping clock signals 1 and 805 Chip 1 derived from the master clock CLK driving the converter During the sampling phase 1 the input signal is applied to 2 e the sampling capacitors Cs At the same time the holding 209 97 capacitors are discharged to analog ground
11. LUATION BOARD COMPONENT FAR SIDE LAYER 4 8 4 ag t Uu od yi FIGURE 16 HIb905EVAL2 EVALUATION BOARD PARTS LAYOUT FAR SIDE 3 8 intersil 6 5 5 iss C18 c17 c14 atur eur 5 02 us E C16 C15 atur eur CLK 5Vp1 C11 C13 5905 C 00 013 g 68 6 910N Application Note 9785 Appendix B Schematic Diagrams Continued C39 4TuF C37 ANALOG 0 1uF c1 J1 0 1uF OPA628AU 10 5VA R2 100 R12 c3 A R a 100 4 7uF C2 0 1uF R20 OPA628U 249 5VA C44 0 1uF J p 5 42 2 CLK IN CLK CLK m o TP1 MAX9686BCSA C22 C21 Samen R9 2 R11 249 3 CW 1 CCW 249 5Vp 5Vp ViN Vpc 0 1uF Viy 3 10 intersil Application Note 9785 Appendix B Schematic Diagrams Continued DO 013 CLK 3 11 intersil cL E1 E2 FB1 5V 5VAIN us AVcc OP AMPS T 5VDIN DGND AGND AND DGND TIE TOGETHER AT A SINGLE POINT WHERE THE POWER SUPPLIES ENTER THE PWB E11 E12 7 5VA 5VAIN OP AMPS AGND C46 C47 4 7uF J 5VD1IN e e 5VD2IN xd E4 2 5Vp 1 C29 C30 COMPARATOR D FF AND INVERTER VIA LP
12. The HI5905 clock input trigger level is approximately 1 5V Therefore the duty cycle of the sampling clock should be measured at this 1 5V trigger level Test point TP2 provides a convenient point to monitor the sample clock duty cycle and make any required adjustments Figure 3 shows the sample clock and digital data timing relationship for the evaluation board The data corresponding to a particular sample will be available at the digital data outputs of the HI5905 after the data latency time tj of 4 sample clock cycles plus the HI5905 digital data output delay top Table 2 lists the values that can be expected for the indicated timing delays Refer to the HI5905 data sheet for additional timing information 5905 SAMPLE CLOCK INPUT j CLK AT TP2 i OD HI5905 DIGITAL DATA OUTPUT N 1 DATA N 00 013 CLOCK OUT CLK AT TP1 P2 C20 OR P2 31 i DIGITAL DATA OUTPUTS 5574 DATA N 1 FIGURE 3 EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS 3 3 intersil Application Note 9785 TABLE 2 TIMING SPECIFICATIONS PARAMETER DESCRIPTION TYP top HI5905 Digital Output Data Delay 50ns tPp1 04 Prop Delay 4 5ns tPp2 U2 3 Prop Delay 9ns The sample clock and digital output data signals are made available through two connectors contained on the evaluation board The line buffering provided by the data output latches allows for driving long leads or
13. analyzer inputs These data latches are not necessary for the digital output data if the load presented to the converter does not exceed the data sheet load limits of 100 and 15pF The P2 connector allows the evaluation board to be interfaced to the DSP evaluation boards available from Intersil Alternatively the digital output data and sample clock can also be accessed by clipping the test leads of a logic analyzer or data acquisition system onto the pins connector header P1 5905 Performance Characterization Dynamic testing is used to evaluate the performance of the 5905 A D converter Among the tests performed are Signal to Noise and Distortion Ratio SINAD Signal to Noise Ratio SNR Total Harmonic Distortion THD Spurious Free Dynamic Range SFDR and InterModulation Distortion IMD Figure 4 shows the test system used to perform dynamic testing on high speed ADCs at Intersil The clock CLK and analog input signals are sourced from low phase noise HP8662A synthesized signal generators that are phase locked to each other to ensure coherence The output of the signal generator driving the ADC analog input is bandpass filtered to improve the harmonic distortion of the analog input signal The comparator on the evaluation board will convert the sine wave CLK input signal to a square wave at TTL logic levels to drive the sample clock input of the HI5905 The ADC data is captured by a logic analyzer
14. and then transferred over the GPIB bus to the PC The PC has the required software to perform the Fast Fourier Transform FFT and do the data analysis Coherent testing is recommended in order to avoid the inaccuracies of windowing The sampling frequency and analog input frequency have the following relationship F Fs M N where is the frequency of the input analog sinusoid Fs is the sampling frequency is the number of samples and M is the number of cycles over which the samples are taken By making M an integer and odd number 1 3 5 the samples are assured of being nonrepetitive Refer to the HI5905 data sheet for a complete list of test definitions and the results that can be expected using the evaluation board with the test setup shown Evaluating the part with a reconstruction DAC is only suggested when doing bandwidth or video testing HP8662A HP8662A BANDPASS FILTER COMPARATOR VIN CLK 5905 DIGITAL DATA OUTPUT HI5905EVAL2 EVALUATION BOARD gt DAS9200 GPIB FIGURE 4 HIGH SPEED A D PERFORMANCE TEST SYSTEM 3 4 intersil Application Note 9785 HI5905EVAL2 Typical Performance Input Amplitude at 0 5dBFS 75 12 11 65 10 N a 9 9 N 8 3 45 1 10 100 1 10 100 INPUT FREQUEN
15. intersil HI5905EVAL2 Evaluation Board User s Manual Application Note Description HI5905EVAL2 evaluation board allows the circuit designer to evaluate the performance of the Intersil 5905 monolithic 14 bit 5 5 5 analog to digital converter ADC As shown in the Evaluation Board Functional Block Diagram the evaluation board includes sample clock generation circuitry a single ended to differential analog input amplifier configuration and digital data output latches buffers The buffered digital data outputs are conveniently provided for easy interfacing to a ribbon connector or logic probes In addition the evaluation board includes some prototyping area for the addition of user designed custom interfaces or circuits The sample clock generator circuit accepts the external sampling signal through an SMA type RF connector J2 This input is AC coupled and terminated in 500 allowing for connection to most laboratory signal generators In addition the duty cycle of the clock driving the A D converter is Evaluation Board Functional Block Diagram CLK IN TTL COMPARATOR DGND zi d d 1999 AN9785 adjustable by way of a potentiometer This allows the effects of sample clock duty cycle on the HI5905 to be observed The analog input signal is also connected through an SMA type RF connector J1 and applied to a single ended to differential analog input amplifier This input is AC coupled a
16. nd terminated 500 allowing for connection to most laboratory signal generators Also provisions for a differential RC lowpass filter is incorporated on the output of the differential amplifier to limit the broadband noise going into the HI5905 converter The digital data output latches buffers consist of a pair of 74ALS574A D type flip flops With this digital output configuration the digital output data transitions seen at the connector are essentially time aligned with the rising edge of the sampling clock CLOCK OUT CLK o DIGITAL DATA OUT VIN DO 013 5905 3 1 1 888 INTERSIL or 321 724 7143 Intersil and Design is trademark Intersil Corporation Copyright Intersil Corporation 2000 Application Note 9785 Reference Generator and HI5905 has an internal reference voltage generator therefore no external reference voltage is required The eval board however offers the ability to use the internal or an external reference must be connected to when using the internal reference Internal to the converter two reference voltages of 1 3V and 3 3V are generated making for a fully differential analog input signal range of 2V The 5905 can be used with an external reference The converter requires only one external reference voltage connected to the Vain pin with left open The evaluation board is configured with connec
17. r Supplies The HI5905 evaluation board is a four layer board with a layout optimized for the best performance of the ADC This application note includes an electrical schematic of the evaluation board a component parts list a component placement layout drawing and reproductions of the various board layers used in the board stack up The user should feel free to copy the layout in their application Refer to the component layout and the evaluation board electrical schematic for the following discussions The 5905 monolithic A D converter has been designed with separate analog and digital supply and ground pins to keep digital noise out of the analog signal path The evaluation board provides separate low impedance analog and digital ground planes on layer 2 Since the analog and digital ground planes are connected together at a single point where the power supplies enter the board DO NOT tie them together back at the power supplies 3 2 intersil Application Note 9785 The analog and digital supplies are also kept separate on the evaluation board and should be driven by clean linear regulated supplies The external power supplies are hooked up with the twisted pair wires soldered to the plated through holes marked 5VAIN 5VAIN1 5 5VDIN 5VD1IN 5VD2IN 5VDIN AGND and near the analog prototyping area 5VDIN 5VD1IN 5VD2IN and 5VDIN are digital supplies and are returned to DGND 5VAIN 5VAIN1 and
18. ror that may exist before generating the final fourteen bit digital data output 00 014 of the converter Because of the pipeline nature of this converter the digital Vint data representing an analog input sample is presented on Vour the digital data output bus on the 4th cycle of the clock after VouT the analog sample is taken This delay is specified as the data latency After the data latency time the data representing each succeeding analog sample is output on the following clock pulse The output data is synchronized to the external sampling clock with a data latch and is presented in offset binary format FIGURE 17 ANALOG INPUT SAMPLE AND HOLD ANALOG INPUT P PUT SN 1 HN 1 SN HN SN 4 1 SN42 HN 2 5 5 4 HN 4 5 HN 5 5 6 HN 6 INPUT S H GE 5 5 STAGE gt ELITE Bou 1 N 4 1 5 2ND STAGE B2 N 2 v STAGE 5 GEAD 3 N42 3 3 3 4 STAGE _ X X AX 4 STAG 5 N 3 5 1 5 N 2 5 3 C C Dn J C Dn 9 OUTPUT tar 5 1 Sy N th sampling period 2 holding period 3 M th stage digital output corresponding to N th sampled input 4 Final data output corresponding to N th sampled input FIGURE 18 HI5905 INTERNAL CIRCUIT TIMING 3 1
19. ted to Vain through 00 resistor R4 If it is desired to evaluate the performance of the converter utilizing an externally provided reference voltage R4 can be removed and the alternate reference voltage can be brought in through twisted pair wire or coaxial cable The latter would be the recommended method since it would provide the greatest immunity to externally coupled noise voltages In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference input pin Vain Analog Input The fully differential analog input of the HI5905 A D can be configured in various ways depending on the signal source and the required level of performance Differential Analog Input Configuration A fully differential connection Figure 1 will yield the best performance from the HI5905 A D converter Since the HI5905 is powered off a single 5V supply the analog input must be biased so it lies within the analog input common mode voltage range of 1 0V to 4 0V Figure 2 illustrates the differential analog input common mode voltage range that the converter will accommodate The performance of the ADC does not change significantly with the value of the common mode voltage Ay 5905 Vpc fA FIGURE 1 AC COUPLED DIFFERENTIAL A 2 3V DC bias voltage source half way between the top and bottom internally generated reference
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