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M5307C3 USER`S MANUAL REVISION 1.1 Matrix Design

1. 33 spy 4 7 9 33 1 e Seso oo 2 em 1 o wosooreot COP SANESESRSESEZ A nat 4 008888689885555555555888888888888 AI IRQS 4 BESs o8E 2 1805 IRQ7 55 A4 A5 AS A6 TA TS A9 CF_RSTI A10 A11 BR 12 BD A13 lt A14 A15 BWEO A16 BWE1 7 BWE2 A18 BWES 19 20 5120 A21 5121 A22 A23 R 50 5002 22 A24 PPB R_RAS1 SO2 R39 A 26 MCF5307FT90 A25 PP9 _CAS0 DOMO RAO 2 85 A26 PP10 CAST DOMI CAS1 DQM1 A27 PP11 8 CAS2 DOM2 B A 28 52 00 2 ColdFire A28 PP12 R CASS DQMS 51 CASS DOMS A29 PP13 R_DRAMW 55 55 557 DRAMW 14 B_SRAS OO R28 gt 94 SRAS 5 P E 557 59 CS6 2 149 CS6 38 588 56 DSCLK TRS 159 DSCLK TRST 655 58 55 55 1204 He oe 55 54 DSDO TDO 151 DSorrpo HS u 4 CS3 DSDI_TDI 154 DSITDI CS2 5i EC 4 lt cs2 BKPT TMS 155 BKPT TMS cst 57 C80 lt g 081 HIZ He Hiz 650 CS0 BCLKO BCLKO Mi RSTO 1721 RSTO H2 CLKIN SLOW CLKIN 102 PSTCLK 184 PSTCLK 8588 scl Fos DA 1 5556 EDGESEL EDGESEL 8
2. R51 T4 HARD RESET 47K id 81 w T6 16 v 17 d 5 vec 7 gt SENSE RESET D2 Ro 6 4 RESET Y 115 T2 coNrRoL H GREENLED 270 4 GND 0 1 UF 10 15 uoo vost 9121 TLC77331D Qe TH 101 voso F2 1016 5 Tg 02 vo29 BALE gt 184 vos Z IOCHRDY SAO 20 04 1 027 Fs 51 vos 1026 P BD CS 21 voe 1025 CF_RSTI CS3 gt gt 56 07 1 024 Fz 26 08 57 109 1022 45 6120 28 1 010 1 021 41 Voltage Supervi ETH IRQ3 29 011 vO20 Fay dB IRQ3 28 1 1012 us ETH_RESET 1013 018 16 GREEN LED Sh 1014 vo17 RESIN n x Hz 3 11015 2 VIYOR vec 5 SENSE 45 44 vecoj RESET 13 TDI IN 0 R7 33 ispEN NC 33 IMS NC 1 200 41 2 1 REF BCLK FPLA gt vo 1 2 RESET GND1 atr GND GOEO 0 1 UF E ispLSI2032V 100LJ SMT socket d spo 43 3 SDI 2 5 MODE gt TL 5 SCLK C54 C14 C30 C113 C19 01UF 01UF 0 1UF 0 1 UF 3 3 4 4 Re 47K 45 R5 47K w 47K e 47 4 R11 47K ex e 6 aix 8 c2 0 01 UF MCF5307 Evaluation Board Eze Document Number Rev B MCF5307 PLD 30 late Thursday April 01 1999 Bheet 7
3. 66 5 3 DI DI GND aen I OD D D D 67 Table 13 The LA4 Connector assignment 2 SIGNAL NO NAME 2 4 1 BCLKOB R CAS2 R CASO R CAS3 a DRAMW R SCKE TOUTO DGSEL A gt ajaja t zie Q 2 2 2 2 TOUT1 NC GNI GNI GNI 2 Q Pw Co ITN NH pa Table 14 The LA5 Connector assignment spe 69 4 The Debug Connector Jl MCF5307 does have backoround Debug Port Real Time Trace Support Real Time Debug Support Theecessary signalsare availableat connector Jl Table 15 The Jl Connector pin assignment shows the pin assignment Table 15 The J1 Connector pin assignment No Connect No Connect G SIGNAL NAME B RSTI round LK DM SI Connect 43 3 5V selectable NO 19 foso 16 Ground thur 70 APPENDIX A Configuring dBUG for Network Downl
4. 2 a i MEMORY MODIFY MM WIDTH ADDR DATA D EG QR REGISTER MO RM REG DATA RESET RESET RESET SET SET CONFIGURAT SHOW SHOW CONFIGURATIO IF R STER SPLAY RD REG D iG IO STEP STEP OVER SYMBOL SYMBOL LEN NE TRACE INTO TRACE lt NUM gt DBUG UPDATE DBUG UPDBUG P DATE USER rg UPUSER U MANAGEMENT FLASH VERSION SHOW VERSION DD DEBUG COMMAN SET OPTION lt VALUE gt NS SHOW OPTION NS STEP SYMBOL lt 5 gt lt A SYMB VALUE lt R SYMB gt lt L 5 gt N N COG N O N Fo Jo FR FH FN Fer D UPUSER VERSION DS KKKKKKK Zu AS Assemble AS Usage AS lt addr gt instruction The AS command assembles instructions The val absolute address specified as a hexadecimal val Ihe assembler keeps track of the address where lue for addr may be an lue or a symbol name Instruction may be any valid instruction for the target processor the last instruction s opcode was written If no address is provided to the AS command and the AS command has not been used since system reset t
5. K K KOK KOK KOK KOK K K KOK KOK KOK KOK KOK KOK KOK RIC KOK KOK KOK KOK M 18 19 20 21 22 23 24 25 26 27 M0 PIN 33 Mux Input 0 M1 PIN 4 Mux Input 1 M2 PIN EH Mux Input 2 M3 PIN 6 Mux Input 3 CA18 PIN 25 Input ColdFire driven address CA19 PIN 7 Input ColdFire driven address CA20 PIN 9 Input ColdFire driven address CA21 PIN 10 Input ColdFire driven address CA22 PIN 11 Input ColdFire driven address CA23 PIN 12 Input ColdFire driven address CA24 PIN 13 Input ColdFire driven address CA25 PIN 16 Input ColdFire driven address CA26 PIN 23 Input ColdFire driven address 27 21 Input ColdFire driven address 5 8 24 Output SDRAM input address 8 SA9 PIN 19 Output SDRAM input address A9 SA10 PIN 25 Output SDRAM input address A10 SA11 PIN 17 Output SDRAM input address A11 SA12 PIN 27 Output SDRAM input address A12 SA13 PIN 20 Output SDRAM input address A13 BAO PIN 18 Output SDRAM input address BAO BA PIN 26 Output SDRAM input address 1 select 3 2 1 01 f k KKK KK KKK KKK KK AM t Lattice attributes TIO RIO II IO ke K K K IO I K KOK KOK pLSI property CLK XCLKO CLKO DLSI property CLK CLK8MHZ SLOWCLK pLSI property ISP pLSI property PULLUP ON 12 Connecting the MCF5307 t
6. CBU43 MACRO 00 01 02 CLK EN CS 200 02 clk CLK TOUD 00 Q amp CS TEN amp CS 01 amp CS 2Q0 Q amp TEN amp CS 02 D 202 0 5 00 0 amp 201 0 6 amp equations 1 Bidirectional circuit equations OT21 TAL DA DAOE OB21 IORL IOR OB21 IOWL IOW OB21 RST L RST_H SBHEL 1 IRQ3 ETHER DB CS 1 RST_H amp CS3 ABORTML ABORTIL ABORTML clk CLK8MHZ ABORTOL ABORTOL clk CLK8MHZ RSTMH RSTIN_L CS RSTMH PORIN L BDM 1 L RST 1 1 1 DAOE CS3 L DA DAOE clk XCLKO A0 15171 5 SIZO AOIN 16 SBHE STARTISA amp 5171 6 5120 AOIN STARTISA 6 65171 amp SIZO AOIN f STARTISA amp 5171 5 SIZO AOIN CLK16MHZ CLK16MHZ CLK16MHZ clk XCLKO CLK8MHZ CLK8MHZ amp CLK16MHZ CLK8MHZ amp CLK16MHZ CLK8MHZ clk XCLKO CLK4MHZ CLKAMHZ CLK16MHZ amp CLK8MHZ CLKAMHZ clk XCLKO DA CS3 L 6 END16 amp ENDIT amp IOCS16L amp RD amp CLK8MHZ amp SBHE CS3 L 6 END8 5 ENDIT amp RD amp CLK8MHZ DLYDA amp CS3 1 DA amp CS3 L DA clk XCLK
7. o 5 Is D feo feo Jeo feo D 1 IDIOTS Co 5 D N A Co D D 45 49 E aM 53 Q 2 Jg Tabl 9 Th J5 Connector pin assignment N SIGNAL SIGNAL O NAME NO NAME BCLKOHEA 2 33 3 DER 6 Z m 3 R R_RASOSO R_RAS1_SO 5 5 DRAMW j j 10 LA2 Connector assignment SIGNAL NAME A21 64 A23 A27 11 42 cw __ A18 14 10 8 6 4 2 GND GNI GND GNI GND py 65 Table 11 The 1 Connector assignment 2 zz H N 2 5 N Q Q zi Jg Po co 05 Co Co N Table 12 LA3 Connector assignment GNAL NAME NO PIN NC 2 4 12 14 PSTCLK PSTO WE d 6 mrmop1 12 2 RXD2 RTS2 po wc cn 3 8 5 sro tem 11
8. jedes EB SDA SDA 2222222220909090009099099009290900 3 ZEEE agpo 9202 z233 Rag 5666666666666666666666666666666 gt 5555 HKPL 3 3 lt hq R22 _ 2K E P 4484 d E TA MTMOD3 DDATA 0 3 Em MTMOD2 4 7K 338i MTMODI DUE A MTMODO R25 2 R312R32 2 R33 DDATAO PLL3 3 4 7K 94 TK 947K y4 7K TOUTO TOUTO R74 ld 4 m TINO R49 C85 C86 TIN1 TINA 4 7K 1500 PF 1500 PF 10 CSL CTS2 RTS2 by BXD lt 2 IS HARD WIRED oe lt 5 1 De CTS1 3 3 RTS1 RTS1 BXD1 F RXD1 TXD1 c9 C10 12 79 C80 C81 C82 C83 itle 1500 1500 1500 1500 1500 1500PF 1500 1500 1500 1500PF 500 1500 PF 1500 MGF5207 Evaluation Board 1 Eze Document Number Rev x 5 B MCFS307 CPU 30 ate Thursday April 01 1999 Bheet 1 8 Mictor NTROL Mictor 5 Mictor DEBUG Mictor ORAM LA3 D 0 31 LAT LA4 LA5 LA2 X3 Nea NC3 X3 Noa X3 Nea gt Nes NC4 2 NC2 2 Nes 2 Nes 3 1 Nc2 NC3 3 2 2 1 Nez NC2 CLK 0
9. 02 5 4 15 6 9 1 Te 01 5 x RXD1 16 819 A 0 31 7 RTS1 Ta 012 gt 3 CTS1 1 002 75 gt 12 013 TG HX 5 74 5 2 3 C2 18 t 1 o C2 BCLKOHEADER 433 m vcc vSS 4 J3 5120 9121 VDD GND 4 10 UF TANT Size 4 C24 lt i 2 PPO BD IRQ3 JOUANT MC145407DW cis TOUTI PP1 IRQ CS1 TINO s amp 2 CS2 1083 10 UF TANT TOUTO T 87 56 CS7 c 4 12 CF_RST TS SDA 13 14 5 TXD1 TXD2 IRQ1 13 PPG RXDI RXD2 IRQ5 RTS1 RTS2 E CS0_HEADER 17 7 24 CTST CTS2 90 19 2 A25 MTMODO Hiz 10 UF TANT BWE1 21 22 26 R 5 R_CAS1 DQM1 3 BWE2 23 24 A27 R_CAS2 DQN2 R_CAS3 DOM3 5 2 25 A28 R_RASO SO R_RAS1 SO2 m 3 E OE 29 R_DRAMW R SRAS TXD2 14 on CS4 a 32 A30 SCAS SCKE RXD2 12 555 34 A31 5 RTS2 gt 13 012 TX2 4 RSTO CTS2 10 002 RX2 7 719 RW 119 1816 X 2 Lo AS 6 E vost 1 ils lt 16 8 as E t voc vss 5 t VDD GND 4 SION y e MC145406DW AUXILAR 43 3 i R2 4 7K Ji 0 1 UF R34 1 2 BKPT TMS 4 7K Bus osc e 4 XDSCLK TRST 2 2 5 3 022 BDM RSTI gt a oso TDI vec H4 t 1 12 0500 TDO pgs PST2 13 14 iz R35 PSTO 15 16 DDATAG EROS CU HS SLOW DDATAT GND 22 8 433 OSC 45 MHZ DDATA O 3 X 23 25
10. Ethernet 10 Base T u12 R18 800 HEX 501 MSD6 SLOT go 502 MSD5 BNCSW 503 EX U13 Ethernet E2 SD4 MSD3 ec gt lt 2 7 RI7 505 MSD2 EECK HE 2 sk NC x SD6 MSD1 EEDO 64 5101 4 7K 507 800 EED1 x 508 509 5010 EECS vec 2 5 5011 i cs MA 0 19 gt 5012 5 7 3013 56 GND Te 5014 25 ds 8015 DAS 58 AT93C46 10SC 2 7 not populated during assembly F sao gt 22 99 2 SA1 EX SA2 PA2 62 Pes SA4 PAO SAS SAG Fe amp ETH SAB IRQ4 27 T SA9 IRQS 50 SA10 1809 54 SA11 18010 53 R12 IRQ11 SA14 IRQ12 22 SA15 IRQ15 Ethernet aei SA16 06 SA17 SA18 1016 vec 4 5 SA19 5 5 45 z bn s 25 amp IocHRDY 8 BALE 2 gt BALE 7 GND aos 59 14 svscik x HE ds OSC 20 MHZ R14 RIS Ens or X R16 4 7K XH ow BNCEN 4 7K 22 23 SMEMR BH 35 TX 40 P5 ETH gt 2 RX ES RX 24 AEN CD 2 iD
11. base Thisisthe default radix for use inconverting number from theirASC text representation to the internal quantity used by dBUG The default is hexadecimal base 16 other choices are binary base 2 octal base 8 and decimal base 10 client Thisisthe network Internet Protocol IP address of the board For network communications the clientIP isrequired be set to a unique value usually assigned by your local network administrator server Thisisthe network IP address of the machine which contains files accessible via Your local network administrator will have this information and can assist in properly configuring a TFTP serwae not exist gateway This is the network IP address of the gateway for your local subnetwork If the clientIP address and server IP address are not on the same subnetwork then thisoption must be properly set Your localnetwork administrator will have this information netmask This i amp he network address mask to determine ifuse of a gateway is required Thisfieldmust be properly set Your localnetwork administrator will have this information filename Thisisthe default filename to be used for network download ifno name is provided to the DN command filetype Thisisthe default filetype to be used for network download ifno type is provided to the DN command Valid values are s rec
12. exit and transfer to dBUG CHAPTER 3 HARDWARE DESCRIPTION AND RECONFIGURATION This chapter provides a functional description ofM amp hE7C3 board hardware With the description given here the schematic diagram providedta end of thismanual the user can gain a good understanding of the board s design In thismanual an activelow signalisindicatedby a preceding the signal name in this text and a bar over the signal name in the schematics 3 1 THE PROCESSOR AND SUPPORT LOGIC This part ofhe Chapter discusses the CPU and general supporting logicon the M5307C3 board Seb ids The Processor The microprocessor used in the M5307C3 isthe highly integrated MCF5307 32 bit processor MCF5307 uses a ColdFireG processes the core with 8K bytes of unified cache two UART channels two Timers 4K bytes of SRAM Motorola M Bus Module supporting the two byte wide parallelI O port and the supporting integrated system logic Allthe registers of the core processor are 32 bitwide except for the Status Register SR which 1516 bits wide Thisprocessor communicates with external devices over a 32 bit wide data bus DO D31 with support for 8 and 16 bit ports This 5 4 G Bytes of memory Space using internalchip selectlogic Allthe processor s signalsare availablethrough mictor connectors LA1 LA2 LA3 LA4
13. 8 SA9 PIN 95 Output SDRAM input address A9 SA10 PIN 25 Output SDRAM input address A10 SA11 PIN 7 Output SDRAM input address A11 SA12 PIN 27 Output SDRAM input address A12 SA13 20 Output SDRAM input address A13 BAO PIN 18 Output SDRAM input address BAO PIN 26 Output SDRAM input address 1 select M3 M2 M1 M0 W lt CA lt CC CK k lt k k lt X lt Xk lt k k k k k k k k k X X W Lattice attributes W lt CA lt CK x C k amp k amp k lt k k lt k k k k k k k k k k k k k X X W pLSI property CLK XCLKO CLKO pLSI property CLK CLK8MHZ SLOWCLK pLSI property ISP ON pLSI property PULLUP ON pLSI property 1 AS RESET OFF equations p FERE AE E HE HE HE TE FE FE FE HE E E E E E COMBINATORIAL Logic Only P ESSSSEASEASEASEASEASEASEASEASTEASAASEASESSET when select 0 then SA8 CA18 SA9 CA19 SA10 CA20 BAO CA21 BA1 CA22 when select 1 then SA8 CA19 SA9 CA20 SA10 CA21 BAO CA22 BA1 CA23 when select 2 then SA8 CA19 5 9 21 5 10 22 0 23 1 24 when select 3 then 5 8 18 SA9 CA19 SA10 CA20 5 11 21 BA0 CA22 1 23 when select 4 then SA8 CA19 5 9 20 10 21 11 22
14. THE CONNECTORS AND THE EXPANSION BUS 59 VE The Terminal Connector P4 59 49 Logical Analyzer connectors LA1 5 and Processor Expansion Bus 93 The Debug Connector J1 70 J4 amp 45 APPENDIX Configuring dBUG for Network Downloads 1 A 1 Required Network Parametersl A 2 Configuring dBUG Network Parameters 1 3 Troubleshooting Network Problems 3 APPENDIX ColdFire to ISA IRQ7 and Reset Logic Abel code 1 APPENDIX C Schematics 2 APPENDIX D SDRAM MUX PAL EQUATION 1 APPENDIX E SDRAM MUX WHITE PAPERI APPENDIX EVALUATION BOARD BOM1 MCF5307EVM_BOM 1 TABLES Table Table Table Table Table Table Table Table JPl Upper Lower Half BOOT JP2 50 select dBUG Commands 5307 3 memory map The P4 Terminal Connector pin assignment The P3 Connector pin assignment The J3 Connector pin assignment The J4 Connector pin assignment Figures Figure Figure Figure Figure Figure Ow Block Diagram of the boardl 3 Pin assignment for Terminal 9 Jumper Table Locationsl 10 System Configuration 11 Flow Diagram of dBUG Operational Mode 2 4 1 15 1 15 2 9 53 60 61 61 63 1 INTRODUCTION THE 5307 3 BOARD 1 1 INTRODUCTION The M5307C3 is a versatile singbeard computer based on MCF5307 ColdFire Processor It used as a powerfu
15. 0 23 1 24 when select 5 then SA8 CA19 5 9 21 5 10 22 5 11 23 BA0 CA24 1 25 when select 6 then SA8 CA19 5 9 21 5 10 23 5 11 24 0 25 1 26 when select 7 then SA8 CA18 SA9 CA19 SA10 CA20 5 11 21 SA12 CA22 BAO CA23 BA1 CA24 when select when select when select 8 the SA SA SA SA BA BA 9 the SA SA SA SA BA BA h0A SA SA SA SA BA BA n SA8 CA19 9 20 10 21 11 22 12 23 0 24 1 CA25 n SA8 CA19 9 CA21 10 CA22 11 CA23 12 CA24 25 1 CA26 then 9 CA21 10 23 11 24 12 25 O CA26 1 CA27 SA8 CA19 WAKKKKKKKKKKKKKKKKKKKKKK X k k k k k k k k k k k amp k amp k k k amp k k k k k k ri X W gt Test Vector Section WAKKKKKKKKKKKKKKKKK lt k x k k k k k k k k k k k k k amp k amp k k amp k k k amp k k W test_vectors M0 1 2 M3 Test Vector M3 2 1 18 19 CA20 CA21 CA22 CA23 24 SA8 SA9 SA10 5411 SA12 BAO 0 0 0 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X15 0 0 0 1 1 0 1 0 1 0 1 0 1 0 X X X X X X X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X 0 0 1 1 1 0 1 0 1 0 1 0 1 0 X X X X
16. HE o VDD17 5 u 1 02 3 01 vsst D1 852 Do vss 353 vssa DU 555 DU2 48 vsss pus 28 vss7 Hat 858 CB 25 859 C107 C108 C109 C110 C111 VSS10 CB3 53 O1UF VSS11 105 VSS12 CBs 10850 t 4 4 vssi3 13729 VSS14 CB7 VSS15 VREF1 3 3 vssig VREF2 146 17 VSS18 lt BCLK_SDRAMI0 3 CLKO T 1 t 1 t 1 t 22 1 Nco CLK1 4 7 BOEK SDRAME NC1 CLK2 50 15247163 SDRAM3 C95 C97 C99 C100 C101 C102 C103 C105 gt 61 3 109 0 1 UF o1UF orur o1UF 0 1 UF EIN Nes NGS FHR Me MOF5307 Evaluation Board NOS Noto 108 145 T 2 d d 2 164 7 Nato Er Eze Document Number Rev B MCF5307 SDRAM 3 0 100 Unbuffered 1 Bank x 64 DIMM 8M or 16M support up to 512M late Thursday April 01 1999 Bheet amp D 0 31 D
17. J5 1 JP7 JP1 AUX erminal ion 11 JP8 9 JP13 12 Figure 3 Jumper Table Locations us JP2 BACKGROUND DEBUG Carrector RS232 TERM INAL orPC 17 SDRAM I MM Figure 4 System Configuration M CROPROCESSOR EXPANSDN BUS 1 10 SYSTEM POWER UP AND NITIAL OPERATION Now that you have connected all the cables you may apply power to the board After power is applied the dBUG initializes the board then display power up message on the terminal which includes the amount of the memory present Hard Reset DRAM Size 8M 2000 0x300 Copyright 1997 1998 Motorola Inc All Rights Reserved ColdFire amp MCF5307 EVS Debugger Vx x x 199x Enter help for help dBUG The board is now ready for operation under the control of the debugger as described in Chapters 2 If you do not get the above response perform the following checks 1 Make sure that the power supply is properly set and connected to the board 2 Check that the terminal and board are set for the same character format and baud 3 Press the red RESET button to insure that the board has been initialized properly If you still are not receiving the proper response your board may have bee damaged in shipping Contact Cadre for further instructions 1 11 M5307C3 Jumper Setup jumpers on the board are d
18. 1 Q 89 X 2 15 MEMW AGND1 X 2 2 30 1 MEMR 80 3 H4 59 LIV 2 t AVDD1 49 a 3 AVDD2 ae RXL TPRX AVDD3 TPRX FERRITE_BEAD 7 10 4 d Ten 48 AGND2 X 0 C65 C64 8 9 AGND1 RXI TPRX 10 UF TANT 0 01 UF AGND2 55 x lt FO E AGND3 1 NC veci 5 FD22 101G A E VCC2 72 GND1 V6C3 Rig Rio GND2 49 9 49 9 603 100 x10 GND4 GNDO eur DM9008F x L O cS RJ45 Thur 0 01 UF 7 7 1 D3 R21 M gt C63 C47 C31 C34 C33 GREEN LED 270 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF 4 ilie MCF5307 Evaluation Board Eze Document Number Rev MCF5307 ETHERNET 30 late Thursday April 01 1999 Bheet 5 00 31 gt RS2
19. If no value for data is provided then the MM command enters intoa loop The loop obtains a value for data sets the contents of thecurrent address to data increments the address according to the data sizeand repeats The loop terminates when invalidentry for the data value is entered i e a period This command firstalignsthe startingaddress for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To set the byte at location 0x00010000 to be OxFF the command is mm b 10000 FF To interactively modify memory beginning at 0x00010000 the command is mm 10000 224418 RD Register Display Usage RD reg The RD command displays the register set of the target If no argument for reg is provided then all registers are displayed Otherwise the value for i is displayed Examples To display all the registers and their values the command is rd To display only the program counter the command is rd pc 2 4 19 RM Register Modify RM Usage RM reg data The RM command modifies the contents of theregisterreg to data The value for reg isthe name of the register and the value for data may be a symbol name or it is converted according to th user defined radix normally hexadecimal dBUG pr
20. M2 amp M3 amp CA22 M2 M2 amp amp M3 amp CA22 M3 amp CA22 M2 amp M3 amp CA23 M2 amp M3 amp CA23 M3 amp CA21 amp 1 amp amp amp amp amp amp amp M2 amp M3 amp CA22 M2 amp M3 M2 amp M3 M2 amp M3 M2 amp M3 amp amp amp amp 2 amp amp CA22 CA23 CA23 CA24 CA24 M3 M3 amp CA20 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 17 17 SA12 MO amp 1 amp M2 amp M3 amp CA22 0 amp 1 amp M2 amp 6 CA23 MO 6 6 M2 amp amp CA24 IMO amp 1 6 M2 amp amp CA25 BAO amp 6 M2 amp M3 6 CA21 MO amp M2 6 M3 amp CA22 MO amp 1 6 2 6 M3 amp CA23 amp amp 2 amp M3 CA23 M0 amp amp M2 amp M3 amp CA23 IMO amp 1 amp M2 amp amp CA24 MO amp amp 2 amp M3 amp CA24 MO amp 1 amp M2 amp amp CA25 IMO amp 1 amp 2 6 M3 6 CA25 amp 1 6 M2 amp 5 CA26 1 amp amp 2 amp M3 amp CA22 MO amp M2 amp M3 amp CA23 MO amp Ml amp M2 amp M3 amp CA24 amp 1 amp 2 amp M3 amp CA24 0 6 Ml amp M2 amp M3 amp CA24 amp amp M2
21. RCR DCR rd rd Receive Configuration Register Data Configuration Register 0000 0x0010 2 PSTART rd CLDAO wr Remote Next Packet Pointer Local Next Packet Pointer Address Counter Lower Odd registers NATURAL16 PSTART NATURAL16 RNPP NATURAL16 LNPP NATURAL16 ACL ae NATURAL16 reservedl NATURAL16 reserved3 NATURAL16 TCR as NATURAL16 IMR page2 regs 58390 The main purpose for compatible to facilitateetwork download The dBUG driver is 100 DN download command The Ethernet Bus interrupt request line is connected via the 2032V PLD The on board ROM MON from a network to supported ar 3 7 THE CONNECTORS thissetup isto allow the use of Ethernet card S Record COFF Transmit Configuration Register rd Interrupt Mask Register rd NE2000 refer to chapter 2 for network NE2000 compatible to ITOR isprogrammed to allow a user to download files memory in different formats Ihe current formats ELF or Image AND THE EXPANSION BUS There are 8 connectors on the M5307C3 which are used to connect theard to external I O devices and or expansion boards This section provides a brief discussion and the pin assignments of the connectors mn The The signalson UARTI drivethe Terminal Th connecting the board Terminal e M5307C3 Connector
22. X X Xl 0 1 0 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X l j Dub OUD 53 0 e 01 XXX e 0 1 1 0 1 0 1 0 1 0 1 0 1 01 gt 1 Q 1 1 1 1 0 1 0 1 0 101 0 1 0 XDX X K X X X y 4 CA25 CA26 CA2 1 01 gt 1 1 0 2I X X X X X X X APPENDIX FSDRAM MUX WHITE PAPER AN1802 D Motorola Order Number 5 1999 REV 0 1 ea MICROPROCESSORS Application Note Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs William R Benner Jr 68K ColdFire Applications Team Pangolin Laser Systems Motorola Inc William_Benner msn com imaging oakhill sps mot com A special note of appreciation goes to William Benner Jr of Pangolin Laser Systems the primary author of this application note Mr Benner is gracious enough to allow Motorola to share his experience and knowledge with other customers This application note shows how to interchange various standard synchronous DRAM SDRAM dual inline memory modules DIMMs in a ColdFire MCF5307 design without re routing the board The MCF5307 integrates a Version 3 core with an 8 KByte unified cache 4 KByte SRAM an asynchronous synchronous DRAM controller and various other popular embedded peripherals For further details on the MCF5307 refer to the MCF5307 Product Brief MCF5307 D 1 1 Intoduction As the demand for lower cost higher performance embedded
23. amp amp CA25 MO amp 1 amp 2 amp M3 amp CA25 MO amp 6 2 amp amp CA26 amp 1 amp 2 amp M3 amp CA26 db o dB IMO amp 6 M2 6 CA27 18 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 18 MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 19 19 Mfax is a trademark and Coldfire is a registered trademark of Motorola Inc ispEXPERT is a trademark of Lattice Semiconductor Intel is a registered trademark of Intel Corporation Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support
24. be swapped without re design This document details a method of connecting the MCF5307 to single sided DIMMs with 8 9 10 or 11 column address lines 11 12 or 13 row address lines and up to 2 bank address lines using a PLD design This design can support up to 512 MBytes of memory which is compatible with the MCF5307 s addressing capability 1 1 1 Definitions Before the PLD design is presented it is helpful to review some of the terminology that will be used in this document e 5307 Memory Bank This refers to any group of memories that are selected by one of the 5307 RAS 1 0 signals Thus the MCF5307 can support two SDRAM banks Note that the RAS 1 0 signals interface to the chip select signals CS on SDRAMs e SDRAM Bank This term is often used by SDRAM manufacturers to distinguish between the internal partitions or banks in a single SDRAM device For example one SDRAM component can have four internal SDRAM banks that is a 64 Mbit SDRAM is configured as 512K x 32 x 4 banks Bank selection is controlled through the bank select pins on the SDRAM e SDRAM Synchronous dynamic random access memory These operate similar to asynchronous DRAMs ADRAMs with the advantage of a synchronous clock a pipelined multibank architecture and faster speed These memories also maintain high memory density DIMM Dual inline memory module DIMMs contain rows of SDRAM components on one or both sides of the memory card
25. 25 1 26 when select h0A then SA8 CA19 5 9 21 5 10 23 5 11 24 SA12 CA25 BAO CA2 6 BA1 CA27 WK KKK KKK kok kok kok KKK KK KKK KK KKK KKK k kok KKK KKK KKK ck ckckckckck KKK KAN Test Vector Section test vectors 0 1 2 Test Vector M3 2 1 MO CA18 CA19 20 CA21 CA22 CA23 CA24 CA25 CA26 271 gt SA8 SA9 SA10 5 11 SA12 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 2 X X X X X X X 0 0 0 1 1 0 1 0 1 0 1 0 1 0 X X X X X X X MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 15 15 0 0 1 0 1 XM Er 4 Co UU yl 0 1 0 9 1 Ud 0 1 1 0 11 051 0 2 4 1 2 19 0201 lg 01 1 end X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 49 gt lt X X X X X X X 1 7 PAL Equations The following code represents the PAL equations generated by compiling the PAL ABEL HDL files using Lattice Semiconductor s freeware package ispEXPERT M System Starter Kit ISP Synario 5 01 Device Utilization Chart SDRAM Mux Controller for the MCF5307EVM Input files ABEL PLA file Device library Output files Report f
26. 287 2 7 Al 29 Ma 23 Dat 288 2 2 4 2 us 1 7 15 26 443 15 CS0 EN 48 oe vee HE 22 7 22 2080 vcc bs 18 2DIR vec 31 11 exo 28 vec 12 25 28 4 134 GND 3e 38 5 GND GND 39 GND 15 GND GND B DI16 31 2 MC74LCX16245DT 45 GND H uqg Bi Buffers MC74LCX16244DT 181 1 1 Die 2183 33 u10 D20 8 184 1 4 R71 2 Dot 94 185 20 A 24100 105 ud 1 022 111186 146 38 22 18 s joe MA18 D23 121187 IE B D23 A19 8 102 10212 19 m pes 281 2 35 B 1 200 F 575 ne 35 5 3 2B2 02616263 ae 33 026 IRQ7 202 202 22 284 24 203 203 gt IRQ7 270 00 31 2 286 2A6 i ad 287 S z 10E vcc 23 288 28 B D 19 20E 1 7 10 5 20 vec 2DIR MC74LCX244DW 4 28 Hes geld eas 21 esp GND 35 TOUTI R69 R70 A C45 MC74LCX16245DT ee T t t INITIAL RESET CONFIGURATIO j E Uni Buffers 2 5 iv oe amp 1A2 1Y2 H D1 C29 C27 C28 C46 C60 C42 C26 C44 5 22 2 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF 0 1 UF MB epe DS 4 3823 ava HS ppo 36 244 214 13 1 35 3v1 ppp
27. 4 that runs through RS 232 driver receiversar uses a 9 pin 59 used to D sub female connector P4 for toa terminal or a PC with terminal emulation software The available signals are working subssmtthe RS 232C standard Table5 The P4 Terminal Connector pin assignmentshows the pin assignment Tabl 5 Terminal Connector pin assignment IGNAL NAME Data Carrier Detect shorted to 4 amp 6 Receive data Transmit data Data Terminal Ready shorted to amp 6 Signal Ground utput Data Set Ready shorted to 1 4 Request to Send Clear to Send Not Used The Auxiliary Serial Communication Connector P3 The MCF5307 has two built imARTs One channel isnot used by the M5307C3 ROM Monitor and isavailableto the user Thissignalisavailableon port P3 The availablesignalsform a working subset of the RS 232C standard Table 6 shows the pin assignment for P3 60 Tabl 6 N DIRECT N P3 Connector pin assignment SIGNAL NAME Data Carrier Detect shorted to 4 amp 6 output Receive data Input Transmit data Th Output Output Input Input Data Terminal Ready Out Input Out shorted to 1 amp 6 Signal Ground tput Data Set Ready shorted to 1 amp 4 Input Request to Send Clear t
28. CLDAO rd PSTART wr NATURAL16 BNRY Boundary pointer rd wr NATURAL16 NCR NCR rd TBCRO wr NATURAL16 ISR Interrupt Status Register rd wr NATURAL16 1 CRDA1 rd wr NATURAL16 RBCRI1 Remote Byte Count 1 wr NATURAL16 CNTRO CNTRO rd TCR wr NATURAL16 CNTR2 CNTR2 rd IMR wr paged struct Even registers NATURAL16 PARI Physical Address Byte 1 NATURAL16 PAR3 Physical Address Byte 3 NATURAL16 PAR5 Physical Address Byte 5 NATURAL16 MARO Multicast Address Byte 0 NATURAL16 MAR2 Multicast Address Byte 2 NATURAL16 MAR4 Multicast Address Byte 4 NATURAL16 MAR6 Multicast Address Byte 6 NATURAL16 reserved 0x10000 0x0010 2 Odd registers NATURAL16 PARO Physical Address Byte 0 NATURAL16 PAR2 Physical Address Byte 2 NATURAL16 PAR4 Physical Address Byte 4 NATURAL16 CURR Current Page Register rd wr NATURAL16 1 Multicast Address Byte 1 NATURAL16 MAR3 Multicast Address Byte 3 NATURAL16 MAR5 Multicast Address Byte 5 NATURAL16 MAR7 Multicast Address Byte 7 pagel struct Even registers NATURAL16 PSTOP PSTOP CLDA1 wr NATURAL16 TPSR Transmit Page Start Address rd NATURAL16 ACU Address Counter Upper NATURAL16 reserved0 NATURAL16 reserved2 58 NATURAL16 NATURAL16 NATURAL16 reserved 0 1
29. D26 A5 058 122 D25 AG 057 voQi 201 7 056 128 22 0 0 02 48 055 150 D WOIQS oq 9 D54 149 D21 VO Q4 7384 053 H4 pat violas E22 126 11 052 142 019 05 54 1321 12 051 Hiat Dia voae 22 A18 050 5 25 TE Das Fe biz 6 vojas H 22 129 bis 17 10 09 128 047 103 D30 R SCKE 31 D46 191 29 19 153 CKE1 pas 107 Da 33 R55 8 8 115 D44 D2 R_SRAS JH 99 Dar ScLK R DRAMW WE D42 Pee 501 22 131 041 95 024 500 2 vec 1354 Dao H MODE MODE GND 113 039 93 D22 iSpGALZ2LV10 SMT socket pe 32 D21 R_CAS2 DQM2 44 ava D36 fet 020 RLCAS3 DOM3 5 085 49 F 28 HS 8 DOMO D33 27 R RAS1 SO2 45 soz os 22 Dis Reo 2 m BRAS S02 40 302 75 Did R58 433 RCRASO SOQ 114 500 030 775 4 7K 4 7K 4 7K 129 501 029 74 012 2 503 D28 E 82 027 71 010 SDA 83 SDA D26 75 05 SCL SCL D25 20 B zh 166 D22 66 165 65 D5 SAO D21 60 D4 D20 58 D3 43 3 1 019 57 D2 VDD2 57 e VDD3 017 26 VDD4 D16 22 po VDD5 015 20 p VDD6 014 HS VDD7 DISHE B VDD8 H Di VDD9 Dit Bit VDD10 010 13 Da VDD11 H VDD12 Hid D VDD13 07 07 VDD14 be VDD15 ps 8 Ds VDD16
30. Flash ROMs appear to be at address 500000000 which provides the initias tack pointer and program counter the first8 bytes of the Flash ROM The initializatiomoutine programs the chip selectlogic locates the Flash ROM s to startat SFFE00000 and the configures the rest of the internal and external peripherals Sec TA Generation 53 The processor starts a bus cycle by providing the necessary information address R W etc and asserting TS The processor then waits for an acknowledgment TA by the addressed device before itcan complete the bus isused not only to indicatethe presence of a device italso allows devices with different access times to communicate with the processor properly The MCF5307 part of the chip select logic has a built in mechanism to generate for allexternal devices which do not have the capabilityto generate TA on theirown The Flash ROM and SRAM can not generate The chip select logicis programmed by the ROM Monitor to generate internallyafter preprogrammed number of wait states order to support future expansionf the board the TA input of the processor is also connected to the Processor Expansion Bus J4 This allows the expansion boards to assert thislineto indicatetheir TA to the processor On the expansion boards however this signal should be generated through an open collec
31. If no ending address is provided then MD will display to an address that is 128 beyond the starting address This command firstalignsthe startingaddress for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To display memory at address 0 00400000 the command is md 400000 To display memory inthe data section definedby the symbols data start and data end the command is md data start To display a range of bytes from 0x00040000 to 0x00050000 the command is md b 40000 50000 To displaya range of 32 bit values startingat 0x00040000 ending at 0x00050000 the command is 1 40000 50000 This command may repeated by simply pressing the carriage return Enter key Itwillcontinue with the address after the lastdisplay address 2 4 17 MM Memory Modify MM Usage MM width addr data The MM command modifies memory at the address addr The value for address addr may be an absolute address specifiedas a hexadecimal value a symbol name Width modifies the size of the data that ismodified The value for data may be a symbol name or a number converted according to the user defined radix normally hexadecimal Ifa value for data is provided then the MM command immediately sets the contents of addr to data
32. LA5 and through 100 mil headers J1 23 24 and J5 Refer to section 3 7 for pin assignment The MCF5307 has an IEEE JTAG compatible port and BDM port used with third party tools These signals are availablgort Jl The processor alsohas the logicto generate up to eight 8 chip selects CSO0 to CS7 and support for 2 banks of ADRAM noton evaluation board or 2 banks of SDRAM on evaluation board 48 duds The Reset Logic The reset logicprovides system initializatiorrhe reset occurs during power on and asserts the signal RSTI which causes totalsystem reset The reset is also triggered by the red reset switch and resets the entire processor U5 isused to produce active low power on RESET signalwhich feeds intothe ispLSI2032 The reset switch 15 fed into U4 which generates a signalinto 05 which then drive U9 s input for reset U9 degenerates the system reset CF RSTI and Ethernet RESET ETH RST signals ROM Monitor performs the following configurations of internal resources during the initialization The instruction calatwalisdiatedand disabled The Vector Base Register VBR points to the Flash However a copy of the exception table is made at address 00000000 in the SDRAM The Software Watchdog Timer is disabled Bus Monitor enabled and internal timers are placed ina stop condition Interrupt controllerregisters are initializedith unique interrupt
33. M ictorand E xpansion Connectors Figure 1 Block Diagram of the board 1 3 SYSTEM MEMORY There are two on board Flash ROM s 020 021 U2hkhe most significantbyte and the U21 is the least significantbyte The M5307C3 comes with two 29LV004 Flash ROM s programmed with a debugger monitor firmware Both AM29LV0OA4DT Flash are 4Mbits each giving a total of l1Mbyte of Flash memory There is one 168 pin DIMM socket for SDRAM System ships with 148 Bank x 16 Bits SDRAM totaling 16M ofvolatilememory Various SDRAM configurations are supported The MCF5307 has 4K bytes organized as 1024x32 bits of internal SRAM The internal cache of the MCF5307 isa non blocking 8kbyte 4 way set associative unified instructiorand data cache with 16 byte linesize Th ROM Monitor currentlydoes not utilizethe cache but programs downloaded with the ROM Monitor can use the cache The M5307C3 evaluation board has a foot print for 512 K SRAM but is unpopulated 1 4 SERIAL COMMUNICATION CHANNELS The MCF5307 has 2 built inmMART s UARTO and UART1 with independent baud rate generators The signalsof channel one are passed through external Driver Receiversto make the channel compatible with RS 232 UARTO isused by the debugger for the user to access with a terminal In addition the signals of both channels are availabletoe mictor connectors to be viewed by a lo
34. SYSTEM CONFIGURATION 1 6 d 9 INSTALLATION AND SETUP 1 6 Unpacking 1 6 Preparing the Board for Use 1 7 Providing Power to the Board 1 7 Selecting Terminal Baud Rate 1 8 The Terminal Character Format 1 8 Connecting the Terminal 1 8 XO XO O O OB Q PFP Using a Personal Computer as a Terminal 1 8 Top SYSTEM POWER UP AND INITIAL OPERATION 1 13 lets M5307C3 Jumper Setup 1 13 LelT ls Jumper 1 Flash Upper Half Lower Half Boot 1 14 1 11 2 Jumper JP2 This jumper selects between 50 to Flash or a header 1 15 7 2 USING THE BDM 1 15 CHAPTER 2 2 1 Broad WHAT IS 2 1 222 OPERATIONAL PROCEDURE 2 3 2x23 System Power up 2 3 2 522 System Initialization 2 5 2 2395 System Operation 2 6 Zug TERMINAL CONTROL CHARACTERS 2 7 2 4 dBUG COMMAND SET 2 8 2 4 1 AS Assemble AS 2 11 2 4 2 BC Compare Blocks of Memory BC 2 13 2 4 3 BF Block of Memory Fill BF 2 14 2 4 4 BM Block Move BM 2 15 2 4 5 BR Breakpoint BR 2 16 2 4 6 BS Block Search BS 2 18 2 4 7 DATA Data Conversion DATA 2 20 2 4 8 DI Disassemble DI 2 21 2 24 94 DL Download Serial DL 2 22 2 4 10 DN Download Network DN 2 23 2 4 11 Go Execute GO 2 25 Sud Co NO BO N Po NW P2 Fo Po P2 PO CO CO C0 WwW WwW Ww Ww GT Execute Till a Temporary Breakpoint GT 2 26 ELP Help HE 2 27 RD Internal Registe
35. hold time for PC66 and PC100 memory 2nS Input hold time for MCF5307 Parameter B4 1 nS timing margin Thus this analysis indicates all timing has adequate margin even for PC66 memory as long as a zero delay clock driver is used Although this timing analysis example is for a PC66 memory there are no timing violations when using PC100 memory either 1 5 Timing Considerations for Older OH55J Mask The timing analysis reviewed in the previous section applies to the most recent MCF5307 mask the 00J20C For those using the 0H55J mask of the MCF5307 the output hold time parameter B11 and parameter B11a have different values from the 0H55J mask Specifically the output hold time for address data and normal bus control signals is 0 0 nS and for DRAM control lines such as RAS and CAS the hold time is 1 0 nS Thus for write cycles the subtracting a 1 5 nS PC66 input hold time from a 1 5 nS MCF5307 output hold time results in a 3 nS timing margin for SDRAM signals 2 5 nS for PC100 memory In other words there is insufficient hold time The proposed solution is to use a clock driver that can provide a 1 0 nS negative propagation delay This is actually possible with the zero delay buffers from Cypress The reference output can be loaded with a 20 pF capacitor yielding a positive setup time in advance of the clock output The following is the resultant analysis for all important times e MCFS307 to SDRAM setup time 2
36. level priorityairs The 11 11 0 port is configured for I O Sade The HIZ Signal The HIZ signalisactivelydriven by the LSI2032 U9 ThisSignalisavailable formonitor on connector and J5 Thissignalshould not be driven by the user The Clock Circuitry The M5307C3 uses a 45MHZ oscillator 022 to provide the clookCLKIN pin of the processor In addition to U22 there also exista 20MHz oscillator U6 which feeds into the Ethernet chigLhe bus clock out of the MCF5307 drivesa clock buffer 018 which is fed intoth dge select pin of the MCF5307 the ispLSI2032 for Ethernet timing 1 4 bus clock SRAM U19 and SDRAM 023 22002454 Watchdog Timer 49 duration of the Watchdog isselectedby 0 1 bitsin System Protection Register The dBUG initializetshis registerwith the value 00 which provides for 1024 system clock time out but dBUG does not enable it 3c 6 Interrupt Sources The ColdFire family of processors can receive interruptsfor seven levelsof interrupt priorities When the processor receives an intemwmimh has higher priority than the current interrugtk instatus register itwillperform an interruptacknowledge cycle at the end of the current instructioncycle This interruptacknowledge cycle indicatesto the source of the interruptthat the request is being acknowledged and the device should provide the proper vector number t
37. liablefor any incidentalor consequential damages During the warranty period Matrix Design will replace at no charge components that the product is returned properlypacked and shipped prepaid to Matrix Design at address below Dated proof of purchase such as a copy of the invoice must enclosed with the shipment We will return the shipment prepaid via UPS Thiswarranty does not apply if inthe opinion of Matrix Design the product has been damaged by accident misuse neglect misapplication or as a result of service or modification other than specified in the manual by others Please send the board and cables with a complete descriptionof the problem to Matrix Design amp Manufacturing Inc 2914 Montopolis Drive 290 Austin TX 78741 Phone 512 385 9210 Fax 512 385 9224 http www cadreiii com Motorola is a registered trademark of Motorola Inc i PC are registered trademark of Corp 2 C Bus is a proprietary Philips interface bus All other trademark names mentioned in this manual are the registered trade mark of respective owners ii TABLE OF CONTENTS CHAPTER 1 1 1 1 1 INTRODUCTION 1 1 qe 2 GENERAL HARDWARE DESCRIPTION 1 1 3 SYSTEM MEMORY 1 4 1 4 SERIAL COMMUNICATION CHANNELS 1 4 1 5 PARALLEL I O PORTS I 4 1 256 PROGRAMMABLE TIMER COUNTER 1 5 du ON BOARD ETHERNET 1 6 1 8
38. lt k k X k k k k k k k k k k k k k k k k k k k k k k k k k k X k k X W Test Vector Section kA CK C CK CC CK CC CK Se C se test vectors HIZ L Test Vector RSTIN L PORIN L BDM RST L CS3 L RST P 1 1 1 1 gt X C 1 1 1 1 gt X C 1 0 1 1 gt X Cel edy gt X Cea ega y gt X ipsus x 11 gt 1 1 gt ipsus X X X gt OO Oe 00180 GODS Y C c C APPENDIX C Schematics
39. necessary prior to downloading an entry point address is specifiedin the S record COFF or ELF file the program counter is set accordingly Examples To download an S record file with the name srec out the command is dn s srec out To download a COFF file with the name coff out the command is dn c coff out To download fileusing the default filetypewith the nam bench out the command is dn bench out To download a file using the default filename and filetype the command is dn This command requires proper Network address parameter setup Refer to Appendix A for this procedure 2 45 11 Usage Go Execute GO GO lt addr gt The GO command executes target code startingat address addr The value for addr may be an absolute address specified as a hexadecimal value osymbol name Ifno argument isprovided the GO command begins executing instructionsat the current program counter When the GO command is executed alluser defined breakpoints are inserted into the target code and the context is switched to the target program Control is onlyegained when the target code encounters a breakpoint illegal instruction or other exception which causes control to be handed back to Examples To execut To execut code at the current program counter the command is go To execut code at the C function main the co
40. or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Literature Distribution Centers USA EUROPE Motorola Literature Distribution Box 5405 Denver Colorado 80217 Tel 1 800 441 2447 or 1 303 675 2140 World Wide Web Address http Idc nmd com JAPAN Nippon Motorola Ltd SPD Strategic Planning Office 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan Tel 81 3 5487 8488 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po New Territories Hong Kong Mfax RMFAX0 email sps mot com TOUCHTONE 1 602 244 6609 US amp Canada ONLY 800 774 1848 World Wide Web Address http sps motorola com mfax I
41. products increase designers are discovering new techniques for lowering the price and complexity of their embedded board platforms By integrating inexpensive fast SDRAM devices on board designs many embedded board manufacturers are realizing lower board costs Due to their large volume This document contains information on a new product under development by Motorola Motorola reserves the right to change or discontinue this product without notice Motorola Inc 1999 All rights reserved 4 MOTOROLA use in standard PCs SDRAM devices are currently the least expensive memory available in addition to being one of the fastest memory types These devices normally come packaged in handy upgradable modules called DIMMs which contain several SDRAM components one or both sides of the memory card Using the SDRAM controller the MCF5307 can seamlessly interface to standard SDRAM components and DIMMs Although the number of row column and bank select lines can vary from module to module the multiplexing scheme in the MCF5307 is designed to support a large variety of SDRAM configurations To extend this MCF5307 feature further a PLD can be designed to interface to the MCF5307 SDRAM controller that allows the connection of a wide variety of SDRAM DIMMs having different row and column configurations Thus rather than hardwiring one specific SDRAM DIMM to a MCF5307 board design SDRAM DIMMs with varying row and column combinations
42. specification for the Intel PC100 can be found at http developer intel com design chipsets memory sdram htm 1 3 System Design Besides interfacing the helper MUX to the MCF5307 other board design requirements must be met to allow for the swapping of various DIMMs One consideration is the number of clock inputs Some 168 pin SDRAM DIMMs only require a single clock input on pin 42 Other DIMMs require two clocks on either pin 42 and CLK1 pin 125 or on CLKO pin 42 and CLK2 pin 79 Yet others require four clocks CLKO pin 42 CLK1 pin 125 CLK2 pin 79 and CLK3 pin 163 Thus a clock driver with at least four outputs is recommended in the board design to satisfy the requirements of a four clock input DIMM DIMMs have on board termination for unused clock inputs Use of zero delay PLL type clock driver such as the Cypress Semiconductor CY2305 CY2308 or CY2309 is highly recommended The next consideration is the connection to the DIMM chip select lines that control the module For single sided or double sided 168 pin DIMMs the MCF5307 RASO should be connected to CSO pin 30 of the module and RAST should be connected to CS2 pin 45 of the module The remaining module chip select lines CS1 pin 114 and pin 129 should be connected to the 3 3 volt DIMM power supply through pull up resistors This ensures that chips on the back side of double sided modules remain deselected i e inactive and preve
43. targeted to Lattice ispLSI 22LV10 PAL 11 logic with this PAL is com CS 4C86 WAKKKKKKKKKKKKKKKKKKKKKK KKK KKK KK KKK KKK KKK KK sk S S KU KK KM CC CK S S Su S CK CK CK S Su 3k CK S Sk S k KK KU KU KM lt Declaration Section KK KK Sk Sk Kk Ko Kk Kk Kk constants C P X A H L iC PapaoX2 4 1 05 5 W lt Xx lt CK x k CK CK k amp k lt k lt k lt k lt k lt k lt k k X k k k k k k k k k k k k k k k k k k k X k X W 0 3 Input 0 1 4 Mux Input 1 M2 PIN 5 Mux Input 2 M3 PIN 6 Mux Input 3 CA18 PIN 2 Input ColdFire driven address 18 CA19 PIN 7 Input ColdFire driven address 19 CA20 PIN 9 Input ColdFire driven address 20 CA21 PIN 10 Input ColdFire driven address 21 CA22 PIN 11 Input ColdFire driven address 22 CA23 PIN 12 Input ColdFire driven address 23 CA24 PIN 13 Input ColdFire driven address 24 CA25 PIN 16 Input ColdFire driven address 25 CA26 PIN 23 Input ColdFire driven address 26 CA27 PIN 21 Input ColdFire driven address 27 SA8 24 Output SDRAM input address
44. time 3 nS Output hold time for PC66 and PC100 memory 2 nS Input hold time for MCF5307 parameter B4 1 nS advance from clock 0 nS timing margin Taking into account the 1 nS clock advance with 2 nS required for the MCF5307 the 3 nS hold time of the SDRAM leaves 0 5 timing margin Hold times are probably less critical because trace impedances and capacitances on the board will tend to extend these hold times In conclusion using a zero delay buffer in the negative one nanosecond model works with PC100 memory assuming that the MCF5307 from the 0H55J mask set is used 1 6 ABEL Code The following is the ABEL code file for the helper MUX for interfacing between a MCF5307 and standard 168 pin unbuffered SDRAM module SDRAMmux title SDRAM Mux Controller for the MCF5307EVM 5307mux device ispLSI22LV10 KOK ke K This abel file contains the code to mux the address lines allowing the MCF5307 to support all 168 pin 1 Bank x 64 bit PC compliant DIMMS It was targeted to Lattice ispLSI 22LV10 PAL All logic with this PAL is com CS XXX K K KOK k K KOK KOK KOK K K KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK KOK ICR ICICI I ICRI IO ICR ICR ICI Declaration Section MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 11 A ORR K k K KOK KOK K K k K KOK KOK KOK KOK KOK KOK constants OPAD Os
45. when debugging dBUG recognizes thisand allows for repeated execution of these commands with minimal typing After a command isentered simply press RETURN or ENTER to invoke the command again The command is executed as if no command line parameters were provided An additional function called the TRAPhandler allows the user program to utilizevarious routines within dBUG The TRAP 15 handler isdiscussed at the end of this chapter The operationalmode of dBUG isdemonstrated inFigure 5 After the system initializatiorhe board waits for command line input from the user terminal When proper command isentered the operation continues in one of the two basic modes If the command causes execution of the user program the dBUG firmware may may not be ntered depending on the discretionof the user For the alternate case the command willbe executed under control of the dBUG firmware and after command completion the System returns to command entry mode During command execution additionaluser input may be required depending on the command function For commands that accept an optional lt width gt to modify the memory access size the valid values are B 8 bit byte access W 16 bit word access cL 32 bit long access When no lt width gt option is provided the default width is W 16 bit The core ColdFire regi
46. 0 324 A18 D7 sw E 17 D6 Sow QB12 16 05 Ts Dig 15 D4 BWE2 amp 580 QB10 68 01 14 0 SBC A13 D2 BWE1 SBB 12 01 BWE3 SBA aas Hx 11 Do QA7 85 B 10 Qas 28 9 QA5 D 8 RY SET 55 NC4 SE2 23 A6 NC3 2 2 SES QA2 gt A5 NC2 Pee M NC1 NC2 45 vect NC3 Nos V6C2 NC4 25 333 MA 0 19 gt A0 NC5 NC8 22 cee VDD1 24 GND2 VDD2 GND2 GND3 VDD3 i GNDt GND4 VDD4 R45 GND5 VDD5 19 GND6 VDD6 33 GND7 VDD7 GND8 VDD8 4 7K GND9 VDD9 AM29LV004T 100EC GND10 VDD10 GND11 VDD11 GND12 VDD12 MCM69F737TQ11 not populated at assembly 3 3 C77 C78 C58 C92 C93 O 1UF O 1UF O1UF itle 7 MCF5307 Evaluation Board Eze Document Number Rev B MCF5307 FLASH 3 0 late Thursday April 01 1999 Bheet MA 0 19 023 161 1 Ao 181 Dat Al 062 159 D29 A2 061 158 D28 SDRAM MUX A3 060 186 U24 M 059 155
47. 0020000 The new image is placed into Flash using the UPDBUG command The user is prompted for verification before performing the operation Use this command with extreme caution as any error can render dBUG and thus the board useless 244 21 UPUSER Update User Code In Flash UPUSER Usage UPUSER number of sectors The UPUSER command places user code and data into space allocatedfor the user inFlash There are sixsectors of 128K each availableas user space To place code and data in user Flash the image is downloaded to address 0x00020000 and the UPUSER command issued This command programs all six sectors of user Flash space l swxss thisspace startingat address OxFFE20000 To program lessthan six sectors supply the number of sectors you wish to program after the UPUSER command Examples To program all 6 sectors of user FLASH space the command is upuser Or upuser 6 To program only 128K of user FLASH space the command is upuser 1 VERSION Display dBUG Version VERSION Usage VERSION Ihe VERSION command display the version information for dBUC dBUG version number and build date are both given The version number isseparated by a decimal for example v1 1 The first number indicates theversion of the CPU specificcode and the second number indicates the version of the board specific code The version date isthe day and time at which the entire dBUG monitor was compiled and
48. 07 MCF5307 Pins SDRAM Pins A15 A0 A14 A1 A13 A2 A12 A3 A11 4 10 5 9 6 17 A7 A18 A8 A19 A9 A20 A10 A21 BAO A22 BA1 1 2 1 Helper MUX Design By organizing the 5307 SDRAM controller hardware connection information in Table 2 and Table 3 the configuration of the helper MUX inputs outputs and multiplex selects can be devised One possible pin configuration for interfacing to a standard 168 pin unbuffered SDRAM DIMM is shown in Figure 1 however this same concept can be carried over to other PLD and pin configurations This MUX configuration is implemented in a single PLD device that has a low cost and profile minimal propagation delay and matches the drive capability of the MCF5307 This example uses a 3 3 volt Lattice ispGAL22LV 10K which has almost identical output characteristics to the MCF5307 and only presents a 5 nS max propagation delay This PLD also is available in an SSOP package 6 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 28 M3 2 27 SDRAM A13 M2 3 26 SDRAM A12 M1 4 25 SDRAM BA1 M0 5 24 SDRAM A8 A26 6 23 SDRAM A11 A25 7 22 8 21 SDRAM A10 A24 9 20 SDRAM BAO A23 10 19 SDRAM AQ A22 11 18 spare A21 12 17 A19 A20 13 16 A18 14 15 Figure 1 Pin Configuration for ispGAL22LV10K Inter
49. 1 e 3 New NC1 CLK 0 2 62 bse BLOB CLK 0 1 lo 1 X 1022 PP1 50 500 10 4 PSTO TOUT 02 104 4 R_CAS2 DQM2 03 105 PST1 TINA 1074 10 5 RAS1 SO2 105 107 PST2 BWE1 10 6 108 R_CAS0 DQMO 07 109 PP6 BWE2 08 10 10 PP2 R_CAS1 DQM1 10 9 10711 PP5 BWES 1010 Io 12 R_CAS3 DQM3 10711 10 13 MTMODO BWEO 10 42 10 14 DDATA3 22 SRAS 10713 10 15 MTMOD1 14 SX 10 14 10 16 DDATA2 28 7 R DRAMW 1015 1017 RXD2 10 16 12 1016 IO 18 DDATA1 1017 L 8 10 17 10 19 RTS2 1018 lt lO 18 1020 DDATAO 1019 26 50 10719 10 21 RXD1 10720 f7 X 10 20 22 MTMOD3 IO 21 IO 21 lo 23 MTMOD2 10 22 TS gt lt 10722 10724 RTS1 10723 y Touro 1023 10 25 SCLK TRST 10 24 6 lO 24 10 26 CTS1 10225 22 lt 10 25 10 27 DSDI TDI 10 26 lO 26 39 1028 CTS2 10 27 22 XK EDGESEL 39 10727 40101 1029 10 28 18 X 39 20 10 28 41 92 10 30 DSDO TDO 20 G1 10 29 i 32101 41 62 G1 10 29 42 93 10 31 TMS 41 92 10 30 FS X 41 92 42 93 62 1030 42104 HIZ 42103 1031 55 SDA 42103 23104 1031 G5 23104 1032 43 54 G5 G4 10732 05 05 05 Mictor Connector 767054 1 Connector 767054 1 Mictor Connector 767054 1 Mictor Connector AMP 767054 1 Mictor Connector AMP 767054 1 3 3 3 3 4 1 3 C20 C21 C38 5 4 t 1 1 1 39 50 51 52 1800
50. 2 nS Bus Frequency 11 nS BCLKO to Valid Output time 2 nS PC100 Memory Setup time 1 nS Clock Driver Advance 8 nS timing margin 5 nS MUX PLD max propagation delay 3 nS worst case timing margin e MCF5307 to SDRAM hold time for writes 1 nS worst case Output hold time MCF5307 for SDRAM controls 1 5 advance from clock driver 1 nS 1 nS skew from termination resistors 1 nS input hold time for PC100 Memory 0 nS timing margin The OH55J mask set MCF5307 Errata published hold time from clock rising edge is 0 0 nS Parameter B11 for normal signals and 1 0 nS for SDRAM control signals Given the additional 1 nS advance on the clock with the loaded reference signal this leaves a 1 0 nS hold time for normal 10 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 10 signals and 0 0 nS for control signals However SDRAM control signals are routed through 22 Ohm series termination resistors before hitting their nominal 50 pF SDRAM input load This would skew these signals by at least 1 0 nS Because 1 0 nS is required for PC100 memory this leaves 0 0 nS timing margin an adequate outcome e SDRAM to MCF5307 setup time for reads 22 nS BCLKO period 7 nS Clock to valid data for PC100 memory This is 10 nS for PC66 memory 1 5 advance from clock driver 5 5 nS Valid input to BCLKO falling setup time parameter B1 10 5 nS timing margin For the SDRAM to MCF5307 hold
51. 3 d0 select the function asm trap 415 make the call 2 4 dendif 29 25 IN CHAR This function function code 0x0010 returns an input character from termina to the caller returned character is in D1 Assembly example move l 50010 d0 Select the function trap 15 Make the call the input character is in dl C example int board in char void asm 1 0 0010 40 select the function asm trap 15 make the call asm 1 41 00 put the character in 40 Zi edu CHAR PRESENT This function functi mde 0x0014 checks ifan input character ispresent to receive value of zero isreturned inDO when no character is present non zero value in DO means a character is present Assembly example move l 50014 d0 Select the function trap 15 Make the call 40 contains the response yes no C example int board char present void asm move l1 0 0014 40 select the function asm trap 15 make the call 2 044 EXIT TO dBUG This function function code 0x0000 transfers the control back to thebgBUG terminating the user code The register context are preserved Assembly example move l 50000 d0 Select the function trap 415 Make the call exit to dBUG C example void board exit to dbug void asm move l 0 0000 90 select the function asm trap 15
52. 33342 Sarig 32 Shas 2319 17 DURING ASSEMBLY PPl0 7 00 avi 18 555 2242 4y2 22 7 26 4Y3 23 4 4 4 4 R62 da i vol E 1 R63 R64 R65 R66 R67 R68 31 veg zoe 28 dn 270 270 270 270 270 270 270 32 o 24 z 28 GND Hg 545 5 5 45 8 5 9 E WB Motorola ColdFire 39 ND GND LIS v v 5 S 45 ann I x lt 44 zz x 2 A MCF53907 Evaluation Board MCTALCX1G244DT eee SEES 4 4 Eze Document Number MCF5307 BUFFERS Date Thursday Api ni 1999 FB D 16 31 gt MA 0 19 gt R54 SRAM 4 7K 019 Hx SAt QD34 58 SA2 9633 25 SA3 0032 24 GE HEABER E 483 33 433 33 514 9031 23 SAS QD30 55 Je SA6 9029 22 SA7 QD28 2 SAB 9027 18 OULD BE SA9 13 SA10 QC26 x Qoid SA11 aces 12 lt 4 7 47K 4 7K SA12 QC24 SA13 ces 8 SA14 Qc22 6 SA15 3 D 10 SA16 QC20 5 D25 RSTOY RESET nea ADSP ADV m AM29LV004T 100EC ADSC 5 5 vias LN 0816 e UND DEMNM BCLK SRAM gt K QB15 an 022 13 e 9814 74 D2
53. ATIC DISCHARGE CAN AND WILL DAMAGE THESE DEVICES Once you verifiedthat allthe items are present remove the board from its protective jacket Check theard for visibledamage Ensure that there are no broken damaged or missing parts If you have not received allthe items listed above othey are damaged please contact Cadre immediately in order to correct the problem 1 2 25 Preparing the Board for Use The board as shipped is ready to be connected to a terminal the power supply without any need for modification Howevefollow the steps below to insure proper operation from the firsttime you apply the power Figure 3 Jumper Table and Locations shows the placement of the jumpers and the connectors which you need torefer to inthe following sections The steps to be taken ar a Connecting the power supply b Connecting the terminal 2953 Providing Power to the Board The board acceptstwo means of power supply connections Connector P2 isa 2 1mm power jack and Pl lever actuated connector Thhboard accepts 6 5V to 9V DC regulated or unregulated at 1 5 Amp via either one of the connector Contact NO Voltage 1 6 5 9V 2 Ground 1 1 9 4 Selecting Terminal Baud Rate The serialchannel of MCF5307 which isused for serialcommunication has builtin timer used by the ROM MONITOR to generate the baud rate used to communicate with a termin
54. M5307C3 USER S MANUAL REVISION dao Matrix Design amp Manufacturing Inc 2914 Montopolis Drive 290 Austin TX 78741 Phone 512 385 9210 Fax 512 385 9224 http www cadreiii com COPYRIGHT Copyright 1999 by Motorola SPS All rights reservedNo part of thismanual and the dBUG software provided in Flash ROM s EPROM s may reproduced stored in a retrievalsystem or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise Use of the program or any part thereof for any purpose other than single end user by the purchaser is prohibited DISCLAIMER The informationinthismanual has been carefullyexamined and isbelievedto b ntirelyreliable However no responsibilityis assumed for inaccuracies Furthermore Motorola reserves the rightto make changes to any product s herein to improve reliabilityXunction or design The M5307C3 board is not intended for use in lifeand or property criticalapplications Here such applicationsare defined to be any situationin which any failure malfunction or unintended operation of the board could directly or indirectlyfhreaten life resultin personal injury or cause damage to property Although every effort has been made to make the suppliedoftware and itsdocumentation as accurate functional as possible Motorola Inc will not assume responsibilityfor any damages inc
55. MCF5307 EVS Debugger Vx x x 199 Enter help for help dBUG and waits for a command The user can call any of the commands supportelHy the firmware A standard input routine controls the system while the user types a line of input Command processing begins only afterthe linehas been entered and followed by a carriage return NOTES 1 Th user memory is located at addresses 00020000 SXXXXXXXX the maximum SDRAM address of the memory installedin the board When first learning the system the user should limit his her activities to thisfarea the memory map Address range 00000000 0001FFFF is used by dBUG 2 If a command causes the system to access an unused address no memory or peripheral devicee mapped at that address a bus trap ermoay occur Thisresultsinthe terminal printingout trap error message the contents of all thMCF5307 core registers Controlisreturned to the dBUG monitor 2 3 TERMINAL CONTROL CHARACTERS The command line editor remembers the last five commands in a history buffer which were issued They can be recalled then executed using control keys Several keys are used as a command lineeditand controlfunctions It isbest to be familiarwith these functions before exercising the system These functions include a RETURN carriage return willenter the command li
56. NTERNET http motorola com sps Technical Information Motorola Inc SPS Customer Support Center 1 800 521 6274 electronic mail address crc amp 9wmkmail sps mot com Document Comments FAX 512 895 2638 Attn RISC Applications Engineering World Wide Web Addresses http www motorola com PowerPC http www motorola com netcomm http www motorola com HPESD M MOTOROLA APPENDIX FEVALUATION BOARD BOM MCF5307EVM_BOM
57. O DLYDA CS3 L amp END16 amp ENDIT amp IOCS16L 6 RD 6 CLK8MHZ amp SBHE CS3 amp END8 amp ENDIT 5161 amp RD amp CLK8MHZ CS3 L amp END8 amp ENDIT amp SBHE amp RD 6 CLK8MHZ DLYDA clk XCLKO0 STARTISA CS3 L amp ENDIT STARTISA clk CLK8MHZ CBU43 BCLKO BCLK1 BCLK2 CLK8MHZ STARTISA STARTISA BALE STARTISA amp CLK8MHZ amp BCLK2 amp BCLK1 amp BCLKO amp IOR amp IOW STARTISA 6 BCLK2 5 BCLK1 amp BCLKO amp CLK8MHZ amp RD CS3 1 TOW STARTISA amp BCLK2 amp BCLK1 5 BCLKO 5 CLK8MHZ amp RD IOW amp STARTISA END16 BCLK2 6 BCLK1 6 BCLKO amp CLK8MHZ END16 amp STARTISA END8 BCLK2 6 6 BCLKO 6 CLK8MHZ END8 amp STARTISA ENDIT END16 amp TOCS16L 5 IOCHRDY amp DLYIOCHRDYO amp DLYIOCHRDY amp SBHE 6 STARTISA END8 amp IOCS16L 6 IOCHRDY amp DLYIOCHRDYO 6 DLYIOCHRDY amp STARTISA i END8 68 SBHE amp IOCHRDY amp DLYIOCHRDYO amp DLYIOCHRDY amp STARTISA DLYIOCHRDYO IOCHRDY DLYIOCHRDYO clk CLK8MHZ DLYIOCHRDY IOCHRDY amp CLK8MHZ f DLYIOCHRDY amp CLK8MHZ W i didi di x dii lt diri k lt k diri
58. PSTCLK 5 TA 7 C49 ces 10 UF TANT 0 1 UF 23 828 lt SRAM 0 y2 886 T BCLKOB BCLKO 61 H2 22 FPLA z R84 2 BCLK_SDRAMO 1 LONE VONT iis 7 S 983 EpGESEL 4 id UF TANT 10 UF TANT 7 14 R82 22 BCLK SDRAM P2 SDRAM O 3 3 11 R81 22 BCLK SDRAM2 1 5404 433 384 1 4 151602 R80 22 BCLK SDRAMS 2 X 22 cet voce 4 R79 22 1 pv BCLKOHEADER 3 200UF GND1 12 GND2 Yi0 2 X 172 C55 C56 cn 20 O1UF 24 Er All itle 6 t 4 4 4 MCFS307 Evaluation Board the 10uF which ad Eze Document Number Rev CDO351DW MCF5307 POWER 30 late Thursday April 01 1999 Bheet 8 8 n z 5 10 APPENDIX D SDRAM MUX PAL EQUATION module SDRAMmux t 16 99 First revision of the code based on Bill Benners application itle SDRAM Mux Controller for the MCF5307EVM 5307mux device ispLSI22LV10 ko C x C CK x lt x lt x lt x lt x lt lt k lt k lt k k k k k k k amp k CK k amp k k k k k k k k k k k k k k k X X W allowing the MCF5307 to support all 168 1Bank x 64 bit PC compliant D lt lt This abel file contains the code to mux the address lines IMMS It was
59. Pr 1900 ET 19002 1500 1500 1500 PF 1500 PF C67 C22 C40 C41 C69 C70 C88 C87 C84 ille 1500 1500 1500 1500 1500PF 1500 1500 1500 500 1500 MCFS307 Evaluation Board t x 2 Eze Documem Number Rev B MCF5307 CONNECTORS 30 ale Thursday April 01 1999 Bheet 2 of FB D 16 31 gt U25 Bi Buffers A 0 31 gt pig 2 iei yii Oni Butfers 19 1 2 1 2 5 183 ic i He e bee 186 1 6 A 41 MA 187 1 7 40 2 1 23 312 2 2 u D24 1 2 27243 282 2 2 36 2M MAS E As 9 35 MA9 2B5 2A5 at 33 D29 20 286 A11 32 MA11 030 221
60. This is not to be confused with the SDRAM row address lines called SRAS signals Note that in this application note all DIMMs mentioned in the design will be single sided since single sided DIMMs contain two CS lines in other words two MCF5307 banks that the MCF5307 can support Double sided DIMMs generally have four CS lines two on one side of the memory card and two on the other Because double sided modules present greater load to the address and data lines of a processor use of single sided modules are preferred Table 1 shows a fairly complete list of the extensive DIMM configurations along with their associated parameters Note that modules can have the same capacity but have different number of bank select lines row and column address lines depending on their organization 2 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA Table 1 Example SDRAM DIMMs Capacity of Chips Chip Organization Chip Density DEL 8 MBytes 4 1 Mbits X 16 16 Mbits 11 rows 8 columns 1 bank select 16 MBytes 8 2 Mbits X 8 16 Mbits 11 rows 9 columns 1 bank select 32 MBytes 16 4 Mbits X 4 16 Mbits 11 rows 10 columns 1 bank select 16 MBytes 2 2 Mbits X 32 64 Mbits 11 rows 8 columns 2 bank select 32 MBytes 4 4 Mbits X 16 64 Mbits 12 rows 8 columns 2 bank select 64 MBytes 8 8 Mbits X 8 64 Mbits 12 rows 9 columns 2 bank select 128 MBytes 16 16 Mbits X 4 64 Mbits 12 row
61. To take ovem exception vector the user places the address of the exception handler in the appropriate vector in the vector table located at 0x00000000 and then points the VBR to 0x00000000 The Software Watchdog Timer is disabled Bus Monitor enabled and internal timers are placed ia stop condition Interrupt controllerregistersinitialized with unique interrupt level priority pairs After initialization the terminal will display Hard Reset DRAM Size 8M 2000 0x300 Copyright 1997 1998 Motorola Inc All Rights Reserved ColdFire MCF5307 EVS Debugger Vx x x 199 Enter help for help dBUG If you did not get this response check the setup RefSectaon1 10 SYSTEM POWER UP AND INITIALOPERATION Note the date 199x may vary in different revisions Other means be used to re initializ amp he M5307C3 Computer Board firmware These means are discussed in the following paragraphs 2 2 2 1 Hard RESET Button Hard RESET is the red button located in the lower right side of the board Depressing thisbutton causes allprocesses to terminate resets the MCF5307 processor and board logicand restartsthe dBUG firmware Pressing the RESET button would be the appropriate action if all else fails Zt 2 2 2 2 ABORT Button ABORT is the blachutton located next to RESET button on the rightside o
62. Usage BC first second length The BC command compares two contiguous blocks of memory the first block starting at address first the second block starting at address second b of length length If the blocks are not identical then the addresses of the first mismatch are displayed The value for addresses first and second may be an absolute address specified as a hexadecimal value or a symbol name The value for length may be a symbol name or a number converted according to the user defined radix normally hexadecimal Examples To verify that the code in the first block of user FLASH space 128K is ident to the code in user SDRAM space the command is bc 20000 FFE20000 20000 2 4 3 BF Block of Memory Fill BF Usage BF width begin end data The BF command fills contiguous block of memory startingat address begin stopping at address end with the value data Width modifies the size of the data that is written The value for addresses begin and end may be an absolute addrespecifiedas hexadecimal value or a symbol name value for data may a symbol name or a number converted according to the user defined radix normally hexadecimal This command firstalignsthe startingaddress for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory ac
63. al It can be programmed to a number of baud rates After the power up or a manual RESET the ROM Monitor firmware configures the channel for 19200 baud After the ROM Monitor isrunning you may issue the SET command to choose any baud rate supported by the ROM Monitor Refer to Chapter 2 for the discussion of this command J 95 The Terminal Character Format The character format of the communication channel is fixed at the power up or RESET The charact prmat 158 bitsper character no parity and one stop bit You need to insure that your terminal or PC is set to this format 15 90 56 Connecting the Terminal The board isnow ready to be connected to a terminal Use the RS 232 serial cable to connect the PC to the M5307C3 The cable has a 9 pin female D sub connector at one end and a 9 male D sub connector at the other end Connect the 9 pin male connector to P4 connector on M5307C3 Connect tBe pin female connector to one of the availableserialcommunication channels normally referred to as COMI COM2 etc on the IBM PC s or compatible Depending on the kind of serialconnector on the back of your PC the connector on your PC may be a male 25 pin or 9 pin You may need obtain 9 pin to 25 pin adapter to make the connection If you need to build an adapter refer to Figure 2 which shows the pin assignment for the 9 pin connector on the board Tog Using a Personal Co
64. built Examples To display the version of the dBUG monitor the command is version 2 5 TRAP 15 Functions An additional utility within the dBUG firmware is a function called the TRAP handler This function can be called by the user program to utilize various routines within the dBUG to perform a special task and to return control to the dBUG This section describes the TRAP 15 handler and how it is used There are four TRAP 415 functions These are OUT CHAR IN CHAR CHAR PRESENT and EXIT TO dBUG 0 This function function code 0x0013 sends a character which is in lower 8 bits of D1 to terminal Assembly example assume dl contains the character move l 50013 d0 Selects the function TRAP 15 The character in dl is sent to terminal C example void board out char int ch Tf your C compiler produces a LINK UNLK pair for this routine then use the following code which takes this into account fif 1 LINK a6 40 produced by C compiler asm 1 8 6 4217 put ch into dl asm 1 0x0013 d0 select the function asm trap T1543 make the call UNLK produced by C compiler else If C compiler does not produce a LINK UNLK pair the use the following code af asm move l 4 5 41 put ch into dl asm 1 0x001
65. cesses Examples To fild memory block startingat 0x00010000 and ending at 0x00040000 with the value 0x1234 the command is bf 10000 40000 1234 To fill a block of memory starting at 0x00010000 and ending at 0 0004086 a byte value of OxAB the command is bf b 10000 40000 AB To zero out the BSS section of the target code defined by the symbols bss start and bss end the command is bf bss start bss end 0 Ped A BM Block Move BM Usage BM begin end dest The BM command moves a contiguous block of memory startingat address begin stopping at address end to the new address dest The BM command copies memory as a series of bytes and does not alter the original block The value for addresses begin end and dest may be an absolute address specifiedas a hexadecimal value or a symbol name If the destination address overlaps the block defined by begin and end an error message is produced and the command exits Examples copy a block of memory startingat 0 00040000 and ending at 0x00080000 to the location 0x00200000 the command is bm 40000 80000 200000 To copy the target code data section definedby the symbols data start and data end to 0x00200000 the command is bm data start data end 200000 Z 40 2 5 BR Breakpoint BR Usage BR addr r c count lt t trigger The BR command insertsor removes breakpoints at address addr The value for addr may be an absolute add
66. ddress is unique for the board Check for proper insertion or connection of the network cable IS statustLE indicating that network traffic is present Check for proper configurationand operation of the TFTP server Most Unix workstations can execute a command named tftp which be used to connect to the TFTP server as well Is the default TFTP root directorypresent and readable f DESTINATION UNREACHABLE or similarICMP message appears then a serious error has occurredReset the board and wait one minute for the TFTP server to time out and terminate any open connections Verify that the IP addresses for the server and gateway are correct APPENDIX BE ColdFire to ISA IRQ7 and Reset Logic Abel code module isa2 title isa Oct 12 98 controller version v3 of the 5307 isa2 device ispLSI W X x x lt x lt x lt x lt x lt x k x k lt k lt k lt k k k C CK k k k k k k k CK k k k k k k k k X X W This abel file contains the code for a NE2000 compatible ethernet for the 5307 ColdFire processor as well as reset and IRQ7 abort It was targeted to Lattice ispLSI LV 2032 PLD CS B25D W X CK C lt x lt x lt lt lt lt lt x k lt k lt k lt k lt k lt k k k k amp k amp k amp k k k Ck k k k k k k k k kX X lt W W X x lt x lt x lt x
67. ed logic for the helper MUX Using Lattice Semiconductor s freeware package ispEXPERT M System Starter Kit the ispGAL was programmed in ABEL HDL For more information on obtaining the starter kit please refer to http www lattice com ftp ispstarter html Both the ABEL HDL and PLD equation files for the helper MUX pictured in Figure 1 can be found at the end of this application note in section 1 6 on page 11 and section 1 7 on page 16 1 2 3 Helper MUX Initialization Once implemented in a system the helper MUX in Figure 1 can be used to interface to various 168 pin SDRAM DIMMs by initializing the MUX select pins M 3 0 to the proper SDRAM configuration SDRAM configuration information can be read at boot time through a serial presence detect SPD EEPROM on the SDRAM DIMM This EEPROM contains data about the number of rows columns banks access times etc of the DIMM The SPD portion of this module is accessed on pins 82 and 83 of a 168 pin DIMM and can be connected to the SDA and SCL pins of the MCF5307 respectively Information can be read from the SPD by using these PC pins on the MCF5307 to determine the configuration of the memory This information should be read at boot time and it should be used to initialize the M 3 0 lines on the helper PLD as well as the internal MCF5307 SDRAM configuration registers Information on the MCF5307 SDRAM Controller initialization sequence can be found in the Motorola application note AN1766 D The
68. ed as even addresses butincreased by 0x8000 bas ino of chip to 0x40000300 D accesses even address is 0x300 and uses ur system as mentioned earlieris0x40000000 though th addressed as they are IRQ3 the Ethernet Which brings Note that all registers should be bytes Note that no change the read However registersar ta in the lower byte of the word Note Stil that the read byte will be in the lower byte of the read word Below isan example copy of this document http www Motorola com ColdFire typedef struc t NATURAL16 CR union str uct Even registers NATURAL16 1 E NATURAL16 TSR NATURAL16 FIFO NATURAL16 CRDAO DE NATURAL16 RBCRO a NATURAL16 RSR a NATURAL16 1 ES NATURAL16 DATAPORT 2d of the data structure used to define th the description of the registers refer to the registers For Data SheetDavficom DM9008 a in on ColdFire Website CLDA1 rd PSTOP wr TSR rd TPSR wr FIFO rd TBCR1 wr CRDAO rd RSARO wr Remote Byte Count 0 wr RSR rd RCR wr CNTR1 rd DCR wr NATURAL16 reserved 0x10000 0x0012 2 Odd registers NATURAL16 CLDAO
69. el 3 priority and autovector The Timers are at Level 5 with Timer 1 with priority3 and Timer 2 with priority2 and both for autovector NOTE No interrupt sources should have the same level and priori as another 50 M5307C3 uses IRQ7 to support the ABORT function the ABORT switch 51 black switch This switsmsed to force a non maskable interrupt level 7 priority 3 if the user s program execution shou hHobeed without issuing a RESET referto Chapter 2 for more information on ABORT Since the ABORT switch is not capable of generating a vector in response to level seven interrupt acknowledge from the processor the debugger programs this request for autovector mode The IRQ1 line of the MCF5307 is not used on However the is programmed for Level 1 with priority dnd autovector The user may use this linefor external interruptrequest Refer to MCF5307 User sManual for more information about the interrupt controller Sud V Internal SRAM The MCF5307 has 4K of internal memory This memory is mapped to 0x20000000 and isnot used by the dBUG It isavailableto the user The memory is relocatable to 32K byte boundary 3 128 MCF5307 Registers Memory memory I O resources of the M5307C3 divided into three groups MCF5307 Internal External resources and the ethernet controller Allthe I O regist
70. ers are memory mapped The MCF5307 has builtin logicand up to eight chip selectpins 50 to 57 which are used to enabl xternal memory I O devices In additionthere are two RAS lines for DRAM s There are registers to specify the address range type of access and the method of TA generation for each chip select and RAS pins These registersare programmed by dBUG to map the external memory and I O devices The M5307C3 uses chip selectzero 50 to enable the Flash ROM s referto Section 3 3 The M5307C3 uses RAS1 RAS2 50 CES1482 and CAS3 to enable the SDRAM DIMM module referto Section 3 2 CS2 for SRAM not populated and CS3 for Ethernet Bus I O space The chip selectmechanism of the MCF5307 allows the memory mapping to be defined based on the memory space desired User Supervisor Program Data Spaces Allthe MCF5307 internalregisters configuration registers parallell O port registers DUART registersand system controlregistersare mapped MBAR registerat any 1K byte boundary Itismapped to 0x10000000 by dBUG For complete map of these registers refer to the MCF5307 User s Manual The M5307C3 board can have up to 16M bytes of SDRAM installed The first 16M bytes are reserved for this memory Refer to Section 3 2 for a discussion of RAM The dBUG is programmed in two 29LV004B Flash ROM s which only occupies bytes of the add
71. eserves the registersby storinga copy of the registerset ina buffer The RM command updates the copy of the registerin the buffer The actual value will not be written to the register until target code is executed Examples To change register DO to contain the value 0x1234 the command is rm DO 1234 ZU uu RESET Reset the board and dBUG RESET Usage RESET The RESET command attempts to reset the board and dBUG to their initial power on states The RESET command executes the same sequence of code that occurs on Thiscode attempts to initializehe devices the board and dBUG data structures If the RESET command fails to r ddetboard to your satisfaction Cycle power or press the reset button Examples To reset the board and clear the dBUG data structures the command is reset 244 23 SET Set Configuration SET Usage SET option value SET The SET command allows the settingof user configurableoptions within dBUG The options are listedbelow Ifthe SET command isissued without option it will show the available options and values The board needs a RESET after this command inorder forthe new option s to take effect baud This is the baud rate for the first 1 on the board All communications between dBUG and the user occur using either 9600 or 19200 bps eight data bits no parity and one stop bit 8N1 Do not choose 38400 baud
72. et filename The DN command downloads code from the network The DN command handle fileswhich ar ither S record COFF or ELF formats The DN command uses Trivial File Transfer Protocol TFTP to transfer files from a network host In general the type of file to be downloadad the name of the filemust be Specified to the DN command The c option indicatesa COFF download the e option indicatesan ELF download I option indicatesan image download and the s indicates an 5 download The o option works only in conjunction with the s option to indicateand optional offset for S record download The filename ispassed directlyto the TFTP server and therefore must be a valid filename on the server If neither of thec e i s or filename options are specified then a default filename and file type will be usegefaultfilename and filetype parameters are manipulated using the set and show commands The DN command checks the destination address for validity If the destination is an address below the defined user spatben an error message is displayed and downloading aborted For ELF and COFF fileswhich contain symbolic debug information the symbol tables are extracted from the fileduring download and used by dBUG Only global symbols kept in dBUGThe dBUG symbol table isnot cleared priorto downloading so itisthe user s responsibilityo clear the symbol table as
73. ets the default SDRAM access provided to 4 2 2 2 burst The ROM monitor also uses 54 the Serial Presence DetectSPD functionalitywf the SDRAM to determine what SDRAM is populated in the evaluation board and configures the system appropriately Please refer to the SDRAM Application Note in Appendix E for address muxing 3 3 FLASH ROM There aretwo 512Kbyte Flash ROM on the M5307C3 020 high even byte U21 low odd byte The board is shipped with two 29LV004 512K byte FLASH ROM for a totalMf bytes The first128K of the Flash contains ROM Monitor firmware The last 896K is available to the user The chip select signal generat MGF5307 CS0 enables both chips The MCF5307 chip select logic can be programmed to generate theTA for 50 signal after a certain number of wait states dBUG programs this parameter to three wait states 3 3 1JP1 Jumper and User s Program This jumper allows users to test code from the boot without having to overwrite the ROM Monitor When the jumper isset between pins 1 and 2 the behavior is normal When the jumper isset between pins 2 and 3 the board boots from the second half of Flash 0x80000 Procedure 1 Compile and linkas though the code was to be place at the base of the flash but setup so that itwilldownload to the SDRAM startingat address 0x80000 The user shoul to refer to the compiler for this since it will depend upon the compiler used u
74. f addressing and 32 linesof data The processor has eight 32 bit data registers eight 32 bit address registers a 32 bit program counter and a 16 bit status register The MCF5307 has System module incorporates many include programmable purpose and Interruptont Integration Module referred to as the SIM The of the functions needed for system design These chip select logic System the use of slower memory Protection logic General referto MCF5307 User detailed information about thSIM selects toaccess the Flash 5 board may be added by th D is used to control one The M5307C3 CS0 SRAM e user and the Ethernet IMM module trollerlogic The chip selectlogiccan select up to eight memory banks and peripheralsin addition to two banks of DRAM s The chip select logic also allows programmable number of wait statesatdow sManual by Motorola for only uses three of the chip CS2 which isnot populated on CS3 The DRAM controller up 2 of SI DRAM both RAS linesand all four CAS lines are used otAerkt functions of the SIM are availableto the user A block diagram of the board is shown in Figure 1 RAS gt AMAA m Tm 5232 5307 lt XCENERS FlasilM bit 020021 LO PORTS ADDR BUS CONTROL BUS DATA BUS
75. f the board The abort function causes an interruptof the present processing a 1 7 interrupton MCF5307 and gives controlto the dBUG firmware This action differs from RESET in that no processor regicteemory contents are changed the processor and peripherals are not reset and dBUG 15 not restarted Also in response to depressing the ABORT button the contents of the MCF5307 core internal registers are displayed The abort functionsmost appropriate when software isbeing debugged The user can interruptthe processor without destroying the present state of the System This is accomplished by forcing a non maskable interrupt whatcall a ROM monitor routine to preserve the current state of the registers to shadow registerin the monitor for display to the user user willbe returned to the ROM monitor prompt after exception handling 2 2 2 3 Software Reset Command dBUG does have a command that causes the dBUG to restartas ifa hardware reset was invoked The command is RESET 2 2 2 4 USER Program The user can return control of the system to the firmware by recalling his her program Instructionscan be inserted into the user program to call dBUG via the TRAP 15 handler Zia System Operation After system initialization the terminal will display Hard Reset DRAM Size 8M NE2000 300 Copyright 1997 1998 Motorola Inc All Rights Reserved ColdFire amp
76. face to Standard 168 pin SDRAM DIMM The M 3 0 lines represent the MUX select configuration mapped from Table2 and Table3 A recommended encoding of M 3 0 is shown in Table 5 These signals can be driven by spare parallel port lines on the MCF5307 Table 5 MUX Select M 3 0 Encoding M 3 0 MUX Inputs Corresponding Configuration 0000 8 columns 11 rows 8 MBytes 16 Mbit or 16 MBytes 64 Mbits 0001 9 columns 11 rows 16 MBytes 16 Mbits or 64 Mbits 0010 10 columns 11 rows 32 MBytes 16 Mbits or 64 Mbits 0011 8 columns 12 rows 16 MBytes 64 Mbits or 32 MBytes 64 Mbits or 128 Mbits 0100 9 columns 12 rows 64 MBytes 64 Mbits or 128 Mbits 0101 10 columns 12 rows 128 MBytes 64 Mbits or 128 Mbits 0110 11 columns 12 rows 256 MBytes 128 Mbits double sided 0111 8 columns 13 rows 32 MBytes 64 Mbits or 64 MBytes 256 Mbits 1000 9 columns 13 rows 64 MBytes 64 Mbits or 128 MBytes 256 Mbits 1001 10 columns 13 rows 128 MBytes 64 Mbits or 256 MBytes 256 Mbits 1010 11 columns 13 rows 512 MBytes 256 Mbits double sided 1011 1111 Reserved MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 7 1 2 2 Helper MUX Implementation An in system programmable device was chosen for the helper MUX implementation because it can easily be reconfigured while on the board The ispGAL22v10 has a 500 gate density which easily fits the requir
77. gher address lines do not connect to column address lines This is illustrated in Table 1 where the 8 MByte module has 8 column address lines but 11 row address lines The MCF5307 SDRAM controller was designed to interface to these asymmetrical SDRAMs seamlessly Standard SDRAM component can be directly connected to the 5307 by following the easy connection chart found in the Asynchronous Synchronous Operation Section of the MCF5307 User s Manual Because the MCF5307 SDRAM controller can be continually re programmed to support various SDRAM configurations this advantage can be leveraged to create a helper MUX that can support swapping of these various SDRAMs in hardware MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 3 Because different density SDRAM devices have different asymmetries a single direct connection scheme is not possible An easy connection scheme for each specific module type can be derived by referring to Table 1 and the MCF5307 address multiplexing scheme in the asynchronous operation section of the 5307 User s Manual Since there is some commonality with respect to the connection scheme of each module type an in between helper MUX can be conceived that interfaces between the MCF5307 and SDRAM DIMM Table 2 and Table 3 depict the MCF5307 SDRAM controller to SDRAM connections necessary for different SDRAMs Table 2 lists the address line connections for various SDRAMs while Table 3 lists the requi
78. gicanalyzer UARTO channel isthe TERMINAL channel used by the debugger for communication with external terminal PCThe TERMINAL baud rate is set at 19200 1 5 PARALLEL PORTS MCF5307 offersone 16 bit general purpose parallell O port Each be individuallyprogrammed as input or output The parallelport bits PP 7 0 is multiplexed with TT 1 0 TM 2 0 DREQ 1 0 and XTIP The second set of parallelport bitsPP 15 8 ismultiplexed with address bus bitsA 31 24 Both bytes of the parallelport are controlledby the PinAssignment Register PAR 1 4 pins are programmable pinbasis settingof the multiplex pins are determined by the configurationbyte during reset After reset all pins are configures general purpose 11 11 0 These pins are connected to 23 LA2 1 6 PROGRAMMABLE TIMER COUNTER The MCF5307 has two builtin general purpose timer counters These timers are available to the user sigfliatthe timer are availableon the LA4 to be viewed by a logic analyzer These pins are connected to J3 as well 1 7 BOARD ETHERNET The M5307C3 has an board Ethernet 2000 compatible operating at 10M bits sec The on board ROM MONITOR is programmed to allow a user to download filesfrom a network to memory indifferentformats The current formats supported are S Record COFF ELF or I
79. hen AS defaults to the beginning address of user space for the target board If no instruction is passed to the AS command then AS prompts with the address where opcode will be written and continues to assemble instructions until the user terminates the AS command by inputting a period The inline assembler permits the use of case sensitive symbols defined by equate statements and labels which are stored in the symbol table The syntax for defining symbols and labels is as follows Symbol equ value Symbol equ value Symbol equ value Symbol equ value Label instruction Label Constants and operands may be input in several different bases Ox followed by hexadecimal constant 5 followed by hexadecimal constant 4 followed by octal constant followed by binary constant digit decimal constant The assembler also supports the different syntax for the indexed displacement and immediate addressing modes 12 or 12 An 4 PC Xn or 4 PC Xn 0x1234 Lor Examples To assemble one command is move To assemble multiple then 0 0001 0x0001 0x0001 0x0001 0x0001 2000 2002 2004 2006 2008 0x1234 L instructions at the next assemble address 1 0x25 d0 lines at 0x12000 the command is 12000 start nop nop lsr 1 1 d0 cmp 4 90 beq start the 2 4 2 BC Compare Blocks of Memory BC
80. ile Programmer load file mux tt3 P22V10C dev SDRAM Mux Controller for P22V10C Programmed Logic 16 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 16 MOTOROLA 5 8 18 amp MO amp 6 MO amp M1 0 amp 1 amp M2 ae SA9 amp M1 0 amp MO amp M1 amp 1 db o MO amp M1 SA10 MO amp M1 amp MO amp M MO amp M MO amp M amp M amp dB o dB amp M SA11 MO amp 1 amp MO amp M1 MO amp M1 0 amp 1 0 6 Ml MOTOROLA amp amp amp amp amp amp amp amp CA18 amp MO amp 1 amp amp 1 amp M2 amp M2 amp M3 M3 M3 M2 amp M3 M1 amp amp amp amp amp M2 amp CA19 CA19 CA19 CA19 amp M3 amp CA19 M3 amp CA19 M2 amp M3 amp CA20 1 amp M2 M2 M2 M2 M3 M2 amp amp amp amp amp amp M3 amp CA20 M3 amp CA20 CA21 M3 amp CA21 CA21 M3 amp CA20 amp Ml amp amp 1 amp amp amp M2 amp M2 amp amp M1 amp M2 amp M3 amp CA21 M3 amp CA21 M3 amp CA21 M2 amp M3 amp CA21
81. ileto download intothe directoryused by the TFTP server A default filename for network downloads ismaintained dBUG change the default filename use the command set filename filename When using the Ethernet network for download ither S record COFF ELF or Image filesmay be downloaded A default filetypefor network downloads is maintained by dBUG as well To change the default filetype use the command set filetype lt srecord coff lelf image gt Continuing with the aboveexample the compiler produces executable COFF file a out Thisfileiscopied to the tftp boot directoryon the server with the command rcp a out santafe i tftp boot a out Change the default filename and filetype with the commands set filename a out set filetype coff Finallyperform the network download with the dn command Ihe network download process uses the configured IP addresses and the default filename and filetype for initiating a TFTP download from the TFTP server A 3 Troubleshooting Network Problems Most problems relatedto network downloads are a direct resultof improper configuration Verifythat allIP addresses configured into dBUG are correct This is accomplished via the show command Using an IP address already assigned to another machine willcause dBUG network download to fail and probably other severe networmkroblems Make certain the client IP a
82. in 11 Input global clock IOWL pin 15 Input write signal from ethernet RD pin 16 INPUT R W from the ColdFire CLK8MHZ pin 17 ISTYPE reg d buffer BALE pin 18 Output address latch enable AO pin 19 OUTPUT AO sent to the ethernet PORIN L pin 26 Input Suppy Voltage Supervisor 253 3 22 Input From ColdFire RSTIN L pin 27 Input Hard Reset switch ETHER IRQ pin 28 Input Ethernet IRQ 3 29 Output IRQ 3 into the ColdFire RST H pin 30 Output to the Ethernet ABORTIL pin 31 INPUT abort signal received from the Abor swith HIZ L pin 32 Output to ColdFire HIZ IORL pin 37 Input read signal from ethernet A16 pin 39 TAL pin 40 Input Output Transfer acknowledge SBHEL pin 41 Output sent to the ethernet 5140 43 BDM RST L pin 44 Input BDM reset input W lt x CK CK amp k amp k amp k lt k k k lt k k k k k k k k k k k k k X X W Lattice attributes CC S pLSI property CLK XCLKO CLKO pLSI property CLK CLK8MHZ SLOWCLK pLSI property ISP ON pLSI property PULLUP ON pLSI property 1 AS RESET OFF Output inverter macro OB21 MACRO 00 0 2 00 0 Tristate Output inverter macro OT21 MACRO 00 0 OE 2 00 OE
83. ire family single board computers firmware stored in two 512 8 FlastOM devices provides a self containedprogramming operating environment dBUG interacts with the user through pre defined commands that are entered via the terminal The user interfaceto dBUG isthe command line A number of features have been implemented to achieve an easy and intuitive command line interfac dBUG assumes that an 80x24 character dumb terminal isutilizecto connect to the debugger For serialcommunications dBUG requires eight data bits no parity one stop bit 8 1 The baud rate is 1920 changed after the power up Ihe command lineprompt is dBUG Any dBUG command may entered from this prompt dBUG does not allow command lines to exceed 80 characters Wherever possible dBUG displays data in 80 columna ess dBUG echoes each character as it typed eliminatingthe need localecho on the terminal side In general dBUG isnot case sensitive Commands may b ntered either in upper or lower case depending upon the user s equipment preference Only symbol names require that the exact case be used Most commands can be recognized by using an abbreviated name For instance entering h is the same as entering helus itisnot necessary to type th ntire command name The commands DI GO MD STEP TRACE are usenepeatedly
84. iscussed in Chapter 3 However brief discussion of the jumper settings is as follows Id Del Jumper 1 Flash Upper Half Lower Half Boot This jumper allows the MCF5307 to boot from the lower or upper half of the flash The default is the lower half Table 1 JP1 Upper Lower Half Lower default 1 11 2 Jumper JP2 This jumper selects between 50 to Flash or a header Table 2 CSO select Flash default 1 12 USING THE BDM The MCF5307 has a built in debug mechanism referred to M5307C3 has the necessary connector J1 to facilitate this connection In order to use the BDM simply connect the 26 pin IDC header at the end of the BDM wiggler cable provided Motorola from P amp E Microcomputer Systems to the 21 connector specialsettingisneeded Refer to the ColdFire User s Manual BDM Section for additional instructions 2 USING THE MONITOR DEBUG FIRMWARE The M5307C3 singleboard computer has a resident firmware package that provides a self contained programming and operating environment The firmware named dBUG provides the user with monitor debug disassembly program download and I O control functions This Chapter is a how to use descriptionof the dBUG package includingthe user interfaceand command structure 2 1 WHAT IS dBUG dBUG isa resident firmware package for the ColdF
85. it value OxABCD the memory block starting at 0x00040000 and ending at 0x00080000 the command is 5 1 40000 80000 ABCD This reads the 32 bit wordocated at 0x00040000 and compares itagainst the 32 bit value Ox0000ABCD If no match 15 found then the address is incremented to 0x00040004 and the next 32 bit value is read and compared To search the BSS section definedby the symbols bss start and bss end for the byte value OxAA the command is bs b bss start bss end AA VET T DATA Data Conversion DATA Usage DATA data The DATA command displays data in both decimal and hexadecimal notation Ihe value for data may be a symbol nameor an absolute value Ifan absolute value passed into the DATA command is prefixed by Ox then data is interpreted as a hexadecimal value Otherwise data is interpreted as a decimal value All values are treated as 32 bit quantities Examples To display the decimal equivalent of 0x1234 the command is data 0x1234 To display the hexadecimal equivalent of 1234 the command is data 1234 28 DI Disassemble DI Usage DI addr The DI command disassembles target code pointed to by addr The value for addr may be an absolute address specified as a hexadecimal value osymbol name Wherever possible the disassembler willuse information from the symbol tableto produce a more meaningful disassembly Thisi
86. l microprocessor based controllerina variety of applications With the addition of a terminal it serves as a complete microcomputer for development evaluation trainingnd educational use The user must only connect an RS 232 compatibterminal ora personal computer with terminal emulation software and a power supply to have fully functional system Provisionshave been made to connect thisboard to additionaluser supplied boards via the Microprocessor Expansion Bus connectors to expand memory I O capabilities Additionalboards may require bus buffers to minimize additional bus loading Furthermore provisions have been made in the PC board to permit configurationof the board ina way which best suits an application Options availableare up to 512M SDRAM 512K SRAM Timer I O Ethernet and 1M of Flash In addition allof the signals are easily accessible to any logical analyzer with mictor probes to assistin debugging Most of the processor s signalsare also availablevia berg connectors J3 J4 and J5 for expansion purposes 1 2 GENERAL HARDWARE DESCRIPTION The M5307C3 board provides the RAM Flash ROM on board NE2000 compatible Ethernet interface 10M bit sec RS232 and allthe built inlI O functions of the MCF5307 for learningand evaluating the attributesof the MCF5307 The MCF5307 isa member of the ColdFire family of processors It isa 32 bit processor with 32 bitso
87. lt x lt x lt x lt x k lt k lt k k k lt k k k k X amp k k k k k k C k k k k k k k k k X X W Declaration Section W X CK C lt x lt x lt x lt x lt x lt k k lt k lt k k k lt k k k k k k k amp k amp k k k k k k k k k k k X X W constants Cig Ps pe Xa poh oy LO ko C x lt x lt X lt k lt x lt k lt x lt X k k KK k k k KK k k k k k k amp k amp k k k k k KK k k k k k k k k X X W DLYIOCHRDYO node ISTYPE reg d buffer DLYIOCHRDY ENDIT END16 END8 node STARTISA node ISTYPE reg d buffer SBHE IOR IOW ISAOE node DA DLYDA node ISTYPE reg d buffer ABORTML DAOE CLK16MHZ node ISTYPE reg d buffer CLK4MHZ node ISTYPE reg d buffer RSTMH node BCLKO node BCLK1 node BCLK2 node ISTYPE reg d buffer ISTYPE reg d buffer ISTYPE reg d buffer ABORTOL prn TSTYPE reg d buffer RST L pin 4 Output to ColdFire reset DB CS L pin 5 Output Data buffer enable for ethernet AOIN pin 6 INPUT 0 received from CF through buffers IOCHRDY pin 7s Input asserted by ethernet 5161 9 Input asserted by ethernet SIZ1 pin 10 XCLKO p
88. mage 1 8 SYSTEM CONFIGURATION The M5307C3 board requires only the following items for minimum system configuration Figure 3 1 The M5307C3 board provided 2 Power supply 6 5V to 9V with minimum of 1 5 Amp 3 RS 232C compatible terminal or a PC with terminal emulation software 4 Communication cable provided Refer to next sections for initial setup pedo NSTALLATION AND SETUP The following sections describe allthe steps needed to prepare the board for operation Please read the following sections carefully before 51 0 When you are preparing the board for the firsttime be sure to check that all jumpers are in the default locations The standard configuration does not require any modifications After the board is functional in its standard configuration you may use the Ethernet by followitkhe instructionsprovided in Appendix A Unpacking Unpack the computer board from itsshippingbox Save the box for storingor reshipping Refer to the following listand verify that allthe items are present You should have received 1 M5307C3 Single Board Computer 1 M5307C3 User s Manual this documentation One RS 232 communication cable Debug wiggler cable Programmers Reference Manual OF C A selection of Third Party Developer Tools and Literature WARNING AVOID TOUCHING THE MOS DEVICES ST
89. mmand is go main code at the address 0x00040000 the command is go 40000 2 4 2 GT Execute Till a Temporary Breakpoint GT Usage GT lt addr gt The GT command executes the target code startingat address inPC whatever the has untila temporary breakpoint as given in the command line is reached Example execute code at the current program counter and stop at breakpoint address 0 10000 the command is GT 10000 2 4 13 HELP Help HE Usage HELP command The HELP command displaysa brief syntax of the commands availablewithin dBUG addition the address of where user code may start is given If command is provided then a brief listingof the syntax of the specified command is displayed Examples To obtain a listing of all the commands available within dBUG the command is help The help listislonger than one page The help command displaysone screen full and ask for an input to display the rest of the list To obtain help on the breakpoint command the command is help br 2 05 34 Usage IRD Internal Registers Display IRD lt module register gt This commands displays the internal registers of different modules inside the MCF5307 In the command line the module refers to the module name wher the register is located and the register refers to the specific register need The registers are organized according to the module to
90. mputer as a Terminal You may use your personal computer a terminal provided you also have a terminal emulation software such as PROCOMM KERMIT OMODEM Windows 95 Hyper Terminal or similar packages Then connect as described in 1 9 6 Connecting the Terminal Once the connection to the PC ismade you are ready to power up the PC and run the terminal emulation software When you are inthe terminal mode you need to selectthe terminal emulation so press the p key whil character format baud rate and the character format for the channel Most ftware packages provide a command known Alt p le pressing the Alt key to choose the baud rate and Make sure you select 8 bits no parity one stop bit see section The Terminal Character Format Then select the baud rate as 19200 Now you are ready to apply power to the board Figure 2 Pin Receive WN 7 Request to Send 8 Clear to send 9 Not connected Data Carrier Transmit Data Signal Ground Data Set Ready input output ec doe de xe qo Data Output Input Data Terminal Ready 8 E assignment for P4 Terminal connector Detect Output shorted to pins 4 and 6 from board receive refers to terminal side to board transmit refers to terminal side input shorted to pin 1 and 6 Output shorted to pins 1 and 4
91. neand causes processing to begin b Delete Backspace ke or CTRL H will delete the last character entered on the terminal c CTRL D Go down in the command history bufferyou may modify then press enter key CTRL U Go up inthe command historybuffer you may modify then press enter key e CTRL F Recalland execute the last command entered does not need the enter key to be pressed For characters requiring the control key CTRL should be pushed and held down and then the other key H should be pressed 2 4 dBUG COMMAND SET Table 3 liststhe dBUG commands Each of the individualcommands is described in the following pages Table 3 dBUG Commands ASSEMBLE AS addr inst tion 25 11 BLOCK COMPARE IRST SECOND ENGTH 25 14 BLOCK FI BF WIDTH BEGI DATA BLOCK MOVE BM BEG DEST BLOCK SEARCH BS WIDTH BEGI BREAKPOI BR ADDR R C COUNT T IGGER DATA CONVERT DATA VALUE W o EN DOWNLOAD SERI DL OFFSET DOWNLOAD DN C E S O OFFSET 2 NETWORK ENAME Go TI GT AD HELP HELP COM INTERNAL STER INTERNAL I T DATA gt ISTER MEMORY NIN NO FN N N IIS NIN NYFF Jr Fo fo FY o Oo N Fo fa Jo Jo o a
92. nt at the C function benchnd set itstriggervalue to 3 the command is br bench t 3 When the target code isexecuted the processor must attempt to execute th function bench a third time before returning control back to dBUG To remove all breakpoints the command is br gt 2 0264 BS Block Search BS Usage BS width begin end data The BS command searches a contiguous block of memory startingat address begin stopping at address end forthe value data Width modifies the size of the data that is compared during the search The value for addresses begin and end may be an absolute addrespecifiedas hexadecimal value or a symbol name value for data may a symbol name or a number converted according to the user defined radix normally hexadecimal This command firstalignsthe startingaddress for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To search for the 16 bit value 0x1234 the memory block starting at 0x00040000 and ending at 0x00080000 the command is bs 40000 80000 1234 This reads the 16 bit wordocated at 0x00040000 and compares itagainst the 16 bit value 0x1234 If no matabs found then the address isincremented to 0x00040002 and the next 16 bit value is read and compared To search for the 32 b
93. nts any possible contention on the data bus Because the back side of the DIMM is not being used in this design its clock select line should also be disabled A 168 pin DIMM has two clock enable lines for each side of the DIMM CKEO pin 128 and pin 63 which activate a low power self refresh mode of an SDRAM It is recommended that the control line be left floating while the CKEO pin is connected to the SCKE pin of the MCF5307 The line controls the clock select line on the back side of DIMMs and has a 10 K Ohm pull up resistor on the module itself 8 Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA 1 4 Timing Analysis To ensure the helper MUX did not interfere with the timing requirements of a standard SDRAM a timing analysis was done based on the following design assumptions BCLKO frequency 45 MHz 22 nS period BCLKO 90 MHz core clock Clock Driver Delay 0 nS EDGESEL Connection Tied high through a pull up Data Bus Connection Connected directly to the SDRAM DIMM with no buffer in between Address Bus Connection Connected directly through the MUX to the SDRAM DIMM with no buffer in between e SDRAM Control Signal Connections Connected to SDRAM DIMM through a 22 Q resistor BCLKO Rising to Valid Output The MCF5307 output signals are guaranteed to be valid a maximum of 11 nS after BCLKO is clocked high parameter 105 e SDRAM Input Setup Time 3 nS f
94. o 168 Pin Unbuffered SDRAM DIMMs 12 MOTOROLA pLSI property 1 AS RESET OFF equations COMBINATORIAL Logic Only TERR RAE EHH RARE EHH RARE EHH E AE AE AE AE EHR HEAR EE EO when select 0 then 5 8 18 SA9 CA19 SA10 CA20 BA0 CA21 BA1 CA22 when select 1 then SA8 CA19 5 9 20 5 10 21 0 22 1 23 when select 2 then SA8 CA19 5 9 21 5 10 22 0 23 1 24 when select 3 then 5 8 18 SA9 CA19 SA10 CA20 SA11 CA21 0 22 1 23 MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 13 when select 4 then SA8 CA19 SA9 CA20 SA10 CA21 SA11 CA22 BA0 CA23 BA1 CA24 when select 5 then SA8 CA19 SA9 CA21 SA10 CA22 SA11 CA23 0 24 1 25 when select 6 then SA8 CA19 SA9 CA21 5 10 23 SA11 CA24 0 25 1 26 when select 7 then 5 8 18 SA9 CA19 SA10 CA20 SA11 CA21 SA12 CA22 0 23 1 24 14 Connecting the MCF5307 to 168 Unbuffered SDRAM DIMMs MOTOROLA 14 when select 8 then 5 8 19 5 9 20 SA10 CA21 SA11 CA22 SA12 CA23 0 24 1 25 when select 9 then 5 8 19 5 9 21 SA10 CA22 SA11 CA23 SA12 CA24 0
95. o Send _______ Usea 5 Sa Logical Analyzer connectors LAi 5 and Processor Expansion Bus 23 4 245 Allthe processors signalsare availableon 5 mictor connectors LA1 5 User may refer to the data sheets for the major parts schematic at the end of this manual to obtain an accurate loading capability mfbshe signals are availableon J8 and J9 for easier access Tables 7 14 show the pin assignment for J3 04 25 LA2 LA4 and LA5 respectively SIGNAL Tabl 7 Ih J3 Connector pin assignment NO NAME NO NAME tino 6 _ 2 Toro sch 10 2 5 6 61 PP7 17 CSO ER A27 A28 A29 A30 A31 21 22 26_ 1 NN 30 62 Tabl 8 Th J4 Connector pin assignment N F gt gt gt gt sN D O1 a o o c D F gt olo o wv o 1 Jo s j e o o fas fas fw co o m s ple 5
96. o indicatewhere the service routine for thisinterruptlevelis located If the source of interruptisnot capable of providing a vector its interrupt should be set ugs autovector interruptwhich directsthe processor to a predefined entry into the exception table referto the MCF5307 User s Manual The processor goes to a exception routine via the exception taBhestableis in the Flash andhe VBR points to it However a copy of thistableismade the RAM starting at 500000000 set an exception vector the user pt ees address of theexception handler inthe appropriate vector inthe vector table located at 00000000 and then points the VBR to 00000000 The MCF5307 has four external interruptrequest lines You can program the external interruptrequest pinsto levell 3 5 and 7 or levels2 4 6 and 7 The M5307C3 configures these linesas levell 3 5 7 There are also six internalinterrupt requests from Timerl Timer2 Software watchdog timer UART1 UART2 and MBUS Each interruptsource external and internal can be programmed forany prioritylevel In case of similarprioritylevel a second relative priority between 0 to 3 will be assigned However the software watchdog is programmed for Level 7 priority2 and uninitializewector The UART1 is programmed for Level 3 priority2 and autovector The UART2 isprogrammed for Level 3 priorityl and autovector The M Bus isat Lev
97. oads The dBUG module has the abilityto perform downloads over an Ethernet network using the TrivialFileTransfer Protocol TFTP Prior to using this feature several parameters are required for network downloads to occufhe information that isrequired and the steps for configuring dBUG are described below 1 Required Network Parameters For performing network downloads dBUG needs 6 parameters 4 are network related and 2 are download related parameters are listedbelow with the dBUG designation following in parenthesis All computers connected to an Ethernet network running the IP protocol n ed network specific parameters These parameters are ternet Protocol IP address for the computer client IP address of the Gateway for non local traffic gateway IP and Network netmask for flagging traffic as local or non local netmask In addition the dBUG network download command requiresthe followingthree parameters IP address of the TFTP server server IP e Name of the file to download filename Type of the file to download filetype of S record COFF ELF or Image Your localsystem administrator can assign a unique IP address for the board and also provide you the IP addresses of the gateway netmask and TFTP server Fill out the lines below with this information Client IP IP address
98. of the board Server IP 5 P a IP address of the TFTP server Gateway IP address of the gateway Netmask Network netmask A 2 Configuring dBUG Network Parameters Once the network parameters have been obtained the Rom Monitor must configured following commands are used to configure the network parameters set client client IP set server server IP set gateway gateway IP set netmask lt netmask gt set Macaddr lt macaddr gt For example the TFTP server is named santafe and has address 123 45 67 1 The board is assigned the IP address of 123 45 68 15 The gateway IP address is123 45 68 250 and the netmask 255 255 255 0 The commands to dBUG are set client 123 45 68 15 set server 123 45 67 1 set gateway 123 45 68 250 set netmask 255 255 255 0 set Macaddr 00 00 00 00 00 00 The laststep isto inform dBUG of the name and type of the fileto download Prior to giving the name of the file keep in mind the following Most if not all TFTP servers willonly permit access to filesstartingat a particular sub directory security feature which prevents reading of arbitraryfilesby unknown persons For example SunOS uses the directory tftp boot as the default TFTP directory When specifyinga filename to SunOS server allfilenames are relativeto tftp boot As a result you normally willbe required to copy the f
99. or PC66 memory and 2 nS for PC100 memory per Intel PC SDRAM specification e SDRAM Input Hold Time 1 5 nS for PC66 memory 1 0 nS for PC100 memory per Intel PC SDRAM specification Thus the MCF5307 to SDRAM Setup Time can be found by the calculation below 22nS Bus Frequency 11nS BCLKO to Valid Output time 3nS PCDRAM setup time 8nS timing margin 5nS MUX PLD max propagation delay 3nS worst case timing margin This indicates that even at the worst case there is enough margin for the MCF5307 signals to reach a PC66 SDRAM while using the helper MUX 1 4 1 Write Bus Cycle A write bus cycle was also evaluated as valid since the published hold time to BCLKO for the MCF5307 is 2 0 nS Parameter B11 and the input hold time for a PC66 memory is 1 5 nS leaving 0 5 nS as timing margin 1 4 2 Read Bus Cycle Read cycles also meet timing margins for setup and hold times to the MCF5307 For SDRAM to MCF5307 setup time the following calculation was used 22 nS BCLKO period 10 nS Clock to valid data for PC66 memory This is 7 nS for PC100 memory 5 5 nS Valid input to BCLKO falling setup time parameter 1 6 5nS timing margin This corresponds to the parameter value found in the Electrical Specification Section of the MCF5307 User s Manual MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs 9 For SDRAM to 5307 hold time the following calculation was used 3 nS Output
100. ord coff image and elf autoboot Thisoption allows for the automatic downloading and execution of a filefrom the network This option can be used to automatically boot an Operating system from the network Validvalues are on and off This option is not implemented on the current of dBUG nicbase this is base address network interface Thiscommand isused to informthe dBUG of the address of the network interface The default value shows 0 0000 However this parameter is hard coded to 0x300 DO NOT CHANGE THIS OPTION macaddr This is the ethernet MAC address of the board For network communications the MAC address isrequired to be set to a unique value Any address that is not already in use is suitable Examples To see all the available options and supported choices the command is set To set the baud rate of the board to be 19200 the command is set baud 19200 Now press the RESET button RED or RESET command forthe new baud to take effect This baud will be programmed Hrash ROM and willbe used during the power up 2 4 22 SHOW Show Configuration SHOW Usage SHOW option SHOW The SHOW command displays the settings of the user configurable options within dBUG Mostoptions configurablevia the SET command be displayed with the SHOW command Ifthe SHOW command isissued without any option it will show all options Examples To display all the cu
101. ormation for the symbol table Symbol names contained inthe symbol table are truncated to 31 characters Any symbol table lookups either by the SYMBOL command or by the disassembler willonly use the first31 characters Symbol names case sensitive Examples To define the symbol main to have the value 0x00040000 the command is symbol a main 40000 To remove the symbol junk from the table the command is symbol r junk To see how full the symbol table is the command is symbol display the symbol table the command is symbol 1 Z0 2425 TRACE Trace Into TR Usage TRACE The TRACE command allows singleinstructionexecution If num is provided then num instructions ar xecuted before control is handed back to dBUGe value for num is a decimal number The TRACE command sets bits in the processors supervisuwsgistersto achieve single instruction execution target code executed Control returns to dBUG after a single instruction execution of the target code Examples To trace one instruction at the program counter the command is EE To trace 20 instructions from the program counter the command is iE 20 2 4 26 UPDBUG Update the dBUG Image UPDBUG Usage UPDBUG The UPDBUG command is used for updating the dBUG image in Flash When updates to the MCF5307 EVS dBUG are available the updated image is downloaded to address 0x0
102. r of I O devices Itiscompatible with industry standard I C Bus The M5307C3 uses thisto access the SDRAM eeprom parameters two M Bus signalsare SDA SCL which are availableat LA4 connector These signalsare open collectorsignals However they have pull up resistorson the M5307C3 These signalsare connected to the SDRAM DIMM module interfacebut not used by the debugger The interruptcontrolregisterfor M Bus is set for Level 3 priority 0 and autovector 3 5 THE PARALLEL I O Port The MCF5307 has one 16 bit parallelport Allthe pins have dual functions They can be configured as I O or their alternate function via the Pin Assignment register Allparallelport pins are configured as I O pins by the ROM Monitor 56 0 7 4 connec 1538 CS CS are general p to LEDs 3 6 ON BOAR The M5307C3 Ethernet chip to allow 10M bit transfer rate aretavork D ETHERNET LOGI C to the SDRAM mux control and LEDs urpose parallel port inputs includesthe necessary logic drivers and the NE2000 compatible The Ethernet spac addresses are located starting at 0x40000000 Th base address the address addressed as interfac the even address registersar word will have the byte of the da For odd addressed bytes the address ismapped to 0x400083xx 1 odd bytes are address
103. red bank select interface Table 2 SDRAM Address Line Connections CF Address Condition SDRAM Address Column Address Row Address A15 Always AO A2 A15 14 Always A1 A3 A14 A13 Always A2 A4 A13 A12 Always A3 A5 A12 A11 Always A4 A6 A11 A10 Always A5 A7 A10 A9 Always A6 A8 A9 A17 Always AT A16 A17 A18 8 columns A8 N A A18 A19 9 10 or 11 columns A18 A19 A19 8 columns A9 N A A19 A20 9 columns N A A20 A21 10 or 11 columns A20 A21 A20 8 columns A10 N A A20 A21 9 columns N A A21 A22 10 columns N A A22 A23 11 columns A22 A23 A21 8 columns A11 N A A21 A22 9 columns N A A22 A23 10 columns N A A23 A24 11 columns N A A24 Note that although the data bus and other control connections to SDRAM are not necessary to these discussions or detailed in these tables information on these hardware hookups can be found in the LAB5307 or SBC5307 schematics and the MCF5307 User s Manual at http www mot com ColdFire Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs MOTOROLA Table 2 SDRAM Address Line Connections Continued CF Address Condition SDRAM Address Column Address Row Address A22 8 columns A12 N A A22 A23 9 columns N A A23 A24 10 columns N A A24 A25 11 columns N A A25 A23 8 columns A13 N A A23 A24 9 columns N A A24 A25 10 columns N A A25 A26 11 column
104. ress space first 1 are used by ROM Monitor and the remainder is left for user use Refer to section 3 3 The Ethernet Bus interfacemaps allthe I O space of the Ethernet bus to the MCF5307 memory at address FE600000 Refer to section 3 6 52 Tabl 4 Th M5307C3 memory map DRESS RANGE SIGNAL and DEVICE ADI 00000000 DRAM space for dBUG ROM Monitor OO0FFFFFF 0000000 1 000 3 5 5 5 5 2 000 Internal SRAM 4K bytes 2 OFFF 5 00 System Integration Module SIM registers 0 0 External SRAM 512K bytes unpopulated SFEA7FFFFl 1M bytes of Flash ROM 1 Not installed Level 2 cache footprint accepts Motorola s MCM69F737TC chip and any other SRAM with the same electrical specifications and package All the unused area of the memory map is available to the user Jue 210 Reset Vector Mapping After reset the processor attempts to get the initias tack pointer and initial program counter values from locations 000000 000007 the firsteight bytes of memory space This requires the board to have a nonvolatilememory device inthisrange with proper information However insome systems itis preferred to have RAM startingat address 500000000 MCF5307 the CSO responds to any accesses after reset untilthe CSMRO iswritten Since CS0 the global chip select isconnected to Flash ROM s the
105. ress specifiedas a hexadecimal value a symbol name Count and trigger armumbers converted according to the user defined radix normally hexadecimal If no argument is provided to the BR command a listingof all defined breakpoints is displayed The option to the BR command removes a breakpoint defined at address addr If address is specifiedin conjunction with the r option then all breakpoints are removed Each time a breakpoint iencountered during the execution of target code its count value isincremented by one By default the initiatount value fora breakpoint is zero but the c option allows settingthe initiatount for the breakpoint Each time a breakpoint is encountered during the executiontefget code the count value is comparedagainst the triggervalue Ifthe count value isequal to or greater than the triggervalue a breakpoint 1 encountered and control returned to dBUG By default the initiatriggervalue for a breakpoint isone but the t option allows setting the initial trigger for the breakpoint address is specifiedin conjunction with the c or t options then all breakpoints are initialized to the values specified by the c or t option Examples To set a breakpoint at the C function main the command is br _main When the target code isexecuted and the processor reaches main control will be returned to dBUG set a breakpoi
106. rrent options the command is show To display the current baud rate of the board the command is show baud To display the TFTP server IP address the command is show server 2 4 23 STEP Step Over ST Usage STEP The ST command can be used to step over a subroutine call rather than tracing every instruction in the subroutifid e ST command sets breakpoint one instructionbeyond the current program counter and then executes th target code The ST command can be used for BSR and JSR instruction amp he ST command will work for other instructionsas well but note that ifthe ST command is used with an instruction that will not return i e BRA then the temporary breakpoint may never be encountered and thus dBUG may not regain control Examples To pass over a subroutine call the command is step 2 4 24 SYMBOL Symbol Name Management SYMBOL Usage SYMBOL lt symb gt a symb value r symb lt 1 5 gt The SYMBOL command adds or removes symbol names from the symbol table a symbol name isprovided to the SYMBOL command then the symbol table is searched for a match on the symbol name and its information displayed The a option adds a symbol name itsvalue intothe symbol table The r option removes a symbol name from the table The c option clears the entisymbol table the loption lists amp he contents of the symbol table and the s option displaysusage inf
107. rs Display IRD 2 28 RM Internal Registers MODIFY IRM 2 29 D Memory Display MD 2 30 M Memory Modify MM 2 31 D Register Display RD 2 32 1 M Register Modify RM 2 33 20 RESET Reset the board and dBUG RESET 2 34 eat SET Set Configuration SET 2 35 222 SHOW Show Configuration SHOW 2 37 i234 STEP Step Over ST 2 38 24 SYMBOL Symbol Name Management SYMBOL 2 39 TRACE Trace Into TR 2 40 26 UPDBUG Update the dBUG Image UPDBUG 2 41 UPUSER Update User Code In Flash UPUSER 2 42 4 WN m HPP PP BP HP PS PB gt SP SP a TRAP 15 Functions 2 44 OUT CHAR 2 44 IN CHAR 2 45 CHAR PRESENT 2 45 EXIT TO dBUG 2 46 aon R 348 THE PROCESSOR AND SUPPORT LOGIC 48 The Processor 48 The Reset Logic 49 The HIZ Signal 49 The Clock Circuitry 49 Watchdog Timer 49 Interrupt Sources 50 Internal SRAM 51 MCF5307 Registers and Memory 51 Reset Vector Mapping 53 0 TA Generation 53 1 Wait State Generator 54 DONA C0 PN THE SDRAM DIMM 54 FLASH 55 3 1 Jumper and User s Program 55 THE SERIAL COMMUNICATION CHANNELS 56 3 45 1 The MCF5307 2 UARTs 56 Soup Des Motorola Bus M Bus Module 56 7 Vd uz The Auxiliary Serial Communication Connector P3 60 THE PARALLEL I O Port 56 ON BOARD ETHERNET LOGIC 57
108. s 10 columns 2 bank select 32 MBytes 2 4 Mbits X 32 128 Mbits 12 rows 8 columns 2 bank select 64 MBytes 4 8 Mbits X 16 128 Mbits 12 rows 9 columns 2 bank select 128 MBytes 8 16 Mbits X 8 128 Mbits 12 rows 10 columns 2 bank select 256 MBytes 16 32 Mbits X 4 128 Mbits 12 rows 11 columns 2 bank select 64 MBytes 2 8 Mbits X 32 256 Mbits 13 rows 8 columns 2 bank select 128 MBytes 4 16 Mbits X 16 256 Mbits 13 rows 9 columns 2 bank select 256 MBytes 8 32 Mbits X 8 256 Mbits 13 rows 10 columns 2 bank select 512 MBytes 16 64 Mbits X 4 256 Mbits 13 rows 11 columns 2 bank select One bank select line selects between two banks within the SDRAM component Denotes a double sided module The memory from only one side can be used due to the SDRAM controller only supporting two CS signals Two bank select lines select between four banks within the SDRAM component 1 2 Hardware Configuration Unlike ADRAM memory SDRAM does not use a symmetrical multiplexed addressing scheme one in which each address line on the DRAM device connects to two internal address lines a row and column address ADRAM memories interfacing to the MCF5307 can use a simple wiring scheme in which a single wire is added each time an ADRAM address bus grows by one bit corresponding to one row address and one column address With SDRAM however the lower 8 or 9 or 10 or 11 address lines typically do connect internally to both row and column address lines but hi
109. s N A A26 1 Note N A indicates that although a ColdFire address will be multiplexed during the column phase this does not matter because the number of column lines on the device is satisfied by lower address lines For example if an 8 column SDRAM is used the 8 column lines are satisfied by ColdFire address lines 9 15 and A17 See the table above Table 3 SDRAM Bank Select Line Connections CF Address Condition SDRAM Bank Select A21 8 columns 11 rows 19 address lines BAO A22 9 columns 11 rows 20 address lines 8 columns 12 rows A23 10 columns 11 rows 9 columns 12 rows 21 address lines 8 columns 13 rows A24 10 columns 12 rows 22 address lines 9 columns 13 rows A25 11 columns 12 rows 23 address lines 10 columns 13 rows A26 11 columns 13 rows 24 address lines A22 8 columns 11 rows 19 address lines BA1 A23 9 columns 11 rows 20 address lines 8 columns 12 rows A24 10 columns 11 rows 9 columns 12 rows 21 address lines 8 columns 13 rows A25 10 columns 12 rows 22 address lines 9 columns 13 rows A26 11 columns 12 rows 23 address lines 10 columns 13 rows A27 11 columns 13 rows 24 address lines MOTOROLA Connecting the MCF5307 to 168 Pin Unbuffered SDRAM DIMMs example of a 2 Mbit x 32 bit x 4 bank 8 MByte SDRAM using Table 2 and Table 3 is shown in Table 4 Table 4 2 Mbit x 32 bit x 4 bank SDRAM Connection to MCF53
110. sespeciallyuseful for branch target addresses and subroutine calls Ihe DI command attempts to track the address of the last disassembled Ifno address isprovided to the DI command then the DI command uses the address of the last opcode that was disassembled Examples To disassemble code that starts at 0x00040000 the command is di 40000 To disassemble code of the C function main the command is di _main 2 59 DL Download Serial DL Usage DL lt offset gt DL command performs S record download of data obtained from the serialport The value for offset 15 converted according to the user defined radix normally hexadecimal If offset is provided then the destination address of each S regaddusted by offset The DL command checks the destinationaddress for validityIfthe destination is an address below the defined user space 0x00000000 0x00020000 then an error message is displayed and downloading aborted If the S record file contains the entry point address th amp e nrogram counter is set to reflect this address Examples To download an S record file through the serial port the command is dl To download S record file through the serial port and adjust the destination address by 0x40 the command is dl 0x40 27405330 DN Download Network DN Usage DN lt gt e 4 1 s 4 0 offs
111. singDiab Data a LOAD command in the linker file is used 2 Set up the jumper for Normal operation pinl connected to pin 2 3 Download to SDRAM Ifusing serialor ethernet start ROM Monitor first If using BDM viawiggler download first then start ROM Monitor by pointing PC to Oxffe00400 and run 4 In ROM Monitor run upuser command 55 5 Move jumper to 3 3V and reset pin 2 connected to 3 User code should be running 3 4 THE SERIAL COMMUNICATION CHANNELS The M5307C3 offers a number of serial communications They are discussed i this section 3 4 1 MCF5307 2 UARTs The MCF5307 has two builtinUART each with itsown software programmable baud rate generators one channel isthe ROM Monitor to Terminal output and the other isavailableto the user The ROM Monitor however programs the interrupt level for UART1 to Level 3 priority2 and autovector mode of operation The interruptlevelfor UART2 to Level 3 priorityl and autovector mode of operation The signals of thesbannels are availableon port and LA3 The signalsof UART1 and UART2 are also passed through the RS 232 driver receiverand are availableon DB 9 connectors J4 and J7 Refer to the MCF5307 User s Manual for programming and the register map 254 2 Motorola Bus M Bus Module The MCF5307 has a builtinM Bus module which allows interchipbus interface fora numbe
112. ster set is maintained by dBUG These are listed belo A0 A7 0 7 SR All control registers on ColdFire are not readable by the supervisor programming model and thus not accessiblevia dBUG User code may change these registers but caution must be exercised as changes may render dBUG useless reference to SP actually refers to A7 2 2 OPERATIONAL PROCEDURE System power up and initiabperation are described in detailin Chapter 1 This information is repeated here for convenience and to prevent possible damage Le ud System Power up a Be sure the power supply is connected properly prior to power up b Make sure the terminal is connected to TERMINAL P4 connector c Turn power on to the board INITIALIZE COMMAND LINE INPUT FROM TERMINAL EXEGUTE COMMAND FUNGTION DOES COMMAND LINE CAUSE USER PROGRAM EXECUTION v JUMP USER PROGRAM AND BEGIN EXECUTION Figure 5 Flow Diagram of dBUG Operational Mode Zo 22x System Initialization The act of powering up the board willinitializehe system The processor is reset and dBUG is invoked dBUG performs the following configurationsof internalresources during the initializationThe instructioncache is invalidatedand disabled The Vector Base Register VBR points to the Flash However a copy o xdc ption table is made at address 00000000 in SDRAM
113. tor buffer witho pull upresistor a pull upresistorisincludedon the board All the TA s from the expansion boasdmld be connected to this line Su duds Wait State Generator The Flash ROM and SDRAM DIMM the board may require som adjustments on the cycle time of the processor to make them compatible with processor Speed To extend the CPU bus cycles for the slower devices the chip select logic of the MCF5307 can be programmed to generate TA after given number of wait states Refer to Sections 3 2 and 3 3 for information about the wait state requirements of SDRAM and Flash ROM respectively 3 2 THE SDRAM DIMM The M5307C3 one 168 pin DIMM socket 023 SDRAM DIMM This socket supports SDRAM DIMM s of 1M x 4 x 16 Bits SDRAM x 2 special configurationis needed The DIMM speed should be a minimum of 70ns The SDRAM Access timing is 2 4 21 1tor tiw tu Pus bus end fespectrulby These timings determine how long the data idelayed after the CAS signal or the read command is asserted during a SDRAM access Thi rresponds to the tgp Specificationsin most SDRAM other timings that correspond to the SDRAM are the active command to precharge command Li precharge command to active command t p last data input to precharge command and lastdata out to early precharge t4 The ROM monitor s
114. urred or generated this product Motorola does not assume any liabilitarisingout of the applicationor use of any product or circuitdescribed herein neither does it convey any license under its patent rights if any or the rights of others WARNING THIS BOARD GENERATES USES AND CAN RADIATE RADIO FREQUENCY ENERGY AND IF NOT INSTALLED PROPERLY MAY CAUSE NTERFERENCE IO RADIO COMMUNICATIONS AS TEMPORARILY PERMITTED BY REGULATION TE HAS NOT BEEN TESTED FOR COMPLIANCE WITH THE LIMITS FOR CLASS A COMPUTING DEVICES PURSUANT TO SUBPART J OF PART 15 OF FCC RULES WHICH ARE DESIGNED PROVIDE REASONABLE PROTECTION AGAINST SUCH NTERFERENCE OPERATION OF THIS PRODUCT A RESIDENTIAL AREA IS LIKELY TO CAUSE NTERFERENCE N WHICH CASE THE USER AT HIS HER OWN EXPENSE WILL BE REQUIRED TO CORRECT THE NTERFERENCE LIMITED WARRANTY Matrix Design warrants this product against defects in material and workmanship for a period of sixty 60 days from the originaldate of purchase This warranty extends to the originalcustomer only and is in lieu of all other warrants including implied warranties of merchantability and fitness Inno event willthe sellerbe
115. which they belong The available Example ird modules on the MCF5307 are SIM UART1 UART2 TIMER M Bus DRAMC and Chip Select Refer to MCF5307 User s Manual sim sypcr display the SYPCR register in the SIM module 2 4 15 IRM Internal Registers MODIFY IRM Usage IRM module register data This commands modifies the contents of the internal registers of different modules inside the MCF5307 In the command line the module refers to the module name where the register is located register refers to the specific register needed and data is the new value to be written into that register The registers are organized according to the module to which they belong The available modules on the MCF5307 are SIM UART1 UART2 TIMER M Bus DRAMC Chip Select Refer to MCF5307 User s Manual Example irm timer tmrl1 0021 write 0021 into TMR1 register in the TIMER module 2 4 16 MD Memory Display Usage MD width begin end The MD command displaysa contiguous block of memory startingat address begin and stopping at address end The value for addresses begin and end may be an absolute address specifiedas a hexadecimal value or a symbol name Width modifies the size of the data that is displayed Memory display starts at the address begin If no beginning address is provided the MD command uses the lastaddress that was displayed

M5307C3 USER`S MANUAL REVISION 1.1 Matrix Design

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