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hmc1190alp6ne copy.indd

1. 2Dh T pegoun fop 61 44x108 fop E 61 44x108 _ 61 44x108 ged fycoxs1 fcox fp gca 100x10 61 44x108 20000 where fycok fvcox is the desired channel spacing 100 kHz in this example 3072d C00h 2 Reg OCh 3 To program Reg 04h the closest integer N boundary frequency fy that is less than the smallest channel VCO frequency fyco must be calculated fy floor fyco7 fpp Using the current example 2800 2 108 ty fpp x floor ___ ita jagen asxer saxo 2764 8 MHz Then 2 4 fico fy fPD Reg 04h ci for channel 1 where fc 2800 2 MHz 224 2800 2x10 2764 8x10 61 4410 4 To change from channel 1 fyco7 2800 2 MHz to channel 2 fyco2 2800 3 MHz only Reg 04h needs to be programmed as long as all of the desired exact frequencies fyco Figure 71 fall between the same integer N boundaries fy lt fycox lt fy47 In that case ceil 9666560d 938000h 224 2800 3x10 2764 8x10 6144x108 9693867d 93EAABh_ andsoon 44x Reg 04h ee 1 2 7 3 4 Seed Register 1 3 1 4 The start phase of the fractional modulator digital phase accumulator DPA may be set to any desired phase relative to the reference frequency The phase is programmed in Reg 1Ah and Exact Frequency Mode is required Phase 27 x Reg1Ah 2 4 via the seed register Reg 1Ah 23 0 The HMC1190ALP6NE will automatically reload the start phase seed value into the DPA every time a new
2. GHz 25C 85C 40C Figure 33 High Side LO Conversion Gain vs Frequency at VGATE 4 8V I CONVERSION GAIN dB 0 5 1 15 2 25 3 3 5 4 FREQUENCY GHz 25C 85C 40C Figure 35 Low Side LO Noise Figure vs Temperature at VGATE 4 8V NOISE FIGURE dB 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz 25C 85C 40C 1 Balun losses at IF output ports are de embedded 2 At room temperature Figure 32 Low Side LO Input IP3 vs Frequency at VGATE 4 8V2 31 29 27 25 23 IIP3 dBm 0 5 1 15 2 2 5 3 3 5 4 FREQUENCY GHz 25C 85C 40C Figure 34 High Side LO Input IP3 vs Frequency at VGATE 4 8V2 31 29 27 25 23 IIP3 dBm 0 5 1 15 2 2 5 3 3 5 4 FREQUENCY GHz 25C 85C 40C Figure 36 High Side LO Noise Figure vs Temperature at VGATE 4 8V NOISE FIGURE dB 0 5 1 15 2 25 3 3 5 4 FREQUENCY GHz 25C 85C 40C For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 37 Channel to Channel Isolation vs Frequency 70
3. P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz VDDIF 5V 139 146 152 mA VCS1 VCS2 5V 2 7 3 3 1 mA Mixer Core Supply Currents VBIASIF1 VBIASIF2 5V 20 21 5 23 mA when IF1EN and IF2EN are Enabled VGATE1 VGATE2 3 3 3 mA LOBIAS1 LOBIAS2 5V 4 4 4 mA LOVDD 3 3V 136 143 150 mA VDDIF 5V o 0 0 mA VCS1 VCS2 5V 3 2 3 45 3 6 mA Mixer Core Supply Currents VBIASIF1 VBIASIF2 5V 1 3 1 6 1 9 mA when IF1EN and IF2EN are Disabled VGATE1 VGATE2 5V 0 0 0 mA LOBIAS1 LOBIAS2 5V 4 5 4 9 5 2 mA LOVDD 3 3V 3 2 3 45 3 6 mA LO_OUT differential LO_MIXER off 5V Supplies VDDLS VCC1 VCC2 VDDCP 144 149 154 mA 3 3V Supplies 3VRVDD DVDD3V VCCHF VCCPS VCCPD 44 5 47 49 5 mA LO_OUT single ended LO_MIXER off 5V Supplies VDDLS VCC1 VCC2 VDDCP 126 130 133 mA 3 3V Supplies 3VRVDD DVDD3V VCCHF VCCPS VCCPD 44 5 47 49 5 mA LO_OUT off LO_MIXER differential 5V Supplies VDDLS VCC1 VCC2 VDDCP 144 149 154 mA 3 3V Supplies 3VRVDD DVDD8V VCCHF VCCPS VCCPD 44 5 47 49 5 mA PLL VCO Core Supply Currents when CHIPEN is LO_OUT off LO_MIXER single ended Enabled 5V Supplies VDDLS VCC1 VCC2 VDDCP 12
4. wa RegAL1 4 13 Start Stop eg 2 RegA 2 0 m 0 2 4 5 n 0 1 2 3 5 6 7 8 50 MHz Max for y FSM VSPI Clocks vco FSM Figure 68 VCO Calibration A 5 bit step tuned VCO for example nominally requires 5 measurements for calibration worst case 6 measurements and hence 7 VSPI data transfers of 20 clock cycles each Total calibration time worst case is given by n T K128T 54 6T pp 2 7 20T cy EQ 7 ca or equivalently T val Tyra 6R lt 2 140 3 128 2 EQ 8 For guaranteed hold of lock across temperature extremes the resolution should be better than 1 8 the frequency step caused by a VCO sub band switch change Better resolution settings will show no improvement 1 1 1 1 4 VCO AutoCal Example The HMC1190ALP6NE must satisfy the maximum fpa limited by the two following conditions a N 16 fint N 2 20 0 fiac where N fvco fpa b fpa lt 100 MHz Suppose the HMC1190ALP6NE output frequency is to operate at 2 01 GHz Our example crystal frequency iS fta 50 MHz R 1 and m 0 Figure 68 hence Tes 20 ns 50 MHz Note when using AutoCal the maximum AutoCal Finite State Machine FSM clock cannot exceed 50 MHz see Reg OAh 14 13 The FSM clock does not affect the accuracy of the measurement it only affects the time to produce the result This same clock is used to clock the 16 bit VCO serial port If time to change frequencies is not a concern then one
5. 2 5 3 3 5 4 FREQUENCY GHz 25C 85C 40C Figure 23 Low Side LO Noise Figure vs Temperature at VGATE 5V 18 y NOISE FIGURE dB 0 5 d 1 5 2 2 5 3 3 5 4 FREQUENCY GHz 250 85C 400 1 Balun losses at IF output ports are de embedded 2 At room temperature Figure 20 Low Side LO Input IP3 vs Frequency at VGATE 5V 31 29 27 IIP3 dBm N ee 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz 25C 85C 40C Figure 22 High Side LO Input IP3 vs Frequency at VGATE 5V 2 31 29 27 25 IP3 dBm 0 5 1 15 2 25 3 3 5 4 FREQUENCY GHz 25C 85C 40C Figure 24 High Side LO Noise Figure vs Temperature at VGATE 5V 18 7 7 NOISE FIGURE dB 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz 25C 85C 40C For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 25 Low Side LO Conversion Gain Figure 26 Low Side LO Input IP3 vs vs Frequency at VGATE 4 9V I Frequency at VGATE 4 9V2
6. 20 and 524 284 Nirac is the fractional part from 0 0 to 0 99999 N 4 Reg 04h 224 R is the reference path division ratio Reg 02h Fytal is the frequency of the reference oscillator input fod is the PD operating frequency fya R As an example fii 1402 5 MHz k 2 fzo 2 805 MHz fetal 50 MHz R 1 fod 50 MHz Nint 56 Nrrac 0 1 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE 1 2 7 3 v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Reg 04h round 0 1 x 224 round 1677721 6 1677722 50e6 1677722 fyco 56 z7 2805 MHz 1 192 Hz error EQ 14 fyco fout 1402 5 MHz 0 596 Hz error EQ 15 2 In this example the output frequency of 1402 5 MHz is achieved by programming the 19 bit binary value of 56d 38h into intg_reg in Reg 03h and the 24 bit binary value of 1677722d 19999Ah into frac_reg in Reg 04h The 0 596 Hz quantization error can be eliminated using the exact frequency mode if required In this example the VCO output fundamental 2805 MHz is divided by 2 Reg 16h 5 0 2h 1402 5 MHz Exact Frequency Tuning Due to quantization effects the absolute frequency precision of a fractional PLL is normally limited by the number of bits in the fr
7. 2646 96 MHz Exact Frequency Mode ON PHASE NOISE dBc Hz 1 10 100 1000 10000 100000 OFFSET KHz Figure 64 Forward Transmission Gain N sat ET IN LO Sun DIFFERENTIAL OUTPUT a a s21 EXT IN LO Our SINGLE ENDED output FORWARD TRANMISSION GAIN dB o a 400 800 1200 1600 2000 2400 2800 OUTPUT FREQUENCY MHz Figure 61 Figure of Merit for PLL VCO 200 R e3 Typ FOM vs Offset 2280 OT Po FOM 1 f Noise NORMALIZED PHASE NOISE dBc Hz OFFSET Hz Figure 63 Fractional N Spurious Performance at 2646 96 MHz Exact Frequency Mode OFF 2 D 3S amp 100 120 PHASE NOISE dBc Hz 140 160 180 _ Lii a tat 1 10 100 1000 10000 100000 OFFSET KHz Figure 65 Closed Loop Phase Noise With External VCO HMC384LP4E at 2200 MHz 40 60 100 F PHASE NOISE dBc Hz 1 10 100 1000 10000 OFFSET KHz 1 Measured from a 50 source with a 100 Q external resistor termination See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details Full FOM performance up to maximum 3 3 Vpp input voltage 2 122 88 MHz clock input PFD 61 44 MHz Channel Spacing 240 kHz 3 S21 from Ext_VCO pin 43 44 in and LO pin32 33 out For price delivery and to place orders Analog Devices Inc One Technology Way P O Box
8. 4 ceil PD 1 2 7 3 3 Hittite Exact Frequency Channel Mode If it is desirable to have multiple equally spaced exact frequency channels that fall within the same interval ie fy lt fycok lt fpa where fyco is shown in Figure 71 and 1 lt k lt 2 it is possible to maintain the same integer N Reg 03h and exact frequency register Reg OCh settings and only update the fractional register Reg 04h setting The Exact Frequency Channel Mode is possible if EQ 16 is satisfied for at least two equally spaced adjacent frequency channels i e the channel step size To configure the HMC1190ALP6NE for Exact Frequency Channel Mode initially and only at the beginning integer Reg 03h and exact frequency Reg OCh registers need to be programmed for the smallest fyco frequency fyco7 in Figure 71 as follows 1 Calculate and program the integer register setting Reg 03h Nwr floor fyco fpp where fyco is shown in Figure 71 and corresponds to minimum channel VCO frequency Then the lower integer boundary frequency is given by fy Nir fpo 2 Calculate and program the exact frequency register value Reg OCh fpp fgcq where foca gcd fycok 1 fvcox fpp greatest common divisor of the desired equidistant channel spacing and the PD frequency fycoxs1 fvcox and fpp Then to switch between various equally spaced intervals channels only the fractional register Reg 04h needs to be programmed to the desired VCO channel frequenc
9. 5V supply through choke inductors See the 21 IF2P evaluation board schematic available on the HMC1190A product page 22 IF2N 41 20 VBIASIF1 Supply voltage pin for IF amplifier s bias circuits VBIASIF2 Connect to 5V supply through filtering 12 19 VORTEI Bias pins for mixer cores Set from 4 8V to 5V for operating frequency band VGATE2 RF Input Pins of the Mixer These pins are internally matched to 50 Ohms RF input pins require 13 18 RF1 RF2 off chip DC blocking capacitors See the evaluation board schematic available on the HMC1190A product page Bias control pins for Local Oscillator Amplifiers Connect these pins to a 5V supply through 270 14 17 Lona Ohms resistors Refer to application section for proper values of resistors to adjust LO amplifier current 15 24 RSV Reserved These pins are reserved for internal use leave them floating 16 LOVDD 3 3V Bias Supply for LO Drive Stages Refer to application circuit for appropriate filtering and bias generation information 25 CHIP_EN Chip Enable Connect to logic high for normal operation 26 LO N Negative Local Oscillator output This pin is used for single ended differential or dual output mode 27 LO P Positive Local Oscillator output This pin is used for differential or dual output mode only Whereas it can drive a separate load from LO_N it cannot be used when LO_N is disabled 28 VCC1 VCO Analog Supply1 5V nomin
10. 7 31 7 29 g 27 6 S 23 wi 21 19 17 15 0 5 1 1 5 2 2 5 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz 25C 85C 40C 25C 85C 40C Figure 27 High Side LO Conversion Gain Figure 28 High Side LO Input IP3 vs vs Frequency at VGATE 4 9V I Frequency at VGATE 4 9V2 12 r 31 7 10 ee 27 k g5 5 6 23 wi 4 21 8 19 Obi ceerg pe ee oe eee eee tee 17 0 15 i 0 5 1 15 2 25 3 3 5 4 0 5 1 1 5 2 25 3 3 5 4 FREQUENCY GHz FREQUENCY GHz 25C 85C 40C 25C 85C 40C Figure 29 Low Side LO Noise Figure vs Figure 30 High Side LO Noise Figure vs Temperature at VGATE 4 9V Temperature at VGATE 4 9V 18 r 18 7 i 7 NOISE FIGURE dB NOISE FIGURE dB 0 5 1 1 5 2 2 5 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz 25C 25C 85C 40C 85C 40C 1 Balun losses at IF output ports are de embedded 2 At room temperature For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 31 Low Side LO Conversion Gain vs Frequency at VGATE 4 8V P CONVERSION GAIN dB 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY
11. DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz VCO Calibration VCO Auto Calibration AutoCal The HMC1190ALP6NE uses a step tuned type VCO A step tuned VCO is a VCO with a digitally selectable capacitor bank allowing the nominal center frequency of the VCO to be adjusted or stepped by switching in out VCO tank capacitors A step tuned VCO allows the user to center the VCO on the required output frequency while keeping the varactor tuning voltage optimized near the mid voltage tuning point of the HMC1190ALP6NE s charge pump This enables the PLL charge pump to tune the VCO over the full range of operation with both a low tuning voltage and a low tuning sensitivity kvco The VCO switches are normally controlled automatically by the HMC1190ALP6NE using the Auto Calibration feature The Auto Calibration feature is implemented in the internal state machine It manages the selection of the VCO sub band capacitor selection when a new frequency is programmed The VCO switches may also be controlled directly via register Reg 15h for testing or for other special purpose operation To use a step tuned VCO in a closed loop the VCO must be calibrated such that the HMC1190ALP6NE knows which switch position on the VCO is optimum for the desired output frequency The HUC1190ALP6NE supports Auto Calibration AutoCal of the step tuned VCO The AutoCal fixes the VCO tuning voltage at the optimum mid point of the charge pump o
12. HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 VCO register e Reg 15h only required for manual control of VCO if Reg OAh 11 1 AutoCal disabled e Reg 16h is required to change the VCO Output Divider value if needed 2 The integer register Reg 03h e In integer mode an integer register write triggers AutoCal if Reg OAh 11 0 and is loaded into the prescaler automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the VCO Normally changes to the integer register cause large steps in the VCO frequency hence the VCO switch settings must be adjusted AutoCal enabled is the recommended method for integer mode frequency changes If AutoCal is disabled Reg OAh 11 1 a prior knowledge of the correct VCO switch setting and the corresponding adjustment to the VCO is required before executing the integer frequency change 1 1 4 VCO Output Mute Function The HMC1190ALPE6NE features an intelligent output mute function with the capability to disable the VCO output while maintaining the PLL and VCO subsystems fully functional The mute function is automatically controlled by the HMC1190ALP6NE and provides a number of mute control options including 1 Always mute Reg 16h 5 0 Od This mode is used for manual mute control 2 Automatically mute the output
13. L1 L2 68 nH 11112 47H L1 L2 47 nH _ L1 L2 27nH L1 L2 27 nH Figure 76 Conversion gain IIP3 vs IF Frequency over IF Amplifier Choke Inductors 1 Table 19 for Selected Frequency Bands 3 6 Input IP3 Dependence on RF Input Power The HMC1190ALP6NE accepts a wide range of RF input power Figure 77 shows the IIP3 vs RF input power for 1900 MHz RF and 150 MHz IF IIP3 dBm RF Power dBm Figure 77 IP3 vs RF Input Power RF 1900 MHz IF 150 MHz VGATE 5V 3 7 Enabling Disabling Mixer Features HMC1190ALP6NE has a dual channel down converter core but it can also be configured as a single channel one When single channel option is desired HMC1190ALP6NE s unused IF amplifier can be 1 Balun losses at IF output ports are de embedded 2 RF 3400 MHz to 3800 MHz LO 3300 MHz LOBias 5V For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz disabled through SPI interface HMC1190ALPE6NE can also be used as standalone PLL VCO In this case all IF and LO buffer amplifiers at mixer side can be disabled through SPI interface Value of Reg14 should be changed in order to make nec
14. Loss vs Frequency over Temperature vs Frequency over Temperature 1 RETURN LOSS dB RETURN LOSS dB 01 02 03 04 05 06 07 08 09 1 FREQUENCY GHz 0 1 0 4 0 7 1 1 3 1 6 1 9 2 2 2 5 2 8 3 1 3 4 37 4 FREQUENCY GHz 25C 850 40C 25C 85C 40C Figure 17 High Side LO Input P1dB vs Figure 18 Low Side LO Input P1dB vs Frequency over Temperature Frequency over Temperature 18 18 a a a no m 12 m 12 Kej pej i i 10 10 8 8 6 6 0 5 1 15 2 25 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz 25C 85C 40C 25C 85C 40C 1 Balun losses at IF output ports are de embedded 3 VGATE 5V 2 Low side LO 4 LO input Frequency 1900MHz LO power setting is 3 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 19 Low Side LO Conversion Gain vs Frequency at VGATE 5V mt CONVERSION GAIN dB 0 5 1 15 2 25 3 3 5 4 FREQUENCY GHz 25C 85C 40C Figure 21 High Side LO Conversion Gain vs Frequency at VGATE 5V Mt CONVERSION GAIN dB 0 5 1 1 5 2
15. MHz PFD 2 5 mA CP 174 pA Leakage 2 Using 100 MHz clock input 50MHz PFD 2 5 mA CP 174 pA Leakage For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 54 Auxiliary LO Output Figure 55 Auxiliary LO Output Open Loop Phase Noise vs Frequency Open Loop Phase Noise vs Temperature 40 100 a0 atobitd F 29 3 R 120 g 8 130 1 100 A Q Q 140 2 120 z 150 o i 160 160 170 180 it 180 1 10 100 1000 10000 100000 30 100 300 1000 4000 OFFSET KHz FREQUENCY MHz 3862 4 MHz 3044 MHz 27C 85C 40C 3643 33 MHz 2558 MHz 3491 74 MHz 2129 4 MHz Figure 56 Auxiliary LO Output Power vs Temperature Figure 57 Integrated RMS Jitter 15 0 3 z 10 2 0 25 g F E 0 2 O Q E o1s5f z o amp 5 0 1 5 7 0 05 G 700 7000 oo 500 4000 T a oy a 3500 an OUTPUT FREQUENCY MH2 OUTPUT FREQUENCY MHz 27C 85C 40C 40C 27C 85C Figure 59 Reference Input Sensitivity Figure 58 Typical VCO Sensitivity Square Wave 50 Q 80 220 70 222 60 b 224 _ w a 50
16. Reg 09h 13 7 and Reg O9h 6 0 are set to 50d the output current of each pump will For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz be 1 mA and the phase frequency detector gain k 1 mA 2m radians or 159 pA rad 1 2 1 1 2 Charge Pump Phase Offset In Integer Mode the phase detector operates with zero offset The divided reference signal and the divided VCO signal arrive at the phase detector inputs at the same time Integer mode does not require any CP Offset current When operating in Integer Mode simply disable CP offset in both directions Up and down by writing Reg O9h 22 21 00 b and set the CP Offset magnitude to zero by writing Reg O9h 20 14 0 In Fractional Mode CP linearity is of paramount importance Any non linearity degrades phase noise and spurious performance In fractional mode these non linearities are eliminated by operating the PD with an average phase offset either positive or negative either the reference or the VCO edge always arrives first at the PD ie leads A programmable CP offset current source is used to add DC current to the loop filter and create the desired phase offset Positive current causes the V
17. can be used whenever the desired frequency fyco can be exactly represented on a step plan where there are an integer number of steps lt 2 4 across integer N boundaries Mathematically this situation is satisfied if f fycok Mod fysg 0 wherefycg 9 U Fycorfpp ANA fog gt te EQ 16 Where gcd stands for Greatest Common Divisor fy maximum integer boundary frequency lt fyco1 fpp frequency of the Phase Detector and fyco are the channel step frequencies where 0 lt k lt 224 1 As shown in Figure 71 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz fvco fyco2 Integer Integer Boundary Boundary m fy fvco1 coz2 fvco3 fvco4 fyco2 2 fvcodt1 fvco2 frei fy 1 tN fo T Figure 71 Exact Frequency Tuning Some fractional PLLs are able to achieve this by adjusting shortening the length of the Phase Accumulator the denominator or the modulus of the Delta Sigma modulator so that the Delta Sigma modulator phase accumulator repeats at an exact period related to the interval frequency fycox fvco k 1 in Figure 71 Consequently the shortened accumulator results in more frequent repeating
18. enable 19 12 R W Reserved Reserved 20 R W Lock Detect Training 0 to 1 transition triggers the training Lock Detect Training is only required after changing Phase Detector frequency After changing PD frequency a toggle Reg 07h 20 from 0 to 1 retrains the Lock Detect R W CSP Enable Cycle Slip Prevention enable When enabled if the phase error becomes larger than approx 70 of the PFD period the charge pump gain is increased by approx 6mA for the duration of the cycle R W Reserved 2 0 Reserved Reg 08h Analog EN Registe as Reserved r DEFAULT 1BFFF h Reserved 5 0 Pin LD_SDO disabled 1 and Reg OFh 7 1 Pin LD_SDO is always driven this 5 R W ea Purpose Output Pin 1 id is required for use of GPO port 1 and Reg OFh 7 0 LDO_SPI is off if chip address not equal to 000 b allowing a shared SPI with other compatible parts 9 6 R W Reserved 4 15d Reserved 0 VCO Buffer and Prescaler Bias Disable 10 R W a ial Fresealer 1 1d 1 VCO Buffer and Prescaler Bias Enable Only applies to External VCO 20 11 R W Reserved 10 55d Reserved 21 R W High Frequency Reference 1 0 Program to 1 for XTAL gt 200 MHz 0 otherwise Output Logic Level on LD SDO pin 22 R W SDO Output Level 1 Od 0 1 8 V Logic Levels 1 DVDD8V Logic Level 23 R W Reserved 1 Od Reserved For price delivery and to place order
19. for LO amplifiers and set the reference currents to these LO amplifiers The LOBIAS voltage is generated from the 5V supply by series resistors R57 and R71 Changing LOBIAS2 voltage changes current consumed by LOVDD pin which can be seen at Table 18 HMC1190ALP6NE s flexible design allows users to choose best configuration for their needs For higher power consumption better OIP3 values can be achieved 1 Balun losses at IF output ports are de embedded For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz IIP3 dBm LOBias 3 75V LOBias 4V og LOBias 4 25V LOBias 4 50V LOBias 4 75V LOBias 3 75V LOBias 4V CONVERSION GAIN dB LOBias 4 25V LOBias 4 50V LOBias 4 75V 33 34 35 36 37 38 39 4 41 42 43 44 45 3 3 34 35 36 37 38 39 4 41 42 43 44 45 VCS V VCS V Figure 75 Conversion Gain IIP3 vs VCS1 VCS2 and LOBIAS2 voltages at 1900 MHz RF Input Table 17 VCS wT vs IF Amplifier Currents VCS Jumper J13 V VCS Pin V IF Amp mA _ R61 R73 ots Table 18 LOBIAS Voltage vs LO Amplifier Currents LOBIAS Jumper J12 V LOBIAS2 Pin V LO Ane mA R57 R71 5V 3 5 High
20. li t l license is granted by implication or otherwise under any patent or patent rights of Analog Devices one iii F raer online at www analog com Trademarks and registered trademarks are the property of their respective owners Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Table 1 Electrical Specifications T 25 C IF Frequency 150 MHz LO Power is set to 3 RF Input Power 5 dBm LOVDD 3VRVDD DVDD38V CHIPEN 3 3V VDDCP VCS1 VCS2 VBIASIF1 VBIASIF2 LOBIAS1 LOBIAS2 VCC1 VCC2 VGATE1 VGATE2 5V unless otherwise noted Mixer Core RF Input Frequency 700 3800 Range Mixer Core IF Output Frequency 50 350 Conversion Gain 5 IIP3 Noise Figure SSB Input 1 dB Compression LO Leakage at RF Port 44 8 49 2 49 5 50 4 48 8 44 2 50 1 48 8 RF to IF Isolation 43 1 39 2 46 7 39 9 41 5 461 44 8 544 Channel to Channel Isolation 55 9 52 6 53 5 51 4 51 49 4 49 8 43 5 2RF 2LO Response 83 71 6 75 7 73 9 81 5 82 2 67 3 761 68 5 68 68 7 69 1 dBc 3RF 3LO Response 89 73 75 3 74 8 86 7 741 79 7 73 6 75 2 71 8 75 5 69 9 dBc 1 LO Power Level can be adjusted using Reg 16h 2 LSB stands for lower side band and refers to RF lt LO USB stands for upper side ban
21. may set the calibration time for maximum accuracy and therefore not be concerned with measurement resolution Using an input crystal of 50 MHz R 1 and f 50 MHz the times and accuracies for calibration using EQ 6 and EQ 8 are shown in Table 11 Where minimal tuning time is 1 8 of the VCO band spacing Across all VCOs a measurement resolution better than 800 kHz will produce correct results Setting m 0 n 5 provides 781 kHz of resolution and adds 8 6 us of AutoCal time to a normal frequency hop Once the AutoCal sets the final switch value 8 64 us after the frequency change command the fractional register will be loaded and the loop will lock with a normal transient predicted by the loop dynamics Hence as shown in this example that AutoCal typically adds about 8 6 us to the normal time to achieve frequency lock Hence AutoCal should be used for all but the most extreme frequency hopping requirements For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Table 11 AutoCal Example with F 50 MHz R 1 m 0 25 MHz 1 1 2 0 04 5 04 12 5 MHz 2 2 4 0 08 5 28 6 25 MHz 3 3 8 0 16 5 76 3 125 MHz 4 5 32 0
22. 0 R W Control 0 Max Gain 3 dB 23 11 R W Reserved 13 0 Reserved For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Master enable for the entire VCO Subsystem LO1 Output Single Ended o R W VCO SubSys Master Enable 1 Needed Chip Enable is also required to set as enable mode 1 R W VCO Enable 1 2 R W External VCO Buffer Enable 1 ame A to output stage enable Only used when locking 3 R W PLL Buffer Enable 1 PLL Buffer Enable Used when using an internal VCO 4 R W LO1 Output Buffer Enable 1 Enables LO1 LO_P amp LO_N pins output buffer 5 R W LO2 Output Buffer Enable 1 Enables the LO2 LO2_N amp LO2_P pins output buffer 6 R W External Input Enable 1 Enables External VCO input 7 R W Pre Lock Mute Enable 1 Mute both output buffers until the PLL is locked Enables Single Ended output mode for LO output 1 Single ended mode LO_N pin is enabled and LO_P pin is 8 R W Enable 1 1 disabled 0 Differential mode both LO_N and LO_P pins enabled Please note that single ended output is o
23. 01h 2 b PD Block Reg 01h 3 c CP Block Reg 01h 4 d Reference Path Buffer Reg O1h 5 e VCO Path buffer Reg 01h 6 f Digital I O Test pads Reg 01h 7 To mute the output but leave the PLL and VCO locked please refer to VCO Output Mute Function section General Purpose Output GPO Pin The PLL shares the LD_SDO Lock Detect Serial Data Out pin to perform various functions While the pin is most commonly used to read back registers from chip via the SPI it is also capable of exporting a variety of signals and real time test waveforms including Lock Detect It is driven by a tri state CMOS driver with 200 Q Rout It has logic associated with it to dynamically select whether the driver is enabled and to decide which data to export from the chip In its default configuration after power on reset the output driver is disabled and only drives during appropriately addressed SPI reads This allows it to share the output with other devices on the same bus The pin driver is enabled if the chip is addressed ie The last 3 bits of SPI cycle 000 b before the rising edge of SEN If SEN rises before SCK has clocked in an invalid non zero chip address the HMC1190ALP6NE will start to drive the bus The BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER will naturally switch away from the GPO data and export the SDO during an SPI read To prevent this automatic data selection and always select the GPO signal set Prevent AutoM
24. 1 1 AutoCal disabled 3 VCO Divide Ratio and Gain Register e Reg 16h 5 0 is required to change the VCO Output Divider value if needed e Reg 16h 10 6 is required to change the Output Gain if needed 4 The fractional register Reg 04h The fractional register write triggers AutoCal if Reg OAh 11 0 and is loaded into the Delta Sigma modulator automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the fractional frequency change is loaded into the Delta Sigma modulator immediately when the register is written with no adjustment to the VCO Small steps in frequency in fractional mode with AutoCal enabled Reg OAh 11 0 usually only require a single write to the fractional register Worst case 3 Main Serial Port transfers to the HMC1190ALP6NE could be required to change frequencies in fractional mode If the frequency step is small and the integer part of the frequency does not change then the integer register is not changed In all cases in fractional mode it is necessary to write to the fractional register Reg 04h for frequency changes 1 1 3 Registers Required for Frequency Changes in Integer Mode A change of frequency in integer mode Reg O6h 11 0 requires Main Serial Port writes to For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES
25. 2 40 60 30 20 80 z 0 5 1 1 5 2 25 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz 25C 85C 40C AtIF At RF Figure 11 Low Side LO Conversion Gain Figure 12 Low Side LO Input IP3 vs LO Drive 21 vs LO Drive 31 29 g 27 z 3 E 25 5 g O 23 5 2 wi 24 2 2 19 17 i 0 5 1 1 5 2 2 5 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz LO Power Setting 0 19 Powar Eee 2 LO Power Setting 1 ower Setting LO Power Setting 2 LO Power Setting 2 LO Power Setting 3 LO Power Setting 3 1 Balun losses at IF output ports are de embedded 3 For low side LO 2 VGATE 5V For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 13 2RF 2LO Response vs Figure 14 3RF 3LO Response vs Frequency over Temperature 21 31 Frequency over Temperature 21 3 90 90 g 80 8 80 i M n nO 70 70 a a no N T T 60 o 60 Gy 50 q 50 40 n 40 1 0 5 1 1 5 2 2 5 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz 25C 85C 40C 25C 850 40C Figure 15 RF Input Return Loss Figure 16 IF Output Return
26. 5 4 FREQUENCY GHz 4 8V 4 9V 5V Figure 4 High Side LO Input IP3 vs VGATE 31 29 27 25 23 IIP3 dBm 21 0 5 1 15 2 25 3 3 5 4 FREQUENCY GHz 4 8V 4 9V 5V Figure 6 High Side LO Noise Figure vs VGATE 1 18 NOISE FIGURE dB 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz 4 8V 4 9V 5V 1 VGATE is bias voltage for passive mixer cores VGATE1 and VGATE2 pins Refer to pin description table 2 Balun losses at IF output ports are de embedded For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 7 Conversion Gain vs High Side LO Figure 8 Input IP3 vs High Side LO amp Low Side LO I amp Low Side LO 31 29 g 27 z 3 25 5 3 gt 23 mj Z a A Q 19 17 15 0 5 1 1 5 2 2 5 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz High Side LO Low Side LO High Side LO Low Side LO Figure 9 RF IF Isolation vs Temperature Figure 10 LO Leakage vs Frequency 80 0 70 20 8 60 A z a O PES 40 50 S
27. 64 8 64 781 kHz 5 6 64 1 28 12 48 390 kHz 6 7 195 kHz 7 8 1 1 1 2 Manual VCO Calibration for Fast Frequency Hopping If it is desirable to switch frequencies quickly it is possible to eliminate the AutoCal time by calibrating the VCO in advance and storing the switch number vs frequency information in the host This can be done by initially locking the HMC1190ALP6NE on each desired frequency using AutoCal then reading and storing the selected VCO switch settings The VCO switch settings are available in Reg 15h 8 1 after every AutoCal operation The host must then program the VCO switch settings directly when changing frequencies Manual writes to the VCO switches are executed immediately as are writes to the integer and fractional registers when AutoCal is disabled Hence frequency changes with manual control and AutoCal disabled requires a minimum of two serial port transfers to the HMC1190ALPE6NE once to set the VCO switches and once to set the PLL frequency If AutoCal is disabled Reg OAh 11 1 the VCO will update its registers with the value written via Reg 15h 8 1 immediately 1 1 2 Registers Required for Frequency Changes in Fractional Mode A large change of frequency in fractional mode Reg O6h 11 1 may require Main Serial Port writes to 1 The integer register intg Reg 03h only required if the integer part changes 2 Manual VCO Tuning Reg 15h only required for manual control of VCO if Reg OAh 1
28. 65 60 55 50 45 ISOLATION dB 40 35 30 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz High Side LO Low Side LO Figure 39 Low Side LO Conversion Gain Mismatch at VGATE 5V 1 1 0 8 0 6 0 4 0 2 0 0 2 0 4 0 6 0 8 CONVERSION GAIN MISMATCH dB 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz Figure 41 Low Side LO Conversion Gain vs VGATE VDDIF VDDIF 4 5V LOVDD 3V f VDDIF 4 75V LOVDD 3 15V VDDIF 5V LOVDD 3 3V i VDDIF 5 25V LOVDD 3 45V_ r VDDIF 5 5V LOVDD 3 6V A CONVERSION GAIN dB 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz 1 Balun losses at IF output ports are de embedded Figure 38 Channel to Channel Isolation vs IF Frequency 70 65 60 S 55 5 i O 50 E High Side LO a45 2 40 f 35 30 0 5 1 5 2 2 5 3 3 5 4 FREQUENCY GHz IF 50MHz _ F 100MHz F 150MHz _ F 200MHz Figure 40 Low Side LO Input IP3 Mismatch at VGATE 5V IIP3 MISMATCH dBm 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz Figure 42 Low Side LO Input IP3 vs VGATE VDDIF 31 29 27 25 23 IIP3 dBm 21 4 l VDDIF 4 5V LOVDD 3V 19 VDDIF 4 75V LOVDD 3 15V VDDIF 5V LOVDD 3 3V i VDDIF 5 25V LOVDD 3 45V 17 i VDDIF 5 5V LOVDD 3 6V ie 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwo
29. 6h 7 6 XREFP Reg16h 9 8 R Reg17h 05 VI eg17h 05 DIVIDER g Reg17h 09 Single Ended EN t LO2_N L02_P Figure 66 HMC1190ALP6NE PLL VCO Block Diagram 1 1 VCO Overview The VCO consists of a capacitor switched step tuned VCO and an output stage In typical operation the VCO is programmed with the appropriate capacitor switch setting which is executed automatically by the PLL AutoCal state machine if AutoCal is enabled Reg OAh 11 0 see section VCO Calibration for more information The VCO tunes to the fundamental frequency 2050 MHz to 4100 MHz and is locked by the CP output from the PLL subsystem The VCO controls the output stage of the HMC1190ALP6NE enabling configuration of e VCO Output divider settings configured in Reg 16h divide by 2 4 6 60 62 to generate frequencies from 33 MHz to 2050 MHz or divide by 1 to generate fundamental frequencies between 2050 MHz and 4100 MHz e Output gain settings Reg 16h 7 6 Reg 16h 9 8 e Single ended or differential output operation Reg 17h 9 8 e Always Mute Reg 16h 5 0 e Mute when unlock Reg 17h 7 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D 1 1 1 1 1 1 1 ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3
30. 7 130 132 5 mA 3 3V Supplies 3VRVDD DVDD3V VCCHF VCCPS VCCPD 44 5 47 49 5 mA LO_OUT differential LO_MIXER differential 5V Supplies VDDLS VCC1 VCC2 VDDCP 179 184 189 mA 3 3V Supplies 3VRVDD DVDD8V VCCHF VCCPS VCCPD 44 5 47 49 5 mA LO_OUT single ended LO_MIXER single ended 5V Supplies VDDLS VCC1 VCC2 VDDCP 146 150 154 mA 3 3V Supplies 3VRVDD DVDD3V VCCHF VCCPS VCCPD 44 5 47 49 5 mA VCCPD VCCPS VCCHF DVDD3V 3VRVDD 3 3V 44 5 47 49 5 mA PLL VCO Core Supply VDDCP VCC1 VCC2 VDDLS 5V 1 1 1 mA Currents when CHIPEN is i 3VRVDD DVDD3V VCCPD VCCPS VCCHF 3 3V 5 5 5 mA Disabled 1 LO Frequency 2400 MHz LO_MIX and LO_OUT outputs set to maximum gain For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Table 3 PLL amp VCO Specifications Logic High 1 2 Logic Low 0 6 Input Current 1 uA Input Capacitance 2 pF LO Output Frequency 50 4100 MHz VCO Frequency at PLL Input 2000 4100 MHz VCO Fundamental Frequency 2000 4100 MHz VCO Output Divider Range 1 2 4 60 62 1 62 Integer 16 524287 19 Bit N Divider Range Fractional 20 524283 Fractional Mode DC 100 MHz PD Fre
31. 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 66 Auxiliary LO Differential Output Figure 67 Auxiliary LO Single Ended Output Return Loss Return Loss 0 0 RETURN LOSS dB a RETURN LOSS dB a 100 1000 100 1000 OUTPUT FREQUENCY MHz OUTPUT FREQUENCY MHz Table 5 Loop Filter Configuration CP R3 R4 VTUNE gt R2 C1 C4 156 180 6 8 47 47 2 2 1 1 eS y c2 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Table 6 Harmonics of LO RF Frequency 0 9 GHz at 5 dBm LO Frequency 0 8 GHz at maximum level All values in dBc below IF power level 1RF 1LO LO Maximum level All values in dBm measured at RF port Table 8 MXN Spurious at IF Port Table 9 MXN Spurious at IF Port RF Frequency 1 9 GHz at 5 dBm RF Fr
32. ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Typical Applications The HMC1190ALPENE is Ideal for e Multiband Multi standard Cellular BTS Diversity Receivers e GSM amp 3G amp LTE WiMAX 4G e MIMO Infrastructure Receivers e Wideband Radio Receivers e Multiband Basestations amp Repeaters Functional Diagram Features Broadband Operation with no external matching High side and Low side LO injection Operation High Input IP3 of 24 dBm Power Conversion Gain of 8 9 dB Input P1dB of 11 dBm SSB Noise Figure of 9 dB 55 dBc Channel to Channel Isolation Enable Disable Mixer and PLLVCO independently Single ended RF input ports 7 Maximum Phase Detector Rate 100 MHz 2 5 5 z z a 2 az Low Phase Noise 110 dBc Hz in Band Typical ne ee PLL FOM re gaa z 3 Ss _ 230 dBc Hz Integer Mode 227 dBc Hz Frac vDDCP M Control 30 VTUNE tional Mode BIAS 2 29 VCC2 lt 180 fs Integrated RMS Jitter 1 kHz to 20 MHz CPt FO a LEO ag veci LO Low Noise Floor 165 dBc Hz cp2 p T 27 LO_P sean lee Aa na V a ON sends i Floor 161 dBc Hz XREFP 6 onher aE o 25 CHIP_EN pvpp3sv 17 al RSV External VCO Input diffe
33. Band RF Matching and Optimization of CG and IIP3 for High IF Applications The HMC1190ALP6NE s RF inputs are internally broadband matched to 500 RF inputs can be externally matched for a specific RF frequency band of interest to further improve Input IP3 IIP3 Matching RF inputs to a specific RF frequency band can be easily accomplished by adding a series inductor and a shunt capacitor See Table 19 for values of the external matching components for corresponding RF frequency bands LOBIAS1 LOBIAS2 pin voltages can be optimized for a specific RF frequency band by changing the resistor values in series with these pins Table 18 shows the resistor values R57 R71 for corresponding LOBIAS pin voltage 1 Balun losses at IF output ports are de embedded For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 31 29 oOo S a z z O 3 25 E Zz 2 O 23 amp T W w 21 8 oO O 19 17 t 15 100 150 200 250 300 350 400 450 500 100 150 200 250 300 350 400 450 500 IF Frequency MHz IF Frequency MHz L1 L2 680 nH L1 L2 680 nH 11 L2 150 nH 11 12 150 nH 11 12 68 nH
34. CO to lead negative current causes the reference to lead The CP offset is controlled via Reg O9h 20 14 The phase offset is scaled from O degrees that is the reference and the VCO path arrive in phase to 360 degrees where they arrive a full cycle late The specific level of charge pump offset current Reg O9h 20 14 is provided in EQ 9 It is also plotted in Figure 70 vs PD frequency for typical CP Gain currents Required CP Offset min 4 3x10 x Fpp x lop 0 25 x lo EQ 9 where Fpp Comparison frequency of the Phase Detector Hz lop is the full scale current setting A of the switching charge pump set in Reg 09h 6 0 13 7 700 T CP Current 2 5 mA 600 1 z Zz W amp 500 i oO CP Current 2 mA ti 400 2 W O 300 Q W a Z 200 5 9 100 W x 0 0 20 40 60 80 100 PHASE DETECTOR FREQUENCY MHz Recommended CP offset current vs PD frequency for typical CP gain currents Calculated using EQ 9 The required CP offset current should never exceed 25 of the programmed CP current It is recommended to enable the Up Offset and disable the Down Offset by writing Reg O9h 22 21 10 b Operation with CP offset influences the required configuration of the Lock Detect function Refer to the description of Lock Detect function in section Lock Detect When operating with PD frequency gt 80MHz the CP Offset current should be disabled for the frequency change and then re enabled after the PLL has se
35. E 0 25mm MAX 8 PACKAGE WARP SHALL NOT EXCEED 0 05mm 9 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND 10 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN Package Information HMC1190ALP6NE RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL3 1 4 Digit lot number XXXX 2 Max peak reflow temperature of 260 C For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Pin Descriptions allt Number Description 1 Power Supply for Charge Pump Analog Section 2 External Bypass Decoupling for Precision Bias Circuits 3 4 CP1 CP2 Charge Pump Outputs 5 38VRVDD Reference supply 3 3 V nominal 6 XREFP Reference Input The DC bias is generated internally Normally it is AC coupled externally 7 DVDD3V DC Power Supply for Digital CMOS Circuitry 3 3 V nominal 8 23 VCS1 VCS2 Bias Control for IF Amplifiers Connect these pins to a 5V supply through 590 Ohms resistors Refer to application section for proper values of resistors to adjust IF amplifier current 9 IF1N 10 IF1P Differential IF outputs Connect these pins to a
36. OADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 3 0 R W Reserved 4 1 Reserved Inverts the PD polarity program to 0 0 Use with a positive tuning slope VCO and Passive Loop Filter default when using internal VCO 4 RAW mp Phaze Select 1 9 1 Use with a Negative Slope VCO or with an inverting Active Loop Filter with a Positive Slope VCO Only recommended when using an External VCO and an active loop filter 5 R W PD Up Output Enable 1 1 Enables the PD UP output see also Reg OBh 9 6 R W PD Down Output Enable 1 1 Enables the PD DN output see also Reg OBh 10 8 7 R W Reserved 2 0 Reserved Program to Od 9 R W Force CP UP 1 0 Forces CP UP output on if CP is not forced down Use for Test only 10 R W Force CP DN 1 0 Forces CP DN output on if CP is not forced up Use for Test only a Force CP Mld Rail Use for Test only if Force CP UP or Force CP t RA korce OF Mig Rail 1 9 DN are enabled they have precedence 23 12 R W Reserved 12 T Reserved 2 14 Reg 0Ch Exact Frequency Register Comparison Frequency divided by the correction rate Must be an integer Frequencies at exactly the correction rate will have zero frequency error Only works in modulator Mode B 3rd order recommended modulator type in Reg 06h 3 2 Reg OCh must be 0 23 0 R W Number of Channels per Fpd 24 0 if using ohter DSM type 0 Disabled 1 Invalid gt 2 v
37. Output Divider setting divide by 2 4 6 60 62 in Reg 16h 5 0 The HMC1190ALP6NE automatically controls frequency tuning in the fundamental band of operation for more information see VCO Calibration To tune to frequencies below the fundamental frequency range lt 2050 MHz it is required to tune the HMC1190ALP6NE to the appropriate fundamental frequency then select the appropriate output divider setting divide by 2 4 6 60 62 in Reg 16h 5 0 1 2 7 1 Integer Mode The HMC1190ALPE6NE is capable of operating in integer mode For Integer mode set the following registers a Disable the Fractional Modulator Reg 06h 11 0 b Bypass the Modulator circuit Reg 06h 7 1 In integer mode the VCO step size is fixed to that of the PD frequency Integer mode typically has 3 dB lower phase noise than fractional mode for a given PD operating frequency Integer mode however often requires a lower PD frequency to meet step size requirements The fractional mode advantage is that higher PD frequencies can be used hence lower phase noise can often be realized in fractional mode Charge Pump offset should be disabled in integer mode Reg O9h 22 14 Oh For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DO
38. T Z 226 9 e f g 9 S 228 lt 30 Q 20 230 10 232 0 234 15 12 9 6 3 0 3 TUNING VOLTAGE V REFERENCE POWER dBm H core Tuning Cap 7 ML core Tuning Cap 15 50 MHz Square Wave 100 MHz Square Wave 14 MHz Square Wave 25 MHz Square Wave MH core Tuning Cap 7 CL core Tuning Cap 15 CH core Tuning Cap 15 L core Tuning Cap 15 1 Both Aux LO and MOD LO Gain Set to 3 Max Level both Aux LO and MOD LO Buffer Enabled measured from Auxiliary LO Port 2 RMS Jitter data is measured in fractional mode using 50 MHz reference frequency from 1 kHz to 100 MHz integration bandwidth 3 Measured from a 50 source with a 100 Q external resistor termination See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details Full FOM performance up to maximum 3 3 Vpp input voltage For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 60 Reference Input Sensitivity Sinusoid Wave 50 Q REFERENCE POWER dBm 14 MHz sin 25 MHz sin 50 MHz sin 100 MHz sin Figure 62 Fractional N Spurious Performance at
39. WNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 2 7 1 1 Integer Frequency Tuning In integer mode the digital AY modulator is shut off and the N divider Reg 03h may be programmed to any integer value in the range 16 to 219 1 To run in integer mode configure Reg 06h as described then program the integer portion of the frequency as explained by EQ 12 ignoring the fractional part a Disable the Fractional Modulator Reg O6h 11 0 b Bypass the delta sigma modulator Reg O6h 7 1 c To tune to frequencies lt 2050 MHz select the appropriate output divider value Reg 16h 5 0 1 2 7 2 Fractional Mode The HMC1190ALPENE is placed in fractional mode by setting the following registers a Enable the Fractional Modulator Reg O06h 11 1 b Connect the delta sigma modulator in circuit Reg O6h 7 0 1 2 7 2 1 Fractional Frequency Tuning This is a generic example with the goal of explaining how to program the output frequency Actual variables are dependant upon the reference in use The HMC1190ALPE6NE in fractional mode can achieve frequencies at fractional multiples of the reference The frequency of the HMC1190ALPE6NE fico is given by ee eee oe EQ 12 fout fico k EQ 13 Where fout is the output frequency after any potential dividers k is 1 for fundamental or k 2 4 6 58 60 62 depending on the selected output divider value Reg 16h 5 0 Nint is the integer division ratio Reg O3h an integer number between
40. _EN pin don t care see Power Down Mode description for more information 2 R W Keep Bias On 1 0 keeps internal bias generators on ignores Chip enable control 3 R W Keep PFD Pn 1 0 keeps PFD circuit on ignores Chip enable control 4 R W Keep CP On 1 0 keeps Charge Pump on ignores Chip enable control 5 R W Keep Reference Buffer ON 1 0 keeps Reference buffer block on ignores Chip enable control 6 R W Keep VCO on 1 0 keeps VCO divider buffer on ignores Chip enable control 7 R W Keep GPO Driver ON 1 0 keeps GPO output Driver ON ignores Chip enable control 9 8 R W Reserved 2 0 reserved 2 4 02h REFDIV lie iniia DEFAULT 1h Reference Divider R Value EQ 8 13 0 R W rdiv 14 1 min 1 max max 214 1 3FFFh 16383d Divider Integer part used in all modes see EQ 10 Fractional Mode min 20d 18 0 R W Integer Setting 19 ton max 219 4 7FFFCh 524 284d Integer Mode min 16d max 219 4 7FFFFh 524 287d For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz r Fractional Part DEFAULT 0h Divider Fractional part 24 bit unsigned see Fractional 2 6 Reg 04h Fr
41. a The Master host on the first 24 falling edges of SCLK places 24 bit data d23 d0 MSB first on SDI as shown in Figure 73 d23 d5 should be set to zero d4 d0 address of the register to be READ on the next cycle b the slave HMC1190ALP6NE shifts in data on SDI on the first 24 rising edges of SCK c Master places 5 bit register address r4 r0 the READ ADDRESS register MSB first on the next 5 falling edges of SCK 25 29 r4 rO 00000 d Slave shifts the register bits on the next 5 rising edges of SCK 25 29 e Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCK 30 32 Chip address is always 000 b f Slave shifts the chip address bits on the next 3 rising edges of SCK 30 32 g Master asserts SEN after the 32nd rising edge of SCK h i J Slave registers the SDI data on the rising edge of SEN Master clears SEN to complete the the address transfer of the two part READ cycle If one does not wish to write data to the chip during the second cycle then it is recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle k Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK I Slave HMC1190ALP6NE shifts the SDI data on the next 32 rising edges of SCK On these same edges the slave places the desired read data ie data from the address specified in Reg OOh 4 0 of the first cycle on LD_SDO whic
42. actional modulator For example a 24 bit fractional modulator has frequency resolution set by the phase detector PD comparison rate divided by 224 The value 274 in the denominator is sometimes referred to as the modulus Hittite PLLs use a fixed modulus which is a binary number In some types of fractional PLLs the modulus is variable which allows exact frequency steps to be achieved with decimal step sizes Unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period channel step size For this reason Hittite PLLs use a large fixed modulus Normally the step size is set by the size of the fixed modulus In the case of a 50 MHz PD rate a modulus of 274 would result in a 2 98 Hz step resolution or 0 0596 ppm In some applications it is necessary to have exact frequency steps and even an error of 3 Hz cannot be tolerated Fractional PLLs are able to generate exact frequencies with zero frequency error if N can be exactly represented in binary eg N 50 0 50 5 50 25 50 75 etc Unfortunately some common frequencies cannot be exactly represented For example Nya 0 1 1 10 must be approximated as round 0 1 x 224 224 0 100000024 At fpp 50 MHz this translates to 1 2 Hz error Hittite s exact frequency mode addresses this issue and can eliminate quantization error by programming the channel step size to Fpp 10 in Reg OCh to 10 in this example More generally this feature
43. al 29 VCC2 VCO Analog Supply 2 5V nominal 30 VTUNE VCO Varactor VTUNE is the tuning port input 31 SEN PLL Serial Port Enable CMOS Logic Input 32 SDI PLL Serial Port Data CMOS Logic Input 33 SCK PLL Serial Port Clock CMOS Logic Input 34 LD SDO Lock Detect Serial Data or General Purpose tig Logic Output GPO This is a multifunction 35 EXT_VCO_N External VCO negative input 36 EXT_VCO_P External VCO positive input 37 VCCHF Analog supply 3 3 V nominal 38 VCCPS Analog supply Prescaler 3 3 V nominal 39 VCCPD Analog supply Phase Detector 3 3 V nominal 40 VDDLS Analog supply Charge Pump 5 V nominal For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Evaluation PCB AN MATT HTL Wil TN WAAAY A WANT SHIT AH AAA ANNI WAM AH WANN UIA AHN tH CARH aT z oe 2 giTCXO_TPLL3V 7 Ae A A BS U care a J6 foe 5V Sm Reo e The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground
44. alid max 224 1 FFFFFFh 16 777 215d For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 2 15 Reg OFh GPO Register Defautt Description o Select signal to be output to SDO pin when enabled DEFAULT LOCK DETECT Data from RegOF 5 Lock Detect Output Lock Detect Trigger Lock Detect Window Output Ring Osc Test Pullup Hard from CSP PullDN hard from CSP Reserved Reference Buffer Output 9 Ref Divider Output 10 VCO divider Output 11 Modulator Clock from VCO divider 12 Auxiliary Clock 13 Aux SPI Clock 14 Aux SPI Enable 15 Aux SPI Data Out 16 PD DN 17 PD UP 18 SD3 Clock Delay 19 SD3 Core Clock 20 AutoStrobe Integer Write 21 Autostrobe Frac Write 22 Autostrobe Aux SPI 23 SPI Latch Enable 24 VCO Divider Sync Reset 25 Seed Load Strobe 26 29 Not Used 30 SPI Output Buffer En 31 Soft RSTB OPNOTRYODAO 4 0 R W GPO 5 1 5 R W GPO Test Data 1 0 1 GPO Test Data when GPO_Select 0 1 Outputs GPO data only 6 R W Prevent Automux SDO l o 0 Automuxes between SDO and GPO data 7 R W Reserved 1 0 Reserved Program to 1 if external pull ups a
45. ase Noise with External HMC384LP4E VCO at 2200 MHz For detailed theory of operation of PLL VCO please refer to the HMC1190A PLLs with Integrated VCOs RF VCOs Operating Guide which will be provided under HUC1190ALP6NE web page For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D
46. at 3862 MHz Measured at 2 5 V 15 MHz V VCO Tuning Sensitivity at 3643 MHz Measured at 2 5 V 14 5 MHz V VCO Tuning Sensitivity at 3491 MHz Measured at 2 5 V 16 2 MHz V VCO Tuning Sensitivity at 3044 MHz Measured at 2 5 V 14 6 MHz V VCO Tuning Sensitivity at 2558 MHz Measured at 2 5 V 15 4 MHz V VCO Tuning Sensitivity at 2129 MHz Measured at 2 5 V 14 8 MHz V VCO Supply Pushing Measured at 2 5 V 2 MHz V Enable Settling Time Mixer Core Enabled 140 ns Disable Settling Time Mixer Core Disabled 110 ns For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES Figure 1 Low Side LO Conversion Gain vs VGATE 1 71 12 CONVERSION GAIN dB 0 5 1 15 2 2 5 3 3 5 4 FREQUENCY GHz 4 8V 4 9V 5V Figure 3 High Side LO Conversion Gain vs VGATE 1 21 12 CONVERSION GAIN dB oO 0 5 1 15 2 25 3 3 5 4 FREQUENCY GHz 4 8V 4 9V 5V Figure 5 Low Side LO Noise Figure vs VGATE 18 7 NOISE FIGURE dB 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz 4 8V 4 9V 5V HMC1190ALP6NE BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz v00 1115 Figure 2 Low Side LO Input IP3 vs VGATE 1 31 7 IIP3 dBm 0 5 1 1 5 2 2 5 3 3
47. ciple of Operation HMC1190ALP6NE s single ended RF inputs are converted into differential through the on chip integrated baluns The single ended RF inputs are internally broadband matched to 50 Q and require only standard DC blocking capacitors The HMC1190ALP6NE s IF amplifiers are designed for differential 200 Q output load impedance A few external components are required at these IF outputs for the broadband frequency response as recommended in the application circuit Refer to the IF output interface section for detailed information The HMC1190ALP6NE requires 5V and 3 3V and supply voltages and external bias voltages Bias voltages generate reference currents for the IF and LO amplifiers 3 3V supply voltage and the external bias voltages can be generated from 5 5V supply voltage to operate with a single supply Please refer to the bias voltage optimization section for more information The reference currents to the IF and LO amplifiers can be disabled through SPI interface See Enabling Disabling Mixer Features section for details 3 2 Bias Voltage Optimization Using External Resistors The VCS1 VCS2 LOBIAS1 LOBIAS2 VGATE1 and VGATE2 pins of HMC1190ALP6NE requires different supply voltages VGATE1 VGATE2 LOBIAS1 LOBIAS2 VCS1 VCS2 voltages are already generated from 5 5V supply voltage on evaluation board See the evaluation board schematic available on the HMC1190A product page These bias voltages can be optimized by
48. d and refers to RF gt LO 3 Balun losses at IF output ports are de embedded 4 VGATE1 VGATE2 4 9V 5 RF1 input power 5 dBm measurement taken from IF2 output RF2 and IF1 ports are terminated with 50 Ohms Table 2 DC Power Supply Specifications 4 5 5 5 5 v 5V Supply Rails VDDCP VCS1 VCS2 VDDLS VBIASIF1 VBIASIF2 LOBIAS1 LOBIAS2 VCC1 VCC2 200 l 330 556 2 mA 3 3 3 3 6 V 3 3V Supply Voltage LOVDD 3VRVDD DVDD3V VCCPD VCCPS VCCHF 142 1 193 246 2 mA VGATE1 VGATE2I5 VDDIF 0 2 5 VDDIF v 5V Supply Rails 41 VDDCP VCS1 VCS2 VDDLS VBIASIF1 VBIASIF2 LOBIAS1 LOBIAS2 VCC1 VCC2 324 330 338 mA 5V 3 3V Supply Voltage 41 LOVDD 3VRVDD DVDD8V VCCPD VCCPS VCCHF 3 3V 185 199 200 mA 1 LO Frequency 2400 MHz LO_MIX is enabled in single ended mode LO_OUT is disabled LO_MIX power setting 0 divide ratio 1 divider stage high gain 0 2 LO Frequency 2400 MHz LO_MIX and LO_OUT are both enabled in differential mode LO_MIX and LO_OUT power setting 3 divide ratio 62 divider stage high gain 1 3 VGATE1 and VGATE2 are obtained through resistors which are connected to VDDIF 4 LO Frequency 2400 MHz LO_MIX is enabled in differential mode LO_OUT is disabled LO_MIX power setting 3 When LO_OUT is enabled in differential mode the bias current increases by 34 mA Typ For price delivery and to place orders Analog Devices Inc One Technology Way
49. e phase difference between the two signals The output current varies linearly over a full 27 radians 360 of input phase difference 1 2 1 1 Charge Pump A simplified diagram of the charge pump is shown in Figure 69 The CP consists of 4 programmable current sources two controlling the CP Gain Up Gain Reg O9h 13 7 and Down Gain Reg O9h 6 0 and two controlling the CP Offset where the magnitude of the offset is set by Reg 09h 20 14 and the direction is selected by Reg 09h 21 1 for up and Reg 09h 22 1 for down offset CP Gain is used at all times while CP Offset is only recommended for fractional mode of operation Typically the CP Up and Down gain settings are set to the same value Reg O9h 13 7 Reg O9h 6 0 UP Offset Reg09 21 UP Gain j 0 635uA Reg09 13 7 1 0 2 54mA 5uA Step 20uA Step Reg09 20 14 UP REF PATH PP Loop a Filter VCO PATH DN DN Offset Reg09 22 DN Gain 0 635uA Reg09 6 0 j 5uA Step 0 2 54mA 1 Reg09 20 14 20uA Step Figure 69 Charge Pump Gain amp Offset Control 1 2 1 1 1 Charge Pump Gain Charge pump Up and Down gains are set by Reg 09h 13 7 and Reg O9h 6 0 respectively The current gain of the pump in Amps radian is equal to the gain setting of this register divided by 27 Typical CP gain setting is set to 2 to 2 5 mA however lower values can also be used Values lt 1 mA may result in degraded Phase Noise performance For example if both
50. ecommended below 200 MHz and High frequency Reg 08h 21 1 for 200 to 350 MHz operation The buffer is internally DC biased with 100 Q internal termination For 50 Q match an external 100 Q resistor to ground should be added followed by an AC coupling capacitor impedance lt 1 Q then to the XREFP pin of the part At low frequencies a relatively square reference is recommended to keep the input slew rate high At higher frequencies a square or sinusoid can be used The following table shows the recommended operating regions for different reference frequencies If operating outside these regions the part will normally still operate but with degraded reference path phase noise performance For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE 1 2 2 1 1 2 3 1 2 4 v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Table 12 Reference Sensitivity Table lt 10 YES 0 6 2 5 X x x 10 YES 0 6 2 5 X x x 25 YES 0 6 25 ok 8 15 50 YES 0 6 25 YES 6 15 100 YES 0 6 25 YES 5 15 150 ok 0 9 2 5 YES 4 12 200 ok 1 2 25 YES 3 8 Input referred phase noise of the PLL when operating at 50 MHz is between 148 and 150 dBc Hz at 10 kHz off
51. equency 2 5 GHz at 5 dBm LO Frequency 1 8 GHz at maximum level LO Frequency 2 4 GHz at maximum level All values in dBc below IF power level 1RF 1LO All values in dBc below IF power level 1RF 1LO Table 10 Truth Table HIGH ON 1 IF and LO amplifiers can be disabled through SPI bus See Enabling Disabling Mixer Features application section For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Absolute Maximum Ratings Recommended Operating Conditions 20 dBm 5V 6V 0 3V to 5 5V 0 3V to 3 6V 40 C to 85 C 150 C 3 3 C W 65 C to 150 C 40 C to 85 C Class 1B Class IV Outline Drawing NOTES 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY 3 LEAD AND GROUND PADDLE PLATING NiPdAu 4 DIMENSIONS ARE IN INCHES MILLIMETERS 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 CHARACTERS TO BE HELVETICA MEDIUM 025 HIGH WHITE INK OR LASER MARK LOCATED APPROX AS SHOWN 7 PAD BURR LENGTH SHALL BE 0 15mm MAX PAD BURR HEIGHT SHALL B
52. equency Registe Frequency Tuning f Fractional Division Value Reg4 23 0 2 4 23 0 R W Fractional Setting 24 0 Used in Fractional Mode only min 0 max 224 1 FFFFFFh 16 777 215d Reg 05h Reserved 23 0 R W Reserved 24 0 Reserved 2 8 Reg 06h Delta Sigma Modulator Register DEFAULT 30F0Ah Name Nidth Default Description 1 0 R W Reserved 2 2 Reserved Program to Oh Select the Delta Sigma Modulator Type 0 1st order 3 2 R W DSM Order 2 2 1 2nd Order 2 3rd Order Recommended 3 Reserved 0 Normal SPI Load all register load on rising edge of SEN 1 Synchronous SPI registers Reg 03h Reg 04h Reg 1Ah wait to load synchronously on the next internal clock cycle Normally When this bit is 0 SPI writes into the internal state machines counters happen asynchronously relative to the internal clocks This can create freq phase disturbances if writing register 3 40r 1A When this bit is enabled the internal SPI registers are loaded synchronously with the internal clock This means that the data in the SPI shifter should be held constant for at least 2 PFD clock periods after SEN is asserted to allow this retiming to happen cleanly 4 R W Synchronous SPI Mode 1 0 Exact Frequency Mode 1 Exact Frequency Mode Enabled 5 R W Enable 0 Exact Frequency Mode Disabled 6 R W Reserved 1 0 Reserved 0 Use Modulator Requ
53. essary enable disable changes See Table 20 for details Table 20 Mixer Enable Disable 3F4 T IF2 disabled IF1 and LO_Mixer enabled 3F2 IF1 disabled IF2 and LO_Mixer enabled 3F6 IF1 IF2 and LO_Mixer disabled 3F0 IF1 IF2 and LO_Mixer enabled 3 8 Using an External VCO In order to configure HMC1190ALP6NE to use with an external VCO Reg 17h needs to be configured to disable the on chip VCO and VCO to PLL path Enable External Buffer second CP link and External I O switch To make these changes Reg 17h 0 11 should be configured as 3157d Figure 79 shows HMC1190ALP6NE configured as PLL alone used with External VCO HMC384LP4E Loop Filter components are used as below R58 R64 820 820 CP1 e s VTUNE aL C73 R59 _L c72 i C100 T 22pF 1 8K T 39pF T 39pF C68 m 0 001uF Figure 78 Loop filter components for HUC1190ALPE6NE is configured as PLL alone used with external VCO HMC384LP4E 1 Balun losses at IF output ports are de embedded For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz PHASE NOISE dBc Hz N 1 10 100 1000 10000 OFFSET KHz Figure 79 Closed Loop Ph
54. external resistors VCS1 VCS2 LOBIAS1 LOBIAS2 VGATE1 and VGATE2 The resistor values of VCS1 VCS2 on evaluation board are 590 Ohms LOBIAS1 and LOBIAS2 series resistor values are 270 Ohms Refer to the VCS Interface and LOBIAS Interface section for more information On the evaluation board VGATE1 VGATE2 pin voltages are 5V however VGATE1 VGATE2 pin voltages can be tuned between 4 8V and 5V for optimization of Input IP3 and conversion gain performances After VGATE1 VGATE2 pin voltages are optimized these pin voltages can be generated from 5V supply by changing the values of series resistors R54 and R56 Refer to the VGATE interface section for more information 3 3 VGATE Interface The VGATE1 VGATE2 pins are bias pins for mixer cores On evaluation board VGATE1 VGATE2 pin voltages are set to 5V However voltage can be tuned between 4 8V and 5V for optimizing input IP3 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz and conversion gain performances for desired frequency band Higher IIP3 values can be obtained by increasing the VGATE1 VGATE2 pin voltages but this will reduce HMC1190ALP6NE s conversion gain Figure 74 shows the
55. ficant The arrival of the two edges within the designated window increments an internal counter Once the count reaches and exceeds a user specified value Reg 07h 2 0 the HMC1190ALP6NE declares lock Failure in registering the two edges in any one window resets the counter and immediately declares an un locked condition Lock is deemed to be reestablished once the counter reaches the user specified value Reg 07h 2 0 again For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 2 4 1 Lock Detect Configuration Optimal spectral performance in fractional mode requires CP current and CP offset current configuration discussed in detail in section Charge Pump These settings in Reg 09h impact the required LD window size in fractional mode of operation To function the required lock detect window size is provided by EQ 10 lop ottset A Fpp HZ x Iop A 2 66 x10 sec Fpp Hz _ f LD Window seconds 2 in Fractional Mode EQ 10 LD Window seconds in Integer Mode x FPD where Fpp is the comparison frequency of the Phase Detector lop offset S the Charge Pump Offset Current Reg 09h 20 14 lop is the
56. fractional frequency is selected Certain zero or binary seed values may cause spurious energy correlation at specific frequencies For most cases a random or non zero non binary start seed is recommended Soft Reset amp Power On Reset The HMC1190ALP6NE features a hardware Power on Reset POR All chip registers will be reset to default states approximately 250 us after power up The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg OOh Power Down Mode Power down the HMC1190ALP6NE by pulling CEN pin pin 17 low assuming no SPI overrides Reg Oth 0 1 This will result in all analog functions and internal clocks disabled Current consumption will typically drop below 10 pA in Power Down state The serial port will still respond to normal communication in Power Down mode It is possible to ignore the CEN pin by setting Reg O1h 0 0 Control of Power Down Mode then comes from the serial port register Reg O1h 1 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D 1 5 ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz It is also possible to leave various blocks on when in Power Down see Reg 01h including a Internal Bias Reference Sources Reg
57. full scale current setting of the switching charge pump Reg O9h 6 0 or Reg O9h 13 7 If the result provided by EQ 10 is equal to 10 ns Analog LD can be used Reg 07h 6 0 Otherwise Digital LD is necessary Reg O7h 6 1 Table 13 provides the required Reg 07h settings to appropriately program the Digital LD window size From Table 13 simply select the closest value in the Digital LD Window Size columns to the one calculated in EQ 10 and program Reg 07h 9 8 and Reg 07h 7 5 accordingly Table 13 Typical Digital Lock Detect Window Fastest 00 6 5 8 11 17 29 53 100 195 01 T 8 9 12 8 21 36 68 130 255 10 7 1 9 2 13 3 22 38 72 138 272 Slowest 11 7 6 10 2 15 4 26 47 88 172 338 1 2 4 1 1 Digital Window Configuration Example Assuming fractional mode with a 50 MHz PD and e Charge Pump gain of 2 mA Reg 09h 13 7 64h Reg O9h 6 0 64h e Down Offset Reg 09h 22 21 10 b e Offset current magnitude of 400 pA Reg O9h 20 14 50h Applying EQ 11 the required LD window size is 1 50 x 10 Hz 0 4x10 A 2 66x10 50x 10 Hz x2x10 A eee EQ 11 LD Window seconds 13 33 nsec 2 Locating the Table 13 value that is closest to the EQ 11 result in this case 13 3 13 33 To set the Digital LD window size simply program Reg 07h 9 8 10 b and Reg 07h 7 5 010 b according to Table 13 There is always a good solution fo
58. h automatically switches to SDO mode from LD mode disabling the LD output m Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock Detect on LD_SDO For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz j SDI setup time to SCK Rising Edge ns SCK Rising Edge to SDI hold time 3 ns SEN low duration 10 ns SEN high duration 10 ns SCK Rising Edge to SDO time 8 2ns 0 2ns pF ns Recovery Time 10 ns SCK 32 Rising Edge to SEN Rising Edge 10 ns For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz FIRST CYCLE A QAR READ Address Register Address 00000 Chip Address 000 LD_SDO ob wes CEEE TRI STATE SEN SECOND CYCLE 1 18 19 20 23 24 25 28 SDI x d23 d5 a4 ao r4 r3 Tocnainat SEN Note Read back on LD_SDO can f
59. hnology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 2 12 Reg 0Ah VCO AutoCal Configuration Register DEFAULT 2046 h Used by internlan AutoCal state machine R Divider Cycles 2 0 R W Vtune Resolution 3 6d 7 256 div cycles for frequency measurement Measurement should last gt 4 usec Note 1 does not work if R divider 1 10 3 R W Reserved 8 16d Reserved 0 AutoCal Enabled 1 AutoCal disabled 12 R W Reserved 1 0 Reserved Set the AutoCal FSM and VSPI Clock 50 MHz maximum 0 Input Crystal Reference 14 13 R W FSM VSPI Clock Select 2 1 1 Input Crystal Reference 4 2 Input Crystal Reference 16 3 Input Crystal Reference 32 11 R W AutoCal Disable 1 0 16 15 R W Reserved 2 0 Reserved 0 Does not attempt to relock if lock is lost 17 R W Auto relock one Try 1 0 1 Attempts to relock if Lock Detect fails for any reason Only tries once 23 18 R W Reserved 5 0 Reserved For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BR
60. ices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 Use the 3 outputs as an SPI port 0 AWCSPIMOQS 1 0 0 Use the 3 outputs as a static GPO port along with Reg 14h 3 1 3 1 Aux GPO Values 3 0 3 Output values can be set indivually when Reg 10h 0 1 A i 14 Aux GPO 3 3 V 1 0 0 1 8 V output out of the Auxiliary GPO pins when Reg 10h 0 1 1 3 3 V output out of the Auxiliary GPO pins when Reg 10h 0 1 8 5 Reserved 4 1 Reserved When set CHIP_EN pin is used as a trigger for phase synchronization Can be used to synchronize multiple 9 Phase Sync 1 1 HMC1190ALPENE or to along with the Reg 1Ah value to phase step the output Exact Frequency Mode must be enabled Option to send GPO multiplexed data ex Lock Detect to one of the auxiliary outputs 0 None 11 10 Aux SPI GPO Output 2 0 1 to 0 2 to 1 3 to 2 When disabled 0 Outputs Hi Z 13 12 Aux SPI Outputs 2 0 1 Outputs stay driven 2 Outputs driven to high 3 Outputs driven to low 23 14 Reserved 10 0 Reserved 2 2 Reg 15h M re 1 VCO subsystem manual calibration enabled 0 ManualGalibra
61. id information may be read by reading the content of read only register chip_ID in Reg OOh For HMC1190ALPE6NE chip id is C7701Ah 1 7 Serial Port Overview The SPI protocol has the following general features a 3 bit chip address enable the use of up to 8 devices connected to the serial bus b Simultaneous Write Read during the SPI cycle c 5 bit address space d 3 wire for Write Only capability 4 wire for Read Write capability Typical serial port operation can be run with SCLK at speeds up to 50 MHz 1 7 1 Serial Port WRITE Operation AVDD DVDD 3V AGND DGND 0V Table 14 SPI WRITE Timing Characteristics Parameter Conditions o Min Typ Max Units t4 SDI setup time to SCLK Rising Edge 3 ns to SCLK Rising Edge to SDI hold time 3 ns t3 SEN low duration 10 ns t4 SEN high duration 10 ns t5 SCLK 32 Rising Edge to SEN Rising Edge 10 ns te Recovery Time 10 ns Max Serial port Clock Speed 50 MHz A typical WRITE cycle is shown in Figure 72 D sa gt The Master host places 24 bit data d23 d0 MSB first on SDI on the first 24 falling edges of SCLK the slave HMC1190ALP6NE shifts in data on SDI on the first 24 rising edges of SCLK Master places 5 bit register address to be written to r4 r0 MSB first on the next 5 falling edges of SCLK 25 29 Slave shifts the register bits on the next 5 rising edges of SCLK 25 29 Master places 3 bi
62. ies of the two PD inputs are different and the phase difference of the two inputs at the PD varies rapidly over a range much greater than 27 radians Since the gain of the PD varies linearly with phase up to 27 the gain of a conventional PD will cycle from high gain when the phase difference approaches a multiple of 271 to low gain when the phase difference is slightly larger than a multiple of O radians The output current from the charge pump will cycle from maximum to minimum even though the VCO has not yet reached its final frequency The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle This can make the VCO frequency actually reverse temporarily during locking This phenomena is known as cycle slipping Cycle slipping causes the pull in rate during the locking phase to vary cyclically Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal Laplace analysis The HMC1190ALP6NE PD features an ability to reduce cycle slipping during frequency tunning The Cycle Slip Prevention CSP feature increases the PD gain during large phase errors 1 2 7 Frequency Tuning HMC1190ALP6NE VCO subsystem always operates in fundamental frequency of operation 2050 MHz to 4100 MHz The HMC1190ALP6NE generates frequencies below its fundamental frequency 33 MHz to 2050 MHz by tuning to the appropriate fundamental frequency and selecting the appropriate
63. il is the ceiling function meaning round up to the nearest integer icok fy fp where ceil Example To configure the HMC1190ALP6NE for exact frequency mode at fyco 2800 2 MHz where Phase Detector PD rate fpp 61 44 MHz Proceed as follows Check EQ 16 to confirm that the exact frequency mode for this fyco is possible f fyca 9CA feo fpo and hca 2 x 6 foa 9od 2800 2108 61 44 10 120x10 gt 3750 Since EQ 16 is satisfied the HMC1190ALP6NE can be configured for exact frequency mode at fyco 2800 2 MHz as follows For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz f 2800 2 x 10 1 Nyy Reg 03h floor Y amp floor 45d 2Dh ae pp 61 44x106 top E 61 44x10 _ 61 44x10 2 Reg 0Ch 3072d CO00h gca fcor 1 fvcor feo ged 100x10 61 44x108 20000 3 To program Reg 04h the closest integer N boundary frequency fy that is less than the desired VCO frequency fyco must be calculated fy fpp Nwr Using the current example fy fop x Niyr 45x 61 44 108 2764 8 MHz 224 2800 2x 10 2764 8 x108 61 44x10 9666560d 938000h x 24 hog h Then Reg04h cl
64. ired for Fractional Mode 1 Bypass Modulator Required for Integer Mode Note When enabled fractional modulator output is ignored but 7 R W Fractional Bypass 1 o fractional modulator continues to be clocked if Reg O6h 11 1 This feature can be used to test the isolation of the digital frac tional modulator from the VCO output in integer mode 1 loads the modulator seed start phase whenever the fractional register Reg 04h is written 8 R W AUTOSE LEN l 1 0 when fractional register Reg 04h write changes frequency modulator starts at previous value phase 10 9 R W Reserved 2 3 Reserved 11 R W Delta Sigma Modulator 1 1 0 Disable DSM used for Integer Mode Enable 1 Enable DSM Core required for Fractional Mode 23 12 R W Reserved 12 aed Reserved 30h For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES R W Ikd_winent_max HMC1190ALP6NE v00 1115 lock detect window BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz sets the number of consecutive counts of divided VCO that must land inside the Lock Detect Window to declare LOCK 0 5 1 32 2 96 3 256 4 512 5 2048 6 8192 7 65535 10 3 R W Reserved Reserved m R W LD Enable 0 LD disable 1 LD
65. line at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 50 Auxiliary LO Output pias hie areas A LO a m Fractional Mode Closed Loop Phase Noise pen Coop T nase Ose a Z at 3600 MHz with various divider ratios 40 80 a gt 100 20 fea fea iz 100 i120 S 8 fe g1 1140 140 f E 160 160 180 480 E 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 OFFSET KHz OFFSET KHz Div1 Div8 Div62 Div2 Div16 Div4 Div32 Figure 52 Auxiliary LO Output Figure 51 Auxiliary LO Output Fractional Mode Closed Loop Phase Noise Open Loop Phase Noise at 4100 MHz at 4100 MHz with various divider ratios 80 z 100 e 3 a Saz Poo vad PHASE NOISE dBc Hz PHASE NOISE E t Q f ie it 180 E 4 os i e 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 OFFSET KHz OFFSET KHz Div1 Div8 Div62 Div2 Div16 Div4 Div32 Figure 53 Auxiliary LO Output Fractional Mode Closed Loop Phase Noise at 3300 MHz with various divider ratios 7 80 7 e ae an mee ae a PHASE NOISE dBc H E 3 160 180 i i i ate mmni 1 10 100 1000 10000 100000 OFFSET KHz Div1 Div8 Div62 Div2 Div16 Div4 Div32 1 Using 122 88 MHz clock input 61 44
66. measured conversion gain and IIP3 for four values of VGATE1 VGATE2 pin voltages Conversion Gain vs VGATE Input IP3 vs VGATE 31 29 c 27 z 3 25 z2 oO D O 23 D oO A a w 21 gt 6 ta 19 17 15 i 0 5 1 5 2 25 3 3 5 4 0 5 1 1 5 2 2 5 3 3 5 4 FREQUENCY GHz FREQUENCY GHz 4 8V 4 9V 4 8V 4 9V 5V 5V Figure 74 Conversion Gain amp IIP3 vs RF Frequency over VGATE Pin Voltage at 25C IF 150 MHz After the VGATE voltage is tuned for optimized IIP3 and conversion gain performance the VGATE pin voltage can be generated from 5V supply voltage by changing the value of series resistors R54 and R56 from 0 Ohm to an appropriate value Table 16 shows the typical resistor values that need to be added in series with VGATE1 VGATE2 pins for different VGATE voltages A fine tune for R54 and R56 resistors can be used if a better fit is required Table 16 Resistor values for Different VGATE Pin Voltages 4 8 V 120 Ohms 3 4 VCS Interface and LOBIAS Interface VCS1 VCS2 pins are bias pins for IF amplifiers on each channel and set the reference currents to these IF amplifiers The VCS voltage is generated from the 5V supply by series resistors Higher IIP3 values can be obtained by changing the values of these series resistors R61 and R73 which will change the total supply current of the IF amplifiers which can be seen on Table 17 LOBIAS1 LOBIAS2 pins are bias pins
67. nly available on LO_N pin Enables Single Ended output mode for LO2 output J 1 Single ended mode LO2_N pin is enabled and LO2_P pin is 9 R W Eog S ened 1 0 disabled 0 Differential mode both LO2_N and LO2_P pins enabled Please note that single ended output is only available on LO2_N pin 10 R W Reserved 1 0 Reserved Connects CP to CP1 or CP2 output 11 R W Charge Pump Output Select 1 0 0 CP1 1 CP2 23 12 R W Reserved 12 0 Reserved 21697d 18 0 R W Reserved 19 54C1h Reserved External Input buffer BIAS 19 R W External Input buffer BIAS bitO bito External Input buffer BIAS 20 R W External Input buffer BIAS bit1 bit1 23 21 R W Reserved Reserved 2 25 Reg 19h Cals Register Default AAA h 2730d Reserved 2 AAA Reserved Program to AB2h For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 2 26 Reg 1Ah Seed Register Default B29D0Bh Used to program output phase relative to the reference frequency Exact Frequency Mode required When not using Exact Frequency Delta Sigma Modulator 11705611d Mode and Auto seed Enable Reg 06h 8 1 Reg 1Ah sets the s
68. od MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Figure 43 Conversion Gain vs IF Frequency Figure 44 IIP3 vs IF Frequency at RF 900 MHz VGATE 5V 1 at RF 900 MHz VGATE 5V 32 30 CONVERSION GAIN dB IIP3 dBm 50 100 150 200 50 100 150 200 FREQUENCY MHz FREQUENCY MHz 25C 85C 25C 40C 85C 40C Figure 45 Conversion Gain vs IF Frequency Figure 46 IIP3 vs IF Frequency at RF 1900 MHz VGATE 5V at RF 1900 MHz VGATE 5V 32 30 28 26 24 CONVERSION GAIN dB IIP3 dBm 50 100 150 200 50 100 150 200 FREQUENCY MHz FREQUENCY MHz 25C 850 40C 25C 85C Figure 47 Conversion Gain vs IF Frequency Figure 48 IP3 vs IF Frequency at RF 2400 MHz VGATE 5V at RF 2400 MHz VGATE 5V z 32 z 30 28 26 24 CONVERSION GAIN dB IIP3 dBm 50 100 150 200 50 100 150 200 FREQUENCY MHz FREQUENCY MHz 25C 85C 40C 25C 85C 1 Balun losses at IF output ports are de embedded For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order on
69. of the VCO Output frequencies ranging from 33 MHz to 2050 MHz are generated by tuning to the appropriate fundamental VCO frequency 2050 MHz to 4100 MHz by programming N divider Reg 03h For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz and Reg 04h and programming the output divider divide by 1 2 4 6 60 62 programmed in Reg 16h in the VCO register For detailed frequency tuning information and example please see Frequency Tuning section 1 2 1 Charge Pump CP amp Phase Detector PD The Phase detector PD has two inputs one from the reference path divider and one from the RF path divider When in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with respect to each other We refer to the frequency of operation of the PD as fpa Most formulae related to step size delta sigma modulation timers etc are functions of the operating frequency of the PD fog fpa is also referred to as the comparison frequency of the PD The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of th
70. patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period or at harmonic frequencies of fycok fvcork 1 For example in some applications these intervals might represent the spacing between radio channels and the spurious would occur at multiples of the channel spacing The Hittite method on the other hand is able to generate exact frequencies between adjacent integer N boundaries while still using the full 24 bit phase accumulator modulus thus achieving exact frequency steps with a high phase detector comparison rate which allows Hittite PLLs to maintain excellent phase noise and spurious performance in the Exact Frequency Mode 1 2 7 3 1Using Hittite Exact Frequency Mode If the constraint in EQ 16 is satisfied HMC1190ALP6NE is able to generate signals with zero frequency error at the desired VCO frequency Exact Frequency Mode may be re configured for each target frequency or be set up for a fixed fgcg which applies to all channels 1 2 7 3 2 Configuring Exact Frequency Mode For a Particular Frequency 1 Calculate and program the integer register setting Reg 03h Nz floor fyco fpp where the floor function is the rounding down to the nearest integer Then the integer boundary frequency fy Ninrt fPD 2 Calculate and program the exact frequency register value Reg OCh fpplfgca where fyca gcd fyco fPp 224 3 Calculate and program the fractional register setting Reg 04h Nerac oe
71. plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes All evaluation board related drawings are available under Evaluation Kits tab of product page www analog com HMC1190A Evaluation Order Information Evaluation PCB Only HMC1190ALP6NE Evaluation PCB EV1HMC1190ALP6N 1 HMC1190ALP6NE Evaluation PCB Evaluation Kit USB Interface Board EK1HMC1190ALP6N 2 6 USB A Male to USB B Female Cable 1 Reference this number when ordering Evaluation PCB Only 2 Reference this number when ordering an HMC1190ALP6NE Evaluation KIt For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 0 Theory of Operation The block diagram of HMC1190ALP6NE PLL with Integrated VCO is shown in Figure 66 EXT_VCO_P EXT_VCO_N VTUNE VCO CAL LOOP Bag Reg15h 09 FILTER VOLTAGE Reg17h 06 EN Single Ended EN Reg17h 08 l Reg17h 04 EN EN Regt 7h 11 LO_P cP1 ao N 1 PHASE DIVIDER o CHARGE FREQUENCY zE o DETECTOR a E 2 4 6 62 cP2 Reg17h 02 Reg16h 10 e LO_N Reg1
72. power dissipation of 2 34 W typical Fast enable control interface reduces power consumption further in TDD applications External VCO input allows the HMC1190ALP6NE to lock external VCOs and enables cascaded LO architectures for MIMO applications Two separate Charge Pump CP outputs enable separate loop filters optimized for both integrated and external VCOs and seamless switching between integrated or external VCOs during operation Programmable RF output phase features can further phase adjust and synchronize multiple HMC1190ALP6NE s enabling scalable MIMO and beam forming radio architectures Additional features include configurable LO output mute function Exact Frequency Mode that enables the HMC1190ALP6NE to generate fractional frequencies with O Hz frequency error and the ability to synchronously change frequencies without changing phase of the output signal that increases efficiency of digital pre distortion loops The HMC1190ALPE6NE is housed in RoHS compliant compact 6x6 mm leadless QFN package Information furnished by Analog Devices is believed to be accurate and reliable However no For price delivery and to place orders Analog Devices Inc responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other One Technology Way P O Box 9106 Norwood MA 02062 9106 rights of third parties that may result from its use Specifications subject to change without notice No Ph 781 329 4700 Ord
73. pplication Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz routine searches for the best step setting that locks the VCO at the current programmed frequency and ensures that the VCO will stay locked and perform well over it s full temperature range without additional calibration regardless of the temperature that the VCO was calibrated at Auto Calibration can also be disabled allowing manual VCO tuning Refer to section Manual VCO Calibra tion for Fast Frequency Hopping for a description of manual tuning 1 1 1 1 1 Auto reLock on Lock Detect Failure It is possible by setting Reg OAh 17 to have the VCO subsystem automatically re run the calibration routine and re lock itself if Lock Detect indicates an unlocked condition for any reason With this option the system will attempt to re Lock only once 1 1 1 1 2 VCO AutoCal on Frequency Change Assuming Reg OAh 11 0 the VCO calibration starts automatically whenever a frequency change is requested If it is desired to rerun the AutoCal routine for any reason at the same frequency simply rewrite the frequency change with the same value and the AutoCal routine will execute again without changing final frequency 1 1 1 1 3 VCO AutoCal Time amp Accuracy The VCO frequency is counted for Tian the period of a single AutoCal measurement cycle Tor Trai RaR EQ 1 n is
74. quency Integer Mode DC 100 MHz fo Mode at 4000 MHz 2nd 3rd 4th 30 22 32 dBc VCO RF Divider Range 1 2 4 6 8 62 1 62 19 Bit N Divider Range Integer Max 2 1 16 524 287 19 Bit N Divider Range Fractional hans Ja EEE aera 20 524 283 Max Ref Input Frequency 350 MHz Ref Input Voltage AC Coupled 1 2 3 3 Vpp Ref Input Capacitance 5 pF 14 Bit R Divider Range 1 16 383 vco Open Loop Phase Noise atto 46Hz O S O 10 kHz Offset 78 dBc Hz 100 kHz Offset 108 dBc Hz 1 MHz Offset 134 5 dBc Hz 10 MHz Offset 156 dBc Hz 100 MHz Offset 167 dBc Hz For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Table 3 PLL amp VCO Specifications Continued 10 kHz Offset 83 dBc Hz 100 kHz Offset 113 dBc Hz 1 MHz Offset 139 5 dBc Hz 10 MHz Offset 165 5 dBc Hz 100 MHz Offset 167 dBc Hz Figure of Ment Floor Integer Mode Normalized to 1 Hz 230 dBc Hz Floor Fractional Mode Normalized to 1 Hz 227 dBc Hz Flicker Both Modes Normalized to 1 Hz 268 dBc Hz vco Characteristics O O VCO Tuning Sensitivity
75. r the lock detect window for a given operating point The user should understand however that one solution does not fit all operating points As observed from EQ 11 If charge For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz pump offset or PD frequency are changed significantly then the lock detect window may need to be adjusted 1 2 5 Configuring LD_SDO Pin for LD Output Setting Reg OFh 4 0 7 will display the Lock Detect Flag on LD_SDO pin of the HMC1190ALP6NE If locked LD_SDO will be high As the name suggests LD_SDO pin is multiplexed between LD and SDO Serial Data Out signals Hence LD is available on the LD_SDO pin at all times except when a serial port read is requested in which case the pin reverts temporarily to the Serial Data Out pin and returns to the Lock Detect Flag after the read is completed LD can be made available on LD_SDO pin at all times by writing Reg OFh 6 1 In that case the HMC1190ALP6NE will not provide any read back functionality because the SDO signal is not available 1 2 6 Cycle Slip Prevention CSP When changing VCO frequency and the VCO is not yet locked to the reference the instantaneous frequenc
76. re used on the SDO line 8 R W Disable PFET 9 Prevents conflicts on the SPI bus Program to 1 if external pull downs are used on the SDO line 9 RAN Digable NEET v Prevents conflicts on the SPI bus 23 10 R W Reserved 14 0 Reserved VCO selection resulting from AutoCalibration 7 0 R VCO Tune Curve 8 0 maximum frequency 16d 10h 1111 1111 b minimum frequency Indicates if the VCO tuning is in process 8 R VCO Tuning Busy 1 0 1 Busy 0 Not Busy For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 2 17 Reg 11h SAR Register Read Only 219 4d 18 0 R SAR Error Magnitude Count 19 7FEFFh SAR Error Magnitude Count SAR Error Sign 19 R SAR Error Sign 1 0 0 positive 1 negative 23 20 R Reserved 4 0 Reserved 2 18 Reg 12h GPOILD Register Read Only 0 R GPO Out 1 0 GPO Output 1 R Lock Detect Out 1 0 Lock Detect Output 23 2 R Reserved 22 7h Reserved 2 19 Reg 13h BIST Register Read Only j 4697d 16 0 R Reserved 16 1259h Reserved For price delivery and to place orders Analog Dev
77. rential LO output vest a gt Y 73 VCS2 Exact Frequency Mode IIN oo li L2 IF2N 0 Hz Fractional Frequency Error IFiP TO Co IF2P Programmable RF Output Phase AS PPeseeAeeR Output Phase Synchronous Frequency Changes 2r A Se ee a ey e Output Phase Synchronization i 226 2 amp 5 4 LO Output Mute Function gt 9 73 e Compact Solution 6x6 mm Leadless QFN Package General Description The HMC1190ALP6NE is a high linearity broadband dual channel downconverting mixer with integrated PLL and VCO optimized for multi standard receiver applications that require a compact low power design Integrated wideband limiting LO amplifiers enable the HMC1190ALP6NE to achieve an unprecedented RF bandwidth of 700 MHz to 3800 MHz for applications including Cellular 3G LTE WiMAX 4G Unlike conventional narrow band downconverters the HMC1190ALP6NE supports both high side and low side LO injection over all RF frequencies The RF and LO input ports are internally matched to 50 Ohms The HMC1190ALP6NE features an integrated LO and RF baluns enable control of IF and LO amplifiers and bias control interface to high linearity passive mixer cores Balanced passive mixer combined with high linearity IF am plifier architecture provides excellent LO to RF LO to IF and RF to IF isolations Low noise figure of 9 dB and high IIP3 of 24 dBm allow the HMC1190ALPE6NE to be used in most demanding applications External bias control pins enable optimization of already low
78. s Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 2 11 Reg 09h Charge Pump Register DEFAULT 547264 h Charge Pump DN Gain Control 20 pAystep Affects fractional phase noise and lock detect settings toog C OHA 6 0 R W CP DN Gain 7 64h 1d 20 pA 2d 40 pA 127d 2 54mA Default 2mA Charge Pump UP Gain Control 20 pA per step Affects fractional phase noise and lock detect settings tood O OHA 13 7 R W CP UP Gain 7 64h 1d 20 pA 2d 40 pA 127d 2 54mA Default 2mA Charge Pump Offset Control 5 pA step Affects fractional phase noise and lock detect settings 0d 0 pA 20 14 R W Offset Magnitude 7 81d 1d 5 pA 2d 10 pA 127d 635 pA Default 405A 21 R W Offset UP enable 1 0 Sets Direction of Reg 09h 20 14 Up 0 UP Offset Off 22 R W Offset DN enable 1 1 Sets Direction of Reg 09h 20 14 Down 0 DN Offset Off Only recommended with external VCOs and Active Loop Filters When enabled the HMC1190ALP6NE increases CP current by 3 mA thereby improving phase noise perfor mance and increasing loop bandwidth 23 R W HiK charge pump Mode 1 0 For price delivery and to place orders Analog Devices Inc One Tec
79. s during VCO calibration Reg 17h 7 1 that occurs during output frequency changes This mode can be useful in eliminating any out of band emissions during freqeuncy changes and ensuring that the system emits only desired frequencies It is enabled by writing Reg 17h 7 1 Typical isolation when the HMC1190ALP6NE is muted is always better than 60 dB and is 30 dB better than disabling the output buffers of the HMC1190ALP6NE via Reg 17h 5 4 1 2 PLL Overview The PLL divides down the VCO output to the desired comparison frequency via the N divider integer value set in Reg 03h fractional value set in Reg 04h compares the divided VCO signal to the divided reference signal reference divider set in Reg 02h in the Phase Detector PD and drives the VCO tuning voltage via the Charge Pump CP configured in Reg 09h to the VCO subsystem Some of the additional PLL subsystem functions include Delta Sigma configuration Reg 06h Exact Frequency Mode Configured in Reg OCh Reg 06h Reg 03h and Reg 04h Lock Detect LD Configuration Reg 07h to configure LD and Reg OFh to configure LD_SDO output pin External CEN pin used as hardware enable pin Typically only writes to the divider registers integer part Reg 03h fractional part Reg 04h VCO Divide Ratio part Reg 04h are required for HMC1190ALP6NE output frequency changes Divider registers of the PLL Reg 03h and Reg 04h set the fundamental frequency 2050 MHz to 4100 MHz
80. set by Reg OAh 2 0 and results in measurement periods which are multiples of the PD period TxtaR R is the reference path division ratio currently in use Reg 02h Tytal is the period of the external reference crystal oscillator The VCO AutoCal counter will on average expect to register N counts rounded down floor to the nearest integer every PD cycle N is the ratio of the target VCO frequency fyco to the frequency of the PD fog where N can be any rational number supported by the N divider N is set by the integer Nin Reg 03h and fractional Njac Reg 04h register contents 24 N N n N rac 2 EQ 2 The AutoCal state machine runs at the rate of the FSM clock Tsm where the FSM clock frequency cannot be greater than 50 MHz m Tega Tse 2 EQ 3 m is 0 2 4 or 5 as determined by Reg OAh 14 13 The expected number of VCO counts V is given by V floor N 2 EQ 4 The nominal VCO frequency measured fycom is given by n ae V lat 2 R EQ 5 where the worst case measurement error ferr iS n 1 fn z tfa 2 EQ 6 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz Tpa Reg02 CALIBRATION WINDOW
81. set depending upon the mode of operation The input reference signal should be 10 dB better than this floor to avoid degradation of the PLL noise contribution It should be noted that such low levels are only necessary if the PLL is the dominant noise contributor and these levels are required for the system goals Reference Path R Divider The reference path R divider is based on a 14 bit counter and can divide input signals by values from 1 to 16 383 and is controlled via Reg 02h RF Path N Divider The main RF path divider is capable of average divide ratios between 219 5 524 283 and 20 in fractional mode and 219 1 524 287 to 16 in integer mode Lock Detect The Lock Detect LD function indicates that the HMC1190ALP6NE is indeed generating the desired frequency It is enabled by writing Reg O7h 11 1 The HMC1190ALP6NE provides LD indicator in one of two ways e As an output available on the LD_SDO pin of the HMC1190ALPE6NE Configuration is required to use the LD_SDO pin for LD purpose for more information please see Configuring LD_SDO Pin for LD Output section e Or reading from Reg 12h 1 where Reg 12h 1 1 indicates locked and Reg 12h 1 0 indicates an unlocked condition The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a user specified time period window repeatedly Either signal may arrive first only the difference in arrival times is signi
82. t chip address a2 a0 MSB first on the next 3 falling edges of SCLK 30 32 Hittite reserves chip address a2 a0 000 for HMC1190ALP6NE Slave shifts the chip address bits on the next 3 rising edges of SCLK 30 32 Master asserts SEN after the 32nd rising edge of SCLK Slave registers the SDI data on the rising edge of SEN Master clears SEN to complete the WRITE cycle For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 2 3 SCK ti i E SEN Figure 72 Serial Port Timing Diagram WRITE 1 7 2 Serial Port READ Operation A typical READ cycle is shown in Figure 73 In general the LD_SDO line is always active during the WRITE cycle During any SPI cycle LD_SDO will contain the data from the current address written in Reg OOh 4 0 If Reg OOh 4 0 is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in progress If it is desired to READ from a specific address it is necessary in the first SPI cycle to write the desired address to Reg OOh 4 0 then in the next SPI cycle the desired data will be available on LD_SDO An example of the two cycle procedure to read from any address follows
83. tart Seed B29D0Bh phase of output signal If AutoSeed disable Reg 06h 8 0 Reg 1Ah is the start phase of the signal after every frequency changel LO Phase 2m xReg 1Ah 224 R W For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 3 0 Application Information The HMC1190ALP6NE is a broadband dual channel high dynamic range high gain low noise high linearity down converting mixer with integrated Fractional N Integer N PLL and VCO designed to cover RF frequencies from 700 MHz to 3 8 GHz The HMC1190ALP6NE s low noise and high linearity performance makes it suitable for a wide range of transmission standards including TDD FDD LTE WiMAX CDMA GSM MC GSM W CDMA UMTS TD SCDMA applications The HMC1190ALP6NE offers an easy to use and complete frequency conversion solution for diversity and MIMO receiver applications in a highly compact 6x6 mm plastic QFN package The HMC1190ALP6NE greatly simplifies the design of diversity and MIMO receiver applications by increasing the integration level and reducing the number of required circuit elements thereby reducing cost area and power consumption 3 1 Prin
84. toniMade 1 o 0 VCO subsystem manual calibration disabled 5 1 Capacitor Switch Setting 5 16d capacitor switch settin 10h 9 8 6 Manual VCO Selection 3 2 selects the VCO core sub band 1 Manual VCO tuning enabled 8 Manyalo Tune Enabig o 0 Manual VCO tuning disabled 15 10 Reserved 6 T Reserved Enable Auto Scale CP 1 Automatically scale CP current based on VCO frequency and 16 einen 1 1 capacitor setting 0 Don t scale CP current 23 17 Reserved 7 7d Reserved For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 2 22 Reg 16h Gain Divider Register Default 6C1 h Default 0 Mute VCO and PLL buffer On RF output stages Off 1 Fo 2 Fo 2 3 invalid defaults to 2 4 Fo 2 p 5 invalid defaults to 4 5 0 R W RF Divide Ratio 6 1 6 Fo 6 60 Fo 60 61 invalid defaults to 60 62 Fo 62 gt 62 invalid defaults to 62 Max Gain Max Gain 3 dB Max Gain 6 dB Max Gain 9 dB LO Output Buffer Gain 7 6 RN Control Max Gain Max Gain 3 dB Max Gain 6 dB Max Gain 9 dB LO2 Output Buffer gain 9 8 R W Control Divider Output Stage Gain 1 Max Gain 1
85. ttled If the CP Offset current is enabled during a frequency change it may not lock For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 2 1 2 Phase Detector Functions 1 2 2 Phase detector register Reg OBh allows manual access to control special phase detector features Setting Reg OBh 5 0 masks the PD up output which prevents the charge pump from pumping up Setting Reg OBh 6 0 masks the PD down output which prevents the charge pump from pumping down Clearing both Reg OBh 5 and Reg OBh 6 tri states the charge pump while leaving all other functions operating internally PD Force UP Reg OBh 9 1 and PD Force DN Reg OBh 10 1 allows the charge pump to be forced up or down respectively This will force the VCO to the ends of the tuning range which can be useful in VCO testing Reference Input Stage RVDD AC couple e 1002 Figure 70 Reference Path Input Stage The reference buffer provides the path from an external reference source generally crystal based to the R divider and eventually to the phase detector The buffer has two modes of operation controlled by Reg 08h 21 High Gain Reg O8h 21 0 r
86. unction without SEN Hoewer SEN rising edge is required to return the LD_SDO to the GPO state Figure 73 Serial Port Timing Diagram READ For more information on using the GPO pin while in SPI Mode please see section General Purpose Output GPO Pin For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 2 0 PLL Register Map 2 1 aeg 00h ID ie Read seid DEFAULT C7701A h 4 0 WO Read Address 5 WRITE ONLY Read Address for next cycle 5 WO Soft Reset 1 WRITE ONLY Soft Reset set to 0 during operation 23 6 WO Not Defined 18 Not Defined set to write Oh 2 3 Reg 01h Chip Enable Register DEFAULT 3h 1 Chip enable via CHIP_EN pin Reg 01h 0 1 and CHIP_EN pin low places the HMC1190ALP6NE in Power Down Mode 0 R W Chip Enable Pin Select 1 1 0 Chip enable via SPI Reg 01h 0 0 CHIP_EN pin ignored see Power Down Mode description for more details Controls Chip Enable Power Down if Reg 01h 0 0 Reg 01h 0 0 and Reg 01h 1 1 chip is enabled CHIP_ F EN pin don t care m WS SPLGRIp Enable 1 Reg o1h o 0 and Reg Oth 1 0 chip disabled CHIP
87. utput then measures the free running VCO frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase locked frequency This procedure results in a phase locked oscillator that locks over a narrow voltage range on the varactor A typical tuning curve for a step tuned VCO is shown in Figure 67 Note how the tuning voltage stays in a narrow range over a wide range of output frequencies such as fast frequency hopping TUNE VOLTAGE AFTER CALIBRATION V OUR ee ee eee oye 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300 VCO FREQUENCY MHz Calibrated at 85C Measured at 85C Calibrated at 85C Measured at 40C Calibrated at 40C Measured at 40C Calibrated at 40C Measured at 85C Calibrated at 27C Measured at 27C Figure 67 Typical VCO Tuning Voltage After Calibration The calibration is normally run automatically once for every change of frequency This ensures optimum selection of VCO switch settings vs time and temperature The user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the AutoCal routine The accuracy required in the calibration affects the amount of time required to tune the VCO The calibration For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com A
88. ux of SDO Reg OFh 6 1 The phase noise performance at this output is poor and uncharacterized The GPO output should not be toggling during normal operation because it may degrade the spectral performance Note that there are additional controls available which may be helpful if sharing the bus with other devices e To disable the driver completely set Reg O8h 5 0 it takes precedence over all else e To disable either the pull up or pull down sections of the driver Reg OFh 8 1 or Reg OFh 9 1 respectively Example Scenarios e Drive SDO during reads tri state otherwise to allow bus sharing e No action required e Drive SDO during reads Lock Detect otherwise e Set GPO Select Reg OFh 4 0 00001 b which is default e Set Prevent GPO driver disable Reg OFh 7 1 e Always drive Lock Detect e Set Prevent AutoMux of SDO Reg OFh 6 1 e Set GPO Select Reg OFh 4 0 00001 which is default e Set Prevent GPO driver disable Reg OFh 7 1 The signals available on the GPO are selected in Reg OFh 4 0 For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz 1 6 Chip Identification The chip
89. y fyco in the following manner 274 cox fy top the smallest channel VCO frequency that is greater than fy Reg04h Nerac ceil wherefy floor fyco fpp andfyco7 as shownin Figure 71 represents Example To configure the HMC1190ALP6NE for Exact Frequency Mode for equally spaced intervals of 100 kHz where first channel Channel 1 fyco 2800 200 MHz and Phase Detector PD rate fpp 61 44 MHz proceed as follows First check that the exact frequency mode for this fy co 2800 2 MHz Channel 1 and fyco2 2800 2 MHz 100 kHz 2800 3 MHz Channel 2 is possible f f fjod1 9CU fycorfpp and fyoq4 2 2g Jana fyca2 9CA fyco2 pp and fjog2 2 42 61 44x108 frat ged 2800 2 10 61 44108 120x108 gt 9750 6 fyca2 9ed 2800 3x108 61 44x 10 20x10 SA 3750 If EQ 16 is satisfied for at least two of the equally spaced interval channel frequencies fyco1fvcozfvcos For price delivery and to place orders Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 Phone 781 329 4700 Order online at www analog com Application Support Phone 1 800 ANALOG D ANALOG DEVICES HMC1190ALP6NE v00 1115 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w Fractional N PLL amp VCO 0 7 3 8 GHz fvcon as it is above Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies and can be configured as follows f 2800 2x10 g floor YE floor 45d

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