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SIS3350 500 MHz 12-bit VME Digitizer User Manual

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1. pages PA A ae age register bit oOo O J ogeregtter bn Example readout routine for 128MSample readout see CVI sis3350_configuration_readout_lib c int sis3350_DMA Read MBLT64 ADC DataBuffer unsigned int module_address VME Base address unsigned int adc_channel Pe NO Seat c Bey unsigned int adc_buffer_sample_start_addr 16 bit word start address unsigned int adc buffer sample length 16 bit word sample length unsigned int dma got no of words read length of 32 bit words unsigned int uint adc buffer read buffer pointer Page 33 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME a ADC Memory Sample Address table Samples Bytes Sample Page register VME Offset Address Address 0 0x2 8 MSample 1 16 MByte 2 0x007F FFFF 0 0x00FF FFFE 8 MSample 16 MByte 0x0080 0000 1 0x0 8 MSample 8 16 MByte 0x10 0x0080 0008 1 0x10 O 0X00 FF FFFE 16 MSample 32 MByte 0x0100 0000 2 0x0 as A eee A es LS A A A AAA AAA A GE A A MN A O ES A A es gg A A ET E IR AS 120 MSample 240 MByte 0x0780 0000 15 0x0 128 MSample 1 256 MByte 2 OxO7FF FFFF 15 OxOOFF FFFE Page 34 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 15 Trigger Output Select register 0x38 define S183350 LEMO OUTPUT SELECT REGISTER 03x38 fe read write D32 This register 1s used to program on
2. tine stamp time stamp event info 4x621162398 Hxhief leh 8x22 760158 xO 7c BAT EN 46755 ix 7038882 AxB26fB2cd x61 f 461F 4 Tz event info 4 AxA2070226 HxBlfFABLES EN 758287 BxH d6BH7a7 o f2 ENG CTIE ei EN KRETZ RAT BWBxHifzHifh long words x61 fF 96264 EN NR ORT 8x83 beb2d1 BxBVF ER eb A PA PES 6x66 Ze 0746 6x82146234 Bx f da1if 8x61 f ab2 68 HxAilechiec ENEE LEET GES DISK d BHABHAE CHAT O HWHxH5 Bf B6 de 4x62 Hah223 BxHifiBHif4 word i 6x8HBHHS5F gt word 2 amp x8986H4a2 gt 5451515 515 15 4400001 A gt Bav CHIC 4 x81ie1Bied 6x85 aa64h BxB FB GES DIS LZ d d AxbicabSaa x61 f aBz2im3 AxBilehBied Ix Ff 461F5 Bachelet BB 266546 SENG d af h AxA eB As 404550534 HxBif 9Hife HxHief if Hx edili fH HxH1eb5liie4d 8x67 Balb 75 HxbVef Arf 64308308087 Hxi34dB83f a ixi fn 9 Hxiie3BH1e7 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 9 Appendix 9 1 Power consumption The SIS3350 uses standard VME voltages only 9 2 Operating conditions 9 2 1 Cooling Although the 8183350 is mainly a 2 5 and 3 3 V low power design substantial power is consumed by the Analog to Digital converter chips and linear regulators however Hence forced air flow is required for the operation of the board The board may be operated in a non condensing environment at an ambient temperature between 10 and 25 Celsius A power up warm up time of some 10 minutes is
3. 16 K Samples FPGA 128 M Samples Ring Buffer Block Memory DDR2 Memory not user accessible user VME accessible Event N Next Event bh Acquisition Note please refer to the PDF in case of black print Page 9 of 79 SIS Documentation SIS3350 SS Gub A 500 MHz 12 bit Digitizer VME a 2 3 Modes of Operation The implemented modes of operation of this generic SIS3350 firmware implementation are listed in this section The FPGA based design of the card allows to meet the requirements of many readout applications with dedicated firmware designs in the future 6 modes of operation are implemented e Ring buffer asynchronous Ring buffer synchronous Direct memory gate asynchronous Direct memory gate synchronous Direct memory stop Direct memory start Note the individual channels acquire data asynchronously in the two asynchronous modes of operation This implies that the user will want to use the address counter and or the address threshold to decide on which channel s has have to be read out 2 3 1 Ring buffer asynchronous Mode Trigger sources internal Threshold Trigger each channel individual internal FIR Trigger Trigger each channel individual no external Trigger no Trigger delay Used Parameters programmable Ringbuffer PRE length up to 16380 in steps of 2 samples programmable Ringbuffer Sample length up to 16384 in steps of 8 samples End of acquisition condition Address Th
4. GI Kli ELSE RE uH Ic at ab ob StS ADCHPIR 6 1 2 Trigger Gate Lemo output The trigger gate output is a LEMO00 connector CON70A with NIM logic level Page 62 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 6 1 3 Clock BNC input The clock input is a BNC connector CON30A with programmable threshold level The programmable threshold level range is from 2 75V to 4 0V and the input impedance is 50 Ohm ANALG CLK IN tg LC Un DA PIERA Bh CONNECT E TO EHD Rife i HELETAN d CER dE Td RUSCH VERI la POH pap DWET GD pos VIT AHALCK CLE 1 3 F VIT ANALOG CLE 35 KRISE 1IISE RI REISER PS la i k Page 63 of 79 SIS Documentation SIS3350 SIS GmbH d 500 MHz 12 bit Digitizer VME 6 1 4 Clock BNC output The clock output signal is available on a BNC connector for diagnosis purposes The output level in DC coupling mode is 300mVpp and the offset is DC 1 1V into 50 Ohm termination The output level in AC coupling mode is 560mVpp without an offset into 50 Ohm termination CONNECTOR TYCO oi 4 EE Mira FERRIT YOU DM L700B Log Y Y IDGND DGND E 18V l fmF C700C mam ZO LOQUnF l 18V DEND Det DAD DGND Quallt t MIttelw Min Max Std abw P diedrige Aufl sung Qualit t Mittelw Min EN Std abw 1 00ns E H Niedrige Aufl sung 110k Pkte foe 5e DC coupling mode AC coupling mode R700G stuffed with 50 Ohm resistor
5. read write D32 EME IAS lt DAC Read Write Clear Cycle BUSY None A EA IN 7 Nos A J 6 om JN EA EP PO AE J 0 09 s 0 DAC Command BitO DACCommandBitOStatus DAC Selection Bit 0 ADC 1 3 respective ADC 2 4 respective Page 54 of 79 SIS Documentation SIS3350 SIS GmbH 4 35 2 ADC DAC Data registers 0x0x2000054 0x0x3000054 read write define S1532950 ADCIZ DAC DATA 0x02000054 read write D32 define 193350 ADCOS4 DAC DATA 0x03000054 read write D32 These registers are used to hold the data send the offset DACs of the 4 ADC channels The DAC is selected via the DAC Selection Bit in the ADC DAC Control registers DAC Input Register Bit 15 from DAC DAC Input Register Bit 0 DAC Output Register Bit 15 DAC Output Register Bit 15 0 DAC Output Register Bit O DAC Output Register Bit O Page 55 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 4 35 3 ADC Sample Counter TN setup register 0x2000070 0x2000074 0x20000078 0x200007C 0x3000070 0x3000074 0x30000078 0x300007C read write define SIS3350 SAMPLE COUNTER THRESHOLD T2T1_ADC1 0x02000070 define SIS3350_ SAMPLE COUNTER THRESHOLD T4T3 ADCI 0x02000074 define SIS3350_ SAMPLE COUNTER THRESHOLD T2T1_ADC2 0x02000078 define SIS3350 SAMPLE COUNTER THRESHOLD T4T3 ADC2 0x0200007C define SIS3350 SAMPLE COUNTER THRESHOLD T2T1_ADC3 0x03000070 defin
6. AAA Ei 2 2 2 Memory philosophy The DDR2 memory of the SIS3350 is controlled by the sample start address during acquisition The default memory of 128 MSamples channel is divided into 16 pages of 16 MByte each The memory page register defines which page can be accessed over the VME bus Full memory is accessible during acquisition however with the option to restrict the use to part of the memory or to divide the memory into smaller events Acquisition to memory controlled by Sample start address Readout from memory controlled by ADC memory page register VME address offset Page 8 of 79 SIS Documentation SIS3350 e See 500 MHz 12 bit Digitizer VME o 2 2 3 Internal memory handling The stream of digitized data from the ADC chips is always recorded to the block memory of the FPGA chips This mechanism facilitates DDR2 memory refresh handling and the implementation of parallel acquisition and readout We distinguish two basic memory modes e Ring buffer acquisition e Direct memory acquisition Ring buffer acquisition is limited to events that fit completely into the 16K block memory and the complete event is transferred to DDR2 memory upon completion In direct memory acquisition blocks of data are streamed to DDR2 memory during acquisition This internal memory handling implementation enables on board data rearrangement prior to readout in all modes of operation except for Direct Memory Trigger Stop
7. DE TS 73 0227 ele GE Ee EE 73 9 3 Co EE 74 OA sP2TOW AIC ENEE NMEN EE 74 Gov ROWwd andz Pin ASST ONIN E 75 A A dudo teteei dei undialaiuvutedet und eiue Pudet vafe tune ide tuse c Yuma id edicd s 76 9 6 1 Upcrdde yere EE 76 9 6 2 UPRUC gyer VB unitat oa 76 rO O DT Lo ee ES T1 Page 4 of 79 SIS Documentation SIS3350 SIS GmbH I 500 MHz 12 bit Digitizer VME 1 Introduction The 8183350 is the extension of our 12 bit digitizer family so far consisting of the 100 MHz SIS3300 and the 250 MHz SIS3320 250 towards higher sampling speed and deeper memory The unit has 4 digitizer channels sampling at up to 500 MSamples s each and a default memory depth of 128 MSamples per channel i e acquisition of 4 s at full sampling rate The use of 512 MSamples per channel allowing for 1s acquisition at full sampling speed is prepared also An offset DAC per channel in combination with a variable gain amplifier VGA gives you oscilloscope like input stage behaviour in combination with superior resolution The module was designed in a fashion that it can be operated in any 6U standard VME enclosure crate i e no non standard voltages going beyond 5 12V and 12 V are required The card is a single slot 4TE design which is available with standard and VME64x lever handles Besides VME bus readout functionality a 4 GBit optical link and a 10 100 1000 raw Ethernet are available as data transfer options with given interest in the corresponding firmware
8. Digitizer VME 4 19 Key address general reset 0x400 write only define S1S3350 KEY RESET 0x400 E EE Onis Dos Ey A write with arbitrary data to this register key address resets the SIS3350 to it s power up state 4 20 Key address VME arm sampling logic 0x410 write only define SIS3350 KEY ARM 0x410 fU write only D32 X A write with arbitrary data to this register key address will arm the sampling logic 4 21 Key address VME disarm sampling logic 0x414 write only define SIS3350 KEY DISARM 0x414 write only D32 7 A write with arbitrary data to this register key address will disarm the sampling logic 4 22 Key address VME Trigger define SIS3350 KEY TRIGGER 0x418 PE a rpe onlays DSZ EE A write with arbitrary data to this register key address will generate an trigger 4 23 Key address VME Timestamp Clear define SIS3350 KEY TIMESTAMP CLEAR 0x41C write only D32 A write with arbitrary data to this register key address will clear the 48 bit timestamp counter Page 42 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME i 4 24 Event configuration registers 0x01000000 0x02000000 0x03000000 read write define SIS3350 EVENT CONFIG ALL ADC 0x01000000 write only D32 define SIS3350 EVENT CONFIG ADC12 0x02000000 read write D32 define SIS3350 EVENT CONFIG ADC34 0x03000000 read write D32 This register is implemented for each channel group and it has to be
9. E x F 22 Boundary Scan 33 Slave Serial Sal Select MAP Ga Desktop Configur Wo ag Direct SPI Config CN Amm a xcf32p iMPACT Modes Ad CG f IMPACT Processes x Short Chain 3 5 and 4 6 closed factory default JP101 In the Impact software you will see iMPACT C temp default ipf Boundary Scan Flows x al Boundary Scan A Gel Slave Serial el Select MAP P 22 Desktop Configur i See en yl cn E IC xcf32p iMPACT Modes file LG d iMPACT Processes Xx f O Page 69 of 79 SIS Documentation SIS3350 SS Gub A 500 MHz 12 bit Digitizer VME 7 4 SW1 and SW2 VME base address These 2 rotary switches are used to define 2 nibbles of the VME base address in non geographical addressing refer to section base address also 7 5 JTAG source The JTAG chain can be connected to VME or to the JTAG connector CON100B The source is programmable via the XILINX JTAG Control register Page 70 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME 8 Getting started The directory SIS3350 software of the Struck Innovative Systeme DVD holds example code for VisualC and National Instruments Labwindows CVI The source code can be used as a base for ports to other environments The SIS3350 h header file can be found in the directory SIS3350 software The routine ConfigurationSetup_SIS3350_A
10. Page 49 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 32 Threshold registers 0x02000034 0x0200003C 0x03000034 0x0300003C define SIS3350_TRIGGER_THRESHOLD_ADC1 0x02000034 define S183350 TRIGGER THRESHOLD ADC2 0x0200003C define S183350 TRIGGER THRESHOLD ADC3 0x03000034 define S183350 TRIGGER THRESHOLD ADC 0x0300003C These read write registers hold the threshold values for the 4 ADC channels 4 32 1 Threshold Trigger default after Reset 0x0 A Trigger Output pulse is generated on two conditions e GT is set GT in trigger setup register the Trigger Out Pulse will be issued if the actual sampled ADC value goes above the threshold value e GT is cleared LT in trigger setup register the Trigger Out Pulse will be issued if the actual sampled ADC value goes below the threshold value GT greater than LT lower than Page 50 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME E 4 32 2 Threshold FIR Trigger default after Reset 0x0 The value of the Sum trapezoidal value depends on the peaking time P Therefore the selection of the value of the Trapezoidal threshold depends on P also Trapezoidal value calculation Trapezoidal value SUM2 SUMI Where x P SUMI Si LSx x P sumG SUM2 Sj j x sumG The FIR Filter logic generates the Trapezoidal by subtraction of the two running sums This implies that the internal value of the tra
11. VME64x Connectors VME64x Front panel VME64x extractor handles on request F1002 compatible P2 row A C assignment 5 V 12V and 12 V VME standard voltages Optical 4 Gigabit link connection Ethernet connection Note The SIS3350 shall not be operated on P2 row A C extensions like VSB e g due to the compatibility to the F1001 FADC modules clock and start stop distribution scheme The P2 row A C connections can be removed on request Page 6 of 79 SIS Documentation SIS3350 SIS GmbH J 500 MHz 12 bit Digitizer VME i 2 2 Module design The 8183350 consists of two identical groups of 2 ADC channels each and a control section as shown in the simplified block diagram below P m System Clock Front Panel VME Interface and Controlo Control FPGA 4 Clock Distribution Address Data VMEBus Dual Channel Group 2 Channels 3 and 4 Dual Channel Group 1 Channels 1 and 2 Page 7 of 79 SIS Documentation SIS3350 SIS GmbH I 500 MHz 12 bit Digitizer VME 2 2 1 Dual channel group Two ADC channels form a group which memory is handled by one Field Programmable Gate Array FPGA A dual channel group has block memory which resides in the FPGA and external DDR2 memory 128 MSamples channel default The block memory holds a ring buffer with a length of 16 K samples per channel FPGA
12. gedet 54 rn Sample doch oot od Lindos entes 42 ADC DAC control 54 55 disarm Ss amplno cick david eeh bech dd 42 ADC E E 55 general KT EE 42 ADC LTE 52 AMES CAT CICA EE 42 ADC memory p ge essere 33 57 TPIS St icici eee ii 42 ADC Sample Counter getup 56 AS eecht 17 32 ADC serial interface ccoocccconcncnonnnnonanonononos 4 IET E 66 broadcast setup esses 32 IM E pote 3 CBLT broadcast setup esee 31 LED Clock Trigger DAC control 36 A 66 Clock Trigger DAC control 36 EE 66 e EE 22 P 66 DAC EE 36 s Gl HC HH HH 67 EEN een EE 20 R 66 direct memory sample Jengath 27 E E 66 end address THES MONG WE 48 LR EE 66 event CONM CULATION s eode been 43 56 eet eebe 66 eu KE TOVIS OD AA 22 UT c 20 HEqueney Ss VILITIGSIZEE sorda 27 LEDs gate synch mode event extend length register 30 SEN A SS oan oaM tas 66 gate synch mode event length limit register 30 ls dee eebe 66 interrupt configuration esseesseesseesee 23 24 A 67 JTAG CONTROL cidos iapicaisds 39 live mserton cece cece cece ecececececececeecececececs 73 75 JTAG DATA IN 39 END SMP vents eege 65 JTAG CES EE 39 EVDS OUMU didas 65 A UNC ondes duc utin Defacto doni eds Enea 22 M 49 MultiEvent event counter cccceeeeeeeeeees 29 REI BK s rt nn EA E Mn E 6 19 MultiEvent max nof events 29 NS A ETE E E 6 8 19 57 ringbu
13. implementation The 4 GBit LC LC SFF small form factor link medium connection is foreseen to be used in combination with the SIS1100 eCMC PCI Express card Applications comprise but are not limited to e digitization of fast detector signals e accelerator machine controls m 69 MOE E Le As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals htm 1 1 Related documents A list of available firmware designs can be retrieved from http www struck de sis3350firm htm Page 5 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 2 Technical Properties Features 2 1 Key functionality Find below a list of key features of the SIS3350 digitizer 4 channels 12 bit resolution 128 MSamples channel memory special clock modes clock prescaling external arbitrary clock Variable gain amplifiers VGA offset DACs external internal clock external random clock multi event mode read on the fly actual sample value pre post trigger option readout in parallel to acquisition trigger generation FIR trigger 4 NIM control inputs 4 NIM control outputs A32 D32 BLT32 MBLT64 2eV ME Hot swap in conjunction with VME64x backplane
14. recommended to ensure equilibrium on board temperature conditions 9 2 2 Hot swap live insertion Please note that the VME standard does not support hot swap by default The SIS3350 1s configured for hot swap in conjunction with a VME64x backplane In non VME64x backplane environments the crate has to be powered down for module insertion and removal Page 73 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 9 3 Connector types The table below lists the connectors used on the SIS3350 9 4 P2 row A C pin assignments The P2 connector of the SIS3350 has several connections on rows A and C for the F1002 compatible use at the DESY H1 FNC subdetector This implies that the module can not be operated in a VME slot with a special A C backplane like VSB e g The pin assignments of P2 rows A C of the SIS3350 is shown below 5___ notconnected 5 not connected J 6 1 DGND 8 DGND P2 START H 9 P2 STARTL ln LD PP Note The P2 ECL signals are bussed and terminated on the backplane of F1002 crates The user has to insure proper termination if a cable backplane or add on backplane is used om a 9 P2 P2_ Page 74 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 9 5 Rowd and z Pin Assignments The SIS3350 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing and live insertion hot swap The prepa
15. the mode of operation Direct Memory Gate Synchronous Mode The maximum programmable limit length is 64M 8 The limit logic is disabled if the value is 0 BA GATE_LIMIT_LENGTH_BIT25 AS GATE_LIMIT_LENGTH _BIT3 Hog AAA UNML MENEENENEENEEMEEMEMMggSsSUIIWMMMHuB2B2BT The power up default value is 0 4 12 Gate Synch Mode Event Length Extend register 0x2C read write define SIS3350 GATE SYNCH EXTEND LENGTH Ox2C read write D32 This register defines the additional sample length to the the gate length in conjunction with the mode of operation Direct Memory Gate Synchronous Mode In combination with the ringbuffer Delay register it is possible program the PreGate and PostGate length The maximum programmable extend length is 248 BA uM A GATE_EXTEND_LENGTH_BIT7 Me Ci GATE EXTEND LENGTH BIT3 2 It 00 o The power up default value is 0 Page 30 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME a 4 13 CBLT Broadcast setup register define SIS3350_CBLT_BROADCAST_SETUP 0X30 read write D32 This read write register defines whether the SIS3350 will participate in a Broadcast The configuration of this register and the registers of other participating modules is essential for proper Broadcast behaviour 24 CBLT Broadcastaddressbit 24 AA AS AA EAT CN CA AA 16 AT Ss CAT 3 reserved o O PAT 11 freserved 0000000 HO Ju E NEN AAA 5 Enable Broadcast M
16. 4 Trigger Threshold register ADC3 Input Tap Delay register ADC4 Input Tap Delay register ADC3 VGA register A A 0x03000030 0x03000034 0x03000038 0x0300003C 0x03000040 0x03000044 0x03000048 0x0300004C 0x03000050 0x03000054 0x03000070 0x03000074 0x03000078 0x0300007C UI EE d n d kal ae d ADC memory pages 0x04000000 0x05000000 0x06000000 0x07000000 16 MByte 16 MByte 16 MByte 16 MByte Note 2 MBLT64 read access is supported from memory Le not from register space only Page 19 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 Register Description The function of the individual registers is described in detail in this section The first line after the subsection header in Courier font like define SIS3350 CONTROL STATUS 0x0 read write D32 refers to the SIS3350 h header file 4 1 Control Status Register 0x0 write read define SIS3350 CONTROL STATUS 0x0 read write D32 The control register is implemented as a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time The only function at this point in time is user LED on off On read access the same register represents the st
17. 5 counter information as illustrated below 31 16 15 0 0000 T1 counter 11 0 0000 T2 Counter 11 0 0000 T3 counter 11 0 0000 T4 Counter 11 0 0000 TS counter 11 0 0000 reserved 0000 reserved 0000 reserved Page 59 of 79 SIS Documentation SIS3350 SIS GmbH I 500 MHz 12 bit Digitizer VME 5 Board layout A printout of the silk screen of the component side of the PCB is shown below epp G 3 E Xm Tres CIE Aas L A EE nus L hore SES des Page 60 of 79 SIS Documentation SIS3350 SIS GmbH I 500 MHz 12 bit Digitizer VME 6 Front panel The SI53350 is a single width 4TE 6U VME module A sketch of the 5183350 front panel without handles 1s shown below e C o L3 i o CLK IN CLK OUT LINK e Trigger In programmable threshold 4 Trigger Out NIM d eg LUDS Let e OOC 3 o c Et N O C on N m I Page 61 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 6 1 Control In Outputs 6 1 1 Trigger Gate Lemo input The trigger gate input is a LEMOOO connector CON60A with programmable threshold level The programmable threshold level range is from 2 75V to 4 0V and an input impedance of 50 Ohm ARAL THIS IK TURRA 1 HINA LIND CH alian DTI E a I y a Sa Ein ESCH z100 d nk is pi mj 4 3 DAG DOME DEINDE WIT ARA TRO 3 TI ANALOG TH 3 B
18. 6 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME DAC Command Bit 0 O0 Nofunction 0 1 Load shift register of selected DAC 1 O0 Load selected DAC Clear all DACs A Clear DAC command sets the value of all DACs to analog ground 4 16 2 Clock Trigger DAC Data register 0x 54 read write define SIS3350 EXT CLOCK TRIGGER DAC DATA 0x54 read write D32 DAC Input Register Bit 15 from DAC DAC Input Register Bit 0 DAC Output Register Bit 15 DAC Output Register Bit 15 0 DAC Output Register Bit O DAC Output Register Bit O The table below lists a set of DAC values and their corresponding threshold voltage The table below lists a set of DAC values and their corresponding threshold voltage The maximum positive threshold value is 4 00V and the maximum negative threshold value is 2 75 V Clock and Trigger Input threshold setting table Threshold Voltage 23700 2 15 V 30000 836 mV Page 37 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 16 3 DAC load sequence The load sequence for the Analog Devices AD5570 DAC chip please refer to the documentation of the chip for more details is illustrated below The sequence is identical for trigger clock and ADC offset DACs 1 e the same component is used in all places Sequence to load offset of channel N N 0 1 Clock Trigger ADC offset 1 2 3 4 respective dacd
19. Addr sample stop address offset Information bit table Stop delay counter Trigger counter Extra Header words Trigger counter Counts the internal triggers Stop delay counter The Sample Stop Address stops on an 8 sample boundary With the help of the Stop delay counter multipy by 2 it is possible to rearange the trigger point see CVI s3183350 configuration readout lib c int rearange WrapRawDataOneChannelAllEvents Page 58 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME Wrap around bit This bit is cleared at start of sampling and it is set when the number of samples reached the value of the Sample Wrap Length register See also Direct Memory Stop Mode Sample Wrap Length register Wrap 0 data are only valid from offset 0 to Sample_Stop_Addr 2 no wrap event N stops at end of page Start 4 Stop d J Event N 1 Event N Event N 1 wrap event N started write pointer cycling within event Note wrap bit set when memory 5 M pointer reaches this point Event N 1 Event N Event N 1 wrap event N stopped stop pointer at arbitrary position within event i Stop a J Event N 1 Event N Event N 1 4 36 3 Extra Header An extra header consisting of four 32 bit words is generated with bit 0 of the event configuration register set to 1 The extra header holds the 12 bit wide T1 T
20. ER WEE 68 biu OK oer mh 69 Technical Properpes Features 6 eege ee 73 termination AM CETTE AAA DD T 15 geet 74 VME AG CTC SSI destin tere eMe teen isa tried 16 ECS re E 14 NW IVI E 5 A A E EE 39 68 NVME OF Xosa EE E E O E 10 trigger WAVES O A ona td ecos 75 A E A E E A 6 14 O 6 74 DO rr 14 EE 44 59 DIG sarin S 14 A E 59 tro Ver COMPO cursado doll iris 14 AILIN A S E 68 tto POT EH 14 Page 79 of 79
21. In combination with the Ringbuffer Delay register it 1s possible program the PreGate and PostGate length The maximum programmable sample length is 65328 64K 8 Bit o RINGBUFFER SAMPLE LENGTH BIT15 RINGBUFFER SAMPLE LENGTH BIT14 RINGBUFFER SAMPLE LENGTH BIT13 RINGBUFFER SAMPLE LENGTH BIT3 am R y The power up default value is 0 only in conjunction with the mode of operation Direct Memory Gate Asynchronous Mode Page 47 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 29 Ringbuffer Pre Delay register define SIS3350_RINGBUFFER_PRE_DELAY_ALL ADC 0x01000024 fdefine SIS3350 RINGBUFFER PRE DELAY ADC12 0x02000024 fdefine SIS3350_RINGBUFFER_PRE_DELAY_ADC34 0x03000024 This register defines the number of pre trigger delay samples in conjunction with all modes The maximum pretrigger delay is 16376 16K 8 Bit RINGBUFFER_PRETRIGGER_DELAY_BIT13 RINGBUFFER_PRETRIGGER_DELAY_BIT1 The power up default value is 0 4 30 End Address Threshold registers define 1 83350 END ADDRESS THRESHOLD ALL ADC 0x01000004 define 1 83350 END ADDRESS THRESHOLD ADC12 0x02000004 define 13 83350 END ADDRESS THRESHOLD ADC34 0x03000004 These registers define the End Address Threshold values for the ADC channel groups The value of the Actual Next Sample address counter will be compared with value of the End Address Threshold register The value is gi
22. R700G stuffed with 100 nF capacitor DC coupling is factory default Note the footprint of R700G is 0603 Page 64 of 79 SIS Documentation SIS3350 SIS GmbH d 500 MHz 12 bit Digitizer VME 6 1 5 LVDS in output The control I O section features one HDMI connector with LVDS levels EXTERN_CONTROLI_LVDS_INL 2 DOND S 3 EXTERN_CONTROLI_LVDS_IN 4 EXTERN_CONTROL2 LVDS INL DGND Trigger Gate Input 6 EXTERN CONTROL2 LVDS IN H Output Signal EXTERNAL CONTROLI LVDS OUT H 8 DGND Clock Output 19 EXTERNAL CONTROLI LVDS OUTL Trigger Gate Output 13 AAN ES A NN EXTERNAL_CONTROL3_LVDS_OUT_H BUSY Output EXTERNAL CONTROL3 LVDS OUT L EXTERN CONTROL LVDS INL EXTERN CONTROL LVDS IN H EXTERN CONTROL LVDS IN L EXTERN CONTROL LVDS IN H EXTERNAL CONTROL LVDS OUT H EXTERNAL CONTROL LVDS OUT L EXTERNAL CONTROL LVDS OUT H EXTERNAL CONTROL LVDS OUT L EXTERNAL CONTROL3 LVDS OUT H EXTERNAL CONTROL3 LVDS OUT L HDMI 19 02 S SMR DGND Page 63 of 79 SIS Documentation SIS3350 SS Gub A 500 MHz 12 bit Digitizer VME 6 2 LED s The SIS3350 has 6 front panel LEDs to visualise part of the modules status The access LED is a good way to check first time communication addressing with the module a E Access to SIS3350 VME slave port Power Green Read on board logis configured Red u2 Sample Logie Busy eener The on duration of the access sample logic armed and sample
23. SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 351353350 500 MHz 12 bit VME Digitizer User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version sis3350 M 0101 1 v102 as of 28 01 2009 Page 1 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME Revision Table 0 06 26 11 07 Temporaryrelease oo 1 02 28 01 09 N Divider frequency range setting table ADC DAC Data register explanation Page 2 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME Table of contents s e M T T RC 3 E INICIO 5 1 1 tee eege 5 2 Ke Te E ENT 6 2 1 Key TUTIC EOD alaridos leas 6 242 Module Eege eeh egene E E E Poder hurt 7 2 241 Dual channel EE 8 2 2 2 Memory patos Opinas 8 22 3 Internal memory Dandini litio 9 2 9 Modes KIEREN 10 2 3 1 Ring buffer asynchronous Mode 10 21 Ring buffer synchronous Mode erii eee peo sone b modestes Uu vae dh 11 23 3 Direct Memory Gate asynchronous Mode 11 2 3 4 Direct Memory Gate synchronous Mode 12 2 3 9 Direct Memory Stop Mode ot o 13 2 3 6 Direct Memory Start Modern eoe t ot a E EEE 13 255 MER A E 14 2 4 1 Internal EE 14 2 4 2 External clock BNC analog or ND 14 2 5 Trigger control pre post start stop and gate mode 14 2 0 ternal ne oero CNET A OM tedio a 14 2 4 NME In
24. X Sample Start Address Register Bit 26 HEN D unused o O The power up default value is 0 Explanation sample start address The contents of the start sample register is assigned as memory data storage address with the arm command key address arm sampling Page 45 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 27 ADC Next Sample address register define SIS3350_ACTUAL_SAMPLE_ADDRESS_ADC1 0x02000010 fdefine SIS3350_ACTUAL SAMPLE ADDRESS ADC2 0x02000014 fdefine 1 83350 ACTUAL SAMPLE ADDRESS ADC3 0x03000010 define SIS3350_ACTUAL_SAMPLE_ADDRESS_ADC4 0x03000014 These 4 read only registers hold the next sampling address for the given channel Sample Address Bit 26 PA A d O O oO O OSOS The power up default value is 0 Page 46 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 28 Ringbuffer Sample Length register define 1 83350 RINGBUFFER SAMPLE LENGTH ALL ADC 0x0 1000020 define SIS3350_RINGBUFFER_SAMPLE_LENGTH_ADC12 0x02000020 define 1383350 RINGBUFFER SAMPLE LENGTH ADC34 0x03000020 This register defines the number of samples in conjunction with the modes of operation Ringbuffer Asynchronous Mode and Ringbuffer Synchronous Mode The maximum programmable sample length is 16376 16K 8 It defines also the additional sample length to the the gate length in conjunction with the mode of operation Direct Memory Gate Asynchronous Mode
25. __________ Status enable source 1 read as 1 if enabled 0 if disabled 0 0 Enable IRQ source O Status enable source O read as 1 if enabled 0 if disabled Ju The power up default value reads 0x 00000000 IRQ source 3 reached Address Threshold level sensitive IRQ source 2 reached Address Threshold edge sensitive IRQ source 1 end of last event disarm IRQ source 0 end of event Page 24 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 5 Acquisition control register 0x10 read write define SIS3350 ACQUISTION CONTROL 0x10 read write D32 The acquisition control register is in charge of most of the settings related to the actual configuration of the digitization process Like the control register it is implemented in a J K fashion 31 Clear reserved IS YA 30 Clear reserved MESA 29 Clear Clock Source Bits 28 Clear Clock Source Dm 27 Clear reserved Il 26 Clear reserve MOE A 25 Clear external LVDS TRG IN as Gate Trigger 1 24 Disable external Lemo TRG IN as Gate Trigger JO S EME 22 Disable internal trigger as Gate Trigger OT 21 Disable Multi Event mode 0 20 Clear reserved4 AO 18 Clear Operation Mode Bit2 9 Enable external LVDS TRG IN as Gate Trigger Status reserved9 8 Enable external Lemo TRG INasGate Trigger Status veel Enable internal channel triggers as Gate Trigger Status enable in
26. arceat 71 CLOCK OUEDUL E 64 IUE Mc 68 eet 14 25 26 CN EE 74 Clock Trigger DAC dat 37 CIR EE 14 65 SEI DE AE 76 Die AG EE 59 CONTOOB sedet intet rere dott tastes ean eer 68 A E 73 75 CONMOUPALION sieke isl its ott 68 A EE 68 76 CONNECT OL assiduo basics Dea tais eben b h 6 input Con tector TYPES eeh be bbc l didus tas ee 74 Ee a II 63 65 control A O A esoe 62 A RW ET TRIN 14 Eege eendeitege bacino 62 OUDUE 1516s iiec O O diano ee 62 AA bedeutend bande cinta 65 SEIN E E 62 EEE AEE E E EE 62 SIE KE 73 ITO PEE S ALC E 65 counter Typ TAINO Goo asc eebe be dnte 53 SEOD Ce Iason osi eti Dados dlls 58 I terna eto 8 ET oo sebo dde bas dva nens 25 A 58 HEET a 23 COU E 56 MEUPE PE siciliana 23 Vui HH mH 5 eege Te 5 E WEEN 71 Invert Bit for external Lemo TRG IN 20 21 pom 6 IRQ p pc 5 6 bank tall ui 24 A e 54 End Address Threshold seneeseeeseeeesseeseee 24 CLOCK eec c ee 36 ANS ege 24 load SEQUE Ciconia ratito no eve xh alee 38 IRO Modesto ee 23 EE 53 POA Koi ee 23 EE 54 55 ET 23 CD SCT E 36 Ug DH 25 data Oma EE 57 58 DA HONO 68 69 Page 77 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME Electric deua fei dosis 16 68 DLOPDan idle eiui doch idad alli dido 70 eeben icc O denis boite 68 76 PRON EE 68 76 JTAG CW EE 69 A e E 64 FFAG SOUTO aia cani 70 register jumper acquisition controls oido est Ls Lets 25 a O fei E 68 actual address Teoria 46 KA actual sample eeur
27. aster 4 Enable Broadcast Enable Broadcast reserved 0 Page 31 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME Broadcast functionality is implemented for all Key address cycles Modules which are supposed to participate in a broadcast have to get the same broadcast address The broadcast address is defined by the upper 8 bits of the broadcast setup register One module has to be configured as broadcast master the enable broadcast bit has to be set for the others as illustrated below La Q uv e uv e o T asi pus ta Broadcast enable Broadcast enable Broadcast enable VME Crate Broadcast setup example broadcast address 0x34000000 Broadcast Setup Register 0x34000020 0x34000010 Broadcast enable 0x34000010 Broadcast enable 0x34000010 Broadcast enable A I 4 modules will participate in a key reset A32 D32 write to address 0x34000400 Note Do not use a broadcast address that is an existing VME address of a VME card in the crate Page 32 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME 4 14 ADC Memory Page register define S183350 ADC MEMORY PAGE REGISTER 0x34 read write D32 The 8183350 default memory size per channel is 256 MByte e 128 MSample The VME address space window per ADC is limited to 16 MByte 8 MSample however The read write ADC memory page register is used to select one of the 16 memory subdivisions
28. ata dacdatum N daccontrol 1 shift N lt lt 4 read dacstatus until busy 0 daccontrolz2 load N lt lt 4 read dacstatus until busy 0 Page 38 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME 4 16 4 XILINX JTAG TEST register define SIS3350 XILINX JTAG TEST 0x60 write only D32 This register 1s used in the firmware upgrade process over VME only A TCK is generated upon a write cycle to the register A D Im 4 16 5 XILINX JTAG_DATA_IN register define SIS3350 XILINX JTAG DATA IN 0x60 read only D32 This register is used in the firmware upgrade process over VME only It is at the same address as the JTAG TEST register and is used in read access It operates as a shift register for TDO The contents of the register is shifted to the right by one bit with every positive edge of TCK and the status of TDO is transferred to Bit 30 Bit 31 reflects the current value of TDO during a read access 4 16 6 XILINX JTAG CONTROL register define SIS3350 XILINX JTAG CONTROL 0x64 write only D32 This register is used in the firmware upgrade process over VME only PP de 4 4 nome E e HI noe 0 00 A TA binmem i tbd for VME JTAG over CON100 TU E OOOO 1 Enable JTAG output Page 39 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 17 Temperature register 0x70 read only The 8183350 i
29. atus register 31 Clear reserved I5 Jl 30 EI S O O 29 JjClerreerved 1369 _ Jl 28 jClerreervd lA AO 27 Clear reserved ll JN 26 Clear reserved 1069 JN 25 ETE 24 JOea reserved 8 9 o O 23 Joar reserved 7 Jl 22 Clear reserved 6 C9 0 o 21 EI 20 ____ Clear Invert Bit for external Lemo TRG IN 9 0 0 19 ATTE 18 ETE 17 JGlarrsevedl 0 16 Switch offuser LED 9 Setreserved9 Statusreserved9 S 8 Setreserved8_____ Statusreserved8 0 6 Setreserved 6 Statusreserved oS Set Invert Bit for external Lemo TRG IN Status Set Invert bit for external Lemo TRG IN O Switch on user LED Status User LED I LED on 0 LED off denotes power up default setting Page 20 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME Invert bit function for external Lemo TRG IN Don t invert Use for high active TTL signal rising edge 1 Invert Use for low active TTL signals falling edge Use for NIM signals leading edge Page 21 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME E 4 2 Module ld and Firmware Revision Register 0x4 read aettine 8981935350 MODID 0x4 wead Galy D32 Fy This register reflects the module identification of the SIS3350 and its minor and major firmware revision levels The major revision level will be used to distinguish betwee
30. ble 0 IRQ disabled LO enabled O MEIS Level Bit2 O 9 VMElQlewlBt oo O S VMElRQlewlBitO Qalway O O o Do LT IRQ Vector Bit 7 placed on D7 during VME IRQ ACK cycle 0 6 IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 5 IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle Do i IRQ Vector Bit 4 placed on D4 during VMEIRQ ACK cyce 0 3 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle p 2 TIRO Vector Bit 2 placed on D2 during VME IRQ ACK cycle 1 RO Vector Bit 1 placed on DI during VME IRQ ACK eyele 0 0 IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle 0 The power up default value reads 0x 00000000 Page 23 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME 4 4 Interrupt control register 0xC rdetine 199350 IRO CONTROL OxC read write D32 This register controls the VME interrupt behaviour of the 5183350 ADC Eight interrupt sources are foreseen for the time being two of them are associated with an interrupt condition the others are reserved for future use 31 Update IRQ Pulse StausIRQsource7 reservd o o o o O 0O 30 unused jStatusIRQsouceO rser
31. board trigger routing 31 Jreerved LI AP O AMET 15 ADC4 Trigger 1 ADC4 _Trigger 1s ored to LVDS Trigger OUT AA EXTERNAL_CONTROL2_LVDS_OUT I reserved o 10 reserved Le 9 LVDS Trigger IN LLVDS Trigger INisoredto LVDS Trigger OUT 8 LEMO Trigger IN L LEMO Trigger IN is ored to LVDS Trigger OUT 6 ADC3 Trigger A ADC3 _Trigger is ored to LEMO OUT __ __ 3 reserved o o PES 0 jLEMO Trigger IN 1 LEMO _Trigger_IN is ored to LEMO OUT Page 35 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 16 External Clock Trigger Input DAC Control Registers The external clock and trigger inputs of the SIS3350 accept analog input signals for maximum flexibility The internal logic signals are generated on the card by comparing the input signal to a digital to analog converter DAC output value Example routine see CVI sis3350_configuration_readout_lib c int s1s3350 write dac offset unsigned int module_dac_control_status_addr unsigned int dac select no unsigned int dac value 4 16 1 Clock Trigger DAC Control Status register 0x50 read write define S183350 EXT CLOCK TRIGGER DAC CONTROL STATUS 0x50 read write D32 St EME IAS lt DAC Read Write Clear Cycle BUSY CA EP PO A Z B j 0 0 ZJ 4 D DACCommandBitO0 DAC Command Bit 0 Status _ DAC Selection Bit 0 Clock Input DAC Trigger Input DAC Page 3
32. dc void in the file 8153350 adc test1 c CVI directory can be used as starting point for a setup routine for the 5183350 8 1 SIS3350 base program The runtime version of the SIS3350 base program in combination with a SIS3150 USB to VME interface provides access to all implemented SIS3350 features without the need for coding in the first step under Windows Feel free to inquire about the possibility for a loaner in case you are working with another VME master An example screen shot of the SIS3350 base program a signal acquired in ring buffer synchronous mode of operation W 5153350 ADC Test 27 August 2008 1 8 xj Panel View SIS3350 Configuration Information Test Menues 8183350 ADC Test Menue 8183350 ADC Temperature Information le Cl i ADC Sample Clock DEE G Temperature Celsius Frequency Synthesizer Clock Mode MultiE vent Mode Ringbuffer Synchronous Mode T Display Histogram 100 00 Ate 5200 Celsius Frequency Synthesizer Parameter a p T Display FFT EN 54 00 Frequence 25 MHz x M 2 Power N Ji 4 Nof Events va B4 Ringbuffer Pretrigger enge Se 125 50 Fahrenheit Fi d 72 Ringbuffer sample length 2500 a SE i va 20 M Divider Frequence in MHz 1000 Address Threshold a O N Divider 500 00 50 00 0 00 i 20 00 47 00 54 8 53 8 Threshold Trigger Trigger Source Threshold Peaki Bap Pulse Mode On als Length Length Fes Inger
33. e N Divider setting has to be chosen in accordance with the frequency limits specified in the table below Valid N Divider frequency range setting table N Divider Output Frequency MHz Value Minimum Maximum 1 250 35 Page 28 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 9 MultiEvent Max Nof Events register 0x20 read write define S 153350 MULTIEVENT MAX NOR EVENTS 0x20 Pe read write 132 SCH The Sampling Logic will be disarmed in Multi Event mode as soon as the Event counter reaches the value of the MultiEvent_Max_Nof_Events register Bit O O CNN MMEMMEEMNMEEEEEEEEENENENNNNNNNNNNNNNNNNNNN MAX NOF Events Bit19 A E 0 MAXNOFEvents BitO gt gt The power up default value is 0 4 10 MultiEvent Event Counter 0x24 read define S1IS3350 MULTIEVENT EVENT COUNTER 0x24 read D32 This register holds the actual number of events in multi event mode The Event Counter is cleared when the Sampling Logic is armed and it is incremented with every start sampling BA AA OOOO Actual Event counter Bit 19 0 Actual Event counter Bit 0 The power up default value is 0 Page 29 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 11 Gate Synch Mode Event Length Limit register 0x28 read write define S1IS3350_GATE_SYNCH_LIMIT_LENGTH 0x29 4 read write D32 y This register defines the maximum number of samples in conjunction with
34. e SIS3350_ SAMPLE COUNTER THRESHOLD T4T3 ADC3 0x03000074 define SIS3350_ SAMPLE COUNTER THRESHOLD T2T1_ADC4 0x03000078 define SIS3380 SAMPLE COUNTER THRESHOLD T4T3 ADC4 0x0300007C Five 12 bit counters named T1 to T5 counter are implemented for the individual ADC channel The table below illustrates under which condition the 5 counters are incrementing their content with every sampling clock tick The output of the counter values to the event data stream is activated by setting bit O extra header enable bit of the event configuration register The thresholds T1 through T4 are defined in the ADC sample counter Tn Tm registers as shown in the table below Bit 31 16 Bit 15 0 THRESHOLD T2TI ADCN Threshold T2 Threshold T1 THRESHOLD T4T3 ADCN Threshold T4 Threshold T3 4095 T4 T3 T2 T1 0 gt Samples Ti Counter MA TS Counter TA Counter T5 Counter Page 56 of 79 SIS Documentation SIS3350 500 MHz 12 bit Digitizer 4 36 ADC memory define define define fdefine Slo39D90 ADCI OFESET OlIl55390ADCOA OBNBOBI 9193350 ADCS OFFSET 5193350 ADCA OFFSET 0x04000000 0x05000000 0x06000000 0x07000000 SIS GmbH VME The 256 MByte ADC memory per channel can be address in pages of 16 MByte The page is selected with the ADC Memory page register One 32 bit word holds 2 ADC samples as sh
35. ector CONIOOB or over VME A list of firmware designs can be found under http www struck de sis3350firm htm Hardware like the HW USB II G JTAG in connection with the appropriate software will be required for in field JTAG firmware upgrades The JTAG chain configuration is selected with jumper JP101 Xilinx JTAG control register is used to select VME or CONIOOB as JTAG SOUICC CONIOOB is a 2mm e metric 14 pin header that allows you to reprogram the firmware of the 5183350 with a JTAG programmer The pinout is shown in the schematic below It is compatible with the cable that comes with the XILINX HW USB platform cable CON 100B Lol GND VREF D O GND IMs b es GND TCK b g ol GND DO b Y a F1 10 O GND TDI es Ul ai GND NC l Sol GND NC E XILINX_JTAG2 MOLEX 87831 1420 DGND Note The SIS3350 has to be powered for reprogramming over JTAG Page 68 of 79 SIS Documentation SIS3350 SIS GmbH I 500 MHz 12 bit Digitizer VME 7 3 JP101 JTAG chain The JT AG chain on the 5183350 can be configured to comprise the serial PROM only short JTAG chain or to comprise the serial PROM and the 3 Virtex FPGAs long chain The configuration is selected with the 6 pin array JP101 as sketched below Long Chain 1 3 and 2 4 closed JP101 CES na an In the Impact software you will see iMPACT C temp default ipf Boundary Scan gt mBuHXxSBBxaSxim mov Rows
36. ess 50 BO Threshold Fee 50 4 52 2 Threshold PIR A AA E E E AN 51 4 927 Threshold EE 52 4 33 ADC Input tap delay registers 0x2000030 0x2000034 0x3000030 0x3000034 52 4 34 VGA gain registers 0x2000048 0x200004C 0x3000048 0x3000040C eee 53 433 ADC DAC Control EE 54 4 35 1 ADC DAC Control Status registers 0x0x2000050 0x0x3000050 read write 54 4 35 2 ADC DAC Data registers 0x0x2000054 0x0x3000054 readiwrte cece cceeeccseeeeeeeeeeneeeees 55 4 35 3 ADC Sample Counter TN setup register 0x2000070 0x2000074 0x20000078 0x200007C 0x3000070 0x3000074 0x30000078 0x300007C read write ooooocccnccoooocccnccnonoconnnnnnoccnnnnnancccnnononaninnos 56 LM MN B Suc SER 57 d o0l Even Data formar EE 57 4302 diventata A a e a a E 58 A MEME RE ssaa D m 50 XB Iram eee 60 oe AONE EE 6l 6 1 CONTO OTU S aeneae e tans e AE 62 6 1 1 ire ver Grate Lemoa a aa e 62 6 1 2 TiresertGate Eemo Out E 62 6 1 3 Re CMO EE 63 6 1 4 Clock BNP os 64 6 1 5 A A E E EE 65 NN E EEN 66 6 3 A ee 66 E E E EE 67 E JUMPEr CONS UA co 68 7 1 JPS0 V ME addressing mode resel De Ma Vigut EE 68 zas CONTOOB ITA TREE 68 Er JPIOTITACGCHI EE 69 7 4 SW lands W2 VWNIE Dbase address iia a 70 Y LAS Cen dd 70 E NAS MEA O A A ore toda UN ME CUM UU eee 71 8 1 SIS3350 Dase PEO A eS 71 Bel SOLS EE E 12 GETT UU TU Tr 73 9 OW CTC ONS Map EE 73 Del o O E E 73 0 24 A O qr
37. ffer pretrigger del n 48 internal handling 9 ringbuffer sample Ieneth 47 mode sample start address 45 SEAR uode toot tiat uu nc ref neat 14 sample wrap Ienath 44 59 module di 7 EE 40 MUTE Event OG EEN 26 A nei E E 50 A EE 28 ti eege 27 NEN NEE 37 Trigger output select ooooocccooccnoncnnnnnono 35 AA II 53 trigger setup esce een emi ta evenit d utis 49 50 52 operating Copndipons 73 A EE E 53 Operation Mois 26 Xilinx JT AG control 68 76 Operation Modest d aa iet i MERE 10 I or PPM P 68 output ROAK rrr 23 DLS BRU neon ee Crete ore tren deterrent ee ern apr 65 Eed 23 ee 64 65 Sena PRON RE 69 S O A 62 O A Uren orate gran Tre rE 5 Eet 65 SIST100 6C EE 5 E 14 62 SIS E NEE 71 IR RE EE 65 SIR SS Derren eee tr MR 5 P 49 A E A E A E O 5 A edd 75 SIS3350 base program 71 SE 6 75 5153350 VISUAL Sta e reli el 22 pin 31 gnTmentg eene 74 SA EN 12 tebmitiatiODs iio 74 A A E A rer eet 17 PODE XPress EE 5 Sl 16 70 power CONSUMPTION oocccooccncnncnnnncnnnnncnnnnacnnononnnns 73 e 16 70 Page 78 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME eeh NEN 56 59 RE WE E 62 A Doni auctior tasati orbes debant ost T 50 LOCC E eid ecoute aUe Urb sb 62 Eege A T 56 A e 37 PP O oat wees 56 OSS c TOT ENTRE cae 68 A E E 56 user PP EAE QR 56 A 20 E stiles 68 Die ON 68 UD EPOC O 39 68 i16 c 5 6 53 R
38. gitizer SIS GmbH A VME 4 34 VGA gain registers 0x2000048 0x200004C 0x3000048 0x300004C These 4 read write registers are used to set the gain of the four variable gain amplifiers VGA The VGA setting is 7 bit wide define define define define SIS3350_ADC_VGA_ADC1 SIS3350_ADC_VGA_ADC2 SIS3350 ADC VGA ADC3 SIS3350_ADC_VGA_ADC4 0x02000048 0x0200004C 0x03000048 0x0300004C Write Function Read Function VGA setting Bit 1 VGA setting Bit 1 0 VGA setting Bit 0 VGA setting Bit 0 Note The resulting ADC input range depends on stuffing options and the offset DAC setting Find below a coarse range table with default stuffing VGA setting Input range in V Note The maximum input voltage is 8V Page 53 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 35 ADC DAC Control Registers This set of 4 registers is used to shift the input of the 4 ADC channels Example routine int sis3350_write_dac_offset unsigned int module_dac_control_status_addr unsigned int dac_select_no unsigned int dac_value The sequence to load the DACs can be found in section 4 16 3 Note The actual sample registers provide a good way to monitor offset shift during a DAC ramp 4 35 1 ADC DAC Control Status registers 0x0x2000050 0x0x3000050 read write define SLS 32350 ADCI2 DAC CONTROL STATUS 0x02000050 read write D32 define S1I1S3350 ADC34 DAC CONTROL STATUS 0x03000050
39. logic busy LEDs is stretched to guarantee visibility even under low rate conditions 6 3 Channel LED s L1 L4 The 4 card edge surface mounted LEDs L1 L4 can be seen through the corresponding holes in the front panel They visualize the trigger status of the corresponding channel The on duration is stretched for better visibility of short pulses Page 66 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 6 4 PCBLEDs Surface mounted red LEDs are used to signal power status trigger status and FPGA debug information the use of the debug LEDs is firmware design dependent A table with the SMD LEDs is given below Page 67 of 79 SIS Documentation SIS3350 SIS GmbH I 500 MHz 12 bit Digitizer VME 7 Jumpers Configuration 7 1 JP80 VME addressing mode reset behaviour This 8 position jumper array is used to select the addressing mode and the reset behaviour of the 5183350 JP80 Factory default A16 not supported GEO not supported open 6 unused opn open 8 connect VME SYSRESET to board reegt closed The enable watchdog jumper has to be removed during initial JTAG firmware load NOTE avoid a power up deadlock situation by not setting Pos 5 and 8 at the same time 7 2 CON100B JTAG The SIS3350 on board logic can load its firmware from a serial PROMS via the JTAG port on conn
40. n substantial design differences and experiment specific designs while the minor revision level will be used to mark user specific adaptations 3 9 Major Revision Bit ss 8 Major Revision Bit S 6 Minor Revision Bit6 S O 0O Minor Revision Di 4 2 1 Major revision numbers Find below a table with major revision numbers used to date Application user Page 22 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 3 Interrupt configuration register 0x8 define SIS3350 IRQ CONFIG 0x8 read write D32 This read write register controls the VME interrupt behaviour of the 5183350 ADC Four interrupt sources are foreseen for the time being three of them are associated with an interrupt condition the fourth condition 1s reserved for future use The interrupter type is DOS 4 3 1 IRQ mode In RORA release on register access mode the interrupt will be pending until the IRQ source is cleared by specific access to the corresponding disable VME IRQ source bit After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again In ROAK release on acknowledge mode the interrupt condition will be cleared and the IRQ source disabled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again Mie ee T2 RORATROAK Mode 0 RORA CROAK O LI VME IRQ Ena
41. nn EE E ES Boundary Scan aa SlaveSerial EM Select MAP 3 Gal Desktop Configur E Direct SPI Ge E PA xcf32p file ji IMPACT P Processes x IT Load the mcs file to the serial PROM shown as xcf32p 9 6 2 Upgrade over VME Not supported with current SIS3350 firmware yet 1 e JTAG source hard coded to CON100 Page 76 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 10 Index RE 64 data representan on 57 DENI EE 6 DESI E 74 HR EE 5 61 DOS a 23 dig qum 5 61 alin devo c n M 4 A E E E 6 A 71 A E 16 edge A TE 6 16 eher ee 14 ADS EE 38 E 14 PID TOA A E A TAEA 40 extra hedder ecrire i A 59 Address Map E 17 FIR address Pate nai 16 O N 6 addressing IRS CCl E 14 BCOOTAPIIC All d eei cra setas ad beoe eds 6 EES eebe 68 UTI E 17 42 45 TIER APO AID STAC os oeste dante gest o gie 76 ALS EE 4 SCT 74 DAC al 6 73 EE EE 57 58 BEU P 6 FPG A i 8 10 ei We GE 60 Mequene y TIME 28 broadcast Mequeney ss EE eebe 26 A teats tomo S M mc Nas 32 TOM PANIC Pase TN eacteculoot 6 61 CBE EE 31 Eet 16 A EE 6 E 53 external EE 14 26 E 12 external Eeer 14 26 Sate CAM ll 12 EXEC ee O ie ceweateirtdenatitusteanteusdoontwacdaeataesas 6 A E 62 frequency gwnthesguzer 14 26 A TT 14 Aea baeni aa e a 14 O m 62 A eost e ERI estas ah de 63 geographical addressing oooccccoccncnocnnnnccnnnnnoss 75 Ad reste ets e ERU estos nde 27 PEUT SLIDE onis nro eo tres erat
42. nononononccnonanononncnonnnononannnnnnons 37 LIS MEME B edu visio Hc Hcc 38 4 16 4 XILINX JT AG TEST ELSE uses eon reu rrt esa eege 39 4 16 5 JXILINX JTAG DATA IN register eessen e 39 4 16 6 XILINX JTAG CONTROL tfe9istet eee teat one e eek E Ud vu Y o veu Pa oe i ouk ga tice cesa Frve gea Econ 39 4 17 Temperature register 0x70 readionfv eene nennen nnne nens 40 4 18 ADC Serial Interface SPI register 0x74 readiwrte esses 41 4 19 Key address general reset 0x400 write only 42 4 20 Key address VME arm sampling logic 0x410 write only 42 4 21 Key address VME disarm sampling logic 0x414 write only 42 422 Key address VME EE Geet 42 4 23 Key address VME Timestamp Clear esses eene nennen eene rne 42 Page 3 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 24 Event configuration registers 0xO 1000000 0x02000000 0x03000000 read write 43 4 25 Direct Memory Stop Mode Sample Wrap Length regater e 44 4 20 Sample Start address E EE 45 421 ADC Next Sample address eebe dsobba taii dabitis e Mast ds boten dandy 46 428 Rineb rner sample EE 47 429 Rigo bummer Pre Dela vientre eebe Maud ibtd 48 430 End Addtess Phreshnobld resisters nica lied lio bid Lotus tee 48 4 3 Trigger setup register registers 0x02000030 0x02000038 0x03000030 0x03000038 49 4 32 Threshold registers 0x02000034 0x0200003C 0x03000034 OxO300003C s
43. on SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 2 4 Clock sources The SIS3350 features following clock modes e Internal fixed clock e Internal frequency synthesizer e External analog e External LVDS 2 4 1 Internal clock The internal clock is generated from an on board 100 MHz quartz or a frequency synthesizer Internal clock speeds 100 MHz fixed Synthesizer 31 25 500 MHz 2 4 2 External clock BNC analog or LVDS A analog symmetric external clock ratio between 45 55 and 55 45 can be fed to the module through the BNC connector The clock that is distributed to the digitizer chips is derived with the clock DAC and a comparator The BNC clock output can be used to verify that the resulting meets symmetry requirements Alternatively a LVDS clock can be fed to the module over the HDMI connector Pins 1 3 Min sym clock Max sym clock 500 MHz 2 5 Trigger control pre post start stop and gate mode The 8183350 features pre post trigger capability as well as start stop mode acquisition and a gate mode in which start and stop are derived from the leading and trailing edge of a single control input signal 2 6 Internal Trigger generation The trigger output of the SIS3350 can be either used to interact with external trigger logic or to base start stop on a threshold ie one individual threshold per ADC channel of the digitized data The user can select between triggering on the conditions above and bel
44. on register ADC1 ADC2 Direct Memory Stop Mode Sample Wrap Length register ADC1 ADC2 Sample Start address register ADC1 ADC2 Next Sample address register ADC 1 Next Sample address register ADC2 Ringbuffer Sample Length ADC1 ADC2 End Address Threshold ADC1 ADC2 ADC 1 Trigger setup register ADC1 Trigger Threshold register ADC2 Trigger setup register ADC2 Trigger Threshold register ADCI Input Tap Delay register ADC2 Input Tap Delay register ADC1 VGA register ADC2 VGA register ADCI ADC2 DAC Control Status register ADCI ADC2 DAC Data register ADC1 Sample Counter T1 T2 setup register ADC1 Sample Counter T3 T4 setup register Ringbuffer PRE Delay ADCI ADC2 ADC2 Sample Counter T1 T2 setup register ADC2 Sample Counter T3 T4 setup register UI ate Ba d mg mich Page 18 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME E Event information ADC group 2 0x03000000 4 Event configuration register ADC3 ADC4 0x03000004 Direct Memory Stop Mode Sample Wrap Length register ADC3 ADC4 0x03000008 Sample Start address register ADC3 ADCA 0x03000010 0x03000014 Next Sample address register ADC3 Next Sample address register ADCA 0x03000020 0x03000024 0x03000028 Ringbuffer Sample Length ADC3 ADC4 Ringbuffer PRE Delay ADC3 ADC4 End Address Threshold ADC3 ADC4 ADC3 Trigger setup register ADC3 Trigger Threshold register ADC4 Trigger setup register ADC
45. ow threshold A FIR trigger mode is implemented as second trigger alternative Page 14 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 2 7 VME Interrupts Two registers the Interrupt configuration and the Interrupt control register are implemented for interrupt setup and control Four interrupt sources are implemented e Reached End Address Threshold level sensitive e Reached End Address Threshold edge sensitive e End of event e End of last event in multi event mode Page 15 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 3 VME Addressing As the SIS3350 VME FADC features memory options with up to 4 times 512 MSamples A32 addressing was implemented as the only option for the time being The module occupies an address space of OX7FFFFFF Bytes Le 128 MBytes are used by the module The base address is defined by the selected addressing mode which is selected by jumper array JP80 and SW and SW2 in non geographical mode The table below summarises the possible base address settings SWI SW220 7 Bit 2720 X SWI SW2 8 F Bit 27 1 nl i Not implemented in this design MES Not implemented in this design Shorthand Explanation SWI SW2 Setting of rotary switch SW1 or SW2 respective Notes e This concept allows the use of the SIS3350 in standard VME as well as in VME64x environments 1 e the user does not need to use a VME64x backplane e The factory default se
46. own in the table below 4 36 1 Event Data format 1 used for all modes except Direct Memory Trigger Stop Mode 31 16 15 0000 Timestamp 47 36 0000 Timestamp 35 24 0000 Timestamp 23 12 0000 Timestamp 11 0 0000 Information 47 36 0000 Sample Length 26 24 0000 Sample Length 23 12 0000 Sample Length 11 0 ADC raw data buffer N Sample Length Note The data representation of the ADC is shown below Digitized Value Analog input voltage Highest input voltage 42 5 V e g sample 2 sample 1 sample 4 sample 3 sample N sample N 1 Lowest input voltage 2 5 V e g Page 57 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 36 2 Event Data format 2 used in Direct Memory Trigger Stop Mode only 31 16 15 0 0000 Timestamp 47 36 0000 Timestamp 35 24 0000 Timestamp 23 12 0000 Timestamp 1 1 0 0000 Information 47 36 0000 Sample Stop Addr 26 24 0000 Sample Stop Addr 23 12 0000 Sample Stop Adadr 1 1 0 0 Sample M 2 sample M 1 ADC raw data buffer sample M 4 sample M 3 M N Sample Length sample M N sample M N 1 Sample Stop Addr 2 ES Sample Stop Addr lt q sample 2 sample 1 4 sample 4 sample 3 Sample Length 2 eee sample M sample M 1 Sample Stop
47. pezoid is on average 0 A Trigger Output pulse is generated IGT is set GT 1 e GT is set GT the Trigger Out Pulse will be issued if the actual trapezoidal value goes above the programmable trapezoidal threshold value e GT is cleared LT the Trigger Out Pulse will be issued if the actual trapezoidal value goes below the negative programmable trapezoidal threshold value Page 51 of 79 SIS Documentation SIS3350 SS Gub A 500 MHz 12 bit Digitizer VME 4 32 3 Threshold Gate Threshold value OFF TE value ON default after Reset 0x0 A valid Gate Output is generated on two conditions e GT is set GT in trigger setup register the Gate output signal will be set if the actual ADC value goes above the programmable threshold value ON and OFF and it is valid until the actual ADC value goes below the threshold value OFF e GT is cleared LT in trigger setup register the Gate output signal will be set if the actual ADC value goes below the programmable threshold value ON and OFF and it is valid until the actual ADC value goes above the threshold value OFF 4 33 ADC Input tap delay registers 0x2000030 0x2000034 0x3000030 0x3000034 Internal use only define SIS3350_ADC_INPUT_TAP_DELAY_ADC1 0x02000040 define SIS3350_ADC_INPUT_TAP_DELAY_ADC2 0x02000044 define SIS3350_ADC_INPUT_TAP_DELAY_ADC3 0x03000040 define SIS3350_ADC_INPUT_TAP_DELAY_ADC4 0x03000044 Page 52 of 79 SIS Documentation 500 MHz 12 bit Di
48. red pins on the d and z rows of the P1 and P2 connectors are listed below GAP GND GA0 pulp RE A p cc GND D GND VPC D GND VPC D Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Page 75 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 9 6 Firmware upgrade The firmware of the SIS3350 can be upgraded over JTAG The upgrade options are VME on units that have intact firmware and the JTAG connector CONI00 The VME upgrade option is not tested for the current firmware release yet 9 6 1 Upgrade over CON100 The firmware can be upgraded with the Xilinx Impact software which is part of the Webpack that can be downloaded from the Xilinx web page for free A Xilinx JTAG parallel cable or USB Xilinx part number HW USB cable can be used to roll in the firmware Configure the SIS3350 for short JTAG chain refer to section 7 3 JP101 CON 100 is JTAG source by default unless programmed for VME with the Xilinx JTAG control register With your hard and software properly set up you should see a screen as illustrated below after executing the initialize chain command ied iMPACT C ftempldefau ip ee acan Lan Ke
49. reshold No explicit Multievent Page 10 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 2 3 2 Ring buffer synchronous Mode Trigger source internal Threshold Trigger or of all channels internal FIR Trigger or of all channels internal VME Key external Trigger LEMO LVDS no Trigger delay End of acquisition condition Single Event Multi Event programmable nof_events Address Threshold Address Counter Used Parameters programmable Ringbuffer PRE length up to 16380 in steps of 2 samples programmable Ringbuffer Sample length up to 16384 in steps of 8 samples 2 3 3 Direct Memory Gate asynchronous Mode Gate source internal Threshold Gate On Off each channel individual no Gate Trigger delay Used Parameters programmable Ringbuffer PRE length up to 16380 in steps of 2 samples programmable Max Length programmable Gate Extend Length End of acquisition condition Address Threshold Address Counter Page 11 of 79 SIS Documentation SIS3350 SIS GmbH 500 MHz 12 bit Digitizer VME 2 3 4 Direct Memory Gate synchronous Mode Gate source internal Threshold Gate On Off or of all channels external Gate Trigger LEMO LVDS no Gate Trigger delay Used Parameters programmable Ringbuffer PRE length up to 16380 in steps of 2 samples programmable Max Length programmable Gate Extend Length End of acquisi
50. s equipped with a serial 10 bit Analog Devices AD7314 temperature sensor The temperature reading is stored in twos complement format Refer to the AD7314 data sheet for more detailed information define 1 53350 INTERNAL TEMPERATURE REG 0x70 Ee read D32 7 BA CM WEG O 3 Data Bit 9 MSB S O A a O Data Bit 0 LSB The operating temperature ranges from 35 C to 85 C and is covered by the table below 025 0 25 C C 00 1100 1000 01 0010 1100 Zo 100 C Note The Celsius temperature reading is obtained by casting the read data to signed short and dividing the obtained value by 4 0 after float conversion Page 40 of 79 SIS Documentation SIS3350 SIS GmbH 4 500 MHz 12 bit Digitizer VME i 4 18 ADC Serial Interface SPI register 0x74 read write define S183350 ADC SERIAL INTERFACE REG 0x74 write D32 Several parameters of the 12 bit 500 MS s ADC AT85ASO001 chip like duty cycle stabilization e g can be configured with the SPI serial Peripheral Interface The SPI register is the interface between the 8183350 front end FPGAs and the ADC SPIs Please refer to the documentation of the ATS5AS001 ADC chip for details BA A LL P D idee Di 16 AddesBi O OOS 5 DaaBilS MSB D Dep Se FR o Data Bit 0 LSB The power up default value is 0x0 Page 41 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit
51. ternal channel triggers as Gate Trigger 4 Setreserved4 S 0 SetMode of Operation Bit L ps Mode of Operation BitO The power up default value reads 0x0 Page 25 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME Operation Mode bit setting table Mode of Mode of Mode of Mode of Operation Operation Operation Operation Bit 2 Bit 1 Bit O O O f O Ringbuffer Asynchronous Mode O O 1 _ Ringbuffer Synchronous Mode NENNEN E eee O 1 0 Direct Memory Gate Asynchronous Mode O 1 1 Direct Memory Gate Synchronous Mode NENNEN A AA 1 0 f O Direct Memory Trigger Stop Mode Z oZ oo 1 0 f 1 Direct Memory Trigger Start Mode E re ee eee 1 reserved Multi Event mode bit 0 Sampling Logic Armed state will be cleared at end of event Sampling Logic Armed state will be cleared at end of last event defined with MultiEvent Max Nof Events register Clock source bit setting table Clock Source Clock Source Clock Source Bitl BitO 0 JO Frequency Synthesizer up to 500 MHz 0 internal 100 MHz t Of external LVDS external BNC Page 26 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 6 Direct Memory Trigger Delay register 0x14 read write define S1I1S3350 TRIGGER DELAY 0x14 read write D32 The external trigger signals LVDS LEMO and the internal trigger signal will be dela
52. tett pts EE 15 SG Eet 16 3 1 Address MaD estates te lotte lille 17 A Eeer 20 4 1 Control Status Register OxO wnteiread nennen enne nene rne nnnnis 20 4 2 Module Id and Firmware Revision Register 0x4 read 22 4 2 1 ENT ere NIS SET EI TET E OE D T 22 A JirupbconipurauomTeelsterdU X65 ida dades 23 4 3 1 IR ere TE 23 44 Interrupt control rebistet Uleila lei 24 4 5 Acquisition control register 0x10 readiwte eese nennen nennen nnns 223 4 6 Direct Memory Trigger Delay register 0x 14 read write ocoooccccoccnnonccnnnonnnonnnnonnconononnnnncononacnnnnnos 27 4 7 Direct Memory Start Mode Sample Length register 0x18 read wrIIte cooooncccoocnnonccnonocnnonccnnnnnnos 21 4 8 Frequency Synthesizer register 0x IC read write esee nennen 21 4 0 MultiEvent Max Nof Events register 0x20 readiwrte eese 29 4 10 M ltibveut Event Counter 0x24 Tead u aedis ot ber tte a et dtes ova det ee lcd 29 4 11 Gate Synch Mode Event Length Limit register 0x28 read write eese 30 4 12 Gate Synch Mode Event Length Extend register Ox2C readivwnte eese 30 ANS XBISI BroddcdsE SCLUD E 31 AAA ADC Memory Pace Tesi ster E 33 415 rover Output Select TC X99 depot tbe Drbetuteit ion 35 4 16 External Clock Trigger Input DAC Control Registers ener 36 4 16 1 Clock Trigger DAC Control Status register 0x50 readiwte 36 4 16 2 Clock Trigger DAC Data register Ox 54 read write ccooocccooccnnoncn
53. tion condition Single Event Multi Event programmable nof_events Address Threshold Find below a illustration for gate mode Besides gate chaining you can see the effect of the pre length pre and gate extend length extend parameters This mode of operation can be used for sparsified data acquisition also Gate chaining example with GT cleared LT time AC DA Ton a y d Event 1 Event 2 Event 3 Header Active Gate T on Threshold on Pre Extend T off Threshold off Page 12 of 79 SIS Documentation SIS3350 500 MHz 12 bit Digitizer 2 3 5 Direct Memory Stop Mode Trigger source internal Threshold Trigger or of all channels internal FIR Trigger or of all channels internal VME Key external Trigger LEMO LVDS Trigger delay End of acquisition condition Single Event Multi Event programmable nof events Address Threshold Used Parameters programmable Ringbuffer PRE length up to 16380 in steps of 2 samples 2 3 6 Direct Memory Start Mode Trigger source internal Threshold Trigger or of all channels internal FIR Trigger or of all channels internal VME Key external Trigger LEMO LVDS Trigger delay End of acquisition condition Single Event Multi Event programmable nof_events Address Threshold Used Parameters TTbd SIS GmbH VME Page 13 of 79 SIS Documentati
54. tting is EN_A32 closed SW1 3 SW2 0 i e the module will react to A32 addressing under address 0x30000000 With more than one unit shipped in one batch a set of addresses like 0x10000000 0x20000000 0x30000000 may be used also e The Al6 jumper allows for a future changed addressing scheme with different resource allocation Page 16 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 3 1 Address Map The SIS3350 resources and their locations are listed in the table below Note Write access to a key address KA with arbitrary data invokes the respective action Offset Size in BLT Access Function Bytes 0x00000000 4 WR Control Status Register U Kregister 0x00000004 4 Ronly Module Id and Firmware Revision register 0x00000008 4 RW Interrupt configuration register 0x00000000 A R W interrupt control register SSS p ADC Serial Interface SPI register 0x00000400 E KA Arm Sampling Logic 0x00000414 A KA Disarm Sampling Logic SSS oxo0000418 4 KA trigger SOS oxo000041c 4 KA Timestamp Cer AAA 0x00000010 4 R W___ Acquisition control status register J K register 0x00000014 Al RW Direct Memory Trigger Delay register 0x00000018 4 RW Direct Memory Start Mode Sample Length register 0x0000001C 4 R W Frequency Synthesizer register 0x00000020 RW ___ MultiEvent Ma
55. v Intemal Trigger ADCAS disable a va zi 1 Lemon Key Timestamp Clear Invert Lemo In NIM Ch a aj ADC3Z disable ed 1 vd 1 LVDS In Event Time s ADC22 disable zs 1 en 1 Wess ADC1S FIR GT rising a 4000 a A n e Sa 4 RAW SIGNALS 52 8 51 8 50 8 43 8 67 116 Panel Plot Style Plot Background Color Grid Color Number of Events Timestamp sec ADC4 4 1 3 774211582 Number of Events Timestamp sec ADC3 4 1 3 774211682 Number of Events Timestamp sec ADC2 4 1 3 774211692 Number of Events Timestamp sec ADC 4 1 11 758703720 vd 0 2 X Min Scale i y E X Mas Scale E show ADC 1 LY Zoe i Zooming Fitting v X Autoscale Y Autoscale IV Auto Delete Raw Graph y i start Q 5153350 Test 5153350 ADC Test 27 Page 71 of 79 SIS3350 500 MHz 12 bit Digitizer SIS GmbH VME SIS Documentation 8 2 SIS3350 visual start A minimum VisualC program to see first data can be found in the directory software Wisualapplication The board 1s set up without VGA and DAC setting what results 1n an input range of about 2 5 2 5 V and operated in VME triggered mode in the example Typical screen output is shown below es CA Sofbware sis3350 wisual start Release sis3350 visual starte A AA 8680661 86 gt levent info i event info 2 Page 72 of 79 x2 4h29 6 ixl 28 2 ENN RS HBxH 74dB6d2Z
56. ved o o 0 29 unused Status IRQ source S reserved TO 28 junued CC Status IRQ source 4 reserved 0 Status IRQ source 3 End Address Threshold Flag level sensitive O 26 unused Stats IRQ source 2 End Address Threshold Flag edge sensitive 0 25 unused Status IRQ source 1 End of last Event edge sensitive 0 24 unused Status IRQ source 0 End of Event edge sensitive 23 Disable Clear IRQ source7 Statusflagsouce7 CCA 22 Disable Clear IRQ source6 StatusflagsoureO gt gt gt 0 21 Disable Cler IRQ sourceS Status flag source5 O 20 Disable Clear IRQ source4 Stausflagsouce 40 19 Disable Cler IRQ source3 Status flag source3 OO 18 Disable Cler IRQ source2 Status flag source o o o oS O 17 Disable Clear IRQ source Status flag souge O 16 Disable Clear IRQ source0 Status flag source ll 15 unsd Sta VME IRQ 14 unsed Statusinternal IRQ D unused 0 O0 OSOS 9 unsed 0 0000 000 0 8 junsed 7 EnableIROsource 7 Statusenable source 7 read as 1 if enabled 0 if disabled 1 6 EnableIRQsource6__________ Statusenable source 6 read as 1 if enabled O if disabled 1 i i p Oi 06 23 Enable IRQ source 3 Status enable source 3 read as 1 if enabled O if disabled O Enable IRQ source 2 L tzts enable source 2 read as 1 if enabled 0 if disabled Jo 1 EnableIRQsourcel__
57. ven in samples 1 e number of 16 bit words BA e Sample Start Address Register Bit 23 Sample Start Address Register Bit 2 O unused read SO gt The power up default value 1s O Page 48 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 31 Trigger setup register registers 0x02000030 0x02000038 0x03000030 0x03000038 define SIS3350_TRIGGER_SETUP_ADC1 0x02000030 define SIS3350 TRIGGER SETUP ADC2 0x02000038 define SIS3350 TRIGGER SETUP ADC3 0x03000030 define SIS3350 TRIGGER SETUP ADCA4 0x03000038 These read write registers hold the 8 bit wide trigger pulse length in samples These read write registers hold the Peaking and Gap Time of the trapezoidal FIR filter Gap Time SumG Time Peaking Time A AA Trigger Pulse Length SumG time only FIR trigger EE EE 2 JjSunGbit 8 SumGbitO 0 6 reserved S Peaking time P only FIR trigger x P Si deu 0 PbO The power up default value reads Ox 00000000 Si Sum of ADC input sample stream from x to x P P Peaking time number of values to sum SumG SumGap time distance in clock ticks of the two running sums The maximum SumG time 16 clocks The minimun SumG time 1 clocks Values gt 16 will be set to 16 Value 0 will be set to 1 The maximum Peaking time 16 clocks The minimun Peaking time 1 clocks Values gt 16 will be set to 16 Value 0 will be set to 1
58. written with the same value the best way is to make use of the address s1 3350 EVENT CONFIG ALL ADC to write to the registers of all channel groups simultaneously ADC group 0 group O ADC 1 and 2 I group 1 ADC 3 and 4 De 9 umsedireadO os 8 unused red AAA 0 _ Extra Header Enable bit S Page 43 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 25 Direct Memory Stop Mode Sample Wrap Length register fdefine 1383350 DIRECT MEMORY SAMPLE WRAP LENGTH ALL ADC 0x01000004 define 13 83350 DIRECT MEMORY SAMPLE WRAP LENGTH ADC12 0x02000004 define 13 3350 DIRECT MEMORY SAMPLE WRAP LENGTH ADC34 0x03000004 This register defines the number of samples of each event in conjunction with the mode of operation Direct Memory Trigger Stop Mode The maximum programmable sample wrap length is 128M 8 E NENNEN sample Wrap Length Register BIT26 D Lines The power up default value is 0 Page 44 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME 4 26 Sample Start address register fdefine 15 83350 SAMPLE START ADDRESS ALL ADC 0x01000008 define 1 83350 SAMPLE START ADDRESS ADC12 0x02000008 define 13 83350 SAMPLE START ADDRESS ADC34 0x03000008 These registers define the memory start address The value is given in samples 1 e number of 16 bit words Only Sample Start addresses on a 8 16 bit sample boundary 1 e 16 bytes are valid BA E
59. x Nof Events register 0x00000024 Ronly MultiEvent Event Counter 0x00000028 R W GateSynch Mode Event Length Limit register 0x0000002C R W Gate Synch Mode Event Length Extend register 0x00000030 4 R W CBLT Broadcast Setup register 0x00000034 4 RW ADC Memory Page register 0x00000058 4 Rw Trigger Output Select register 0x00000050 4 R W Clock and Trigger Input DAC Control Status register input threshold 0x00000054 4 R W Clock and Trigger Input DAC Data register input threshold 0x00000060 RW XILINX JTAG TEST ITAG DATA IN 0x00000064 Wonly XILINX JTAG CONTROL 0x00000070 LI Ronly Temperature Register 0x00000074 Page 17 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME Event information all ADC groups 0x01000000 4 Event configuration register all ADCs 0x01000004 4 Direct Memory Stop Mode Sample Wrap Length register all ADCs sample Start address register all ADCs Ringbuffer Sample Length all ADCs w Ringbuffer PRE Delay all ADCs End Address Threshold all ADCs Event information ADC group 1 0x02000000 4 0x02000004 4 0x02000008 0x02000010 0x02000014 0x02000020 0x02000024 0x02000028 0x02000030 0x02000034 0x02000038 0x0200003C 0x02000040 0x02000044 0x02000048 0x0200004C OX0Z0000390 0x02000054 0x02000070 0x02000074 0x02000078 0x0200007C Event configurati
60. yed by the value of the trigger delay register in samples in conjunction with the modes of operation Direct Memory Trigger Stop Mode and Direct Memory Trigger Start Mode The maximum programmable delay is 64M samples e half memory depth Pretrigger function Be MEME EN TRIGGER DELAY BIT25 AAA AAA A OOOO ES 0 The power up default value is 0 4 7 Direct Memory Start Mode Sample Length register 0x18 read write define SIS3350_DIRECT_MEMORY_SAMPLE_LENGTH 0x18 read write D32 This register defines the number of samples in conjunction with the mode of operation Direct Memory Trigger Start Mode The maximum programmable sample length is 128M 8 BA SAMPLE_LENGTH_BIT26 E E PA 3 SAMPLE_LENGTH_BIT3 0 0 KS 3 2 0 am The power up default value is 0 4 8 Frequency Synthesizer register 0x1C read write define SIS3350 FREQUENCE SYNTHESIZER Ox1C vead write D32 This register defines the sampling frequency of the SIS3350 in frequency synthesizer clock mode Page 27 of 79 SIS Documentation SIS3350 SIS GmbH A 500 MHz 12 bit Digitizer VME The frequency is defined by the expression Frequency 25 MHz M 2 uu unused read as 0 NI bit 1 of N Divider 9 NO0 bit 0 of N Divider 8 MS bit 8 of M PEE 0 MO bit 0 of M The power up default value is 0x14 20 gt 20 x 25MHz 500MHZz Note Th

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