Spartan-IIe Development Platform
Contents
1. 11 User s Manual Spartan lle Development Platform Please note that access to the flash memory via JTAG is not supported However this may be accomplished by using additional software It is highly recommended not to re program the CPLD unless you know exactly what you are do ing Reprogramming the CPLD may break the mechanism which is configuring the FPGA from flash memory Refer to Figure 29 to locate the JTAG compo nents S Figure 29 Locate JTAG Connector VG96 Connector A VG96 connector is used to attach customized peripherals to the board The connector is de signed to provide full access to the FPGA s vari ous I O standards including its LVDS pairs and access to the Vcco and Vref pins The Vref voltages are applied to a number of dual purpose pins on the VG96 connector See the Spartan IIE data sheet for further details The Vcco voltages are set to either 1 8V 2 5V or 3 3V using 4 banks of jumpers Refer to Figure 30 Locate Vcco Jumpers The complete I O banks 5 6 7 and O of the FPGA are routed to the VG96 connector Table 6 lists the available signals The piggy back connectors J2 J3 and J4 are wired in par allel with rows A B and C of the VG96 connec tor Refer to Figure 31 to locate the piggyback connector Piggy back 4 expansion S igure 31 Locate Pi vba i m 12 Trenz Electronic GmbH Spartan lle Development Platform User s Manual Al J2 B J3 C J42. Trenz Electronic GmbH ats he Brendel 20 a trenz 32257 B nde Germany TTO www trenz electronic de 2003 January 9 Spartan lle Development Platform User s Manual Introduction The Spartan lle Development Platform is de signed to provide a complete and consistent FPGA development platform which is especially well suited to develop FPGA centric processing applications The platform provides all compo nents required to create embedded processor systems consisting of e High density FPGA implementing a soft CPU e g Xilinx MicroBlaze and applica tion specific logic e Memory sub system combining flash mem ory and SRAM to store firmware non volatile data and dynamic data e Peripherals for simple user interaction and in system debugging e Expansion ports to interface with application specific circuitry In typical desktop applications the Spartan lle Development Platform does not require any ad ditional hardware or software components be sides a standard PC with USB connector This makes the Spartan lle Development Platform an ideal solution for e Training and education e Development of intellectual property e Firmware development e Prototyping e Industrial control applications Figure 1 Spartan lle Development Platform Trenz Electronic GmbH The TE XC2Se board the basis of the Spartan lle Development Platform comes in the well known 160x100mm Euro form factor with VG96 connector T
3. Function i Function i Function 5V ext 5V ext 5V ext I O DLL M6 L55N T8 GCK1 R7 L54N I O T7 L54P L56N Vref U T I O T6 L56P 01 R5 L58N Vref T4 L60P TS L58P M7 L53N Vref o1 N7 L55P N8 L53P N6 LS7N R4 L61P L57P 01 NS LS9N T3 L6ON Vref P5 L59P K5 L68N P4 L61N K4 L68P P1 0 P2 L62N M4 L64N L62P 11 N1 L66N M3 L64P M1 L66P 2 N3 L63N Vref M2 L67N Vref N2 L63P L1 L69P x A L2 L69N L3 L67P 4 K3 L7ON K1 L71N Vref K2 L70P L5 L65N Vref J1 L71P L4 L65P J2 L72P O J3 L72N c K D I O H1 L73N G1 L75N H2 L73P N H4 L74P O0 H3 L74N G2 L75P Vref F1 G3 L76P co G4 L76N L78N M F3 L79N F2 L78P F4 L79P Vref M E2 L80P NO E1 L80N E3 L81P Vref D2 L82P N N w N N N gt X OV AIJ N gt N o oO gt Oo X O1 O m O O D1 L82N E4 L81N 23 1 L83N Vref 7 3 10 C2 L83P 24 G5 B3 W O F5 L77P L3N B L1P L3P A3 LON Vref C4 4 LOP 27 B5 L4N Vref 6 10 5 L4P 28 C5 L2N Vref A7 O D5 L2P 29 L5N C7 L6P L5P 30 7 L6N 7 L7P I O DLL D7 L7N Vref C8 GCK3 GND GND GND a S D lt cO o 5 D O P a 5 O Trenz Electronic GmbH 1 Spartan lle Development Platform Appendix References Spartan lIE 1 8V FPGA Family Xilinx November 9 2001 FastFLASH XC9500XL H
4. Figure 24 RS232 Connector Pinout VGA Monitor Interface The TE XC2Se board provides circuitry to inter face with industry standard VGA monitors To do so RGB tuples along with horizontal and ver tical sync pulses need to be generated inside the FPGA A simple passive DAC creates the required analog signals Refer to Figure 25 for a simplified schematic INSYNC FPGA J21 Figure 25 VGA Output Circuitry Due to the simple design the maximum dot clock of the VGA output is limited As a rule of thumb a dot clock of 25MHz for 640x480 resolu tion at 60Hz vertical frequency is a good value Figure 26 details the pinout of the VGA connec tor Trenz Electronic GmbH User s Manual q q q SS Figure 26 VGA Connector Pinout JTAG To allow full flexibility in programming configur ing the FPGA and CPLD the JTAG chain is ac cessible on a separate jumper Figure 27 illus trates the JTAG chain JTAG J23 Figure 27 JTAG Chain The pinout of J23 is compatible to the flying leads of Xilinx Parallel Cable lll Refer to Figure 28 for the connector pinout 1 3 3V 2 GND 3 N C 4 TCK 5 N C 6 TDO 7 TDI 8 N C 9 TMS 000000000 Figure 28 JTAG Connector Pinout Before using JTAG to configure the FPGA the configuration mode should be set accordingly This is accomplished with J18 refer to Table 5 for the proper settings slave parallel mode open boundary scan mode closed Table 5 J18 Settings
5. configu ration space of the flash memory 0x40000 When used with the a parameter the rawfile is loades to the application space of the flash memory 0x80000 When used with the f parameter the bitstream contained in bitfile is loaded to the factory con figuration space of the flash memory Caution Do not re program the factory configu ration space unless you know exactly what you are doing Once you re programmed the factory configuration downloading bitstreams via USB may no longer work For your daily work we recommend using one of the following setups e Add a shortcut to TEprog exe to your desk top You may program a bitstream to the user configuration space by just dragging a Ditfile onto this shortcut e Create a batch file calling TEprog exe with the appropriate parameters Add this batch file to your WebPACK ISE project A simple double click on this file will program the bit stream to the board without leaving the Xil inx Project Navigator The duration of the download to the Flash mem ory depends on the type of the USB host con troller and not on the speed of your host PC Refer to Table 1 for typical download durations USB host controller duration seconds UHCI Intel or VIA chipsets OHCI OPTI chipsets EHCI USB 2 0 chipsets Table 1 Download Durations Spartan lle Development Platform User s Manual download designs O FPGA LCD O Gat C 2 300 000 gates 2X 16 charac
6. must be always ne gated E The display features an LED backlight which greatly increases readability In setups with stringent low power requirements the backlight may be disabled by removing jumper J79 Expansion Port The expansion port provides a convenient way of adding small form factor expansions to the TE XC2Se board Virtually any peripheral with a generic 8 bit microcontroller bus may be at tached here In addition five general purpose Os are provided four of them being usable as LVDS pairs Refer to Figure 21 to locate the connector Figure 22 details the connector pinout Serial Port Connector To interface standard RS232 peripherals with the TE XC2Se board a level shifter is attached to the FPGA The required UART functionality may be efficiently implemented in the FPGA Trenz Electronic GmbH D4 E14 expansion D3 E13 port D2 D15 D1 D14 A 2 0 D 7 0 FPGA Expansion Port A Pi n lt i ie i N reserved reserved oo0oo00000000000 oo0o00000000000 Figure 22 Expansion Port Pinout When working with soft CPUs like Xilinx Micro Blaze the serial port may be used for in system debugging using gdb from the GNU tools collec tion The RS232 implements no handshake signals Figure 23 shows a simplified schematic dia 10 Spartan lle Development Platform gram refer to Figure 24 for the connector pi nout TxD TxD B13 C12 RS232 J20 FPGA Figure 23 RS232 Circuitry
7. should be taken not to overwrite the facto ry configuration as this will inhibit future pro gramming of the flash memory via USB Further details on the download mechanism may be found in the FPGA Programming section of this document Consult the flash memorys data sheet for timing diagrams and a description of the command set Spartan lle Development Platform KO C factory configuration 0x00000 0x3FFFF application space 0x80000 0xFFFFF Table 3 Flash Memory Map SRAM An IDT asynchronous Static RAM of type IDT71V416S is attached to the memory bus to store volatile data e g a processor system s stack and heap data The RAM is fast enough to serve as zero wait state main memory for typical processing appli cations Consult the RAM s data sheet for timing diagrams Switches Buttons and LEDs The board provides a set of eight DIP switches four push buttons and four LEDs Refer to Figure 17 to locate the components switches buttons LEDs Figure 17 Locate Switches Buttons LEDs The switches buttons and LEDs are attached to the CPLD which is in turn attached to the mem ory bus Table 4 shows the peripheral s memory map Note that the registers are uni directional i e the LED register may not be read and the switch or button registers may not be written Trenz Electronic GmbH User s Manual ran stn non DIP switch 0x00001 read only S2 1 Bit 0 S2 2 Bit 1 S2 3 Bit 2 S2 4 Bit 3 S
8. 2 5 Bit 4 S2 6 Bit 5 S2 7 Bit 6 S2 8 Bit 7 push buttons 0x00000 PB1 Bit 0 Bit 1 Bit 2 Bit 3 read only 0x00002 Bit O Bit 1 Bit 2 Bit 3 L4 LED FPGA L5 Pin C15 Table 4 CPLD Memory Map write only The CPLD read and write waveforms are similar to those of asynchronous RAMs Refer to Figure 18 and Figure 19 for details S Oh ai CS mm o JS o Figure 18 CPLD Read Waveforms AB gt Figure 19 CPLD Write Waveforms Expansion Bus The TE XC2Se board offers an 8 bit expansion bus which can be used to expand the board with small form factor peripherals The expan sion bus is shared with the liquid crystal display access to LCD or expansion bus is mutually ex clusive Refer to Figure 20 for a simplified sche matic Spartan lle Development Platform A 2 0 User s Manual a I I I III D 7 0 Lu G13 G14 G16 L30P H16 D30 E16 L26P __ oo y O F145 L26N _ ooo y AQ LON oo HtA o O DB FPGA Figure 20 Expansion Bus LCD Display A Polytronix liguid crystal display of type PC 160203 with 2x16 characters is attached to the expansion bus to provide a convenient way of visualizing textural data The display is capable of displaying the complete range of ASCII char acters as well as user defined symbols Refer to the according data sheet for a description of the displays character and command set as well as timing information Signal E is direction signal for a busdriver and
9. 4 R13 A8 D3 G15 M11 A7 D2 F14 P13 A6 D1 E15 N12 A5 DO B16 N11 A4 N10 A3 10 A2 T10 A1 N16 N14 M14 N15 M13 af O Lis o O Ki4 ooo O M6 M5 O ooo e O e FPGA FPGA Figure 16 Memory Subsystem Flash memory An AMD flash memory of type AM29LV800B with 8Mbits of storage 1Mx8 512Kx16 is at tached to the memory bus to store the following non volatile data e FPGA factory configuration e FPGA user configuration e application data The FPGA factory configuration is used to pro gram the flash memory via USB The factory configuration is loaded into the FPGA whenev er button S7 labelled PROGRAM is pressed The factory configuration occupies 256kB of memory and should not be altered The FPGA user configuration stores your FPGA design and is loaded into the FPGA during power up or whenever button S8 labelled RUN is pressed The user configuration occu pies 256kB of memory and the associated Trenz Electronic GmbH memory space should not be used for other pur poses than storing an FPGA configuration The application data space may be used to store various application dependent data e g firmware or data received from a measurement unit The application space provides 512kB of memory and may be read and written under ap plication control It is highly recommended using the download utility supplied with the Spartan lle Development Platform to program the flash memory Special care
10. ctronic GmbH User s Manual to the VG96 connector All circuitry is easily ac cessible when doing so and the boards may be assembled or de assembled in a matter of sec onds Figure 7 Expanding in line Finally the TE XC2Se together with the expan sion circuitry may be installed in an industry standard 19 rack with a VG96 backplane Among others suitable rack mount systems are provided from the following manufacturers e Schroff Propac line of cases or Europack Pro line of subracks www schroff de e Apw Diplomat line of 19 cases and case frames www apw com e Bopla Combicard Il line of card enclosure systems www bopla de FPGA Programming The FPGA on the TE XC2Se board is config ured from on board non volatile flash memory The flash memory in turn is programmed via Universal Serial Bus The concept involves two configurations both of them being stored in the flash memory The user configuration and the factory configuration After power up the user configuration is auto matically loaded into the FPGA The user con figuration holds the latest user defined bit stream which was downloaded to the board After pressing the PROGRAM button the facto ry configuration is loaded into the FPGA The Spartan lle Development Platform factory configuration implements a USB circuit ry which is used to re program the Flash memo ry with a new user configuration Once the Flash memory is re programm
11. ed the user may press RUN to load the updated user configuration into the FPGA Refer to Figure 8 for a simple flowchart of this procedure light D6 USB download load factory configuration power on reset load user K0 ouuuuuuy press user functionality PROGRAM light D7 Figure 8 Programming Flow The status of the board is indicated by two LEDs D6 and D7 Refer to Figure 9 to locate the programming buttons and the LEDs FPGA programming buttons ANGE Xe y lt xy KS lt oS A OG 2 X VX vie E Se gt Figure 9 Locate Programming Buttons The bitstreams loaded into the flash memory do not need be formatted by the Xilinx PROM File Formatter Instead the bitstreams are down loaded to the board exactly as being created by Xilinx bitgen The FPGA is configured in Slave Parallel Mode To do so the Start Up Clock must be set to CCLK Refer to the WebPACK ISE documentation for further details Once a bitstream is created the TE XC2Se download utility is used to download the bit Trenz Electronic GmbH User s Manual stream to the board The following steps need to be performed to do so e connect the board to the USB e load the factory configuration by pressing the PROGRAM button e run TEprog exe TEprog exe uses the following syntax TEprog bitfile TEprog a rawfile TEprog f bitfile When used without a parameter the bitstream contained in biffile is loaded to the user
12. he mechanical dimensions and connectors have been chosen to meet the fol lowing requirements e convenient for desktop applications e easy integration into rack mount systems e simple and reliable expansion The TE XC2Se board provides the following key features e 300K gate Spartan IIE FPGA e 8Mbit 1M x 8 512K x 16 of flash memory e AMbit 256K x 16 Bit of Static RAM e LCD with 2x16 characters and backlight e Universal Serial Bus interface e RS232 interface e VGA monitor output e LEDs DIP switches and push buttons e Up to 100 user I Os In addition to the TE XC2Se board the Spartan lle Development Platform contains the following components e complete FPGA design environment includ ing design entry and HDL synthesis e Ready to Use IP Modules encapsulating standard functionality e Documentation tutorials and comprehensive application notes Spartan lle Development Platform User s Guide Packing List Your Spartan lle Development Platform ships with the following items e TE XC2Se board e USB cable e CD ROM with FPGA design software soft ware utilities documentation and application notes Figure 2 Package Contents System Requirements The Development Platform and its accompany ing software tools have the following minimum system requirements e IBM PC or compatible e 128MBytes of RAM e SOOMBytes of disk space e USB port e Windows 98SE or Windows Millennium Windows 2000 o
13. ided e USB clock e User clock The USB clock provides a clock frequency of 48MHz as required to implement the USB inter face This clock cannot be altered to ensure Spartan lle Development Platform O Xilinx MicroBlaze 950 LUTs 15 32 bit RISC CPU USB Function Controller 380 LUTs 8051 microcontroller 2500 LUTs 40 including peripherals 8 bit RISC CPU 250 LUTS Table 2 XC2S300E Resource Usage proper operation of the USB download mecha nism under all circumstances The user clock provides a clock frequency of 25MHz suitable as dot clock for the VGA out put However the oscillator may be substituted by any other canned crystal oscillator depend ing on your application s requirements Refer to Figure 12 to locate the clock oscillator Figure 12 Locate User Clock Oscillator The Spartan lle FPGA provides a total of four dedicated clock input pins the remaining two clocks are routed to the VG96 connector Refer to the appropriate section for further details Button S9 labelled RESET is used to provide an asynchronous active low reset to the FPGA Refer to Figure 13 to locate the reset button Figure 14 illustrates the circuitry as simplified schematic diagram for quick reference Universal Serial Bus A USB transceiver is attached to the FPGA as shown in Figure 15 With the FPGA running the board s factory configuration the flash memory may be programmed via USB With the FPGA Trenz Electronic G
14. igh Performance CPLD Family Xilinx June 7 1999 Am29LV800B 8 Megabit 1M x 8 Bit 512 K x 16 Bit CMOS 3 0 Volt only Boot Sector Flash Memory AMD August 14 2000 IDT71V416S IDT71V461L 3 3V CMOS Static RAM 4 Meg 256K x 16 Bit IDT August 2000 Character Type LCD Module PC 160203 Product Specification Polytronix Inc June 2001 Trenz Electronic GmbH User s Manual e HD44780U LCD II Dot Matrix Liquid Crystal Display Controller Hitachi September 1999 e PDIUSBP11A Universal Serial Bus Transceiver Data Sheet Philips Semiconductors June 4 1999 e ISE 4 User Guide Xilinx July 2001 e Development System Reference Guide ISE 4 Xilinx July 2001 Revision History omen owe me Joem Table 7 Revisions History 14
15. ing a power supply with the wrong voltage or polarity may cause permanent dam age to the hardware Double check that power is applied to the correct pins of the VG96 con nector Expanding the System The TE XC2Se board is designed as an ex pandable system While the TE XC2Se board already provides a set of commonly used pe Spartan lle Development Platform ripherals your application may require other specialized circuitry which may be attached to the TE XC2Se board in various ways The expansion bus is an 8 bit bus which is suit able to attach standard microprocessor periph erals like timers or I O controllers The size of the circuit boards is relatively small but the ex pansion unit may provide I O connectors to the front panel Figure 5 details this Refer to the Ex pansion Bus section for a complete description of the available signals Figure 5 Connecting to the Expansion Port More complex circuitry may be attached to the TE XC2Se board as piggyback as Figure 6 de tails The advantage of doing so is that all sig nals routed to the VG96 connector are accessi ble the PCB may be up to full Euro format and the resulting system is very compact However when attaching a piggyback board access to the push buttons and the LCD display is difficult ST Figure 6 Expanding as Piggyback In case a compact design is not too crucial it is highly recommended to attach circuitry in line Trenz Ele
16. m your designs into the FPGA e example designs e documentation Copy the contents of the CD ROM to a directory of your choice You should make sure that the directory path does not contain blanks For convenience you should create a shortcut to the 7Eprog exe download utility on your desk top Hardware Setup USB powered Desktop System The TE XC2Se board may be powered from the USB yielding an extremely convenient desktop development system as no additional circuitry power supply or cabling is required Perform the following steps to use this setup e switch S1 to USB before connecting any cables Spartan lle Development Platform e connect the TE XC2Se board with the USB port of your host PC In this setup the switch S1 may also be used as a power switch avoiding the need to disconnect the TE XC2Se board from the USB Refer to Figure 3 to locate the switch S1 USB ports are specified to deliver a maximum current of 500mA Therefore you should either connect your TE XC2Se board directly to the host PC or use a self powered USB hub with its own power supply In rare occasions you may receive a warning message from your host PC stating that the maximum USB power consumption is exceed ed In these cases the power LED of the TE XC2Se does not light up If you encounter prob lems powering your board from the USB con sider using the externally powered desktop set Up Externally powered Desktop Sy
17. mbH User s Manual FPGA programming buttons L S9 RESET l USB clock _ B8 GCK2 user Clock FPGA Figure 14 Clock amp Reset Circuitry running a user configuration customized USB device functionality may be implemented in the FPGA if required by your application transceiver Figure 15 Universal Serial Bus The CON signal is used to switch the pull up re sistor in the D line By driving the CON pin to Vec or high impedance the USB connection may be established or closed under FPGA con trol This in turn triggers the host PC to re run USB enumeration The USB transceiver is wired for 12Mbps full Speed operation with the output driver in Mode 0 Consult the USB transceiver s data sheet for pin descriptions and signal waveforms Spartan lle Development Platform Memory Subsystem The memory subsystem consist of a 16 bit bus the memory bus with the following devices at tached to it e flash memory A 21 1 User s Manual e Static RAM Buttons switches and LEDs Figure 76 illustrates the memory subsystem As all devices share the same set of bus signals the access to the bus is mutually exclusive D 15 0 D15 J13 R14 A19 D14 J16 T14 A18 D43 J15 P10 A17 D42 K13 R10 A16 flash memory static RAM pil K12 T111 A15 512K x 16 bit 256K x 16 bit D10 L12 R11 A14 pal K16 P12 A13 pal K15 T12 A12 D7 P16 R12 A11 pel ue P11 A10 D5 L13 T13 A9 pal J4
18. r Windows XP Please note that the due to the missing USB support the TE XC2Se board is not compatible with Windows NT Software Setup Install the Design Software The TE XC2Se board may be programmed us ing Xilinx free WebPACK ISE package We rec ommend using version 4 2 or later The Web PACK ISE package is an integrated FPGA development software including design entry Verilog and VHDL synthesis and behavioral simulation In case you did not receive the software with your TE XC2Se board or you need to upgrade Trenz Electronic GmbH User s Manual to a more recent version visit the Xilinx web site at www xilinx com and download the WebPACK software with the following options e Design Entry e Spartan Fitter e Virtex Fitter e FPGA Programming Optionally you may also download the following modules e MXE Simulator Verilog FPGA e VHDL FPGA e StateCAD e HDL Bencher e XPower e FPGA Schematic Libraries The complete software package is also avail able as a single file download with the following size e WebPACK 4 2 FPGA installer 106MByte e MXE Simulator installer 39MByte When installing the software make sure the in stall path does not contain blanks It is recom mended to keep the default path suggested by the installer Install the Development Platform Tools In addition to the design software the compan ion CD ROM contains the following tools e download utility to progra
19. stem In case your system consumes more power than the USB ports deliver you may source your TE XC2Se board from an external regulated 5V power supply We recommend using an indus try standard computer supply Perform the fol lowing steps to do so e switch S1 to EXT POWER before connecting any other cables Connect the TE XC2Se board with the USB port of your host PC e connect the TE XC2Se board with your power supply See Figure 4 to locate the switch 1 Trenz Electronic GmbH User s Manual NL F ll i R Figure 4 Externally Powered Desktop System Using an external power supply is recommend ed in the following scenarios e you are working with a laptop and do not want to draw too much power from it e you are creating a complex and high speed design e you are planning to attach complex peripher als to the board e you are working with a bus powered USB hub which only provides 100mA of current per port Caution Using a power supply with the wrong voltage or polarity may cause permanent dam age to the hardware Double check your setup Rack mount System The TE XC2Se board perfectly integrates with industry standard 19 rack mount systems fea turing VG96 backplane connectors To do so perform the following steps e download your design to the user configura tion space using the USB powered desktop setup e switch S1 to EXT POWER e mount the TE XC2Se board into the rack Caution Us
20. ters o O store si attach onfig amp firmwarey O o 5 expansion gt add ons store g debug processing data O 4 gt iene l o O firmware E serial por VGA monitor s O output simple expand the user input Oo ise oo O system clocks reset power suppl Figure 10 TE XC2Se Block Diagram Programmer s Models This section describes the various building blocks of your TE XC2Se board and how they interact with the FPGA from a programmer s perspective To better serve this purpose sim plified schematics and block diagrams are used Figure 10 shows a block diagram of the TE XC2Se board Figure 11 helps to locate the most important components on the TE XC2Se board Connector So Figure 11 Locate Basic Components Trenz Electronic GmbH FPGA The XC2S300E 6FT256C FPGA from Xilinx Spartan llE family of devices is the main reposi tory of programmable logic on your TE XC2Se board The device provides the following key features e Up to 300 000 system gates e Up to 200MHz of system performance e Up to 98kBits of distributed RAM e 64kBits of dedicated block RAM e 182 User I Os To help measuring the capacity of the FPGA the Jable 2 summarizes the resource usage of some common building blocks Please note that these are only rough approximations which are highly dependent upon the actual applica tion Clocks amp Reset To provide clock signals to the FPGA two clock oscillators are prov
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