model 104-aio12-8 104-ai12-8 104-ao12-4 user
Contents
1. of interrupt Interrupt Enable Disable Software Controlled 32 Manual 104 AIO12 6 AI12 8 AO12 4 Appendix B 82C54 Counter Timer Operation The board contains one type 8254 programmable counter timer The 8254 consists of three independent 16 bit presettable down counters Each counter can be programmed to any count between 2 and 65 535 in binary format depending on the mode chosen The programmed value is a divisor the output frequency equals the input frequency divided by the programmed value In this manual these three counter timers are designated Counter Timer O Counter Timer 1 and Counter Timer 2 OPERATIONAL MODES The 8254 modes of operation are described in the following paragraphs to familiarize you with the versatility and power of this device For those interested in more detailed information a full description of the 8254 programmable interval timer can be found in the Intel or equivalent manufacturers data sheets The following conventions apply for use in describing operation of the 8254 Clock A positive pulse into the counter s clock input Trigger A rising edge input to the counter s gate input Counter Loading Programming of a binary count into the counter Mode 0 Pulse on Terminal Count After the counter is loaded the output is set low and will remain low until the counter decrements to zero The output then goes high and remains high until a new count is loaded into the counter A trigger enables the counter2. 12V DC DC converter and 4 20mA inputs P1 P2 LA TI 1 1 TELTET ITT 1 P6 EBIRO 9 5V JP21 12V UNIPOLARI S O JP20 12V BIPOLAR BIPOLAR lt 0 Rg E a 5V e Ei E BIRO 15 Z cg Q HELEN E BIPOLAR E lt Rg UNIPOLAR JO IRO 5 5VE IRO 4 alelo JIRQ 3 353 A9 A8 A7 BJAG BSJAS JP13 in P4 Figure 3 1 Option Selection Map 12 Manual 104 A1012 8 Al12 8 A012 4 DAC Range Set these jumpers to select the range of each DAC DACs A and C use the same layout similar to the ones on the top and DACs B and D use the same layout similar to the ones on the bottom Analog Output The card has four 12 bit analog output channels based on a pair of AD5343 dual D A chips Analog Input and Counter Timer The card has an Integrated Multiplexer and A D chip which has 8 single ended inputs Instrumentation amplifiers are populated on the standard board model for true differential readings The board may be ordered without those differential amplifiers installed as a factory option as well as offset circuitry and dropping resistors as a factory option to read 4 20mA signals The card also has three 16 bit counter timers based on an industry standard 8254 chip specifically a Harris Semiconductor 82054 The A D range is software selectable to 5V 0 5V 10V or 0 10V In bipolar modes the data is returned in standard two s complement form The gate clock and output pins f
3. 6 pin 30 Ch 7 pin 32 Use these pins with a Digital Multi Meter to measure the output of the amplifier which should correspond to the input signal level Do not connect any signal source to these output pins IDC 34 Pin Header Male ns Table 6 3 P2 Differential Analog Inputs es Senate amma 7 Cerf sem free Oa 28 Manual 104 A1012 8 Al12 8 A012 4 The 104 AlO12 8 can optionally be purchased for single ended use without the differential amplifiers In this case refer to the single ended pinout table following where pins 6 8 14 16 22 24 30 and 32 are the inputs In the case where the 104 AlO12 8 is fully populated with the differential amps here is a comparison of how the external signals are connected to the I O pins Table 6 5 S E and Diff Signal Source Connections to Standard Bd fTSingeEnded Differential Non inverting Differential Input Non inverting Input Inverting Differential Input Inverting Input Ground Ground The digital I O bits are arranged in an industry standard configuration Pin 1 can be identified by the square pad on the bottom of the board Also with the PC 104 connector closest to you pin 1 of P4 is on the bottom row closest to you 29 Manual 104 A1012 8 Al12 8 A012 4 IDC 50 Pin Header Male HLILILILID so aia LILID unajn LILI mm ae mm nar Table 6 6 P4 Digital I O Signal 5VFUSED iN Port A Bit O iN Port A Bit 1 iN
4. 8 AO12 4 If bit O DACTRIG is set at Base 16h writing to these registers will not update the DACs In this mode DAC updates occur simultaneously on all DACs only when the trigger event occurs D AC OUTPUT STAGE REFERENCE DAC OUTPUT OFFSET VOLTAGE BIPOLAR UNIPOLAR GAIN 0 5 0 10 CONNECTOR P3 Figure 5 5 D AC Output Stage 21 Manual 104 AIO12 6 AI12 8 AO12 4 Base Ch through Base Fh 8254 Counter Timer Please refer to Appendix B 8254 for detailed information on using the full features of the 8254 chip COUNTER TIMER 62054 CLK 0 GATE O OUTPUT 0 CONNLCIOR PT P2 CLK 1 CATE 1 OUTPUT 1 CIK2 GATE 2 QUIPUI 2 Figure 5 6 Counter Timer Block Diagram USING COUNTER 1 TO TRIGGER A D and D A CONVERSIONS In Mode 2 the Counter chip will generate a 1 microsecond negative going pulse at a programmed rate If bit 1 of the Timer Triggered Conversion Enable register base address 16h is set high the ADC chip will initiate conversions on the tick If bit O is set high the DAC chip will initiate conversions on the tick The ADC chip needs a command byte to begin a conversion This byte is stored in the ADC Command register at base 15h Note that only the lowest 5 bits are significant the top 3 bits will automatically be zeros All of the DACs present will be updated simultaneously Typically the user would configure the board t
5. HIGH when any DIO bit on Port C changes Bit 2 reflects the global interrupt enable written to Base 1h This is not an event and is not cleared when read 16 Manual 104 A1012 8 Al12 8 A012 4 Base 1h Interrupt Enables Interrupt Status READ A DC IRQ Change of Counter 1 Digital I O Digital I O IRQ Event always State IRQ IRQ Port C3 Port CO zero IRQ IRQ WRITE ADC IRQ Change of Counter 1 Digital I O Digital I O Global State IRQ IRQ Port C3 Port CO IRQ Enable Enable IRQ IRQ Enable Enable Enable All bits are active HIGH Reading this address accesses the Status register Writing to this address affects the Enables register Note that the register that s written to is not the same register that s read at this address Interrupts from this board can be shared The IRQ driver will pull the PC 104 interrupt line LOW for 500nS briefly drive it HIGH and then tri state After an interrupt is generated another won t be allowed until the IRQ has been cleared write to Base 0h and the data read for some event types If multiple enabled events occur for example an A D end of conversion and a Port C change of state and only one is cleared for example by reading the A D data and writing to Base 0h but not reading the COS data the other event will cause another interrupt Set bit 2 HIGH to enable interrupts from the board The default after system RESET is LOW Without this global enable set the board will not ge
6. ae edad eee SE en ee E 13 Analog OUUTE na is ase a AR added aus sates RE ADD RR RE PRO RE OIE oddest NR IDP ote 13 Analog Input and Counter Timer pp 13 ga 13 Mode 1 Digital Inversion JP2 JP1 JP8 and JP13 pp 13 E12V Source JP 20 and 2 13 DC DC Converter VR1 Factory Option pp 13 Chapter 4 Address SCICCHON me ee oes 14 Table T Hex Representation sus acto teen ne a a ho ets AA E a E da aa 14 Table 4 2 Standard Address Assignments for Computers pp 15 Chapter 5 Programming kt kt kk REE E REEL REE ELERS RENEE SEERE 16 Table 5 1 Register Address Map saia ee eo ad sa a a da 16 USING THE ANALOG TO DIGITAL CONVERTER 18 Figure 5 1 Differential Source to Differential Input pe 19 Figure 5 2 Single Ended Source to Differential Input rear reea rrenan renan 19 Figure 5 3 4 20mA Source to Differential Input e errar rrenan are ea er ERNE nene TERE E REE 19 Figure 5 4 Single Ended Input Stage pp 20 Figure 5 5 DIAC OMPpUEStage ne a tens EDEN ydet babe A DO as a 21 Figure 5 6 Counter Timer Block Diagram pp 22 USING COUNTER 1 TO TRIGGER A D and D A CONVERSIONS eee 22 Table 5 2 Control Register Bit Assignments pp 23 Chapter 6 Connector Pin Assignments eee 21 Table 6 1 PS DAG mn ee a E 21 Figure 6 1 P2 Analog Inputs P1 Timer Counter Arrangement Diagram pp 27 Table 6 2 PI P2 Split TMe Counter saias as a dd ao aa 28 Table 6 3 P2 Differential Analog INPUTS 0 a pesado e a R
7. from pin 6 DC DC Converter VR1 Factory Option This option is needed when the PC 104 bus J1 or P6 is not providing both 12V and 12V If these voltages are not supplied to the board the A D and D A circuitry will not operate properly 13 Manual 104 AIO12 6 AI12 8 AO12 4 Chapter 4 Address Selection The board base address on the I O bus is set by JUMPERS next to the PC 104 connector The jumper posts are marked A5 through A9 and A5 is the least significant bit of the address The base addresses can be selected anywhere within the I O address range 100 3FF provided that they do not overlap with other functions The FINDBASE software utility provided on CD with your board will help you select a base address that does not conflict with other assignments If in doubt refer to the following table for a list of standard address assignments In order to configure the desired address the hexadecimal address must be converted to a binary representation For example as illustrated below jumper selection corresponds to hex 2C0 or binary 10 110xxxxx The xxxxx represents address lines A4 through AO used on the board to select individual registers as described in the Chapter 5 Programming of the manual Hex FS Representation See ele Table 4 1 Hex Representation Please note that 1 out no jumper and 0 in jumper installed Review the Address Selection Table carefully before selecting the board a
8. select the read write mode of the selected counter Counter Read Write Function Counter Latch Command Read Write LS Byte Read Write MS Byte Read Write LS Byte then MS Byte MO0 M2 These bits set the operational mode of the selected counter BCD Set the selected counter to count in binary BCD 0 or BCD BCD 1 35 Manual 104 A1012 8 Al12 8 A012 4 READING AND LOADING THE COUNTERS If you attempt to read the counters on the fly when there is a high input frequency you will most likely get erroneous data This is partly caused by carries rippling through the counter during the read operation Also the low and high bytes are read sequentially rather than simultaneously and thus it is possible that carries will be propagated from the low to the high byte during the read cycle To circumvent these problems you can perform a counter latch operation in advance of the read cycle To do this load the RW1 and RW2 bits with zeroes This instantly latches the count of the selected counter selected via the SC1 and SCO bits in a 16 bit hold register An alternative method of latching counter s which has an additional advantage of operating simultaneously on several counters is by use of a readback command to be discussed later A subsequent read operation on the selected counter returns the held value Latching is the best way to read a counter on the fly without disturbing the counting process You can only rely on directly read
9. to start decrementing Mode 1 Retriggerable One Shot The output goes low on the clock pulse following a trigger to begin the one shot pulse and goes high when the counter reaches zero Additional triggers result in reloading the count and starting the cycle over If a trigger occurs before the counter decrements to zero a new count is loaded Thus this forms a re triggerable one shot In mode 1 a low output pulse is provided with a period equal to the counter count down time Mode 2 Rate Generator This mode provides a divide by N capability where N is the count loaded into the counter When triggered the counter output goes low for one clock period after N counts reloads the initial count and the cycle starts over This mode is periodic the same sequence is repeated indefinitely until the gate input is brought low Mode 3 Square Wave Generator This mode operates periodically like mode 2 The output is high for half of the count and low for the other half If the count is even then the output is a symmetrical square wave If the count is odd then the output is high for N 1 2 counts and low for N 1 2 counts Periodic triggering or frequency syntheses are two possible applications for this mode Note that in this mode to achieve the square wave the counter decrements by two for the total loaded count then reloads and decrements by two for the second part of the wave form Mode 4 Software Triggered Strobe This mode sets the output h
10. 2 8 A012 4 Chapter 2 Installation A printed Quick Start Guide QSG is packed with the board for your convenience If you ve already performed the steps from the QSG you may find this chapter to be redundant and may skip forward to begin developing your application The software provided with this PC 104 Board is on CD and must be installed onto your hard disk prior to use To do this perform the following steps as appropriate for your operating system Substitute the appropriate drive letter for your CD ROM where you see d in the examples below CD Installation The following instructions assume the CD ROM drive is drive D Please substitute the appropriate drive letter for your system as necessary DOS 1 Place the CD into your CD ROM drive 2 Type JL Je to change the active drive to the CD ROM drive 3 Type UNS U to run the install program 4 Follow the on screen prompts to install the software for this board Place the CD into your CD ROM drive The system should automatically run the install program If the install program does not run promptly click START RUN and type JUUNSCTA UL click OK or press fed WINDOWS 1 2 3 Follow the on screen prompts to install the software for this board LINUX 1 Please refer to linux htm on the CD ROM for information on installing under linux 10 Manual 104 AIO12 6 AI12 8 AO12 4 Installing the Hardware Before installing the board carefully read Chapter
11. 3 and Chapter 4 of this manual and configure the board according to your requirements The SETUP Program can be used to assist in configuring jumpers on the board Be especially careful with Address Selection If the addresses of two installed functions overlap you will experience unpredictable computer behavior To help avoid this problem refer to the FINDBASE EXE program installed from the CD The setup program does not set the options on the board these must be set by jumpers To Install the Board 1 99 Install jumpers for selected options and base address according to your application requirements as mentioned above Remove power from the PC 104 stack Assemble standoff hardware for stacking and securing the boards Carefully plug the board onto the PC 104 connector on the CPU or onto the stack ensuring proper alignment of the pins before completely seating the connectors together Install MO cables onto the board s I O connectors and proceed to secure the stack together or repeat steps 3 5 until all boards are installed using the selected mounting hardware Check that all connections in your PC 104 stack are correct and secure then power up the system Run one of the provided sample programs appropriate for your operating system that was installed from the CD to test and validate your installation f you are installing this board into a PC 104 Pin 0 stack that has the holes for Pin C19 and DE B10 blocked please cul these
12. 49 70 PRODUCTS INC 10623 Roselle Street San Diego CA 92121 858 550 9559 Fax 858 550 7322 contactus accesio com www accesio com MODEL 104 Al012 8 104 Al12 8 104 A012 4 USER MANUAL FILE M104 AlO12 8 D5a Notice The information in this document is provided for reference only ACCES does not assume any liability arising out of the application or use of the information or products described herein This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of ACCES nor the rights of others IBM PC PC XT and PC AT are registered trademarks of the International Business Machines Corporation Printed in USA Copyright 2001 2006 by ACCES I O Products Inc 10623 Roselle Street San Diego CA 92121 All rights reserved WARNING ALWAYS CONNECT AND DISCONNECT YOUR FIELD CABLING WITH THE COMPUTER POWER OFF ALWAYS TURN COMPUTER POWER OFF BEFORE INSTALLING A BOARD CONNECTING AND DISCONNECTING CABLES OR INSTALLING BOARDS INTO A SYSTEM WITH THE COMPUTER OR FIELD POWER ON MAY CAUSE DAMAGE TO THE I O BOARD AND WILL VOID ALL WARRANTIES IMPLIED OR EXPRESSED 2 Manual 104 A1012 8 A112 8 A012 4 Warranty Prior to shipment ACCES equipment is thoroughly inspected and tested to applicable specifications However should equipment failure occur ACCES assures its customers that prompt service and support will be available A
13. A112 8 A012 4 SV GROUND Figure 5 4 Single Ended Input Stage Base 2h 3h Read A D Data Base 3h 8 bit rarely used Base 2h 8 or 16 bit ms wlwlelelylelelelelelwle Reading base 2h as a 16 bit value will return the results of the most recently completed A D conversion Although it is possible to read the two bytes comprising the value separately it is not necessary and is slower The data is in two s complement format in Bipolar modes and is an unsigned 12 bit value in unipolar modes Base 4h 5h through Base Ah Bh DAC Output Base 5h 7h 9h Bh 8 bit rarely used Base 4h 6h 8h Ah pase 4h 6h 8h Ah eus wlwelwlwlglwlwlwlslelele_ No voltage can be generated by the DACs until the DAC reference enable register at Base 18h has been configured to enable the reference Every system reset disables the DAC reference until enabled by your software Writing a 16 bit value to the DAC Output register will update that DACs output to the new value Only the bottom 12 bits of the 16 bit data are significant decimal values O through 4095 The output voltage is given by Vout Gain Vref Counts 4096 Offset where Vref 4 096V and Counts the decimal equivalent of the binary code written to the DAC a number between 0 and 4095 Jumper Selected DAC Range 0 10V 10V On power up the DAC output values will be at the most negative for the selected range 20 Manual 104 AIO12 6 AI12
14. O Rd a EA 28 Table 6 4 P2 Single Ended Analog I puts assina es a a roret Dad 29 Table 6 5 S E and Diff Signal Source Connections to Standard Bd 29 Table 6 6 P Digital TO ene e ee 30 table 6 7 PO EI2V POWO ni ra ee Cae TU ee nr a o da a 31 Appendix A Technical Specifications 32 Appendix B 82C54 Counter Timer Operation pp 33 OPERATIONAL MODES sos paso or a a a 33 PROGRAMMING 00m a dc sane a enebarn De 35 READING AND LOADING THE COUNTERS eee erereeea ear ereeea ar ereeeaaanena 36 4 Manual 104 A1012 8 Al12 8 A012 4 Chapter 1 Introduction Flexibility The following functions are available in many configurations This gives the user the ability to specify exactly what s needed in order to minimize costs Interrupts from each circuit can eliminate the need for constant polling Interrupts are individually enabled or disabled via software A status register is provided to determine the interrupt source Analog In The Analog Inputs feature software programmable gain with ranges of 0 5V 0 10V 5V and 10V The configuration employs an instrumentation pre amplifier per channel which allows for true differential inputs 200V Common Mode Rejection and high input impedance The gain may be set at the factory to accommodate low level inputs from sensors Also any combination of channels may be factory configured to convert 4 20mA current This feature includes a built in offset to allow for full 12 bit resolution on the current i
15. Port A Bit 2 iN Port A Bit 3 CD Port A Bit 4 Port A Bit 5 Port A Bit 6 Port A Bit 7 CD Port B Bit 0 N Port B Bit 1 N Port B Bit 2 Port B Bit 3 N Port B Bit 4 N Port B Bit 5 Port B Bit 6 All even numbered pins are GROUND Port B Bit 7 Port C Bit O Port C Bit 1 Port C Bit 2 Port C Bit 3 Port C Bit 4 Port C Bit 5 Port C Bit 6 Port C Bit 7 Pin Signal 49 5VFUSED LI La EE LI EL BEZA 30 Manual 104 A1012 8 A112 8 A012 4 IDC 8 Pin Header Male 2 OM E 8 7 LM Table 6 7 P6 12V Power Normally the board takes 12V power from the PC 104 bus However it can be used on a PC 104 stack that does not provide 12V power by providing it here on P6 Note Pins 4 and 6 of P6 are connected to the corresponding lines of the PC 104 bus If your PC 104 stack provides 12V power it will be sourced on these pins 31 Manual 104 A1012 8 Al12 8 A012 4 Appendix A Technical Specifications Analog Inputs Conversion Frequency 100k Samples per Second Differential Input Impedance 2MegQ with pre amp S E w o pre amp Input Impedance 21kQ 16kQ uni bipolar Programmable Voltage Ranges 0 5V 0 10V 5V 10V 4 20mA as a factory option Preamplifier gain 1 standard up to 200 upon request Reference Output Voltage 4 096V 0 02V Common Mode Rejection Ratio 86dB typical Full Power Down Mode 1uA maximum Standby Power D
16. UT OUTPUT CTR 2 GATE e CLOCK e CPLD o o ADDRESS f IRQ LEVELS 3 7 9 12 14 15 PC 104 BUS Figure 1 1 104 A1012 8 Analog Multifunction Board Block Diagram 6 Manual 104 A1012 8 A112 8 A012 4 SE MAX197 P2 gt TYPICAL 8 PORTA G ds OF 12 ap gt 19 N 19 8 MUX 5 PORTB INPUTS 5 PORT C 8 cos ie P1 OUTPUT CTR O 4 HA GATE CLOCK 8 Nm OUTPUT y 2 a CTR 1 GATE 5 EO 4 EN 1MHz OUT cTR2 A GATE fr lt CLOCK ie CPLD o ADDRESS f RQL PC 104 BUS Figure 1 2 104 Al12 8 Analog Input Board Block Diagram 7 Manual 104 A1012 8 A112 8 A012 4 P4 PORT A 10 oe often MO 0101 N P3 A DACO DI DAC1L_ a 4 DAC2 31 DAC3 Ls P1 OUTPUT CTRO GATE _ CLOCK OUTPUT 5 CTR 1 io GATE 1MHz OUT 4 EM gt OUTPUT em e SE CPLD ADDRESS PC 104 BUS Figure 1 3 104 AO12 4 Analog Output Board Block Diagram 8 Manual 104 A1012 8 A112 8 A012 4 Ordering Guide e 104 AlO12 8 PC 104 12 Bit analog input output multi function board e 104 Al12 8 PC 104 12 Bit analog input multi function board e 104 A012 4 PC 104 12 Bit analog output multi function board Model Options e 4 20mA inputs with offset e Channel by channel pre amplifier gains of 1 100 e Single ended inputs e 5VDC only operation e 40 to 85 C extended operating temperature e Pull down resistors on digital I O lines 9 Manual 104 A1012 8 Al1
17. Value Digital MO Port A Digital I O Port B Digital I O Port C Write Function IRQ Clear Interrupt Enables A D Control Start Conversion D AC 1 LSB D AC 1 MSB D AC 2 LSB D AC 2 MSB D AC 3 LSB D AC 3 MSB D AC 4 LSB D AC 4 MSB Counter Timer O Load Value Counter Timer 1 Load Value Counter Timer 2 Load Value Counter Control Digital I O Port A Output Value Digital I O Port B Output Value Digital I O Port C Output Value 13h Digital MO Status Modes 1 amp 2 Digital I O Command Byte Tan Digital VO Buffer Control E AIDC Command en Counter Trigger Enables COS Status Clear COS Status P DAC Reference Enable also 4 20mA inputs Table 5 1 Register Address Map NOTE Applies only to Revision D and above Also used to enable 4 20mA input factory option Base Oh Board Status A DC Port C reserved reserved reserved IRQ reserved reserved EOC Change Enabled of State This register shows the state of the two events that can generate interrupts IRQs and the state of the global interrupt enable The interrupt enables disables have no affect on the events shown in this register All bits are active HIGH Also all of the event bits are latched when an event occurs its bit goes HIGH until this register is read Reading this register clears it Writing to this register clears IRQs see the description of IRQ enables Bit 7 goes HIGH when an A D conversion completes used for simple A D acquisition Bit 6 goes
18. counter data if the counting process is suspended while reading by bringing the gate low or by halting the input pulses For each counter you must specify in advance the type of read or write operation that you intend to perform You have a choice of loading reading a the high byte of the count or b the low byte of the count or c the low byte followed by the high byte This last is of the most general use and is selected for each counter by setting the RW1 and RWO bits to ones Of course subsequent read load operations must be performed in pairs in this sequence or the sequencing flip flop in the 8254 chip will get out of step The readback command byte format is reta er Poh CNT When is O latches the counters selected by bits CO C2 STA When is O returns the status byte of counters selected by CO C2 CO C1 C2 When high select a particular counter for readback CO selects Counter 0 C1 selects Counter 1 and C2 selects Counter 2 You can perform two types of operations with the readback command When CNT 0 the counters selected by CO through C2 are latched simultaneously When STA 0 the counter status byte is read when the counter I O location is accessed The counter status byte provides information about the current output state of the selected counter and its configuration The status byte returned if STA 0 is OUT Current state of counter output pin NC Null count This indicates when the last count loaded into th
19. d in the COS status register until read For example if Port C changed from 50 to 40 bit 4 has changed so the COS status register will contain the value 10 bit 4 high If Port C then changed to 60 bit 5 has changed so the COS status register will contain the value 30 bits 4 and 5 high If it s then read this 30 will be read and it will be cleared to 00 17 Manual 104 AIO12 6 AI12 8 AO12 4 Base 2h Write A D Control Start Conversion Device Device Acquisition Range Bipolar Channel Channel Channel Mode 1 Mode O Mode Unipolar Selection Selection Selection Bit Bit 2 Bit 1 0 USING THE ANALOG TO DIGITAL CONVERTER This circuit is based on a Maxim ADC chip Please refer to file MAX197 pdf in the CHIPDOCS directory on the CDROM A conversion begins when a control byte is written to the ADC The control byte contains five bit fields channel selection bipolar unipolar range acquisition mode and device mode Normally the acquisition mode and device mode bits will be zero The two bits in the device mode field select the clock source and the power state Before putting the ADC ina power down state a conversion with Normal Operation selected should be triggered The chip will remember this clock setting if the Standby power down mode is subsequently used The Standby state is entered after a conversion is complete there is no start up delay on the next conversion There is a 50mS start up delay befor
20. ddress If the addresses of two installed functions overlap you will experience unpredictable computer behavior If you have doubts concerning available addresses in your particular computer use the FINDBASE utility provided to determine available addresses 14 Manual 104 A1012 8 Al12 8 A012 4 EX RANGE 000 00F 020 021 040 043 060 06F 070 07F 080 09F OAO OBF 0C0 0DF OFO OF 1 OF8 OFF 170 177 1FO 1F8 200 207 238 23B 23C 23F 218 27F 2B0 2BF 2C0 2CF 2D0 2DF 2E0 2E7 2E8 2EF 2F8 2FF 300 30F 310 31F 320 32F 370 377 378 37F 380 38F 3A0 3AF 3B0 3BB 3BC 3BF 3C0 3CF 3D0 3DF 3E8 3EF 3FO 3F 7 3F8 3FF USAGE 8237 DMA Controller 1 8259 Interrupt 8253 Timer 8042 Keyboard Controller CMOS RAM NMI Mask Reg RT Clock DMA Page Register 8259 Slave Interrupt Controller 8237 DMA Controller 2 Math Coprocessor Math Coprocessor Fixed Disk Controller 2 Fixed Disk Controller 1 Game Port Bus Mouse Alt Bus Mouse Parallel Printer EGA EGA EGA GPIB AT Serial Port Serial Port Hard Disk XT Floppy Controller 2 Parallel Printer SDLC SDLC MDA Parallel Printer VGA EGA CGA Serial Port Floppy Controller 1 Serial Port Table 4 2 Standard Address Assignments for Computers 15 Manual 104 AIO12 6 AI12 8 AO12 4 Chapter 5 Programming The board uses 24 consecutive registers in I O space as follows Offset 02h 03h FO O FPS Counter Timer O Value Counter Timer 1 Value Counter Timer 2
21. e a conversion from the full power down state ES Normal Operation selects the external to the ADC clock mode a 2MHz clock frequency is applied 1 Internal clock mode not appropriate for this circuit unexpected events may occur if this mode is selected 0 Standby power down supply current will typically be 700uA Full power down supply current will be 120uA worst case The ADC has a Sample and Hold circuit controlled by the Acquisition Mode bit A control byte with this bit set low will select an acquisition interval of 3uS after which a conversion will begin A noisy signal may require more integration A control byte with this bit set high will start a user determined acquisition period conversion will begin when a 2 control byte is sent with bit 5 set low Bits O 1 and 2 must be the same value but the power state may be changed Bit 4 the range bit doubles the input voltage range when set Bit 3 selects bipolar mode when set Bipolar Unipolar The channel selection bits direct one of the eight analog inputs connected to the ADC s multiplexor to the Sample and Hold circuit Bits 2 1 and O make a binary value equal to the channel number 18 Manual 104 A1012 8 Al12 8 A012 4 12V Figure 5 1 Differential Source to Differential Input Single Ended 1 2V Signal Source Connected to a Differential Input 12V 12V Figure 5 3 4 20mA Source to Differential Input 19 Manual 104 A1012 8
22. e counter register has actually been loaded into the counter itself The exact time of load depends on the configuration selected Until the count is loaded into the counter itself it cannot be read RW1 RWO Read Write command M2 M1 MO Counter mode BCD BCD 0 is binary mode otherwise counter is in BCD mode 36 Manual 104 A1012 8 Al12 8 A012 4 If both STA and CNT bits in the readback command byte are set low and the RW1 and RWO bits have both been previously set high in the counter control register thus selecting two byte reads then reading a selected counter address location will yield 1st Read Status byte 2nd Read Low byte of latched data 3rd Read High byte of latched data After any latching operation of a counter the contents of its hold register must be read before any subsequent latches of that counter will have any effect If a status latch command is issued before the hold register is read then the first read will read the status not the latched value 37 Manual 104 A1012 8 A112 8 A012 4 Customer Comments If you experience any problems with this manual or just want to give us some feedback please email us at manuals accesio com Please detail any errors you find and include your mailing address so that we can send you any manual updates 6 PRODUCTS INC 10623 Roselle Street San Diego CA 92121 Tel 858 550 9559 FAX 858 550 7322 www accesio com 38 Manual 104 A1012 8 Al12 8 A012 4
23. ement Diagram P1 and P2 are combined into one 50 pin connector P1 starts where P2 ends P2 is the A D inputs and has 34 pins P1 is the closest to you and pin 1 is on the bottom row pin 41 in the combined arrangement See also the next page for the pinout of P2 Pins 35 40 are not used Pins 42 and 48 are the clock or event inputs for the Programmable Interval Timer counters Zero and Two and are pulled up to 5V through a 10K resistor 8MHz is the maximum frequency Pin 45 is an output of the 1MHz square wave applied to the clock input of counter one Pins 43 46 and 49 are the gate inputs and are pulled up to 5V through a 10K resistor Pull these inputs low to pause disable the counters Pins 44 47 and 50 are the counter outputs and can not tri state Either TTL or CMOS signal levels are acceptable at all inputs The 1MHz clock signal pin 45 is a CMOS output 2i Manual 104 A1012 8 A112 8 A012 4 Table 6 2 P1 P2 split Timer Counter The 4 096V reference on pin 1 is current limited by a 6200 resistor The Reference Adjust input is limited by a 510KQ resistor and may have from 1V to SV applied If the instrumentation amplifiers are present as in the standard model the inverting inputs are connected to ground through a 1M resistor The non inverting inputs are floating Also the instrumentation amplifier outputs are available at the Channel x Output pins Ch 0 pin 6 Ch 1 pin 8 Ch 2 pin 14 Ch 3 pin 16 Ch 4 pin 22 Ch 5 pin 24 Ch
24. esigned to support off the shelf software The cards are designed to use the PPI in mode O wherein There are two 8 bit ports A and B and two 4 bit ports C Hi and C Lo Any port can be configured as an input or an output Outputs are latched Inputs are not latched oo The PPI contains a control register This Write only 8 bit register is used to set the mode and direction of the ports At Power Up or Reset all I O lines are set as inputs The PPI should be configured during initialization by writing to the control registers even if the ports are going to be used as inputs Output buffers are automatically set by hardware logic according to the control register states The control register is located at base address 13h Bit assignments in this control register is as follows CM melon memso rimam Port C Hi C4 C7 1 Input 0 Output D5 D6 Mode Selection 01 Mode 1 00 Mode 0 1X Mode 2 Mode Set Flag amp Tristate 1 Active amp Tristate O Inactive Table 5 2 Control Register Bit Assignments 23 Manual 104 A1012 8 Al12 8 A012 4 Note In Mode O do not use the control register byte for the individual bit control feature The hardware uses the I O bits to control buffer directions on this card The control register should only be used for setting up input and output of the ports and enabling the buffer Programming Example The following programming example is provided as a guide to assist you i
25. igh and when the count is loaded the counter begins to count down When the counter reaches zero the output will go low for one input period The counter must be reloaded to repeat the cycle A low gate input will inhibit the counter This mode can be used to provide a delayed software trigger for initiating A D conversions 33 Manual 104 A1012 8 Al12 8 A012 4 Mode 5 Hardware Triggered Strobe In this mode the counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached The counter is retriggerable The output will not go low until the full count after the rising edge of the trigger 34 Manual 104 A1012 8 Al12 8 A012 4 PROGRAMMING On this card the 8254 counters occupy the following addresses hex Base Address C Read Write Counter O Base Address D Read Write Counter 1 Base Address E Read Write Counter 2 Base Address F Write to Counter Control register The counters are programmed by writing a control byte into a counter control register The control byte specifies the counter to be programmed the counter mode the type of read write operation and the modulus The control byte format is as follows SC0 SC1 These bits select the counter that the control byte is destined for Program Counter 0 A Program Counter 1 1 0 Program Counter 2 1 1 Read Write Cmd See Chapter on READING AND LOADING THE COUNTERS RWO RW1 These bits
26. ions Note the value loaded in Base 15h is used as the A D control byte for counter triggered A D conversions If you wish to acquire timed data from more than this single channel you must write a new A D control value to Base 15h before the next trigger output from CTR 1 Base 17h COS Status Clear COS Status Bit PC 7 COS PC 6 COS PC 5 COS PC 4 COS PC 3 COS PC 2 COS PC 1 COS PC 0 COS Each bit of this register indicates Has this bit of Port C changed since last checked when read The memory of COS events is cleared by reading the register 25 Manual 104 A1012 8 A112 8 A012 4 That is if you reset the board toggle bit n of Port C any number of times and read this register bit n of this register will be set high 1 If you then toggle any other bit of Port C any number of times and read this register only the new bit will be set high Base 18h DAC Reference Enable also used for 4 20mA input Factory option DAC Unused Reference Enable Bit O is set to zero at every board reset In order to generate voltages with the DACs you must first set Bit O write 1 to Base 18h If your board has the Factory option of 4 20mA inputs the DAC Reference Voltage is used for the offset of the 4 20mA signals instead of the A D reference Therefore you must set Bit O once at every board start up prior to reading the 4 20mA input signals At power on or reset all DACs will be generating a near ground voltage o
27. ll equipment originally manufactured by ACCES which is found to be defective will be repaired or replaced subject to the following considerations Terms and Conditions If a unit is suspected of failure contact ACCES Customer Service department Be prepared to give the unit model number serial number and a description of the failure symptom s We may suggest some simple tests to confirm the failure We will assign a Return Material Authorization RMA number which must appear on the outer label of the return package All units components should be properly packed for handling and returned with freight prepaid to the ACCES designated Service Center and will be returned to the customer s user s site freight prepaid and invoiced Coverage First Three Years Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with equipment shipment Following Years Throughout your equipment s lifetime ACCES stands ready to provide on site or in plant service at reasonable rates similar to those of other manufacturers in the industry Equipment Not Manufactured by ACCES Equipment provided but not manufactured by ACCES is warranted and will be repaired according to the terms and conditions of the respective equipment manufacturer s warranty General Under this Warranty liability of ACCES is limited to replacing repairing or issuing credit at ACCES discretion for an
28. llows the lines to be pulled high by the onboard pull ups Software would then initialize the outputs and re enable the buffer s preventing a low going glitch from occurring To re enable the buffers simply write the control byte a 2 time but with Bit 7 cleared That is if and only if you are in TRISTATE mode every write to Base 13h should be followed after writing an initial output value to every port in output mode by another write to Base 13h containing the same command byte AND 0x7F Base 15h A D Counter Triggered Command Byte Bipolar nani Unused Range p Selection Bit Unipolar 2 The value written here is stored for use when starting conversions via the 8254 Counter 2 trigger output see Base 15h The format of the data in bits 4 through O is identical to Base 2 and the top 3 bits are handled internally simply write Os to these bits Note The channel selected here will be used each time the 8254 counter 2 starts an A D conversion Base 2h is ignored for this mode of operation Base 16h Counter Trigger Enables Bit 4 Unused ADTRIG DACTRIG Write to this register to enable Counter 1 to generate trigger events for the A D and or DAC circuit Each negative going pulse from the output of Counter 1 will be used as a trigger for enabled events Set Bit 1 ADTRIG to enable the output of counter 1 to generate Start A D Conversion triggers Set Bit O DACTRIG to use the output to trigger DAC Convers
29. n developing your working software In this example the PPI base address is 2D0 hex and I O lines of Port O are to be setup as follows port A Input port B Output port C hi Input port C lo Output Configure bits of the Control Register as pacea oro Pore ou pelofo gsleso pofo fe This corresponds to 98 hex If the PPI base address is 2D0 hex use the BASIC OUT command to write to the control register as follows 10 BASEADDR amp H2D0 2U OUT BASEADDR 3 H98 To read the inputs at Port A and the upper nybble of Port C use the BASIC INPUT command 30 X INP BASEADDR Read Port A 40 Y INP BASEADDR 2 16 Read Port C Hi To set outputs high 1 at Port B and the lower nybble of Port C 50 OUT BASEADDR 1 amp HFF Tu on ali Port B Dits 60 OUT BASEADDR 2 amp HF MPU On a prts Or Port CG 6 This circuit can as a factory installed option operate in 8255 programmed I O Modes 1 and 2 Note that if Bit 6 is set then Bit 5 is unused 24 Manual 104 AIO12 6 AI12 8 AO12 4 Base 14h Digital I O Buffer Control unused TST If the TST bit bit 0 is set the TRISTATE mode is entered Clear bit O to exit TRISTATE mode When software configures an 8255 port to be an output the lines will immediately all go low odd quirk of the chip Since most control signals are active low this is considered sub optimal When in TRISTATE mode this board will tri state the associated buffer when it becomes an output This a
30. nerate interrupts of any kind If an interrupt has been generated by the board this bit will be HIGH when read Set bit 7 HIGH to enable interrupts from the A DC When read bit 7 is HIGH if the A DC generated an interrupt that was not yet cleared Read Base 2h and Base 3h to get the A D data and write to Base 0h to clear the board s interrupt so it can generate another Set bit 6 HIGH to enable interrupts from the Change of State detection circuit at DIO Port C When read bit 6 is HIGH if a change of state generated an interrupt that was not yet cleared Read Base 17h to get the COS data and write to Base 0h to clear the board s interrupt so it can generate another Set bit 5 HIGH to enable interrupts from falling edges of Counter 1 When read bit 5 is HIGH if the counter generated an interrupt that was not yet cleared Write to Base 0h to clear the board s interrupt so it can generate another Set bits 4 and 3 HIGH to enable interrupts from rising edges of DIO Port C bits 3 and 0 respectively When read bit 4 is HIGH if this bit generated an interrupt that was not yet cleared Write to Base Oh to clear the board s interrupt so it can generate another Port C Change Of State COS If any bit of Port C changes state this event is noted in the board status register Base 0h an interrupt is generated if enabled at Base 1h and the specific bit that changed is noted in the COS status register Base 17h Multiple changes are accumulate
31. nly because the DAC reference is disabled The DAC chips themselves are trying to generate random voltages If you simply re enable the DAC reference after a reset your output voltages will be random To avoid this write known values to all DACs via the Base 4h through Base Bh registers before enabling the DAC Reference here Note this feature exists only on boards with Revision D and above 26 Manual 104 AlO12 8 Al12 8 AQ012 4 Chapter 6 Connector Pin Assignments IDC 10 Pin Header Male 2 eh ey 10 Table 6 1 P3 DAC Pin 2 Pin 4 Pin 6 Pin 8 Pin 10 DAC A Output DAC B Output 4 096V Reference Output DAC C Output DAC D Output Pin 1 Pin 3 Pin 5 Pin 7 Pin 9 Ground Ground Ground Ground Ground Each DAC output can drive up to 10mA Due to a limitation of the optional DC DC converter power supply the total drive of these four signals should be kept below 20mA If 12V power is supplied at the ISA bus connectors or at P6 there isn t a cumulative drive current limit Each DAC output has three configuration jumpers If the jumper labeled DAC x 5V where x is either A B C or D is in place the range is limited to 5V 0 5V or 5V If the jumper labeled UNIPOLAR is in place the range is limited to 0 5V or 0 10V If the jumper labeled BIPOLAR is in place the range is either 5V or 10V Note that UNIPOLAR and BIPOLAR are mutually exclusive 39 Figure 6 1 P2 Analog Inputs P1 Timer Counter Arrang
32. nput The board may be ordered without the instrumentation amplifiers as a factory option if the inputs are from single ended sources Analog Out Output ranges of 0 5V 0 10V 5V and 10V are field selectable with jumpers Note that four conversions may take place at once Digital I O The circuit uses an 82C55A Programmable Peripheral Interface Ports A and B 16 lines are buffered and all 24 lines have pull up resistors to 5V As a factory option lines can be pulled down to ground Port C is not buffered and should normally be used only as inputs Port C also features Change of State detection Counter Timer The circuit uses an 82C54 Programmable Interval Timer 3 sixteen bit counter timers The user has access to each counter timer s gate clock and output signals The output of counter one can be used to generate an interrupt The Counter Timer can be used to initiate A D conversions for more precise timing between samples thus eliminating jitter which can occur when initiating conversions via software command The software package supports counting events frequency output pulse and frequency measurement 5 Manual 104 A1012 8 Al12 8 A012 4 P4 PORTA gt S E PORT B porte Oyo MAX197 g x O P2 a a gt P3 DAC 0 A 8 u TO D DAC1 gt 8 MUX ne 3 OUTPUTS INPUTS 4 DAC2 3 DAC3 gt OUTPUT CTR O GATE CLOCK 3 OUTPUT CTR 1 GATE gt 1MHz O
33. o generate an interrupt on the tick from counter 1 the user would also enable DAC conversions triggered by the same tick Base 10h 11h 12h Digital I O Port Bit 7 Port Bit 6 Port Bit 5 Port Bit 4 Port Bit 3 Port Bit 2 Port Bit 1 Port Bit 0 Each of these three registers contains one 8 bit digital value Base 10h is the value associated with 8255 Port A Base 11h is Port B and Base 12h is Port C also known as Chi Clo 22 Manual 104 A1012 8 A112 8 A012 4 Reading these registers will return either the current state of the inputs or the current state of the outputs depending on the current mode of each port Base 13h Digital I O Command Byte Mode Set Group A Group A Port A Port C Upper Group B Port B Port C Lower Flag Mode Mode Direction Direction Mode Direction Direction 1 Active 1 Mode 2 1 Mode 1 1 Input 1 Input 1 Mode 1 1 Input 1 Input O use Bit5 0 Mode O O Output O Output O Mode O O Output O Output This circuit is based on an 82C55A chip Please refer to file 82C55 pdf in the CHIPDOCS directory On power up or on Reset the circuit will be in the mode O input state That is ports A and B each 8 bits and ports Chi and Clo each 4 bits will be readable and any floating pins at connector P4 will be high To change Port A and Port B I O configuration there are two modes In the default mode the buffers direction is automatically set by the command byte This mode is d
34. or each counter are exposed on the connector Counter 2 s output can generate interrupts Counter 1 s clock has a 1MHz input These counter timers can be used for frequency generation frequency measurement pulse width measurement and event counting and can be cascaded together for larger counts Digital I O The card has 24 bits of digital I O based on an industry standard 8255 chip specifically a Harris Semiconductor 82C55A All 8255 modes are supported by the card with jumpers controlling the inversions necessary for Mode 1 operation Ports A and B are buffered Port C features change of state detection All pins have pull ups to 5V Mode 1 Digital Inversion JP2 JP1 JP8 and JP13 These jumpers invert four bits of Port C of the 8255 digital I O chip on the card This is intended for 8255 Mode 1 operation inverting bits 1 and 2 allows Port A to be a Mode 1 port talking to an uninverted Mode 1 port and inverting bits 5 and 6 does the same with Port B The inverters treat bits 1 JP1 and 5 JP8 as outputs and bits 2 JP2 and 6 JP13 as inputs which is how they re used in 8255 Mode 1 When uninverted these bits can freely be inputs or outputs 12V Source JP20 and JP21 Set these jumpers to select where the card gets 12V reference power In the left position they re taken from the PC 104 connector In the right position they re taken from P6 the eight pin connector just below these jumpers 12V is taken from pin 4 and 12V
35. own Mode 400uA maximum Trigger Source s Software selectable for program command or programmable timer Gain Temperature Coefficient typical 6 ppm C bipolar 8ppm C unipolar Common Mode Voltage 200V Integral Nonlinearity 1 LSB maximum Analog Outputs we vate Voltage Ranges 0 5V 0 10V 5V 10V Relative Accuracy 2 LSB typical Trigger Source s Software selectable for program command or programmable timer Digital Input Output Programmable Peripheral Interface 820554 Channels TOKQ to SV optional to ground Buffered Channels 6 ports A c B Ca amp Source Current 64mA amp 32mA Un Buffered Channels 8 port C Sink amp Source Current 2 5mA direct from 82C55A Modes supported mode 0 1 and 2 factory options Change of State Detection 8 inputs port C Counter Timer Peripheral Interface Timer Type 82C54 3 x 16 Bit down counters Clock Frequency Output Inputs Outputs Fully Buffered Native Modes Pulse on terminal count retriggerable one shot rate generator square wave generator software triggered strobe hardware triggered strobe Software support Event counter frequency output frequency and pulse measurement General Power Required 5V 40mA 12V 30mA 12V 30mA Environmental Operating O to 70 C standard 5V 240mA w optional 12V DC DC conv Temperature 40 to 85 C optional Interrupt Requests Eleven channels IRQ 3 7 9 12 14 15 Interrupt Status Register Indicates source s
36. two pins as shown from the solder side of this board It is not necessary to block the holes on the component side of the board re LA Pin 1 Figure 2 1 PC 104 Key Information 11 Manual 104 A1012 8 A112 8 A012 4 Chapter 3 Option Selection Refer to the Setup Program on the provided CD for details of selecting appropriate options for your application Jumpers are available on the board to configure the following functions 1 Base address jumpers labeled A5 through A9 see Chapter 4 for details 2 IRQ level 3 DAC output voltage ranges 4 Mode 1 Digital Inversion 82C55 on Digital I O 5 12V Power Options JP20 JP21 As Factory Options you can also order the board e for use with single ended inputs without instrumentation amplifiers e configured for any number of 4 20mA inputs up to 8 e configured with pull down resistors on digital I O lines e witha DC DC converter installed so the board operates on 5V only e to operate in an industrial temperature range Your board also may be populated with any combination of functionality such as Digital I O with four DAC channels or Analog Inputs with 82C54 Counter Timers This is indicated by a label on the PC 104 connector that has a part number ending in SOX where X indicates a unique number identifying a special configuration The standard board has most of the functionality that the board is capable of with the exception of the following factory installed options
37. y products which are proved to be defective during the warranty period In no case is ACCES liable for consequential or special damage arriving from use or misuse of our product The customer is responsible for all charges caused by modifications or additions to ACCES equipment not approved in writing by ACCES or if in ACCES opinion the equipment has been subjected to abnormal use Abnormal use for purposes of this warranty is defined as any use to which the equipment is exposed other than that use specified or intended as evidenced by purchase or sales representation Other than the above no other warranty expressed or implied shall apply to any and all such equipment furnished or sold by ACCES 3 Manual 104 A1012 8 Al12 8 A012 4 Table of Contents Chapter 1 Introduction 4 5 IE 5 Analog I ee O Og E E a 5 Analog sas Eiras re PRR DS nO a eT EN Br Sa nee mre me CN ES NE ee ET ease eee 5 Digtal Or ee a a a N 5 Counter TIMER uaaa a ce dec See a a A A A N 5 Figure 1 1 104 AlO12 8 Analog Multifunction Board Block Diagram pp 6 Figure 1 2 104 Al12 8 Analog Input Board Block Diagram pp T Figure 1 3 104 AO12 4 Analog Output Board Block Diagram pp 8 Grassrngelges a CRS Me rotted aun Nee aD aon en che O ene SEALS 9 MOC bt 9 Chapter 2 INS CAM ACO Ns e O a SEE 10 Figure 2 1 PC 104 Key Information ssa a DS aie nee i ES OSS ae inde 11 Chapter 3 Option SCICCHON aaa assis is DDD AD 12 Figure 3 1 Option Selection Map pp 12 DAC Range a te a
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