Home

Infineon C166 Family Instruction Set Manual

1. Table 5 Condition Code Encoding Condition Code Test Description Encoding c Mnemonic cc cc_UC 1 1 Unconditional OH cc_Z Z 1 Zero PH cc NZ Z 0 Not zero 3H cc_V V 1 Overflow 44 cc_NV V 0 No overflow 5H cc_N N 1 Negative 6H cc_NN N 0 Not negative 74 cc_C C 1 Carry 8H cc_NC C 0 No carry 9H cc_EQ Z 1 Equal 2H cc_NE Z 0 Not equal 3H cc_ULT C 1 Unsigned less than 8H cc_ULE ZvC 1 Unsigned less than or equal FH cc_UGE C 0 Unsigned greater than or equal 94 cc_UGT ZvC 0 Unsigned greater than Ey cc_SLT NOV 1 Signed less than Cy cc_SLE Zv N V 1 Signed less than or equal BH cc SGE N V 0 Signed greater than or equal Dy cc_SGT Zv N V 0_ Signed greater than Ay cc_NET ZvE 0 Not equal AND not end of table 14 User s Manual 38 V2 0 2001 03 o C166 Family Infineon TE Sass Detailed Description Peculiarities of the ATOMIC and EXTended Instructions These instructions ATOMIC EXTR EXTP EXTS EXTPR EXTSR disable standard and PEC interrupts and class A traps during a sequence of the following 1 4 instructions The length of the sequence is determined by an operand op1 or op2 depending on the instruction The EXTended instruction additionally change the addressing mechanism during this sequence see detailed instruction description The ATOMIC and EXTended instructions become active immediately i e no interrupt PEC request or Clas
2. E Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes CALLR rel BB rr 2 61 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set CALLS Syntax Operation Description Condition Flags Addressing Modes User s Manual Detailed Description Call Inter Segment Subroutine CALLS CALLS 0p1 op2 SP lt SP 2 SP lt CSP SP lt SP 2 SP lt IP CSP lt op1 IP op2 A branch is taken to the absolute location specified by op2 within the segment specified by op1 The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address to the calling routine The previous value of the CSP is also placed on the system stack to insure correct return to the calling segment E Z V C N Not affected Not affected Not affected Not affected z O lt s NM Not affected Mnemonic Format Bytes CALLS seg caddr DA SS MM MM 4 62 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CM P Integer Compare Syntax CMP op1 op2 Operation 0p1 op2 Data Types WORD Description Detailed Description CMP The source operand specified by op1 is compared to the source opera
3. E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Setif result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes AND Rw RWm 60 nm 2 AND Rw Rw 68 n 10ii 2 AND Rw Rw 68 n 11ii 2 AND Rw data3 68 n O 2 AND reg data16 66 RR 4 AND reg mem 62 RR MM MM 4 AND mem reg 64 RR MM MM 4 45 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set ANDB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Logical AND ANDB ANDB op1 op2 0p1 lt op1 a op2 BYTE Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E Z V C N E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Setif result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ANDB Rb Rb 61 nm 2 ANDB Rb Rwi 69 n 10ii 2 ANDB Rb Rw 69 n 11ii 2 ANDB Rb data3 69 n O 2 ANDB reg data8 6
4. 1 The Extended Special Function Register ESFR area is not available in the SAB 8XC166 W devices Users Manual 132 V2 0 2001 03 o C166 Family Infineon TE Addressing Modes Rw Rb Specifies direct access to any GPR in the currently active context register bank Both Rw and Rb require four bits in the instruction format The base address of the current register bank is determined by the content of register CP Rw specifies a 4 bit word GPR address relative to the base address CP while Rb specifies a 4 bit byte GPR address relative to the base address CP reg Specifies direct access to any E SFR or GPR in the currently active context register bank reg requires eight bits in the instruction format Short reg addresses from 004 to EF4 always specify E SFRs In that case the factor A equates 2 and the base address is 00 FEOOw for the standard SFR area or 00 F000 for the extended ESFR area reg accesses to the ESFR area require a preceding EXT R instruction to switch the base address not available in the SAB 8XC166 W devices Depending on the opcode of an instruction either the total word for word operations or the low byte for byte operations of an SFR can be addressed via reg Note that the high byte of an SFR cannot be accessed via the reg addressing mode Short reg addresses from FO to FF4 always specify GPRs In that case only t
5. Not affected Not affected Not affected Not affected zZz O lt s NM Not affected Mnemonic Format Bytes SCXT reg data16 C6 RR 4 SCXT reg mem D6 RR MM MM 4 119 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set SHL Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Shift Left SHL SHL op1 op2 count lt op2 C lt 0 DO WHILE count 0 C 0p145 op1 op1n 1 n 1 15 opto 0 count count 1 END WHILE WORD Shifts the destination word operand op1 left by as many times as specified by the source operand op2 The least significant bits of the result are filled with zeros accordingly The MSB is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Z V C N 0 0 S ig Always cleared Set if result equals zero Cleared otherwise Always cleared O lt NM The carry flag is set according to the last MSB shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SHL Rwy RWm 4C nm 2 SHL Rw data4 5C n 2 120 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set SHR Syntax Ope
6. Mnemonic SHR Rw RWm SHR Rw data4 122 Detailed Description SHR Format Bytes 6C nm 2 7C n 2 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set SRST Syntax Operation Description Note Condition Flags Addressing Modes User s Manual Detailed Description Software Reset S RST SRST Software Reset This instruction is used to perform a software reset A software reset has a similar effect on the microcontroller as an externally applied hardware reset To insure that this instruction is not accidentally executed it is implemented as a protected instruction E Z V C N 0 0 0 0 0 Not affected Not affected Not affected Not affected z O lt NMN om Not affected Mnemonic Format Bytes SRST B7 48 B7 B7 4 123 V2 0 2001 03 TT C166 Family Infineon TE Sas Detailed Description SRVW DT Service Watchdog Timer SRVW DT Syntax SRVWDT Operation Service Watchdog Timer Description This instruction services the Watchdog Timer It reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence Once this instruction has been executed the watchdog timer cannot be disabled Note To insure that this instruction is not accidentally executed it is implemented as a protected instruction Condition E Z V C N Flags E Not affected Z Not affecte
7. count 1 END WHILE WORD Rotates the destination word operand op1 right by as many times as specified by the source operand op2 Bit 0 is rotated into Bit 15 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Z V C N 0 S S Always cleared Z Set if result equals zero Cleared otherwise Set if in any cycle of the rotate operation a 1 is shifted out of the carry flag Cleared for a rotate count of zero C The carry flag is set according to the last LSB shifted out of op1 Cleared for a rotate count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ROR Rw RWm 2C nm 2 ROR Rw data4 3C n 2 118 V2 0 2001 03 TT e e Infineon technologies C166 Family Instruction Set SCXT Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Switch Context SCXT SCXT op1 op2 tmp1 op tmp2 op2 SP lt SP SP tmp1 op1 tmp2 WORD Used to switch contexts for any register Switching context is a push and load operation The contents of the register specified by the first operand op1 are pushed onto the stack That register is then loaded with the value specified by the second operand op2 E Z V Cc N
8. E Z V C N E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise 95 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set MOV Addressing Modes User s Manual continued Mnemonic MOV Rw RWm MOV Rw data4 MOV reg data16 MOV Rw RW MOV Rw RWm MOV Rwm Rw MOV Rw Rwy MOV Rw RW MOV Rwp RW MOV Rwy Rwm MOV Rw Rw data16 MOV Rw data16 Rw MOV Rw mem MOV mem Rw MOV reg mem MOV mem reg 96 Detailed Description Format FO nm EO n E6 RR A8 nm 98 nm B8 nm 88 nm C8 nm D8 nm E8 nm D4 nm C4 nm 84 On MM MM 94 0n MM MM F2 RR MM MM F6 RR MM MM MOV Bytes RRR RRBRNHNNNNNNAND ND V2 0 2001 03 o C166 Family Infineon TE Sass Detailed Description MOVB Move Data MOVB Syntax MOVB 0op1 op2 Operation op1 lt op2 Data Types BYTE Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the condition codes are updated accordingly
9. Missing or existing parentheses signify whether the used operand specifies an immediate constant value an address or a pointer to an address as follows opX opX opX Specifies the immediate constant value of opX Specifies the contents of opX Specifies the contents of bit n of opX Specifies the contents of the contents of opX i e opX is used as pointer to the actual operand The following operands will also be used in the operational description User s Manual CP CSP MD MDL MDH PSW SP SYSCON C V SGTDIS count tmp 0 1 2 Context Pointer register Code Segment Pointer register Multiply Divide register 32 bits wide consists of 16 bit registers MDH and MDL Multiply Divide Low and High registers both 16 bits wide Program Status Word register System Stack Pointer register System Configuration register Carry condition flag in register PSW Overflow condition flag in register PSW Segmentation Disable bit in register SYSCON Temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the shift or rotate operation Temporary variable for an intermediate result Constant values due to the data format of the specified operation 33 V2 0 2001 03 eo nfineon C166 Family technologies Instruction Set Detailed Description Data Types This part specifies the particular data type according to the instruction Basically the
10. Operation If the target operand op1 features bit protection only the bits marked by a 1 in the mask operand op2 will be updated E Z V C N 0 0 0 i Always cleared Set if the word result equals zero Cleared otherwise Always cleared Always cleared 2 O lt s NM Set if the most significant bit of the word result is set Cleared otherwise Mnemonic Format Bytes BFLDL _bitoffg maskg data8 0A QQ 4 53 V2 0 2001 03 TT C166 Family Infineon TE Sass Detailed Description BMOV Bit to Bit Move BMOV Syntax BMOV _ op1 op2 Operation op1 lt op2 Data Types BIT Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly Condition E Z V C N Flags 0 B 0 0 B Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared Always cleared N Contains the previous state of the source bit Addressing Mnemonic Format Bytes Modes BMOV bitaddrz z bitaddra 4A QQ ZZ qz 4 User s Manual 54 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Detailed Description BMOVN Bit to Bit Move and Negate BMOVN Syntax BMOVN op1 op2 Operation op1 0p2 Data Types BIT Description Moves the complement of a single bit from the
11. 143 Branch execution times corrected 148f Keyword index introduced We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Ea TT e z nfineon C166 Family technologies Instruction Set Table of Contents Page 1 Introduction 644 5 8445 4b 5245 45 66054 8559444949 ennen kreere en 1 2 OvervieWS 0 0 3 3 Summary Fives ths cere ueee ese K ERR EE DERESE ETENE eee Rees 8 3 1 Data Addressing Modes 1 1 eee es 8 3 2 Branch Target Addressing Modes 1 eee ee 8 3 3 Multiply and Divide Operations 0000 c eee ee 9 3 4 Extension Operations 1 ees 9 3 5 Branch Condition Codes ww ees 9 4 ENCOGING 606s ae bem douse eee wha ye RUN WARE GS Renee es 22 5 Detailed Description 0 0 00 cece 31 6 Addressing Modes 00000 cece ee 132 6 1 Short Addressing Modes 2000 cece eee eee eee 132 6 2 Long Addressing Mode 2 ec2siccy denen ee eee ennen nen 134 6 3 Indirect Addressing Modes 0 0c cece eee ees 135 6 4 DPP Override Mechanism 0 cece eects 137 6 5 Constants within Instructions s sssaaa 0000 eee eee 138 6 6 Instruction Range irang2 2ssaceeweews oe eee ee eA ee ee eee
12. Condition E Z V C N Flags Fi p E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise User s Manual 97 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Detailed Description MOVB continued MOVB Addressing Mnemonic Format Bytes Modes MOVB Rb Rbm F1 nm 2 MOVB Rb data4 E1 n 2 MOVB reg data8 E7 RR xx 4 MOVB _ Rb Rwm A9 nm 2 MOVB Rb Rwm 99 nm 2 MOVB Rw Rb B9 nm 2 MOVB Rw Rb 89 nm 2 MOVB Rw Rwy C9 nm 2 MOVB Rw RW D9 nm 2 MOVB Rw Rwm E9 nm 2 MOVB _ Rb Rw data16 F4 nm 4 MOVB Rw data16 Rb E4 nm 4 MOVB Rw mem A4 On MM MM 4 MOVB mem Rw B4 On MM MM 4 MOVB reg mem F3 RR MM MM 4 MOVB mem reg F7 RR MM MM 4 User s Manual 98 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set MOVBS Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Move Byte Sign Extend MOVBS 0p1 op2 low byte op1 op2 IF op27 1 THEN high byte op1 FFy ELSE high byte op1 lt 004 END IF WORD BYTE Detailed Description MOVBS Moves and
13. Mnemonic Format Bytes PCALL reg caddr E2 RR MM MM 4 108 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set POP Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Pop Word from System Stack PO P POP op1 tmp SP SP SP 2 op1 lt tmp WORD Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1 The Stack Pointer is then incremented by two E Z V C N E Set if the value of the popped word represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the popped word equals zero Cleared otherwise V Not affected Not affected N Set if the most significant bit of the popped word is set Cleared otherwise Mnemonic Format Bytes POP reg FC RR 2 109 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set PRIOR Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Prioritize Register PRIOR PRIOR 0p1 op2 tmp op2 count lt 0 DO WHILE tmp45 1 AND count 15 AND op2 0 tmpn lt tmpn 1 count lt count 1 END WHILE op1 lt count WORD This instruction stores a count value in the word operand specified by o
14. 0p2 0p3 The syntax for the actual operands of an instruction depends on the selected addressing mode All of the addressing modes available are summarized at the end of each single instruction description In contrast to the syntax for the instructions described in the following the assembler provides much more flexibility in writing C166 Family programs e g by generic instructions and by automatically selecting appropriate addressing modes whenever possible and thus it eases the use of the instruction set Note For more information about this item please refer to the Assembler manual Operation This part presents a logical description of the operation performed by an instruction by means of a symbolic formula or a high level language construct pseudo code The following symbols are used to represent data movement arithmetic or logical operators Diadic Operations opX operator opY opY is MOVED into opX OpX is ADDED to opY opY is SUBTRACTED from opX x opX is MULTIPLIED by opY OpX is DIVIDED by opY A opX is logically ANDed with opY v opX is logically ORed with opY opX is logically EXCLUSIVELY ORed with opY S opX is COMPARED against opY mod opX is divided MODULO opY User s Manual 32 V2 0 2001 03 nfineon technologies C166 Family Instruction Set Monadic Operations opX is Detailed Description operator opX logically COMPLEMENTED
15. Data Addressing Modes Word GPR RO R1 R15 Byte GPR RLO RHO RL7 RH7 SFR ESFR or GPR in case of a byte operation on an SFR only the low byte can be accessed via reg Direct word or byte memory location Indirect word or byte memory location Any word GPR can be used as indirect address pointer except for the arithmetic logical and compare instructions where only RO to R3 are allowed Direct bit in the bit addressable memory area Direct word in the bit addressable memory area Immediate constant The number of significant bits which can be specified by the user is represented by the respective appendix x Immediate 8 bit mask used for bit field modifications Branch Target Addressing Modes Direct 16 bit jump target address updates the Instruction Pointer Byte GPR RLO RHO RL7 RH7 Direct 8 bit segment address updates the Code Segment Pointer Signed 8 bit jump target word offset address relative to the Instruction Pointer of the following instruction Immediate 7 bit trap or interrupt number 1 Inthe 8XC166 W devices the segment is only a 2 bit number due to the smaller address range User s Manual 8 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Summary 3 3 Multiply and Divide Operations The MDL and MDH registers are implicit source and or destination operands of the multiply and divide instructions 3 4 Extension Operations pag1
16. Data Page op1 DO WHILE count 0 AND Class_B_trap_condition TRUE Next Instruction count count 1 END WHILE count 0 Data_Page DPPx Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard PEC interrupts and class A hardware traps are locked The EXTP instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 AO is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence Please see additional notes on Page 39 The EXTP instruction is not available in the SAB 8XC166 W devices E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected 78 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set EXTP Addressing Modes User s Manual continued Mnemonic EXTP Rwm irang2 EXTP pag irang2 79 Detailed Description EXTP Format Bytes DC 01 m 2 D7 01 0 pp 0 00pp 4 V2 0 2001 03 o nfineon techno
17. indirect or to specify the target address of a branch instruction absolute relative indirect The different addressing modes use different formats and cover different scopes 6 1 Short Addressing Modes All of these addressing modes use an implicit base offset address to specify a 24 bit physical address 18 bit address for the SAB 8XC166 W devices Short addressing modes permit access to the GPR SFR ESFR or bit addressable memory space by specifying just 8 bits within an instruction Physical Address Base Address A x Short Address Note A is 1 for byte GPRes A is 2 for word GPRs and SFRs ESFRs Table 6 Short Addressing Mnemo Physical Address Short Address Scope of Access nic Range Rw CP 2 x Rw Rw 0 15 GPRs word Rb CP 1xRb Rb 0 15 GPRs byte reg 00 FE00 2 x reg reg 00 EFy SFRs_ word low byte 00 F000 2x reg reg 00 EF ESFRs word low byte CP 2x regaOFy reg FO FFy GPRs word CP 1x rega0Fh reg FO FFy GPRs byte bitoff 00 FDO0 2 x bitoff bitoff O0y4 7Fy RAM _ bit word offset 00 FF004 2 x bitoffa7F4 bitoff 804 EFy SFR bit word offset 00 F1004 2 x bitoffa7F4 bitoff 804 EFy ESFR bit word offset CP 2 x bitoffAOF bitoff FO FFy GPR bit word offset bitaddr Word offset as with bitoff bitoff 00 Immediate bit position bitpos 0 15 FF Any single bit
18. o i C166 Family nfineon technologies Instruction Set Overviews Table 3 Instruction Overview ordered by Mnemonic cont d Mnemo Addressing Modes 4 Addressing Modes nic s es m m MOV Rwn Rwm 2 seg caddr 4 MOVB Rwn data4 2 Rwn Rwm 2 rel 2 Rwn Rwm 2 Rwm Rwn 2 cc rel 2 Rwm Rwn 2 bitaddrQ q rel 4 Rwn Rwm 2 Rwn Rwm 2 Rwn Rwm 2 reg caddr 4 reg data16 4 3 i Rwn Rwm d16 4 reg Rwm d16 Rwn 4 Rwn mem 4 mem Rwn 4 reg data16 4 reg mem 4 reg mem 4 mem reg 4 Rwn Rwm 2 MOVBS_ Rwn Rom 2 trap7 2 MOVBZ reg mem 4 irang2 3 Jo mem reg 4 1 Byte oriented instructions suffix B use byte registers Rb instead of Rw except for indirect addressing modes Rw or Rw 2 Byte oriented instructions suffix B use data8 instead of data16 3 The ATOMIC and EXTended instructions are not available in the SAB 8XC166 W devices User s Manual V2 0 2001 03 C166 Family Infineon TE Sass 3 Summary Summary This chapter summarizes the instructions by listing them according to their functional class This enables the user to identify the right instruction s for a specific required function The following general explanations apply to this summary 3 1 Rw Rb reg mem baddr bitoff datax mask8 3 2 caddr Rb seg rel trap7
19. 03 TT Cinfineon C166 Family technologies Instruction Set Summary Table 4 Instruction Set Summary contd Mnemonic Description Bytes Arithmetic Operations cont d ADDCB reg data8 Add immediate byte data to direct register with Carry 4 ADDCB reg mem Add direct byte memory to direct register with Carry 4 ADDCB men reg Add direct byte register to direct memory with Carry 4 SUB Rw Rw Subtract direct word GPR from direct GPR 2 SUB Rw Rw Subtract indirect word memory from direct GPR 2 SUB Rw Rw Subtract indirect word memory from direct GPR and 2 post increment source pointer by 2 SUB Rw data3 Subtract immediate word data from direct GPR 2 SUB reg datai6 Subtract immediate word data from direct register 4 SUB reg mem Subtract direct word memory from direct register 4 SUB mem reg Subtract direct word register from direct memory 4 SUBB Rb Rb Subtract direct byte GPR from direct GPR 2 SUBB Rb Rw Subtract indirect byte memory from direct GPR 2 SUBB Rb Rw Subtract indirect byte memory from direct GPR and 2 post increment source pointer by 1 SUBB Rb data3 Subtract immediate byte data from direct GPR 2 SUBB reg data8 Subtract immediate byte data from direct register 4 SUBB reg mem Subtract direct byte memory from direct register 4 SUBB mem reg Subtract direct byte register from direct memory 4 SUBC Rw Rw
20. 16 bit x 16 bit MULU Rw Rw Unsigned multiply direct GPR by direct GPR 2 16 bit x 16 bit DIV Rw Signed divide register MDL by direct GPR 2 16 bit 16 bit DIVL Rw Signed long divide register MD by direct GPR 2 32 bit 16 bit DIVLU Rw Unsigned long divide register MD by direct GPR 2 32 bit 16 bit DIVU Rw Unsigned divide register MDL by direct GPR 2 16 bit 16 bit CPL Rw Complement direct word GPR 2 CPLB Rb Complement direct byte GPR 2 NEG Rw Negate direct word GPR 2 NEGB Rb Negate direct byte GPR 2 User s Manual 12 V2 0 2001 03 TT if ne C166 Family technologies Instruction Set Summary Table 4 Instruction Set Summary cont d Mnemonic Description Bytes Logical Instructions AND Rw Rw Bitwise AND direct word GPR with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR and 2 post increment source pointer by 2 AND Rw data3 Bitwise AND immediate word data with direct GPR 2 AND reg data16 Bitwise AND immediate word data with direct register 4 AND reg mem Bitwise AND direct word memory with direct register 4 AND mem reg Bitwise AND direct word register with direct memory 4 ANDB Rb Rb Bitwise AND direct byte GPR with direct GPR 2 ANDB _ Rb Rw Bitwise AND indirect byte memory with direct GPR 2 AND
21. ATOMIC and EXTended instructions have been added for these devices and are not recognized by the following devices from the first generation of 16 bit microcontrollers e SAB 80C166 SAB 80C166W e SAB 83C166 SAB 83C166W These differences are noted for each instruction where applicable User s Manual 2 V2 0 2001 03 o C166 Family Infineon Keira A Overviews 2 Overviews The following compressed cross reference tables quickly identify a specific instruction and provide basic information about it Two ordering schemes are included e The hexadecimal opcode of a specific instruction can be quickly identified with the respective mnemonic using the first compressed cross reference table e The mnemonics and addressing modes of the various instructions are listed in the second table The table shows which addressing modes may be used with a specific instruction and also the instruction length depending on the selected addressing mode This reference helps to optimize instruction sequences in terms of code size and or execution time Both ordering schemes hexadecimal opcode and mnemonic are provided in more detailed lists in the following sections of this manual Note The ATOMIC and EXTended instructions are not available in the SAB 8XC 166 W devices They are marked in the cross reference table User s Manual 3 V2 0 2001 03 o n
22. Modes User s Manual Integer Addition ADDB op1 op2 0p1 op1 op2 BYTE Detailed Description ADDB Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 E Z V C E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic ADDB Rb Rbm ADDB Rb Rw ADDB Rb Rw ADDB Rb data3 ADDB reg data8 ADDB reg mem ADDB mem reg 42 Format 01 nm 09 n 10ii 09 n 11ii 09 n 0 07 RR xx 03 RR MM MM 05 RR MM MM Bytes 2 RAR RMN N V2 0 2001 03 o nfineon technologies C166 Family Instruction Set ADDC Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Integer Addition with Carry ADDC 0p1 lt 0p1 op2 C WORD op1 op2 Detailed Description ADDC Performs a 2 s complement binary addition of the source oper
23. RET CB 00 2 113 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set RETI Syntax Operation Description Condition Flags Addressing Modes User s Manual Detailed Description Return from Interrupt Routine RE TI RETI IP lt SP SP SP 2 IF SYSCON SGTDIS 0 THEN CSP SP SP SP 2 END IF PSW lt SP SP SP 2 Returns from an interrupt routine The PSW IP and CSP are popped off the system stack Execution resumes at the instruction which had been interrupted The previous system state is restored after the PSW has been popped The CSP is only popped if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register E Z V C N S S S S S Restored from the PSW popped from stack Restored from the PSW popped from stack Restored from the PSW popped from stack Restored from the PSW popped from stack z O lt s NM Restored from the PSW popped from stack Mnemonic Format Bytes RETI FB 88 2 114 V2 0 2001 03 TT e e Infineon technologies C166 Family Instruction Set RETP Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Return from Subroutine and Pop Word RETP RETP op1 P SP P SP 2 I S tmp SP SP SP 2 op1 lt tmp WORD Returns fr
24. Z V C N S E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPI2 Rw data4 90 n 2 CMPI2 Rw data16 96 Fn 4 CMPI2 Rw mem 92 Fn MM MM 4 68 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CPL Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Integer One s Complement CPL CPL op1 0p1 op1 WORD Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 E Z V C N 0 0 E Setifthe value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Setif result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CPL Rw 91 nO 2 69 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CPLB Syntax
25. a 16 bit wide data bus takes one additional ALE Cycle Time For timing calculations of external program parts this extra time must always be considered The value of Tjagqg which must be considered for timing evaluations of internal program parts may fluctuate between 0 state times and 1 ALE Cycle Time This is because external writes are normally performed in parallel to other CPU operations Thus Tjagqa Could already have been considered in the standard processing time of another instruction Writing a word operand via an 8 bit wide data bus requires twice as much time 2 ALE Cycle Times as the writing of a byte operand Tiaaa 0 or 1 or 2 ACT Testing Branch Conditions Mostly NO extra time is required for conditional branch instructions to decide whether a branch condition is met or not However an additional state time is required if the preceding instruction writes to register PSW as shown in the following example BSET USRO Explicit write to PSW JMPR cc _Z JumpTarget Test condition flag in PSW Tadd 1 State In this case the extra state time can simply be intercepted by putting another suitable instruction before the conditional branch instruction Tiadd 0 or 1 State Users Manual 146 V2 0 2001 03 C166 Family Instruction Set technologies Instruction State Times Jumps into the Internal Program Memory The minimum time of 4 state times for standard jumps into the internal ROM space will be extended
26. by 2 additional state times if the branch target is a double word instruction at a non aligned double word location xxx24 Xxx6y4 xxxAy XxxEy as shown in the following example ORG OFFEH Any non aligned double word location LABEL JumpTarget Any double word instruction JMPA cc_UC JumpTarget If standard branch is taken Tadd 2 States A cache jump which normally requires just 2 state times will be extended by 2 additional state times if both the cached jump target instruction and its successor instruction are non aligned double word instructions as shown in the following example ORG 12FAh Any non aligned double word location LABEL JumpTarget Any double word instruction aioe eae Any double word instruction JMPR cc UC JumpTarget If cache jump is taken Tadd 2 States If required these extra state times can be avoided by allocating double word jump target instructions to aligned double word addresses xxx04 xxx44 XXx8 4 XXXCy Tiadd 0 or 2 States Users Manual 147 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set 8 Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the C166 Family instruction set This helps to quickly find the answer to specific questions about the C166 Family instruction set e g addressing encoding etc A Additional state times 145 Addressing indirect 135 long 134 modes 36 short 132 Addressing m
27. cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ORB Rb Rb 71 nm 2 ORB Rb Rw 79 n 10ii 2 ORB Rb Rw 79 n 11ii 2 ORB Rb data3 79 n O0 2 ORB reg data8 77 RR xx 4 ORB reg mem 73 RR MM MM 4 ORB mem reg 75 RR MM MM 4 107 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set PCALL Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Push Word and Call Subroutine Absolute PCALL PCALL 0op1 op2 tmp lt op SP SP 2 SP lt tmp SP SP 2 SP lt IP IP op2 WORD Pushes the word specified by operand op1 and the value of the instruction pointer IP onto the system stack and branches to the absolute memory location specified by the second operand op2 Because IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine E Z V C N E Set if the value of the pushed operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed operand op1 equals zero Cleared otherwise V Not affected Not affected N Set ifthe most significant bit of the pushed operand op1 is set Cleared otherwise
28. data8 Compare immediate byte data to direct register 4 CMPB reg mem Compare direct byte memory to direct register 4 User s Manual 15 V2 0 2001 03 TT oe i C166 Family nfineon technologies Instruction Set Summary Table 4 Instruction Set Summary cont d Mnemonic Description Bytes Compare and Loop Control Instructions CMPD1 Rw data4 Compare immediate word data to direct GPR and 2 decrement GPR by 1 CMPD1 Rw data16 Compare immediate word data to direct GPR and 4 decrement GPR by 1 CMPD1 Rw mem Compare direct word memory to direct GPR and 4 decrement GPR by 1 CMPD2 Rw data4 Compare immediate word data to direct GPR and 2 decrement GPR by 2 CMPD2 Rw datai6 Compare immediate word data to direct GPR and 4 decrement GPR by 2 CMPD2 Rw mem Compare direct word memory to direct GPR and 4 decrement GPR by 2 CMPI1 Rw data4 Compare immediate word data to direct GPR and 2 increment GPR by 1 CMPI1 Rw datai6 Compare immediate word data to direct GPR and 4 increment GPR by 1 CMPI1 Rw mem Compare direct word memory to direct GPR and 4 increment GPR by 1 CMPI2 Rw data4 Compare immediate word data to direct GPR and 2 increment GPR by 2 CMPI2 Rw datai6 Compare immediate word data to direct GPR and 4 increment GPR by 2 CMPI2 Rw mem Compare direct word memory to direct GPR and 4 increment GPR by 2 Shift and Rotate Instructions SHL Rw Rw Shift left
29. direct word GPR 2 number of shift cycles specified by direct GPR SHL Rw data4 Shift left direct word GPR 2 number of shift cycles specified by immediate data SHR Rw Rw Shift right direct word GPR 2 number of shift cycles specified by direct GPR User s Manual 16 V2 0 2001 03 TT e z nfineon C166 Family technologies Instruction Set Summary Table 4 Instruction Set Summary cont d Mnemonic Description Bytes Shift and Rotate Instructions cont d SHR Rw data4 Shift right direct word GPR 2 number of shift cycles specified by immediate data ROL Rw Rw Rotate left direct word GPR 2 number of shift cycles specified by direct GPR ROL Rw data4 Rotate left direct word GPR 2 number of shift cycles specified by immediate data ROR Rw Rw Rotate right direct word GPR 2 number of shift cycles specified by direct GPR ROR Rw data4 Rotate right direct word GPR 2 number of shift cycles specified by immediate data ASHR Rw Rw Arithmetic sign bit shift right direct word GPR 2 number of shift cycles specified by direct GPR ASHR_ Rw data4 Arithmetic sign bit shift right direct word GPR 2 number of shift cycles specified by immediate data Data Movement MOV Rw Rw Move direct word GPR to direct GPR 2 MOV Rw data4 Move immediate word data to direct GPR 2 MOV reg datai6 Move immediate word data to direct register 4 MOV Rw Rw Move i
30. ee 138 6 7 Branch Target Addressing Modes 00000 139 7 Instruction State Times 0 00 00 eee eee 141 7 1 Time Unit Definitions fss5 das edwin vans e oa 8 dee e eee dees 142 7 2 Minimum Execution Time 00 ennen nn kk es 143 7 3 Additional State Times 20 sneen eee 145 8 Keyword Index 266 eit nnana bee ie eee Reese k kk kk kk eS 148 User s Manual V2 0 2001 03 TT C166 Family Infineon TE A Introduction 1 Introduction The Infineon C166 Family of 16 bit microcontrollers offers devices that provide various levels of peripheral performance and programmability This allows to equip each specific application with the microcontroller that fits best to the required functionality and performance Still the Infineon family concept provides an easy path to upgrade existing applications or to climb the next level of performance in order to realize a subsequent more sophisticated design Two major characteristics enable this upgrade path to save and reuse almost all of the engineering efforts that have been made for previous designs All family members are based on the same basic architecture All family members execute the same instructions except for upgrades for new members The fact that all members execute basically the same instructions saves know how with respect to the understanding of the controller itself and also with respect to the used tools assembler disassem
31. if Bit Clear and Set Bit JNBS JNBS op1 op2 IF op1 0 THEN op1 1 IP IP sign extend op2 ELSE Next Instruction END IF BIT If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is set allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNBS instruction If the specified bit was set the instruction following the JNBS instruction is executed E Z V C N 0 B 0 0 B Always cleared Z Contains logical negation of the previous state of the specified bit V Always cleared Always cleared N Contains the previous state of the specified bit Mnemonic Format Bytes JNBS bitaddrg q rel BA QQ rr q0 4 94 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set MOV Syntax Operation Data Types Description Condition Flags User s Manual Detailed Description Move Data M OV MOV op1 op2 op1 op2 WORD Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the condition codes are updated accordingly
32. interface In contrast to execution from the internal program memory the time required to process an external program additionally depends on the length of the instructions and operands on the selected bus mode and on the duration of an external memory cycle which is partly selectable by the user Processing a program from the internal RAM space is not as fast as execution from the internal ROM area but it offers a lot of flexibility e g for loading temporary programs into the internal RAM via the chip s serial interface or end of line programming via the bootstrap loader Execution from the on chip extension RAM XRAM is faster than execution from the internal RAM IRAM The following description allows evaluating the minimum and maximum program execution times This will be sufficient for most requirements For an exact determination of the instructions state times it is recommended to use the facilities provided by simulators or emulators In general the execution time of an instruction is composed of several additive units e The minimum instruction state time represents the number of clock cycles required to step through the instruction pipeline or to execute the instruction MUL DIV e Operand reads can increase the instruction s execution time if the operand is read from the on chip program memory space is read from the IRAM immediately after a preceeding write to the IRAM is read from external resources
33. onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally The condition codes for op1 are defined in Table 5 E Z V C N Not affected Not affected Not affected Not affected 2 O lt s NM Not affected Mnemonic Format Bytes CALLI cc Rw AB cn 2 60 V2 0 2001 03 o nfineon technologies CALLR Syntax Operation Description Condition Flags Addressing Modes User s Manual C166 Family Instruction Set Detailed Description CALLR Call Subroutine Relative CALLR 0p1 SP SP 2 SP lt IP IP IP sign_extend 0p1 A branch is taken to the location specified by the instruction pointer IP plus the relative displacement op1 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine The value of the IP used in the target address calculation is the address of the instruction following the CALLR instruction E Z V Cc N
34. or 80 JMPS 4 160 JMPA JMPI JMPR 4or2 160 or 80 MUL MULU 10 400 DIV DIVL DIVU DIVLU 20 800 RET RETI RETP RETS 4 160 MOV B Rn Rm data16 4 160 TRAP 4 160 All other instructions 2 80 Users Manual 143 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Instruction State Times Instructions executed from the internal RAM The minimum instruction time see Table 11 must be extended by an instruction length dependent number of state times as follows For 2 byte instructions Timin RAM Timin PM 4 States For 4 byte instructions Timin RAM Timin PM 6 States Instructions executed from the External Memory The minimum instruction time see Table 11 must be extended by an instruction length dependent number of ALE Cycle Times This number depends on the instruction length 2 byte or 4 byte and on the data bus width 8 bit or 16 bit Accesses to the on chip XRAM are controlled by the EBC and therefore also must be considered as external accesses For 2 byte instructions Tjmin ext Tymin PM 1 ACT For 4 byte instructions Timin ext Timin PM 2 ACT Note For instructions fetched from external memory via an 8 bit data bus the minimum number of required ALE Cycle Times is twice the given number 16 bit bus Users Manual 144 V2 0 2001 03 TT e z Infineon C166 Family technologies Instruction Set Instruction State Times 7 3 Additional State Times In mo
35. or from the XRAM via the EBC e Operand writes can increase the instruction s execution time if the target is in the external memory and the write cycle conflicts with another external memory operation e Jumps to the on chip program memory can increase the instruction s execution time if the jump target is a non aligned doubleword instruction e Testing branch conditions can increase the instruction s execution time if the previous instruction has written to register PSW Users Manual 141 V2 0 2001 03 o C166 Family Infineon Tre fas Instruction State Times 7 1 Time Unit Definitions This section defines the subsequently used time units summarizes the Minimum standard state times of the 16 bit microcontroller instructions and describes the exceptions from that standard timing The following time units are used to describe the instructions processing times fFcru CPU operating frequency may vary depending on the employed device type and on the actual operating mode of the device State One state time is specified as the duration of one CPU clock period Henceforth one State is used as the basic time unit because it represents the shortest period of time which has to be considered for instruction timing evaluations 1 State 1 fopu s 40 ns for fopy 25 MHz ACT The ALE Address Latch Enable Cycle Time specifies the time required to perform one external memory access One ALE Cycle Time consists o
36. sign extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the condition codes are updated accordingly E Z V C N 0 Always cleared Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected Not affected N Setif the most significant bit of the source operand op2 is set Cleared otherwise Mnemonic MOVBS Rw Rb MOVBS reg mem MOVBS mem reg 99 Format Bytes DO mn 2 D2 RR MM MM 4 D5 RR MM MM 4 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set MOVBZ Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Move Byte Zero Extend MOVBZ MOVBZ 0p1 op2 low byte op1 op2 high byte op1 lt 004 WORD BYTE Moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the condition codes are updated accordingly E Z V C N 0 ij 7 0 Always cleared Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected Not affected N Always cleared Mnemonic Format Bytes MOVBZ Rwy Rbm CO mn 2 MOVBZ reg mem C2 RR MM MM 4 MOVBZ me
37. source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is then stored in op1 This instruction can be used to perform multiple precision arithmetic E Z V C N S S E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SUBC Rw RWm 30 nm 2 SUBC Rw Rwi 38 n 10ii 2 SUBC Rw Rw 38 n 11ii 2 SUBC Rw data3 38 n 0 2 SUBC reg data16 36 RR 4 SUBC reg mem 32 RR MM MM 4 SUBC mem reg 34 RR MM MM 4 127 V2 0 2001 03 o nfineon technologies SUBCB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual C166 Family Instruction Set Detailed Description Integer Subtraction with Carry S U BC B SUBCB__op1 op2 0p1 lt op1 op2 C BYTE Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is th
38. that this instruction is not accidentally executed it is implemented as a protected instruction E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes DISWDT A5 5A A5 A5 4 71 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set DIV Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description 16 by 16 Signed Division DIV DIV op1 MDRIU 1 MDL MDL op1 MDH lt MDL mod op1 WORD Performs a signed 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH DIV is interruptable Please see additional description on Page 40 E Z V C N 0 ij S 0 Always cleared Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred i e if the divisor op1 was zero the result in MDH and MDL is not valid in this case Cleared otherwise Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes DIV Rw 4B nn 2 72 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set DIVL
39. word GPR Rw The override mechanism is valid for the number of instructions specified in the irang parameter of the respective EXTend instruction EXTP R ae 16 Bit Long Address pag 14 Bit Page Offset 24 Bit Physical Address EXTS R 15 0 16 Bit Segment Offset seg 24 Bit Physical Address MCD04932 Figure 3 Overriding the DPP Mechanism Note The EXTend instruction and hence the override mechanism are not available in the SAB 8XC166 X devices Users Manual 137 V2 0 2001 03 eo nfineon C166 Family technologies Instruction Set Addressing Modes 6 5 Constants within Instructions The C166 Family instruction set also supports the use of wordwide or bytewide immediate constants For an optimum utilization of the available code storage these constants are represented in the instruction formats by either 3 4 8 or 16 bits Thus short constants are always zero extended while long constants are truncated if necessary to match the data format required for the particular operation see Table 9 Table 9 Constants Mnemonic Word Operation Byte Operation data3 00004 data3 004 data3 data4 00004 data4 004 data4 data8 00004 data8 data8 data16 data16 data16 FFy mask 00004 mask mask Note Immediate constants are always signified by a leading number sign 6 6 Instruction Range irang2 The effect of the ATOMIC and EXTend in
40. 0 Immediate 10 bit page address seg8 Immediate 8 bit segment address irang2 Immediate 2 bit instruction range The extension instructions EXTP EXTPR EXTS and EXTSR override the standard DPP addressing scheme using immediate addresses instead Note The EXTended instructions are not available in the SAB 8XC166 W devices 3 5 Branch Condition Codes cC cc_UC Unconditional cc_Z Zero cc_NZ Not Zero cc_V Overflow cc_NV No Overflow cc_N Negative cc_NN Not Negative cc_C Carry cc_NC No Carry cc_EQ Equal cc_NE Not Equal cc_ULT Unsigned Less Than cc_ULE Unsigned Less Than or Equal cc_UGE Unsigned Greater Than or Equal cc_UGT Unsigned Greater Than cc SLE Signed Less Than or Equal cc SGE Signed Greater Than or Equal cc SGT Signed Greater Than cc NET Not Equal and Not End of Table Note Condition codes can be specified symbolically within an instruction A detailed description of the condition codes can be found in Table 5 User s Manual 9 V2 0 2001 03 TT if ne C166 Family technologies Instruction Set Summary Table 4 Instruction Set Summary Mnemonic Description Bytes Arithmetic Operations ADD Rw Rw Add direct word GPR to direct GPR 2 ADD Rw Rw Add indirect word memory to direct GPR 2 ADD Rw Rw Add indirect word memory to direct GPR and 2 post increment source pointer by 2 ADD Rw data3 Add immediate word data to
41. 7 RR xx 4 ANDB reg mem 63 RR MM MM 4 ANDB mem reg 65 RR MM MM 4 46 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set ASHR Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Arithmetic Shift Right ASHR ASHR op1 op2 count lt op2 V 0 C 0 DO WHILE count 0 V C v V C opto op1 0p1y44 IN 0 14 count count 1 END WHILE WORD Arithmetically shifts the destination word operand op1 right by as many times as specified in the source operand op2 To preserve the sign of the original operand op1 the most significant bits of the result are filled with zeros if the original MSB was a 0 or with ones if the original MSB was a 1 The Overflow flag is used as a Rounding flag The LSB is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Z V Cc N 0 S S Always cleared Z Setif result equals zero Cleared otherwise Set if in any cycle of the shift operation a 1 is shifted out of the carry flag Cleared for a shift count of zero C The carry flag is set according to the last LSB shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic For
42. B _ Rb Rw Bitwise AND indirect byte memory with direct GPR and 2 post increment source pointer by 1 ANDB Rb datas3 Bitwise AND immediate byte data with direct GPR 2 ANDB reg data8 Bitwise AND immediate byte data with direct register 4 ANDB reg mem Bitwise AND direct byte memory with direct register 4 ANDB men reg Bitwise AND direct byte register with direct memory 4 OR Rw Rw Bitwise OR direct word GPR with direct GPR 2 OR Rw Rw Bitwise OR indirect word memory with direct GPR 2 OR Rw Rw Bitwise OR indirect word memory with direct GPR and 2 post increment source pointer by 2 OR Rw data3 Bitwise OR immediate word data with direct GPR 2 OR reg datai6 Bitwise OR immediate word data with direct register 4 OR reg mem Bitwise OR direct word memory with direct register 4 OR mem reg Bitwise OR direct word register with direct memory 4 ORB Rb Rb Bitwise OR direct byte GPR with direct GPR 2 ORB Rb Rw Bitwise OR indirect byte memory with direct GPR 2 ORB Rb Rw Bitwise OR indirect byte memory with direct GPR and 2 post increment source pointer by 1 ORB Rb data3 Bitwise OR immediate byte data with direct GPR 2 User s Manual 13 V2 0 2001 03 TT oe nfineon C166 Family technologies Instruction Set Summary Table 4 Instruction Set Summary cont d Mnemonic Description Bytes Logical Instructions cont d ORB re
43. B bitaddrg q rel 8A QQ rr q0 4 User s Manual 87 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set JBC Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Relative Jump if Bit Set and Clear Bit J BC JBC op1 op2 IF op1 1 THEN op1 O IP IP sign extend op2 ELSE Next Instruction END IF BIT If the bit specified by op1 is set program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is cleared allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JBC instruction If the specified bit was clear the instruction following the JBC instruction is executed E Z V C N 0 B 0 0 B Always cleared Z Contains logical negation of the previous state of the specified bit V Always cleared Always cleared N Contains the previous state of the specified bit Mnemonic Format Bytes JBC bitaddrg q rel AA QQ rr q0 4 88 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set JMPA Syntax Operation Description Note Condition Flags Addressing Mode
44. BCMP Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description Bit to Bit Compare BCM P BCMP op1 op2 0p1 op2 BIT Performs a single bit comparison of the source bit specified by operand opi to the source bit specified by operand op2 No result is written by this instruction Only the condition codes are updated The meaning of the condition flags for the BCMP instruction is different from the meaning of the flags for the other compare instructions E Z V C N 0 NOR OR AND XOR Always cleared Contains the logical NOR of the two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits zo lt s NM Contains the logical XOR of the two specified bits Mnemonic Format Bytes BCMP bitaddrz z bitaddrgg 2A QQ ZZ qz 4 51 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set BFLDH Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description Bit Field High Byte BFLDH BFLDH op1 op2 op3 tmp 0p1 high byte tmp high byte tmp a o0p2 v op3 op1 lt tmp WORD Replaces those bits in the high byte of the destination word operand op1 which are selected by a 1 in the AND mask op2 with the bits at the corresponding positions
45. C 2 EXTP R Rw irang2 EXTS R CD 2 JMPR cc_SLT rel DD 2 JMPR cc_SGE rel CE 2 BCLR bitoff 12 DE 2 BCLR bitoff 13 CF 2 BSET bitoff 12 DF 2 BSET bitoff 13 Users Manual 29 V2 0 2001 03 o A C166 Family nfineon technologies Instruction Set Encoding g g 2 Mnemonic Operands 3 Mnemonic Operands I ja I M EO 2 MOV Rw data4 FO 2 MOV Rw Rw E1 12 MOVB Rb data4 Fi 12 MOVB Rb Rb E2 4 PCALL reg caddr F2 MOV reg mem E3 F3 14 MOVB reg mem E4 14 MOVB Rw data16 F4 14 MOVB Rb Rb Rw data16 E5 F5 l E6 14 MOV reg data16 F6 14 MOV mem reg E7 4 MOVB reg data8 F7 14 MOVB mem reg E8 2 MOV Rw Rw F8 E9 2 MOVB Rw Rw F9 l EA 4 JMPA cc caddr FA 4 JMPS seg caddr EB 2 RETP reg FB 2 RETI EC 2 PUSH reg FC 2 POP reg ED 2 JMPR cc_UGT rel FD 2 JMPR cc_ULE rel EE 2 BCLR bitoff 14 FE 2 BCLR bitoff 15 EF 2 BSET bitoff 14 FF 2 BSET bitoff 15 Users Manual 30 V2 0 2001 03 TT e z nfineon C166 Family technologies Instruction Set Detailed Description 5 Detailed Description This chapter describes each instruction in detail The example further down on this page lists the elements of a description and demonstrates how the information given for each instruction is arranged The next pages explain the elements of an inst
46. Description Peculiarities of Multiplication and Division Instructions Multiplications and divisions are interruptible to optimize the interrupt response time Bit MDC MDRIU indicates that register MD is currently in use bit PSW MULIP indicates an interrupted multiplication Chapter System Programming of the respective User s Manual describes the handling of interrupted multiplications and divisions Bit MDRIU is set at the start of a MUL instruction not when the instruction is resumed or upon a write to register MDL or MDH Bit MDRIU is cleared upon a read from register MDL Bit MDRIU is affected by a write to register MDC of course When the MUL instruction is interrupted bit MULIP is set in the PSW of the interrupting routine i e after pushing the previous PSW onto stack When returning from the interrupt bit MULIP must be set cleared according to the next executed instruction Note For the first instruction after RET bit MULIP 1 prevents the multiplicand from being reloaded the intermediate result resides in MD This mechanism will disturb the operand fetching if another instruction than the continued multiplication is executed after RETI For standard interrupt handling return to interrupted multiplication this is done automatically Task schedulers must keep track of interrupted multiplications in each task The following pages of this section contain a detailed description of each instruction of the C166 Fa
47. In some rare cases however either one or two additional state times will be caused by particular SFR operations as follows Reading an SFR immediately after an instruction which writes to the internal SFR space as shown in the following example MOV TO 1000h write to Timer 0 ADD R3 T1 read from Timer 1 Tadd 1 State Reading register PSW immediately after an instruction which implicitly updates the condition flags as shown in the following example ADD RO 1000h implicit modification of PSW flags BAND Er Z read from PSW Tadd 2 States Users Manual 145 V2 0 2001 03 TT C166 Family Infineon Tr Sas Instruction State Times Implicitly incrementing or decrementing register SP immediately after an instruction which explicitly writes to register SP as shown in the following example MOV SP 0FBOOh explicit update of the stack pointer SCXT R1 1000h implicit decrement of SP Tadd 2 States In these cases the extra state times can be avoided by putting other suitable instructions before the instruction 14 4 reading the SFR Tiaqg 0 or 1 or 2 State s Operand Reads from External Memory Any external operand reading via a 16 bit wide data bus requires one additional ALE Cycle Time Reading word operands via an 8 bit wide data bus takes twice as much time 2 ALE Cycle Times as the reading of byte operands Tiadd 10r2 ACT Operand Writes to External Memory Writing an external operand via
48. M AO 2 CMPD1 Rw data4 BO 2 CMPD2 Rw data4 A1 2 NEGB Rb B1 2 CPLB Rb A2 4 CMPD1 Rw mem B2 4 CMPD2 Rw mem A3 B3 l A4 14 MOVB Rw mem B4 4 MOVB mem Rw A5 4 DISWDT B5 14 EINIT A6 14 CMPD1 Rw data16 B6 14 CMPD2 Rw data16 A7 4 ISRVWDT B7 4 SRST A8 2 MOV Rw Rw B8 2 MOV Rw Rw A9 2 MOVB Rb Rw B9 2 MOVB Rw Rb AA 14 JBC bitaddr rel BA 4 JNBS bitaddr rel AB 2 CALLI cc Rw BB 2 CALLR rel AC 2 ASHR Rw Rw BC 12 ASHR Rw data4 AD 2 JMPR cc_SGT rel BD 2 JMPR cc SLE rel AE 2 BCLR bitoff 10 BE 2 BCLR bitoff 11 AF 2 BSET bitoff 10 BF 2 BSET bitoff 11 User s Manual 28 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Encoding D D 3 Mnemonic Operands 3 Mnemonic Operands I m I m CO 2 MOVBZ Rw Rb DO 2 MOVBS Rw Rb Ci l D1 2 ATOMIC irang2 or EXTR C2 4 MOVBZ reg mem D2 4 MOVBS reg mem C3 l D3 C4 4 MOV Rw data16 D4 14 MOV Rw Rw Rw data16 C5 4 MOVBZ mem reg D5 4 MOVBS mem reg C6 4 SCXT reg data16 D6 4 SCXT reg mem C7 D7 4 EXTP R pag10 irang2 EXTS R seg8 irang2 C8 2 MOV Rw Rw D8 2 MOV Rw Rw C9 2 MOVB Rw Rw D9 2 MOVB Rw Rw CA 14 CALLA cc addr DA 4 CALLS seg caddr CB 2 RET DB 2 RETS cc 2 NOP 2 D
49. MPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV _ EXTPIR x7 IDLE PWRDN SRVWDT SRST EXTSIR MOVB MOVB x8 MOV MOV MOV MOV MOV MOV MOV x9 MOVB MOVB MOVB MOVB MOVB MOVB MOVB xA JB JNB JBC JNBS CALLA CALLS JMPA JMPS xB TRAP CALLI CALLR RET RETS RETP RETI i EXTPIR xC JMPI ASHR ASHR NOP gyre PUSH POP xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET User s Manual 5 V2 0 2001 03 TT i nfineon C166 Family technologies Instruction Set Overviews Table 3 Instruction Overview ordered by Mnemonic Mnemo Addressing Modes Addressing Modes R nic s ES m ADD B _ Rwn Rwm Rwn Rbn 2 ADDC B Rwn Rwi ANDJB Rwn Rwi Rwn 2 OR B Rwn data3 SUB B SUBCIB reg data16 XOR B reg mem mem reg Rwn Rwm 2 ASHR Rwn Rwm Rwn data4 2 ROL Rwn data4 ROR Rwn data16 4 SHL Rwn mem 4 SHR BAND bitaddrZ z bitaddrQ q Rwn Rwm 2 BCMP Rwn Rwi 2 BMOV Rwn Rwi 2 BMOVN Rwn data3 2 BOR BXOR reg data16 4 reg mem 4 BCLR bitaddrQ q CC caddr 4 BSET BFLDH bitoffQ mask8 CC Rwn 2 BFLDL data8 EXTS Rwm irang2 3 Rwm irang2 3 2 EXTSR _ seg irang2 pag irang2 4 NOP _ 4 RET RETI RETS Users Manual V2 0 2001 03
50. Manual 149 Keyword Index V2 0 2001 03 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG
51. Operands x Im x Im 40 2 CMP Rw Rw 50 12 XOR Rw Rw 41 2 CMPB Rb Rb 51 2 XORB Rb Rb 42 4 CMP reg mem 52 XOR reg mem 43 4 CMPB reg mem 53 4 XORB reg mem 44 54 4 XOR mem reg 45 55 4 XORB mem reg 46 4 CMP reg data16 56 4 XOR reg data16 47 4 CMPB reg data8 57 4 XORB reg data8 48 2 CMP Rw Rw or 58 2 XOR Rw Rw or Rw Rw or Rw Rw or Rw data3 Rw data3 49 2 CMPB Rb Rw or 59 2 XORB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 4A 4 BMOV bitaddr bitaddr 5A 4 BOR bitaddr bitaddr 4B 2 DIV Rw 5B 2 DIVU Rw 4C 2 SHL Rw Rw 5C 2 SHL Rw data4 4D 2 JMPR cc V rel 5D 2 JMPR cc_NV rel 4E 2 BCLR bitoff 4 SE 2 BCLR bitoff 5 4F 2 BSET bitoff 4 5F 2 BSET bitoff 5 User s Manual 25 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Encoding D D 3 Mnemonic Operands 3 Mnemonic Operands x M I Im 60 2 AND Rw Rw 70 2 OR Rw Rw 61 2 ANDB Rb Rb 71 2 ORB Rb Rb 62 4 AND reg mem 72 OR reg mem 63 4 ANDB reg mem 73 4 ORB reg mem 64 4 AND mem reg 74 4 JOR mem reg 65 14 ANDB mem reg 75 14 ORB mem reg 66 4 AND reg data16 76 4 OR reg data16 67 4 ANDB reg data8 77 4 ORB reg data8 68 2 AND Rw Rw or 78 2 JOR Rw Rw or Rw Rw or Rw Rw or Rw data3 Rw data3 69 2 ANDB
52. Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Integer One s Complement CPLB CPL op1 0p1 lt op1 BYTE Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 E Z V C N 0 0 E Setifthe value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Setif result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CPLB Rb B1 nO 2 70 V2 0 2001 03 o nfineon technologies DISWDT Syntax Operation Description Note Condition Flags Addressing Modes User s Manual C166 Family Instruction Set Disable Watchdog Timer DISWDT Disable the watchdog timer Detailed Description DISWDT This instruction disables the watchdog timer The watchdog timer is enabled by a reset The DISWDT instruction allows the watchdog timer to be disabled for applications which do not require a watchdog function Following a reset this instruction can be executed at any time until either a Service Watchdog Timer instruction SRVWDT or an End of Initialization instruction EINIT are executed Once one of these instructions has been executed the DISWDT instruction will have no effect To insure
53. R MUL rw rw rw ww rwh rwh rwh rwh rwh rwh The resulting state of the flags is represented by symbols as follows User s Manual 34 V2 0 2001 03 o C166 Family Infineon TE Sas Detailed Description Symbolic Settings for Condition Flags kk The flag value depends on the result of the instruction and is set cleared according to the following standard rules N 1 MSB of the result is set N 0 MSB of the result is not set C 1 Carry occurred during operation C 0 No Carry occurred during operation V 1 Arithmetic Overflow occurred during operation V 0 No Arithmetic Overflow occurred during operation Z 1 Result equals zero Z 0 Result does not equal zero E 1 Source operand represents the E 0Q Source operand does not represent the lowest negative number 8000 80 for word byte data The flag is set cleared according to special rules which deviate from the described standard For more details see instruction pages below or the ALU status flags description The flag is not affected by the operation The flag is cleared by the operation The flag contains the logical NOR of the two specified bit operands The flag contains the logical AND of the two specified bit operands The flag contains the logical OR of the two specified bit operands The flag contains the logical XOR of the two specified bit operands The flag contains the original value of the specified bit operand The flag c
54. Rb Rw or 79 2 ORB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 6A 4 BAND bitaddr bitaddr 7A 4 BXOR bitaddr bitaddr 6B 2 DIVL Rw 7B 2 DIVLU Rw 6C 2 SHR Rw Rw 7C 2 SHR Rw data4 6D 2 JMPR cc_N rel 7D 2 JMPR cc_NN rel 6E 2 BCLR bitoff 6 7E 2 BCLR bitoff 7 6F 2 BSET bitoff 6 7F 2 BSET bitoff 7 User s Manual 26 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Encoding D D 3 Mnemonic Operands 3 Mnemonic Operands x ia x M 80 2 CMPI1 Rw data4 90 2 CMPI2 Rw data4 81 2 NEG Rw 91 12 CPL Rw 82 4 CMPI1 Rw mem 92 14 CMPI2 Rw mem 83 l 93 84 4 MOV Rw mem 94 4 MOV mem Rw 85 l 95 86 14 CMPI11 Rw data16 96 4 CMPI2 Rw data16 87 4 IDLE 97 14 PWRDN 88 2 MOV Rw Rw 98 2 MOV Rw Rw 89 2 MOVB Rw Rb 99 2 MOVB Rb Rw 8A 14 JB bitaddr rel 9A 4 JNB bitaddr rel 8B 9B 2 TRAP trap7 8C l 9C 2 JMPI cc Rw 8D 2 JMPR cc_C rel or 9D 2 JMPR cc_NC rel or cc_ULT rel cc_UGE rel 8E 2 BCLR bitoff 8 9E 2 BCLR bitoff 9 8F 2 BSET bitoff 8 OF 2 BSET bitoff 9 User s Manual 27 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Encoding D D 3 Mnemonic Operands 3 Mnemonic Operands x ia x
55. Rw Rw 1C 2 ROL Rw data4 OD 2 JMPR cc UC rel 1D 2 JMPR cc_NET rel OE 2 BCLR bitoff 0 1E 2 BCLR bitoff 1 OF 2 BSET bitoff 0 1F 12 BSET bitoff 1 User s Manual 23 V2 0 2001 03 o C166 Family nfineon technologies Instruction Set Encoding g g 3 Mnemonic Operands 3 Mnemonic Operands x Im I ja 20 2 SUB Rw Rw 30 2 SUBC Rw Rw 21 2 SUBB Rb Rb 31 2 SUBCB Rb Rb 22 4 SUB reg mem 32 SUBC reg mem 23 4 SUBB reg mem 33 4 SUBCB reg mem 24 4 SUB mem reg 34 4 SUBC mem reg 25 4 SUBB mem reg 35 4 SUBCB mem reg 26 4 SUB reg data16 36 4 SUBC reg data16 27 4 SUBB reg data8 37 4 SUBCB reg data8 28 2 SuUB Rw Rw or 38 2 SUBC Rw Rw or Rw Rw or Rw Rw or Rw data3 Rw data3 29 2 SUBB Rb Rw or 39 2 SUBCB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 2A 4 BCMP bitaddr bitaddr 3A 4 BMOVN bitaddr bitaddr 2B 2 PRIOR Rw Rw 3B l 2C 2 ROR Rw Rw 3C 2 ROR Rw data4 2D 2 JMPR cc_EQ rel or 3D 2 JMPR cc NE rel or cc_Z rel cc NZ rel 2E 2 BCLR bitoff 2 3E 2 BCLR bitoff 3 2F 2 BSET bitoff 2 3F 2 BSET bitoff 3 User s Manual 24 V2 0 2001 03 o i C166 Family nfineon technologies Instruction Set Encoding D D 3 Mnemonic Operands 3 Mnemonic
56. S Return from inter segment subroutine 2 RETP reg Return from intra segment subroutine and 2 pop direct word register from system stack RETI Return from interrupt service subroutine 2 System Control SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode supposes NMI pin being low 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End of Initialization on RSTOUT pin 4 ATOMIC irang2 Begin ATOMIC sequence 2 EXTR irang2 Begin EXTended Register sequence 2 EXTP Rw irang2 Begin EXTended Page sequence 2 EXTP pag10 Begin EXTended Page sequence 4 irang2 EXTPR Rw irang2 Begin EXTended Page and Register sequence 2 EXTPR pag10 Begin EXTended Page and Register sequence 4 irang2 EXTS Rw irang2 Begin EXTended Segment sequence 2 EXTS seg8 Begin EXTended Segment sequence 4 irang2 EXTSR Rw irang2 Begin EXTended Segment and Register sequence 2 EXTSR_ seg8 Begin EXTended Segment and Register sequence 4 irang2 User s Manual 20 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Summary Table 4 Instruction Set Summary cont d Mnemonic Description Bytes System Stack Instructions POP reg Pop direct word register from system stack 2 PUSH reg Push direct word register onto system stack 2 SCXT reg data16 Push direct word register onto system stack and 4 update register with immediate data SCXT reg mem Push dire
57. Subtract direct word GPR from direct GPR with Carry 2 SUBC Rw Rw Subtract indirect word memory from direct GPR with 2 Carry SUBC Rw Rw Subtract indirect word memory from direct GPR with 2 Carry and post increment source pointer by 2 SUBC Rw data3 Subtract immediate word data from direct GPR with 2 Carry SUBC reg data16 Subtract immediate word data from direct register with 4 Carry SUBC reg mem Subtract direct word memory from direct register with 4 Carry User s Manual 11 V2 0 2001 03 TT e nfineon C166 Family technologies Instruction Set Summary Table 4 Instruction Set Summary con d Mnemonic Description Bytes Arithmetic Operations cont d SUBC mem reg Subtract direct word register from direct memory with 4 Carry SUBCB Rb Rb Subtract direct byte GPR from direct GPR with Carry 2 SUBCB Rb Rw Subtract indirect byte memory from direct GPR with 2 Carry SUBCB Rb Rw Subtract indirect byte memory from direct GPR with 2 Carry and post increment source pointer by 1 SUBCB Rb data3 Subtract immediate byte data from direct GPR with 2 Carry SUBCB reg data8 Subtract immediate byte data from direct register with 4 Carry SUBCB reg mem Subtract direct byte memory from direct register with 4 Carry SUBCB mem reg Subtract direct byte register from direct memory with 4 Carry MUL Rw Rw Signed multiply direct GPR by direct GPR 2
58. Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description 32 by 16 Signed Division DIVL DIVL op1 MDRIU 1 MDL MD op1 MDH MD mod 0p1 WORD DOUBLEWORD Performs an extended signed 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH DIVL is interruptable Please see additional description on Page 40 E Z V C N 0 ij S 0 ii Always cleared Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred i e the quotient cannot be represented in a word data type or if the divisor 091 was zero the result in MDH and MDL is not valid in this case Cleared otherwise Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes DIVL Rwy 6B nn 2 73 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set DIVLU Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description 32 by 16 Unsigned Division DIVLU DIVLU opt MDRIU 1 MDL MD op1 MDH MD mod 0p1 WORD DOUBLEWORD Performs an extended unsign
59. User s Manual V2 0 Mar 2001 Instruction Set Manual for the C166 Family of Infineon 16 Bit Single Chip Microcontrollers Microcontrollers Never stop thinking Edition 2001 03 Published by Infineon Technologies AG St Martin Strasse 53 D 81541 Munchen Germany Infineon Technologies AG 2001 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effective
60. WRDN Syntax Operation Description Note Condition Flags Addressing Modes User s Manual C166 Family Instruction Set Enter Power Down Mode PWRDN Enter Power Down Mode Detailed Description PWRDN This instruction causes the part to enter the power down mode In this mode all peripherals and the CPU are powered down until the part is externally reset To further control the action of this instruction the PWRDN instruction is only enabled when the non maskable interrupt pin NMI is in the low state Otherwise this instruction has no effect To insure that this instruction is not accidentally executed it is implemented as a protected instruction E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes PWRDN 97 68 97 97 4 112 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set RET Syntax Operation Description Condition Flags Addressing Modes User s Manual Detailed Description Return from Subroutine RET RET IP lt SP SP SP 2 Returns from a subroutine The IP is popped from the system stack Execution resumes at the instruction following the CALL instruction in the calling routine E Z V C N Not affected Not affected Not affected Not affected 2 O lt s NM Not affected Mnemonic Format Bytes
61. age FOR loops of any range E Z V C N S E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPI1 Rw data4 80 n 2 CMPI1 Rw data16 86 Fn 4 CMPI1 Rw mem 82 Fn MM MM 4 67 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CMPI2 Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Integer Compare and Increment by 2 CM P 2 CMPI2 0p1 op2 op1 lt op2 op1 op1 2 WORD This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is incremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range E
62. and specified by op2 the destination operand specified by op1 and the previously generated carry bit The sum is then stored in op1 This instruction can be used to perform multiple precision arithmetic E Z V C N S E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Setif an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic ADDC Rw RWm ADDC Rw Rwi ADDC Rw Rw ADDC Rw data3 ADDC reg data16 ADDC reg mem ADDC mem reg 43 Format 10 nm 18 n 10ii 18 n 11ii 18 n O 16 RR 12 RR MM MM 14 RR MM MM Bytes 2 RA KRM ND V2 0 2001 03 o nfineon technologies ADDCB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual C166 Family Instruction Set Integer Addition with Carry ADDCB 0p1 0p1 op2 C BYTE op1 op2 Detailed Description ADDCB Performs a 2 s complement binary addition of the source operand specified by op2 the destination oper
63. and specified by op1 and the previously generated carry bit The sum is then stored in op1 This instruction can be used to perform multiple precision arithmetic E Z V C N S E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Setif an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic ADDCB Rb Rb ADDCB Rb Rw ADDCB _Rb Rw ADDCB Rb data3 ADDCB reg data8 ADDCB reg mem ADDCB men reg 44 Format 11 nm 19 n 10ii 19 n 11ii 19 n O 17 RR xx 13 RR MM MM 15 RR MM MM Bytes 2 RA KRM ND V2 0 2001 03 o nfineon technologies C166 Family Instruction Set AND Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Logical AND AND AND opi op2 op1 lt op op2 WORD Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E Z V C N
64. bit short GPR address Rw or Rb 4 bit position of the source bit within the word specified by QQ 4 bit position of the destination bit within the word specified by ZZ 4 bit immediate constant data4 7 bit trap number trap7 8 bit word address of the source bit bitoff 8 bit relative target address word offset rel 8 bit word address reg 8 bit word address of the destination bit bitoff 8 bit immediate constant data8 8 bit immediate constant represented by data16 where byte xx is not significant 8 bit immediate constant mask8 16 bit address mem or caddr low byte high byte 16 bit immediate constant data16 low byte high byte 1 For the SAB 8xC166 devices the segment number is a 2 bit value ss due to the smaller addressing range of 256 KByte compared to 16 MByte User s Manual 37 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Detailed Description Condition Code Some instructions JUMP CALL are executed only if a specific condition is true and are skipped otherwise The condition which has to be fulfilled for the execution of the respective instruction is specified in the so called condition code Table 5 summarizes the 16 possible condition codes that can be used within Call and Branch instructions The table shows the mnemonic abbreviations the test that is executed for a specific condition and the internal representation by a 4 bit number
65. bler compiler etc This instruction set manual provides an easy and direct access to the instructions of the Infineon 16 bit microcontrollers by listing them according to different criteria and also unloads the technical manuals for the different devices from redundant information This manual also describes the different addressing mechanisms and the relation between the logical addresses used in a program and the resulting physical addresses There is also information provided to calculate the execution time for specific instructions depending on the used address locations and also specific exceptions to the standard rules Description Levels In the following sections the instructions are compiled according to different criteria in order to provide different levels of precision e Cross Reference Tables summarize all instructions in condensed tables e The Instruction Set Summary groups the individual instructions into functional groups e The Opcode Table references the instructions by their hexadecimal opcode e The Instruction Description describes each instruction in full detail User s Manual 1 V2 0 2001 03 o C166 Family Infineon TE EA Introduction All instructions listed in this manual are executed by the following devices new derivatives will be added to this list C161K C1610 C161PI C161CS C161JC C161 C163 C164Cl C164SI C164CM C164SM C165 C167CR C167SR e C167CS A few instructions
66. changed E Z V C N S E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic CMPB Rb Rbm CMPB Rb Rwi CMPB Rb Rw CMPB Rb data3 CMPB reg data8 CMPB reg mem 64 Format 41 nm 49 n 10ii 49 n 11ii 49 n O 47 RR xx 43 RR MM MM Bytes 2 2 2 4 4 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CMPD1 Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Integer Compare and Decrement by 1 CM PD1 CMPD1 opt op2 0p1 op2 op1 lt opt 1 WORD This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is decremented by one Using the set flags a branch instruction can then be u
67. cription Sets the bit specified by op1 This instruction is primarily used for peripheral and system control Condition E Z V C N Flags 0 B 0 0 B Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared Always cleared N Contains the previous state of the specified bit Addressing Mnemonic Format Bytes Modes BSET bitaddrg q qF QQ 2 User s Manual 57 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set BXOR Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Bit Logical XOR BXOR BXOR op1 op2 0p1 lt op1 op2 BIT Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2 with the destination bit specified by operand op1 The XORed result is then stored in op1 E Z V C N 0 NOR OR AND XOR Always cleared Contains the logical NOR of the two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits z O lt NM Contains the logical XOR of the two specified bits Mnemonic Format Bytes BXOR bitaddrz z bitaddrgg 7A QQ ZZ qz 4 58 V2 0 2001 03 TT e e nfineon technologies CALLA Syntax Operation Description Note Condition Flags Addressing Modes User s Manual C166 Fam
68. ct word register onto system stack and 4 update register with direct memory Miscellaneous NOP Null operation 2 1 The ATOMIC and EXTended instructions are not available in the SAB 8XC166 W devices User s Manual 21 V2 0 2001 03 o C166 Family Infineon Frente Sas Encoding 4 Encoding The following pages list the instructions of the 16 bit microcontrollers ordered by their hexadecimal opcodes This helps to identify specific instructions when reading executable code i e during the debugging phase The explanations below should help to read the tables on the following pages Extended Opcodes 1 These instructions ADD C B SUB C B CMP B AND B X OR B are encoded by means of additional bits 1 2 in the operand field of the instruction For these instructions only the lowest four GPRs RO to R3 can be used as indirect address pointers nnnn O p Rw data3 or Rb data3 nnnn 1Oiip Rw Rwi or Rb Rwi nnnn 1 tiip Rw Rw or Rb Rw 2 The following instructions are encoded by means of two additional bits in the operand field of the instruction Note The ATOMIC and EXTended instructions are not available in the SAB 8XC 166 W devices 00xx XXXXg EXTS or ATOMIC 01Xx XXXXxg EXTP 10xx XXXXg EXTSR or EXTR 11XX XXxXXp EXTPR Conditional JMPR Instructions The condition code to be tested for the JMPR instructions is specified by the opcode Two mnemonic representati
69. cution both standard PEC interrupts and class A hardware traps are locked The EXTSR instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTSR instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bits A15 AO The value of op2 defines the length of the effected instruction sequence Please see additional notes on Page 39 The EXTSR instruction is not available in the SAB 8XC166 W devices 84 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set EXTSR Condition Flags Addressing Modes User s Manual continued Detailed Description EXTSR zo lt N om Mnemonic EXTSR Rwm irang2 EXTSR seg irang2 Not affected Not affected Not affected Not affected Not affected 85 Format Bytes DC 10 m 2 D7 10 0 SS 00 4 V2 0 2001 03 o C166 Family Infineon TE Sas Detailed Description IDLE Enter Idle Mode IDLE Syntax IDLE Operation Enter Idle Mode Description This instruction causes the device to enter idle mode or sleep mode if provided by the device In both modes the CPU is powered down In idle mode the peripherals remain running while in sleep mode also the peripherals a
70. d V Not affected C Not affected N Not affected Addressing Mnemonic Format Bytes Modes SRVWDT A7 58 A7 A7 4 Users Manual 124 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set SUB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Integer Subtraction SUB op1 op2 0p1 lt op op2 WORD Detailed Description SUB Performs a 2 s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1 The result is then stored in op1 E Z V C N S E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic SUB Rw RWm SUB Rw Rwi SUB Rw Rw SUB Rw data3 SUB reg data16 SUB reg mem SUB mem reg 125 Format 20 nm 28 n 10ii 28 n 11ii 28 n 0 26 RR 22 RR MM MM 24 RR MM MM Bytes 2 AR ABRKRMODND V2 0 2001 03 o nfineon technologies C166 Family Instruction Set SUBB Syntax Operation Data Type
71. d by op1 E Z V C N Not affected Not affected Not affected Not affected 2 O lt s NM Not affected Mnemonic Format Bytes JMPS seg caddr FA SS MM MM 4 92 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set JNB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Relative Jump if Bit Clear JNB JNB op1 op2 IF op1 0 THEN IP lt IP sign extend op2 ELSE Next Instruction END IF BIT If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNB instruction If the specified bit is set the instruction following the JNB instruction is executed E Z V Cc N Not affected Not affected Not affected Not affected zo lt s NM Not affected Mnemonic Format Bytes JNB bitaddrg q rel 9A QQ rr q0 4 93 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set JNBS Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Relative Jump
72. direct GPR 2 ADD reg datai6 Add immediate word data to direct register 4 ADD reg mem Add direct word memory to direct register 4 ADD mem reg Add direct word register to direct memory 4 ADDB Rb Rb Add direct byte GPR to direct GPR 2 ADDB Rb Rw Add indirect byte memory to direct GPR 2 ADDB Rb Rw Add indirect byte memory to direct GPR and 2 post increment source pointer by 1 ADDB Rb data3 Add immediate byte data to direct GPR 2 ADDB reg data8 Add immediate byte data to direct register 4 ADDB reg mem Add direct byte memory to direct register 4 ADDB men reg Add direct byte register to direct memory 4 ADDC Rw Rw Add direct word GPR to direct GPR with Carry 2 ADDC Rw Rw Add indirect word memory to direct GPR with Carry 2 ADDC Rw Rw Add indirect word memory to direct GPR with Carry and 2 post increment source pointer by 2 ADDC Rw data3 Add immediate word data to direct GPR with Carry 2 ADDC reg data16 Add immediate word data to direct register with Carry 4 ADDC reg mem Add direct word memory to direct register with Carry 4 ADDC mem reg Add direct word register to direct memory with Carry 4 ADDCB Rb Rb Add direct byte GPR to direct GPR with Carry 2 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry 2 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry and 2 post increment source pointer by 1 ADDCB Rb data3 Add immediate byte data to direct GPR with Carry 2 Users Manual 10 V2 0 2001
73. e Please see additional description on Page 40 E Z V C N 0 ig S 0 i Always cleared Z Set if the result equals zero Cleared otherwise This bit is set if the result cannot be represented in a word data type Cleared otherwise Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes MULU Rw RWm 1B nm 2 102 V2 0 2001 03 o C166 Family Infineon TE Sas Detailed Description N EG Integer Two s Complement N EG Syntax NEG op1 Operation op1 0 op Data Types WORD Description Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in op1 Condition E Z V C N Flags S E Setifthe value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Mnemonic Format Bytes Modes NEG Rw 81 n0 2 User s Manual 103 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set NEGB Syntax Operation Data Types Description Condition Flags Addressing M
74. e current segment Branches MAY NOT be taken to odd code addresses Therefore the least significant bit of caddr must always contain a 0 otherwise a hardware trap would occur This mnemonic represents an 8 bit signed word offset address relative to the current Instruction Pointer contents which points to the instruction after the branch instruction Depending on the offset address range either forward rel 004 to 7Fp or backward rel 804 to FF4 branches are possible The branch instruction itself is repeatedly executed when rel 1 FF for a word sized branch instruction or rel 2 FE for a double word sized branch instruction In this case the 16 bit branch target instruction address is determined indirectly by the content of a word GPR In contrast to indirect data addresses indirectly specified code addresses are NOT calculated via additional pointer registers e g DPP registers Branches MAY NOT be taken to odd code addresses Therefore the least significant bit of the address pointer GPR must always contain a 0 otherwise a hardware trap would occur Specifies an absolute code segment number 256 different code segments are supported where the eight bits of the seg operand value are used for updating the lower half of register CSP Note The SAB 8XC166 W devices support only 4 different code segments where only the two lower bits of the seg operand val
75. e memory to direct GPR 2 MOVB Rb Rw Move indirect byte memory to direct GPR and 2 post increment source pointer by 1 MOVB Rw Rb Move direct byte GPR to indirect memory 2 MOVB Rw Rb Pre decrement destination pointer by 1 and move 2 direct byte GPR to indirect memory MOVB Rw Rw Move indirect byte memory to indirect memory 2 MOVB Rw Rw Move indirect byte memory to indirect memory and 2 post increment destination pointer by 1 MOVB Rw Rw Move indirect byte memory to indirect memory and 2 post increment source pointer by 1 MOVB Rb Move indirect byte memory by base plus constant 4 Rw d16 to direct byte GPR MOVB Rw d16 Move direct byte GPR to indirect memory by base 4 Rb plus constant MOVB Rw mem Move direct byte memory to indirect memory 4 MOVB mem Rw Move indirect byte memory to direct memory 4 MOVB reg mem Move direct byte memory to direct register 4 MOVB mem reg Move direct byte register to direct memory 4 User s Manual 18 V2 0 2001 03 o nfineon C166 Family C technologies gt Instruction Set Summary Table 4 Instruction Set Summary contd Mnemonic Description Bytes Data Movement cont d MOVBS Rw Rb Move direct byte GPR with sign extension to 2 direct word GPR MOVBS reg mem Move direct byte memory with sign extension to 4 direct word register MOVBS mem reg Move direct byte register with sign ex
76. e see additional description on Page 40 E Z V C N 0 ij S 0 Always cleared Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred i e if the divisor op1 was zero the result in MDH and MDL is not valid in this case Cleared otherwise Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes DIVU Rwy 5B nn 2 75 V2 0 2001 03 o C166 Family Infineon factual eek Detailed Description EINIT End of Initialization EINIT Syntax EINIT Operation End of Initialization Description This instruction is used to signal the end of the initialization portion of a program After a reset the reset output pin RSTOUT is pulled low It remains low until the EINIT instruction has been executed at which time it goes high This enables the program to signal the external circuitry that it has successfully initialized the microcontroller After the EINIT instruction has been executed execution of the Disable Watchdog Timer instruction DISWDT has no effect Note To insure that this instruction is not accidentally executed it is implemented as a protected instruction Condition E Z V C N Flags E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Mnemonic Format Bytes Modes EINIT B5 4A B5 B5 4 User s Manual 76 V2 0 2001 03 TT e e nfine
77. ed 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH DIVLU is interruptable Please see additional description on Page 40 E Z V C N 0 ij S 0 ii Always cleared Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred i e the quotient cannot be represented in a word data type or if the divisor 091 was zero the result in MDH and MDL is not valid in this case Cleared otherwise Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes DIVLU Rwy 7B nn 2 74 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set DIVU Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description 16 by 16 Unsigned Division DIVU DIVU opt MDRIU 1 MDL MDL 0p1 MDH lt MDL mod op1 WORD Performs an unsigned 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH DIVU is interruptable Pleas
78. en stored in op1 This instruction can be used to perform multiple precision arithmetic E Z V C N S S E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SUBCB Rb Rb 31 nm 2 SUBCB _Rb Rw 39 n 10ii 2 SUBCB _Rb Rw 39 n 11ii 2 SUBCB Rb data3 39 n O 2 SUBCB reg data8 37 RR xx 4 SUBCB reg mem 33 RR MM MM 4 SUBCB mem reg 35 RR MM MM 4 128 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set TRAP Syntax Operation Description Condition Flags Addressing Modes User s Manual Detailed Description Software Trap TRA P TRAP op1 SP lt SP 2 SP PSW IF SYSCON SGTDIS 0 THEN SP SP 2 SP CSP CSP 0 END IF SP lt SP 2 SP lt IP IP zero extend op1 x 4 Invokes a trap or interrupt routine based on the specified operand op1 The invoked routine is determined by branching to the specified vector table entry point This routine has no
79. f either two for demultiplexed external bus modes or three for multiplexed external bus modes state times plus a number of state times which is determined by the number of waitstates programmed in the MCTC Memory Cycle Time Control and MTTC Memory Tristate Time Control bit fields of the SYSCON BUSCONx registers In case of demultiplexed external bus modes 1ACT 2 15 MCTC 1 MTTC States 80 ns 720 ns for fopy 25 MHz In case of multiplexed external bus modes 1ACT 3 15 MCTC 1 MTTC States 120 ns 760 ns for fopy 25 MHz The total time Ty which a particular part of a program takes to be processed can be calculated by the sum of the single instruction processing times Ty of the considered instructions plus an offset value of 6 state times which considers the solitary filling of the pipeline as follows Tiot Ti Tyo TIN 6 States The time Tiy which a single instruction takes to be processed consists of a minimum number of instruction states Timin plus an additional number of instruction states and or ALE Cycle Times Tjaqq as follows Tin Timin Tiada Users Manual 142 V2 0 2001 03 o C166 Family Infineon Tre Sas Instruction State Times 7 2 Minimum Execution Time The minimum number of state times to process an instruction is required if the instruction is fetched from the internal program memory Timin PM The minimum number of state times
80. fineon C166 Family C technologies Instruction Set Summary Table 4 Instruction Set Summary cont d Mnemonic Description Bytes Boolean Bit Manipulation Operations BCLR _ baddr Clear direct bit 2 BSET baddr Set direct bit 2 BMOV baddr baddr Move direct bit to direct bit 4 BMOVN baddr baddr Move negated direct bit to direct bit 4 BAND baddr baddr AND direct bit with direct bit 4 BOR baddr baddr OR direct bit with direct bit 4 BXOR baddr baddr XOR direct bit with direct bit 4 BCMP baddr baddr Compare direct bit to direct bit 4 BFLDH bitoff Bitwise modify masked high byte of bit addressable 4 mask8 data8 direct word memory with immediate data BFLDL bitoff Bitwise modify masked low byte of bit addressable 4 mask8 data8 direct word memory with immediate data CMP Rw Rw Compare direct word GPR to direct GPR 2 CMP Rw Rw Compare indirect word memory to direct GPR 2 CMP Rw Rw Compare indirect word memory to direct GPR and 2 post increment source pointer by 2 CMP Rw data3 Compare immediate word data to direct GPR 2 CMP reg datai6 Compare immediate word data to direct register 4 CMP reg mem Compare direct word memory to direct register 4 CMPB Rb Rb Compare direct byte GPR to direct GPR 2 CMPB Rb Rw Compare indirect byte memory to direct GPR 2 CMPB Rb Rw Compare indirect byte memory to direct GPR and 2 post increment source pointer by 1 CMPB_ Rb data3 Compare immediate byte data to direct GPR 2 CMPB reg
81. fineon C166 Family C technologies Instruction Set Overviews Table 1 Instruction Overview ordered by Hex Code lower half 0x 1x 2X 3x 4x 5x 6x 7X x0 ADD ADDC SUB SUBC CMP XOR AND OR x1 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x2 ADD ADDC SUB SUBC CMP XOR AND OR x3 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x4 ADD ADDC SUB SUBC XOR AND OR x5 ADDB ADDCB SUBB SUBCB XORB ANDB ORB x6 ADD ADDC SUB SUBC CMP XOR AND OR x7 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x8 ADD ADDC SUB SUBC CMP XOR AND OR x9 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB xA BFLDL BFLDH BCMP BMOVN BMOV BOR BAND BXOR xB MUL MULU PRIOR DIV DIVU DIVL DIVLU xC ROL ROL ROR ROR SHL SHL SHR SHR xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET Users Manual 4 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Overviews Table 2 Instruction Overview ordered by Hex Code upper half 8x 9x Ax Bx Cx Dx Ex Fx x0 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV MOV ATOMIC x1 NEG GPL NEGB CPLB EXTR MOVB MOVB x2 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL MOV x3 7 z MOVB x4 MOV MOV MOVB MOVB MOV MOV MOVB MOVB x5 DISWDT EINIT MOVBZ MOVBS x6 CMPI1 C
82. following data types are possible BIT BYTE WORD DOUBLEWORD Except for those instructions which extend byte data to word data all instructions have only one particular data type Note that the data types mentioned in this subsection do not consider accesses to indirect address pointers or to the system stack which are always performed with word data Moreover no data type is specified for System Control Instructions and for those of the branch instructions which do not access any explicitly addressed data Description This part provides a brief verbal description of the action that is executed by the respective instruction Also hints are given on using the instruction itself its operands and its flags Note In some cases additional notes point out special circumstances These notes shall help the user to avoid faulty operation of his her software Conditional instructions refer here to the condition codes listed in Table 5 Condition Flags This part reflects the state of the N C V Z and E flags in the PSW register which is the state after execution of the corresponding instruction except if the PSW register itself was specified as the destination operand of that instruction see Note The condition flags are displayed in the way they appear in register PSW PSW Processor Status Word SFR FF10 88 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HLD US
83. for instructions fetched from the internal RAM Timin RAM or of ALE Cycle Times for instructions fetched from the external memory Timin ext can be easily calculated by adding the indicated additional times Most of the 16 bit microcontroller instructions require a minimum of two state times except some of the branches the multiplication the division and a special move instruction In case of execution from internal program memory there is no execution time dependency on the instruction length except for some special branch situations The injected target instruction of a cache jump instruction can be considered for timing evaluations as if being executed from the internal program memory regardless of which memory area the rest of the current program is really fetched from For some of the branch instructions Table 11 represents two execution times e standard execution time for a taken branch e reduced execution time for a branch which is not taken because the specified condition is not met which can be serviced by the jump cache The respective longer execution time result from the fact that after a taken branch the current instruction stream is broken and the pipeline has to be refilled Table 11 Minimum Instruction State Times Unit States ns Instruction s Timin PM States Timin PM ns 25 MHz CALLI CALLA 4or2 160 or 80 CALLS CALLR PCALL 4 160 JB JBC JNB JNBS 4or2 160
84. g data8 Bitwise OR immediate byte data with direct register 4 ORB reg mem Bitwise OR direct byte memory with direct register 4 ORB mem reg Bitwise OR direct byte register with direct memory 4 XOR Rw Rw Bitwise XOR direct word GPR with direct GPR 2 XOR Rw Rw Bitwise XOR indirect word memory with direct GPR 2 XOR Rw Rw Bitwise XOR indirect word memory with direct GPR and 2 post increment source pointer by 2 XOR Rw data3 Bitwise XOR immediate word data with direct GPR 2 XOR reg datai6 Bitwise XOR immediate word data with direct register 4 XOR reg mem Bitwise XOR direct word memory with direct register 4 XOR mem reg Bitwise XOR direct word register with direct memory 4 XORB Rb Rb Bitwise XOR direct byte GPR with direct GPR 2 XORB Rb Rw Bitwise XOR indirect byte memory with direct GPR 2 XORB Rb Rw Bitwise XOR indirect byte memory with direct GPR and 2 post increment source pointer by 1 XORB Rb data3 Bitwise XOR immediate byte data with direct GPR 2 XORB reg data8 Bitwise XOR immediate byte data with direct register 4 XORB reg mem Bitwise XOR direct byte memory with direct register 4 XORB mem reg Bitwise XOR direct byte register with direct memory 4 Prioritize Instruction PRIOR Rw Rw Determine number of shift cycles to normalize direct 2 word GPR and store result in direct word GPR Users Manual 14 V2 0 2001 03 o n
85. g mode is referred to by the mnemonic mem Table 7 Long Addressing Mnemonic Physical Address Long Address Scope of Access Range mem DPPO Il mema3FFFy 00004 SFFFy Any Word or Byte DPP1 Il mema3FFFy 40004 7FFF DPP2 I mema3FFF 8000 BFFF DPP3 Il mema3FFFy C000 FFFF mem pag Il mema3FFFy 00004 FFFF Any Word or Byte 14 bit mem seg Il mem 00004 FFFFy Any Word or Byte 16 bit 6 3 Indirect Addressing Modes These addressing modes can be regarded as a combination of short and long addressing modes This means that long 16 bit addresses are specified indirectly by the contents of a word GPR which is specified directly by a short 4 bit address Rw 0 to 15 There are indirect addressing modes which add a constant value to the GPR contents before the long 16 bit address is calculated Other indirect addressing modes allow decrementing or incrementing the indirect address pointers GPR content by 2 or 1 referring to words or bytes In each case one of the four DPP registers is used to specify physical 24 bit addresses 18 bit for the SAB 8XC166 W devices Any word or byte data within the entire memory space can be addressed indirectly Note The exceptions for instructions EXTP R and EXTS R i e overriding the DPP mechanism apply in the same way as described for the long addressing modes Some instructions only use the lowest four word GPRs R R3 RO as ind
86. he lower four bits of reg are significant for physical address generation and thus it can be regarded as being identical to the address generation described for the Rb and Rw addressing modes bitoff Specifies direct access to any word in the bit addressable memory space bitoff requires eight bits in the instruction format Depending on the specified bitoff range different base addresses are used to generate physical addresses Short bitoff addresses from 004 to 7F4 use 00 FD00 as a base address and thus they specify the 128 highest internal RAM word locations 00 FD004 to 00 FDFE Short bitoff addresses from 804 to EF use 00 FF004 as a base address to specify the highest internal SFR word locations 00 FF00 to 00 FFDE or use 00 F 100 as a base address to specify the highest internal ESFR word locations 00 F100 to 00 F1DE bitoff accesses to the ESFR area require a preceding EXT R instruction to switch the base address not available in the SAB 8XC166 W devices For short bitoff addresses from FO to FFy only the lowest four bits and the contents of the CP register are used to generate the physical address of the selected word GPR bitaddr Any bit address is specified by a word address within the bit addressable memory space see bitoff and by a bit position bitpos within that word Thus bitaddr requires twelve bits in the instruction format User
87. ily Instruction Set Call Subroutine Absolute CALLA IF 091 THEN SP SP 2 SP IP IP op2 ELSE next instruction END IF If the condition specified by op1 is met a branch to the absolute memory location specified by the second operand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally The condition codes for op1 are defined in Table 5 E Z op1 op2 V C N z O lt s NM Not affected Not affected Not affected Not affected Not affected Mnemonic CALLA cc caddr 59 CA c0 MM MM Detailed Description CALLA Bytes 4 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set CALLI Syntax Operation Description Note Condition Flags Addressing Modes User s Manual Detailed Description Call Subroutine Indirect CALLI CALLI op1 op2 IF op1 THEN SP SP 2 SP IP IP op2 ELSE next instruction END IF If the condition specified by op1 is met a branch to the location specified indirectly by the second operand op2 is taken The value of the instruction pointer IP is placed
88. ily Instruction Set ROL Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Rotate Left R O L ROL op1 op2 count op2 C 0 DO WHILE count 0 C 0p145 op1 op1n 1 n 1 15 0p10 C count count 1 END WHILE WORD Rotates the destination word operand op1 left by as many times as specified by the source operand op2 Bit 15 is rotated into Bit 0 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Z V C N 0 0 S ii Always cleared Set if result equals zero Cleared otherwise Always cleared O lt s NM The carry flag is set according to the last MSB shifted out of op1 Cleared for a rotate count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ROL Rw RWm OC nm 2 ROL Rw data4 1C n 2 117 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set ROR Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Rotate Right ROR ROR op1 op2 count lt op2 C 0 V 0 DO WHILE count 0 V V v C C opto op1 0p1y44 IN 0 14 0p145 C count
89. in the OR mask specified by ops op1 bits which shall remain unchanged must have a 0 in the respective bit of both the AND mask op2 and the OR mask op3 Otherwise a 1 in op3 will set the corresponding op1 bit see Operation If the target operand op1 features bit protection only the bits marked by a 1 in the mask operand op2 will be updated E Z V C N 0 i 0 0 Always cleared Set if the word result equals zero Cleared otherwise Always cleared Always cleared zo lt s NM Set if the most significant bit of the word result is set Cleared otherwise Mnemonic Format Bytes BFLDH _bitoffg mask8 data8 1A QQ 4 52 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set BFLDL Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description Bit Field Low Byte BFLDL BFLDL op1 op2 op3 tmp op1 low byte tmp low byte tmp sop2 v op3 op1 lt tmp WORD Replaces those bits in the low byte of the destination word operand op1 which are selected by a 1 in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by ops op1 bits which shall remain unchanged must have a 0 in the respective bit of both the AND mask op2 and the OR mask op3 Otherwise a 1 in op3 will set the corresponding op1 bit see
90. indication of whether it was called by software or hardware System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected The RETI return from interrupt instruction is used to resume execution after the trap or interrupt routine has completed The CSP is pushed if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register E Z V C N Not affected Not affected Not affected Not affected zZz O lt s NM Not affected Mnemonic Format Bytes TRAP trap7 OB t tttO 2 129 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set XOR Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Logical Exclusive OR XOR op1 op2 op1 op1 op2 WORD Detailed Description XOR Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E Z V C E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z V Always cleared C Always cleared N otherwise Mnemonic XOR Rwp RWm XOR Rw Rw XOR Rw Rw XOR Rw data3 XOR reg data16 XOR reg mem XOR mem reg 130 Set if result equals zero Cleared otherwise For
91. irect address pointers which are specified via short 2 bit addresses in that case Note Word accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP registers are initialized in a way that all indirect long addresses are directly mapped onto the identical physical addresses User s Manual 135 V2 0 2001 03 o C166 Family Infineon TE E Addressing Modes Physical addresses are generated from indirect address pointers via the following algorithm 1 Calculate the physical address of the word GPR which is used as indirect address pointer using the specified short address Rw and the current register bank base address CP GPR Address CP 2 x Short Address Pre decremented indirect address pointers Rw are decremented by a data type dependent value A 1 for byte operations A 2 for word operations before the long 16 bit address is generated GPR Address GPR Address A optional step Calculate the long 16 bit address by adding a constant value if selected to the content of the indirect address pointer Long Address GPR Pointer Constant Calculate the physical 24 bit or 18 bit address using the resulting long address and the corresponding DPP register content see long mem addressing modes Physical Address DPPi Page offset Post Incremented indirect address pointers Rw are incremented by a da
92. logies C166 Family Instruction Set EXTPR Syntax Operation Description Note User s Manual Detailed Description Begin EXTended Page and EXTPR Register Sequence EXTPR 0op1 op2 count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Page op1 AND SFR_range Extended DO WHILE count 0 AND Class B trap condition TRUE Next Instruction count lt count 1 END WHILE count 0 Data_Page DPPx AND SFR_range Standard Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard PEC interrupts and class A hardware traps are locked For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 AO is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence Please see additional notes on Page 39 The EXTPR instruction is not available in the SAB 8XC166 W devices 80 V2 0 2001 03 TT e e nfineon technologies C166 Family Instructi
93. m reg C5 RR MM MM 4 100 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set MUL Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description Signed Multiplication M U L MUL op1 op2 MDRIU 1 MD lt 0p1 x op2 WORD Performs a 16 bit by 16 bit signed multiplication using the two words specified by operands op1 and op2 respectively The signed 32 bit result is placed in the MD register MUL is interruptable Please see additional description on Page 40 E Z V C N 0 ig S 0 i Always cleared Z Set if the result equals zero Cleared otherwise This bit is set if the result cannot be represented in a word data type Cleared otherwise Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes MUL Rw RWm OB nm 2 101 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set MULU Syntax Operation Data Types Description Note Condition Flags Addressing Modes User s Manual Detailed Description Unsigned Multiplication M U LU MULU op1 op2 MDRIU 1 MD lt 0p1 x op2 WORD Performs a 16 bit by 16 bit unsigned multiplication using the two words specified by operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register MULU is interruptabl
94. mat 50 nm 58 n 10ii 58 n 11ii 58 n 0 56 RR 52 RR MM MM 54 RR MM MM Set if the most significant bit of the result is set Cleared Bytes 2 RR LARNDN DN N V2 0 2001 03 o nfineon technologies C166 Family Instruction Set XORB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Logical Exclusive OR XORB op1 op2 op1 0p1 op2 BYTE Detailed Description XORB Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by 0p1 The result is then stored in op1 E Z V C E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z V Always cleared C Always cleared N otherwise Mnemonic XORB Rb Rb XORB Rb Rwi XORB Rb Rw XORB Rb data3 XORB reg data8 XORB reg mem XORB mem reg Set if result equals zero Cleared otherwise Format 51 nm 59 n 10ii 59 n 11ii 59 n 0 57 RR xx 53 RR MM MM 55 RR MM MM Set if the most significant bit of the result is set Cleared Bytes 2 RR LARNDN DN N V2 0 2001 03 o C166 Family Infineon TE E Addressing Modes 6 Addressing Modes The Infineon 16 bit microcontrollers provide a lot of powerful addressing modes for access to word byte and bit data short long
95. mat Bytes ASHR Rw RWm AC nm 2 ASHR Rw data4 BC n 2 47 V2 0 2001 03 TT e e nfineon technologies ATOMIC Syntax Operation Description Note Condition Flags Addressing Modes User s Manual C166 Family Instruction Set Detailed Description ATOMIC Begin ATOMIC Sequence ATOMIC 0p1 count 0p1 1 lt op1 lt 4 Disable interrupts and Class A traps DO WHILE count 0 AND Class B trap condition TRUE Next Instruction count count 1 END WHILE count 0 Enable interrupts and traps Causes standard and PEC interrupts and class A hardware traps to be disabled for a specified number of instructions The ATOMIC instruction becomes immediately active such that no additional NOPs are required Depending on the value of op1 the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMIC instruction Please see additional notes on Page 39 The ATOMIC instruction is not available in the SAB 8XC166 W devices E Z V Cc N E Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes ATOMIC irang2 D1 00 0 2 48 V2 0 2001 03 o nfineon technol
96. mily in alphabetical order User s Manual 40 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set ADD Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Integer Addition ADD op1 op2 op1 lt op1 op2 WORD Detailed Description ADD Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 E Z V C E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic ADD Rwy RWm ADD Rw Rwi ADD Rw Rw ADD Rw data3 ADD reg data16 ADD reg mem ADD mem reg 41 Format 00 nm 08 n 10ii 08 n 11ii 08 n 0 06 RR 02 RR MM MM 04 RR MM MM Bytes 2 RRLBRD0NN N V2 0 2001 03 o nfineon technologies C166 Family Instruction Set ADDB Syntax Operation Data Types Description Condition Flags Addressing
97. nd specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 The flags are set according to the rules of subtraction The operands remain unchanged Condition E Z V C N Flags S E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Setif result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Mnemonic Modes CMP Rw RWm CMP Rw Rwi CMP Rw Rwi CMP Rw data3 CMP reg data16 CMP reg mem User s Manual 63 Format 40 nm 48 n 10ii 48 n 11ii 48 n 0 46 RR 42 RR MM MM Bytes 2 2 2 4 4 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CMPB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Integer Compare CMPB op1 op2 0p1 op2 BYTE Detailed Description CMPB The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 The flags are set according to the rules of subtraction The operands remain un
98. ndirect word memory to direct GPR 2 MOV Rw Rw Move indirect word memory to direct GPR and 2 post increment source pointer by 2 MOV Rw Rw Move direct word GPR to indirect memory 2 MOV Rw Rw Pre decrement destination pointer by 2 and move 2 direct word GPR to indirect memory MOV Rw Rw Move indirect word memory to indirect memory 2 MOV Rw Rw Move indirect word memory to indirect memory and 2 post increment destination pointer by 2 MOV Rw Rw Move indirect word memory to indirect memory and 2 post increment source pointer by 2 User s Manual 17 V2 0 2001 03 o nfineon C166 Family C technologies Instruction Set Summary Table 4 Instruction Set Summary cont d Mnemonic Description Bytes Data Movement cont d MOV Rw Move indirect word memory by base plus constant 4 Rw d16 to direct word GPR MOV Rw d16 Move direct word GPR to indirect memory by base 4 Rw plus constant MOV Rw mem Move direct word memory to indirect memory 4 MOV mem Rw Move indirect word memory to direct memory 4 MOV reg mem Move direct word memory to direct register 4 MOV mem reg Move direct word register to direct memory 4 MOVB Rb Rb Move direct byte GPR to direct GPR 2 MOVB Rb data4 Move immediate byte data to direct GPR 2 MOVB reg data8 Move immediate byte data to direct register 4 MOVB Rb Rw Move indirect byt
99. neon technologies C166 Family Instruction Set JMPR Syntax Operation Description Note Condition Flags Addressing Modes User s Manual Detailed Description Relative Conditional Jump J M P R JMPR op1 op2 IF op1 1 THEN IP lt IP sign extend op2 ELSE Next Instruction END IF If the condition specified by op1 is met program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JMPR instruction If the specified condition is not met program execution continues normally with the instruction following the JMPR instruction The condition codes for op1 are defined in Table 5 E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes JMPR CC rel cD rr 2 91 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set JMPS Syntax Operation Description Condition Flags Addressing Modes User s Manual Detailed Description Absolute Inter Segment Jump J M PS JMPS op1 op2 CSP lt op1 IP op2 Branches unconditionally to the absolute address specified by op2 within the segment specifie
100. ness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered User s Manual V2 0 Mar 2001 Instruction Set Manual for the C166 Family of Infineon 16 Bit Single Chip Microcontrollers Microcontrollers Never stop thinking C166 Family Microcontroller Instruction Set Manual Revision History V2 0 2001 03 Previous Version Version 1 2 12 97 Version 1 1 09 95 03 94 Page Subjects major changes since last revision all Converted to new company layout 4 30 Overview and summary tables reformatted 2 List of derivatives updated 31 Description template added 34 PSW image added 38 Condition code table moved 40 Note for MUL DIV added 42ff Immediate data for byte instructions corrected to data8 52f Note improved 62 Description of operation corrected 72ff Description of division instructions improved 85 Format description corrected 86 Description improved 101f Description of multiplication instructions improved 128 Description of flags corrected 132 bitoff for ESFRs added 137 Section moved 139 Target address for rel corrected 141 General description improved 142ff Timing examples converted to 25 MHz
101. odes User s Manual Detailed Description Integer Two s Complement N EG B NEGB op1 op1 lt 0 op1 BYTE Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in op1 E Z V C N S E Setifthe value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes NEGB Rb A1 nO 2 104 V2 0 2001 03 TT e z nfineon C166 Family technologies Instruction Set Detailed Description NOP No Operation NOP Syntax NOP Operation No Operation Description This instruction causes a null operation to be performed A null operation causes no change in the status of the flags Condition E Z V C N Flags E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Mnemonic Format Bytes Modes NOP CC 00 2 User s Manual 105 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set OR Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed De
102. odes branch target 8 139 data 8 Arithmetic instructions 10 Bit manipulation instructions 15 Branch condition codes 9 38 target addressing modes 8 139 C Call instructions 19 Compare instructions 16 Condition code 9 38 flags 35 Constants 138 Control instructions 20 D Data addressing modes 8 move instructions 17 types 34 DPP override 137 User s Manual E Encoding of opcodes 22 Execution time 141 additional states 145 minimum 143 Extend instructions 39 operations 9 F Flags 35 Format of instructions 31 Indirect addressing 135 Instruction execution time 141 format 31 format symbols 37 overview 6 Instructions arithmetic 10 bit manipulation 15 compare and loop 16 data move 17 extend 39 jump and call 19 logical 13 return 20 shift and rotate 16 stack 21 system control 20 J Jump instructions 19 148 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set L Logical instructions 13 Long addressing 134 Loop instructions 16 M Minimum execution time 143 Mnemonic summary 10 Move instructions 17 O Opcode encoding 22 overview 4 Operands 33 Operators 32 Override mechanism 137 Overview instruction 6 opcode 4 P PSW 34 R Return instructions 20 Rotate instructions 16 S Shift instructions 16 Short addressing 132 Stack instructions 21 State times 141 Summary mnemonics 10 Symbols for instr format 37 System control instructions 20 User s
103. ogies C166 Family Instruction Set BAND Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Bit Logical AND BAND BAND op1 op2 0p1 lt op1 a op2 BIT Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in opt E Z V C N 0 NOR OR AND XOR Always cleared Contains the logical NOR of the two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits zo lt N m Contains the logical XOR of the two specified bits Mnemonic Format Bytes BAND bitaddrz z bitaddrg 6A QQ ZZ qz 4 49 V2 0 2001 03 o C166 Family Infineon TE Sas Detailed Description BCLR Bit Clear BCLR Syntax BCLR op1 Operation op1 0 Data Types BIT Description Clears the bit specified by 0p1 This instruction is primarily used for peripheral and system control Condition E Z V C N Flags 0 B 0 0 B Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared Always cleared N Contains the previous state of the specified bit Addressing Mnemonic Format Bytes Modes BCLR bitaddrg 4 qE QQ 2 User s Manual 50 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set
104. om a subroutine The IP is first popped from the system stack and then the next word is popped from the system stack into the operand specified by op 1 Execution resumes at the instruction following the CALL instruction in the calling routine E Z V C N E Set if the value of the word popped into operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the word popped into operand op1 equals zero Cleared otherwise V Not affected Not affected N Set if the most significant bit of the word popped into operand op1 is set Cleared otherwise Mnemonic Format Bytes RETP reg EB RR 2 115 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set RETS Syntax Operation Description Condition Flags Addressing Modes User s Manual Detailed Description Return from Inter Segment Subroutine R ETS RETS IP lt SP SP SP 2 CSP SP SP lt SP 2 Returns from an inter segment subroutine The IP and CSP are popped from the system stack Execution resumes at the instruction following the CALLS instruction in the calling routine E Z V C N Not affected Not affected Not affected Not affected zZz O lt s NM Not affected Mnemonic Format Bytes RETS DB 00 2 116 V2 0 2001 03 o nfineon technologies C166 Fam
105. on technologies C166 Family Instruction Set EXTR Syntax Operation Description Note Condition Flags Addressing Modes User s Manual Detailed Description Begin EXTended Register Sequence EXTR EXTR op1 count op1 1 lt op1 lt 4 Disable interrupts and Class A traps SFR_range Extended DO WHILE count 0 AND Class B trap condition TRUE Next Instruction count count 1 END WHILE count 0 SFR_range Standard Enable interrupts and traps Causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard PEC interrupts and class A hardware traps are locked The value of op1 defines the length of the effected instruction sequence Please see additional notes on Page 39 The EXTR instruction is not available in the SAB 8XC166 W devices E Z V C N Not affected Not affected Not affected Not affected 2 O lt s NM Not affected Mnemonic Format Bytes EXTR irang2 D1 10 0 2 77 V2 0 2001 03 eo nfineon technologies C166 Family Instruction Set EXTP Syntax Operation Description Note Condition Flags User s Manual Detailed Description Begin EXTended Page Sequence EXTP EXTP op1 op2 count op2 1 lt op2 lt 4 Disable interrupts and Class A traps
106. on Set EXTPR Condition Flags Addressing Modes User s Manual continued Detailed Description EXTPR zo lt N om Mnemonic EXTPR Rwm irang2 EXTPR pag irang2 Not affected Not affected Not affected Not affected Not affected 81 Format Bytes DC 11 m 2 D7 11 0 pp 0 00pp 4 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set EXTS Syntax Operation Description Note Condition Flags User s Manual Detailed Description Begin EXTended Segment Sequence EXTS EXTS op1 op2 count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data_Segment 0p1 DO WHILE count 0 AND Class B trap condition TRUE Next Instruction count count 1 END WHILE count 0 Data Page DPPx Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard PEC interrupts and class A hardware traps are locked The EXTS instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTS instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bit
107. on alternatives exist for some of the condition codes condition codes are described in Table 5 BCLR and BSET Instructions The position of the bit to be set or to be cleared is specified by the opcode The operand bitoff n n O to 15 refers to a particular bit within a bit addressable word Undefined Opcodes A hardware trap occurs when one of the undefined opcodes signified by is decoded by the CPU Note The 8XC166 W devices also do not recognize ATOMIC and EXTended instructions but rather decode an undefined opcode Users Manual 22 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Encoding D D 3 Mnemonic Operands 3 Mnemonic Operands x Im x m 00 2 ADD Rw Rw 10 12 ADDC Rw Rw 01 2 ADDB Rb Rb 11 2 ADDCB Rb Rb 02 4 ADD reg mem 12 ADDC reg mem 03 4 ADDB reg mem 13 14 ADDCB reg mem 04 4 ADD mem reg 14 14 ADDC mem reg 05 4 ADDB mem reg 15 14 ADDCB mem reg 06 4 ADD reg data16 16 14 ADDC reg data16 07 4 ADDB reg data8 17 14 ADDCB reg data8 08 2 ADD Rw Rw or 18 2 ADDC Rw Rw or Rw Rw or Rw Rw or Rw data3 Rw data3 09 2 ADDB Rb Rw or 19 2 ADDCB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 OA 4 BFLDL bitoff mask8 1A 14 BFLDH bitoff mask8 data8 data8 OB 2 MUL Rw Rw 1B 2 MULU Rw Rw OC 2 ROL
108. on to form common high level language FOR loops of any range E Z V C N S E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPD2_ Rw data4 BO n 2 CMPD2 Rw data16 B6 Fn 4 CMPD2 Rw mem B2 Fn MM MM 4 66 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CMPI1 Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Integer Compare and Increment by 1 CM PI CMPI1 op1 op2 op1 gt op2 op1 op1 1 WORD This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is incremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level langu
109. ontains the complemented value of the specified bit operand Note If the PSW register was specified as the destination operand of an instruction the User s Manual condition flags can not be interpreted as just described because the PSW register is modified depending on the data format of the instruction as follows For word operations register PSW is overwritten with the word result For byte operations the non addressed byte is cleared and the addressed byte is overwritten For bit or bit field operations on the PSW register only the specified bits are modified Supposed that the condition flags were not selected as destination bits they stay unchanged This means that they keep the state after execution of the previous instruction In any case if the PSW was the destination operand of an instruction the PSW flags do NOT represent the condition flags of this instruction as usual 35 V2 0 2001 03 TT C166 Family Infineon TE Sas Detailed Description Addressing Modes This part specifies which combinations of different addressing modes are available for the required operands Mostly the selected addressing mode combination is specified by the opcode of the corresponding instruction However there are some arithmetic and logical instructions where the addressing mode combination is not specified by the identical opcodes but by particular bits within the operand field The addressing mode entries are made up of
110. p1 indicating the number of single bit shifts required to normalize the operand op2 so that its MSB is equal to one If the source operand op2 equals zero a zero is written to operand op1 and the zero flag is set Otherwise the zero flag is cleared E Z V C N 0 0 0 0 Always cleared Set if the source operand op2 equals zero Cleared otherwise Always cleared Always cleared zZz O lt s NM Always cleared Mnemonic Format Bytes PRIOR Rw RWm 2B nm 2 110 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set PUSH Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Push Word on System Stack PUSH PUSH op1 tmp op1 SP SP 2 SP tmp WORD Moves the word specified by operand op1 to the location in the internal system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two E Z V C N E Set if the value of the pushed word represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed word equals zero Cleared otherwise V Not affected Not affected N Set if the most significant bit of the pushed word is set Cleared otherwise Mnemonic Format Bytes PUSH reg EC RR 2 111 V2 0 2001 03 o nfineon technologies P
111. ration Data Types Description Condition Flags User s Manual Detailed Description Shift Right SHR SHR op1 op2 count lt op2 C lt 0 V 0 DO WHILE count 0 V C v V C 0p 0p1 0p1y44 N 0 14 0p145 0 count count 1 END WHILE WORD Shifts the destination word operand op1 right by as many times as specified by the source operand op2 The most significant bits of the result are filled with zeros accordingly Since the bits shifted out effectively represent the remainder the Overflow flag is used instead as a Rounding flag This flag together with the Carry flag helps the user to determine whether the remainder bits lost were greater than less than or equal to one half an LSB Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Z V C N 0 S S j Always cleared Set if result equals zero Cleared otherwise Set if in any cycle of the shift operation a 1 is shifted out of the carry flag Cleared for a shift count of zero C The carry flag is set according to the last LSB shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise 121 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set SHR Addressing Modes User s Manual continued
112. re powered down The device remains powered down until a peripheral interrupt only possible in Idle mode or an external interrupt occurs Sleep mode must be selected before executing the IDLE instruction Note To insure that this instruction is not accidentally executed it is implemented as a protected instruction Condition E Z V C N Flags E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Mnemonic Format Bytes Modes IDLE 87 78 87 87 4 User s Manual 86 V2 0 2001 03 TT e z nfineon C166 Family technologies Instruction Set Detailed Description JB Relative Jump if Bit Set JB Syntax JB op1 op2 Operation IF op1 1 THEN IP lt IP sign extend op2 ELSE Next Instruction END IF Data Types BIT Description If the bit specified by op1 is set program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JB instruction If the specified bit is clear the instruction following the JB instruction is executed Condition E Z V C N Flags E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Mnemonic Format Bytes Modes J
113. ruction description see example and then all instructions are listed individually The instructions are ordered alphabetically MN E M Short Description M N E M Syntax MNEM _ operand s Operation definition in pseudo code Data Types BIT BYTE WORD DOUBLEWORD Description Verbal description of the instruction s effect Note Additional hints Condition E Z V Cc N Flags 9 2 2 2 E Effect of this instruction on flag E Z Effect of this instruction on flag Z V Effect of this instruction on flag V C Effect of this instruction on flag C N Effect of this instruction on flag N Addressing Mnemonic Format Bytes Modes MNEM _ operand s encoding 214 User s Manual 31 V2 0 2001 03 o C166 Family Infineon TE Sass Detailed Description Instruction Name MNEM Specifies the mnemonic opcode of the instruction in oversized bold lettering for easy reference The mnemonics have been chosen with regard to the particular operation which is performed by the specified instruction These mnemonics are also used by tools such as assemblers Short D Short description which is also used in the compact tables on the previous pages Syntax Specifies the mnemonic opcode and the required formal operands of the instruction as used in the following subsection Operation There are instructions with either none one two or three operands which must be separated from each other by commas MNEMONIC opl
114. s User s Manual Detailed Description Absolute Conditional Jump J M P JMPA op1 op2 IF op1 1 THEN IP lt op2 ELSE Next Instruction END IF If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPA instruction is executed normally The condition codes for op1 are defined in Table 5 E Z V Cc N Not affected Not affected Not affected Not affected zZz O lt s NM Not affected Mnemonic Format Bytes JMPA cc caddr EA c0 MM MM 4 89 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set JMPI Syntax Operation Description Note Condition Flags Addressing Modes User s Manual Detailed Description Indirect Conditional Jump J M Pl JMPI op1 op2 IF op1 1 THEN IP lt op2 ELSE Next Instruction END IF If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPI instruction is executed normally The condition codes for op1 are defined in Table 5 E Z V Cc N Not affected Not affected Not affected Not affected zZz O lt s NM Not affected Mnemonic Format Bytes JMPI cc Rwy 9C cn 2 90 V2 0 2001 03 o nfi
115. s Description Condition Flags Addressing Modes User s Manual Integer Subtraction SUBB op1 op2 0p1 lt 0p1 op2 BYTE Detailed Description SUBB Performs a 2 s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1 The result is then stored in op1 E Z V C N S E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic SUBB Rb Rbm SUBB Rb Rwj SUBB Rb Rw SUBB Rb data3 SUBB reg data8 SUBB reg mem SUBB mem reg 126 Format 21nm 29 n 10ii 29 n 11ii 29 n O 27 RR xx 23 RR MM MM 25 RR MM MM Bytes 2 AR ABRKRMODND V2 0 2001 03 o nfineon technologies C166 Family Instruction Set SUBC Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Integer Subtraction with Carry SU BC SUBC op1 op2 0p1 lt op1 op2 C WORD Performs a 2 s complement binary subtraction of the
116. s A15 AO The value of op2 defines the length of the effected instruction sequence Please see additional notes on Page 39 The EXTS instruction is not available in the SAB 8XC166 W devices E Z V C N Not affected Not affected Not affected Not affected 2 O lt NM Not affected 82 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set EXTS Addressing Modes User s Manual continued Mnemonic EXTS Rwm irang2 EXTS seg irang2 83 Detailed Description EXTS Format Bytes DC 00 m 2 D7 00 0 ss 00 4 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set EXTSR Syntax Operation Description Note User s Manual Detailed Description Begin EXTended Segment EXTSR and Register Sequence EXTSR op op2 count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Segment op1 AND SFR_range Extended DO WHILE count 0 AND Class B trap condition TRUE Next Instruction count lt count 1 END WHILE count 0 Data_Page DPPx AND SFR_range Standard Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their exe
117. s Manual 133 V2 0 2001 03 o C166 Family Infineon TE E Addressing Modes 6 2 Long Addressing Mode This addressing mode uses one of the four DPP registers to specify a physical 24 bit address 18 bit for the SAB 8XC166 W devices Any word or byte data within the entire address space can be accessed with this mode An override mechanism for the DPP addressing scheme is also supported see Section 6 4 Note Word accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP registers are initialized in a way that all long addresses are directly mapped onto the identical physical addresses Any long 16 bit address consists of two portions which are interpreted in different ways Bits 13 0 specify a 14 bit data page offset while bits 15 14 specify the Data Page Pointer 1 of 4 which is to be used to generate the physical 24 bit or 18 bit address see Figure 2 15 1413 0 VM AUTT 14 Bit Page Offset i MCD04933 Figure 2 Interpretation of a 16 bit Long Address The supported address space is up to 16 MByte 256 KByte for the SAB 8XC166 W devices so only the lower ten bits two bits respectively of the selected DPP register content are concatenated with the 14 bit data page offset to build the physical address Users Manual 134 V2 0 2001 03 TT e z nfineon C166 Family technologies Instruction Set Addressing Modes The long addressin
118. sA trap is accepted during the execution of the ATOMIC EXTx instruction and the following locked instructions see irang2 All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMIC and EXTended instructions ATTENTION When a ClassB trap interrupts an ATOMIC or EXTended sequence this sequence is terminated the interrupt lock is removed and the standard condition is restored before the trap routine is executed The remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under standard conditions Within a ClassA or ClassB trap service routine EXTend instructions do not work i e override the DPP mechanism as long as any of the ClassB trap flags is set ATTENTION There is only ONE counter to control the length of an ATOMIC or EXTend sequence i e issuing an ATOMIC or EXTend instruction within a sequence will reload the counter with the value of the new instruction ATOMIC and EXTend instructions can be nested to generate longer locked sequences When using the ATOMIC and EXTended instructions with other system control or branch instructions please note that the counter counts any executed instruction Note The ATOMIC and EXTended instructions are not available in the SAB 8XC 166 W devices User s Manual 39 V2 0 2001 03 o C166 Family Infineon TE Sass Detailed
119. scription Logical OR OR OR op1 op2 op1 lt opt v op2 WORD Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E Z V C N E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Setif result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes OR Rw RWm 70 nm 2 OR Rw Rwi 78 n 10ii 2 OR Rw Rwj 78 n 11ii 2 OR Rw data3 78 n O 2 OR reg data16 76 RR 4 OR reg mem 72 RR MM MM 4 OR mem reg 74 RR MM MM 4 106 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set ORB Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Logical OR ORB ORB op1 op2 op1 lt opt v op2 BYTE Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E Z V C N E Setif the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always
120. sed in conjunction with this instruction to form common high level language FOR loops of any range E Z V C N S E Setifthe value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPD1 Rw data4 AO n 2 CMPD1 Rw data16 A6 Fn 4 CMPD1 Rw mem A2 Fn MM MM 4 65 V2 0 2001 03 o nfineon technologies C166 Family Instruction Set CMPD2 Syntax Operation Data Types Description Condition Flags Addressing Modes User s Manual Detailed Description Integer Compare and Decrement by 2 CM PD2 CMPD2_ 0p1 op2 0p1 op2 op1 lt opt 2 WORD This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is decremented by two Using the set flags a branch instruction can then be used in conjunction with this instructi
121. source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly Condition E Z V C N Flags 0 B 0 0 B Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared Always cleared N Contains the previous state of the source bit Addressing Mnemonic Format Bytes Modes BMOVN bitaddrz z bitaddra 3A QQ ZZ qz 4 User s Manual 55 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set Detailed Description BOR Bit Logical OR BOR Syntax BOR op1 op2 Operation op1 op1 v op2 Data Types BIT Description Performs a single bit logical OR of the source bit specified by operand op2 with the destination bit specified by operand op1 The ORed result is then stored in op1 Condition E Z V C N Flags 0 NOR OR AND XOR Always cleared Contains the logical NOR of the two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits 2 O lt N m Contains the logical XOR of the two specified bits Addressing Mnemonic Format Bytes Modes BOR bitaddrz z bitaddra q 5A QQ ZZ qz 4 User s Manual 56 V2 0 2001 03 o C166 Family Infineon TE Sas Detailed Description BSET Bit Set BSET Syntax BSET op1 Operation op1 1 Data Types BIT Des
122. st cases the given execution time also includes the handling of the involved operands if any Some operand accesses however can extend the execution time of an instruction Tin Since the additional time Tiagg is mostly caused by internal instruction pipelining it often will be possible to evade these timing effects in time critical program modules by means of a suitable rearrangement of the corresponding instruction sequences Simulators and emulators offer a lot of facilities which support the user in optimizing his program whenever required Operand Reads from Internal Program Memory Both byte and word operand reads always require 2 additional state times Tadd 2 States Operand Reads from Internal RAM via Indirect Addressing Modes Reading a GPR or any other directly addressed operand within the internal RAM space does NOT cause additional state times However reading an indirectly addressed internal RAM operand will extend the processing time by 1 state time if the preceding instruction auto increments or auto decrements a GPR as shown in the following example MOV R1 RO auto increment RO MOV R3 R2 if R2 points into IRAM space Tadd 1 State In this case the additional time can easily be avoided by putting another suitable instruction before the instruction indirectly reading the internal RAM Tadd 0 or 1 State Operand Reads from an SFR Mostly SFR read accesses do NOT require additional processing time
123. structions is valid only for a limited scope and can be defined for the following 1 4 instructions This instruction range 1 4 is coded in the 2 bit constant irang2 and is represented by the values 0 3 User s Manual 138 V2 0 2001 03 TT e e nfineon technologies C166 Family Instruction Set 6 7 Branch Target Addressing Modes Addressing Modes Different addressing modes are provided to specify the target address and segment of jump or call instructions Relative absolute and indirect modes can be used to update the Instruction Pointer register IP while the Code Segment Pointer register CSP can only be updated with an absolute value A special mode is provided to address the interrupt and trap jump vector table which resides in the lowest portion of code segment 0 Table 10 Branch Addressing Mnemonic Target Address Target Segment Valid Address Range caddr IP caddr current caddr 00004 FFFEH rel IP IP 2 x rel current rel 004 7Fy IP IP 2 x rel 1 current rel 804 FFy Rw IP CP 2 x Rw current Rw 0 15 seg CSP seg seg 0 255 3 trap7 IP 00004 4 x trap7 CSP 00004 trap7 00 7Fy User s Manual 139 V2 0 2001 03 o nfineon C166 Family technologies Instruction Set caddr rel Rw seg trap7 Addressing Modes Specifies an absolute 16 bit code address within th
124. ta type dependent value A 1 for byte operations A 2 for word operations GPR Pointer GPR Pointer A optional step The following indirect addressing modes are provided Table 8 Indirect Addressing Mnemonic Particularities Rw Most instructions accept any GPR R15 RO as indirect address pointer Some instructions however only accept the lower four GPRs R3 RO Rw The specified indirect address pointer is automatically post incremented by 2 or 1 for word or byte data operations after the access Rw The specified indirect address pointer is automatically pre decremented by 2 or 1 for word or byte data operations before the access Rw The specified 16 bit constant is added to the indirect address pointer data16 before the long address is calculated User s Manual 136 V2 0 2001 03 o C166 Family Infineon TE E Addressing Modes 6 4 DPP Override Mechanism The DPP override mechanism temporarily bypasses the standard DPP addressing scheme The EXTP R and EXTS R instructions override this addressing mechanism Instruction EXTP R replaces the content of the respective DPP register i e the data page number with a direct page number while instruction EXTS R concatenates the complete 16 bit long address with the specified segment base address The overriding page or segment may be specified directly as a constant pag seg or indirectly via a
125. tension to 4 direct word memory MOVBZ Rw Rb Move direct byte GPR with zero extension to 2 direct word GPR MOVBZ reg mem Move direct byte memory with zero extension to 4 direct word register MOVBZ mem reg Move direct byte register with zero extension to 4 direct word memory Jump and Call Instructions JMPA cc caddr Jump absolute if condition is met 4 JMPI cc Rw Jump indirect if condition is met 2 JMPR cc rel Jump relative if condition is met 2 JMPS _ seg caddr Jump absolute to a code segment 4 JB baddr rel Jump relative if direct bit is set 4 JBC baddr rel Jump relative and clear bit if direct bit is set 4 JNB baddr rel Jump relative if direct bit is not set 4 JNBS _ badd rel Jump relative and set bit if direct bit is not set 4 CALLA cc caddr Call absolute subroutine if condition is met 4 CALLI cc Rw Call indirect subroutine if condition is met 2 CALLR rel Call relative subroutine 2 CALLS seg caddr Call absolute subroutine in any code segment 4 PCALL reg caddr Push direct word register onto system stack and 4 call absolute subroutine TRAP trap7 Call interrupt service routine via immediate trap number 2 User s Manual V2 0 2001 03 o A C166 Famil op Instruction Set Summary Table 4 Instruction Set Summary con d Mnemonic Description Bytes Return Instructions RET Return from intra segment subroutine 2 RET
126. three elements e Mnemonic shows an example of what operands the respective instruction will accept e Format specifies the format of the instruction symbols are explained on Page 37 as it is represented in the assembler listing The figure below shows the reference between the instruction format representation of the assembler and the corresponding internal organization of such an instruction format N nibble 4 bits e Number of Bytes specifies the size of an instruction in bytes All C166 Family instructions consist of 2 bytes or 4 bytes single word or double word instruction Representation in the N2N1 N4N3 T N8N7 Assembler Listing TT Tease Byte 2nd Word Low Byte 2nd Word High Byte 1st Word Low Byte 1st Word lt Bits in ascending order MCD04931 Nx Nibble x Figure 1 Instruction Format Representation User s Manual 36 V2 0 2001 03 nfineon technologies C166 Family Instruction Set Detailed Description Symbols for the Instruction Format 004 through FF4 Instruction Opcodes Hex 0 1 LAH HH XX MM MM HH Constant Values bits Each of the 4 characters immediately following a colon represents a single bit 2 bit short GPR address Rw Code segment number seg byte value 2 bit immediate constant irang2 3 bit immediate constant data3 4 bit condition code specification cc see also Table 5 4 bit short GPR address Rw or Rb 4
127. ue are used for updating the CSP register Specifies a particular interrupt or trap number for branching to the corresponding interrupt or trap service routine via a jump vector table Trap numbers from 004 to 7F4 can be specified which allow to access any double word code location within the address range 00 0000 00 01FC in code segment 0 i e the interrupt jump vector table For the association of trap numbers with the corresponding interrupt or trap sources please refer to chapter Interrupt and Trap Functions in the respective Users Manual Users Manual 140 V2 0 2001 03 TT C166 Family Infineon Tre Sas Instruction State Times 7 Instruction State Times Basically the time to execute an instruction depends on where the instruction is fetched from and where possible operands are read from or written to The fastest processing mode is to execute a program fetched from the internal program memory ROM OTP Flash In that case most of the instructions can be processed within just one machine cycle which is also the general minimum execution time All external memory accesses are performed by the on chip External Bus Controller EBC which works in parallel with the CPU Mostly instructions from external memory cannot be processed as fast as instructions from the internal ROM because some data transfers which internally can be performed in parallel have to be performed sequentially via the external

Infineon C166 Family Instruction Set Manual

Contents

Download Pdf Manuals

Related Search

Related Contents