20-W Mono Digital Input Audio Amplifier (Rev. A)
Contents
1. 4073267 C 03 05 A All linear dimensions are in millimeters B This drawing is subject to change without notice C Body dimensions do not include mold flash or protusions mold flash not to exceed 0 15mm This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMAO02 for information regarding recommended board layout This document is available at www ti com See the product data sheet for details regarding the exposed thermal pad dimensions E Falls within MO 1535 PowerPAD is a trademark of Texas Instruments 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty Tl s terms and conditi2. 1 1 1 This system clock rate is not supported for the given sampling frequency NR H 2 0V System Clock SCK 0 8V L 4 PPM lscv gt Figure 18 System Clock Input Timing PARAMETERS SYMBOL MIN TYP MAX UNITS System clock pulse duration high tSckH 7 System clock pulse duration low lisckL ns System clock pulse cycle time tiscy 7 See 1 1 1 128 fs 1 256 fs 1 384 fs 1 512 fs 1 768 fs or 1 1152 fs AUDIO SERIAL INTERFACE The audio serial interface for the TPA3200D1 consists of a 3 wire synchronous serial port It includes LRCK pin 4 BCK pin 1 and DATA pin 3 BCK is the serial audio bit clock and it is used to clock the serial data present on DATA into the serial shift register of the audio interface Serial data is clocked into the TPA3200D1 on the rising edge of BCK LRCK is the serial audio left right word clock It is used to latch serial data into the internal registers of the serial audio interface Both LRCK and BCK should be synchronous to the system clock Ideally it is recommended that LRCK and BCK be derived from the system clock input SCK LRCK is operated at the sampling frequency fs BCK can be operated at 32 48 or 64 times the sampling frequency for standard and left justified formats BCK can be operated at 48 or 64 times the sampling frequency for the 125 format Internal operation of t
3. 2 V 17 1 18 18 6 dB GAIN1 2 V GAINO 0 8 V 229 236 244 OPERATING CHARACTERISTICS PVgc 12 V 25 C unless otherwise noted PARAMETER TEST CONDITIONS MAX UNIT Continuous output power at 10 THD N 1 kHz R 249 12 8 f 1 kHz R 8Q 9 Po Continuous output power at 1 THD N f 2 1 kHz R 2490 10 3 f 1 kHz R 8Q 7 5 THD N Total harmonic distortion plus noise 10 42 f 20 Hz to 20 kHz 0 2 Bom Maximum output power bandwidth THD 1 20 kHz Supply ripple rejection ratio f 1 kHz Cieypass 1 HF 60 SNR Signal to noise ratio 10 40 95 Cieypass 1 HF f 20 Hz to 22 kHz 150 pV rms Vn Noise output voltage A weighted filter Gain 12 dB 765 dBV 35 TEXAS TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 Functional Block Diagram SS S BCK LRCK DATA FORMAT MUTE DEMP SCLK LR SEL VCOM FLT2 FLT1 SHUTDOWN GAINO GAIN1 COSC ROSC BYPASS 4x 8x Oversampling Digital Filter and Function Control Multi Level Delta Sigma Modulator System Clock Zero Detect ZERO VDD Power Supply DGND Ciamp VCLAMP PVCC Deglitch Gate Logic Drive Y Y Deglitch Logic 4 Start Up Short Circuit Pr
4. Figure 22 OUTP OUTN Differential 412V Voltage ov Across Load 12V Output 0 V Current See OUr Output gt 0 V Differential 412V m Voltage ov Across Load ee Current 4 4 Figure 22 The TPA3200D1 Output Voltage and Current Waveforms Into an Inductive Load 33 Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 Maximum Allowable Output Power Safe Operating Area The TPA3200D1 can drive load impedances as low as 3 6 from power supply voltages ranging from 8 V to 18 V To prevent device failure however the output power of the TPA3200D1 must be limited Figure 23 shows the maximum allowable output power versus load impedance for three power supply voltages at an ambient temperature of 25 MAXIMUM OUTPUT POWER VS LOAD IMPEDANCE 21 19 Vcc 18 V 17 13 Vec 15V 12 Po Output Power W 7 25 10 THD Maximum 3 6 4 5 6 7 8 9 10 Z Load Impedance Q Figure 23 Output Power Driving The Output Into Clipping The output of the TPA3200D1 may be driven into clipping to attain a higher output power than is possible with no distortion Clipping is typically quantified by a THD measurement of 10 The amount of additional power into
5. 33 Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 1 16 Bit Word Right Justified 4 Tits LRCK 4 L Channel i R Channel 4 ee FLSA LE LALA LATS LEAL APA 32 15 48 fs or 64 fs 16 Bit Right Justified 48 fg 64 fs eps ne ERE E LEG MSB LSB MSB LSB 1 16 Bit Right Justified BCK 3215 DATA MSB LSB MSB LSB 2 25 Data Format L Channel LOW R Channel HIGH le 1 6 pl LRCK L Channel R Channel UA rfnnn AAAA mne 48 fs or 64 fs oa PS e ep Figure 20 Audio Data Input Formats ZERO FLAG ZERO pin 39 is the L channel and R channel common zero flag pin If the data for L channel and R channel remains at a 0 level for 1024 sampling periods or LRCK clock periods the ZERO flag output is set to a logic 1 state The ZERO pin output can be inverted using a standard logic gate or transistor and connected to the SHUTDOWN terminal pin 13 This places the TPA3200D1 into a low current state conserving power and disables the switching outputs TPA3200D1 43 Texas INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 REGISTER CONTROL The digital functions of the TPA3200D1 are controlled by 4 terminals Table 2 shows selectable data formats Table 3 shows de emphasis control Table 4 shows mute control and Table 5 shows channel output select Table 2 Data Format Sel
6. 5 Veg 12V R 49 2 Gain 18 dB f 48 kHz 4 24 bit S format 0 5 1 kHz 0 2 0 1 0 05 20 Hz 0 02 0 01 10m 100m 200m 1 10 20 Po Output Power W Figure 4 Texas INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued Total Hormonic Distortion Plus Noise Total Hormonic Distortion Plus Noise Total Harmonic Distortion Plus Noise vs Frequency 20 Vcc 12V 10 RL 80 Gain 18 dB fs 48 kHz 24 bit I2S format 2 1 5 0 5 0 2 500 mw 0 05 0 02 rl Po 1W 0 01 20 100 200 1k 2k 10k 20k f Frequency Hz Figure 5 Total Harmonic Distortion Plus Noise vs Frequency 20 10 Vcc 18V RL 8Q 5 Gain 18 dB fs 48 kHz 2 24 bit 125 format 1 0 5 0 2 0 1 Po 500 mW 0 05 Po 1W 0 02 e 5 0 01 20 100 200 1k 2k 10k 20k f Frequency Hz Figure 7 Total Hormonic Distortion Plus Noise 96 Total Hormonic Distortion Plus Noise 96 TPA3200D1 SLOS
7. Ferrite _ _ 6562 Bead Ferrite Ferrite PGND DGND Bead 8 B Bead OUTN OUTP Figure 17 Typical Application Circuit 12 33 Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 APPLICATION INFORMATION continued SYSTEM CLOCK INPUT The TPA3200D1 requires a system clock for operating the digital interpolation filters and multilevel delta sigma modulators The system clock is applied at the SCLK input pin 44 Table 1 shows examples of system clock frequencies for common audio sampling rates Figure 18 shows the timing requirements for the system clock input For optimal performance it is important to use a clock source with low phase jitter and noise 5 PLL170x family of multiclock generators is an excellent choice for providing the TPA3200D1 system clock Table 1 System Clock Rates for Common Audio Sampling Frequencies SAMPLE SYSTEM CLOCK FREQUENCY MHz FREQUENCY 128 fs 192 fs 256 fs 384 15 512 fs 768 15 115215 8 kHz 1 0240 1 5360 2 0480 3 0720 4 0960 6 1440 9 2160 16 kHz 2 0480 3 0720 4 0960 6 1440 8 1920 12 2880 18 4320 32 kHz 4 0960 6 1440 8 1920 12 2880 16 3840 24 5760 36 8640 44 1 kHz 5 6448 8 4672 11 2896 16 9344 22 5792 33 8688 1 48 kHz 6 1440 9 2160 12 2880 18 4320 24 5760 36 8640 1 88 2 kHz 11 2896 16 9344 22 5792 33 8688 45 1584 1 1 96 kHz 12 2880 18 4320 24 5760 36 8640 49 1520 1 1 192 kHz 24 5760 36 8640 49 1520 See 0 1
8. the load may be calculated with Equation 1 Poqo THD Poa THD 1 29 1 For example consider an application in which the TPA3200D1 drives 8 Q speaker from an 18 V power supply The maximum output power with no distortion less than 1 THD is 16 W which corresponds to a maximum peak output voltage of 16 V For the same output voltage level driven into clipping 10 THD the output power is increased to 20 W Output Filter Considerations A ferrite bead filter shown in Figure 24 should be used in order to pass FCC and or CE radiated emissions specifications and if a frequency sensitive circuit operating higher than 1 MHz is nearby The ferrite filter reduces EMI around 1 MHz and higher FCC and CE only test radiated emissions greater than 30 MHz When selecting a ferrite bead choose one with high impedance at high frequencies but very low impedance at low frequencies Use an additional LC output filter if there are low frequency lt 1 MHz EMI sensitive circuits and or there are long wires greater than 11 inches from the amplifier to the speaker as shown in Figure 25 and Figure 26 TPA3200D1 SLOS442A MAY 2005 REVISED JULY 2005 Ferrite Chip Bead OUTP TEXAS INSTRUMENTS www ti com Ferrite Chip Bead ai 4 Q or Greater Figure 24 Typical Ferrite Chip Bead Filter Chip bead example Fair Rite 2512067007 Ferrite 15 uH Chip Bead OUTP
9. VCLAMP CAPACITOR To ensure that the maximum gate to source voltage for the NMOS output transistors is not exceeded an internal regulator clamps the gate voltage A 1 uF capacitor must be connected from VCLAMP pin 15 to ground This capacitor must have a rating of Vcc or more The voltage at VCLAMP pin 15 varies with Vcc and may not be used for powering any other circuitry MIDRAIL BYPASS CAPACITOR The midrail bypass capacitor is the most critical capacitor and serves several important functions During start up or recovery from shutdown mode Cypass determines the rate at which the amplifier starts up The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal This noise is from the midrail generation circuit internal to the amplifier which appears as degraded PSRR and THD N VREF DECOUPLING CAPACITOR The VREF terminal pin 34 is the output of an internally generated 5 V supply used for the oscillator and gain setting logic It requires a 0 1 uF to 1 uF capacitor to ground to keep the regulator stable The regulator may not be used to power any additional circuitry SWITCHING FREQUENCY The switching frequency is determined using the values of the components connected to ROSC pin 31 and COSC pin 32 and may be calculated using Equation 5 f 6 6 Rosc Cosc 5 The frequency be varied from 225 kHz to 275 kHz by adjusting the values chosen for ROSC and COSC 22
10. a class D amplifier that switches at a high frequency the layout of the printed circuit board PCB should be optimized according to the following guidelines for the best possible performance e Decoupling capacitors The high frequency 1 uF decoupling capacitors should be placed as close to the PVCC pin 18 and pin 27 and VCC pin 35 terminals as possible The BYPASS pin 33 capacitor VREF pin 34 capacitor and VCLAMP pin 15 capacitor should also be placed as close to the device as possible The large 10 pF or greater bulk power supply decoupling capacitor should be placed near the TPA3200D1 at the PVCC terminals e Grounding The VCC 35 decoupling capacitor VREF pin 34 capacitor BYPASS 33 capacitor COSC pin 32 capacitor and ROSC pin 31 resistor should each be grounded to analog ground AGND pin 29 and pin 30 The PVCC pin 18 and pin 27 decoupling capacitors should each be grounded to power ground PGND pins 14 21 22 23 and 24 Analog ground and power ground may be connected at the PowerPAD which should be used as a central ground connection or star ground for the TPA3200D1 DGND pins 5 9 38 and 40 should be connected to PGND and AGND at the power supply through a ferrite bead Connect the VDD pins 6 and 8 decoupling capacitor to DGND This pattern separates the digital power switching currents and digital input currents and prevents interference between them e Digital input signal routin
11. options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release Addendum Page 1 H PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com 10 Jun 2014 In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 2 MECHANICAL DATA DCP R PDSO G PowerPAD PLASTIC SMALL OUTLINE PACKAGE 30 PIN SHOWN 0 08 Thermal Pad i l Gage Plane i 0 05 PINS
12. to Vpp 4 0 3 V FORMAT MUTE DEMP Continuous total power dissipation See Dissipation Rating Table TA Operating free air temperature range 25 to 85 Ty Operating junction temperature range 25 to 150 Storage temperature range 65 to 150 Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability DISSIPATION RATINGS PACKAGE lt 25 C DERATING FACTOR 70 C 85 1 0 44 4 89 W 39 1 mW C 3 13W 2 54 W 1 Based on a JEDEC high K PCB with the PowerPAD soldered to a thermal land on the printed circuit board See the PowerPAD Thermally Enhanced Package technical brief literature number SLMA0002 The PowerPAD must be soldered to the PCB 4i TEXAS INSTRUMENTS www ti com RECOMMENDED OPERATING CONDITIONS TPA3200D1 SLOS442A MAY 2005 REVISED JULY 2005 PARAMETER PIN NAME MIN MAX UNIT Vss s ppi voltage VCC 8 18 VDD 4 5 5 5 Vin High level input voltage M
13. 00 1k 2k 5k 10k 20k f Frequency Hz Figure 9 Efficiency vs Output Power 12 14 0 2 4 6 8 Po Output Power W 10 Figure 11 PSRR Power Supply Rejecyion Ratio dB Po Output Power W TEXAS INSTRUMENTS www ti com Power Supply Voltage Rejection Ratio vs Frequency 12 V RIPPLE 200 80 Gain 18 dB 1 f Frequency Hz 100 10k 20k Figure 10 Output Power v s Load Impedance 21 18 19 17 15 Vcc 15V 13 11 7 F 25 096 THD Maximum 3 6 4 5 6 7 8 9 10 21 Load Impedance 2 Figure 12 X5 Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 TYPICAL CHARACTERISTICS continued Maximum pat Power Maximum Output Power Load impedence Load impedance 21 TA 45 C 19 Vcc 18V 17 15 a 5 5 13 15 5 5 11 E gt 9 12 0 0 7 5 3 6 4 5 6 7 8 9 10 3 6 4 5 6 7 8 9 10 21
14. 3 TEXAS TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 20 W MONO DIGITAL INPUT AUDIO AMPLIFIER FEATURES DESCRIPTION Digital Interface The TPA3200D1 is a 20 W per channel efficient 24 bit Resolution digital audio power amplifier for driving a bridged tied Supports 125 and 16 Bit Word speaker The TPA3200D1 can drive a speaker with whe 24 an impedance as low as 4 high efficiency of BONES Usted Manak Input Formats the TPA3200D1 85 eliminates the need for an Multiple Sampling Frequencies external heat sink kHz 200 kH The digital input accepts 16 24 bit data in 125 format 8x Oversampling Digital Filter or 16 bit word right justified A digital filter performs Soft Mute an 8x interpolation function Other features include Power Amplifier soft mute pads input output flag tee 20 W into an 8 Load from an 18 V Supply ere Efficient Operation Eliminates Need for Heat Sinks Three Selectable Fixed Gain Settings Thermal and Short Circuit Protection Simplified Application Circuit TAS3103 PS or 16 bit RJ Digital Audio Processor Control MUTE Inputs DEMP TPA3200D1 GAINO Gain Select m 510 Shutdown Control SHUTDOWN e e Channel Select LR_SEL ae Zero Input Flag ZERO 0 22 uF v 18V 5 Please be aware that an imp
15. 33 Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 SHUTDOWN OPERATION The TPA3200D1 employs a shutdown mode of operation designed to reduce supply current loc to the absolute minimum level during periods of non use for battery power conservation The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low current state locsp 1 SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable Ideally the device should be held in shutdown when the system powers up and brought out of shutdown once any digital circuitry has settled However if SHUTDOWN is to be left unused the terminal may be connected directly to USING LOW ESR CAPACITORS Low ESR capacitors are recommended throughout this application section A real as opposed to ideal capacitor can be modeled simply as a resistor in series with an ideal capacitor The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor A metalized polyester capacitor is recommended for the capacitor placed in parallel across the FLT1 and FLT2 inputs This ensures the best noise performance PRINTED CIRCUIT BOARD PCB LAYOUT Because the TPA3200D1 is
16. 442A MAY 2005 REVISED JULY 2005 Total Harmonic Distortion Plus Noise vs Frequency 20 10 Vec 12 V 5 80 Gain 23 6 dB fs 48 kHz 2 24 bit 25 format 1 0 5 0 2 0 1 Po mW 0 05 1W 0 02 5 0 01 20 100 200 1k 2k 10k 20k f Frequency Hz Figure 6 Total Harmonic Distortion Plus Noise vs Frequency 20 10 18V 8Q 5 Gain 23 6 dB fs 48 kHz 2 24 bit I2S format 1 0 5 0 2 0 1 Po 500 mW 0 02 EE Po 1W 0 02 5 0 01 20 100 200 1k 2k 10k 20k f Frequency Hz Figure 8 TPA3200D1 SLOS442A MAY 2005 REVISED JULY 2005 TYPICAL CHARACTERISTICS continued 10 THD N Total Harmonic Distortion Noise Efficiency Total Harmonic Distortion vs Frequency 10 5 E Vec 12V R 40 Gain 18 dB 2L fs 48 kHz 24 Bit lS format 1 2 0 5 4 0 2 Po 200 mw 0 1 0 05 7 5 0 02 0 01 20 50 100 200 5
17. Conditions in 192 kHz operation are system clock 128 fs and oversampling rate 64 fs of register 18 TPA3200D1 SLOS442A MAY 2005 REVISED JULY 2005 FORMAT CHARACTERISTICS All specifications at T 25 C Vp 5 V fs 44 1 kHz system clock 384 fs and 24 bit data unless otherwise noted TEXAS INSTRUMENTS www ti com PARAMETER TEST CONDITIONS MIN TYP UNIT Resolution 24 Bits Data Audio data interface format Audio 25 standard Audio data bit length Audio 16 24 bit 125 16 bit Right justified Audio data format MSB first 2s complement System clock frequency 128 fs 192 fs 256 fs 384 fs 512 fs 768 fs 1152 fs ELECTRICAL CHARACTERISTICS at Ta 25 C PVoc Voc 12 V unless otherwise noted PARAMETER TEST CONDITIONS MIN UNIT 1 Output offset voltage measured differentially MUTE 2 V Ay 12 dB 100 mV PSRR Power supply rejection ratio 11 5 V to 12 5 V 73 Veer 5 V regulator voltage 10 mA Veg 8 V 18 4 55 49 5 45 V SHUTDOWN 2 0 V No load 8 15 mA loc Supply current SHUTDOWN Vec Voc 18 V 20 W 1 3 80 lcc sp Supply current shutdown mode SHUTDOWN 0 8 V 1 2 pA P on resistance high side and lo 0 5 A 25 C 0 5 0 6 07 GAIN1 0 8 V GAINO 0 8 V 10 9 12 13 1 GAIN1 0 8 V GAINO
18. ITE OEE 2 Vit Low level input voltage POC DEP SOUS DATA 0 8 Vin High level input voltage LR_SEL VDD x 0 7 Vit Low level input voltage LR_SEL VDD x 0 3 SHUTDOWN V VCC VCC 12V 1 GAINO GAIN1 LR SEL Vj VDD VDD 5V 1 High level input current SCLK DATA LRCK V VDD VDD 5 V 10 FORMAT MUTE DEMP V VDD VDD 5 V 100 uA SHUTDOWN Vj 0 V VCC 12V 1 a Low level input current GAINO GAIN1 LR SEL Vj 0 V VDD 5 1 BCK SCLK DATA LRCK FORMAT MUTE DEMP 10 Vi20V VDD 5V Vou High level output voltage 1 mA ZERO 2 4 VoL Low level output voltage lo 1 mA ZERO 0 4 fosc Oscillator frequency 200 300 kHz ELECTRICAL CHARACTERISTICS All specifications at T 25 C Vp 5 V fs 44 1 kHz system clock 384 fs and 24 bit data unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY REQUIREMENTS fg 44 1 kHz 26 31 Ipp Supply current fg 96 kHz 25 mA fg 192 kHz 30 DIGITAL FILTER PERFORMANCE FILTER CHARACTERISTICS Pass band 0 04 dB 0 454 fs Stop band 0 546 f Pass band ripple 0 04 dB Stop band attenuation Stop band 0 546 fs 50 dB ANALOG FILTER PERFORMANCE At 20 kHz 0 03 Frequency response dB At 44 kHz 0 20 SAMPLING FREQUENCY fs Sampling frequency 5 200 KHz DYNAMIC PERFORMANCE Channel separation fg 44 1 KHz 96 KHz 192 KHz 100 dB 1
19. Load Impedance 2 21 Load Impedance 2 Figure 13 Figure 14 De emphasis Level De emphasis Error vs vs Frequency Frequency 0 0 5 1 0 4 22 0 3 S 3 02 4 5 0 1 5 K 5 2 0 0 8 5 6 a 0 1 amp 7 amp 0 2 8 0 3 9 0 4 10 0 5 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 f Frequency kHz f Frequency kHz Figure 15 Figure 16 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 APPLICATION INFORMATION l S RJ Clocks D gt 4 SCLK amp Data llb Cr nc FORMAT Control DATA min MUTE OOJ A Inputs Cor DEMP 4i CIC Deno DGND voo LL vob ZERO BD Zero Flag Output OUR lca DGND T VDD rr Fo o 15 DGND FLT2 OO 22nF 0 1 pF L5 Tr vcom vec Ho 10 pF CIT caino VREF Gain Control 4 GAIN BYPASS OO cis pois 1 uF Shutdown Control gt SHUTDOWN cosc Bra C e 220 pF IL PGND ROSC 1uF 120 VCLAMP O v p Nc AGND ES 510 0 22 uF o ssn BsP OO 022uF 510 vcc 9 1r Pvcc Pvcc OO 7 vcc Cor OUTN Cor OUTN ourP 22 uF 1 pF 1 pF PGND PGND E PGND PGND and DGND e e e connected at 7 power supply 1 1
20. ambient temperature for an application that requires the TPA3200D1 to drive 20 W into an 8 speaker UNVM PDissipated 20 W x 515 1 3 53 W Tamax 150 C 25 6 C W x 1 76 W 59 6 C This calculation shows that the TPA3200D1 can drive 20 W of RMS power into an 8 Q speaker up to a maximum ambient temperature rating of 60 GAIN SETTING VIA GAINO AND GAIN1 INPUTS The gain of the TPA3200D1 is set by two input terminals GAINO and GAIN1 See Table 6 Table 6 Gain Settings AMPLIFIER GAIN Output Voltage with Full Scale Input GAIN1 GAINO dB and Vpp 5 V Vnus TYP TYP 0 0 12 5 63 0 1 18 11 23 1 0 23 6 21 40 1 1 Reserved Reserved 1 Output clipping with Veg 18 V 21 TPA3200D1 R3 Texas INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 The typical output voltage measured across the load is also given in Table 6 at each of the gain steps This is the expected voltage with a full scale input signal applied at the digital inputs and Vpp 5 V This voltage scales proportionally with a lower or higher Vpp For example if Vpp 4 5 V scale the results in Table 6 by 4 5 5 or 0 9 The differential offset voltage measured across the speaker outputs increases as the gain is increased For the lowest offset voltage specified in the electrical characteristics table set the gain at the lowest step 12 dB POWER SUPPLY DECOUPLING The TPA3200D1 is a high perform
21. ance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion THD is as low as possible Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads For higher frequency transients spikes or digital hash on the line a good low equivalent series resistance ESR ceramic capacitor typically 1 uF placed as close as possible to the device lead works best For filtering lower frequency noise signals a larger aluminum electrolytic capacitor of 10 uF or greater placed near the audio power amplifier is recommended BSN AND BSP CAPACITORS The full H bridge output stage uses only NMOS transistors It therefore requires bootstrap capacitors for the high side of each output to turn on correctly A 0 22 uF ceramic capacitor rated for at least 25 V must be connected from each output to its corresponding bootstrap input Specifically one 0 22 uF capacitor must be connected from OUTP to BSP and one 0 22 uF capacitor must be connected from OUTN to BSN BSN AND BSP RESISTORS To limit the current when charging the bootstrap capacitors a resistor with a value of approximately 50 10 maximum must be placed in series with each bootstrap capacitor The current will be limited to less than 500
22. diodes should have a forward voltage rating of 0 5 V at a minimum of 1 A output current and a dc blocking voltage rating of at least 30 V The diodes must also be rated to operate at a junction temperature of 150 C If short circuit protection is not required the Schottky diodes may be omitted 20 R Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 THERMAL PROTECTION Thermal protection on the TPA3200D1 prevents damage to the device when the internal die temperature exceeds 150 C There is a 15 tolerance on this trip point from device to device Once the die temperature exceeds the thermal set point the device enters into the shutdown state and the outputs are disabled This is not a latched fault The thermal fault is cleared once the temperature of the die is reduced by 15 C The device begins normal operation at this point with no external system interaction THERMAL CONSIDERATIONS OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE To calculate the maximum ambient temperature Equation 2 is used Jmax JA Dissipated where 1509C 0 JA deratingfactor 0 0391 2366 2 The derating factor for the 44 pin DCP package is given in the dissipation rating table To estimate the power dissipation Equation 3 is used 1 P dissipated PO average ass 1 Efficiency 75 for 4 Q load Efficiency 85 for an 8 Q load 3 Example What is the maximum
23. e YY __ __ ___ _ A 022yF le eut 1nF T d d Ferrite 1 ze 15 uH Chip Bead OUTN 9 ne e Q e o22uF Em d EN 1nF Figure 25 Typical LC Output Filter for 4 O Speaker Cutoff Frequency of 41 kHz Ferrite 33 uH Chip Bead OUTP 9 e 8 9 9 A 0 47 BF y 0 1 pF Tl ae and e ES Ferrite 33 uH Chip Bead OUTN 9 e 0 e E 1nF Figure 26 Typical LC Output Filter for 8 Speaker Cutoff Frequency of 41 kHz SHORT CIRCUIT PROTECTION The TPA3200D1 has short circuit protection circuitry on the outputs that prevents damage to the device during output to output shorts output to GND shorts and output to Vcc shorts When a short circuit is detected on the outputs the part immediately disables the output drive and enters into shutdown mode This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high state for normal operation This will clear the short circuit flag and allow for normal operation if the short was removed If the short was not removed the protection circuitry will again activate Two Schottky diodes are required to provide short circuit protection The diodes should be placed as close to the TPA3200D1 as possible with the anodes connected to PGND and the cathodes connected to OUTP and OUTN as shown in the application circuit schematic The
24. e TPAO32D0x family has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage VCC Therefore the differential pre filtered output varies between positive and negative Voc where filtered 50 duty cycle yields 0 V across the load The traditional class D modulation scheme with voltage and current waveforms is shown in Figure 31 Note that even at an average of 0 V across the load 50 duty cycle the current to the load is high causing high loss thus causing a high supply current OUTP OUTN 412V Differential Voltage Across Load 12V Current mr E xr xu Figure 21 Traditional Class D Modulation Scheme s Output Voltage and Current Waveforms Into Inductive Load With No Input TPA3200D1 Texas INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 TPA3200D1 Modulation Scheme The TPA3200D1 uses a modulation scheme that still has each output switching from ground to Vec However OUTP and OUTN are now in phase with each other with no input The duty cycle of OUTP is greater than 50 and OUTN is less than 50 for positive output voltages The duty cycle of OUTP is less than 50 and OUTN is greater than 50 for negative output voltages The voltage across the load is 0 V throughout most of the switching period greatly reducing the switching current which reduces any I R losses the load See
25. ect FMT PIN 43 DATA FORMAT LOW 16 to 24 bit 5 format HIGH 16 bit right justified Table 3 De Emphasis Control DEMP PIN 41 DE EMPHASIS FUNCTION LOW 44 1 kHz de emphasis OFF HIGH 44 1 kHz de emphasis ON Table 4 Mute Control MUTE PIN 42 MUTE LOW Mute OFF HIGH Mute ON Table 5 Channel Output Select LR SEL PIN 7 ACTIVE CHANNEL LOW Right HIGH Left 1 A digital data stream consists of two channels of data In an 125 or right justified data stream the left channel data precedes the right channel data See Figure 20 The LR SEL input selects the channel to send to the mono output OVERSAMPLING RATE CONTROL The TPA3200D1 automatically controls the oversampling rate of the delta sigma D A converters with the system clock rate The oversampling rate is set to 64x oversampling with every system clock and sampling frequency VCOM OUTPUT One unbuffered common mode voltage output pin VCOM pin 10 is brought out for decoupling purposes This pin is nominally biased to a dc voltage level equal to 0 5 x This pin cannot be used to bias external circuits Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 CLASS D OPERATION This section focuses on the class D operation of the TPA3200D1 Traditional Class D Modulation Scheme The traditional class D modulation scheme which is used in th
26. g The SCLK BCK LRCK and DATA input are sensitive high frequency signals that should be shielded by a clean GND layer to avoid interference For a 2 layer PCB shield the signals on the bottom layer with a plane connected to DGND On the top layer route DGND closely around these signals e Output filter The ferrite filter Figure 24 should be placed as close to the output terminals pins 19 20 25 and 26 as possible for the best EMI performance The LC filter Figure 25 and Figure 26 should be placed closest to the output and followed by a ferrite bead filter The capacitors used in both the ferrite and LC filters should be grounded to power ground e PowerPAD The PowerPAD must be soldered to the PCB for proper thermal performance and optimal reliability The dimensions of the PowerPAD thermal land on the PCB should be 3 5 mm by 9 5 mm Three rows of solid vias six vias per row 0 3302 mm or 13 mils diameter should be equally spaced underneath the thermal land The vias should connect to a solid copper plane either on an internal layer or on the bottom layer of the PCB The vias must be solid vias not thermal relief or webbed vias For additional information see the PowerPAD Thermally Enhanced Package technical brief TI literature number SLMAO02 For an example layout see the TPA3200D1 Evaluation Module TPA3200D1EVM User Manual literature number SLOU173 Both the EVM user manual and the PowerPAD application note are avai
27. he TPA3200D1 is synchronized with LRCK Accordingly internal operation is held when the sampling rate clock of LRCK is changed or when SCK and or BCK is interrupted for a 3 bit clock cycle or longer If SCK BCK and LRCK are provided continuously after this held condition the internal operation is re synchronized automatically in a period of less than 3 fs External resetting is not required TPA3200D1 43 Texas INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 AUDIO DATA FORMATS AND TIMING TPA3200D1 supports 126 and 16 bit word right justified data formats are shown in Figure 20 Data formats are selected using the FORMAT pin on the TPA3200D1 All formats require binary 2s complement MSB first audio data Figure 19 shows a detailed timing diagram for the serial audio interface 1 LRCK 1 4V pi t BCH a tci gt tB BCK f TA fh 1 4V t BCY gt lt gt DATA 1 4V tps gt gt Figure 19 Audio Interface Timing PARAMETERS SYMBOL MIN TYP UNITS pulse cycle time 1 32 fs 1 48 fs 1 64 fs BCK high level time 35 low level time 35 BCK rising edge to LRCK edge tie 10 ns LRCK falling edge to BCK rising edge ta p 10 DATA setup time lips 10 DATA hold time 10 1 fg is the sampling frequency e g 44 1 kHz 48 kHz 96 kHz etc
28. l Hormonic Distortion Plus Noise Total Hormonic Distortion Plus Noise TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS Total Harmonic Distortion Plus Noise vs Output Power 10 5 Vec 12V 8Q Gain 18 dB 2 fs 48 kHz 24 bit 125 format 1 0 5 0 2 10 kHz 0 1 0 05 1 kHz 0 02 20 Hz 0 01 10m 100m 200m 1 2 10 Po Output Power W Figure 1 Harmonic Distortion Plus Noise vs Output Power 10 5 Voc 18V 80 Gain 23 6 dB 2 fs 48 kHz 24 bit 5 format 1 0 5 0 2 10 kHz 0 1 0 05 1 kHz 20 Hz 0 02 0 01 10m 100m 200m 1 2 10 20 Po Output Power W Figure 3 Total Hormonic Distortion Plus Noise 96 THD N Total Harmonic Distortion Noise Total Harmonic Distortion Plus Noise vs Output Power 10 51 12 80 __ Gain 23 6 dB 2 fs 48 kHz 24 bit 125 format 1 0 5 0 2 0 1 0 05 0 02 0 01 100m 200m 1 2 10 Output Power W 10m Figure 2 Total Harmonic Distortion vs Power 10
29. lable on the TI web site at http Awww ti com 23 H PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com 10 Jun 2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Op Temp C Device Marking Samples Drawing Qty 2 6 3 4 5 TPA3200D1DCP NRND HTSSOP DCP 44 40 TBD Call TI Call TI 40 to 85 TPA3200D1 TPA3200D1DCPG4 NRND HTSSOP DCP 44 40 TBD Call TI Call TI 40 to 85 TPA3200D1 TPA3200D1DCPR NRND HTSSOP DCP 44 2000 TBD Call TI Call TI 40 to 85 TPA3200D1 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semico
30. nductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device 6 Multiple Device Markings will be inside parentheses Only one Device Marking contained in parentheses and separated by will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device 9 eag Ball Finish Orderable Devices may have multiple material finish options Finish
31. ons of sale of semiconductor products Testing and other quality control techniques are used to the extent deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices TI is not re
32. ootstrap I O negative high side FET 28 BSP Bootstrap I O positive high side FET 2 16 NC No internal connection 31 ROSC for current setting resistor for ramp generator 32 COSC I O for charge discharging currents onto capacitor for ramp generator creation 33 BYPASS Midrail analog reference voltage 34 VREF Analog 5 V regulated output Not to be used for powering external circuitry 35 VCC High voltage analog power supply 8 V to 18 V 19 20 OUTN Class D 1 2 H bridge negative output Zero flag output HIGH No input present 39 ZERO LOW Data present at input This can be used to shutdown the device when no data is present at input De emphasis control 41 DEMP HIGH 44 1 kHz De emphasis ON LOW 44 1 kHz De emphasis OFF Soft mute control 42 MUTE HIGH Mute ON LOW Mute OFF Audio data format select 43 FORMAT HIGH 16 bit right justified LOW 16 to 24 bit 125 format 44 SCLK System clock input 18 27 PVCC Power supply for H bridge 8 V to 18 V 25 26 OUTP Class D 1 2 H bridge positive output 29 30 AGND Analog ground 14 21 22 23 24 PGND Power ground for H bridge 10 VCOM Midrail digital reference voltage 36 FLT2 VO Noise filter terminals Connect capacitor across pins 36 and 37 37 FLT1 Thermal Pad Connect to AGND and PGND should be the center point for both grounds Internal esistive connection to AGND TPA3200D1 SLOS442A MAY 2005 REVISED JULY 2005 Tota
33. ortant notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PowerPAD is a trademark of Texas Instruments PRODUCTION DATA information is current as of publication date Copyright 2005 Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters TPA3200D1 SLOS442A MAY 2005 REVISED JULY 2005 A AVAILABLE OPTIONS TEXAS INSTRUMENTS Ta PACKAGED DEVICE 44 DCP 40 C to 85 C TPA3200D1DCP 1 The DCP package is available taped and reeled To order a taped and reeled part add the suffix R to the part number e g TPA3200D1DCPR ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted www ti com These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates TPA3200D1 UNIT Vss Supply voltage VCC 0 3 to 21 V Supply voltage VDD 0 3 to 6 5 V RL Load Impedance 23 6 Q SHUTDOWN 0 3 to Voc 0 3 V Vi GAINO GAIN1 SCLK DATA LRCK LR SEL 0 3
34. otection Detect Biases and References Ramp Generator VREF AGND AVCC Logic Thermal TPA3200D1 SLOS442A MAY 2005 REVISED JULY 2005 BCK NC DATA LRCK DGND VDD LR_SEL VDD DGND VCOM GAINO GAIN1 SHUTDOWN PGND VCLAMP DCP TOP VIEW 18 20 21 22 SCLK FORMAT MUTE DEMP DGND ZERO DGND FLT1 FLT2 VREF BYPASS COSC ROSC AGND AGND BSP PVCC OUTP OUTP PGND PGND TEXAS INSTRUMENTS www ti com 43 Texas TPA3200D1 INSTRUMENTS www ti com SLOS442A MAY 2005 REVISED JULY 2005 Terminal Functions TERMINAL yo DESCRIPTION NO NAME 1 BCK Bit clock input for audio data 3 DATA Audio data input 4 LRCK Left and right channel audio data latch enable input Select left channel or right channel data 7 LR_SEL HIGH Left channel active LOW Right channel active 11 GAINO Gain select least significant bit TTL logic levels with compliance to 5 V 12 GAIN1 Gain select most significant bit TTL logic levels with compliance to 5 V SHUTDOWN Shutdown signal for IC low shutdown high operational 13 TTL logic levels with compliance to 18 V 5 9 38 40 DGND Digital ground 6 8 VDD Digital power supply 4 5 V 5 5 V 15 VCLAMP Internally generated voltage supply for bootstrap capacitor 17 BSN B
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36. s Nonetheless such components are subject to these terms No TI components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Compute
37. sponsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases components may be promoted specifically to facilitate safety related applications With such components goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirement
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