Home

PDF version - ARM Information Center

1. Copyright 2010 ARM Limited All rights reserved 14 Programmer s model 5 4 2 SYS MEMCFG 0xDFFF0004 The Memory Configuration register is reset only by power on reset soft resets such as debug or system reset do not alter the state of this register The default value allows the MPS to boot from Flash memory Refer to section 5 1 for details of the function of the REMAP and ALIAS bits Name Bits Power On Reset Reserved 31 2 oct ALIAS 1 RW bt JAlias FLASH 1 is Aliased on O Aliased off REMAP 0 RW bo J Remap SSRAM 1 is Remap on 0 Remap off 5 4 8 SYS SW 0xDFFF0008 The Switch register returns the value of the eight switches arranged as two groups of four labeled P1 and P2 on the HMALC AS3 board 1 Name Bits Reserved 31 8 EE Ss USER SWITCH 7 0 RO h Value depends on switch settings 5 4 4 SYS LED 0xDFFF000C The LED register controls the eight processor LEDs on the HMALC ASS board 1 unless overridden by SYS CTRL1 Name Bits Reserved 31 8 LED 7 0 Write 1 to light the corresponding LED Reads return the last value written to the register 5 4 5 SYS TS 0xDFFF0010 The TouchScreen status register shows the busy and interrupt status from a touchscreen device on the Hpe midiv2 baseboard TS INT 1 RO fb External Interrupt from Touchscreen TS BUSY 0 RO b Exteral Busy signal from Touchscreen Application Note 232 Copyright 2010 ARM Limited All rights res
2. FPU exception event The processor FPIXC FPOFC FPUFC FPIOC FPDZC and FPIDC pins are not used Table 2 Cortex M4 System Configuration 2 2 Software Program mable Configuration Some aspects of the processor and system may be dynamically configured by software using the CPU FPGA System Registers see section 5 4 Table 3 shows the software configu rable features in this FPGA image Configuration Register Comments SYS CPUCFG The Cortex M4 MPUDISABLE FPUDISABLE and DBGEN signals are driven by SYS CPUCFG register SYS BASE The Cortex M4 FPGA does not support any software programmable configuration The SYS BASE register is Read Only The SYS BASE reflect the location of the CoreSight debug ROM table Table 3 Software Programmab The SYS CPUCFG register is r is shown in Table 4 le Configuration eadable and writable The definition of the SYS CPUCFG register 0xDFFF0028 Bit Definition Reset Connected signals Valid values 31 3 Reserved Read as 0 2 Debug Disable 0 Invert of DBGEN 0 Debug enabled 1 Debug disabled 1 FPU Disable 0 FPU DISABLE 0 FPU functional 1 FPU disabled 0 MPU Disable 0 MPU DISABLE 0 MPU functional 1 MPU disabled Table 4 SYS_CPUCFG register definition 4 Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B MPS Architecture 3 MPS Architecture The
3. MICTOR_TRACEPKT output 15 0 TRACEDATA 15 1 0 from the processor MICTOR TRACESYNC output Unused Tied to 0 MICTOR_TRACECLK output Connects to processor TRACECLK port 6 10 RS232 connection X4 The CPU FPGA includes one UART implemented using PrimeCell PLO11 7 FPGA Signal Direction Width Note RS1 RXD LVTTL input R81 TXD LVTTL output 22 Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B
4. Debug Level DEBUG LVL 3 Full debug with data matching All debug functionality is present including data matching for watchpoint generation 8 Breakpoints 4 Watchpoints Trace Level TRACE LVL 2 Full trace ARMv7 M ITM ARMv7 M TPIU ETM and DWT triggers and counters are present The TPIU provides 4 bit wide trace on the Mictor trace connector X14 The trace clock is the same as the CPU clock Register Reset RESET ALL REGS 0 Only essential registers are reset Debug Interface JTAG PRESENT 1 JTAG and Serial Wire debug interfaces supported by the DAP Architectural Clock Gating CLKGATE PRESENT 0 Clock gating is not implemented in the FPGA Wake up Interrupt Controller WIC PRESENT 0 The WIC is not implemented in the FPGA Bit band support BB PRESENT 1 Bit banding is implemented in the FPGA FPU support FPU PRESENT 1 FPU is implemented in the FPGA Table 1 Cortex M4 Processor Configuration Application Note 232 Copyright 2010 ARM Limited All rights reserved 3 ARM DAI0232B About the Processor Implementation System Configuration Option Comments Power Management Unit Sleep modes will not offer any power saving because there is no PMU implemented in the FPGA System Timer Reference Clock The SysTick timer is provided with a 100kHz reference clock The appropriate 10ms calibration value is also provided Multi Processor Communications The processor TXEV and RXEV pins are exported to the DUT
5. FPGA IC 35 33 output HBURST 2 0 FPGA IC 36 output HMASTLOCK FPGA IC 40 37 output 3 0 HPROT FPGA IC 43 41 output 2 0 HSIZE FPGA 1C 45 44 output 1 0 HTRANS FPGA IC 46 output Reserved for HSEL tied to 1 b1 FPGA IC 78 47 output 31 0 HADDR FPGA IC 110 79 input 31 0 HRDATA FPGA IC 111 input HRESP FPGA IC 1 12 input HREADY FPGA IC 113 output HRESETn 6 5 Processor Miscellaneous Signals The following CPU signals are exported to the DUT FPGA FPGA Signal Direction Width Note FPGA IC 125 114 input 11 0 INT 11 0 L14 DUTOUT DN 1 1 0 input 23 12 INT 23 12 L14 DUTOUT DN 12 input NMI L14 CPUOUT DN 0 output SLEEPING L14 CPUOUT DN 1 output SLEEPDEEP L14 CPUOUT DN 2 output HALTED 20 Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B Signal assignments L14 CPUOUT DN 3 output LOCKUP L14 CPUOUT DN 4 output TXEV L14 CPUOUT DN 5 input RXEV Tie low if not used by DUT L14 CPUOUT DN 6 input WDOGRES Watchdog Reset Request tie low if not used by DUT L14 CPUOUT DN 12 7 N C L14 CPUOUT DP 9 0 N C L14 CPUOUT CLK N C 6 6 Touch Screen Interface The TouchScreen SPI interface is driven by PrimeCell PLO22 6 Additional signals are visible via the TouchScreen Status Register see section 5 4 5 FPGA Signal Direction Width Note TOUCH SPI BUSY
6. be configured to route the CPU FPGA programmable clock back to the CPU and DUT FPGAs as HCLK on signal CLK1p If you need to operate the MPS at an HCLK frequency not supported by the clock switcher above a suitable HCLK must be generated within the DUT FPGA and the Clock Factory configured to route it to CLK1p Since the flash wait state configuration register adjusts automatically according to the clock frequency selection in such case using DUT for system clock generation you may still want to program the clock configuration register and the flash configuration register to adjust the flash memory wait state At reset power on reset as well as system reset the flash memory defaults to 3 wait states per access You must ensure that the selected wait state configuration is acceptable for the HCLK frequency you are driving from the DUT The CPU FPGA is reset by the USER RESET signal The PLL lock status output is also factored in to ensure the FPGA does not leave reset before the PLL has stabilized The CPU FPGA drives the AHB HRESETn signal to the DUT FPGA to create a synchronous reset with respect to HCLK The DUT FPGA can use this to resynchronise resets to all other local clock domains as required A Reset may be generated by e Pushing the Reset Button e Writing 1 to the ARM Cortex M architected reset request bit AIRCR SYSRESETREQ This may be done by code executing on the processor or by an external debugger Note that the reset i
7. register controls the number of wait states inserted by the memory controller when accessing Flash memory The default value of three wait states is required for the default operating frequency of 50MHz The register contains hardware logic to determine if the write data is valid for the current operating frequency and automatically forces the write data to a valid value if necessary If the clock frequency setting is updated to a higher frequency WSCFG is automatically updated to a valid value if necessary Table 8 shows the valid wait state configurations when running at the different clock frequencies supported by SYS CLKCFG Name Bits Reserved 31 2 WSCFG 1 0 Note 0x3 3 wait states on read 3 wait states on write 0x2 2 wait states on read 2 wait states on write Ox1 1 wait state on read 1 wait state on write 0x0 O wait state on read 1 wait state on write Frequency MHz 3 Wait States 2WaitStates 1 Wait State 0 Wait State Yes E Yes Yes 15 20 25 Yes Yes 1 2 4 6 8 10 12 Yes Yes Yes Table 8 Valid Wait State Configurations 5 4 9 SYS CPUCFG 0xDFFF0028 The CPU Configuration register is used to control various processor specific features Refer to section 2 to determine if and how this register is used by the processor FPGA Name Bits Access Reset Note 31 8 ll Processor Specific Refer to section 2 5 4 10 SYS BASE 0xDFFF0038 The SYS BASE register drives the
8. system flash memory Refer to the MPS QuickStart Guide 4 for details of setting up and using the MPS including how to download an alternative ARM processor image to the CPU FPGA Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B 2 About the Processor Implementation About the Processor Implementation The FPGA image supplied with this Application Note contains an implementation of the ARM Cortex M4 EAC release processor plus peripherals and bus infrastructure which are described in section 2 2 The ARM Cortex M4 processor implements the ARMv7 M architecture The FPGA image provided is in encrypted pof format 2 1 fpga processor cm4 encrypted pof Fixed Configuration The ARM Cortex M4 EAC processor includes a number of configuration options that may be set when the device is synthesized Table 1 lists the options chosen for the FPGA implementation that accompanies this Application Note Table 2 lists the system configuration choices that are relevant to this FPGA image The Configuration Name is the Verilog parameter name used to configure the processor and is included for reference for processor licencees Core Configuration Option Configuration Name Value Comments Number of Interrupts NUM IRQ 32 32 external IRQs Interrupt Priority LVL WIDTH 3 8 levels of interrupt priority 25 Memory Protection Unit MPU PRESENT 1 MPU present
9. 10 0000 0xE000 0000 OxD000 0000 0xC000 0000 0xB000 0000 0xA000 0000 0x9000 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x5000 0000 0x4000 0000 0x3000 0000 0x2000 0000 0x1000 0000 0x0000 0000 0xE000 0000 V6 M Reserved V6 M V7 M System Bus Reserved OxDFFF 1000 OxDFFF 6000 OxDFFF OFEC r1 CPU FPGA OxDFFF 0000 Config Regs OxDFFF 5000 PLO11 3 Reserved OxDFFE 0000 Reserved OxDFFF 4000 PLO22 TouchScrn OxbFFF 3000 DS702 PC DVI OxbEFF 2000 Reserved OxDFFF 003C ID2 OxDFFE 1000 Reserved OxDFFF 0038 Debug BASE OxDFFF 0000 CPU Sys Regs OxDFFF 0034 Reserved OxDFFF 0030 Reserved OxDFFF 002C Reserved Ox2FFF FFFF OxDFFF 0028 CPU Config Reserved Reserved 0x2040 0000 OxDFFF 0024 Wait State Config 0x2000 0000 SSRAMO 4M SSRAMO 4M OxDFFF 0020 Clock Config 0x1F00_9000 Reserved Reserved OXDFFF_001C Reserved OxlEFF 0000 RAM FPGA 64k RAM FPGA 64k OxDFFF 0018 Reserved OxDFEF 0014 Misc CTRL1 Reserved Ox1C00 0000 OxDFFE 0010 TS Status Reserved OxDFFF_ 000C CPU LEDs Flash 64M alias OxDFFF_0008 CPU Switches 0x1800_0000 OxDFFF 0004 Remap Alias OxDFFF 0000 System ID 0x1080 0000 Reserved Reserved 0x1040 0000 0x1000 0000 SSRAM1 4M SSRAM1 4M ALIAS 1 ALIAS 0 Int RAM Exec 000 0000 Int ROM Exec
10. 5 describes the cycle performance of the CPU FPGA components shown in Figure 4 This information should be considered when benchmarking the performance of software running on the MPS Component Wait States Note AHB Lite Mux 0 Implemented as combinatorial logic and therefore do not introduce any cycle delays even when switching between segments SSRAMO The two SSRAM blocks use ZBT RAMs to provide zero wait state access SSRAM1 0 best case SSRAM shares physical pins with FLASH so wait states may be incurred when accessing the FLASH and SSRAM1 in sequence For benchmarking purposes it is advisable to avoid using both the FLASH and SSRAM1 simultaneously For best performance program code from FLASH can be copied to SSRAM for execution FLASH 3 default The FLASH memory interface inserts wait states according to the value programmed in SYS WSCFG and the clock frequency selected by SYS CLKCFG see section 5 4 for further details RAM FPGA The RAM FPGA block uses FPGA No Bus Latency RAM internally to provide zero wait state access AHB to APB Bridge The AHB APB bridge adds 1 wait state for accesses to the local peripherals and System Registers Table 5 AHB Component Cycle Performance Application Note 232 ARM DAI0232B Copyright 2010 ARM Limited All rights reserved 4 3 Clocks and Resets CPU FPGA Architecture The example reference system
11. Application Note 232 Using the Cortex M4 processor on the Microcontroller Prototyping System Document number ARM DAI0232B Issued May 2010 Copyright ARM Limited 2010 ARM Application Note 232 Using the Cortex M4 processor on the Microcontroller Prototyping System Copyright 2010 ARM Limited All rights reserved Release information The following changes have been made to this Application Note Date October 2009 May 2010 Issue Change A First release Beta B Second release EAC Change history SYS CPUCFG register definition changed Version controlled by Domino Doc DS158 GENC 009974 4 0 References Document Issuer 1 User Manual for HMALC AS3 52 Gleichmann Industries 2 HPE Desk Basic Online Help Gleichmann Industries 3 AN227 Using the Microcontroller Prototyping ARM Ltd System with the example reference design 4 MPS QuickStart Guide ARM Ltd 5 CH7303 HDTV DVI Transmitter CH7303 Data Chrontel Sheet 6 PrimeCell Synchronous Serial Port PLO22 ARM Ltd Technical Reference Manual 7 PrimeCell amp UART PLO11 Technical Reference ARM Ltd Manual Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B Proprietary notice ARM ARM Powered StrongARM Thumb Multi ICE ModelGen PrimeCell PrimeXsys RealView TrustZone Jazelle ARM7TDMI ARM9TDMI ARMulator AMBA and The Architecture for the Digital World are registered trademarks of ARM Limited C
12. Gleichmann Microcontroller Prototyping System includes two FPGAs on which an AHB Lite AMBA 2 0 system is implemented e CPU FPGA e DUT FPGA Figure 3 shows a high level block view of the MPS This Application Note describes the CPU FPGA Refer to 3 for details of the DUT FPGA including how to customize and rebuild the DUT FPGA ss Mplemente de e e e Not Implemented e e Hpe _midiv2 Base Board E EEE UART Switches LEDs Switches LEDs Ethernet CAN Flexray LIN HMALC AS3 Processor Board Trace Debug CPU FPGA m AHB Lit eeece Zeeececeece Video DMB SMB UARTS AC97 SD MMC PC SPI Figure 3 Block diagram of the Microcontroller Prototyping System Application Note 232 Copyright 2010 ARM Limited All rights reserved 5 ARM DAI0232B CPU FPGA Architecture 4 CPU FPGA Architecture The CPU FPGA contains e ARM Cortex M4 processor with o o o O Serial Wire and JTAG Debug Access Port DAP ARMv7 M Embedded Trace Macrocell ETM ARMv7 M Instrumentation Trace Macrocell ITM ARMv7 M Trace Port Interface Unit TPIU e AHB Memory Controllers that interface to o O o 64k FPGA RAM Internal No Bus Latency RAM 8MB SSRAM Zero Bus Turnaround SSRAM 64MB NOR FLASH e AHB Master Interface to the DUT FPGA e AHB to APB bridge o o o APB Registers Configuration of local components Interfaces to LEDs and Switches APB Pri
13. Int ROM Exec Reserved Reserved 0x0400 0000 RR Flash 60M 0x0020 0000 Flash 64M 0x0000 0000 SSRAM 4M REMAP 1 REMAP 0 Figure 7 CPU FPGA memory map 12 Figure 7 shows the memory map of the CPU FPGA SSRAMO provides 4MB of RAM in the architected ARMv6 M and ARMv7 M SRAM memory region SSRAM1 provides an additional 4MB of RAM within the architected CODE memory region SSRAM1 can be used to provide zero wait state code access in fast systems and to allow code development without the need to reprogram the Flash memory The REMAP and ALIAS control bits are available to software via the SYS MEMCFG register Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B 5 3 CPU FPGA Peripherals Programmer s model The CPU FPGA includes the local peripherals listed in Table 6 Details of the PrimeCell UART PLO11 and SSP PL022 can be found in 7 and 6 Details of the DS072 and the CPU System Registers can be found in section 5 4 Address Peripheral Usage OxDFFF6000 OxDFFFFFFF Reserved OxDFFF5000 0xDFFFSFFF PLO11 RS232 interface UARTS used by BootMonitor OxDFFF4000 OXDFFFAFFF PLO22 SSP interface to touchscreen controller on Hpe midiv2 OxDFFF3000 OxDFFFSFFF DS072 C interface to DVI Transmitter on Hpe midiv2 OxDFFF1000 OxDFFF2FFF Reserved OxDFFF0000 OXDFFFOFFF CPU System Registers LEDs Switches and local configur
14. application note 3 details the clock and reset structure of the overall MPS system Figure 5 shows the clocks used within the CPU FPGA CLK100M L2 CLKOUTO R2 CLKOUTO CLK10p 25M CLKip CPU FPGA SYS_CLKCFG HCLK CPU AHB PLO11 UART Reference Clock PLO22 SPI Reference Clock Ls ceugystix Reference Clock Figure 5 CPU FPGA Clocks The CPU FPGA uses the following clocks e CLK100M 100MHz reference from the oscillator to drive the PLL e CLK1p HCLK from the clock factory AHB subsystem e CLK10p 25MHz reference from the clock factory PrimeCell reference clock for SPI and UART and divided down to generate 100kHz SysTick external clock reference The CPU FPGA generates the following clocks e CPU PLL R2 CLKOUTO for use as HCLK when re distributed by the Clock Factory e CPU PLL L2 CLKOUTO 25MHz clock to Clock Factory The CPU FPGA uses one internal PLL to generate a range of fixed clock frequencies from the 100MHz reference clock A software controllable block allows code running on the processor or a debugger to change the HCLK frequency of the system by switching between these PLL generated clocks See section 5 4 7 for details of how to program the HCLK frequency Application Note 232 Copyright 2010 ARM Limited All rights reserved ARM DAI0232B CPU FPGA Architecture 4 3 1 Resets For normal operation the Clock Factory must
15. ation controls Table 6 CPU FPGA Peripherals Application Note 232 Copyright 2010 ARM Limited All rights reserved 13 ARM DAI0232B Programmer s model 5 4 CPU FPGA System Registers The CPU System Registers are based at address 0xDFFF0000 Table 7 lists the registers Full descriptions can be found in the following sections Address Register Description OxDFFFO0000 SYS ID ID Registers OxDFFFO0004 SYS MEMCFG Memory Configuration including REMAP and ALIAS controls OxDFFFOO08 SYS SW CPU DIP Switches OxDFFFOO0C SYS LED CPU LEDs OxDFFFO0010 SYS TS TouchScreen Status OxDFFF0014 SYS CTRL1 Miscellaneous Configuration OxDFFF0018 Reserved OxDFFF001C Reserved OxDFFF0020 SYS CLKCFG Clock Configuration OxDFFF0024 SYS WSCFG Wait State Configuration OxDFFF0028 SYS CPUCFG CPU Configuration OxDFFF002C Reserved OxDFFF0030 Reserved OxDFFFO0034 Reserved OxDFFF0038 SYS BASE Debug Access Port CoreSight Component Pointer Address OxDFFFOOSC SYS ID2 Secondary Identification Register OxDFFF0040 Reserved OxDFFFOFFC Table 7 CPU FPGA System Registers 5 4 1 SYS ID 0xDFFF0000 The System Identification register returns a value specific to the CPU FPGA image Application Note 232 ARM DAI0232B Bits 31 28 27 16 15 12 11 8 7 0 Note Board Revision B HBI Board number Build Variant of board Bus Architecture 4 AHB 5 AXI FPGA build
16. bugger cable is detected otherwise they are routed to the Mictor connector 6 9 1 Rear Panel JTAG Connector X14 Debug FPGA Signal Direction Width Note FTSH GNDDET bi dir Connector Detect Weak pull up on FPGA which is pulled low by the connector to indicate a connection FTSH TMS bi dir Input to SWDIOTMS on processor Also used as Data Out for Serial Wire Debug FTSH TCK bi dir JTAG Clock to processor FTSH TDO bi dir JTAG Data Out from processor FTSH TDI bi dir JTAG Data In to processor FTSH TRST bi dir JT AG Reset This is an active low signal 6 9 2 Mictor Connector X14 The Mictor connector allows a Trace probe to be connected to processors that support ETM FPGA Signal Direction Width Note INTCPU TDI input JTAG Data In to processor INTCPU TDO bi dir JTAG Data Out from processor INTCPU TCK input JTAG Clock to processor INTCPU TMS input Input to TMS on processor This is not connected to the Serial Wire Debug Data Out INTCPU TRSTn input JTAG TAP Reset This is an active low signal INTCPU SRSTn input Factored into CPU reset INTCPU RTCK output Unused Tied to 0 INTCPU DBGRQ input Not connected INTCPU DBGACK output Unused Tied to 0 MICTOR PIPESTATO output TRACEDATA 0 from the processor MICTOR_PIPESTAT1 output Tied to 0 MICTOR_PIPESTAT2 output Tied to 1 MICTOR_EXTTRIG output Tied to 0
17. erved 15 ARM DAIO232B Programmer s model 5 4 6 SYS CTRL1 0xDFFF0014 The Miscellaneous control register allows the function of the eight processor LEDs that are normally controlled by the SYS_LED register to be overridden with the status of various processor outputs The output signals are pulse stretched to ensure that single cycle pulses are visible as flashes on the LEDs Note Write 0 to drive LEDs from SYS_LED register Write 1 to drive LEDs from CPU status signals SLEEPING SLEEPDEEP HALTED LOCKUP SYSRESETREQ TXEV WAKEUP DBGRESTARTED O NWAMON 5 4 7 SYS CLKCFG 0xDFFF0020 The Clock Configuration register allows the clock speed of the processor and its AHB subsystem to be modified easily by software for benchmarking purposes Attempting to write a reserved value to this register will result in a valid clock value being selected Note that when 12MHz setting is used the duty cycle of the output clock can either be 40 or 60 Name Bits Note Reserved 31 4 CLOCKCFG 3 0 OxF OxE Reserved OxD 50MHz OxC 40MHz OxB 30MHz OxA 25MHz 0x9 20MHz 0x8 15MHz 0x7 12MHz 0x6 10MHz 0x5 8MHz 0x4 eMHz 0x3 4MHz 0x2 2MHz 0x1 1MHz 0x0 Reserved 16 Copyright O 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B Programmer s model 5 4 8 SYS WSCFG 0xDFFF0024 The Wait State configuration
18. heral is based at address OxDFFF4000 and is used to interface to the touchscreen on the baseboard 5 7 PLO11 UART Interface The PLO11 PrimeCell peripheral is based at address OxDFFF5000 and provides the UART3 RS 232 serial interface This interface may be used by the BootMonitor software see 3 for more details Application Note 232 Copyright 2010 ARM Limited All rights reserved 19 ARM DAI0232B Signal assignments 6 Signal assignments 6 1 Resets FPGA Signal Direction Width Note USER RESETn input User reset 6 2 Clocks from Clock Factory FPGA Signal Direction Width Note CPU CLK1 input AHB and Processor clock input HCLK CPU CLK5 input Not used CPU CLK10 input Peripheral reference clock input 25MHz CPU CLK15 input Not used CPU CLK100M input 100MHz reference clock 6 3 Clocks to Clock Factory FPGA Signal Direction Width Note CPU PLL L2 CLKOUTO output Peripheral reference clock from FPGA PLL 25MHz CPU PLL R2 CLKOUTO output AHB and Processor clock from FPGA PLL 1 50MHz CPU PLL B1 CLKOUTS output Not used by clock factory 60MHz CPU PLL T1 CLKOUTS3 output Not used by clock factory 40MHz 6 4 AHB Lite Interface to DUT The CPU FPGA implements a 32bit AHB Lite master interface to the DUT FPGA FPGA Signal Direction Width Note FPGA IC 31 0 output 31 0 HWDATA FPGA IC 32 output HWRITE
19. input Connects to TS BUSY TOUCH SPI CS amp output Driven by TS FSSOUT TOUCH SPI DCLK output Driven by TS CLK TOUCH SPI DIN input Connects to TS DIN TOUCH SPI DOUT output Driven by TS DOUT TOUCH SPI IRQ input Connects to TS INTn 6 7 LCD VGA DVI The CPU FPGA de multiplexes signals from the DUT FPGA and passes them on to the LCD connector and DVI transmitter Refer to 3 for details of how to drive these interfaces from the DUT FPGA The DVI Transmitter 5 is controlled using an C interface as described in section 5 5 Figure 8 shows the electrical connections for this interface SDA SCL nSDAOUTEN 1 bO gt VIDEO_I2C_SDA Tri stated driver VIDEO_I2C_SCL Driver Figure 8 Video I C Connections 6 8 Human Interface Switches and LEDs FPGA Signal Direction Width Note CPU_DSW input 7 0 Read via System register SYS_SW CPU_LED output 7 0 Set via System Register SYS_LED Application Note 232 Copyright 2010 ARM Limited All rights reserved 21 ARM DAI0232B Signal assignments 6 9 JTAG and Trace The Processor FPGA can support JTAG Serial Wire debug interfaces and a Trace interface Refer to section 2 to determine the options supported by the processor The JTAG Serial Wire debug interface is available on two connectors the rear panel debug connector and the internal Mictor connector The debug interface signals are routed to the rear panel connector if a de
20. meCell Components PLO11 UART UART 3 PL022 SSP interface to TouchScreen controller APB Components DS702 PC interface to DVI Transmitter Application Note 232 Copyright 2010 ARM Limited All rights reserved ARM DAI0232B CPU FPGA Architecture 4 1 Bus Architecture The CPU FPGA implements an AHB bus infrastructure to give the processor access to the local FLASH and SSRAM memory and to the Customer DUT FPGA An APB bus is used to connect local PrimeCell APB peripherals Figure 4 shows the full AHB and APB system code mux AHB Lite mux AHB Lite mux 0x0000 0000 OxO3FF FFFF 0x1000 0000 DEED ERE XI ae aes OxTEFF 0000 0x2000 0000 OxDFFF 0000 OXEO10 0000 0x1 BFF FFFF 0x1 EFF_FFFF 0x203F_FFFF OxDFFF FFFF OxFFFF FFFF AHB to APB SMC1 RAM FPGA SMCO APB Config registers r VO PADS d J VO PADS E VOPADS 1 WOPADS GT EE dy iot m i Peel deste l PLO11 3 PLO22 0 EL rs DS702 0 A AHB Interface to DUT FPGA loss 4 0x2000_0000 Ox203F FFFF 0x1000 0000 And remaped to 0x103F_FFFF 0x0000_0000 0x0000_0000 And aliased to Ox03FF_FFFF 0x1800 0000 Figure 4 CPU FPGA Bus Architecture Application Note 232 Copyright 2010 ARM Limited All rights reserved 7 ARM DAI0232B CPU FPGA Architecture 4 2 Benchmarking Information Table
21. oessesoesossessossesssssssoesossessossessossesoesssso 1 Overview of the hardware platform 4 eeeeee eee e eee sees esee seen ettet tasto aeos stone tane sado ease sed tastes es tte stesse spas eaae eaae 1 Getting startedss stssssisees cores o ssasisaaseaa sado asda 2 ABOUT THE PROCESSOR IMPLEMENTATION ec eeeneeeeeeeeeenn nennen 3 Fixed Earn Palliative sint 3 Software Programmable Configuration eee e eese eee essen enata ense seta soss sonata sesto seta suse ta sone acne tac cenas ess mesa snae 4 MPS ARCHITECTUBE iara rasa eua D IU uA a EUER e aaa rs nennen 5 CPU FPGA ARCHITEGTU RE iriecticn ien odes n at proceder feitas ecu non d as Exe en buona ane E 6 Bus Architecture c s onies 7 Benchmarking Information eeeee esee esee ee enses enata teneat ciast tn senses tosta sone ta sene sad 00 toS osreb STDs sacas sad osr nes asa suae 8 Clocks and 9 PROGRAMMER S MODEL sir Fl eR FRE cu ci D a S E Cc QT e D c rol 11 Interrupt architecture eee 11 Memory Map C ossadas 12 CPU FPGA Peripherals e 13 CPU FPGA System Register ss ccisisssosscssccsesesssvccsosssesostaseesccensnssensaseesoeteseasenissensesvcesssenscasssensessssessacsoserseesonsssessocoosaseus 14 DS072 PC In
22. ortex AXI AHB ARM7 ARM7TDMI S ARM7EJ S ARM720T ARM740T ARM9 ARM9TDMI ARM920T ARM922T ARM940T ARM9E ARM9E S ARM926EJ S ARM946E S ARM966E S ARM968E S ARM996HS ARM10 ARM1020E ARM1022E ARM1026EJ S ARM11 ARM1136J S ARM1136JF S ARM1156T2 S ARM1156T2F S ARM1176JZ S ARM1176JZF S EmbeddedICE EmbeddedICE RT AMBA ARM Development Suite ETM ETM7 ETMS ETM10 ETM10RV ETM11 Embedded Trace Macrocell Embedded Trace Buffer ETB ETB11 Embedded Trace Kit Integrator JTEK Mali MultiTrace MPCore MOVE OptimoDE AudioDE SecurCore SC100 SC110 SC200 SC210 Keil p Vision ULINK are trademarks of ARM Limited Java is a trademark of Sun Microsystems Inc XScale is a trademark of Intel Corporation All other brand names or product names are the property of their respective holders ARM is used to represent ARM Holdings plc LSE ARM and NASDAQ ARMHY its operating company ARM Limited and the regional subsidiaries ARM Inc ARM KK ARM Korea Ltd ARM Taiwan Limited ARM France SAS ARM Consulting Shanghai Co Ltd ARM Belgium N V AXYS Design Automation Inc ARM Germany GmbH ARM Embedded Technologies Pvt Ltd ARM Norway AS and ARMSweden AB Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to contin
23. s not guaranteed to take place immediately after the write e The DUT FPGA asserts signal WDOGRES to the CPU FPGA This could be used to implement a programmable watchdog timer within the DUT See section 6 for details of the signal connections between the CPU and DUT Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAIO232B Programmer s model 5 Programmer s model This chapter describes the MPS Programmer s Model in terms of the CPU FPGA e Interrupt Architecture e Memory Map Parts of the memory map and interrupt allocation depend on the system in the DUT FPGA Refer to 3 for details of the example DUT reference design 5 1 Interrupt architecture The ARM Cortex M processor family include a Nested Vectored Interrupt Controller NVIC which is integrated into the processor Figure 6 shows the mapping of external interrupts to the NVIC The top eight interrupts are reserved for use within the CPU FPGA as shown The remaining interrupts and NMI are available to the DUT FPGA The allocation of these interrupts is dependent on the DUT FPGA 31 PLO22 SPI touchscreen 30 PLO11 0 UART 3 29 Reserved Ext touchscreen CPU FPGA 28 Reserved CPU FPGA CLCD Reserved Figure 6 Interrupt Allocation Table Application Note 232 Copyright 2010 ARM Limited All rights reserved 11 ARM DAI0232B Programmer s model 5 2 Memory map 0x10000 0000 0xF000 0000 OxEO
24. sesessevsecdsudveteessnvccessoteodbesees ee eo ee duel oes dou e een soa suds detesta cas Enab aonde oca cas ivo sta seuvecsssvbeesesss 22 Application Note 232 Copyright 2010 ARM Limited All rights reserved V ARM DAI0232B Introduction 1 Introduction 1 1 Purpose of this application note This Application Note covers the operation of the HMALC AS3 Hpe amp module with the Hpe amp midiv2 FPGA development system from Gleichmann Electronics Research It describes the contents of the CPU FPGA on the HMALC ASS including the clock structure and peripherals local to the CPU After reading this Application Note the user should be able to use the CPU FPGA with the example reference design described in 3 or with their own DUT FPGA design 1 2 Overview of the hardware platform This application note is designed to work on the Microcontroller Prototyping System as shown in Figure 1 fitted with the ARM Hpe amp module as shown in Figure 2 For further details on this system please see 1 ERRAR 7 mnm ES Figure 1 Microcontroller Prototyping System Application Note 232 Copyright O 2010 ARM Limited All rights reserved 1 ARM DAI0232B Introduction Figure 2 ARM Hpe amp module HMALC AS3 1 3 Getting started The system comes pre configured with an example design installed on the customer FPGA described in 3 The CPU FPGA is pre configured with the ARM Cortex M3 processor and BootMonitor software is loaded into the
25. ter interface only the IC protocol must be generated in software using a bit banging technique Table 9 lists the registers Full descriptions can be found in the following sections Address Register Description OxDFFF3000 SB CONTROL Status Register OxDFFF3000 SB CONTROLS Output Set Register Note Same address as SB CONTROL OxDFFF3004 SB CONTROLC Output Clear Register Table 9 DS072 I C Registers 5 5 1 SB CONTROL 0xDFFF3000 The SB CONTROL register returns the value of the serial data SDA and serial clock SCL pins when read SB SDA 1 RO bo X Levelof SDA signal SB SCL 0 RO bo J Levelof SCL signal 18 Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAIO232B Programmer s model 5 5 2 SB CONTROLS 0xDFFF3000 The SB CONTROLS SET register allows the SDA and SCL pins to be pulled high by pullup resistors on the board by writing b1 to the corresponding bit Name Bits Reserved 31 2 SB nSDAOUTEN 1 Sets SDA line when 1 Seseo Jo Ww fo jseis Sine wine 5 5 3 SB CONTROLC 0xDFFF3004 The SB CONTROLC CLEAR register allows the SDA and SCL pins to be driven low by writing b1 to the corresponding bit Name Bits Access Reset Note Reserved 31 2 SB nSDAOUTEN fi Ww bo Clears SDA line when 1 SB SCLOUT 0 W bo Clears SCL line when 1 5 6 PL022 SPI Interface The PL022 PrimeCell perip
26. terface to DVI Transmitter sscssscssscssscsnscsnscssscsnscsnscsnscsnscsnscenscsnsessccsnscenscenscsnecsnscsnscsnsessccancesnecsneesnee 18 PEO22 SPL Ute race decor M M 19 PLOILUART E uero Er HE 19 SIGNAL ASSIGNMENTS iiri rap take ph pu Rar ae t ture Dn casi bia cu ro ka E Ma aaa nie RE CH a cud Sede 20 Dl T M N R RAG 20 Clocks from Clock E Clory MITES 20 Clocks to Clock Factory e 20 AHB Lite Interface to DUT eeeeeeeee eee eee esee ee enses ense tn tune sereno secs atenas seca ae to sone aaa aa sua RSS ta sone acao tastes ense nes seta snae 20 Processor Miscellaneous Signals eee e eee eee ee eee eese suas arenas anta seta sins enses tosta suse tasa sen sens enses ense sess eta sensn ae 20 Copyright 2010 ARM Limited All rights reserved Application Note 232 ARM DAI0232B 6 6 Touch Screen LLL WI L6 RETE DNE oeeo siose seess soies 21 6 7 LCD VGA DWVL itisss ste ee cusa codo evo eet aset eo den cando eoe suno Dose aee e e eETE OS A ence erase oe rae oe Uer ER Oe E Sea ndo sanidade aede e eC eu UVP SESS NU ra aae eR ae 21 6 8 Human Interface Switches and LEDS eee ecce eene eese ee ee eee tn ee eee eee te enses eene seen ases seen sees ease esee toas e ete eese en a 21 6 9 PEA Gand TRA CC iiss RR P RE ES 22 6 10 RS232 connection X4 a cscscccsscsssssavitesscsv
27. uous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith All warranties implied or expressed including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded This document is intended only to provide information to the reader about the product To the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information Confidentiality status This document is Open Access This document has no restriction on distribution Feedback on this Application Note If you have any comments on this Application Note please send email to errata arm com giving e the document title e the document number e the page number s to which your comments refer e an explanation of your comments General suggestions for additions and improvements are also welcome ARM web address http www arm com Application Note 232 Copyright 2010 ARM Limited All rights reserved iii ARM DAIO232B Table of Contents 1 11 1 2 1 3 2 1 2 2 4 1 4 2 4 3 5 1 5 2 5 3 5 4 5 5 5 6 5 7 6 1 6 2 6 3 6 4 6 5 INTRODUCTION sis inda 1 Purpose of this application note sessesseseossesessossesoossesoesoesessossessossesoesseseesossessosses
28. value that an external Serial Wire or JTAG debugger sees when connecting to the Debug Access Port and reading its BASE register Refer to section 2 to determine if this feature is supported by the processor FPGA BASEADDRESS is reset by power on reset to the ARMv6 M and ARMv7 M architected value for the processor ROM table Soft resets such as debug or system reset do not alter the state of this register Application Note 232 Copyright 2010 ARM Limited All rights reserved 17 ARM DAIO232B Programmer s model This register may be updated by software to point to a system level ROM table in the DUT FPGA which in turn points to the architected processor ROM table The system level ROM table s may provide identification of the user s customized processor system and any additional CoreSight compliant peripherals within it This register allows the user to test debug tools connectivity with such customized systems Name Bits BASEADDRESS 31 0 does not support reprogramming of the DAP BASE register value 5 4 11 SYS ID2 OXDFFFO003C The SYS ID2 register may contain additional CPU FPGA build information The format of that information is not specified Name Bis Access Reset Note ID 2 31 0 RO hx Reserved for ARM internal use 5 5 DS072 IC Interface to DVI Transmitter The DS072 IC peripheral is based at address OXDFFF3000 and is used to interface to the DVI transmitter 5 on the baseboard The DS072 implements a simple regis

PDF version - ARM Information Center

Contents

Download Pdf Manuals

Related Search

Related Contents