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1. Don t show this dialog again can be set through preferences dialog Cancel Help FIGURE 21 111 PAntzCF SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams 8 There are two ways of downloading the program into the target hardware one is generating the bit file for downloading into the FPGA device and the other is generating the mcs file for downloading into the PROM device 9 To download the program as bit file in Boundary Scan mode do the following steps i Shunt of Jumper J2 of must be in S3 position for FPGA selection ii In the Project Navigator window and click Implement design in Processes category refer Figure 22 Notice that after Implementation is complete the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings Xilinx ISE EEXEPERMIENTTYADDITION ADDITION ise code vhd M File Edit View Project Source Process Window Help Bx DAHA LB ERARA AR 4M kG OO AA HENDT PPP ES 2 AMO D a o 9E OO Pls 7j o0 S A Sources for Synthesis Impler v 2 expi VHDL CODE FOR 4 BIT ADDITION S ADDITION B 3 xc3s200 4tql 44 A z library IEEE DES addition Behavior T 5 6 use IEEE STD LOGIC 1164 ALL 7 use IEEE STD LOGIC ARITH ALL 8 use IEEE STD LOGIC UNSIGNED ALL d gt E Sources gi Snap gt a
2. PWR ON OFF 13 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 5 4x4 Matrix keypad and Push Button Keypads arranged by matrix format each row and column section pulled by high all row lines and column lines connected directly by the i o pins 4x4 MatrikKeys XC3S200 pins Matrix Format The Spartan3 FPGA Kit has four contact push button switches for interrupt input PUSH BUTTON XC35200 pins SW31 P103 SW 32 P102 14 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 6 Stepper Motor The ULN2803A is a high voltage high current Darlington transistor array The device consists of eight NPN Darlington pairs that feature high voltage outputs with common cathode clamp diodes for switching inductive loads The collector current rating of each Darlington pair 500 mA ULN2803 is used as a driver for port I O lines drivers output connected to stepper motor connector provided for external power supply if needed m Stepper Motor 5V XC3S200 Lines Stepper Motor PWR Select P82 vco COIL A MOTOR_PWR STEPPER IN2 IN3 IN4 H EN1 L7 EN2 Make switch SW1to SM RL label Cs marking position PWR ON OFF For Motor relay designer get power from on board internal or external supply through jumper JP5 by default JP5 pin 1 am
3. 10 entity addition is DES sport oe 12 a in std logic vector 3 downto 0 1st input value 13 b in std logic vector 3 downto 0 2nd input value 3 Add Existing Source 14 output out std logic vector 4 downto 0 output result 7 Create New Source 15 p X View Design Summary 16 end addition 3 4 Design Utilties 17 y User Constraints 18 architecture Behavioral of addition is 3 Q Synthesize XST 19 signal declarations MET m 2f signal store Std logic vector 4 downto 0 Reun p 4 BIT ADDITION MODULE ar Rerun All rocess a b zw egin at Stop Open Without Updating tore lt conv std logic vector conv_integer a conv integer b 5 addition ae Properties utput 3 downto 0 lt store 3 downto 0 sum utput 4 lt store 4 carry end nroaroces v Processes LA Processes f code ar o Started Launching ISE Text Editor to edit code vhd w 1 E Ed E Console QyEmors fy Wamings jg Find in Files Run highlighted process Ln 1 Coli CAPS NUM SCRL VHDL S lLa lh 2a 2 Lad Figure 22 112 PAntzECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 10 After implement design has become successful refer Figure 23 click Generate Programming File refer Figure 24 After generate programming file has been completed successfully cl
4. Transcript s Console Q Eros Jy Warnings A Find in Files CAPS FIGURE 9 4 A window given in Figure 10 will appear Select Project menu New Source refer Figure 11 A window given in Figure 12 will appear Then select VHDL module and specify the file name in appropriate field as shown in figure 13 and Click Next If you want you can give inputs amp outputs in the appropriate positions in the window shown in Figure 14 You can also skip these information by simply clicking Next button and click Finish refer Figure 15 100 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams se Xilinx ISE E EXEPERMIENT1 ADDITION ADDITION ise File Edit View Project Source Process Window Help ng9PHOGOSoBIEEAIdSXxXXXABA4e XBR MAL daent Sources for Synthesis Impler ADDITION E uc3s200 4tq144 Add Existing Source O Create New Source 8 4 Design Utilities Figure 10 101 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Xilinx ISE EVEXEPERMIENT T ADDITIONADDITION ise Fie Edit View SETTE Source Process Window Help e AAR SY BB OO NAL lr BAO Add Source Ins Add Copy of Source Shift Ins Cleanup Project Files Toggle Paths Archive Take Snapshot Make Snapshot Current Apply Project Properties uU M z Add Existing Source FT Create New S
5. A Sources for Spnthesis Impler 2 Company SJADDITION c M RCM n 5 Create Date 23 36 36 06 28 2009 ifs code Behavioral L0 CR Mnt 7 Module Name code Behavioral 8 Project Name 9 Target Devices el AN 10 Tool versions 11 Description Processes il A 13 Dependencies 7 Add Existing Source ia lt lt 7 Create New Source 15 Revision E ViewDesignSummay 16 Revision 0 01 File Created H y Design Utilities 17 Additional Comments E User Constraints Sa aca E Synthesize XST comm m Pm aE Implement Design 20 library IEEE GF Generate Progamming 21 use IEEE STD LOGIC 1164 ALL 22 use IEEE STD LOGIC ARITH ALL 23 use IEEE STD LOGIC UNSIGNED ALL 24 45 Uncomment the following library declaration if instantiating 26 any Xilinx primitives in this code 27 library UNISIM 28 use UNISIM VComponents all 29 30 entity code is c3 231 Dart e in GTh TARI WRCTOD 12 dosmto Mi x h code Design Summary 1 Started Launching Design Summary Y 4 c b Transcript E Console Qm QD Waminos jj Find in Files niColi CAPS NUM SCRL VHDL E untitl E Xilinx addit Figure 16 107 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Xilinx ISE EXEXEPERMIENTT ADDITION ADDITION ise code vhd fy
6. iM PACT Processes Assign Mew Configuration File Look in 9 C tutorial Ca met counter bit IMPACT Process Operations C isim tmp save a il C templates X PROGRESS END En ElanscH time c File name f BATCH CMD S sll Output Error IL Warning Cancel All File type All Design Files bit rbt nky tec bsd Transcript e fyougeta Warning message click OK e Select Bypass to skip any remaining devices e Right click on the xc3s200 device image and select Program The Programming Properties dialog box opens e Click OK to program the device When programming is complete the Program Succeeded message is displayed Program Succeeded e Close iMPACT without saving After successful configuration you can check the output on your target hardware 115 PAntzECF SOLUTIONS Www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams
7. jegsmm Q9 Sources x Sources for Synthesis Impler SJADDITION E xc3s200 4tql 44 Processes x i E Add Existing Source P 3 Create New Source WB Design Utillie Transcript Architecture Name Entity Name New Source Wizard Define Module Behavioral Figure 14 105 PANTECE SOLUTIONS www pantechsolutions net Technology Beyond the Dreams L scheme VLSI Lab M anual Xilinx ISE EXEXEPERMIENT T ADDITIONADDITION ise File Edit View Project Source Process Window Help DBHSOGBGOBISGEIOAISXXXXAB SY XBR one MA aent BJADDITION EF no3s200 4tgl 44 jns New Source Wizard Summary E Add Existing Source Project Navigator will create a new skeleton source with the following specifications Create New Source 7 200 Figure 15 5 A window shown in Figure 16 will appear You can type your VHDL code in the right side of window and save it by clicking on the Save button refer Figure 17 Now in the Processes window double click Synthesize XST as shown in Figure 18 106 PAntECF soLutions www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Xilinx ISE E EXEPERMIENTT ADDITION ADDITION ise code vhd fj File Edit View Project Source Process Window Help BxXx DAHA LDE RTTY AD SY XBR SOMA FF BAO PPP EE SLED AAAKNM Ba Sd No rns r 1
8. s 0 anc s s 1 amd mot s 2 gt not s 0 and not s 1 and s 2 s 0 anc nor s 1 anci 3 2 not s0 anci sll and s 2 lt s 0 andi s 1 anc 2 00000 0 ON nN nn M MM D end data 65 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEM ENTATION OF 7 SEGMENT DECODER Description Develop Boolean expression for 4 input variables and 7 output variables Design and develop seven segment decoder in VHDL for 7 equations A seven segment display is connected to the output of the circuit Four switches are connected to the input The 4 bit input is decoded to 7 segment equivalent Flow Chart SWITCH TO 7 SEGMENT DISPLAY 66 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams PIN Masi dd I O CLK SELO SELI SEL2 SEL3 PINS FPGA P55 P32 P33 P93 P105 P129 P130 P131 P132 P135 P137 P140 P124 P125 P127 P128 Look Up Table 67 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing rror dU BES c use IEEE STD LOGIC 1164 ALLl Uncomment the following library declaration if using camgubmetbuctumnetuons with Sigmed or Unsigned values SSuUse EEE NOUMER We SS Ak Uncomment the following library declaration if TLE LOU IL SHE T 005
9. 5 Rio a D E Console QyEmors gy Wamings Find in Files Ln 28 Col45 CAPS NUM SCRL VHDL FIGURE 19 e Select the Package View tab e In the Design Object List window enter a pin location for each pin in the Loc column using the seeing on board LED amp SWITCHES or refer before pages in manual 110 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams E Xilinx PACE E Mifting based dspVZseglobject co ucf File Edi View IOBs Areas Tools Window Help Os ow AR HS Rees Ba nee Design Browser BH L Device Architecture for xc3s200 4 tq144 BE ss EEE EE eee Hy 1 0 Pins oo Global Logic i clk put v Ese Output BEskb Output Be Output BEsk Output BIO Output Output Output gt Output Output Output B5 o Output Bo Output Figure 20 Select File gt Save You are prompted to select the bus delimiter type window will open Select synplify VHDL exemplar default and click OK refer FIGURE 21 Close PACE Bus Delimiter m Select 10 Bus Delimiter C ST Default lt gt C ST Optional Synplify Verlag Default Sunplifu VHDL Exemplar Default
10. File Edit View Project Source Process Window Help X DAHA LAERA BARA AR SY x88 OO MA rl bera VPP EE 9 5n AANAND Bu d 000 v ns 7i library IEEE use IEEE STD LOGIC 1164 ALL 6 7 use IEEE STD LOGIC ARITH ALL 8 use IEEE STD LOGIC UNSIGNED ALL 9 Sources Sources for S ADDITION E EA xc3s200 4tql 44 fs code Behavioral 10 entity addition is 11 porti gt 12 a in std logic vector 3 downto 0 ist input value E Sources p Snap 13 b sod ao EP NER C downto 0 2nd input value l J 14 output out std logic vector 4 downto 0 output result Pr 15 e P 3 16 end addition rocesses 17 Add Existing Source 18 architecture Behavioral of addition is E Create New Source 19 signal declarations X View Design Summary 20 signal store std logic vector 4 downto 0 HSA Design Utilities 21 begin y User Constraints 22 4 BIT ADDITION MODULE amp E Synthesize XST 23 process a b E P Implement Design i begin BLA Generate Programming 26 store lt conv std logic vector conv integer a conv integer b 5 addition 27 output 3 downto 0 lt store 3 downto 0 8m 28 output 4 lt store 4 carry 29 30 31 end process 32 33 end Behavioral 34 e e m t f code Design Summary re Started Launching Design Summary Ww rr 5 Console Enos Wamings Find
11. SET input B Verify output Y www pantechsolutions net L scheme VLSI Lab M anual Code Listing ibrary IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity sub is Port a in STD LOGIC VECTOR 3 downto 0 b in STD LOGIC VECTOR 3 downto 0 bin in STD LOGIC Diff out STD LOGIC VECTOR 3 downto 0 bout out STD LOGIC end sub architecture Behavioral of sub is component fullsub port a b bin in std logic Diff bout out std logic end component signal D std logic vector 2 downto 0 begin X1 fullsub port map x2 fullsub port map x3 fullsub port map xA fullsub port map end Behavioral library ieee use ieee std logic 1164 all entity fullsub is port a b bin in std logic Diff bout out std logic end fullsub architecture comb of fullsub is begin Diff lt a xor b xor bin bout lt nota and b or not bin and a xor b vend comb 47 PANTECE SOLUTIONS www pantechsolutions net Technology Beyond the Dreams L scheme VLSI Lab M anual Input Waveform We give input a 1010 b 0101 in waveform window End Time 1000 ns 150 ns 250 ns 350 ns 550 ns 650 ns 750 ns B50 ns 950 ns Eb ap gr ad b ag gag ar b d I LL3 Jp gqop qux gu iu bin 0 MI bout D TDR T Den imo momo 0 a Output Waveform We get output in simulation window according to that subtraction Operation Now 10
12. Technology Beyond the Dreams Look Up Table PIN Description I O CLK I1 2 I3 A C E F G SELO SEL1 SEL2 SEL3 mo PP eee LOC 70 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing JL stone eere TUBIS c use IEEE STD LOGIC 1164 ALLI entity SEVEN SEG LUT is D oU Ih 2 aioe SINR ECCO BONO EE Sees ob eub le entibieeb O CHE Coe AO TOR A clave m Ol Ve Ouro IDE OG EC VIS C TORT o Tolosam o O end SEVEN SEG LUT architecture Behavioral of SEVEN SEG LUT is begin Specs process I BEGIN case I is when OOOO gt when 0001 2 when 0010 2 when 0011 2 when 0100 2 when TOOTIS when ONU when TOs when 1000 2 when 1001 gt when others gt end cage lt 1000000 egg SCSUIBEIFGIDXIFOIODE ey 1018 07 c e md gius ECOUTER TONNG D se 06999 9 evi 9999s e 0090000 eO 099r EU ID EE US Fi F4 FS F4 F4 F4 F4 FS FS FS FS end process end Belay bora ll 71 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEM ENTATION OF ENCODER Encoder Design and develop HDL code for decimal Octal to BCD encoder There will be10 input switches or 8 switches and 4 LEDs in the FPGA kit The input given from switches and it is noted that any one of the switch is active The binary equivalent for the corresponding inpu
13. a noue soe end iirst architecture Behavioral of first is begin process clock variable i integer 0 begin P clock event ond clock m e em it i OOOO OOO then am cq c ANUS eS TEES 255 0100 0 000 cen 15010000 010 0 then qq ee el a lt 0 elsif 1 100000000 then 1 0 end if Ope end process end Behavioral 76 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input in waveform window clk 1 End Time 1000 ns AN clock Wa Output Waveform We get output in simulation waveform a delayed signal Now 1200 ns all clock dla 77 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEM ENTATION FOR BLINKING A LED Description Develop a VHDL Code for delay and verify by simulating it This delay output is connected to LED Delay is adjusted such away LED blinks for every 1 or 2 seconds Flow Chart start Bes TNT TTE TTE TETTE RTT TERRENT ETT TIE 78 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description FPGA LOC P55 P53 Code Listing pro ey IEEE use IEFEE STD LOGIC 1164 ALL se TEER TDT CTOCGIC EUR IL Wel ACL use IEEE STD LOGIC UNSIGNED ALL entity first S ponte elo k e n sede oae LED Sondeo Me en
14. alg lt i Iain Voici cerae Sibel las Cocke ibrary UONE IM 05e UNIS IM VComponents all entity seven seg is porum NU sc ME yen E SOON sel Ole e ro logis t weoien or cowace 9 s A Boc Dh coupe Ce end seven seg architecture Behavioral of seven seg is SIGNAL gx ey oue xdv So oy DIS IBIE OI TEE begin E esd S RT RA EM a Eat X0 I3 AND NOT ZPO STESSO POINTS Xl1 JE O CASH NOME AND NOT TITAND TO X2 lt I3 AND NOT AND TI AND NOT TO X3 I3 AND NOT AND I1 AND I0 X4 lt Ley IND SANZ NOT TI AND NOT TO Xb Io AND T HOTET IAANDETON X6 lt T gt AND STA TITAND NOTTTO lt 7 lt O E TA TEADET Xo lt T gt AND NOT T72 NOT TI AND NOT TO ILS AND NOTT HOTET TESTE EI CIE Z Z Q ml m ON A NN AM A M ON AM AM AMM XI OR X4 ISS OEC OMG Kae XOR xd OR X9 xl OR xc ie OR X5 OR X7 OR X9 X1 OR X2 OR OR X7 X0 OR X1 OR end Behavioral 68 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEM ENTATION OF 7 SEGMENT DECODER BY LUT Description Develop a 7 segment decoder using Look up table Describe the seven segment decoder in VHDL using developed Look up table A seven segment display is connected to the output of the circuit Four switches are connected to the input The 4 bit input is decoded into 7 segment equivalent Flow Chart 69 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual
15. yz 1 and cinz l in waveform window End Time 1000 ns 150 ns A ns d ns i ns al ns 650 ns a ns i ns m ns iul cin AN cout Bo qa B vI3 0 qe sum 3 0 Output Wave form We give input x 1 y 1 and cinz so we get sum 3 waveform window Now 1000 ns t x 3 0 t v 3 0 el cin i sum 3 0 el cout 44 PARtECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 2 2 Subtraction Program for 4 bit subtraction using arithmetic operator It is possible to create a logical circuit using multiple full subtractor to subtract N bit numbers Each full subtractor inputs a Bin which is the Bout of the previous subtractor This kind of subtractor 1s called a ripple carry subtractor since each Borrow bit ripples to the next full subtractor B3 B7 B1 BO Single connection suae between subtractors so if for e g AO BO 0 1 B out B out B out B out then F50 can borrow from F51 via this connection but cannot D3 D2 D1 DO borrow from FS if A1 also happens to be 0 Full Subtractor A combinational circuit which performs the subtraction of three input bits 1s called full subtractor The three input bits include two significant bits and a previous borrow bit 45 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Flow Chart 46 PAntzCF SOLUTIONS Technology Beyond the Dreams
16. 3 2x16 Char LCD Display The 2x16 character LCD interface card with supports both modes 4 bit and 8 bit interface and also facility to adjust contrast through trim pot In 8 bit interface 11 lines needed to create 8 bit interface 8 data bits DO D7 three control lines address bit RS read write bit R W and control signal E The LCD controller is a standard KS0070B or equivalent which is a very well known interface for smaller character based LCDs M LCD MODULE XC3S200 Pins 2x16 LCD Selection DATA LINES ce Make switch SW1 to LCD Net label marking position PWR ON OFF 12 PANTECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 4 7 Segment Display The Spartan 3 FPGASP3 Kit has a four character seven segments LED display controlled by FPGA user I O pins Each digit shares eight common control signals to light individual LED segments Each individual character has a separate anode control input The pin number for each FPGA pin connected to the LED display is shown in below table To light an individual signal drive the individual segment control signal Low along with the associated anode control signal for the individual character m XC3S200 Pins 7 Segment Display m Make high to digit selection Make low to segment CIC Make switch SW1 to 7SEG Ne X label marking position
17. Demultiplexer VHDL implementation of multiplexer VHDL implementation of Demultiplexer VHDL implementation of 7 segment decoder VHDL implementation of 7 segment decoder by LUT VHDL implementation of encoder simulation of VHDL code for delay VHDL implementation for blinking a led simulate a VHDL test bench code for testing a gate VHDL implementation for blinking a array of LED VHDL implementation of a speller with an array of LED VHDL implementation of 7 segment display 32 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR COM BINATIONAL CIRCUIT Sum of Product Description Optimize a 4 variable combinational function SOP or POS describe it in VHDL code and Simulate it Example F 0 5 8 9 12 in sop Truth Table for Sum of Product Simplification A B C D _ __ SumofProduct _ CECH SCEE O C o 0 O 1 ABCD o O0 1 1 ABC a joii joo H0 1 ft fo J LL H E u M Oo Boolean Expression Y A B C D A BC D AB C D AB C D ABC D Y B C D A A C A BD AB D ABD Y B C D A BC D AB C D ABC D 33 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Flow Chart 34 PAnczCF SOLUTIONS Technology Beyond the Dreams SET input A SET input B SET input C SET
18. H gt not s0 Vand nor s land nous 2 9 s 0 anc notr S NEST tomes 229 now s 0 and s Cl anod nort s 2 9 s 0 and s 1 and not s c2 not s 0 and not s 1 and s 2 s 0 and noe s1 and 29 not s 0 and s il anai s 2 5 s 0 sand s 1 and s 2s QOO OO OO CH E ELE C EE E 60 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We put enable as high in all condition and here we give input 010 in selection line according to that selection line we get output End Time 1000 ns iul e E pX s 0 2 il stu al stt i sci aX v 7 Output Waveform We get output in simulation window according to that selection line Now 1000 ns el e ex s 0 2 El iX v 0 7 SEW ey stt el v ey v3 ey via ey ys e vie evt alaj ajl aj ajl aj A 61 Pan t ck SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEM ENTATION OF M ULTIPLEXER Description Describe the code for a multiplexer and implement it in FPGA kit in which switches are connected for select input and for data inputs a LED is connected to the output Flow Chart Read A B SELECT amp ENABLE 62 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description worm TR 8 t DSO su OUTPUT FPGA LOC P26 P27 P28
19. P93 P105 P53 Code Listing library ieee use ieee std_logic_1164 all use wecetstd logic arith all use ieee std logic unsigned all erp Uc cs pore 4 8 6 7 in TDSELOGTC SEG 2 im STD LOGIC vector 1 downto Output 2 OUE STD LOGIC end mux gate architecture behav of mux gate is begin process SEL A BCD begin Gase ET is when QO gt Output when 01 gt Output when 10 gt Output when 11 gt Output when others gt null end case end process end behave 63 PAntzECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams VHDL IM PLEM ENTATION OF DEM ULTIPLEXER Description Switches are connected for select inputs and a data input Eight LEDs are connected to the output of the circuit Flow Chart When A amp B 0 IN zOutO When A z 0 amp B z 1 IN zOutl WhenA z 1 amp B z 0 IN Out2 WhenA 1 amp B 1 IN Out3 io SE 64 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description Code Listing library ieee use ieee std logic 1164 al1l entity demultiplexer is port le 3 in sca Logic s 3 in sco logie vector 0 to 2 5 y 3 out sto logic vector 0 to 7 3 end demultiplexer architecture data of demultiplexer is D nous 0 anci nots lL anci nort s 7 s 0 and not s 1 and not s 2 not s 0 and s 1 and not s 2
20. SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 7 6 128x64 GLCD Graphical LCD The FPGASP3 KIT is the GLCD 14 pins are needed to create 8 bit interface 8 data bits DBO DB7 two chip select line CS1 and CS2 address bit R S read write bit R W and control signal E and Reset RST The GLCD controller is a standard S6B0108 or equivalent which is a very well known interface for Graphical based LCDs Figure below illustrate the GLCD part of the design and which pins are used for the interface The GLCD is powered from the 5V power supply enabled by switch SW1 GLCD XC3S200 LINES 128x64 GLCD Selection LCD DATA LINES AA s cr M ake switch SW1 and SW28 to GLCD label marking position PWR ON OFF 27 PAnteCF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Pin Details of GLCD Symbol VO Type Description Chip selection When C31 L C32 LH select C1 wee C51 2ILC52 2L select C2 LUD dover supply voltage Data input output pin of internal shift register M5 SHE DIOL DIO H H Ouipau Output H l Output Output Input utput E L Output Input Read oi Write RM Description H ata appears at DB 7D and can be read bv the CPL while E H CS1B L CS28 L and C33 H L Display data DB 7 0 can be written zt falling edgz of C when CSID L CSZD L aad C53 IL Enable signal E Description I Acad data ia DD 7 9 app
21. Sound Manager OL School Atlas m LLL Y 4 199 10 56 PM Ce FIGURE 1 92 PANTECE SOLUTIONS Wwww pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams ilinx ISE G PSTYRO FPGASP3 CODE EXA 3a EXA 3a ise Fie Edit view Project Source Process Window Help DAHA LDE BHARX AD 4v VBE wel Fr BAO No project is open Select File Open Project or File New Project No flow available FIGURE 2 Create a New Project Create a new ISE project which will target the FPGA device on the Spartan 3 TYRO PRIM ER board To create a new project 1 Select File gt New Project The New Project Wizard appears refer figure 3 93 PARtECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams Xilinx ISE G PSTYRO FPGASP3 CODE EXA 3a EXA 3a ise mie Edit View Project Source Process Window Help Gt SMAAK AR 4Y XDE Oo wal annt Open Project Open Example Close Project Save Project As O New Ctr N p Open Ctrl 0 Close g Save Ctrl 5 Save As g Save all amp Print Ctrl P B Print Preview Recent Files Recent Projects Exit FIGURE 3 2 New Project wizard window shown in Figure 4 will appear In the Name field enter your project name and enter the location where you want to create the project in the Location field NOTE don t use c drive or desktop In the Top Level Module select HDL and click Next r
22. Teg T E Edge 0 CK CK Edge 10 PS 2 keyboard connector MINI DIN6 2 fi af d n CLK PS2C Connector Pin Purpose l LT Pin 1 KBDAT data Tsy uU HLD Pin 2 not used DATA PS2D LEY n Pins GND Pin4 VCC 45V Pin 5 KBDCLK clock 1 stop bit Pin 6 not used 0 start bit 1ouse connector pinout is identical to PS 2 keyboard Both a PC mouse and keyboard use the two wire PS 2 serial bus to communicate with a host device the Spartan 3 FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start stop and odd parity bit However the data packets are organized differently for a mouse and keyboard Furthermore the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the Keyboard The PS 2 bus timing appears as shown in above figure The clock and data signals are only driven when data transfers occur otherwise they are held in the idle state at logic High The timing defines signal requirements for mouse to host communications and bidirectional keyboard communications The attached keyboard or mouse writes a bit on the data line when the clock signal is High and the host reads the data line when the clock signal is Low 24 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Keyboard The keyboar
23. input D Output Y End www pantechsolutions net L scheme VLSI Lab M anual Code Listing 35 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input a high in waveform window End Time 1000 ns 50 ns 150 ns 250 ns 350 ns 450 ns 550 ns 550 ns 750 ns 850 ns 950 ns ala alb alc a d ly Output waveform Finally we get output in simulation window y high according to that SOP Equation Now 1000 ns dla alb ic aa to LE 36 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR COM BINATIONAL CIRCUIT Product of Sum Description Optimize a 4 variable combinational function POS describe it in VHDL code and Simulate it Example F 0 5 8 9 12 in POS Truth Table for Product of Sum Simplification A IB IC ID Y Product of Sum LM oO A B C D o A B C D o UN o uj o o A B C D m A B C D l I 0 A B C D 0 A B C D l d p I 0 A B 4C D 0 A B C D i 1 o 1 0 A BSCHD a I JO 0 A B C D 1 I 1 I 0 A B C D_ EN Y A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D 37 PANTECE SOLUTIONS www
24. logic unsigned all USE ieee numeric stol Anm ENTITY code_vhd IS END code_vhd ARCHITECTURE behavior OF code_vhd IS Component Declaration for the Unit Under Test UUT COMPONENT cd PORT a IN st Loge D 23 IN ta Logie e IUD Sus obe Egi END COMPONENT INPUTS SIGNAL a Suc Ogg cus M SIGNAL b srel logre s OY QUT PUTS SMENA CU ES OOE BEGIN Instantiate the Unit Under Test UUT uut cd PORT MAP a s a b gt er DL C tb PROCESS BEGIN a a D Wane OO mes tror globa lllresct to en ims wait for 100 ns a cte loss a0 Place stimulus here Wate tor 100 ns will wait forever END PROCESS END 1 82 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Output Waveform We get output in simulation window c 1 according to that gate operation Now 1000 ns ella ab alc 83 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEM ENTATION FOR BLINKING A ARRAY OF LEDS Description Design and develop a VHDL Code for 4 bit binary up counter Four LEDs are connected at the output of the counter The counter should up for every one seconds Flow Chart Enable Clock Counter Value Increase from 0 to 15 84 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams PIN Descript
25. pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Flow Chart 38 PAnczCF SOLUTIONS Technology Beyond the Dreams SET input A SET input B SET input C SET input D Output Y End www pantechsolutions net L scheme VLSI Lab M anual Code Listing 39 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input a high in waveform window End Time 1000 ns 50 ns 150 ns 250 ns 350 ns 450 ns 550 ns 650 ns 750 ns 850 ns 950 ns ala Output waveform Finally we get output in simulation window y high according to that POS Equation Now 1000 ns dla alb ic ond oly 40 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams SIMULATION OF VHDL CODE FOR ARITHMETIC CIRCUITS Description Design and Develop the circuit for the following arithmetic function in VHDL Codes and simulate 1t Addition Subtraction Multiplication 4 x 4 bits 2 1 Addition Program for 4 bit addition using 4 bit Ripple adder It is possible to create a logical circuit using multiple full adders to add N bit numbers Each full adder inputs a Cin which is the Cou of the previous adder This kind of adder 1s called a ripple carry adder since each carry bit ripples to the next full adder Initial carry in Sum Final Carry out 41 PANTECE SOLUT
26. pixel location The Spartan 3 Evaluation Kit uses three bits per pixel producing one of the eight possible colors shown in above table The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel The VGA controller generates the HS horizontal sync and VS vertical sync timings signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with practical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency 23 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 7 5 PS 2 Interface The FPGASP3 Kit includes a PS 2 port and the standard 6 pin mini DIN connector labeled U11 on the board User can connect PS 2 Devices like keyboard mouse to the FPGASP3 KIT PS 2 s DATA P8 and CLK P10 lines connected to SPARTAN3 FPGA I O Lines 6PIN MINI PS 2 PARTAN PS 2 PORT SELECT Connector FPGA Lines n
27. the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass The size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated determine the display resolution Modern VGA displays support multiple display resolutions and the VGA controller indicates the resolution by producing timing signals to control the raster patterns The controller produces TTL level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the 22 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams pixel D 538 B4D pixels are displayed each time the beam traverses the screen VGA Display Retrace No Current information through the horizontal defection cail pixel 478 0 pixel 478 538 is displayed during this time Stable current ramp Information is displayed during this time Total horizontal time Horizontal display time retrace time sme net porch back porch lp 4 dA E Horizontal sync signa L front porzh sets the retrace frequency correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each
28. 00 ns E X a 3 0 E X b 3 0 ell hin Fl X difiT3 0 AN dita AN diti ay ditm AN aito ell bout 48 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 2 3 Multiplication Program for simple 4x4 multiplications using arithmetic operator Consider the multiplication of two numbers as 4 x4 a b where a and b are 4 bit numbers and the output of multiplication is taken in y as 8 bit number Flow Chart START SET input A SET input B Verify output Y 49 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity codef is Port a in STD LOGIC VECTOR 3 downto 0 b in STD LOGIC VECTOR 3 downto 0 y out STD LOGIC VECTOR 7 downto 0 end codef architecture Behavioral of codef is begin y a b end Behavioral 50 PAntzeCF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give inputa 2 amp b 2 End Time 1000 ns 150 ns 250 ns 350 ns 450 ns 550 ns 650 ns BA a 3 0 Output Waveform We give input a amp b so we get output yz 4 according to that multiplication operation Now 1000 ns e a 3 0 ex 3 0 ex v 7 0 51 PANTECr SOLUTIONS ww
29. 1 i gt Project Navigator or double click BEESESEE desktop icon refer Figure 1 A Window shown in Figure 2 will appear G g My Documents 101MSDCF i Set Program Access and Defaults em Xilinx ISE 8 1i a Accessories Wb Windows Catalog ga DivX Documentation E47 Windows Update eal Mero 7 Essentials lese Project Navigator Ga a Winzip ga SuperCopier2 7 Readme My Computer P EZ Ea Packs Software Update Center ModelSim SE 5 6 Evaluati d Accessories Ee Modem valuation X Tek 42 a Games Se 5 Keil uVision3 My Network P_VLS EA Realtek Places cm avast Antivirus ma Startup mA i za K Lite Codec Pack Internet Explorer TE ina a recycle B HOTOS FDD eal Total Video Converter Randdal HAEA aes amp Outlook Express Acrobat com p Remote Assistance A Act T Adobe Reader 9 windows Media Player Je 8 Windows Messenger computer j a Windows Movie Maker T Internet Microsoft Office Tally 9 e hoy E mail Winamp gt WinZip tReet c 50 FREE MP3s from eMusic i T V Adobe ImageReady C5 E yis ni Adobe Photoshop CS r3 VLC media player skir MA E5 CyberLink DVD Solution EISE iem Java 2 Runtime Environment i y Java Web Start z H o Jd LG ODD Auto Firmware Update l Microsoft Office Powe c 2007 L Mero Turbo C 4 5 CyberLink DVD Suite MATLAB 6 5 All Programs p QuickTime P WordWeb ig Log OFF Tul r y is 2 Windows P PR RRRBRHO Realtek
30. 1s one possible circuit diagram for the demultiplexer In this program a 1 x 8 de multiplexer have two 1 bit inputs a 3 bit select line and a 8 bit output Additional control signals may be added such as enable The output of the multiplexers depends on the level of the select line 57 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams m 0 1 5 L am pem ID TEE 00e 91 Qs 535450 Sa E O4 I 5555 Og S5S4S9 Og 858459 Og I 5554Sg eO I S555 DATA input OUTPUTS SELECT code 95 94 Sp xd Mote Iis the data input A cOo l2o00 Oooooococo O 000000 cOOc ooooo OOoO ooo00 oooo0 ooo OOOooo0 o0o cOoooooc o ooocceccs 58 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams Flow Chart START 1 L iz RRR RR RRR ORR RR A al When A amp B 0 IN zOutO When A z 0 amp B z 1 IN zOutl WhenA z 1l amp B z 0 IN Out2 WhenA z l amp Bz l IN Out3 59 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams Code Listing library ieee use ieee std logic 1164 a11 entity demultiplexer is ona e an Suc ikecaves SES teste moie etr on ESO OF Ou Stes loge Vector ton UE end demultiplexer architecture data of demultiplexer is O D Q
31. 200 v Package TQ144 selected Y Speed Grade 4 v Top Level Module Type HDL v Synthesis Tool XST VHDL Verilog v Simulator ISE Simulator VHDL Verilog Then click Next refer Figure 6 7 8 and then Finish refer Figure 9 96 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams File Edit View Project Source Process Window Help DAHA OB Geo StAX ab 4 XDA wal rl BAO Sources No project is open Select File gt Open Project or File New Project New Project Wizard Device Properties Select the Device and Design Flow for the Project 7 77 7 il unie n LSU Pelea 00 0 LLLLLLLLLLLLE LEES MEE n Bekge fa 0 NN TelemSemelpe o OOS T SmbesTe DSTMHNPkg 7 a CEN EI Samay O feles O D por D Transcript FIGURE 6 97 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams File Edit View Project Source Process Window Help DAHA 5B gau nBDgPHOZ SBSEGESAXISYXSXIStAB Ae YBBR WM jegmcoo Sources No project is open Select File gt Open Project or File New Project New Project Wizard Create New Source Create a New Source Saee te No flow available Crea
32. 5 by default JP5 pin 1 amp 2 shorted 6 9 Buzzer Interface 5V continuous buzzer connected through FPGA s I O pins P5 to enable buzzer place jumper JP7 at E label mark position Buzzer Module Spartan3 FPGA pins Buzzer P5 make port pins to high buzzer will activated M e oes BEEN JP7 17 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 10 Traffic Light Controller Traffic light controller card consist of 12 Nos point led arranged by 4Lanes Each lane has Go Green Listen Yellow and Stop Red LED is being placed Each LED has provided for current limiting resistor to limit the current flows to the LEDs a XC3S200 pins Traffic Light Controller Direction copy MN D21 Listen 330E a mL RE SOUTH D25 Go ee Make high to LED On D24 Listen M ake low to LED Off be am praises 18 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 7 Peripherals Section Il 7 1 RS 232 Communication USART USART stands for Universal Synchronous Asynchronous Receiver Transmitter FPGASP3 Kit provides an RS232 port that can be driven by the Spartan 3 FPGA A subset of the RS232 signals is used on the Spartan 3 kit to implement this interface RxD and TxD signals e RS 232 communication enables point to point data transfer It is commonly used in data acquisition applications for the tra
33. CE or JTAG File Contigur Rerun cL Rerun All PEE Stop Open Without Updating E dara EN Processes E Properties FIGURE 28 IMPACT Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File 3 Prepare a System ACE File C3 Prepare a Boundary 5 can File C3 Configure devices using Slave Serial made e Inthe Welcome dialog box select Configure devices using Boundary Scan JTAG e Verify that Automatically connect to a cable and identify Boundary Scan chain is selected e Click Finish 114 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams e Ifyou get a message saying that there are two devices found click OK to continue e The devices connected to the JTAG chain on the board will be detected and displayed in the IMPACT window e The Assign New Configuration File dialog box appears To assign a configuration file to the xc3s200 device in the JTAG chain select the addition bit file and click Open IMPACT C tutorial tutorial ipf Boundary Scan E Fie Edit View Operations Options Output Debug Window Help PH xxxi p Hi FBO ww x Sel Boundary Scan Su SlaveSerial PA SelecthAP alb esktop Configur SystemACE m xc3z200 xef 2s IMPACT Modes file file 7
34. IONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Full Adder The full adder circuit adds three one bit binary numbers Cin A B and outputs two one bit binary numbers a sum S and a carry Cout Cout Flow Chart 42 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams ibrary IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity adder is Port x in STD LOGIC VECTOR 3 downto 0 y in STD LOGIC VECTOR 3 downto 0 cin in STD LOGIC sum out STD LOGIC VECTOR 3 downto 0 cout out STD LOGIC end adder architecture Behavioral of adder is component fulladder port x y cin in std logic sum cout out std logic end component signal c std logic vector 2 downto 0 begin in sum 0 c 0 0 sum 1 c 1 1 sum 2 c 2 2 sum 3 cout a2 fulladder port map a3 fulladder port map O O A OC end Behavioral library ieee use ieee std logic 1164 all entity fulladder is port x y cin in std logic sum cout out std logic end fulladder architecture comb of fulladder is begin sum lt x xor y xor cin cout lt x and y or cin and x xor y end comb b 43 PAnCtECF SOLUTIONS www pantechsolutions net Technology Beyond the Dreams L scheme VLSI Lab M anual Input Wave form We give input xz 1
35. JL 43 44 JL4D jf 54 5B JL sp CapsLock 5f z d 3n bs 4c 4 5j ES E EX 12 JL 22 Jo 22 J 2 H H a EH A EX Ctrl Ed a Alt Ct 14 E IDEEN E011 E014 The host can also send commands and data to the keyboard Below figure provides a short list of some often used 25 PAnteCF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Commands Turn on off Num Lock Caps Lock and Scroll Lock LEDs Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate Resend Upon receiving a resend command the keyboard resends the last scan code sent OR Reset Resets the keyboard The keyboard sends commands or data to the host only when both the data and clock lines are High the Idle state Because the host is the bus master the keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a O start bit followed by eight bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit Echo Upon receiving an echo command the keyboard replies with the same scan code EE ED EF F3 FE FF 26 PAntecCF
36. PSPRIM ER FPGASP3 SPARTAN3 Development Kit Hardware amp Software User Manual 1 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Contents MEME MIE NOY E 3 NES O 3 1 2 Technical or Customer SUpport eunt mese euntuctbusideturtuet ue iater besbesergted cedes tuse is ebd etes PRU IE 3 2 Jeytombonente and Feature Scenen t bbb dad xis U mos C DO dmn NDS 4 2 1 General Block Diagram nennen nnne nennen nnne nennen nnne nnn 5 2 JUMPE Se SWIECH Detail sE dera acu EE EE 6 4 COTA ECHO Details m 7 5228 7 7 070 ee E E EE cites 8 b Dnooata PF SVAN IG sueta aD MERC RII DUM OON UU 9 SE Eo eiiis Pie e 10 6 2 Digital INOUtS cecsecscscssssssssseserseresrsersesesersereseesensereseesnesansensnesansunssaesersenesansensseesarsenesansensesesansenssansensses 11 SRL CHV CS AA staid EAE E ani tetracaine EE A N 12 6 4 7 Segment Display V 13 6 5 4x4 M atrix keypad and Push BUEEOTPLsasasasasirmvotono duo bIvivH visito ee bd TH PEDE Feo odE 14 SUSE MOOT c X 15 MESE ol 16 b 9 o Relay Tete Buses tapped uiv dS ditt D bat ctv dE O OO 17 6 9 Buzzer Interface nennen nnne nennen nennen nennt innen n a na 8n 17 6 10 5 Traffic EBORE CONT OUST savait tuotatuntisi Redes
37. X voltage input supplies power to Digital Clock Managers DCM s within the FPGA and supplies some of the I O structures In specific all of the FPGA s dedicated configuration pins such as DONE PROG B CCLK and the FPGA s JTAG pins are powered by VCCAUX The FPGA configuration interface on the board is powered by 3 3V Consequently the 2 5V supply has a current shunt resistor to prevent reverse current Finally a 1 2V regulator supplies power to the FPGA s VCCINT voltage inputs which power the FPGA s core logic The board uses four discrete regulators to generate the necessary voltages 8 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 On board Peripherals The Development Kit comes with many interfacing options e 8Nos Slide Switches for digital inputs e 8nos of Point LEDs for Digital outputs e 2x16 Character LCD interface e 4Nos 7 segment LED CA display e 2Nos of 5V SPDT Relay with termination e 4x4 Matrix Keypad interface e 4 Way Traffic Light controller Module e Stepper motor Driver interface e DCMotor interface controlled by PWM e Buzzer Interface e UART for serial port communication through PC e GLCD I2C EEPROM RTC 1 Wire Temp Sensor Optional e JTAG Programmer e Clock Source e 3 bit 8 Color VGA Interface e PS 2 Keyboard interface 9 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 1 Light Emitt
38. ap cor muxos MUX Port Mae VE ae muxo mux Pori map z4 ma T mM Pore MAE zo end Behavioral 55 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input a high in waveform window End Time 1000 ns cQjojojojoojocjoajoalojoojzdoc zo Output Waveform We get output in simulation window y high according to that multiplexer operation End Time 1000 ns 5S ns 150 ns 250 ns 350 ns 150 ns 550 ns 550 ns TS ns 850 ns 950 ns ELE LEE br b rrr b rrr barra Era dr ba rar bara dd iua iub iu iul d Ule uf MP ilh iu co iul c1 ul c2 Mz D A c c A A c c3 c c3 56 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR DEM ULTIPLEXER Description Design and develop an 8 output demultiplexer using truth table Demultiplexer The demultiplexer is the inverse of the multiplexer in that it takes a single data input and n address inputs It has 2 outputs The address input determine which data output is going to have the same value as the data input The other data outputs will have the value 0 Here is an abbreviated truth table for the demultiplexer We could have given the full table since it has only 16 rows but we will use the same convention as for the multiplexer where we abbreviated the values of the data inputs Here
39. d Lirsey architecture Behavioral of first as begin process Clock variable i integer 0 begin it ekock event anil Clock TT Ehen ir 4 lt S0000000 ehen gu mE gD lt C Slee cte SOOOOOOO aac cb lt HOOOMOOOO Ehen See ell LIED ik elsif 1 T00000000 then 1 0 end If endi end process end Behavioral 79 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATE A VHDL TEST BENCH CODE FOR TESTING A GATE Description Develop a VHDL test bench code for testing any one of the simple gate Simulate the test bench code in the HDL software Flow Chart START cc a d Amn Anaa a A m A nn AA A AEA RAe SET input clock Delay for 1sec m otete naa a aaa aaa 80 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing AND gate program Mor tay BIN EN use LEEB STDOCDOGIC LIO4 ADLIL Use ER euet o SIND TEONGTE C eges TE TE Ist ALLE Visits TEER e m IID COGIC INS IGN ACL entity gate is Port a in SID LOGIC b in SID LOGIC Ce Oui To IDT LOGI V end gate architecture Behavioral of gate is begin C lt a and bD end Behavioral 81 PAntzECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams Testbench code ON LIBRARY ieee USE ieee std logic 1164 ALL USE ieee std
40. d uses open collector drivers so that either the keyboard or the host can drive the two wire bus If the host never sends data to the keyboard then the host can use simple input pins A ps 2 style keyboard uses scan codes to communicate key press data nearly all keyboards in use today are ps 2 style Each key has a single unique scan code that is sent whenever the corresponding key is pressed The scan codes for most keys appear in below figure If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key is released the keyboard sends an fO key up code followed by the scan code of the released key the keyboard sends the same scan code regardless if a key has different shift and non shift characters and regardless whether the shift key is pressed or not The host determines which character is intended Some keys called extended keys send an e0 ahead of the scan code and furthermore they might send more than one scan code When an extended key is released an e0 f0 key up code is sent followed by the scan code ESC Fi F2 F3 F4 FS Fe F7 FB F Fto F11 76 05 06 J 04 J oc o3 o8 83 c 01 02 78 07 If 1 ff2e 3s 4 sall 6 7 amp e 9 If 0 zs 4 og 16 J 1E 26 25 a amp 36 J 3p 3 amp 46 45 4 55 66 TAB O WI E if R Y uj t yo lee toe I M me oD 15 J in 24 J 2D 2c JL 35 JL 3c
41. e4 state5 state6 state7 states state 9 Signal next state ps state state0 begin Sq ie process clk next state variable i integer 0 begin if clk event and clik Ie then if i lt 100000000 then MEC CTI elsif 1 gt 100000000 then i 0 Nee SEO oon end rr if next state state0 then y Z poU ps lt statel elsif next state statel then qox xe ig One ps lt state2 elsif next state State2 then y lt ai ps lt state3 elsif next state State3 then y lt eo c 89 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams ps lt state4 elsif next state state4 y lt xX 99 ps lt stated elsif next state stated Ww lt AU ps lt state6 elsif next_state state6 wy lt XOU UPS ps lt state7 elsif next state state7 Ww lt XOU We ps lt state8 elsif next state state8 wow XU Eg ps lt state9 elsif next state state9 vy lt Kopu ps lt state0 end if eng om end process end beav 90 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Getting Started with Xilinx ISE Tutorial 91 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 9 Getting Started with Xilinx ISE After installing Xilinx ISE 8 1 i software go to Start menu Start Programs gt Xilinx ISE 8
42. ears while C Tigh L Display data DB 7 0 s latclizd al alline edge vl E Data bus 0 7 Bi directional cata bus Reset signal Whenu RSTB L 1 ON OFF register becomes set by display ott d splay start line register hecomes set by 0 7 ddress C set display from line 0 3 After releasing reser this condition can he changed orly hy insirmetior VEE is cunnecied by Tie same vollage 19 JA Backkghtanode 20 K Backkhghtcatbode 28 PAnteCF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 7 7 Serial EEPROM The AT24C01A 02 04 08 16 provides 1024 2048 4096 8192 16384 bits of serial electrically erasable and programmable read only memory EEPROM organized as 128 256 512 1024 2048 words of 8 bits each The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential Features of AT24Cxx e Internally Organized 128 x 8 1K 256 x 8 2K 512 x 8 4K e 2 wire Serial Interface e Bi directional Data Transfer Protocol e 100 kHz 1 8V 2 5V 2 7V and 400 kHz 5V Compatibility e Write Protect Pin for Hardware Data Protection e 8 byte Page 1K 2K 16 byte Page 4K 8K 16K Write Modes Data Retention 100 Years aM I2C EEPROM XC35200 pins Serial EEPROM SPARTAN3 29 PAnteCF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technolo
43. efer Figure 5 94 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams File Edit View Project Source Process Window Help DAHA GDE BHXHHHX AB sv lt BR mel F BAO Sources x No project is open Select File gt Open Project or File gt New Project New Project Wizard Create New Project Enter a Name and Location for the Project Project Name Project Location Eme ie No flow available Select the Type of Top Level Source for the Project Top Level Source Type HDL Transcript FIGURE 4 95 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams Xilinx ISE G PSTYRO FPGASPS CODE EXA 3a EXA 3a ise File Edit View Project Source Process Window Help DAHA GDF A BYXHAAK AD 4M XDA weal Fi SEO x Sources No project is open File gt Open Project or File New Project New Project Wizard Create New Project Processes x No flow available Enter a Name and Location for the Project ADDITION E EXEPERMIENT1 A4DDITION Project Name Project Location Select the Type of Top Level Source for the Project Top Level Source Type CAPS sng nets r E Lus dia risen Figure 5 3 A window given in Figure 6 will appear Fill in the properties in the table as shown below v Product Category All v Family Spartan3 v Device XC3S
44. gy Beyond the Dreams 7 8 Real Time Clock DS1307 The Real Time Clock RTC is a set of counters for measuring time when system power is on and optionally when it is off It uses little power in Power down mode On the LPC2148 the RTC can be clocked by a separate 32 768 KHz oscillator or by a programmable prescale divider based on the VPB clock Also the RTC is powered by its own power supply pin VBAT which can be connected to a battery or to the same 3 3 V supply used by the rest of the device Features e Measures the passage of time to maintain a calendar and clock e Ultra Low Power design to support battery powered systems e Provides Seconds Minutes Hours Day of Month Month Year Day of Week Day of Year e Dedicated 32 kHz oscillator or programmable pre scalar from VPB clock e Dedicated power supply pin can be connected to a battery or to the main 3 3 V i I2C RTC XC3S200 Real Time Clock o9 Sa DS1307 at an 30 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams VLSI LAB Examples L Scheme 31 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Contents 8 VLSI Lab Experiments l 2 10 11 12 13 14 15 simulation of VHDL code for combinational circuit simulation of VHDL code for arithmetic circuits simulation of VHDL code for multiplexer simulation of VHDL code for
45. hnology Beyond the Dreams Code Listing 2 1 multiplexer program TEE TERE D use IEEE STD LOGIC 1164 ALL ise TEER gt IPT LOGICVARTIOALL Use TERE SIND LOGIC SUIS TONED ACE cU mi eie shi ell Ikevvikiere library declara ion Wie In Cantat ina Z GN la a e a Egil aade a cia AMNES Use UNIS IM Commons s aLi entity m x is POE Noc See ol DE LOGE Nn LOG le sel in SID LOGIC ZEN ES SPT TOCIL end mux architecture Behavioral of mux as begin process x y sel begin if sel 0 then Z elsif sel 1 then Z y end 1f end process 54 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 8 1 mux port map program liprary IEEE use IEEE SID LOGIC 1164 A ALL USC TEER IDEF COGIC ARITH ALE lise IET os TODE JOG IE C TUN TONED ACE Uneme Be Mew following library declaration 1i Instan rating a a la n aee DIOE IE QUIE oode e 05 UE S use UNISIM VComponents all entity multiplexer is Benian i ay One Cy Cyl 7 Oy nas aa LD SLOG Ee T CO lye I bs ese oe Ibo cule Z OUL SD o a gt end multiplexer architecture Behavioral of multiplexer is Comoe aie lex Porr Ken Edl dee ake yon E RO Gre sel inm std Logic z oUt o Ed logie i end component Sup en zd Sd Om Eco ncm c begin Sugmce iuo uos MEE cmo UN begin MUS IS muU Port map a mu x2 m x port map eg MUS MB Porte map er mux4 mux port m
46. ick Manage Configuration Project IMPACT refer Figure 25 11 Download Design to the Spartan 3 TYRO PRIM ER Kits This is the last step in the design verification process e Connect the 9V DC power cable to the power input on the TYRO Primer Kits J1 e Connect the download cable between the PC and development board J4 e Check Synthesis Implementation from the drop down list in the Sources window refer figure 26 S Ounces Sources for Sunthesis Implementatian ADD Synthesis Implementation rier Ba xc3s Behavioral Simulation i Post F oute simulation ENS Sources pay Snapshots f Libraries Figure 26 Select addition in the Sources window refer figure 27 C Ounces Sources for Sunthesis Implementatian hil ADDITION E E xc3s200 4tq1 44 a addition Behavioral code vh di ENS Sources ge Snapshots f Libraries Figure 27 In the Processes window click the sign to expand the Generate Programming File processes e Double click the Configure Device IMPACT process Refer FIGURE 28 113 PAntzECF SOLUTIONS WWw pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams Processes 71 Add Existing Source 7 Create Mew Source X2 Wiew Design Summary EE Design Utilities ES uA User Constraints Pg Synthesize ST J Implement Design Pg Generate Programming File E Pragramming File Generation Report Generate PAOM A
47. ide switches Traffic light LCD 7 Seg UART VGA and PS 2 with ease to create a stand alone versatile test platform 1 1 Packages g e Spartan3 Development Kit XC3S200 att D e Serial Port Cable we JTAG Programming Cable thigh e Printed User Manual e CDcontains o Software Programmers ISE o Example Programs o User Manual 1 2 Technical or Customer Support E mail questions to support pantechsolutions net Send questions by mail to Pantech Solutions Pvt Ltd 151 34 M ambalam High Road Sri Ranga Building T Nagar Chennai 600 017 Tamilnadu India Phone 191 44 4260 6470 Fax 491 44 4260 6350 Website www pantechsolutions net 3 PARtECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 2 Key Components and Features On Chip Features e 200 000 gate Xilinx Spartan 3 FPGA in a 144 TQFP XC3S200 4TQG144C 4 320 logic cell equivalents Twelve 18K bit block RAM s 216K bits Twelve 18x18 hardware multipliers Four Digital Clock Managers DCM s Up to 97 user defined O signals On Board Features e 10 Nos Slide Switches for digital inputs e 10nos of Point LEDs for Digital outputs e 2 Nos of Push Button e 2x16 Character LCD interface e 4Nos 7 segment LED CA display e 2 Nos of 5V SPDT Relay with termination e 4x4 Matrix Keypad interface e 4 Way Traffic Light controller Module e Stepper motor Driver interface e DCMotor interface con
48. in Files Transcript Ln 28 Col 45 CAPS NUM SCRL VHDL Rp uni E silinx gt 1r Figure 17 108 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Xilinx ISE EXEXEPERMIENT T ADDITION ADDITION ise code vhd f File Edit View Project Source Process Window Help Bx DRAA DBEA Rr AB SY XBR OO MAL Ti DP EE z5 7 AAAKNHHM Ba Sd 00 n 7 library IEEE p Sources for Synthesis Impler 6 use IEEE STD LOGIC 1164 ALL S ADDITION 7 use IEEE STD LOGIC ARITH ALL S 5 xc3s200 4tql 44 use IEEE STD LOGIC UNSIGNED ALL ides addition Behavior 4 5 entity addition is Lin spoLe i gt 12 a in std logic vector 3 downto 0 ist input value EY Sources ej Snar lt gt 13 b Soim Men SORE MESURE C downto 0 Zznd input value 14 output out std logic vector 4 downto 0 output result 15 is P 16 end addition rTOCesses 1 Add Existing Source 18 architecture Behavioral of addition is 3 Create New Source 19 signal declarations X View Design Summary 20 signal store std logic vector 4 downto 0 y Design Utilities 21 begin y User Constraints 22 4 BIT ADDITION MODULE Es NETS ae 22 process a b ab 0 0 tm JE Ge Rerun E at Rerun All tore lt conv std logic vector conv integer a conv_integer b 5 addition ay S
49. ing Diodes e Light Emitting Diodes LEDs are the most commonly used components usually for displaying pin s digital states e The FPGASP3 KIT has 8 nos of Point LEDs connected with port pins details tabulated below the cathode of each LED connects to ground via a 3300 resistor To light an individual LED drive the associated FPGA control signal to High BEI re erw e q 555 L3 5 LED D29 10 PANTECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 2 Digital Inputs e This is another simple interface of 8 Nos of slide switch mainly used to give an input to the port lines and for some control applications also e The FPGASP3 KIT slide switches SW20 SW 27 directly connected with FPGA 1 0 lines details tabulated below user can give logical inputs high through slide switches The switches are connected to 43 3V in order to detect a switch state by default lines are pull downed through resistors The switches typically exhibit about 2 ms of mechanical bounce and there is no active de bouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board A 10KO series resistor provides nominal input protection seeepemese 7 sek SW24 SW25 M ake Switch Close High M ake Switch Open Low 11 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6
50. ion Q 3 Q 2 Q 1 Q 0 Code Listing Ero csv CH EER Use LEE SID_ LOGIC 1164 ALL USSTEEL IDE EOS TE redes TE AE Isis ALL ipte CET ug 4S dE IDA OIG TEC TOURS GNI ALL entity first 15 Porte ucl ook Sin sta Logie IS ep cT gp ere ote Ik OYG Hs e q ou SENI MO cts oe lov e end first architecture Behavioral of first is signal tmp td logic v Coro downto O 0000 begin process clock rst variable i integer 0 begin ae est 1 then Tenino eae elsif clock event and clock ied lt a OOOO dau ie UE elsif 1 50000001 then 1 0 tmp Silo E GE process tmp Behavioral 85 PANTECE SOLUTIONS www pantechsolutions net Technology Beyond the Dreams L scheme VLSI Lab M anual VHDL IM PLEM ENTATION OF A SPELLER WITH AN ARRAY OF LEDS Description Design and develop VHDL Code for a 5 bit Johnson ring counter 4 bit The LEDs are connected at the output of the counter The speller should work for every one seconds Flow Chart Enable Clock Value incerse In ring order PIN Description 86 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Johnson Ring Counter CODE Listing Delete ate IERE use IEEE STD LOGIC 1164 ALL iS 4 SND OG INC ug 8 lel 6 ACL obses c CES BR ero TED IOI TIC UNS IG NaI c TEES 2 entity first 1s EPOCE E cde E e EO Reset in std logic output out std logic vec
51. ject Source Process Window Help X DAHA CAFFRA ETATE AR 4 ABE OO ARL O rl ssrt APEE E2I2L2AAAANAN DuS Sources 5 library IEEE E Sources for Synthesis Impler 6 use IEEE STD LOGIC 1164 ALL ADDITION 7 use IEEE STD LOGIC ARITH ALL E E3 xc3s200 4tql 44 use IEEE STD LOGIC UNSIGNED ALL hake addition Behavior 10 entity addition is TI DOE 4 REL gt 12 a in std logic vector 3 downto 0 ist input value ER Sources ej Snap gt 13 b in std logic vector 3 downto 0 2nd input value 14 output out std logic vector 4 downto 0 output result 15 l P 7 16 end addition TOCesses i Add Existing Source 18 architecture Behavioral of addition is 7 Create New Source 19 signal declarations X View Design Summary 20 signal store std logic vector 4 downto 0 Design Utilities 21 begin User Constraints 22 4 BIT ADDITION MODULE Pa Create Timing Con 23 p INS Assign Package P 2 begin veia eda 26 store lt conv std logic vector conv integer a conv integer b 5 addition i EX Gondate T 27 output 3 downto 0 lt store 3 downto 0 sum g Synthesize XST 28 output 4 lt store 4 carry FQ Implement Design 29 fj Generate Programming 3 31 end process us 33 end Behavioral 34 ac P 4 gt ap Processes 3 hol h code Design Summary G Started Launching Design Summary v
52. nology Beyond the Dreams an example of how the FPGA might drive VGA monitor in 640 by 480 modes For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics Websites Video Electronics Standards Association http www vesa org VGA Timing Information http www epanorama net documents pc vga_timing html Signal Timing for a 60Hz 640x480 VGA Display CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permittivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCD displays have evolved to use the same signal timings as CRT displays Consequently the following discussion pertains to both CRTs and LCD displays Within a CRT display current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As shown in below figure information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of
53. nsfer of data between the microcontroller FPGA and a PC e The voltage levels of a FPGA and PC are not directly compatible with those of RS 232 a level transition buffer such as MAX3232 be used UART SPARTANS Serial Port Section SPARTAN3 The FPGASP3 Kit has a dedicated 50 M Hz series clock oscillator source and an optional socket for another clock oscillator source SPARTAN3 Crystal Oscillator FPGA Lines b o a 7 2 Clock Source 19 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 7 3 JTAG Programmer The FPGASP3 Kit includes a JTAG programming and debugging chain Pantech JTAG3 low cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header DB 25 parallel port connector to 6 pin female header connector The JTAG cable connect directly to the parallel port of a PC and to a standard 6 pin JTAG programming header in the kit can program a devices that have a JTAG voltage of 1 8V or greater 6 Pin SPARTAN3 UM JTAG Signals EN sinu nes JTAG Cable III P111 NAH 9 79 19 5 RR ow p ES re The Pantech low cost parallel port to JTAG cable fits directly over the header stake pins as shown in above figure When properly fitted the cable is perpendicular to the board Make sure that the signals at the end of the J TAG cable align with the labels listed on the board The other end of the Pantech cable connects to the PC s parallel p
54. ort The Pantech cable is directly compatible with the Xilinx iM PACT software 20 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 7 4 VGA Interface The FPGASP3 Kit includes a VGA display port through DB15 connector Connect this port directly to most PC monitors or flat panel LCD displays using a standard monitor cable As shown in table the Spartan 3 FPGA controls five VGA signals RED R its 1ST pin in connector GREEN C its 2nd pin BLUE B its 3rd pin Horizontal Sync HS 13th pin and Vertical Sync VS its 14th pin all available on the VGA connector PARTAN DB 15 VGA Signals S 3 VGA port bows from Wire Side Vertical Sync VS PE Horizontal Sync HS J PF Each color line has a series resistor to provide 3 bit color with one bit each for Red Green and Blue The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA specified OV to 0 7V range The HS and VS signals are TTL level Drive the R G and B signals High or Low to generate the eight possible colors shown in below table ee oee w A E E LIII LE E E L1 T E 1 E E 1 E L VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as 21 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Tech
55. ource ca Design Utilities Figure 11 102 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams File Edit View Project Source Process Window Help DAHA SCHR RFARTARHX AD 4Y XBR hal BOD Sour x Synthesis Impler v ADDITION 5 xc3s200 4tql 44 New Source Wizard Select Source Type Add Existing Source E 7 Create New Source Design Utilities 1 IP Coregen amp Architecture Wizard Po Location E EXEPERMIENT1 ADDITION Ma VHDL Test Bench v Add to project Transcript 103 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams File Edit View Project Source Process Window Help DARHA SR RFE GLATAN 4v XBA OO heal F BAO Sources x Synthesis Impler 7 f JADDITION Cd xc3s200 4tql 44 New Source Wizard Select Source Type IP Coregen amp Architecture Wizard be E Add Existing Source te 7 Create New Source 3 Test Bench WaveForm y Design Utilities EP iis Docaneri v Verilog Module At Verilog Test Fixture File name Location E EXEPERMIENT1 ADDITION y VHDL Test Bench v Add to project Transcript 104 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams File Edit View Project Source Process Window Help DAAA DEZALA AD aY X88 MeL
56. p 2 shorted 15 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 7 DC Motor 5V DC Motor speed has controlled through PWM signal M otor can run both clockwise counter clockwise M otor speed controlled by varying ENA duty cycle signal through program aM DC Motor 5V XC3S200 Lines DC Motor PWR Select OFF 1 Q Make switch SW1 to SM RL label Een Sur marking position PWR ON OFF For DC Motor designer get power from on board internal or external supply through jumper JP6 by default JP6 pin 1 amp 2 shorted 16 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 6 8 Relay Interface ULN2803 is used as a driver for port I O lines drivers output connected to relay modules Connector provided for external power supply if needed Relay Module Spartan3 FPGA pins Realy1 P59 and Relay2 P60 for relay module make port pins to high relay will activated aM RELAY SPDT XC35200 pins RELAY Power Select 5V E Relay 1 P59 4 1 8 On in PWR ON OFF Relay 2 JP5 6 6 Internal 5V Stepper Motor sis Note Relay selection make switch SW1 to SM RL label marking position r For Motor relay designer get power from on board internal or external supply through jumper JP
57. surget rrt dU dO D de fiaR Vur var b vii tip Rr URL Dri Rr Rua Sor Ctm tui 18 DSP CUI als Se CUO ll T 19 Fle R9232 COInmunicatloB USAR nstccsctacescestesicet niece tetera teen pees comp Bo REIR XD senses 19 WZ 00 OWN CO 19 Fo LEG PRO ASIC osos trem RpE XU ERU EHARER TEENS DIE DU HdERIr I REDEEM RE UI YU ELU dU Un I ae yoda RU 20 FER ICM aas EET 21 1 5 PS 2 Interface EEnt 24 1 6 128x64 GLCD Graphical EC esutotesturinskt sets it dtr qu th reo tritam tud rs et e etr RE Rc v Dern 27 Teal DEM AINE EIA IM risann E E 29 1 8 Real Time Clock DS1307 ictes ecresreccstex baw toes ccatcednce toe secs ose che cn sareasceeteedontenconcerqasuenievtenstoxcatcscerccecueteenecsoue 30 o EN Ee SF MS VS E E EAE E A PE REOR UU I EOrS bra rope cv PED E E 32 9 Getting Started WED AI IIE oeste ds s ORO E OP OP CDU ONU EISE PUDE 92 2 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 1 Introduction Thank you for purchasing the Xilinx Spartan 3 Development Kit You will find it useful in developing your Spartan 3 FPGA application FPGASP3 Kit DPK is an exclusive general purpose kit for the SPARTAN family The intention of the design is to endorse the engineers and scholars to exercise and explore the capabilities of FPGA architectures with many interfacing modules on board point LEDs Sl
58. t switch will be glowing in the LED as output Logical Diagram L scheme VLSI Lab M anual 72 PAntECF SOLUTIONS www pantechsolutions net Technology Beyond the Dreams Flow Chart 73 PAntzECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab Manual Technology Beyond the Dreams PIN Description TN PINS LOC Code Listing library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity first is port x in std logic vector 9 downto 1 a b c d out std logic end first architecture Behavioral of first is begin a lt xl or x3 or x or x7 or x9 b lt x2 or x3 or x6 or x7 c lt x4 or x5 or x6 or x7 d x9 or x8 end Behavioral 74 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR DELAY Description Develop a VHDL code for making a delayed output for 1second or 2 seconds by assuming clock frequency provided in the FPGA Kit Simulate same code to get a delayed waveform Flow Chart START SET input clock Delay for 1sec 75 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing Wpro EEE use IFEE STD LOGIC 1164 ALL uoe TEER DEI CDD ALC Wise TERE od t D COCCI TUNS IGN eID ALCL entity first is pons oee e a a o e
59. ting a new source to add to the project is optional Only one new source can be created with the New Project Wizard Additional sources can be created and added to the project by using the Project New Source command Existing sources can be added on the next page Transcript FIGURE 7 98 PANTECE SOLUTIONS www pantechsolutions net Technology Beyond the Dreams L scheme VLSI Lab M anual He G ow ut Sors Pues Wim Hd AIER kopiena Additional cn can bo ad nd ar the rca icd uirga TIAM Sauce or Pioti Copy of Sou coremands FIGURE 8 99 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Xilinx ISE G PSTYRO FPGASP3 C ODE EXA 3a EXA 3a ise File Edit View Project Source Process Window Help DAHA SGA RFFABAXARCA AB 4Y XBR xa annt x Sources No project is open Select File gt Open Project or File gt New Project New Project Wizard Project Summary Processes x No flow available Project Navigator will create a new project with the following specifications Project Project Name ADDITION Project Path E EXEPERMIENT1 ADDITION Top Level Source Type HDL Device Device Family Spartan3 Device xc3s200 Package tq144 Speed 4 Synthesis Tool XST VHDL Verilog Simulator ISE Simulator VHDL Verilog Enhanced Design Summary disabled Message Filtering disabled lt Back Cancel
60. top utput 3 downto 0 lt store 3 downto 0 sum utput 4 lt store 4 carry Open Without Updating at Properties nd process 33 end Behavioral 34 v a EM Processes h code y Design Summary LI Started Launching Design Summary e Ww i MM d Console Enor fy Wamings Find in Files Run highlighted process Ln 28 Col45 CAPS NUM SCRL VHDL Figure 18 5 Note You must correct any errors found in your source files You can check for errors in the Console tab of the Transcript window If you continue without valid syntax you will not be able to simulate or synthesize your design 6 Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan 3 TYRO PREM IER board To constrain the design ports to package pins do the following before that refer the LED amp SWITCH PIN DETAILS in before pages or see board for giving the pin location e Verify that ADDITION is selected in the Sources window 109 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams e Double click the Assign Package Pins process found in the User Constraints process group The Xilinx Pin out and Area Constraints Editor PACE opens refer figure 19 amp 20 Xilinx ISE EEXEPERMIENTTYADDITION ADDITION ise code vhd M File Edit View Pro
61. tor 4 downto 0 end first architecture Behavioral of farst 18 signal temp std logic vector A downto 0 000007 begin process clk Reset variable i k integer 0 begin if Reset 1 then temp lt 5000007 elsif clk event and clk fe 2 s OO00O0 00 chen EEG Le 50000000 then temp 0 iene TE temp 2 temp 3 not temp 4 end process Dc Lum End Behavioral 87 PAnctECF SOLUTIONS www pantechsolutions net Technology Beyond the Dreams L scheme VLSI Lab M anual VHDL IM PLEM ENTATION OF 7 SEGMENT DISPLAY Description Design and develop a seven segment decoder in VHDL Design and develop a 4 bit BCD counter the output of the counter is given to seven segment decoder A seven segment display is connected to the output of the decoder The display shows 0 1 2 9 for every one second Flow Chart Enable Digit Selection Digit1 Digit6 Display Message 000000 FFFFFF PIN bacca sata P140 P141 P124 88 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams Code Lisitng library ieee use ieee std logic 1164 a1l1l use ieee std logic arith all use ieee std logic unsigned all entity object co is SXc nets elle age ens ee Locuaner y 7 OU otl logic vector downto O sel Our e e e S aa ouo end object co architecture beav of object co is type state is state0 statel state2 state3 stat
62. trolled by PWM e 3 bit 8 color VGA display port e RS232Serial Port e PS 2 connector for mouse keyboard interface port e 128x64 GLCD Module Interface Optional e Serial EEPROM Optional e 2C Real Time Clock with battery back up Optional e 1 Wire Digital Temperature Sensor Optional e bOMHzcrystal oscillator clock source e 20 pin l o connector for interface external peripherals modules e JTAG port for download user program through cable e 9V AC DC power input through adapter e On board 5V 3 3V 2 5V and 1 2V regulators 4 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 2 1 General Block Diagram 9V Input JTAG 315V 3 3V 1 2V Port 2 Nos of Push Button UART Serial Comm 3 bit 8 color VGA Interface 2 Nos SPDT Relay 10 Nos LED Digital Outputs PS 2 20 pin I O connector 10 Slide Switch Digital Outputs Traffic Light Module 4 Nos of 7 segment DISP XC3S200 DCMotor Interface 2x16 Char LCD Stepper Motor Driver Buzzer GLCD128x64 I2C RTC I2C EEPROM 1 Wire Temp WERE E 5 PANTECE SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 3 Jumper amp Switch Details Stepper Relay JP5 Internal Supply 25V External Supply 45V DCMotor JP6 Internal Supply 25V External Supply 45V Buzzer P5 JP7 Enable Buzzer Disable Buzzer Switch Details Program Exec
63. ution Mode Selection EXE M ODE JTAG PROM Execution through JTAG J6 Execution through PROM GLCD Traffic Light Selection GLCD Traffic Select GLCD 9W28 Select TRAFFIC 15V Power Selection SW DIP 4 6 PAntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 4 Connector Details 20pin Box Connector J7 1063 1068 1069 1070 1073 1074 1076 1077 1078 1079 1080 1082 1083 1084 10102 10103 JTAG Connector J2 TMS TDI TDO TCK GND VCC CON6 7 PARntECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 5 PowerSupply The external power can be AC or DC with a voltage between 9V 1A output at 230V AC input The SPARTAN3 board produces 45V using an LM 7805 voltage regulator which provides supply to the peripherals USB socket meant for power supply and USB communication user can select either USB or Ext power supply through SW1 Separate On Off Switch SW1 for controlling power to the board ON OFF Power 45V ON External through Adaptor SW2 Power 45V ON Internal through USB There are multiple voltages supplied on the Spartan 3 Evaluation Kit 3 3V 2 5V and 1 2V regulators Similarly the 3 3V regulator feeds all the VCCO voltage supply inputs to the FPGA s I O banks and powers most of the components on the board The 2 5V regulator supplies power to the FPGA s VCCAUX supply inputs The VCCAU
64. w pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR MULTIPLEXER Description Design and develop a 2 bit multiplexer and port map the same for developing up to 8 bit multiplexer Multiplexer A multiplexer is a combinatorial circuit that 1s given a certain number usually a power of two data inputs let us say 2 and n address inputs used as a binary number to select one of the data inputs The multiplexer has a single output which has the same value as the selected data input In other words the multiplexer works like the input selector of a home music system Only one input is selected at a time and the selected input 1s transmitted to the single output While on the music system the selection of the input is made manually the multiplexer chooses its input based on a binary number the address input The truth table for a multiplexer 1s huge for all but the smallest values of n We therefore use an abbreviated version of the truth table in which some inputs are replaced by to indicate that the input value does not matter Here is such an abbreviated truth table for n 3 The full truth table would have 20 2048 rows 52 PANTECr SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Technology Beyond the Dreams 2 1 mux to construct 8 1 mux Flow chart 53 PAnteECF SOLUTIONS www pantechsolutions net L scheme VLSI Lab M anual Tec

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