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Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data

1. Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk lio 10 mA Vpp 5 V 2 VoL Output low level with 4 pins sunk lo 4 MA Vpp 3 3 V 10 Von Output high level with 8 pins sourced lig 10 MA Vpp 2 5V 2 8 i Output high level with 4 pins sourced lig 4 mA Vpp 3 3 V 2 101 1 Data based on characterization results not tested in production Table 40 Output driving current true open drain ports Symbol Parameter Conditions Max Unit ho 10 mA Vpp 5 V 1 VoL Output low level with 2 pins sunk lo 10 mA Vpp 3 3 V 1 5 V lio 20 mA Vpp 5V 20 1 Data based on characterization results not tested in production Table 41 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk lo 10 mA Vpp DM 0 8 VoL Output low level with 4 pins sunk lo 10 mA Vpp 3 3 V 100 Output low level with 4 pins sunk lo 20 mA Vpp DM 1 5 0 y Output high level with 8 pins sourced lio 10 mA Vpp 5V 4 0 Vou Output high level with 4 pins sourced lio 10 mA Vpp 3 3 V 240 Output high level with 4 pins sourced lo 20 mA Vpp DM 3 30 1 Data based on characterization results not tested in production Figure 25 Typ Vo Vpp 5 V standard ports T 40 C n BC 1 25 85 C 125 C ky 15441 Rev 3 67 95 Electr
2. Table 5 VFQFPN32 LQFP32 pin description impor ER m Alternate Z 25 function o NG o0 Pin e a 5 lt co Default alternate after Pin name S g E TT 3r 3 no P E 35 Z5 olala 5 function remap E 2 EI e 2 O nx 35 option dB c 1 NRST UO X Reset 2 PA1 OSCIN 1 O X X O1 X X Port A1 Resonator crystal in 3 PA2 OSCOUT vo x x x o1 X X Port az Resonatovorystal 4 Vss Digital ground 5 VCAP S 1 8 V regulator capacitor 6 Vpp Digital power supply SPI master 7 PASATIME Cis 1 O X X X HS O3 X X Port A3 Timer 2 channel 3 slave SPI_NSS select AFR1 8 PF4 1 O X X O1 X Port F4 9 PB7 O X X X O1 X Port B7 10 PB6 O X X X O1 X Port B6 11 PB5 I2C SDA VO X X O1 T Port B5 C data 12 PB4 l2C_SCL VO X X O1 T Port B4 I2C clock Analog input 3 13 Kala 1 O X X X HS O3 X X Port B3 Timer 1 external trigger Analog input 2 14 eege 1 O X X X HS O3 X X Port B2 Timer 1 inverted channel 3 22 95 15441 Rev 3 ky STM8S103x Pinout and pin description Table 5 VFQFPN32 LQFP32 pin description continued Input Output co Alternate m 25 function e Dis oo Pin a 5 x co Default alternate after Pin name Sle E T O 3r no F iz 23 23 92 0 5 function remap 5 5 E 9
3. k 7 YA ME Table 54 8 20 pin 4 40 mm body 0 65 mm pitch mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 200 0 0472 A1 0 050 0 150 0 0020 0 0059 A2 0 800 1 000 1 050 0 0315 0 0394 0 0413 b 0 190 0 300 0 0075 0 0118 0 090 0 200 0 0035 0 0079 6 400 6 500 6 600 0 2520 0 2559 0 2598 6 200 6 400 6 600 0 2441 0 2520 0 2598 E1 4 300 4 400 4 500 0 1693 0 1732 0 1772 e 0 650 0 0256 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 8 0 0 0 8 0 aaa 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits 15441 Rev 3 D STM8S103x Package characteristics 11 1 4 UFQFPN package mechanical data Figure 47 20 lead ultra thin fine pitch quad flat no lead package outline 3 x 3 A3 A1 103 A0A5 ME 1 Drawing is not to scale Table 55 20 lead ultra thin fine pitch quad flat no lead package 3 x 3 package mechanical data mm inches Dim Min Typ Max Min Typ Max D 300 one 3 000 0 1181 A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 0060 e 0 500 0 0197 L1 0 500 0 550 0 600 0 0197 0 0217 0 0236 L2 0 300 0 350 0 400 0 0118 0 0138 0 0157 L3 0 150 0 0059 L4 0 200 0 0079 b 0 180 0 250 0 300 0 0071 0 0098 0 0118 ddd 0 050 0 0020
4. Reset block 4 XTAL1 16 MHz SCH Clock controller Reset lt gt Reset lt RC int 16 MHz Detector POR BOR Al RCint 128 kHz Clock to peripherals and core lt gt Window WDG STMB core lt F gt lt gt Independent WDG Single wire 8 Kbytes debug interf Debug SWIM 4 lt gt program Flash 640 bytes CD data EEPROM 3 400 Kbit s LD Gr 5 gt F gam 1 Kbytes 5 RAM ko c oO 8 Mbit s lt gt Set E 2 k Up to lt 4 CAPCOM LIN master lt gt 16 bit advanced control K gt channels UART1 gt i SPI emul lt timer TIM1 4 3 complementary outputs r 16 bit general purpose K Up to Timer TIM2 3 CAPCOM channels 5 gt 8 bit basic timer Upto5 ADG1 lt gt TIM4 channels 1 2 4 kHz lt gt e beep Beeper 5 gt AWU timer 15441 Rev 3 11 95 Product overview STM8S103x 4 4 1 12 95 Product overview The following section intends to give an overview of the basic features of the STM8S103x access line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e H
5. 10 205 PDS HS AIN4 TIM2_CH2 ADC_ETR 2 19E3 PD2 HS AIN3 TIM2_CH3 3 18 PD1 HS SWIM 4 17E3 PC7 HS SPI MISO TIM1_CH2 5 16E3 PC6 HS SPI MOSI TIM1 CH1 6 15 PC5 HS SPI_SCK TIM2_CH1 7 14E3 PC4 HS TIM1_CH4 CLK_CCO AIN2 TIM1 CH2N 8 sc PC3 HS TIM1 CH3 TLI TIM1 CH1N 9 12E3 PB4 T I2C_SCL ADC_ETR 10 11E3 PBS T IPC SDA TIM1 BKIN 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option 15441 Rev 3 D STM8S103x Pinout and pin description d Figure 5 STM8S103F UFQFPN20 pin pinout x O Eu TO 3 Q F T o X x E ai I oF o TO ANO ql EEZ lt ZE 2 E DP DE e IT x 9 z Zu Z lt s go 2 nan o D I LI LIL st n N 8 SA ZS a a e O O WELT ME 20 19 18 17 16 NRST 7 1 15 7 OSCIN PA1 2 14 7 OSCOUT PA2 3 13 7 Vss 4 12 VCAP e e 6 7 9 10 F 3 3 3 z gt Q o o E E o I z L saas I 0 5r GL o 9 S255 2 Z7 o2 Ss T D X ES o m D 2 JE 7258 7 a E zz D I 9 z E PD1 HS SWIM PC7 HS SPI_MISO TIM1 CH2 PC6 HS SPI_MOSI TIM1 CH1 PC5 HS SPI_SCK TIM2 CH1 PC4 HS TIM1 CHA CLK CCO AIN2 TIM1_CH2N dis 2 3 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping opti
6. Table 8 General hardware register map continued Address Block Register label Register name kaaga 0x00 525F TIM1 CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1 PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1 DCH TIM1 repetition counter register 0x00 0x00 5265 TIM1 CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 en TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1 CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1 CCR3L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1 CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1 CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1 BKR TIM1 break register 0x00 0x00 526E TIM1 DTR TIM1 dead time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 0x00 5270 to Reserved area 147 bytes 0x00 52FF 0x00 5300 TIM2_CR1 TIM2 control register 1 0x00 0x00 5301 Reserved 0x00 5302 Reserved 0x00 5303 TIM2 IER TIM2 Interrupt enable register 0x00 0x00 5304 TIM2_SR1 TIM2 status register 1 0x00 0x00 5305 TIM2_SR2 TIM2 status register 2 0x00 0x00 5306 TIM2 TIM2 EGR TIM2 event generation register 0x00 0x00 5
7. Pinout and pin description STM8S103x Table 5 VFQFPN32 LQFP32 pin description continued Input Output e Alternate m 25 function Ka oo Pin a 5 x co Default alternate after Pin name Sle E T O 3r no iz 23 23 92 0 5 function remap S F E O 8 sh option FA bit d 31 PD6 UART1 RX 1 O X X X HS O3 X X Port D6 UART1 data receive Timer 1 32 PDT7 TLI TIM1 CH4 I O X X X HS OS X X Port D7 Top level interrupt channel 4 AFR6 1 I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Table 16 Current characteristics 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain I O P buffer and protection diode to Vpp are not implemented 24 95 Figure 4 STM8S103F TSSOP20 pin pinout UART1 TX AINS HS PDS UART1_RX AIN6 HS PD6 NRST OSCIN PA1 OSCOUT PA2 Vss VCAP Vpp SPI NSS TIM2 CH3 HS PA3 UART1 CK TIM2 CH1 BEEP HS PD4 E
8. 60 10 3 4 Internal clock sources and timing characteristics 62 10 3 5 Memory characteristics 64 10 3 6 I O port pin characteristics 1 122222 sasa aaa 65 10 3 7 Reset pin characteristics sisssussskasaaaaaaanaa 71 10 3 8 SPI serial peripheral interface 73 10 3 9 PC interface characteristics lle eese 76 10 3 10 10 bit ADC characteristics skaka aaa aa 77 10 3 11 EMC characteristics aksara 80 11 Package characteristics anna 83 11 4 Package mechanical data 22 2 2 ss ee 84 11 1 1 LQFP package mechanical data 84 11 1 2 VFQFPN package mechanical data 85 11 1 39 TSSOP package mechanical data leeren 86 11 1 4 UFQFPN package mechanical data 87 112 Thermal characteristics iss ere orm RR OE Ru ER peek LAGA 89 11 2 1 Reference document naknan aanaaaa 89 11 2 2 Selecting the product temperature range 90 12 Ordering information 91 ky 15441 Rev 3 3 95 Contents STM8S103x 13 STM8 development tools 92 13 1 Emulation and in circuit debugging tools 92 13 2 Software tools 2225 20acs vat bdawe ese AER GERE NE RN aaa NKO 93 13 2 1 STMB8 toolset e 93 13 2 2 Cand assembly toolchains aras 93 193 Programming tools Haima Ea eS EA EE aaa aka akka aaa 93 14 Revision history a d CNEL KKK KE AE EELER EE e e e eg Nie 94
9. Table 44 1 C characteristics Standard mode DC Fast mode I2C Symbol Parameter Unit Min 2 Max Min Max twiscLL SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 tsuspa SDA setup time 250 100 tsp SDA data hold time 06 o9 9009 SDA SDA and SCL rise time 1000 300 ns t sCL SDA SDA and SCL fall time 300 300 tyScL ty stay START condition hold time 4 0 0 6 us tsustay Repeated START condition setup time 4 7 0 6 tsuisTo STOP condition setup time 4 0 0 6 us STOP to START condition time bus tw STO STA free 4 7 1 3 us Cp Capacitive load for each bus line 400 400 pF 1 fmasrter must be at least 8 MHz to achieve max fast I2C speed 400kHz Data based on standard C protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 15441 Rev 3 D STM8S103x Electrical characteristics 10 3 10 10 bit ADC characteristics Subject to general operating conditions for Vpp faster and Ta unless otherwise specified Table 45 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp 2 95 to 5 5 V 1 4 fapc ADC clock frequency MHz Vpp 4 5 to 5
10. 700 mv Rp Pull up resistor Vpp 5 V Vin Vss 30 45 60 kQ Fast I Os 20 ns te te Rise and fall time Load 50 pF R F 10 90 Standard and high sink I Os 125 s Load 50 pF Digital input leakage likg current Vss lt ViN lt Vpp 1 pA Analog input lt lt likg ana leakage current Vss Vin S Von Se lika ini Leakage current in Injection current 4 mA 1 kon adjacent UO J E 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production d 15441 Rev 3 65 95 Electrical characteristics STM8S103x Figure 22 Typical Vj and Vu vs Von 4 temperatures 40 C 6 25 C 5 85 C 1250 _ 4 2 I gt 3 zi 5 2 1 0 T T T 25 3 85 4 45 5 55 6 Voo V Figure 23 Typical pull up resistance vs Vpp 4 temperatures 40 C 60 25 C 85 C 55 125C Gi EE o Q e a 2 t ER K a 45 3 a i 4 Kl a 35 30 T T T T T 2 5 3 35 4 45 5 5 5 6 Von V Figure 24 Typical pull up current vs Vpp 4 temperatures 140 120 100 E 80 9 o 3 25 C 40 85 C S m 125 C pd op 0 1 2 3 4 5 6 Voo V 66 95 15441 Rev 3 ky STM8S103x Electrical characteristics Table 39 Output driving current standard ports
11. hJ STM8S103K3 STM8S103F3 STM8S103F2 Access line 16 MHz STM8S 8 bit MCU up to 8 Kbytes Flash data EEPROM 10 bit ADC 3 timers UART SPI I2C Features Core m 16 MHz advanced STMB8 core with Harvard architecture and 3 stage pipeline m Extended instruction set Memories m Program memory 8 Kbytes Flash data retention 20 years at 55 C after 10 kcycles m Data memory 640 bytes true data EEPROM endurance 300 kcycles m RAM 1 Kbytes Clock reset and supply management m 2 95 to 5 5 V operating voltage m Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC m Clock security system with clock monitor m Power management Low power modes wait active halt halt Switch off peripheral clocks individually m Permanently active low consumption power on and power down reset Interrupt management m Nested interrupt controller with 32 interrupts m Up to 27 external interrupts on 6 vectors Timers m Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization June 2009 TSSOP20 UFQFPN20 3x 3 m 16 bit general purpose timer with 3 CAPCOM channels IC OC or PWM m 8 bit basic timer with 8 bit prescaler m Auto wake up timer m 2 watchdog timers Window watchdog and independent watchdo
12. 0x00 50C8 crs CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB CLK CANCCR CAN clock control register 0x00 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register XX 0x00 50CD CLK SWIMCCR SWIM clock control register XO 0x00 50CE to Reserved area 3 bytes 0x00 50DO 0x00 50D1 WEG WWDG CR WWDOG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to Reserved area 13 bytes 00 50DF 0x00 50E0 IWDG KR IWDG key register 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to Reserved area 13 bytes 0x00 50EF 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer Ox3F register 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F 0x00 50F4 to Reserved area 12 bytes 0x00 50FF 15441 Rev 3 ky STM8S103x Memory and register map d Table 8 General hardware register map continued Address Block Register label Register name kaaga 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control reg
13. Updated Figure 6 Memory map Updated reset status of port D CR1 register in Table 7 Updated alternate function remapping descriptions in Table 13 and Table 14 Added Section 9 Unique ID Updated Table 19 General operating conditions Updated name of Figure 19 Typical HSI accuracy at VDD 5 V vs 5 temperatures Updated Table 43 SPI characteristics and added TBD data Added max values to Table 46 and Table 47 in the 10 bit ADC characteristics Updated Section 10 3 11 EMC characteristics d 15441 Rev 3 STM8S103x Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of
14. 24 0x4869 Wafer number U ID 39 32 0x486A U ID 47 40 0x486B U ID 55 48 0x486C U ID 63 56 0x486D Lot number U ID 71 64 0x486E U ID 79 72 0x486F LU ID 87 80 0x4870 U_ID 95 88 1677 15441 Rev 3 45 95 Electrical characteristics STM8S103x 10 10 1 10 1 1 10 1 2 10 1 3 10 1 4 46 95 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 25 C and T4 Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equa
15. 4 95 15441 Rev 3 ky STM8S103x List of tables List of tables Table 1 STM8S103xx access line features 10 Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers 15 Table 3 TIM timer features 2 0 RR mnn 18 Table 4 Legend abbreviations llle rra 22 Table 5 VFQFPN32 LQFP32 pin description ree 22 Table 6 STM8S103F pin description een 26 Table 7 I O port hardware register map n osasuna III 30 Table 8 General hardware register map res 31 Table 9 CPU SWIM debug module interrupt controller registers 38 Table 10 Interrupt Mapping 6 20 RR RII I RR tt 40 Table 11 Option bytes see em rash 41 Table 12 Option byte description RR Ie 42 Table 13 STM8S103K alternate function remapping bits for 32 pin devices 43 Table 14 STM8S103F alternate function remapping bits for 20 pin devices 44 Table 15 Unique ID registers 96 bel 45 Table 16 Voltage characteristics 0 0 en 47 Table 17 Current characteristics sasa eee 48 Table 18 Thermal characteristics en 48 Table 19 General operating conditions ne 49 Table 20 Operating conditions at power up power down esee 50 Table 21 Total current consumption with code execution in run mode at Vpp 2 5 V 51 Table 22 Total current consumption
16. 45 C 0 50 0 00 A 0 50 Pap bo a e a a i 1 00 1 50 2 00 T r T r T 1 25 3 3 5 4 45 5 5 6 Von V Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and T4 Table 35 LSI oscillator characteristics Symbol Parameter Min Typ Max Unit he Frequency 110 128 150 kHz Luten LSI oscillator wake up time 7 us Ibos LSI oscillator power consumption 5 HA Figure 21 Typical LSI frequency variation vs Vpp 4 temperatures 25 C 85 C 5 00 125 C 4 0096 49G 3 00 Se a 2 00 1 00 3 0 00 T 1 00 2 00 3 00 4 00 5 00 r r T r d 2 2 5 3 3 5 4 45 55 6 Voo V 15441 Rev 3 63 95 Electrical characteristics STM8S103x 10 3 5 Memory characteristics RAM and hardware registers Table 36 RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode Halt mode or reset Vir max V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 20 on page 50 for the value of Vit max Flash program memory data EEPROM memory Table 37 Flash program memory data EEPROM memory Symbol Parameter Operating voltage all modes execution write erase Conditions fopu lt 16 MHz Min 2 95 Typ Max 5 5 Unit Standard programming time including er
17. 5 w o X c 2 1 a a 0 5 0 T T 2 4 6 8 10 12 14 16 18 Fcru MHz 15441 Rev 3 57 95 Electrical characteristics STM8S103x Figure 13 Typ IDD RUN VS Vpp HSI RC OSC fepy 16 MHz IDD run HSI mA 25 C 2 85 C 125 C 45 C eo L a En o e o tn a u 4 5 5 N 2 5 3 3 5 4 5 5 6 Vop V Figure 14 Typ Ipp wri VS Vpop HSE user external clock fcpy 16 MHz 0 8 0 6 IDD WFI HSE mA 04 0 2 m 25 C 4 85 C 125 C r 45 C 2 25 3 3 5 4 45 5 5 5 6 Voo V Figure 15 Typ Ipp wen VS fcpu HSE user external clock Vpp 5 V 25C 18 85 C 125 C 16 45 C 14 121 Boa T E os 8 os 04 0 24 0 l l l 2 4 6 8 10 12 14 16 18 Fcru MHz 58 95 15441 Rev 3 y STM8S103x Electrical characteristics d Figure 16 Typ Ipp wr VS Vpp HSI RC OSC cpu 16 MHz mA IDD_WFI_HSI 25 C 85 C 125 C 45 C 2 5 3 3 5 4 45 Fceu MHz 15441 Rev 3 59 95 Electrical characteristics STM8S103x 10 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and T Table 32 HSE user external clock characteristics Symbol Parameter Conditions
18. 55 option E 2 bit wi Analog input 1 15 aa bng WO X X X HS O3 X X Port B1 Timer 1 inverted channel 2 Analog input 0 16 AA WO X X X HS O3 X X Port BO Timer 1 inverted channel 1 17 PE5 SPI NSS Vo x x x Hs 03 X X Portes cn slave PC1 TIM1_CH1 Timer 1 channel 1 18 UART1 CK 1 O X X X HS O3 X X Port C1 UART1 clock 19 PC2 TIM1_CH2 WO X X X HS O3 X Port C2 Timer 1 channel 2 20 PC3 TIM1_CH3 yox HS O3 Port C3 Timer 1 channel 3 Timer 1 channel 4 PC4 TIM1_CH4 21 CLK CCO 1 O X X X HS O3 X X Port C4 configurable clock output 22 PC5 SPI_SCK 1 O X X X HS O3 X X Port C5 SPI clock 23 PC6 SPI_MOSI V O X X X HS O83 X X Portce SP master out slave in SPI master in slave 24 PC7 SPI MISO 1 O X X X HS O3 X X PortC7 out Con K figurable 25 PDOTIM1_BKIN Vo x X X HS os x X PortDo Timer 1 break clock CLK CCO input output AFR5 26 PD1 SWIM JO X X X HS 04 X X Port D1 SWIM data interface Timer 2 27 PD2 TIM2_CH3 1 O X X X HS O3 X X Port D2 channel 3 AFR1 Timer 2 channel 28 PD3 TIM2_CH2 1 O X X X HS O3 X X Port D3 2 ADC external ADC_ETR trigger PD4 BEEP TIM2 CH Timer 2 channel 29 1 1 O X X X HS O3 X X Port D4 1 BEEP output 30 PD5 UART1 TX Vo Xx X X HS os X X Portps VARTI data transmit ky 15441 Rev 3 23 95
19. 95 15441 Rev 3 ky STM8S103x Pinout and pin description Table 6 STM8S103F pin description continued Pin no Input Output a Alternate sla 25 function SIS Sioa 3 z o Default alternate after Q Z Pin name S c c 9 3r o amp PE 3 SE 2lala function remap I 9 5 amp oja SS option EIS Sle bit l Analog input 2 PC4 CLK_CCO mahila AFR2 14 11 TIM1_CH4 AIN2 1 O X X X HS O3 X X Port C4 output TIRE Timer 1 TIM1 CH2N p inverted channel 4 channel 2 AFR7 Timer 2 15 12 Ger WO X X X HS O3 X X Port C5 SPI clock channel 1 AFRO Timer 1 16 13 PC6 SPI_MOSI vo x x x HS O3 X x Port ce master out Channel 1 TIM1_CH1 slave in AFRO PC7 SPI_MISO SPlmasterin TMS 1 17 14 lO X X X HS OS X X Port C7 channel 2 TIM1_CH2 slave out AFRO 18 15 PD1 SWIM 1 0 x x x HS 04 X X Port D1 SWIM data interface Analog input 3 PD2 AIN3 AFR2 19 16 TIM2 CH3 1 O X X X HS O3 X X Port D2 Timer 2 channel 3 AFR1 Analog input 4 PD3 AIN4 TIM2 CH2 Timer 2 channel 20 17 ADC ETR 1 O X X X HS O3 X X Port D3 2 ADC external trigger 1 I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect
20. LSB 1 J Z id IDEAL i l i J l LL 0 1 2 3 4 5 6 7 1021102210231024 Vssa Vpp 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Er Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 43 Typical application with ADC Von STM8 V R ZN 06V AIN AINx F 10 bit A D VAN WA a NNN Kee C V T Wa ZN 0 6V v IL TI CADC ki 15441 Rev 3 79 95 Electrical characteristics STM8S103x 10 3 11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through UO ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs
21. Typ Vo 9 Vpp 3 3 V standard porte 68 Figure 27 Typ Vo 9 Vpp 5 V true open drain porte 68 Figure 28 Typ Vo 9 Vpp 3 3 V true open drain ports lese 68 Figure 29 Typ Vo 9 Vpp 5 V high sink ports BRI 69 Figure 30 Typ Vo 9 Vpp 3 3 V high sink ports BB 69 Figure 31 Typ Vpp Vou 9 Vpp 5 V standard porte 69 Figure 32 Typ Vpp Vou 9 Vpp 3 3 V standard porte 70 Figure 33 Typ Vpp Vou 9 Vpop 5 V high sink ports 0 2 0 eee 70 Figure 34 Typ Vpp Vou 9 Vpop 3 3 V high sink porte 70 Figure 35 Typical NRST Vj and Vy vs Vpp 4 temperatures eese 71 Figure 36 Typical NRST pull up resistance vs Vpp 4 temperatures 71 Figure 37 Typical NRST pull up current vs Vpp 4 temperatures 1 1 1 a 72 Figure 38 Recommended reset pin protection eee 72 Figure 39 SPI timing diagram slave mode and CPHA 0 2 2 2220 74 Figure 40 SPI timing diagram slave mode and CPHA 1 2 222 2 74 Figure 41 SPI timing diagram master WEE 75 Figure 42 ADC accuracy characteristics Ih 79 Figure 43 Typical application with ADC RII III eh 79 Figure 44 32 pin low profile quad flat package xv 84 Figure 45 32 lead very thin fine pitch quad flat no lead package 5 x5 85 Figure 46 20 pin 4 40 mm body 0 65 mm pitch eese 86 Figure 47 20 lead ultra thin fi
22. aka aaa aaa 71 Table 43 SPI characteristics s ssassasanaa sasaran akak aran aaa aa aaa a 73 Table 44 l C characteristics EE 76 Table 45 ADC characteristics 2s ssassanaa saak akak aaa aaa ra aaa aa 77 Table Ap ADC accuracy with Ra lt 10 KO Vpp2 BV lll lll lakka kakak kaka aaa 78 Table 47 ADC accuracy with RAIN lt 10 kQ RAIN Vpp NAA 78 Table 48 EMSdata hh hh 80 ky 15441 Rev 3 5 95 List of tables STM8S103x Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 6 95 EMI dat a nxor n Rea Rendre Eo ure RHET wee RUE VLA V der dean EO e 81 ESD absolute maximum ratings eres 81 Electrical sensitivities 82 32 pin low profile quad flat package mechanical data 84 32 lead very thin fine pitch quad flat no lead package mechanical data 85 20 pin 4 40 mm body 0 65 mm pitch mechanical data 86 20 lead ultra thin fine pitch quad flat no lead package 3 x 3 package mechanical data hr 87 Thermal characteristics llle 89 Document revision history 94 15441 Rev 3 ky STM8S103x List of figures List of figures Figure 1 Block diagram EEN os ame meh esr ENEE ENEE PG e ank add 11 Figure 2 Flash memory organisation 14 Figure 3 STM8S103K VFQFPNS32 LQFP32 pinout eres 21 Figure 4 STM8S103F TSSOP20 pin pinout rens 24 Figure 5 STM8
23. complemented one NOPTXx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 11 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 11 Option bytes Option Option Option bits Factory Addr namie byte default no 7 6 5 4 3 2 1 0 setting Read out 0x4800 protection OPTO ROP 7 0 00h ROP 0x4801 User boot OPT1 UBC 7 0 00h oxago2 code UBC NOPTI NUBC 7 0 FFh 0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 00h function ox4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh AFR LSI IWDG WWDG WWDG 0x4805h OPT3 Reserved HSITRIM 00h Miscellaneous EN HW HW HALT option NLSI NIWI 0x4806 NOPT3 Reserved NESI S POH NWWG UNG FFh TRIM EN W _HW _HALT EXT CKAWU PRS PRS 0x4807 OPT4 Reserved 00h CLK SEL C1 CO Clock option NEXT NCKAWUS NPR NPR 0x4808 NOPT4 Reserved FFh CLK EL SC1 SCO 0x4809 HSE clock OPT5 HSECNT 7 0 00h Ox480A Startup NOPT5 NHSECNT 7 0 FFh ky 15441 Rev 3 41 95 Option bytes STM8S103x T
24. control register 0x00 0x00 540F ADC ANGAL ADC analog m control register 0x00 0x00 5410 to 0x00 57FE Reserved area 1008 bytes 15441 Rev 3 37 95 Memory and register map STM8S103x Table 9 CPU SWIM debug module interrupt controller registers Address Block Register label Register name Wiese 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 0x00 7FOB to 0x00 Reserved area 85 bytes 7F5F 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 i ITC SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt software priority regis
25. detection with interrupt generation e Parity control Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Maximum speed 1 Mbit s at 16 MHz fcpu 16 LIN master mode e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame 4 14 2 SPI Maximum speed 8 Mbit s fuAsrER 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin KY 15441 Rev 3 19 95 Product overview STM8S103x 4 14 3 20 95 Pc I2C master features Clock generation Start and stop generation IC slave features Programmable DC address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz 15441 Rev 3 ki STM8S103x Pinout and pin description 5 d Pinout and pin description Figure 3 STM8S103K VFQFPN32 LQFP32 pinout D SPI_NSS TIM2_CH3 HS PA3 NRST OSCIN PA1 OSCOUT PA2 Vss VCAP Vp PF4 CH2 ADC ETR HS BEEP TIM2 CH1 HS TLI TIM1 CH4 HS UART1_RX HS TIM2 HS TIM2 CH3 HS UART1 TX HS SWIM HS
26. fmasTER 16 MHz HSI clock 2 B conforming to IEC 1000 4 2 V Voltage limits to be applied on any 1 O pin FESD to induce a functional disturbance Fast transient voltage burst limits to be Vpp 3 3 V Ta 25 C Verte applied through 100 pF on Vpp and Vss fmaster 16 MHz HSI clock 4 A pins to induce a functional disturbance conforming to IEC 1000 4 4 80 95 15441 Rev 3 ky STM8S103x Electrical characteristics Electromagnetic interference EMl Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm SAE J 1752 3 which specifies the board and the loading of each pin Table 49 EMI data Conditions 1 Symbol Parameter Monitored Max fuse fcpu Unit General conditions frequency band 16 MHz 16 MHz 8 MHz 16 MHz 0 1MHz to 30 MHz 2 3 Vppz 5V E Peak level Ta 25 C 30 MHz to 130 MHz 10 10 dByV Sc LQFP32 package 130 MHz to 1 GHz 5 7 Conforming to SAE J 1752 3 SAE EMI level SAE EMI level 2 5 2 5 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application n
27. imasTER 128 HSI RC osc 16 MHz 8 0 46 0 58 15 625 kHz 5 Ee LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 52 95 15441 Rev 3 D STM8S103x Electrical characteristics Total current consumption in wait mode Table 23 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 6 fcpu fMASTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply fepy f 128 Ippwrn current in aa HSI RC osc 16 MHz 0 7 0 88 mA wait mode fcpu fmasTER 128 2 4E dns HE HSI RC osc 16 MHz 8 0 45 0 57 fcpu fMASTER 198 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 24 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 1 fcpu IMASTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply fopu f 128 Ippiwry current in a E HSI RC osc 16 MHz 0 7 0 88 mA wait mode fcpu fuAsrER 128 2 i a na HSI RC osc 16 MHz 8 0 45 0
28. min when the trgyp delay has elapsed VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cer to the Vcap pin Geer is specified in Table 19 Care should be taken to limit the series inductance to less than 15 nH Figure 10 External capacitor Cgx1 ESR C ESL e r I asses 1 ESR is the equivalent series resistance and ESL is the equivalent inductance D 15441 Rev 3 STM8S103x Electrical characteristics 10 3 2 Supply current characteristics The current consumption is measured as described in Figure 8 on page 47 Total current consumption in run mode The MCU is placed under the following conditions e AN UO pins in input mode with a static value at Vpp or Vas no load e All peripherals are disabled clock stopped by peripheral clock gating registers except if explicitly mentioned Subject to general operating conditions for Vpp and T Table 21 Total current consumption with code execution in run mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 3 fcpu fMASTER 16 MHz HSE user ext clock 16 MHz 2 2 35 HSI RC osc 16 MHz 1 7 2 Supply current in run fopy fmastep 128 HSE user ext clock 16 MHz 0 86 mode coda JEE HSI RC osc 16 MHz 0 7 0 87 executed from RAM fcpu fmasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcp
29. of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 1577 15441 Rev 3 95 95
30. regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh th
31. the absolute maximum ratings see Table 16 Current characteristics 2 When the MCU is in halt active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if halt active halt is used in the application 3 In the open drain output column T defines a true open drain I O P buffer and protection diode to Vpp are not implemented d 15441 Rev 3 27 95 Pinout and pin description STM8S103x 5 1 28 95 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 15441 Rev3 ky STM8S103x Memory and register map 6 Memory and register map 6 1 Memory map Figure 6 Memory map 0x00 0000 RAM 1 Kbyte oooosrr 4 513 bytes stack 0x00 0800 Reserved 0x00 3FFF 0x00
32. 0 AFR1 remapping option inactive Default alternate functions 1 Port A3 alternate function SPI_NSS port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option O Reserved 1 Do not use more than one remapping option in the same port It is forbidden to enable both AFR1 and AFRO 2 Referto pinout description d 15441 Rev 3 43 95 Option bytes STM8S103x Table 14 STM8S103F alternate function remapping bits for 20 pin devices Option byte no Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive Default alternate functions 1 Port C3 alternate function TIM1_CH1N port C4 alternate function TIM1_CH2N AFR6 Alternate function remapping option 6 Reserved AFRB5 Alternate function remapping option 5 Reserved AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate functions 1 Port B4 alternate function ADC ETR port B5 alternate function TIM1 BKIN OPT2 AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive Default alternate functions 1 Port C4 alternate function AIN2 port D2 alternate function AIN3 AFR1 Alternate function remapping option 1 2 0 AFR1 remapping option inactive Default alternate functions
33. 1 Port A3 alternate function SPI_NSS port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option o 0 AFRO remapping option inactive Default alternate functions 1 Port C5 alternate function TIM2 CH1 port C6 alternate function TIM1 CH1 port C7 alternate function TIM1 CH2 1 Refer to pinout description 2 Do not use more than one remapping option in the same port It is forbidden to enable both AFR1 and AFRO D 44 95 15441 Rev 3 STM8S103x Unique ID 9 Unique ID STM8S103x devices feature a 96 bit unique device identifier which provides a reference number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm The unique device identifier is ideally suited e For use as serial numbers e For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory e To activate secure boot processes Table 15 Unique ID registers 96 bits Unique ID bits em description 7 6 5 4 3 2 1 0 0x4865 X co ordinate on U ID 7 0 0x4866 the wafer U ID 15 8 0x4867 Y co ordinate on U_ID 23 16 0x4868 the wafer U_ID 31
34. 1 Values in inches are converted from mm and rounded to 4 decimal digits d 15441 Rev 3 87 95 Package characteristics STM8S103x 88 95 Figure 48 Recommended footprint for on board emulation date Ve 0 8mm 0 032 4mm 0 157 Pol 0 5mm i 1 65mm 0 065 HL 0 9mm 0 035 0 3mm 0 012 4mm 0 157 ai15319 Bottom view 1 Drawing is not to scale Figure 49 Recommended footprint without on board emulation prs Dem aen mu spese 3 30 E HAI 2 30 1 ki F 40 55 E ahy nad tp I 3 30 4 1 Drawing is not to scale 2 Dimensions are in millimeters 15441 Rev 3 ky STM8S103x Package characteristics 11 2 Thermal characteristics The maximum chip junction temperature T max must never exceed the values given in Table 19 General operating conditions on page 49 The maximum chip junction temperature T max in degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X ya Where Tas S the maximum ambient temperature in C Oy is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Piyomax PDmax Pintmax Pi Omax e Pintmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pi omax represent
35. 1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits 15441 Rev3 Si STM8S103x Package characteristics 11 1 2 d VFQFPN package mechanical data Figure 45 32 lead very thin fine pitch quad flat no lead package 5 x 5 C 1 Seating plane E2 Bottom view 42 ME Table 53 32 lead very thin fine pitch quad flat no lead package mechanical data mm inches Dim Min Typ Max Min Typ Max A 0 80 0 90 1 00 0 0315 0 0354 0 0394 Al 0 0 02 0 05 0 0008 0 0020 A3 0 20 0 0079 b 0 18 0 25 0 30 0 0071 0 0098 0 0118 D 4 85 5 00 5 15 0 1909 0 1969 0 2028 D2 3 20 3 45 3 70 0 1260 0 1457 E 4 85 5 00 5 15 0 1909 0 1969 0 2028 E2 3 20 3 45 3 70 0 1260 0 1358 0 1457 e 0 50 0 0197 L 0 30 0 40 0 50 0 0118 0 0157 0 0197 ddd 0 08 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 15441 Rev 3 85 95 Package characteristics STM8S103x 11 1 3 86 95 TSSOP package mechanical data Figure 46 20 pin 4 40 mm body 0 65 mm pitch
36. 307 TIM2 CCMR1 TIM2 a i mode register 0x00 0x00 5308 TIM2 CCMR2 TIM2 aa al mode register 0x00 0x00 5309 TIM2 CCMR3 TIM2 Spem mode register 0x00 0x00 530A TIM2 CCER1 TIM2 SP GG enable register 0x00 15441 Rev 3 35 95 Memory and register map STM8S103x 36 95 Table 8 General hardware register map continued Address Block Register label Register name nese status 0x00 530B TIM2 CCER2 TIM2 ve enable register 0x00 00 530COx TIM2_CNTRH TIM2 counter high 0x00 0x00 530D TIM2_CNTRL TIM2 counter low 0x00 0x00 530E TIM2_PSCR TIM2 prescaler register 0x00 0x00 530F TIM2_ARRH TIM2 auto reload register high OxFF 0x00 5310 Kou TIM2 ARRL TIM2 auto reload register low OxFF cont 0x00 5311 TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5312 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5313 TIM2_CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5314 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5315 TIM2 CCR3H TIM2 capture compare register 3 high 0x00 0x00 5316 TIM2 CCR3L TIM2 capture compare register 3 low 0x00 0x00 5317 to Reserved area 43 bytes 0x00 533F 0x00 5340 TIM4 CR1 TIM4 control register 1 0x00 0x00 5341 Reserved 0x00 5342 Reserved 0x00 5343 TIM4 IER TIM4 interrupt enable register 0x00 0x00 5344 TIM4 TIM4 SR TIM4 st
37. 4000 X00 53D 640 bytes data EEPROM 0x00 4280 Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 480A 0x00 480B Ox00 4864 DEE 0x00 4865 0x00 4870 Unique ID 0x00 4871 0x00 4FFF Reserved PROS ROS GPIO and periph reg sees see Table 7 and Table 8 0x00 5800 Reserved 0x00 7EFF 0x00 75 00 CPU SWIM debug ITC registers see Table 9 0x00 7FFF 0x00 8000 32 interrupt vectors 0x00 807F Tel 0x00 8080 Flash program memory 0x00 9FFF 8 Kbytes 0x00 A000 Reserved 0x02 7FFF ky 15441 Rev 3 29 95 Memory and register map STM8S103x 6 2 Register map Table 7 O port hardware register map Address Block Register label Register name Weer 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register 0x00 0x00
38. 441 Rev 3 73 95 Electrical characteristics STM8S103x Figure 39 SPI timing diagram slave mode and CPHA 0 NSS input tsu NSS pa tc SCK th NSS 74 CPHA 0 FT CPOL 0 SCK Input OO 32 iT O 77 o A e lt i v Le ISCH t ta SO lt gt I th SO pa Pa mad hn dis SO r T X BIT tv SO MISO i OUTPUT MSB OU our SETTU OUT su Sl e atin Ya X INPUT ths ai14134 Figure 40 SPI timing diagram slave mode and CPHA 1 NSS input A CPHA 1 ES V N i CPOL 0 j TEN CPHA 1 t i EDEN Ju SCKy l t di th SO Za is sora MISO OUTPUT Velour Mskou BIT6 OUT Bou OUT me Sl a pi E EE SI INPUT man IN 4 n IN ai14135 SCK Input 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 Vpp d 74 95 15441 Rev 3 STM8S103x Electrical characteristics Figure 41 SPI timing diagram master mode SCK Input SCK Input High NSS input ng i SCKj CPHA 0 N N N CPOL 0 fi No CPHA 0 3 Y CA xa PG MISO f SCK ECCE OUTUT MSBOUT AN U EE C su V MO 76 8 h MO gt ai14136 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 Vpp ky 15441 Rev 3 75 95 Electrical characteristics STM8S103x 10 3 9 76 95 IPC interface characteristics
39. 5 V 1 6 Vain Conversion voltage range Vss Vpp V Internal sample and hold Cape capacitor 3 pF fap 4 MHz 0 75 te Minimum sampling time E us fADC 6 MHz 0 5 terag Wake up time from standby 7 us Minimum total conversion time ibe S 99 us tconv including sampling time 10 bit fapc 6 MHz 2 33 us resolution 14 l fApc d 1 During the sample time the input capacitance Cam 3 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tg After the end of the sample time tg changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming 15441 Rev 3 77 95 Electrical characteristics STM8S103x 78 95 Table 46 ADC accuracy with Ran lt 10 kQ Vpp 5 V Symbol Parameter Conditions Typ Max Unit fApc 2 MHz 1 6 3 5 EA Total unadjusted error fapc 4 MHz 2 2 4 fapc 6 MHz 2 4 4 5 fapc 2 MHz 1 1 2 5 IEg Offset error fapc 4 MHz 1 5 3 fapc 6 MHz 1 8 3 fapc 2 MHz 1 5 3 lEgl Gain error fapc 4 MHz 2 1 3 LSB fapc 6 MHz 2 2 4 fapc 2 MHz 0 7 1 5 lEpl Differential linearity error fapc 4 MHz 0 7 1 5 fapc 6 MHz 0 7 1 5 fapc 2 MHz 0 6 1 5 IE I Integral linearity error fapc 4 MHz 0 8 2 fApc 6 MHz 0 8 2 D
40. 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0x00 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 30 95 15441 Rev 3 ky STM8S103x Memory and register map Table 8 General hardware register map Address Block Register label Register name nesel status 0x00 501E to Reserved area 60 bytes 0x00 5059 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Midi dE OxFF register 2 0x00 505D Flash FLASH FPR Flash pro
41. 5232 UART1 BRR1 UART1 baud rate register 1 00h 0x00 5233 UART1 BRR2 UART1 baud rate register 2 00h 0x00 5234 UART1 CR1 UART1 control register 1 00h 0x00 5235 UART1 UART1 CR2 UART1 control register 2 00h 0x00 5236 UART1 CR3 UART1 control register 3 00h 0x00 5237 UART1_CR4 UART1 control register 4 00h 0x00 5238 UART1 CR5 UART1 control register 5 00h 0x00 5239 UART1_GTR UART1 guard time register 00h 0x00 523A UART1 PSCR UART1 prescaler register 00h 0x00 523B to Reserved area 21 bytes 0x00 523F 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 Ka a IG mode register 0x00 TIM1 0x00 5259 TIM1_CCMR2 TIM1 EES mode register 0x00 0x00 525A TIM1 CCMR3 TIM1 didi mode register 0x00 0x00 525B TIM1 CCMR4 TIM1 add as mode register 0x00 0x00 525C TIM1_CCER1 TIM1 HUG enable register 0x00 0x00 525D TIM1 CCER2 TIM1 SEH enable register 0x00 0x00 525E TIM1 CNTRH TIM1 counter high 0x00 34 95 15441 Rev 3 Si STM8S103x Memory and register map d
42. 57 fcpu fMAsTER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off d 15441 Rev 3 53 95 Electrical characteristics STM8S103x Total current consumption in active halt mode Table 25 Total current consumption in active halt mode at Vpp 5 V Conditions 1 Maxat85 Maxat Symbol Parameter Main voltage Flash Clock Typ oc 125 c t Unit regulator model source MvR HSE crystal osc 1030 Operating 16 MHz mode LSI RC osc 128 kHz 200 260 300 On Supply HSE crystal osc 970 current in Power down 16 MHz A DD AH active halt mode LSI RC osc mode 128 kHz 150 200 230 Operating 66 85 110 mode LSI RC osc pi 128 kHz Power down 10 20 40 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 26 Total current consumption in active halt mode at Vpp 3 3 V Conditions e Max at Max at Symbol Parameter ae Flash Clock Typ 85 c 125 ec Unit 3 MVR O mode Source HSE crystal osc 550 Operating 8MH fT mode LSI RC osc 128 kHz 200 260 290 On Supply HSE crystal osc 970 current in Power down 16 MHz A DD AH active halt mode LSI RC os
43. C 10 pF 12 fosc 16 MHz stabilized 9 Om Oscillator transconductance 5 mA V tuus Startup time Vpp is stabilized 1 ms 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details Data based on characterization results not tested in production sU HSE is the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 18 HSE oscillator circuit diagram Resonator Du E fuse to core asin gt Resonator OSCOUT gt Consumption control STM8 d HSE oscillator critical g formula Jmorit 2x IIx HSE x R 2Co C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 42 Cj C Grounded external capacitance 9m gt gt Omcrit 15441 Rev 3 61 95 Electrical characteristics STM8S103x 10 3 4 Subject to general operating conditions for Vpp and T High speed internal RC oscillator HSI Table 34
44. HSI oscillator characteristics Internal clock sources and timing characteristics Symbol fusi Parameter Frequency Conditions Min Typ 16 Max Unit MHz ACCusi Accuracy of HSI oscillator User trimmed with CLK HSITRIMR register for given Vop and TA conditions Accuracy of HSI oscillator factory calibrated Vpp 5 V Ta 25 C 2 53 1 33 Yo Vpp 5 V 25 C T4 B5 C 253 2 3 2 95 lt Vpp lt 5 5 V 40 C XTA s125 C 4 5 2 3 3 2 3 tsu HSI HSI oscillator wakeup time including calibration 14 us Ipp HSI e ob gt HSI oscillator power consumption Refer to application note 170 Data based on characterization results not tested in production Subject to further characterization to give better results Guaranteeed by design not tested in production Figure 19 Typical HSI accuracy at Vpp 5 V vs 5 temperatures 250 HA 3 00 1 2 00 1 1 0096 4 0 00 4 1 00 1 2 00 1 3 00 4 00 1 ee max min 5 0096 40 125 62 95 15441 Rev3 d STM8S103x Electrical characteristics d Figure 20 Typical HSI frequency variation vs Vpp 4 temperatures 25 C 85 C 1 00 125 C
45. MHz 0 56 n operating 4 7 6 MVR voltage ode regulator on Flash in power 30 5 i Wakeup time active halt down mode HSI us WU AH mode to run model Flash in operating after wakeup 180 5 MVR voltage mode 4 regulator off Flash in power 50 down mode 9 Wakeup time from halt Flash in operating mode 52 WU H 3 mode to run mode Fiash in power down mode 54 1 Data guaranteed by design not tested in production 2 twuwel 2 X 1 fmaster 6 X 1 fcpu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK_ICKR register 5 Configured by the AHALT bit in the FLASH CR1 register 6 Plus 1 LSI clock depending on synchronization ky 15441 Rev 3 55 95 Electrical characteristics STM8S103x Total current consumption and timing in forced reset state Table 30 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Ipp R Supply current in reset state ki wd UA Vpp 3 3 V 300 tRESETBL Reset pin release to vector fetch 150 us 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vgs Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T4 HSI internal RC fcpy fuAsrER 16 MHz Vpp 5 V Table 31 Peripheral current consumption Symbol Parameter Typ Unit Ippcrim1 TIM1 supply c
46. Min Max Unit fius G t Se clock source 0 16 MHz Vasen Sech input pin high level 0 7xVpp Vpp 0 3 V Vuen Di Ge input pin low level Vig 0 3 x Vpp S LEAK uer OSCIN input leakage current Vas lt Vin lt Vpp 1 1 yA 1 Data based on characterization results not tested in production Figure 17 HSE external clock source VhseH VuseL h External clock source PLL OSCIN gt fusE STM8 HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy 60 95 15441 Rev 3 STM8S103x Electrical characteristics Table 33 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit Ges GE speed oscillator 4 16 MHz Rp Feedback resistor 220 kQ c Recommended load capacitance 2 20 pF C 20 pF 6 oe fosc 16 MHz stabilized 9 loomse HSE oscillator power consumption E ERU mA
47. S103F UFQFPN20 pin pinout RII III 25 Figure 6 Memory map mr ru hr 29 Figure 7 Pin loading conditions RR RII I eae 46 Figure8 Pin input voltage 2 e RI e I re 47 Figure 9 fopumax Versus VDD l a aaeanoa eaa EEEE EEEE EEEE A sl rrr rli 50 Figure 10 External capacitor CEXT rm 50 Figure 11 Typ Ipp Ruw VS Von HSE user external clock fepy 16 MHz 57 Figure 12 Typ Ipp run VS fcpu HSE user external clock Vpp 5 V L aa 57 Figure 13 Typ Ipp Ruw VS Von HSI RC osc fcpy 16 MHZ n a ee 58 Figure 14 Typ Ipp wry VS Vpp HSE user external clock fepy 16 MHz a 58 Figure 15 Typ Ipp wry VS fcpy HSE user external clock Vpp BV 58 Figure 16 Typ Ipp wri VS Vpp HSI RC osc fepy 16 MHz eee 59 Figure 17 HSE external clock source m 60 Figure 18 HSE oscillator circuit diagram eee 61 Figure 19 Typical HSI accuracy at Vpp 5 V vs 5 temperatures 1 1 1 2 eee 62 Figure 20 Typical HSI frequency variation vs Vpp 4 temperatures 63 Figure 21 Typical LSI frequency variation vs Vpp 4 temperatures 63 Figure 22 Typical Vj and Vj vs Vpp 4 temperatures eee 66 Figure 23 Typical pull up resistance vs Vpp 4 temperatures 1 1 sssa sanna 66 Figure 24 Typical pull up current vs Vpp 4 temperatures 66 Figure 25 Typ Vo 9 Vpp 5 V standard porte 67 Figure 26
48. TIM1 BKIN CLK CCO PD6 PD5 PD4 PD3 PD2 PD1 PDO w pari w o N Ce N o N N ND o m Cc e o PD7 o Joo ko 9 1011121314 PB7 PB6 T PB5 T PB4 HS PB3 HS PB2 GC SCL TIM1 ETR AIN3 lac SDA TIM1 CH3N AIN2 TIM1 CH2N AIN1 1 HS PB1 HS PBO TIM1 CH1N AINO PC7 PC6 PC5 PC4 HS SPI MISO HSy SPI MOSI HS SPI_SCK HS TIM1_CH4 CLK_CCO PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1 CH1 UART1 CK PE5 HS SPI NSS HS high sink capability duplication of the function 15441 Rev 3 T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a 21 95 Pinout and pin description STM8S103x Table 4 Legend abbreviations Type I Input O Output S Power supply Level Input CM CMOS Output HS High sink Output speed O1 Slow up to 2 MHz O2 Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset O4 Fast slow programmability with fast as default state after reset Port and control Input float floating wpu weak pull up configuration Output T True open drain OD Open drain PP Push pull Reset state Bold X
49. This test conforms with the IEC 1000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 48 EMS data Symbol Parameter Conditions Level class Vpp 3 3 V Ta 25 C
50. able 12 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Page O defined as UBC memory write protected 0x02 Pages O to 1 defined as UBC memory write protected Page 0 and 1 contain the interrupt vectors Ox7F Pages 0 to 126 defined as UBC memory write protected Other values Pages O to 127 defined as UBC memory write protected Note Refer to the family reference manual RM0016 section on Flash write protection for more details OPT2 AFR 7 0 Refer to Table 13 and Table 14 respectively for alternate function remapping descriptions for 32 pin and 20 pin devices OPT3 HSITRIM High speed internal clock trimming register size 0 3 bit trimming supported in CLK HSITRIMR register 1 4 bit trimming supported in CLK HSITRIMR register LSI EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG win
51. always be connected to the external power supply 2 Iw must never be exceeded This is implicitly insured if Vjy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the liy pin value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vas For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected d 15441 Rev 3 47 95 Electrical characteristics STM8S103x 48 95 Table 17 Current characteristics Symbol Ratings Max Unit Jupp Total current into Vpp power lines source 100 lyss Total current out of Vss ground lines sink 80 Output current sunk by any 1 O and control pin 20 Ho Output current source by any I Os and control pin 20 Injected current on NRST pin 4 Ge Inem 24 Injected current on OSCIN pin 4 Injected current on any other pin 4 Zus Total injected current sum of all I O and control pins 20 Data based on characterization results not tested in production All power Vpp and ground Vss pins must always be connected to the external supply Iw must never be exceeded This is implicitly insured if Vu maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the lj j piyy value A positive injection is induced by Vu Vpp while a negative injection is induce
52. arvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers 15441 Rev 3 ky STM8S103x Product overview 4 2 4 3 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in al
53. ase for byte word block 1 byte 4 bytes 64 bytes 6 6 Fast programming time for 1 block 64 bytes 3 33 Erase time for 1 block 64 bytes 3 33 ms IRET Ipp Erase write cycles program memory Ta 85 C 10k Erase write cycles data memory Data retention program and data memory after 10k erase write cycles at Ta 55 C Ta 125 C Tret 55 C 300 k 20 1M Data retention data memory after 300k erase write cycles at Ta 125 C Supply current Flash programming or erasing for 1 to 128 bytes Tuer 85 C cycles years mA 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte 64 95 15441 Rev3 D STM8S103x Electrical characteristics 10 3 6 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 38 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level ViL voltage 0 3 V 0 3 x Vpp V Input high level Vop 5V Vin voltage 0 7 x Von Vpp 0 3 V V Vays Hysteresis
54. ata EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller 4 5 Clock controller The clock controller distributes the system clock fuAsrER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources Four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Upto 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontrolle
55. ata characterization in progress 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for In up and Zlins Piny in Section 10 3 6 does not affect the ADC accuracy Table 47 ADC accuracy with RAIN lt 10 kQ Rain Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fADC 2 MHz 1 6 3 5 IE Total unadjusted error fADC 4 MHz 1 9 4 fap 2 MHz 1 2 5 lEol Offset error S fADC 4 MHz 1 5 2 5 fap 2 MHz 1 3 3 IEg Gain error LSB fADC 4 MHz 2 3 fap 2 MHz 0 7 1 lEpl Differential linearity error E fADC 4 MHz 0 7 1 5 fap 2 MHz 0 6 1 5 IE Integral linearity error E fADC 4 MHz 0 8 2 1 Data characterization in progress 15441 Rev 3 ky STM8S103x Electrical characteristics Figure 42 ADC accuracy characteristics A Ee 1029 EE p 1022 Misg _ VpDA sSA IDEAL 1024 1021 4 P p sn we Qj 27 i ET as 4 i 7 4 1 Ex ox 1 1 Zi 1 6 o lt 1 d Er z r i NU din 1 1 7 i 1 34 1 z 1 i i 7 Pt ED i mik E i 1
56. atus register 0x00 0x00 5345 TIM4 EGR TIM4 event generation register 0x00 0x00 5346 TIM4 CNTR TIM4 counter 0x00 0x00 5347 TIM4 PSCR TIM4 prescaler register 0x00 0x00 5348 TIM4 ARR TIM4 auto reload register OxFF 0x00 5349 to Reserved area 153 bytes 0x00 53DF 0x00 53E0 to ADC1 ADC _DBxR ADC data buffer registers 0x00 0x00 53F3 0x00 53F4 to Reserved area 12 bytes 0x00 53FF 15441 Rev 3 D STM8S103x Memory and register map d Table 8 General hardware register map continued Address Block Register label Register name HER status 0x00 5400 ADC _CSR ADC control status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high 0x00 0x00 5405 ADC DRL ADC data register low 0x00 0x00 5406 ADC TDRH ADC Schmitt Re disable register 0x00 0x00 5407 ADC_TDRL ADC Schmitt e disable register 0x00 0x00 5408 T ADC HTRH ADC high threshold register high 0x03 con 0x00 5409 ADC HTRL ADC high threshold register low OxFF 0x00 540A ADC_LTRH ADC low threshold register high 0x00 0x00 540B ADC LTRL ADC low threshold register low 0x00 0x00 540C ADC AWSRH ADC analog n status register 0x00 0x00 540D ABGONWSRL ADC analog Hi status register 0x00 0x00 540E ADG Zeie ADC analog Sd
57. c H mode 128 kHz 150 200 230 parating 66 80 105 mode LSI RC osc Off kH Power down 128 kHz 10 18 35 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register 54 95 15441 Rev 3 d STM8S103x Electrical characteristics Total current consumption in halt mode Table 27 Total current consumption in halt mode at Vpp 5 V Maxat Maxat Symbol Parameter Conditions Typ 85 c 125 sc D Unit Flash in operating mode HSI clock after wakeup 63 75 105 Supply current in A DD H halt mode Flash in power down mode HSI clock after 6 0 15 35 H wakeup 1 Data based on characterization results not tested in production Table 28 Total current consumption in halt mode at Vpp 3 3 V T Max at Symbol Parameter Conditions 125 cl i Supply current in Flash in operating mode HSI clock after wakeup 60 75 100 HA DD H halt mode Flash in power down mode HSI clock after wakeup 4 5 12 30 1 Data based on characterization results not tested in production Low power mode wakeup times Table 29 Wakeup times Symbol Parameter Conditions Typ Max Unit See t Wakeup time from wait note WU WF mode to run model fopu fuAsrER 16
58. compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break 4 11 TIM2 16 bit general purpose timer 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 3 individually configurable capture compare channels PWM mode Interrupt sources 3 x input capture output compare 1 x overflow update ky 15441 Rev 3 17 95 Product overview STM8S103x 4 12 TIM4 8 bit basic timer e 8 bitautoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 3 TIM timer features Counter Counting CAPCOM Complem Ext Timer Timer s Prescaler F synchronization size bits mode channels outputs trigger ds chaining Any integer from TIM1 1 to 65536 Up down 4 3 Yes Any power of 2 from 1 TIM2 16 39768 Up 3 0 No No Any power of 2 from 1 TIM4 to 128 Up 0 0 No 4 13 Analog to digital converter ADC1 STM8S103x products contain a 10 bit successive approximation A D converter ADC1 with up to 5 external multiplexe
59. d by Viy Vss For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected Negative injection disturbs the analog performance of the device See note in Section 10 3 10 10 bit ADC characteristics on page 77 When several inputs are submitted to a current injection the maximum Du unn is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with lj py maximum current injection on four I O port pins of the device Table 18 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 4150 B Tj Maximum junction temperature 150 D 15441 Rev 3 STM8S103x Electrical characteristics 10 3 d Operating conditions Table 19 General operating conditions Symbol Parameter Conditions Min Max Unit fopy Internal CPU clock frequency 0 16 MHz Vpp Standard operating voltage 2 95 5 5 V lt lt CExT VCAP external capacitor lm coal 470 3300 nF LQFP32 330 Power dissipation at VFQFPN32 550 Taz 85 C for suffix 6 TSSOP20 207 UFQFPN20 220 Pp mW LQFP32 83 Power dissipation at VFQFPN32 110 Ta 125 C for suffix 3 TSSOP20 59 UFQFPN20 55 Wer temperature fors Maximum power dissipation 40 85 T suffix version A Ambient seperate tors Maximum power dissipation 40 125 C suffix version 6 suffix vers
60. d in Table 56 Thermal characteristics on page 89 T ymax is calculated as follows for LQFP32 59 C W TJmax 75 C 59 C W x 464 mW 75 C 27 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 15441 Rev 3 Ly STM8S103x Ordering information 12 d Ordering information Figure 50 STM8S103x access line ordering information scheme Example Product class STM8 microcontroller STM8 ON S Family type S Standard 103 K Sub family type 103 Access line 103 sub family Pin count K 32 pins F 20 pins 3 Program memory size 3 8 Kbytes 2 4 Kbytes T Package type P TSSOP T LQFP U VFQFPN or UFQFPN 6 Temperature range 3 40 C to 125 C 6 40 C to 85 C Package pitch No character 0 5 mm B 0 65 mm C 0 8 mm Packing C TR No character Tray or tube TR Tape and reel 1 15441 Rev 3 For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you 91 95 STM8 development tools STM8S103x 13 13 1 92 95 STM8 development tools Development tools for the STM8 microcontrollers include the full feat
61. d input channels and the following main features e Input voltage range 0 to Vpp e Conversion time 14 clock cycles e Single and continuous and buffered continuous conversion modes e Buffer size n x 10 bits where x number of input channels e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e Analog watchdog interrupt e External trigger input e Trigger from TIM1 TRGO e Endofconversion EOC interrupt 4 14 Communication interfaces 18 95 The following communication interfaces are implemented UART 1 Full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode single wire mode LIN2 1 master capability SPI Full and half duplex 8 Mbit s I C Up to 400 Kbit s 15441 Rev 3 STM8S103x Product overview 4 14 1 UART1 Main features One Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s fep 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e Two receiver wakeup modes Address bit MSB dle line interrupt e Transmission error
62. dow watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active 42 95 D 15441 Rev 3 STM8S103x Option bytes Table 12 Option byte description continued Option byte no OPT4 Description EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles Table 13 STM8S103K alternate function remapping bits for 32 pin devices Option byte no OPT2 Description AFR7 Alternate function remapping option 7 Reserved AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive Default alternate function 1 Port D7 alternate function TIM1_CH4 AFRB5 Alternate function remapping option 5 0 AFR5 remapping option inactive Default alternate function 1 Port DO alternate function CLK_CCO AFR 4 2 Alternate function remapping options 4 2 Reserved AFR1 Alternate function remapping option 1
63. e counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register 15441 Rev 3 ky STM8S103x Product overview Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s 4 8 Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM1 input capture channel 1 for calibration 4 9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz 4 10 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Four independent capture
64. equence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 The size of the UBC is programmable through the UBC option byte Table 12 in increments of 1 page 64 byte block by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory Up to 8 Kbytes minus UBC e User specific boot code UBC Configurable up to 8 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organisation Data Data memory area 640 bytes EEPROM memory Option bytes r Programmable area from 64 bytes UBC area 1 page up to 8 Kbytes Remains write protected during IAP in 1 page steps Low density Flash program memory 8 Kbytes Program memory area Write access possible for IAP 15441 Rev 3 ky STM8S103x Product overview Read out protection ROP The read out protection blocks reading and writing the Flash program memory and d
65. g Communications interfaces m UART with clock output for synchronous operation Smartcard IrDA LIN master mode m SPlinterface up to 8 Mbit s m DC interface up to 400 Kbit s Analog to digital converter ADC m 10 bit 1 LSB ADC with up to 5 multiplexed channels scan mode and analog watchdog l Os m Upto28l Os on a 32 pin package including 21 high sink outputs m Highly robust I O design immune against current injection m Development support Embedded single wire interface module SWIM for fast on chip programming and non intrusive debugging Unique ID m 96 bit unique key for each device 15441 Rev 3 1 95 www st com Contents STM8S103x Contents 1 Lasa Fi EEN 9 2 DescrIDHO oa uasa dw ras bssspsda ak k E eis m masin RR CR REOR CR 10 3 Block diagram 6 maa maaya ck ci kek cab ae eu 60 NAG a ra ad 11 4 Product overview saisie minh om hm ene RO 8 08 OR EE aaa 12 4 1 Central processing unit STM8 sansar skarar 12 4 2 Single wire interface module SWIM and debug module DM 13 4 3 Interrupt controller Xa ga kaaa on EROR ERR YER ehe re RR ced 13 4 4 Flash program and data EEPROM memory 14 45 Clock controller aset de RERROERRRESG RES rakna REFER ERE 15 4 6 Power management 0 enne 16 4 7 Watchdogtimers soie x ERRRER RR IEEE DDR ER RREERRERG RR aaa a 16 48 Auto wakeup counter eene 17 4 9 Beeper mc T 17 4 10 TIM1 16 bit advanced c
66. ical characteristics STM8S103x 68 95 Figure 26 Typ Vo Vpp 3 3 V standard ports 40 C a 25 C 1 25 85 C 125 C Vol V la mA Figure 27 Typ Vo Vpp 5 V true open drain ports C 2 25 C 85 C 1 5 1 125 C Voll lo mA 25 Figure 28 Typ Vo Vpp 3 3 V true open drain ports C 25 C 85 C 151 125 C Va V 15441 Rev 3 D STM8S103x Electrical characteristics Figure 29 Typ Vo Vpp 5 V high sink ports 4 0C m 25 C 125 85 C 125 C 25 lo mA Figure 30 Typ Vo Vpp 3 3 V high sink ports 40 25 C 125 85 C 125 C lo mA Figure 31 Typ Vpp Vou Vpp 5 V standard ports 40 C 25 C 85 C 15 125 C Voo VoH V lou mA ky 15441 Rev3 69 95 Electrical characteristics STM8S103x Figure 32 Typ Vpp Von Vpp 3 3 V standard ports paa 401C 25C 85 C 125 C V
67. ighlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontrollers Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences 13 2 2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com e Haisonance C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www raisonance com e STMS8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code 13 3 Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which pro
68. ion 40 105 Ty Junction temperature range 3 suffix version 40 1803 1 Care should be taken when selecting the capacitor due to its tolerance as well as its dependency on temperature DC bias and frequency in addition to other factors 2 To calculate Pomax Ta use the formula Ppmax T max Ta Qya see Section 11 2 Thermal characteristics with the value for Tjmax given in Table 19 and the value for Qj given in Table 56 Thermal characteristics 3 TJmax is given by the test limit Above this value the product behavior is not guaranteed 15441 Rev 3 49 95 Electrical characteristics STM8S103x 10 3 1 50 95 Figure 9 fcpumax versus Vpp fcpu MHz FUNCTIONALITY NOT GUARANTEED IN THIS AREA 16 KA _ FUNETIONALITY _ _ GUARANTEED TA 40 to 125 8 ues l 22 2 l l A M oO pens Sse pete 0 l l SUPPLY VOLTAGE V Table 20 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 2 oo Wee us V Vpp fall time rate 2 oo Reset release D tremp delay Vpp rising 1 7 ms Power on reset Vira threshold 2 6 2 7 2 85 Brown out reset VIT threshold 2 5 2 65 2 8 Brown out reset VHYS BOR hysteresis Q mV 1 Reset is always generated after a treyp delay The application must ensure that Vpp is still above the minimum ooperating voltage Vpp
69. ister 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 id SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF 0x00 5208 to Reserved area 8 bytes 0x00 520F 0x00 5210 GC CR1 I2C control register 1 Ox00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 IOC FREQR Ic frequency register 0x00 0x00 5213 Il2C OARL DC Own address register low 0x00 0x00 5214 I2C OARH DC Own address register high Ox00 0x00 5215 Reserved 0x00 5216 GC DR DC data register 0x00 0x00 5217 lc DC SR1 DC status register 1 0x00 0x00 5218 IOC SR2 DC status register 2 0x00 0x00 5219 l2C SR3 I2C status register 3 OxOx 0x00 521A I2C ITR Ic interrupt control register 0x00 0x00 521B I2C CCRL DC Clock control register low 0x00 0x00 521C I2C CCRH DC Clock control register high 0x00 0x00 521D l2C TRISER DC TRISE register 0x02 0x00 521E l2C PECH DC packet error checking register 0x00 0x00 521F to Reserved area 17 bytes 0x00 522F 15441 Rev 3 33 95 Memory and register map STM8S103x Table 8 General hardware register map continued Address Block Register label Register name kaaya 0x00 5230 UART1 SR UART status register COh 0x00 5231 UART1 DR UART1 data register xxh 0x00
70. l device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 27 external interrupts on six vectors including TLI Trap and reset interrupts 15441 Rev 3 13 95 Product overview STM8S103x 4 4 14 95 Flash program and data EEPROM memory e 8Kbytes of Flash program single voltage Flash memory e 640 bytes true data EEPROM User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key s
71. l to the value indicated mean x 2 X Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7 Figure 7 Pin loading conditions STM8 PIN 50pF 15441 Rev 3 ky STM8S103x Electrical characteristics 10 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8 Figure 8 Pin input voltage STM8 PIN 10 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 16 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage 0 3 6 5 Input voltage on true open drain pins Vss 0 3 6 5 V Vin Input voltage on any other pin Vss 0 3 Vpp 0 3 IVppx Vpp Variations between different power pins 50 T IVssx Vss Variations between all the different ground pins 50 see Absolute maximum VEsp Electrostatic discharge voltage ratings electrical sensitivity on page 81 1 All power Vpp and ground Vss pins must
72. ne pitch quad flat no lead package outline 3x 3 87 Figure 48 Recommended footprint for on board emulation 0 00 eee ee 88 ky 15441 Rev3 7 95 List of figures STM8S103x Figure 49 Recommended footprint without on board emulation aaa 88 Figure 50 STM8S103x access line ordering information scheme 91 8 95 15441 Rev 3 ky STM8S103x Introduction 1 Introduction This datasheet contains the description of the STM8S103x access line features pinout electrical characteristics mechanical data and ordering information e Forcomplete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e Forinformation on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 e Forinformation on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e Forinformation on the STM8 core please refer to the STM8 CPU programming manual PM0044 ky 15441 Rev 3 9 95 Description STM8S103x 2 Description The STM8S103x access line 8 bit microcontrollers offer 8 Kbytes Flash program memory plus integrated true data EEPROM The STM8S microcontroller family reference manual RM0016 refers to devices in this family as low density They provide the follo
73. on 15441 Rev 3 25 95 Pinout and pin description STM8S103x Table 6 STM8S103F pin description Pin no Input Output c Alternate al gt 29 function ala F Sioa 3 g 9 Defaultalternate after lz Pin name Sle El 9 3 ol Zig a all 2 a a z5 function remap HE E sia oja SS option PIS Re B EN i Timer 2 channel 1 18 Mo 1 O X X X HS O3 X X Port D4 1 BEEP output ES UART1 clock Analog input 5 2 19 PD5 AIN5 UART1_TX 1 O X X X HS O3 X X Port D5 UART1 data transmit Analog input 6 3 20 PD6 AIN6 UART1_RX I O X X X HS 1 O3 X X Port D6 UART1 data receive 4 1 NRST y o X Reset 5 2 PA1 OSCINO Vo X x x 01 x X Port A1 Resonator crystal 6 3 PA2 OSCOUT vu x x x O1 X X Port az Resonaforforystal 7 4 Vss Digital ground 8 5 VCAP 1 8 V regulator capacitor 9 6 Vpp s Digital power supply SPI master 10 7 Paa TIS Blas O X X X HS O03 X X Port A3 Timer 2 channel 3 slave SPI NSS select AFR1 Timer 1 PB5 I2C SDA 3 2 break 111 8 TIM1 BKIN 1 O X X O1 T Port B5 C data input AFR4 ADC 12 9 PBA I2C SCL vo x X 01 T Port B4 C clock vidi AFR4 Top level interrupt AFR3 13 19 POSTIMI CASIO ig x x x Hs os x x Portes Timert channel Iri ers TIM1 CHIN 3 inverted channel 1 AFR7 26
74. ontrol timer 17 4 11 TIM2 16 bit general purpose mer 17 4 12 TIM4 8 bitbasictimer 00 eee 18 4 13 Analog to digital converter DCH 18 4 14 Communication interfaces esee 18 KI UARTI 4 ette ck un e be eo Ea ex P RR OR Sie a aaa be 19 BVA OP r a a r R a ated a ka 19 APA 20 5 Pinout and pin description 2 a 21 5 1 Alternate function remapping enn 28 6 Memory and register map eee 29 6 1 Memory Map cic cc ks asal eu seb atu ace te eee bd ei waa Kae bees 29 6 2 Hegister Map sit kbduakk dair HAR Hg ites S400 RES KEAN Fed 30 7 Interrupt vector Mapping 40 2 95 15441 Rev3 ky STM8S103x Contents 8 Optloit BYTES 1 214 a i ec aD Ct CR de Re cl a a 41 9 Unique ID 404kmh uox x EUER eaten does RH eU KG vsa ERROR A NOE ncn 45 10 Electrical characteristics aaa 46 10 1 Parameter conditions eee 46 10 1 1 Minimum and maximum values skaka kaa aaa 46 10 1 2 Typical valdes eres 46 10 1 9 Typical curves iocur RR ERR RR RR RN ANNER E ER LEIG EN 46 10 1 4 Loading capacitor ren 46 10 5 Pininput voltage cele ERR RR PRE EL xu DINAMA REEL 47 10 2 Absolute maximum ratings 47 10 3 Operating conditions usarse xpo e d rece doe e Rei ace AR aca Rie icd 49 10 3 1 VCAP external capacitor 50 10 3 2 Supply current characteristics 51 10 3 3 External clock sources and timing characteristics
75. oo Mel lo MA Figure 33 Typ Vpp Von Vpp 5 V high sink ports 24 40C 25 C 85 C 125 C Voo VoH V Figure 34 Typ Vpp Vou Vpp 3 3 V high sink ports Geer 4C m 25 C 85 C 125 C 25 lo mA 15441 Rev 3 STM8S103x Electrical characteristics 10 3 7 d Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 42 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vit nrst NRST Input low level voltage 1 0 3 V 0 3 x Vpp 1 1 0 7 x Vpp Vin wrst NRST Input high level voltage ger 0 3 V VornRsT NRST Output low level voltage 1 lo 2 MA 0 5 Reuwrst NRST Pull up resistor 30 40 60 kQ Hepupen NRST Input filtered pulse 9 75 ns tinrp nrst NRST Input not filtered pulse 3 500 ns toP NRST NRST output pulse 3 20 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 35 Typical NRST Vj and Vj vs Vpp 4 temperatu
76. ote AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin One model can be simulated Human body model This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 50 ESD absolute maximum ratings Symbol Ratings Conditions Class aie Unit V Electrostatic discharge voltage TA 25 C conforming to A 4000 ESD HBM Human body model JESD22 A114 V Electrostatic discharge voltage TAL QFP32 package VESD CDM K 25 C conforming to IV 1000 Charge device model SD22 C101 1 Data based on characterization results not tested in production 15441 Rev 3 81 95 Electrical characteristics STM8S103x 82 95 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 51 Electrical sensitivities Symbol Parameter Conditions Class Ty 25 C A LU Static latch up cla
77. overage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 15441 Rev 3 ky STM8S103x STM8 development tools 13 2 Software tools STMB8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code 13 2 1 STM8 toolset STMB8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST Visual Develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax h
78. r restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM2 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM3 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 DC PCKEN24 Reserved PCKEN20 Reserved ky 15441 Rev 3 15 95 Product overview STM8S103x 4 6 4 7 16 95 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with
79. res 40 C 6 o 25 C 5 85 C 125 C 4 z 33 gt R 2 1 0 T r 7 7 T 7 1 25 3 35 4 45 5 5 5 6 Wor VI Figure 36 Typical NRST pull up resistance vs Vpp 4 temperatures 0 C 60 25 C 85 C e 125 C 2 tri as 2 45 4 aata E 40 35 30 T T T T T T 1 2 5 3 3 5 4 45 5 55 6 Voo V 15441 Rev 3 71 95 Electrical characteristics STM8S103x 72 95 Figure 37 Typical NRST pull up current vs Vpp 4 temperatures 120 100 60 40 C 25 C NRESET Pull Up current p 85 C 20 2 125 C 3 WO The reset network shown in Figure 38 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in Table 38 Otherwise the reset is not taken into account internally Figure 38 Recommended reset pin protection Vpp STM8 Rpy External NRST Internal reset reset e Filter circuit 0 01 pF optional 15441 Rev 3 ky STM8S103x Electrical characteristics 10 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 43 are derived from tests performed under ambient temperature faster frequency and Vpp supply voltage conditions tMASTER 1 MASTER Refer to I O por
80. s the maximum power dissipation on output pins Where Pyomax No lol 2 Vpp Von Ton taking into account the actual Ve Jo and Vou log of the I Os at low and high level in the application Table 56 Thermal characteristics Symbol Parameter Value Unit CH ee degen junction ambient 60 C W De EE E 22 C W Gn lods dnd junction ambient 84 C W Gia a se Un Een 90 C W 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment 11 2 1 Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org ky 15441 Rev 3 89 95 Package characteristics STM8S103x 11 2 2 90 95 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 12 Ordering information on page 91 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions e Maximum ambient temperature Tamaxz 75 C measured according to JESD51 2 e IpDmax 8 mA Vpp 25V e Maximum 20 l Os used at the same time in output at low level with lot 8 mA VoL 0 4 V PiNTmax 8 mA x 5 V 400 mW Piomax 20 X 8 MA x 0 4 V 64 mW This gives Pintmax 400 mW and Piomax 64 mW PDmax 400 mW 64 mW Thus Ppmax 464 mW Using the values obtaine
81. ss Ta 85 C A Ta 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard 15441 Rev3 ky STM8S103x Package characteristics 11 Package characteristics To meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 15441 Rev 3 83 95 Package characteristics STM8S103x 11 1 11 1 1 84 95 Package mechanical data LQFP package mechanical data Figure 44 32 pin low profile quad flat package 7 x 7 32 D1 D3 24 Pin 1 identification 1 C coo C ES E1 E ag Sh ON ez 5V_ME Table 52 32 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D
82. such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks
83. t characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 43 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 8 SCK SPI clock frequency S MHz Losch Slave mode 0 7 hann SPI clock rise and fall time Capacitive load C 30 pF 25 f SCK tsuNss NSS setup time Slave mode 4 X tMASTER wee NSS hold time Slave mode 70 3 IwSCKH SCK high and low time Master mode tsck 2 15 tsck 2 15 tw SCKL t 3 Master mode 5 su MI 3 Data input setup time tsu S1 Slave mode 5 t 3 Master mode 7 ns n Ml 5 Data input hold time thsi Slave mode 10 taso V Data output access time Slave mode 3 X MASTER tais soy Data output disable ime Slave mode 25 tuso Data output valid time Slave mode after enable edge 650 tymo Data output valid time Master mode after enable edge 30 tirso Slave mode after enable edge 27 pa Data output hold time mo Master mode after enable edge 112 1 Parameters are given by selecting 10 MHz UO output frequency 2 Data characterization in progress 3 Values based on design simulation and or characterization results and not tested in production 4 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 5 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z d 15
84. tection register 0x00 0x00 505E FLASH NFPR Flash complementary protection OxFF register 0x00 505F FLASH IAPSR Flash in application programming 0x00 status register 0x00 5060 to Reserved area 2 bytes 0x00 5061 0x00 5062 Flash FLASH_pukr_ Flash program memory unprotection ep register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065 to Reserved area 59 bytes 0x00 509F 0x00 50A0 WE EXTI CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI CR2 External interrupt control register 2 0x00 0x00 50A2 to Reserved area 17 bytes 0x00 50B2 0x00 50B3 RST RST SR Reset status register XX 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50CO Pise CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte ky 15441 Rev 3 31 95 Memory and register map STM8S103x 32 95 Table 8 General hardware register map continued Address Block Register label Register name aaa status 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register piang 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 Peripheral clock gating register 1 OxFF
85. ter 8 OxFF 0x00 7F78 to Reserved area 2 bytes 0x00 7F79 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to Reserved area 15 bytes 0x00 7F8F 38 95 15441 Rev 3 D STM8S103x Memory and register map d Table 9 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name Wee 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF 0x00 7F9B to Reserved area 5 bytes 0x00 7F9F 1 Accessible by debug module only 15441 Rev 3 39 95 Interrupt vector mapping STM8S103x 7 Interrupt vector mapping Table 10 Interrupt mapping Due Description aem Makeup rom Vec
86. tor address RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes veel 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 Reserved 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIMI a E R 0x00 8034 12 TIM1 TIM1 capture compare 0x00 8038 13 TIM2 TIM2 update overflow 0x00 803C 14 TIM2 TIM2 capture compare 0x00 8040 15 Reserved 0x00 8044 16 Reserved 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19 Se I2C interrupt Yes Yes 0x00 8054 20 Reserved 0x00 8058 21 Reserved 0x00 805C leet iii 000 s60 23 TIM4 TIM4 update overflow 0x00 8064 24 Flash EOP WR PG DIS 0x00 8068 Bagaman 0x00 806C to 0x00 807C 1 Except PA1 40 95 15441 Rev 3 Si STM8S103x Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a
87. u fMAsTER 128 kHz LSI RC osc 128 kHz 0 41 0 55 IDD RUN i HSE crystal osc 16 MHz 4 5 mA CPU IMASTER 16 MHz HSE user ext clock 16 MHz 4 3 4 75 HSI RC osc 16 MHz 3 7 4 5 Supply eu IMASTER HSI RC osc 16 MHz 8 2 0 84 1 05 current in run 2 MHz mode code f f 128 executed from CPU MASTER 9 HSI RC osc 16 MHz 0 72 0 9 125 kHz Flash foru fmasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcpu MASTER 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off d 15441 Rev 3 51 95 Electrical characteristics STM8S103x Table 22 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 8 UL ere HSE user ext clock 16 MHz 2 2 3 Supply HSI RC osc 16 MHz 1 5 2 current in run fopuy fyasteR 128 125 HSE user ext clock 16 MHz 0 81 de cod e HSI RC osc 16 MHz 0 7 0 87 from RAM UE MASTER 128 HSI RC osc 16 MHz 8 0 46 0 58 UC ARMES LSI RC osc 128 kHz 0 41 0 55 IDD RUN HSE crystal osc 16 MHz 4 mA EEN 7 HSE user ext clock 16 MHz 3 9 4 7 HSI RC osc 16 MHz 3 7 4 5 ee a D MSIE HSI RC ose 16 MHz 8 2 084 1 05 mode code executed cry ImasTER 128 125 ioi RC osc 16 MHz 072 09 from Flash fopu
88. ured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code c
89. urrent 210 Ippcimz TIM2 supply current 130 IDD TIM4 TIM4 timer supply current 50 Ipo uanri UART1 supply current 120 UA Ippsey SPI supply current 45 Ipp i c I C supply current 65 IDD ADC1 ADC1 supply current when converting 1000 56 95 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production Data based on a differential Ipp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Not tested in production 15441 Rev 3 d STM8S103x Electrical characteristics d Current consumption curves Figure 11 to Figure 16 show typical current consumption measured with code executing in RAM Figure 11 Typ Ipp nuw VS Vpp HSE user external clock fcpy 16 MHz IDD run HSE mA 23 2 25 N h N a N N Q a N to a to E a eo 25 C 85 C 125 C Aer 2 25 3 35 4 45 5 55 6 Voo V Figure 12 Typ Ipp nuw VS fcpu HSE user external clock Vpp 5 V 25 C 85 C 125 C 25 245 C 2 1
90. vide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family ky 15441 Rev 3 93 95 Revision history STM8S103x 14 94 95 Revision history Table 57 Document revision history Date 02 Mar 2009 Revision 1 Changes Initial revision 10 Apr 2009 Added Table 2 on page 15 Updated Section 4 8 Auto wakeup counter on page 17 Modified description of PB4 and PB5 removed X in PP column and added footnote concerning HS I Os in Table 5 and Table 6 Removed TIM3 and UART from Table 10 Interrupt mapping Updated VCAP specifications in Section 10 3 1 on page 50 Corrected block size in Table 37 Flash program memory data EEPROM memory Updated Section 10 Electrical characteristics Updated Table 56 Thermal characteristics 10 Jun 2009 Document status changed from preliminary data to datasheet Replaced WFQFPN20 package with UFQFPN package Replaced VFQFN with VFQFPN Added bullet point on the unique identifier to Features on page 1 Updated Section 4 8 Auto wakeup counter on page 17 Updated wpu and PP status of PB5 12C_SDA and PB4 12C SCL pins in Table 5 and Table 6 Removed Table 7 Pin to pin comparison of pin 7 to 12 in 32 pin access line devices
91. wing benefits e Reduced system cost Integrated true data EEPROM for up to 300 k write erase cycles A High system integration level with internal clock oscillators watchdog and brown out reset e Performance and robustness 16 MHz CPU clock frequency Robust I O independent watchdogs with separate clock source Clock security system e Full documentation and a wide choice of development tools e Advanced core and peripherals made in a state of the art technology Table 1 STM8S103xx access line features i o 3 o v 252 2 F a a E o E O Sl c c o E S a c El so gt V 2 T Ei 5 a C o o 2 e A 5 32 5 ox ox cEQ 2 Device 8 SQ EO Eg E sft 9 Peripheral set c a S v G 298 o oz Q E Fa 2 Z e os Lu lt q Ki o E o gt J 2 ul a o L al t c e mE ela g 5 z E o M E lt L Multipurpose timer TIM1 SPI CG UART STM8S103K3 32 28 27 7 3 4 21 8K 640 1K window WDG STM8S103F3 20 16 16 7 0 5 12 8K 640 1K independent WDG STM8S103F2 20 16 16 7 0 5 12 4K 6407 1K ADC PWM timer TIM2 8 bit timer TIM4 1 Noread while write RWW capability 10 95 15441 Rev 3 KY STM8S103x Block diagram 3 d Block diagram Figure 1 Block diagram
92. with code execution in run mode at Vpp 2 3 8V 52 Table 23 Total current consumption in wait mode at Vpp 5V lll lkk kkk kaka 53 Table 24 Total current consumption in wait mode at Vpp 3 3V lakka kakak a 58 Table 25 Total current consumption in active halt mode at Vpp 5 V a 54 Table 26 Total current consumption in active halt mode at Vpp z 332N a 54 Table 27 Total current consumption in halt mode at Vpp 2 DM 55 Table 28 Total current consumption in halt mode at Vpp 3 3 V 11 122 a 55 Table29 WakeuptimeS lh ren 55 Table 30 Total current consumption and timing in forced reset state 56 Table 31 Peripheral current consumption en 56 Table 32 HSE user external clock characteristics liliis 60 Table 33 HSE oscillator characteristics liliis 61 Table 34 HSI oscillator characteristics liliis nee 62 Table 35 LSI oscillator characteristics liiis 63 Table 36 RAM and hardware registers en 64 Table 37 Flash program memory data EEPROM memory nua akka 64 Table 38 I O static characteristics sasa aaa kakak akka aaa a 65 Table 39 Output driving current standard ports sss aaa eee 67 Table 40 Output driving current true open drain ports sasa kakak ana 67 Table 41 Output driving current high sink porte 67 Table 42 NRST pin characteristics 2 2sssa sasa kakak aaa

Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data

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