the ccd-controller systems - INAF -Astronomical Observatory of Padova
Contents
1. F N C H Sensors 1 2 3 4 V Common K Heater Resistor J N C L Heater Resistor Oxford Temperatures Connector Site 1k x 1k2. Tab 1 Power Supply Board Parameters Technical Report N 15 The CCD Camera Controller at the 182 cm 2 2 Sequencer The Sequencer board is a double eurocard form factors 6U size B 160 X 234 mm The board acts as motherboard for four standard TRAM service slots two of them are used to mount permanently two piggy back modules the DTM560 and the SMT227 boards the other two slots are for service purposes The DTM560 module is the heart of the Sequencer and it was purchased from Perimos Germany It is a standard TRAM module which contains two high speed processors a 16 bit T222 20 MHz transputer and a 24 bit 56001 MOTOROLA DSP 20MHz The transputer and DSP communicate by means of a shared memory The SMT227 from Sundance or PST207 TRAM module from Paratech is a standard TRAM fibre optic link module which provides the link between the CCD controller and the CCDVME host computer Besides these two commercial parts the Sequencer contains all the electronic circuits needed to support functions that are not directly involved with the readout of the CCD chip such as temperature control and setting shutter curtain or iris control external synchronization circuit and address decoder circuits for the Motorola DSP The functions of the Transputer are data commands and telemetry handling bias and clock voltages programming and communication with the host computer via fibre optic link The Motorola DSP 20MHz 56001 DSP is used as timing gen
3. Contr J1 Amphenol Clocks 55 pin Cryo conn Clock 1 A Serial clocks 2 a amp d amplifiers 4V 9V Clock 2 A Serial clocks 2 b amp c amplifiers 4V 9V RTN 1 S3ad Clock 3 A Serial clocks 3 a amp d amplifiers 4V 9V S3bc Clock 4 A Serial clocks 3 b amp c amplifiers 4V 9V Slabed 5 Serial clocks 1 a amp b amp c amp d amplifiers 4V 9V Swabcd Clock6A Summing Well clocks a amp b amp c amp d amplifiers 4V 9 6V RTN 2 RGabcd Clock 7A Reset Gate clocks a amp b amp c amp d amplifiers 0V 12V Clock 8 A P1Uab Clock9A Parallel clock 1 Upper Quadrant 9 0V 4 0V P2Uab 10 Parallel clock 2 Upper Quadrant 9 0V 4 0V P3Uabed Clock 11 A Parallel clock 3 Common Upper amp Lower Quadrants 9 0V 4 0V TGULabcd Clock 12 A Transfer Gate clock Common Upper amp lower Quadrants 9 0V 7V Clock 13 A Parallel clock 1 Lower Quadrant 9 0V 4 0V Common Shield DD CC H D E F G H J K L M N P R S T U W X ie P2Lbc Clock 15 A Parallel clock 2 Lower Quadrant 9 0V 4 0V RTN 7 NK 13 Technical Report N 15 The CCD Camera Controller at the 182 cm Instrument Contr J2 VidBias Crio Site 1K x 1K Afosc Controller J2 connector Connector Type 1 62GB 56T 16 32 S Amphenol 55 pin Cryo conn PO SS e i Tere Pin lt AA AA CCD PCB VRDa b c d VDDa b c d Function Bias 1 Bias 4 VLG
4. 30 31 32 33 34 35 36 37 38 39 40 4 File Ctablesisiten sxrwt seg Table Id Date 13 09 1999 FHO S2AD FH1 S2BC FH2 S3AD FH3 S3BC FH4 S1ABCD FHb SW FH6 RG FH FH8 FH9 HAUX 11 12 13 STC CIF Comments SITE 1Kx1K SLOW SCAN RIGTH HORIZONTAL READOUT TABLE outputs b amp c Grid Step 10 11 Technical Report N 15 The CCD Camera Controller at the 182 cm 4111111 Pt vab ee P3Uabed sn LLLI AM STB rem i fii ttt lstes o TE Tus IT CEECEEEEECEEEELE arm FEE EEE EEE a 12345 6 7 8 9 10111213 1415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 File CAtablesisiterMydwt seq Table Id 1 Date 13 07 1999 Comments SITE 1Kx1K VERTICAL SCAN DOWN WAVEFORM TABLE OUTPUT c and Grid Step 25 Tr s i P2Uab MU P3Uabcdc ERESDIDIDILIDE 1 11 dli LLLELLLI Pit tT tT TT oT eae STB LineClp NUI NU2 12343557 8 9 1011121314 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39140 File CAtablesisitenifyuwt seq Table Id 2 Date 13 0 7 1999 Comments SITE 1Kx1K VERTICAL SCAN UP WAVEFORM TABLE OUTPUT a and b Grid Step 25 12 Technical Report N 15 The CCD Camera Controller at the 182 cm Appendix b Crio Site 1K x 1K cabling Coste es ik Ato O Crio Site 1K x 1K Afosc eteri 62GB 56T 16 26 5
5. ISSN 1594 1906 Padova and Asiago Observatories THE CCD CAMERA CONTROLLER AT THE 182 CM D Alessandro M Fantinel D Giro E Technical Report n 15 August 2001 Document available at http www pd astro it Vicolo dell Osservatorio 5 35122 Padova Tel 390498293411 Fax 390418759840 This page is left intentionally blank Technical Report N 15 The CCD Camera Controller at the 182 cm 1 Introduction The CCD camera controller has been designed and built by the CCDWG CCD Working Group for the scientific Optical Imager Low Resolution Spectrograph High Resolution Spectrograph and the service cameras Guide camera Shack Hartmann camera of the Telescopio Nazionale Galileo TNG In the past years a complete upgrade of the Asiago Telescope Instrumentation was planned especially related to the CCD camera Controller CCD Chip Cryogenic Dewar and Software In this framework the CCD camera controller designed and built for the TNG was adopted for the AFOSC Asiago Faint Object Spectrograph and Camera instrument The next sections will give an overview of the main features of the controller and of the CCD chip Moreover a brief description the mechanical arrangement of the cryogenic system Dewar will be reported The complete system mounted at the telescope is depicted in Preamp Box Fig 1 The AFOSC instrument the cryogenic dewar and the CCD controller mounted at The Telescope Technical Report N 15 T
6. a b c d Bias 6 Video pos Video neg Video 2 pos Video 2 neg Comm Video Shield Video 3 pos Video 3 neg Video 4 pos Video 4 neg 20V 20V Comm Bias Shield 30V_RET LineClamp GAIN 20V RET Spare 14 Reset Drain Voltage Out Drain voltage Las Gate Voltage Twisted pairs Twisted pairs Twisted pairs Twisted pairs Twisted pairs Twisted pairs Twisted pairs Twisted pairs Comment 15 7 Volts 25 5Volts 3 9Volts CCD Output A 20KQ load CCD Output 20KQ load CCD Output 20KQ load CCD Output D 20KQ load Sheet 1 of 1 Technical Report N 15 The CCD Camera Controller at the 182 Crio Site 1K x 1K Afosc Controller J3 connector Connector Type 1 62GB 56T 16 26 5 Temperatures Cryo Connector TMP 1 CCD Temperature Sensor 53 TMP 2 Crio Wall Temperature Sensor 52 TMP 3 LN2 Temperature Sensor 54 TMP 4 TMP 5 TMP 6 CCD Temperature Control Sensor S1 5V REF Common Voltage for Temperature Sensors Heather 1 Temperature Control Resistor Heather 2 Temperature Control Resistor ENACLK DISCLK SHUTTER 1 OUT SHUTTER 2 OUT SHUT A SHUT B V SHUT Peltier pos Peltier neg Pin A B C D E F G H J K L M P R S U W X Z b C 15 Technical Report N 15 The CCD Camera Controller at the 182 cm A Sensor SI regulator Sensor S2 Crio Wall Temperature Sensor S3 CCD Temp D Sensor S4 LN2 Temperature E
7. and the generation of the local power supply from three main voltages 32V 20V Site 1k x 1k CCD Gye 4 m si ont CCD Support structure bottom 27 Fig 7a 7b Support structure for the CCD 4 CCD Chip The CCD chip currently mounted at the AFOSC instrument is an SI 003AB from Site Inc USA Thinned Back Illuminated MPP Serial number 7405GBR05 A1 VisAR Coat The device specifications are the following Format 1024 1024 pixels Pixel Size 24 um 24 um Imaging Area 24 6 mm 24 6 mm Dark Current 15C 28 e pixel sec MPP Readout Noise 5 e RMS Full Well 350K e Output gain Amp B 1 2 uV e Parallel CTE Amp B 0 999999 Serial CTE Amp B 0 999996 The chip has four outputs that are located in each corner of the device at the ends of the serial registers Fig 8 presents a schematic view of the CCD chip configuration The 51 003 chip can be operated with one two three or four outputs simultaneously In our case we use only the B output amplifier The time required to read the full image from one amplifier is about Technical Report N 15 The CCD Camera Controller at the 182 cm Dama n O oil i fi 14 Fig 8 51 003 functional diagram 50 seconds 40usec per pixel and 100usec per line if we need to read images at higher rate it is possible to define a small area of the chip centred on the reference object for example with a sub area window of 128 by 128 pixels the r
8. e cryogenic Dewar the Dewar and the controller are connected by means of three cables each of them carrying different signals e Video and Bias Cable e Clocks Cable e Shutter and Temperature Cable Controller Housing Til T CDS amp Power supply Sequencer Board VME Backplanes Fig 2 CCD Controller Housing This kind of arrangement has been chosen to avoid electromagnetic interferences between the video lines and the other signals clocks temperature shutter control signals A complete list of the connectors pin out is reported in Appendix B Technical Report N 15 The CCD Camera Controller at the 182 cm Front panel ne Roue Fn F L gt da bre Inc cz s w I ix pa LJ Clocks 1d Bias mie i MH bat acres per ren pe ea m Cooling Fan Fiber Optic Link Connectors Fig 3 CCD Controller Housing front and rear panels Inside the controller housing are located the power supply board PSB the transformer and the bridge rectifiers The PSB provides all the voltages and currents needed to operate the CCD controller in a quad readout configuration four outputs of one CCD or four CCDs with one output All voltage supplies are linear and optimized for efficiency and reliability Fab 1 summarizes the main parameters of the power supply board Analog GND AGND Digital GND DGND Temp GND TGND oT
9. eadout time goes down to 15 This way of reading the chip gives the optimal combination of a relatively fast frame rate while allowing long pixel time inside the sub area to minimize the read out noise Correlated Double Sampling technique for each pixel The working bias and clock voltages are reported in The chip is liquid Nitrogen cooled at about 100 C as described in the previous section The Site SI 003A is thinned back illuminated CCD with VisAr coating that provides superior quantum efficiency as reported in In Appendix A are reported the waveforms used to read the chip CCD CDS Name Funetion Volages V VDD OUT4 Output Drain Voltage 907 VOD OUTI Reset Drain Voltage IS VOG OUT6 Output Gate Voltage fo SS GE VSUB AGND Substrate Voltage AGD VOS a b c d VIDX 1 2 3 4 Video output line 20KO Lod Clocks Voltages CCD Name Seq CDS Name Function Serial Clock 2 Amp a amp d Serial Clock 2 Amp b amp c Serial Clock 3 Amp b amp c Serial Clock 3 Amp b amp c Serial Clock 1 Amp a amp b amp c amp d Summing well Amp a amp b amp c amp d 00 20 90 0 90 1 0 l Parallel 3 Clock Amp a amp b amp e amp d 5 0 0 90 90 90 P1Uab Clk9 Parallel 1 Clock Amp a amp b RGabcd Clk7 Reset Gate Amp a amp b amp c amp d P2Uab Clk10 Parallel 2 Clock Amp a amp b TGULabcd Clk12 Transfer Gate Clock Amp a amp b amp c amp d P1Lcd Clk13 Parallel 1 Clock Amp c amp d P2Lcd CIk15 Parallel 2 Cloc
10. erator to read the CCD chip and to control the auxiliary functions related to the CCD operations exposure time shutter and temperature The list below summarizes the main features of the Sequencer board 16 Digital outputs for pixel processing i e CCD serial clocks clamp hold start conv etc 12 Digital outputs for CCD parallel clocks and line clamp Software programmable Temperature control D A and A D converters Shutter control Iris and Curtain shutters Sequencer built around Motorola DSP56000 1 Time resolution 100nanosecs Data handling and commands interface by means of Transputer T222 2 3 Analog Electronics CDS The CDS Correlated Double Sampling board is a double eurocard form factors 6U size B 160 X 234 mm like the Sequencer The function of this board is to sample to filter and to convert each pixel of the CCD chip The main parts of the analog processing circuit are the differential input amplifier the integrator amplifier integrate hold and reset and the Analog to Digital Converter 16 Bit resolution The A D converter is also used for the telemetry In addition the generation of the Mos level for the CCD clock and the bias voltages are located inside this board 8 12 Bit resolution The main features of the CDS are the following x differential video channels with correlated double sampling CDS x 16 bits resolution ADCs Crystal CS5101 used for Data and Telemetry x 18 bits resolution DACS for video channel o
11. ff set 8 Software programmable bias voltages with 12 Bits resolution 8 Buffered Serial clocks with software programmable low and high levels with 8 Bits resolution 8 Buffered Parallel clocks with software programmable low and high levels with 8 Bits resolution The DC bias and the clock high and low voltage ranges are shown in Bias5 Bias8 Last Gate Output Gate Substrate of CCD 12 12 or general use DC Clock Voltage eee 8 Serial Clocks 10 10 CIK9 clk16 Parallel clocks 10 10 Tab 2 Voltage ranges Technical Report N 15 The CCD Camera Controller at the 182 cm 24 VMEACQ system is built around a standard 19inch rack which contains the VME back plane the power supply module and the hard disk drive The boards involved to CCD control are the following see CPU Eurocom 6 Master from Eltec Gmbh Germany TCD 101 Graphic boards from Eltec Gmbh Germany ATX290 Transputer Interface board VME VSB from Atenix Italy ATX630 32 Mbyte Memory board VME VSB from Atenix Italy The CPU Eurocom 6 controls all the functions of the It is equipped with a real time multi tasking Operating System PDOS and a software environment GATE developed by the TNG Software Group see GATE is modular environment that provides the overall control of the functions of the and of the communication with the other VME or Workstations The communication between the CPU and the ATX290 boa
12. he CCD Camera Controller at the 182 cm 2 The CCD Controller This section will describe the CCD camera s electronics primarily related to the following parts e CCD Camera Controller electronics CCDC e CCD VME Host computer CCDVME The CCDC controller consists of four main components Housing and Power Supply Board for the controller electronics Two electronic boards Analog board and Sequencer board Three Cables to connect the controller with the cryogenic system dewar Fibre link with the CCDVME host computer D ne 2 1 Controller Housing The Analog board named CDS and the Sequencer are housed in a standard 19inch metallic box The housing contains two five slots VME back plane P1 96 Pin Connectors 3 Rows x 32 Pins for accommodating the CDS and the Sequencer boards The signal and the power supply lines of the VME back plane have been redefined and their functions have been changed to fit with the functionalities needed by the CCD controller The data and the signals between the CDS and the Sequencer are exchanged through this bus Fig 2 shows the housing while Fig 3 shows the front and the rear panels of the controller housing Onto the front panel are located the connectors used to bond the controller with the Dewar containing the CCD chip The rear panel contains the Main Power Supply plug the ON OFF switch the cooling fan and the SMA connectors for the fibre optic link The CCD controller housing is located close to th
13. ium see the wires to from the PCB and the hermetically sealed connector of the Dewar UBK7 window MN SS SESS Meesde NR HE PA Fig 5 Front flange of the dewar with UBK window Fig 6 The PCB CCD chip for the Site chip Cooling is transferred from the nitrogen cold plate to the chip by means of a copper strap that is adjusted in length to hold the CCD temperature close to the working value A resistive heater keeps the chip to the wanted temperature under the control of the temperature control circuit of the Sequencer board The cold finger contains two temperature sensors AD590 the former is used to control the temperature temperature regulator the latter gives the working temperature of the CCD The preamplifier board is housed in a metallic box that is attached to the side of a cryogenic dewar as close as possible to the CCD chip The box is mounted on the dewar and contains a hole in the base plate for passing through the hermetically sealed circular connector Amphenol 55pin of the dewar Onto the preamplifier box are mounted two connectors to bond by means of two cables the preamplifier to the CCD controller see previous section The preamplifier contains four fully differential input stages The gain is adjustable via a resistors network Inside the 6 Technical Report N 15 The CCD Camera Controller at the 182 cm preamplifier board there are also the buffers to boost the bias voltages needed by the CCD
14. k Amp c amp d Tab 3 Site SI 003A CCD working parameters Technical Report N 15 The CCD Camera Controller at the 182 Quantum Efficiency ve Wavelength 42 room temp pt Ju i Fig 9 SI 003A Quantum Efficiency References Ref 1 User Manuals September 1999 Technical Report N 15 The CCD Camera Controller at the 182 cm Appendix A Waveform to read the Site CCD FH0 S2AD FH1 S2BC FH2 SSAD FH3 S3BC FH4 S1ABCD FH5 SW FH6 RG File CAtables siten fxlwt seq Table Id 5 Date 13 09 1999 Comments SITE 1Kx1K FAST SCAN left HORIZONTAL SHIFT NO READ WAVEFORM TABLE outputs a amp d Grid Step 10 123455789 1011121314 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4 File CAtablesisitenisxlwt seq Table Id 8 Date 13 09 1999 FH0 S2AD FH1 S2BC FH2 S3AD FH3 S3BC FH4 S1ABCD FH5 SW FH6 RG FH FH8 FH9 HAUX H 12 13 STC CIF Comments SITE 1 Kx1K SLOW SCAN LEFT HORIZONTAL READOUT TABLE Outputs a amp d Grid Step 10 10 Technical Report N 15 The CCD Camera Controller at the 182 cm File CAtables siten fxrvt seq Table Id 4 Date 13 09 1999 FHO S2AD FH1 S2BC FH2 S3AD FH3 S3BC FH4 S1ABCD FH5ISW FH6 RG FH8 FH9 HAUX 11 12 13 SIC CHF Comments SITE 1Kx1K FAST SCAN RIGTH HORIZONTAL SHIFT NO READ WAVEFORM TABLE Grid Step 10 123455789 1011121314 15 1617 18 19 2021 22 23 24 25 26 27 28 29
15. rd is done by means of Dual Port Ram DPR contained into the Atx290 all the commands and the telemetry are exchanged using this shared memory VME Bus The Data coming from the CCD controller via the fibre link are stored by the ATX 290 onto the ATX630 memory board using the VSB bus The TCD101 graphic board is dedicated to the Real Time display of the image coming from the CCD controller 8 bit depth 256 colours Other boards are inserted in the VMEACQ rack and are used for service operations of the telescope such as control of the telescope movements during the auto guide acquisition of the telescope coordinates Fig 4 The VMEACQ system Technical Report N 15 The CCD Camera Controller at the 182 cm 3 Cryogenic System and Preamplifier The CCD must be cooled thermoelectrically or cryogenically to reduce thermal dark current In our system the CCD chip is housed in an Oxford cryostat model MN1815 INV with liquid nitrogen tank capacities of 1 5 litres which assures 12 hour hold times The original front flange of this cryostat has been removed and a custom front flange containing a UBK7 window has been built to fit with the Afosc instrument mechanical and optical requirements see figure 5 Onto this front flange is mounted the CCD mechanical support which consists of four main parts the CCD Printed Circuit Board see an insulating material to hold the PCB and the cold finger glass epoxy see the cold finger alumin
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