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1. Multiple Outputs 10 100 1000Mbps to output Ethernet MAC GbE selection 7 RGMII GMI PHY TCP IP HDLC USB 2 0 Protocol to oi input AID Frequency PSK Viterbi Min l 7 ULPlinterface USB Tobis driver translation gt demod decoder 9 7 Elastic PHY 5 scrambler Buffer N Synchronous Serial interface Receiver Multiple Inputs from 10 100 1000Mbps input GbE Ethernet MAC selection RGMII GMII TCP IP i USB 2 0 Protocol rom i ugg ULP interface gt Elastic a Buffer v 35 FEC PSK Interpolation M Dual gt E scrambler 7 encoder modulator 7 Frequency gt DACs a HDLC translation drivers L Synchronous Serial interface Internal PRBS11 Test Sequence Generator Transmitter 14 Software Licensing The COM 1505SOFT is supplied under the following key licensing terms 1 A nonexclusive nontransferable license to use the VHDL source code internally and 2 An unlimited royalty free nonexclusive transferable license to make and use products incorporating the licensed materials solely in bitstream format on a worldwide basis The complete VHDL IP Software License Agreement can be downloaded from http www comblock com download softwarelicense pdf Configuration Management The current software revision is 2 Device Utilization Summary Device Xilinx Spartan 6 Reg2. li MAE RU TNT I TA 1000 NS V ADIP AEB RU 800 500 TEM AW TUM II 1500 t x10 receiverl vhd input I channel blue after internal AGC normalization magenta 1000 500 500 Real NI 188 1 89 19 191 192 193 194 x 10 receiverl vhd after internal AGC normalization magenta bias removal red and frequency translation to baseband green ideal case no bias no frequency error 1000 1000 F 2000 3000 4000 5000 6000 1 445 145 1455 1 46 1 465 147 1475 148 1485 x 10 receiverl vhd baseband input case after frequency translation to baseband green CIC decimation blue and half band filter magenta 1000 iul nil ME hi n 1000 li i i 2000 3000 4000 8 36 8 865 837 8 375 8 38 8 385 8 39 x 10 receiver vhd illustrating frequency translation from IF input to baseband after frequency translation to baseband green CIC decimation blue and half band filter magenta psk_demod vhd after phase correction blue resampling at 4 samples symbol magenta half band low pass filtering red 18 1500 p 1000 e 500 500 amp 1000 4500 7 et O 200 400 600 800 1000 1200 1400 1600 1800 2000 psk demod2 vhd after root raised cosine filter subsampled at 1 sample per symbol center of the eye diagram Shows the symbol t
3. TX DATA IN N j X X to modem best time for user FPGA to send a tx data bit reads data at rising edge In the transmit direction the user provides serial data TX DATA IN preferably at the falling edge of the modem supplied CLK IN The TX DATA IN is read at the rising edge of CLK_IN The user MUST provide data otherwise an underflow condition will occur Option C is for continuous mode operation No gap in data 11 transmission is allowed TCP IP A option The transmit and receive data streams can also be transferred over a TCP IP network connection This requires an additional Ethernet PHY with standard RGMII or GMII interface a COM 5102 plug in Ethernet adapter for example In this case the modem acts as a TCP server waiting for connection from a remote client at port 1024 A unique IP address and a unique MAC address must be assigned to the modem see control registers REG41 through REG50 The TCP IP protocol guarantees that no overflow will occur in the user to modem direction The built in flow control mechanism of the TCP IP will prevent the user application from writing more data than the modem can handle for the specified data rate In the receiver to user direction however it is the user s responsibility to read data as fast as possible to prevent an overflow condition from occurring at the receiver The TCP bytes are sent received serially most significant b
4. clock as DAC sampling clock fak tx 20 bit unsigned integer expressed as fa tx 27 300MHz 120 MHz maximum 20 MHz recommended minimum REGO bits 7 0 LSB REGI bits 15 8 MSB REG2 3 0 bits 19 16 MSB Internal External frequency reference 0 internal Use the internal 60 MHz clock from the USB PHY as frequency reference 1 external Use the 10 MHz clock externally supplied through the J7 SMA connector as frequency reference REG2 7 Symbol rate fsymbol rate tx The modulator symbol rate is in the form Lua ratetx lclk tx 2 where n ranges from 1 fak tx is twice the symbol rate to 15 symbol rate fak tx 65536 n is defined in REG3 3 0 Output Center frequency feou Frequency translation 32 bit signed integer 2 s complement representation expressed as oout 27 clk tx REGS bits 7 0 LSB REG bits 15 8 REG1O bits 23 16 REGI1 bits 31 23 MSB Modulation type 0 BPSK 1 QPSK 2 OQPSK REG4 5 0 Spectrum inversion Invert Q bit This is helpful in compensating any frequency spectrum inversion occurring in a subsequent RF frequency translation 0 off l on REG4 6 Input bit rate Option C only Set the nominal input bit rate in order to generate a regular bit clock to the data source Must be consistent with the modulator symbol rate modulation type and FEC rate Example 2 M
5. Com Block COM 1505SOFT INTEGRATED PSK MODEM VHDL source code overview IP core Overview The COM 1505SOFT is a complete PSK modem written in VHDL including PSK modulation demodulation convolutional error correction encoding and decoding scrambling HDLC framing TCP IP network interface and USB 2 0 interface It is designed to be embodied within a single low cost FPGA such as the Xilinx Spartan 6 LX45 The entire VHDL source code is included Key features and performance e PSK BPSK QPSK OQPSK modulation e Continuous mode operation i e Burst mode is not supported e Convolution error correction rates 1 2 2 3 3 4 5 6 and 7 8 e Overall performance 2 10 BER 4dB Eb No for K 7 rate V FEC e Serial HDLC to transmit empty frames over the synchronous link when no payload data is available e V 35 scrambling to randomize the modulated data stream e Maximum encoded data rate of 25 Msymbols s when using a 100 MHz FPGA processing clock e User interfaces o Synchronous serial with elastic buffer or o GbE TCP IP server o USB 2 0 FS HS e Demodulator performance o BER lt 0 5 dB implementation losses w r t theory o Programmable frequency acquisition range o Demodulator acquisition threshold uncoded Eb No 2dB e Ancillary components are also included for streaming test signal generation and bit error rate measurement e Drivers for the high speed and auxiliary DACs and ADCs are
6. MS s 15 6 2 Xilinx Spartan 6 3 Ready to use Hardware The COM 1505SOFT was developed on and therefore ready to use on the following commercial off the shelf hardware platform FPGA development platform COM 1500 FPGA DDR2 SODIMM socket ARM development platform Network adapter COM 5102 Gigabit Ethernet HDMI interface Analog COM 3504 Dual Analog lt gt Digital Conversions Xilinx specific code The VHDL source code is written in generic VHDL with few Xilinx primitives No Xilinx CORE is used The Xilinx primitives are IBUF IBUFG BUFG global clocks PLL_BASE clock generation DCM clock generation RAM block MULT18X18 hardware multiplier VHDL components overview Top level 3 ii COM1505 Behavioral C Users AK Documents source_ VHDL com 1505 PSK rr ts FREQ REF DLL 001 freqRefDLL xilinx C Users AK Documents source VHDL Ha Inst LFSRI1P LFSR11P behavior C Users AK Documents source_ VHDL corr ts HDLC SERIAL 2TX 001 HDLC SERIAL 2TX behavioral C Users AK Documer Ha V35SCRAMBLER 001 V35SCRAMBLER behavioral CAUsers AK Documents si ENCODER ROOT 001 ENCODER ROOT behavioral C Users AK Documents PX TO P8 CONVERSION 001 PX TO P8 CONVERSION behavioral C Users s X CLK DOMAINS NODATALOSS 001 CROSS CLK DOMAINS NODATALOSS E tg Inst BURST MODULATOR BURST MODULATOR Behavioral C User
7. Q 10 l Q 00 gt l Q 11 l Q 01 Clocks generation external BUFGMUX frequency referenc amp non 60 120 tx symbol rate Tal 60 MHz 300 MHz MHz i PLL 9 NCO 9 J 2N x2 On board as SUME 2 programmable 100 MHz PLL ADC rx symbol rate gt x NCO x2 gt ye CLK P 32 bit pace eae programmable The software is written to accept a 10 MHz or a 60 MHz clock as frequency reference The design includes several clock domains CLK_P main processing clock selected to be the same as the ADC sampling clock in this project CLK_TXG processing clock for the digital PSK modulator This clock is programmable see control registers REGO through REG2 as it relates to the modulation symbol rate it is always a power of 2 multiple of the modulation symbol rate 60 to 120 MHz for a Xilinx Spartan 6 implementation USB CLK 60G processing clock for the USB 2 0 serial interface engine Always 60 MHz Supplied by the external USB PHY through the standard ULPI interface LANI RXC 2 5 25 125 MHz clock for the 10 100 1000 Ethernet MAC COMS5401 vhd Supplied by the external LAN PHYthrough the standard RGMII interface Limitation and trade off Due to the lack of flexible programmable PLL in the Xilinx Spartan 6 family we use a ad hoc high speed NCO which is quite flexible 20 bit precision but which i
8. S 11 sequence is being transmitted USB20ULPI vhd implements the USB 2 0 protocol Serial Interface Engine It acts as a driver for an external USB PHY integrated circuit through a standard ULPI low pin interface COM5401 vhd implements the 10 100 1000 Ethernet MAC functions It is designed to interface with an external Gigabit Ethernet PHY integrated circuit via a standard RGMII or GMII interface The default interface is RGMII 1 COM5402 vhd implements the higher level IP protocols namely ARP PING TCP server UDP Two TCP servers are configured by default at port 1024 for payload transmit and receive at port 1028 for monitoring and control From the network the modem is a TCP server it listens for a remote connection from a client before transferring data 2 17 Receiver simulation The internal digital signal processing can be illustrated by the following screenshots obtained through VHDL simulation A Matlab program siggen psk2 m generates a stimulus file which mimics A D converter samples at the receiver input Internal FPGA signals are saved into Matlab loadable load command text files by setting the constant SIMULATION to 1 in various VHDL components Ideal signals case 100 Msamples s input samples 10 Msymbol s BPSK modulation 20 rolloff no impairments noiseless channel no symbol timing error no center frequency error 1500 p 1000 Wa Myn o ao E Pp pp tolg LAT PA ru i Il
9. UFFER NRAMB 001 ELASTIC BUFFER NRAMB behavioral C User ELASTIC BUFFER NRAMB 002 ELASTIC BUFFER NRAMB behavioral C User COMSCOPE 001 COMSCOPE behavioral C Users AK Documents source_VI SIM2OUTFILE 002 SIM2OUTFILE Behavioral C Users AK Documents source Ha DNA ID 001 DNA ID Behavioral C Users AK Documents source_VHDL con t C Users AK Documents source_VHDL com 1505 PSK modem convolutional FE COM1505 vhd top level Includes modulator demodulator clock generation interface to a supervisory microcontroller 8 bit address data bus to exchange control registers REG and status registers SREG CLK_P is the main processing clock LFSRI11P vhd pseudo random binary sequence generator PRBS 11 8 bit parallel output for a maximum data rate of 8 times the processing clock frequency HDLC SERIAL 2TX vhd bit serial HDLC is used for asynchronous to synchronous conversion The components inserts empty frames to tell the destination when no data is being transmitted over the synchronous always on link It encapsulates payload data within frames of at most 512 bytes A shorter frame will be transmitted over the link if no new payload data is available within 20us A 16 bit CRC is appended to each non empty frame to detect and reject erroneous frames at the receiving end The matching component at the receiving end is HDLC_SERIAL_2RX vhd V35SCRAMBLER vhd implements ITU V 35 Intelsat IESS 308 scrambling or descrambl
10. X RegO A2 Reg 13 00 Reg26 5F Reg39 00 Regi EE Regi4 00 Reg27 5E Reg40 00 Reg2 03 Regi5 00 Reg28 00 Reg41 AC Reg3 09 Reg16 00 Reg29 00 Reg42 10 Reg4 00 Reg17 00 Reg30 00 Reg43 01 Reg5 01 Regi8 00 Reg31 00 Reg 44 80 Reg6 30 Regi19 00 Reg 32 00 Reg 45 00 Reg7 75 Reg20 00 Reg 33 00 Reg46 01 Reg8 00 Reg21 00 Reg 34 08 Reg 47 02 Reg9 00 Reg22 00 Reg35 07 Reg 48 03 Regi0 00 Reg23 00 Reg36 01 Reg 49 04 Regii 00 Reg 24 00 Reg 37 02 Regi2 02 Reg25 31 Reg 38 00 Configuration Configuration option currently loaded rev 1 Configuration example 3 Same as above with 70 MHz IF input requires an external anti aliasing bandbass filter Set REG32 3 1 30 29 to B3 33 33 33 30 MHz Status Registers The baseline code is written so that 8 bit status registers SREGx are read by an external microcontroller through an 8 bit address data bus See process UC_READ_001 Digital status registers are read only PSK QAM APSK Demodulator Monitoring Parameters Monitoring Front end 8 bit unsigned value prior to DAC AGC conversion to RX_AGC1 Inverted scale 0 is for the maximum gain SREG10 Carrier Residual frequency offset with respect to frequency the nominal carrier frequency offset 24 bit signed integer 2 s complement fedelta expressed as fedelta 27 fa rx SREG11 LSB SREG12 SREG13 MSB Carrier Lock is declared if the standard deviation tracking loop lock status of the ph
11. ase error is less than 25deg rms 0 unlocked 1 locked SREG14 0 Inverse SNR A measure of noise over signal power 0 represents a noiseless signal Valid only when demodulator is locked SREGIS Viterbi FEC decoder monitoring Parameters Monitoring Synchronized FEC DEC LOCK STATUS variable Solid 1 when the Viterbi decoder is locked 0 or toggling when unlocked SREG14 1 Decoder The Viterbi decoder computes the BER built in BER on the received encoded data stream irrespective of the transmitted bit stream Encoded stream bit errors detected over a 1000 bit measurement window unless modified in com1509pkg vhd SREG16 bits 7 0 LSB SREGI7 bits 15 8 SREGIS bits 23 16 MSB HDLC decoder monitoring Parameters Monitoring Cumulative SREG19 LSB number of valid SREG20 bits at HDLC SREG21 output SREG22 MSB BER Measurement Parameters Monitoring Bit Errors Bit errors can be counted when a PRBS 11 test sequence is transmitted Number of bit errors in a 1 000 000 bit window 32 bit unsigned SREG23 error count 7 0 LSB SREG24 error count 15 8 SREG25 error count 23 16 SREG26 error count 31 24 MSB The bit errors counter is updated once every periodic measurement window Reading the value will not reset the counter BER 0 not synchronized 2047 bit pattern is Synchronization not detected stat
12. band near zero center frequency input signal 7 internal loopback mode from modulator REG35 2 0 Viterbi FEC decoder Parameters Configuration Constraint 0001 K 7 R 1 2 Intelsat length Kand 0010 K 7 R 2 3 Intelsat rate R 0011 K 7 R 3 4 Intelsat 0100 K 7 R 5 6 Intelsat 0101 K 7 R 7 8 Intelsat REG37 4 1 Differential 0 disabled Decoding enabled REG37 5 V 35 Intelsat 0 enabled IESS 308 e descrambling p after FEC REG37 7 decoding Bypass FEC 0 decoding enabled decoding _ 1 bypass REG38 7 Output 0 high speed USB 8 bit parallel selection 1 LAN TCP IP port 1024 through Ethernet adapter 8 bit parallel 2 bit synchronous serial 3 exclusively to the BER measurement REG36 2 0 Network Interface Parameters Configuration IP address 4 byte IPv4 address when Example 0x AC 10 01 80 designates connected address 172 16 1 128 to Gbit Ethernet The new address becomes effective PHY like immediately no need to reset the COM ComBlock 5102 REG41 MSB COM REG42 5104 REG43 REG44 LSB Re Writing to the last control register REG44 is recommended after a configuration change to enact the change Configuration example 1 Vw aue m em ag kHz M M SWT 6251ms Ref 20 0 dBm Att 16 dB Modulator j lt QA yl ANE 2 Msymbols s modulation BPSK convolutional a encoding K 7 R 1 2 PRBS 11 test sequence EJ baseband 0Hz com
13. bps x051EB852 uoi 2 T Duis REGI3 bits 7 0 LSB REGIA bits 15 8 REGIS bit 23 16 REG16 bit 31 23 MSB Channel filter enabled 0 enable the spectrum shaping filters root raised cosine interpolation 1 bypass the spectrum shaping filters special use in applications when a root raised cosine filter is not used in the demodulator REG4 7 External transmitter gain control When using an external transceiver such as the COM 350x family the transmitter gain can be controlled through the TX GAIN CNTRLI analog output signal Range 0 3 3V REG17 bits 7 0 LSB REG18 3 0 bits 11 8 External transmitter controls REG19 0 TX_ENB REGI9 1 RX TXN Signal gain Signal level 16 bit unsigned integer The maximum level should be adjusted to prevent saturation The settings may vary slightly with the selected symbol rate Therefore we recommend checking for saturation at the D A converter when changing either the symbol rate or the signal gain REG6 bits 7 0 LSB REG7 bits 15 8 MSB Receiver PSK Demodulator Parameters Configuration Processing clock The demodulator processing clock also serves as A D converter sampling clock It can be generated within the FPGA or externally Code baseline fak rx 100 MHz Note when using IF undersampling a dedicated oscillator is recommended as
14. fsymbol rate rx 512 apart The user can thus trade off acquisition time versus frequency acquisition range by specifying the number of scanning steps here For example 52 steps yield a frequency acquisition range of fsymbol rate rx O 10 REG24 AGC response time Users can to optimize the AGC response time while avoiding instabilities depends on external factors such as gain signal filtering at the RF front end and symbol rate The response time is approximately 0 8 symbols 1 16 symbols 2 32 symbols 3 64 symbols etc 10 every thousand symbols Valid range 0 to 14 REG34 4 0 Modulation type 0 BPSK 1 QPSK 2 OQPSK REG33 5 0 AGC internal external 0 internal AGC 1 external AGC When selecting internal AGC mode the user is responsible for avoiding saturation at or prior to the A D converter The internal AGC maximum gain is 256 in amplitude 48 dB in power Therefore it is recommended to keep the input samples amplitude between maximum and maximum 256 In the input dynamic range is larger please adjust the INTERNAL_AGC_005 process within RECEIVER vhd REG34 7 2 0 digital real 12 bit unsigned samples Se SCHON right connector COM 3504 transceiver Use in the case of IF input signal digital complex 2 12 bit unsigned samples right connector COM 3504 transceiver Use in case of base
15. iming tracking loop convergence at start up 8000 p 6000 j 4000 2000 2000 4000 E 0 500 1000 1500 2000 2500 3000 3500 4000 psk demod2 vhd carrier tracking phase replica for 50KHz magenta and 20KHz blue frequency error Reference documents 1 COM 5401SOFT Tri mode 10 100 1000 Ethernet MAC VHDL source code overview www comblock com download com5401soft pdf 2 COM 5402SOFT IP TCP UDP ARP PING STACK for GbE VHDL source code overview www comblock com download com5402soft pdf ComBlock Ordering Information COM 1505SOFT INTEGRATED PSK MODEM Contact Information MSS 18221 A Flower Hill Way Gaithersburg Maryland 20879 U S A Telephone 240 631 1111 Facsimile 240 631 1676 E mail info Qcomblock com 19
16. included for a seamless interface with popular Analog Devices analog digital converters Target Hardware The code is written in generic VHDL so that it can be ported to a variety of FPGAs The code is developed and tested on a Xilinx Spartan 6 FPGA It can be easily ported to any Xilinx Kintex 7 Virtex 6 Virtex 5 Spartan 6 FPGAs and other FPGAs Overall Block Diagrams USB 2 0 high speed TCP IP RJ 45 demodulator FEC decoder Synchronous Serial interface BER Measurement Demodulator connectivity MSS 18221 A Flower Hill Way Gaithersburg Maryland 20879 U S A Telephone 240 631 1111 Facsimile 240 631 1676 www ComBlock com MSS 2013 Issued 4 2 2013 10 100 1000Mbps COM 5102 5401 USB 2 0 high speed TCP IP RJ 45 10 100 1000Mbps COM 5102 5401 Synchronous Serial interface Internal Test Sequence Generator modulator FEC enc Modulator connectivity Synthesis time configuration parameters In the COM 1505 vhd component set the OPTION constant as A for LAN and USB interfaces B for synchronous serial clk data cts and USB interfaces C for synchronous serial clk data no HDLC Run time configuration parameters The user can set and modify the following controls at run time through 8 bit control registers REGx as listed below The baseline code is written so that control registers REGx are written by an external microcontroller through a simple 8 bi
17. ing 16 Scrambling is required to randomized the transmitted data stream before FEC encoding ENCODER ROOT vhd convolutional encoder The matching component at the receiving end is VITERBI DECODER vhd Bit serial to 8 bit parallel conversions and back are implemented by PX TO P8 CONVERSION vhd and P8 TO SI CONVERSION vhd respectively CROSS CLK DOMAINS NODATALOSS vhd preserves the signal integrity while crossing clock domains from the general processing clock domain CLK P to the digital modulator clock domain CLK TXG for example BURST MODULATOR vhd implements the digital modulation and spectrum shaping Key controls include modulation symbol rate output signal amplitude modulation type BPSK QPSK etc The programmable modulation symbol rate sets the entire transmitter data throughput RECEIVERI vhd is the front end digital receiver which processes digital samples from the A D converter s Its functions include fixed frequency translation to near zero baseband AGC variable decimation CIC filters and one half band filter for image rejection Input digital samples can be complex in the case of baseband input samples or real in the case of IF undersampling PSK_DEMOD2 vhd demodulates the PSK symbols while tracking the received modulated signal three key parameters amplitude center frequency and symbol rate BER2 vhd synchronizes with the received bit stream and counts the number of bit error when a PRB
18. isters 17271 31 LUTs 1887 69961 Block RAM 44 37 DSP48A 1s 30 48 GCLKs 10 62 DCMs 3 37 PLL_ADVs 2 50 B Directory Contents doc Specifications user manual implementation documents src vhd source code ucf constraint files pkg packages One component per file sim Test benches Matlab m signal generation program bin ngc bit mcs configuration files Key files Xilinx ISE project file com 1505_ISE431 xise ucf constraint file example when used on the COM 1500 FPGA platform src COM1505 ucf VHDL development environment The VHDL software was developed using the following development environment a Xilinx ISE 14 1 with XST as synthesis tool b Xilinx ISE Isim as VHDL simulation tool The entire project fits within a Xilinx Spartan 6 LX45 Therefore the ISE project can be processed using the free Xilinx WebPack tooks Registers 14154 25 LUTs 15089 55 Block RAM 25 21 DSP48A1s 24 41 GCLKs 8 50 DCMs 3 37 PLL_ADVs 2 50 Registers 14484 26 LUTs 15039 55 Block RAM 26 22 DSP48A 1s 30 51 GCLKs 9 56 DCMs 3 37 PLL_ADVs 2 50 Xilinx Kintex 7 2 Clock and modem speed The modem design primarily uses two global clocks a transmit DAC clock and a receive ADC clock Typical maximum clock frequencies for various FPGA families are listed below Xilinx Virtex 100 MHz 120 MHz 25
19. it first The modem monitoring and control information can also be sent over the same physical link using the TCP server at port 1028 More information regarding the built in 10 100 1000 Mbps Ethernet MAC and the TCP server can be found here www comblock com download com5401 soft pdf www comblock com download com5402soft pdf USB Data streams can also be transmitted over a USB 2 0 cable together with monitoring and control information This modem acts as a USB device See http comblock com download USB20_UserManual pdf for details More information regarding the built in USB 2 0 Serial Interface Engine SIE can be found here http comblock com download USB2soft pdf 12 Performance Bit Error Rate 10 10 10 10 10 Bit Error Rate Bit error probability curve for BPSK QPSK modulation c c c c heory i HHH HHH HH i 1 3 HH POEH HAH ee t actual E e T j aa e r r r r r 2 0 2 4 6 8 Eb No dB BER performance demodulator only no FEC Bit error rate performance for rate 1 2 E p In 4 In c cE jx la uncoded 7 P K 7 10 z K 9 10 E 10 1 E 1 0 t f r r r r r r r 0 0 5 1 1 5 2 2 5 3 3 5 4 5 Eb No dB BER performance FEC only no demodulator oh 13 Implementation Block Diagram
20. plex I Q modulated output signal Demodulator amp 0 lt joy 2 Msymbols s BPSK convolutional encoding K 7 R 1 2 internal AGC with response speed 8 internal loopback mode demodulated data directly to BER measurement E IP address 172 16 1 128 e MAC address 00 01 02 03 04 05 f com1505 PSK Modem Convolutional FEC TCP IP Network I 100 GHE Span 20 MHz Typical RF output spectrum after D A conversion Registers and direct RF modulation All register values in HEX RegO DO Regi3 00 Reg 26 Configuration example 2 Modulator Reg2 03 RegiS 00 Reg28 144 Ksymbols s modulation BPSK convolutional encoding K 7 R 1 2 from LAN TCP IP baseband OHz complex I Q modulated output signal Regi 69 Regi4 00 Reg 27 Reg3 05 Regi6 00 Reg 29 Reg4 00 Regi7 00 Reg 30 Reg5 03 Regi8 00 Reg3i Demodulator 144 Ksymbols s BPSK convolutional encoding K 7 R 1 2 internal AGC with response speed 8 Reg7 75 Reg20 00 Reg33 internal loopback mode demodulated data to LAN TCP IP Reg6 30 Regi9 00 Reg32 Reg8 00 Reg21 00 Reg 34 Reg 9 Reg22 00 Reg 35 IP address 172 16 1 128 Reg10 00 Reg23 00 Reg36 MAC address 00 01 02 03 04 05 Regii 00 Reg24 00 Reg 37 Regi2 02 Reg25 52 Reg 38 Configuration Configuration option currently loaded rev 1 Fr COM1505 PSK Modem Convolutional FEC TCP IP Network I Registers E All register values in HE
21. s AK Doc H H H H H CROSS CLK DOMAINS 001 CROSS CLK DOMAINS behavioral C Users AK CROSS CLK DOMAINS 002 CROSS CLK DOMAINS behavioral C Users AK AD9627 ADC DRIVER 001 AD9627 ADC DRIVER2 Behavioral C Users AK Dc a Inst AUX DACS ADC AUX DACS ADC Behavioral C Users AK Documents MEASURE INTERVAL 001 MEASURE INTERVAL Behavioral C Users AK Doct Wa RECEIVERI 001 RECEIVERI Behavioral C Users AK Documents source_VHD PSK DEMOD2 001 PSK_DEMOD2 behavioral C Users AK Documents sourc VITERBI DECODER 001 VITERBI DECODER behavior C Users AK Document wj V3SDESCRAMBLER 001 V35SCRAMBLER behavioral C Users AK Documents ha HDLC SERIAL 2RX 001 HDLC SERIAL 2RX behavioral C Users AK Documer E a BER2 001 BER2 behavioral C Users AK Documents source_VHDL com 150 p D m p H M i AD9747 DAC DRIVER2 001 AD9747 DAC DRIVER2 Behavioral C Users AK D M M a PX TO P8 CONVERSION 003 PX TO P8 CONVERSION behavioral C Users s P8 TO SI CONVERSION 001 P8 TO S1 CONVERSION Behavioral C Users 4 CLEAN OUTPUT CLK 001 CLEAN CLK behavioral C Users AK Documents ELASTIC BUFFER32b 001 ELASTIC BUFFER32b behavioral C Users AK Docu USB20ULPI 001 USB20ULPI Behavioral C Users AK Documents source_VHD LAN 001 COMS401 Behavioral C Users AK Documents source_VHDL com IPSTACK 001 COM5402 Behavioral C Users AK Documents source_VHDL c ELASTIC B
22. s afflicted by 3ns peak peak jitter To mitigate this impairement the modulated signal is resampled and filtered creating some minor aliasing 45 dB Substituting the HIGH SPEED NCO vhd component with the DCM_CLKGEN_DYNAMIC vhd component eliminates the aliasing impairements but limits the symbol rate programmability to coarser steps of at most 1 versus 3ppm for the baseline version 10 l Os 1 bit synchronous serial B option RECEIVER INTERFACE exor I LI LI NEN RX DATA OUT i j Y best time for user to read the rx data bit TRANSMITTER INTERFACE CTS_OUT clear to send K CLK_IN N TX DATAIN l Y best time for user FPGA Stop sending to send a tx data bit reads data tx data when FPGA at rising edge input buffer is full In the transmit direction the user provides both clock CLK_IN and data TX_DATA_IN The user should always check the Clear To Send CTS OUT flag before sending additional data bits to the modulator As option B includes HDLC the user is allowed not to transmit data When so the modem will send empty HDLC frames 1 bit synchronous serial C option RECEIVER INTERFACE CLK OUT RX DATA OUT J X best time for user to read the rx data bit TRANSMITTER INTERFACE CLK IN from modem
23. t address data bus See process UC_WRITE_001 FEC convolutional encoder Parameters Configuration Constraint 0001 K 7 R 1 2 Intelsat length Kand 0010 K 7 R 2 3 Intelsat rate R 0011 K 7 R 3 4 Intelsat 0100 K 7 R 5 6 Intelsat 0101 K 7 R 7 8 Intelsat REG12 4 1 Differential Differential encoding is useful in Encoding removing phase ambiguities at the PSK demodulator at the expense of doubling the bit error rate When enabled the differential decoding must be enabled at the receiving end There is no need to use the differential encoding to remove phase ambiguities at the PSK demodulator when the Viterbi decoder and HDLC decoder are enabled 0 disabled 1 enabled REGI2 5 Bypass FEC 0 encoding enabled encoding B 1 bypass REG12 6 V 35 Intelsat 0 enabled TESS 308 1 byp ss scrambling nicis before FEC REGI2 7 encoding PSK Modulator Transmitter Parameters Configuration Input selection Select the origin of the transmitter format test modes input data stream 0 high speed USB 8 bit parallel 1 LAN TCP IP port 1024 through Ethernet adapter 8 bit parallel 2 1 bit synchronous serial 3 internal PRBS 11 test sequence 5 unmodulated carrier 8 bit parallel input bytes are transmitted MSb first REGS 3 0 Parameters Configuration Processing Modulator processing clock Also serves
24. the FPGA generated clock may show excessive jitter which translates into phase noise Spectrum inversion Invert Q bit This is helpful in compensating any frequency spectrum inversion occurring during RF frequency translations REG33 6 High SNR To minimize the false lock probability at high SNR set this bit to 1 when Eb No is likely to exceed 10dB To emphasize operation at very low Eb No set this bit to 0 REG33 7 Nominal symbol rate Lobo rate rx The demodulator nominal symbol rate is in the form fsymbol rate rx L REG25 bits 7 0 LSB REG26 bits 15 8 REG27 bit 23 16 REG28 bit 31 23 MSB 232 Nominal Center frequency f rx Expected center frequency of the received signal 32 bit signed integer 27s complement representation expressed as fou a Lg In the case of IF undersampling the residual intermediate frequency is removed here For example in the case of a 125 MHz IF signal sampled at 100 Msamples s the 25 MHz residual frequency is removed here by entering 0x40000000 REG29 bit 7 0 LSB REG30 bit 15 8 REG31 bit 23 16 REG32 bit 31 23 MSB Frequency acquisition range scan The demodulator natural frequency acquisition range is around 1 of the symbol range depending on modulation SNR The frequency acquisition range can be extended by frequency scanning Scanning steps are spaced
25. us 2 synchronized SREG27 0 TCP IP Connection Monitoring Parameters Monitoring TCP IP Bit 0 port 1028 M amp C connected connection on Bit 1 port 1024 data connected port 1024 data stream 1 for connected 0 otherwise SREG28 1 0 LAN PHY ID Expect 0x22 when the PHY IC is Micrel KSZ9021 SREG29 LSB MAC address Unique 48 bit hardware address 802 3 In the form Since the MAC address is unique it can also be used as a unique identifier in a radio network with many nodes Note multi words status registers such as frequency offset or BER are latched upon reading status register SREGIO Troubleshooting checklist 1 Place modem in loopback mode REG35 0x07 while sending a PRBS 11 test sequence REGS 0x03 Be sure to direct the demodulated bit stream to the BER measurement REG36 0x03 Check the status registers for a Demodulator and Viterbi decoder are locked SREG14 0x03 b No Viterbi decoder errors SREGI6 17 18 2 0 c BER measurement is synchronized SREG27 0x01 d No BER errors SREG23 24 25 26 0 e Bits are being received at the HDLC decoder output SREG19 20 21 22 counter keeps increasing at a rate consistent with the modulation rate Operation Constellation Symbol Mapping The packing of serial data stream into symbols is done with the Most Significant bit first BPSK gt O OPSK Gray encoding Q A l
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