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MN101C485/487 LSI User`s Manual

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1. Vico Vico lt lt lt Dd SSE ES 1 3 duty 1 3 bias 1 4 duty 1 3 bias d 1 3 duty 1 3 bias 1 4 duty 1 3 bias Voo 2 V Vico 3 V Voo Vico MN101C485 487 MN101C485 487 3 i ER gt Vico Ms Vico Ge R Vic 3 Vica co 2 Vie Vss Page Line Definition Previous Edition Ver 2 51 New Edition Ver 2 7 1 11 Table Change If a capacitor is to be inserted between If a capacitor is to be inserted between rss NRST NRST and Vss 1 14 ry Change Discription of BUZZER 1 17 ne Change A16 P53 SEG51 LED3 A16 P53 SEG24 LED3 1 24 27 Change Pull up resistor ON Pull up resistor built in 35 2 Change only for output output and LCD output 3 Change only for output output and LCD output Jus Change only for output output and LCD output IIl 3 2 Vector number 2 to 18 Vector number 2 to 20 S Table address x 04008 to x 04048 Table address x 04008 to x 04050 Ke 3 Change 3 5 35 37 Change f jT i iD 43 3 Delete timer 1 interrupt timer 7 interrupt signal timer 4 interrupt signal v 9 90 Change
2. NFCTR NFOEN NEOCKSO IRQOICR NFOCKS1 IRQOIR NF1EN IRQOIE 80 fs 2 NFiCKS1 15 2 9 i REDGO 7 IRQOLVO fs 2 MUI X IRQOLV1 5 2 7 Y P20 IRQ0 X Noise filter IRQO interrupt reques M 5 16 bit timer X x Automatic data Polarit d inversion transfer RQ1ICR Y IRQ1IR fs 2 3 IRQ1IE fs 2 10 REDG1 8 2 IRQ1LVO Y IRQILVI oft Noise filter P21 IRQ1 ACZ X detection circu LL lu To T put control M m U U 16 bit timer X Polarit X Automatic data inversion transfer FLOAT1 P7RDWN PARDWN 211 zero cross detection circuit amp Schmitt input Figure 3 3 1 External Interrupt 0 Interface and External Interrupt 1 Interface Block Diagram 30 External Interrupts Chapter 3 Interrupts Interrupt 2 Interface Block Diagram IRQ2ICR IRQ2IE _ REDG2 IRQ2LVO 21 1 P22 IRQ2 M U IRQ2 interrupt request Polarity X 16 bit timer Inversion Port 7 Figure 3 3 2 External Interrupt 2 Interface External Interrupts III 31 Chapter 3 Interrupts External Interrupt 4
3. Reset P6PLUO 7 Pull up resistor control DO 6 90 gt gt Write Read Reset P6DIRO 7 VO direction control GbIRO Write Read 3 P60 P67 Z N D Reset w RIP TO 7 Port output data 5 600 0 Write Read 7 7 P6INO 7 4 Port input data 4 Read Segment output control signal are Segment output control Address output VDD Expansion control VLC1 Y Lp Segment output gt gt lt 2 gt 26 VLC3 When segment output is selected segment output control automatically sets port I O direction control to input mode and segment output control is set to without pull up resistors In memory expansion mode output mode is always selected Figure 4 6 3 Block Diagram P60 to P67 Chapter 4 Ports 4 7 Port7 4 7 1 Description Port Setup Each bit of the port 7 control I O direction register P7DIR can be set individually to set pins as input or output The control flag of the port 7 direction control register P7DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 7 direction control register P7DIR to 0 and read the value of the port
4. OIvIALL 91 8 v s 250 Timer 4 Block Diagram Figure 6 1 1 VI 3 Overview Chapter 6 16 bit Timer 6 2 Control Registers Timer 4 contains the binary counter TMABCL TMABCH the compare register TMAOCL TMAOCH and input capture register TM4ICL TM4ICH The timer 4 mode register TM4MD controls timer 4 6 2 1 Registers Table 6 2 1 shows the registers that control timer 4 Table 6 2 1 16 bit Timer Control Registers Register Address R W Function Page TM4BCL x 03F64 Timer 4 binary counter lower 8 bits VI 5 TM4BCH x 03F65 Timer 4 binary counter upper 8 bits 5 TM4OCL x 03F74 R W Timer 4 compare register lower 8 bits VI 5 TM4OCH X03F75 R W Timer 4 compare register upper 8 bits 5 Timer 4 TM4ICL x 03F66 Timer 4 input capture regsiter lower 8 bits VI 6 TM4ICH x 03F67 Timer 4 input capture register upper 8 bits VI 6 TM4MD x 03F84 R W Timer 4 mode register VI 7 TM4ICR R W Timer 4 interrupt register timer 4 compare match 23 1 x 03F39 R W Port 1 output mode register V 12 P1DIR xOSF31 R W Port 1 direction control register 11 R W Readable Writable Readable only VI 4 Control Registers Chapter 6 16 bit Timer 6 2 2 Programmable Timer Registers Timer 4 has a 16 bit programmable timer register It contains a compare register a
5. Clock source 1 count time hs fosc 50 ns fs 100 ns fs 4 400 ns 16 1 6 us fx 30 5 Notes as fosc 20 MHz fx 32 768 kHz fs fosc 2 10 MHz 10 8 bit Timer Count Chapter 5 8 bit Timers iCount Timing of Timer Operation Timers 2 and 3 Binary counter counts up with selected clock source as a count clock The basic operation of the whole function of 8 bit timer is as follows Count clock uis TMnEN EE Row ci ou 4 flag AE eee ae Compare i i y i register H 02 03 04 operation stop 1 0 y 00 01 by N vy 01 counter A B C Compare match signal Interrupt request flag Figure 5 3 1 Count Timing of Timer Operation Timers 2 and 3 A If the value is written to the compare register during the TMnEN flag is 0 the binary counter is cleared to 00 at the writing cycle B If the TMnEN flag is 1 the binary counter is started to count The counter starts to count up at the falling edge of the count clock But the binary counter doesn t count up at the first falling of the count edge C the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock then the binary counter is cleared to 00 and the counting is restarted D Even if the compare register is rew
6. 5 at reset XX Figure 12 2 3 A D Buffer 0 ANBUFO 92 A D Buffer 1 ANBUF1 The upper 8 bits from the result of A D conversion are stored to this register 7 6 5 4 3 2 1 0 ANBUF1 ANBUF17 ANBUF16 ANBUF 15 meur mur neue ANBUF10 atreset X X X XXXXX Figure 12 2 4 A D Buffer 1 ANBUF1 93 Control Registers XII 7 Chapter 12 A D Converter 12 3 Operation Here is a description of A D converter circuit setup procedure 1 XII 8 Set the analog pins Set the analog input pin set in 2 to special function pin by the port A input mode register PAIMD Setup for the port A input mode register should be done before analog voltage is put to pins Select the analog input pin Select the analog input pin from AN7 to ANO PA7 to PAO by the ANCHS2 to ANCHSO flag of the A D converter control register 0 ANCTRO Select the A D converter clock Select the A D converter clock by the ANCK1 ANCKO flag of the A D converter control register 0 ANCTRO Keep the converter clock TAD over 800 ns with any resonators Set the sample hold time Set the sample hold time by the ANSH1 ANSHO flag of the A D converter control register 0 ANCTRO The sample hold time should be based on analog input impedance Set the A D ladder resistance Set the ANLADE flag of the A D converter control register 0 ANCTRO to 1 an
7. ZF Zero flag 0 Operation result is not 0 1 Operation result is 0 CF Carry flag A carry or a borrow from MSB did not occur A carry or a borrow from MSB occured NF Negative flag 0 MSB of operation results is 0 1 MSB of operation results is 1 VF Overflow flag 0 Overflow did not occur 1 Overflow occured IM1 to 0 Interrupt mask level Controls maskable interrupt acceptance MIE Maskable interrupt enable All maskable interrupts are 0 disabled 1 xxxLVn xxxlE for each interrupt are enabled Reserved Set always 0 Figure 2 1 3 Processor Status Word PSW 8 Overview Chapter 2 CPU Basics Zero Flag ZF Zero flag ZF is set to 1 when all bits are 0 in the operation result Otherwise zero flag is cleared to 0 Flag CF Carry flag CF is set to 1 when from or a borrow to the MSB occurs Carry flag is cleared to 0 when no carry or borrow occurs iNegative Flag NF Negative flag NF is set to 1 when MSB is 1 and reset to 0 when MSB is 0 Negative flag is used to handle a signed value WOverflow Flag VF Overflow flag VF is set to 1 when the arithmetic operation results overflow as a signed value Other wise overflow flag is cleared to O Overflow flag is used to ha
8. IInterrupt acceptance cycle 1 1 0 90 Interrupt service routine 2 Restart interrupt processing program 1 RTI imt o t0 RTI im1 0 11 Parentheses indicate hardware processing Figure 3 1 7 Processing Sequence with Multiple Interrupts Enabled Overview 13 Chapter 3 Interrupts 3 1 4 interrupt Flag Setup Bi Interrupt request flag IR setup by the software The interrupt request flag is operated by the hardware That is set to 1 when any interrupt factor is generated and cleared to 0 when the interrupt is accepted If you want to operate it by the software the IRWE flag of MEMCTR should be set to 1 Bi interrupt flag setup procedure A setup procedure of the interrupt request flag set by the hardware and the software shows as follows Setup Procedure Description Disable all maskable interrupts PSW bp6 MIE 0 Select the interrupt factor Enable the interrupt request flag to be rewritten MEMCTR x 3F01 bp2 IRWE 1 Rewrite the interrupt request flag xxxICR bpO xxxIR Disable the interrupt request flag to be rewritten MEMCTR x 3F01 Enable all maskable interrupts PSW bp6 MIE 1 Clear the MIE flag of PSW to disable all maskable interrupts This is necessary especially when the interrupt control register is changed Select the interrupt factor such as interrupt edge selection or timer int
9. 2 aee cete 2 11 1 2 Operation at STANDBY XI 3 11 1 3 Maximum Number of Pixels 2 2 XI 3 11 1 4 LCD Driver Block Diagram 4 Control Re sisters XI 5 112221 on oen Cte er bre e eee eee qois cat com disent rie te XI 5 11 2 2 LCD Mode Control Register 6 11 2 3 Segment Output Control Register LCCTR 22 2 2 2 2 XI 8 11 2 4 Segment Outpit XI 9 11 2 5 Operation saci eee epp eere peii XI 10 LCD Voltage Control Circuit XI 11 Operation thea i e P e AEE RE Ep XI 14 11 41 LCD Display Examples XI 14 11 42 Setup 16 11 4 3 LCD Display Examples 1 2 Duty eee XI 18 11 44 Setup Example 1 2 Duty sse XI 20 contents 11 4 5 LCD Display Examples 1 3 XI 22 11 46 Setup Example 1 3 XI 24 11 4 7 LCD Display Examples 1 4 Duty een XI 26 11 4 8 Setup Example 1 4 XI 28 Chapter 12 A D Conversion Functions 12 1 12 2 12 3 OVerVIeW ee Rer Oe RE d XII 2 1251 1 P nctions D RUE ERREUR XII 2 12 12 Diagram 5 oet
10. Data output pin Data input pin Clock VO pin Setup item SBTO pin SBO0 pin pin Internal clock External clock master communication slave communication Pin 1 2 SBI0 SBOO independent SBIO SBOO pin SCOMD3 SCOIOM Port Serial data input Serial clock VO Port Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull Style Nch open drain Nch open drain SCOMD3 SCOSBTM Input mode Output mode Input mode PODIR PODIR1 PODIR PODIR2 Bd Added Not added Added Not added Added Not added ull up POPLU POPLU1 POPLU POPLU2 Operation Chapter 10 Serial Interface 0 Pins Setup 3 channels at transmission reception Table 10 3 7 shows the setup for synchronous serial interface pin with 3 lines SBOO pin SBIO pin SBTO pin at transmission reception Table 10 3 7 Setup for Synchronous Serial Interface Pin 8 channels at transmission reception Data output pin Data input pin Clock VO pin Setup item i SBTO pin SBOO pin pin Internal clock External clock master communication slave communication Pin 1 2 5 0 SBOO independent SBOO pin SCOMD3 SCOIOM POPLU POPLUO POPLU POPLU1 meats Serial data output Serial data input Serial clock VO Port SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull
11. SYSMDO 7 Synchronous output control DQ Write A Read 777 Reset P7INO 7 4 Port input data 4 Read Segment output control signal Segment output control VDD T VLC1 i e 54 Segment output F Synchronous output event VLC3 FLOAT register P7SYEV1 0 flag When segment output is selected segment output control automatically sets port I O direction control to input mode and segment output control is set to without pull up resistors In memory expansion mode set the bp5 6 of the EXADV register to be used as general I O as address output pin Figure 4 7 5 Block Diagram P70 to P77 Pot7 IV 33 Chapter 4 Ports 4 8 8 4 8 1 Description Port Setup Each bit of the port 8 control I O direction register P8DIR can be set individually to set pins as input or output The control flag of the port 8 direction control register P8DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 8 direction control register P8DIR to 0 and read the value of the port 8 input register P8IN To output data to pin set the control flag of the port 8 direction control register P8DIR to 1 and write the value of the port 8 output
12. 1 ANCHSO Analog input selection 0 0 ANO 1 1 0 1 0 AN2 1 AN3 0 0 4 4 1 5 1 0 AN6 1 AN7 ANLADE A D ladder resistance control 0 A D ladder resistance OFF A D ladder resistance ON ANCK1 ANCKO A D conversion clock ftad 1 TAD 0 fs 2 1 fs 4 1 0 fs 8 1 fxx2 as 800 ns lt TaD lt 15 26 us ANSH1 ANSHO Sample and hold time 0 x 2 0 1 Tap x 6 1 0 Tap x 18 1 Not to use Sampling and holding time is decided by the input impedance at analog input Tap means the cycle for A D conversion clock Figure 12 2 1 A D Converter Control Register 0 ANCTRO x 03F90 R W Control Registers XII 5 Chapter 12 A D Converter A D Converter Control Register 1 ANCTR1 7 6 5 4 3 2 1 0 At reset 0 1 ANST 4 ANST A D conversion status 0 A D conversion is completed stopped 1 A D conversion is started in progress Figure 12 2 2 A D Converter Control Register 1 x 03F91 R W XII 6 Control Registers Chapter 12 A D Converter 12 2 3 A D Buffers They are reading only registers that stores result of A D conversion A D Buffer 0 ANBUFO The lower 2 bits from the result of A D conversion are stored to this register 7 6 5 4 3 2 1 0 ANBUFO
13. i fee Y 5 OXOEIAL uopezuonpulg ndu 73 Timers 2 and 3 Block Diagram igure 5 1 1 V 3 Overview Chapter 5 8 bit Timers mRemote Control Carrier Output Block Diagram Remote control ouput Synchronizing circuit RMCTR Reserved RMDTYO Reserved RMOEN Reserved MUX gt 1 2 duty 1 3 duty Timer 3 output Figure 5 1 2 Remote Control Carrier Output Block Diagram 4 Overview Chapter 5 8 bit Timers 5 2 Control Registers Timers 2 and 3 consist of the binary counter TMnBC and the compare register TMnOC And they are controlled by the mode register TMnMD Remote control carrier output is controlled by the remote control carrier output control register RMCTR 5 2 1 Registers Table 5 2 1 shows registers that control timers 2 and 3 and remote control carrier output Table 5 2 1 8 bit Timer Control Registers Register Address Function Page R W bowsr wezmrycnne ve 7 Timer 3 compare register V 6 03 83 Timer 3 mode register V 8 Timer 3 Timer 3 interrupt control register Ill 22 x O3F39 Port 1 output mode register 12 P1DIR X O3F31 R W 1 dir
14. Matsushita Electronics Corporation Differences between Old manual 1st Edition 1st Printing and Current manual 1st Edition 2nd Printing Page Line Old manual 1st Edition 1st Printing Current manual 1st Edition 2nd Printing 1 24 ROM Option Bits Figure 1 6 1 ROM Option Bits address X OFFFF Figure 1 6 1 ROM Option Bits address X 07FFF Table 1 6 1 ROM Option Adddress ROM Option Address X 07FFF X 07FFF X 07FFF X 07FFF Model 101 485 101 487 MN101CP485 MN101CP487 Ed After a reset connect oscillator pins to both side whichever an oscillator mode is After a reset connect oscillator pins to the high speed oscillation input too even if the slow mode is selected The WDMD bp5 should be always set to 1 If itis set to 0 that operation cannot be stopped after the watchdog timer is generated 1 25 Contents of mask option are subject to change 1 When placing an order for masks please request the most recent option list from the sales office 6 in Figure 4 1 4 gt ROM option X OFFFF ROM option X 07FFF V 19 Ten registers control the serial interface Seven registers control the serial interface IX 9 In the MN101C48X microcomputer EPROM versions MN101CP485 MN101CP487 etc bits 2 to 0 at the highest address See tabl
15. 20 to 70 VDD 2 0 V 2 3 v 5 5v VSS 0 Parameter Symbol Conditions Unit MIN TYP MAX VO pin3 P50 to P53 34 Input high voltage 1 VIH7 0 8 VDD 35 Input high voltage 2 ViH8 VDD 4 5 V to 5 5V 0 7 VDD VDD 36 Input low voltage 1 VIL7 0 0 2 VDD 37 low voltage 2 ViL8 VDD 4 5 V to 5 5V 0 0 3 VDD 38 Input leakage current Vi 0 V to 2 39 Input high current PRE cer on 9v 30 100 300 d 40 Output high current VoH7 VDD 5 0 V 0 5mA 4 5 41 Output low current VOL7 Vpp 5 0V loL 15 mA 1 0 d VO pin4 P60 to P67 P80 to P87 42 Input high voltage 1 VIH9 0 8 VDD 43 Input high voltage 2 ViH10 4 5 V to 5 5 V 0 7 VDD VDD i 44 Input low voltage 1 9 0 0 2 45 Input low voltage 2 ViL10 VDD 4 5 V to 5 5 V 0 0 3 46 Input leakage current ILkg Vi 0 VDD 2 47 Input current ay 30 100 300 E 48 Output high voltage VoH9 5 0 V 0 5 mA 4 5 49 Output low voltage 9 Vpp 5 0 V loL 1 5mA 0 5 VO pin5 P70 to P77 50 Input high voltage 1 0 8 VDD 51 Input high voltage 2 ViH12 4 5 V to 5 5 V 0 7 VDD 52 Input low voltage 1 VILI 0 0 2 VDD 53 Input low voltage 2 ViL12 4 5 V to 5 5 V 0 0 3 VDD 54 Input leakage current ILK11 Vi 0 2 55 Inpu
16. 50013 P5OUT2 P5OUT1 500 0 At reset 0000 P5OUT Output data 0 Low Vss level 1 High level Port 5 output register P5OUT x 03F15 R W 3 2 1 0 2 P5IN1 5 Atreset XXXX Input data 0 Pin is Low Vss level 1 Pin is High VDD level Port 5 input register 25 3 2 1 0 P5DIR3 P5DIR2 P5DIR1 P5DIRO Atreset 0000 P5DIR mode selection 0 Input mode 1 Output mode Port 5 direction control register P5DIR x 03F35 R W 3 2 1 0 P5PLU3 P5PLU2 P5PLU1 P5PLUO Atreset 0000 P5PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 5 pull up resistor control register PBPLU x 03F45 R W Port 5 Figure 4 5 1 Port 5 Registers 1 3 Chapter 4 Ports 7 6 5 4 3 2 1 0 EXADV EXADV3 EXADV2 EXADVI i At reset 000 P73 P70 11 A8 address output EABBYI during memory expansion mode 0 General port 1 A11 to A8 address output EXADV2 P77 P74 A15 A12 address output during memory expansion
17. 3 2 3 1001 000H lt d4 gt 4 if ZF 0 3 gt BEQ label if ZF 1 4 7 1 4 2 3 1000 1010 d7 2 if ZF 0 4 BEQ label i ZF 1 PC 5 d11 label H gt PC 5 2 8 1001 1010 lt d11 H 4 if ZF 0 5 BNE label if ZF 0 PC 3 d4 label H gt PC 3 2 3 1001 001H lt d4 gt 1 if ZF 1 PC 32PC BNE label if ZF 0 PC 4 d7 label HPC 4 2 8 1000 1011 d7 if ZF 1 4 BNE label if ZF 0 PC 5 d11 label H PC 5 2 3 1001 1011 lt d11 3 if ZF 1 5 BGE label if VF NF 0 PC 44d7 labe amp HAPC 4 2 8 1000 1000 d7 2 if VFANF 1 PC 4 PC BGE label if VE NF 0 PC 5 d1 label H PC 5 2 3 1001 1000 lt 11 22 3 if VFANF 1 PC 5PC BCC label if CF 0 PC 44d7 label H PC 4 2 3 1000 1100 d7 2 if CF 1 4 BCC label if CF 0 5 011 1 5 2 3 1001 1100 dii 1 PC 52PC BCS label if CF 1 PC 44d7 label H PC 4 2 3 1000 1101 d7 2 if CF 0 4 BCS label if CF 1 5 911 5 2 3 1001 1101 dii if CF 0 PC 52PC BLT labe if VE NF 1 PC 4 d7 label H gt PC 4 2 3 1000 1110 d7 2 i
18. 4 l lt 1 U Write Read 7 7 X Schmitt input POINO E Port input data N Read Serial interface 0 reception data input UART reception data input Serial interface 0 transmission data output UART transmission data output SCOMDS register SCOSBOS flag Figure 4 2 2 Block diagram P00 mes Reset POPLU1 Pull up resistor control gt Write F Read Reset PODIR1 direction control 0 Write F Read 8 f Reset gt Port output data Write F Read 7 7 j POIN1 Sent input Port input data M J ae Read Serial interface 0 reception data input UART reception data input Figure 4 2 3 Block diagram P01 8 PortO SCOMDS register Chapter 4 Ports SCOSBTM flag Reget POPLU2 Pull up resistor control Write FA Read mE R PODIR2 Ls direction control 9 gt Write Read X poe Reset 5 POOUT2 Port output data g an U Write Read 7 7 X POIN2 input Port input data M J Read Serial interface 0
19. EI 0 7 40 to 85 Storage temperature 55 to 125 Applied to any 100 ms period Connect at least one bypass capacitor of 0 1 supply pin and the ground for latch up preve uF or larger between the power ntion The absolute maximum ratings are the limit values beyond which the LSI may be damaged I 19 Electrical Characteristics Chapter 1 Overview 1 5 2 Operating Conditions NORMAL mode fs fosc 2 SLOW mode fs fx 4 is for EPROM vers Ta 40 to 85 20 to 70 Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage 2 1 1 0 MHz lt fosc lt 20 0 MHz 45 5 5 2 1 0 MHz lt fosc lt 8 00 MHz 2 7 5 5 3 supply voltage 1 0 MHz lt fosc lt 4 20 MHz 2 3 5 5 4 1 0 MHz lt fosc lt 2 00 MHz Ba 55 Y 5 Voos 32 768 kHz lt fx lt 100 kHz 3 55 6 Voltage to maintain RAM data Vppe During STOP mode 1 8 5 5 Operation speed 3 7 tet 4 5 5 5 V 0 100 2 00 8 tc 2 7 V to 5 5 V 0 250 2 00 mor Teste Qon tos 2 3 V to 5 5 V 0 480 200 us execution time 10 tod 2 0 2 3 V to 55 V 100 2 00 11 tos 2 0 V 2 3 V to 5 5 V 400 122 1 EPROM vers is in 2 fosc the input clock frequency to OSC1 fx the input clock freq
20. j MUX buzzer S 1 29 Figure 2 5 3 Block Diagram of Oscillation Stabilization Wait Time watchdog timer Reset II 31 Chapter 2 Basic CPU Oscillation Stabilization Wait Time Control Register 7 6 5 4 3 2 1 DLYCTR BUZOE BUZCK1 BUZCKO DLYS1 DLYSO At reset 00 Oscillation stabilization DLYS1 DLYSO wait period selection 0 0 214 1 210 1 0 26 1 Do set stabilization wait Note After reset is released the oscillation period is fixed at fs 214 BUZCK1 BUZCKO frequency selection Buzzer output 15 212 15 211 15 210 15 29 Figure 2 5 4 Oscillation Stabilization Wait Time Control Register DLYCTR x 03F03 R W Control the Oscillation Stabilization Wait Time At recovering from STOP mode the bit 1 0 DLYS1 DLYSO of the oscillation stabilization wait time control register can be set to select the oscillation stabilization wait time from 2 219 26 x system clock BUZOE 06 output selection port data output P06 buzzer output The DLYCTR register is also used for controlling of buzzer functions At releasing from reset the oscillation stabilization wait time is fixed to 2 x system clock System clock 4 is determined by the CPU mode control register CPUM Table 2 5 1 2
21. tet m eee VI 17 6 5 1 Op ration ise ed mb dees hen hice VI 17 6 5 2 Setup Example 4 nte ee hie t e tee e eei VI 18 Added Pulse Type 16 bit PWM Output VI 20 6 6 1 Operation deed ER VI 20 6 6 2 Setup Example eee nIe bep epe VI 22 16 bit Timer Synchronous Output VI 24 6 7 1 Operation Jae teeth deere ter RT VI 24 6 7 2 Setup Example eren ie 25 16 bit Timer Capture eoe oer eie eH VI 27 6 8 1 Operation E UH VI 27 6 8 2 Setup Example p redde erre tte tre sper eee VI 29 Chapter7 Base Timer 8 bit Free running Timer 7 1 7 2 7 3 2 7 1 1 BUN CHONS 2 7 1 2 Block Diagram VII 3 Control Registers ie B eu rou VII 4 7 2 1 Control Registers nei hee ener ERG VII 4 7 2 2 Programmable Timer Registers sese 5 7 2 3 Timer gene eR eger ide ER E 6 8 bit Free running Timer esee err PRO pri VII 7 7 3 1 rU ORBI REUS VII 7 7 3 2 Setup Example den etn dt eed eg ees VII 10 Time Base Timer esee eb ptr e Rigi wie ee VII 12 7 4 1 Ope ratiOD s eer Pete a a ee APRES VII 12 7 4 2 setup Example 5 enc ede Uie VII 14 Chapter 8 Watchdog Timer contents 8 1 8 2 8 3 OVGIVIeW M bu S
22. x 3F84 1 to start timer 4 bp6 1 counts up from x 00 The PWM source waveform outputs until TMABCL reaches the set value of the TM4OCL register then after the match it outputs L After that TMABCL continues to count up once a overflow happens the PWM source waveform outputs H again and TM4BCL counts up from 00 again From the above setting the basic PWM waveform becomes 64 192 And the TM4OCH is set to x 07 in the PWM output repetitions 256 times the added pulse is appended 7 times and the duty becomes 65 191 For PWM operation x FF in TM4OCL produces the same result as x 00 constant low level output at the PWM4 pin not constant high Do not set x FF in TM4OCL Use 16 bit access instruction to set the TM4OCL register Added Pulse Type 16 bit PWM Output VI 23 Chapter 6 16 bit Timer 6 7 16 bit Timer Synchronous Output 6 7 1 Operation When the binary counter of the timer reaches the set value of the compare register the latched data is output from port 7 at the next count clock BSynchronous Output Operation by 16 bit timer Timer 4 The port 7 latched data is output from the output pin at the interrupt request generation by the match of the binary counter 4 and the compare register Only port 7 can perform synchronous output operation and individual pins can be set iCount Timing of Sync
23. 1 2 1 1 2 Product Surninary bine em dae rtr I 2 Hardware Functions heec eser tote pendere pe e ete I 3 Pins Description cree a re EH dee ink ree etui paese pee trt edes I 8 1 3 1 Pin Configuration aterert tee p Grip tere dr epis I 8 1 3 2 5 IRR ER I 9 1 3 3 Pin F nctions iiti ette re eed e eerte I 11 Block Diagram i eene epp ebenso I 18 1 4 1 Block Diagram th t ee emo I 18 Electrical Characteristics Gr RUE I 19 1 5 1 Absolute Maximum Ratings I 19 1 5 2 Operating Conditions iet eee rhe te I 20 1 5 3 DC Char cteristics notnenane tee I 23 1 5 4 AC Ch tracterlstics teret ad dece ta RE e I 27 1 5 4 Characteristics ieies 28 1 5 5 Bus Timing 0 wait states during Memory Expansion I 29 a 1 30 1 6 1 ROM Option vs 30 1 6 2 Option Check List 5p eae Ip 31 Package Dimension teet 32 Precautionsz RE 1 34 1 8 1 General Usage au sce I Ue git REESE I 34 1 8 2 Un sed Pins e e enne eme e t e I 35 1 8 3 Power Supply 2 ai ete ep E E R a e I 37 1 8 4 Power Supply Circuit I 38 1 8 5 Usage of Oscillator etre
24. If fx is selected as the count clock source in timer 5 when the binary counter is read at operation uncertain value on counting up may be read To prevent this select the synchro nous fx as the count clock source But if the synchronous fx is selected as the count clock source CPU mode cannot return from STOP HALT mode If the compare register is set smaller value than the binary counter s during the count opera tion the binary counter counts up to the overflow at first 8 bit Free running Timer VII 9 Chapter 7 Time Base Timer 8 bit Free running Timer 7 3 2 Timer Operation Setup Timer 5 Timer 5 generates an interrupt constantly for timer function fs 4 fosc 20 MHz is selected as a clock source to generate an interrupt every 250 dividing 100 us An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Enable the binary counter initialization TM5MD x 3F88 bp7 TM5CLRS 0 Select the clock source TM5MD x 3F88 bp3 1 5 1 001 Set the interrupt generation cycle 5 x 3F78 9 Enable the interrupt request generation TM5MD x 3F88 bp7 TM5CLRS 1 Set the interrupt level x 3FF0 bp7 6 TM5LV1 0 01 Enable the interrupt x 3FFO0 bp1 1 Set the TM5LRS flag of the timer 5 mode register T
25. b 1 2 duty 1 2 bias MN101C485 487 101 485 487 Pd ea Vice Vica V DN MNA 55 Lec SRAM R Vss Vss 1 3 duty 1 3 bias 1 4 duty 1 3 bias d 1 3 duty 1 3 bias 1 4 duty 1 3 bias 2 Vicp 3 MN101C485 487 101 485 487 WWW Vp Vict R VLCD R VLCD n Vice Vice R Vics Vics Pie een EIIE A ae 2R E EET EAA Vss Vss Figure 11 3 1 Examples of the LCD Power Supply Connection LCD Voltage Control Circuit XI 11 Chapter 11 LCD Functions 1 Figure 11 3 1 current always flows through the voltage divider resistors The following connection can be used to cut off the current flow through these dividing resistors 101 485 487 Vss Figure 11 3 2 Voltage Dividing Resistors with Current Cutoff 2 The LCD power supply is applied as shown below The specific value varies depending on the type of LCD used Refer to the LCD specifications to determine the correct value 1 3 Vic2 2 3 Vics VLCD Vpp are normally divided by resistors and supplied to the LCD Commonly used resistor values range between several tens to several hundreds kQ When VLCD VDD R is no need
26. 3 When the synchronous TMnlO input is selected as the count clock source the timer n counter counts up in synchronization with system clock therefore the correct value is always read But if the synchronous TMnlO is selected as the count clock source CPU mode cannot return from STOP HALT mode 8 bit Event Count 15 Chapter 5 8 bit Timers 5 4 2 iEvent Count Setup Example Timers 2 and 3 Setup Example If the falling edge of the TM2IO input pin signal is detected 5 times with using timer 2 an interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM2MD x 3F82 bp4 2 0 Set the special function to input P1DIR x 3F31 bp2 P1DIR2 0 Select the normal timer operation TM2MD x 3F82 bp3 STM2PWM 0 Select the count clock source TM2MD 3 82 bp2 0 TM2CK2 0 011 Set the interrupt generation cycle 2 x 3F72 x 04 Set the interrupt level TM2ICR x 3FE6 bp7 6 TM2LV1 0 10 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop timer 2 counting Set the P1DIR2 flag of the port 1 direction control register P1DIR to 0 to set P12 pin to input mode If it needs pull up resistor should be added Chapter 4 Port Function Set the TM2PWM flag of the TM2MD register 0 to select
27. iCount Timing of PWM Output at normal Timer 2 TMnEN flag Compare a Y N register i H H H Binary y 22 y y y 2 counter 00 01 N 1 jJ N 14 N 2 FE FF 00 01 4 NH Compare eri M match signal TMnIO output PWM output A B C Set time in the compare register lt PWM basic components overflow time of binary counter Figure 5 6 1 Count Timing of PWM Output at Normal PWM source waveform H while counting up from 00 to the value stored in the compare register B is L after the match to the value in the compare register then the binary counter continues counting up till the overflow C is again if the binary counter overflows 8 bit PWM Output V 21 Chapter 5 8 bit Timers iCount Timing of PWM Output when the compare register is x 00 Timer 2 Here is the count timing when the compare register is set to x 00 TMnEN flag Compare register i 00 muri pon counter TMnIO output always L PWM output Figure 5 6 2 Count Timing of PWM Output when compare register is x 00 iCount Timing of PWM Output when the compare register is x FF Timer 2 is the count timing when the compare register is set to x FF TMnEN flag Compare register Binary co TMnIO output PWM output Figure 5 6 3 Count Timing of PWM Output whe
28. MOVW d4 SP DWm mem16 d4 SP DWm 1110 0114 MOVW mem16 d4 SP gt Am 1110 010a d4 SP Am MOVW d8 SP DWm mem16 d8 SP DWm 1110 0114 MOVW d8 SP Am mem16 d8 SP gt Am 1110 010a mem16 d16 SP 2DWm 1110 001d MOVW d16 SP Am mem16 d16 SP Am 1110 000a MOVW abs8 DWm mem16 abs8 2DWm 1100 0114 MOVW abs8 A mem16 abs8 Am 1100 010a MOVW abs16 DWm mem16 abs16 2GDWm 1100 0114 MOVW d16 SP DWm MOVW abs16 Am mem16 abs16 5Am 1100 010a MOVW DWn Am DWn mem16 Am 1111 00aD MOVW An Am 16 1111 10 MOVW DWn d4 SP DWn gt mem16 d4 SP 1111 011D lt d4 gt MOVW An d4 SP gt 16 04 5 1111 010 lt d4 gt MOVW DWn d8 SP DWn gt mem16 d8 SP 1111 011D lt d8 MOVW An d8 SP gt 16 08 5 1111 010 lt 08 MOVW DWn d16 SP DWn gt mem16 d16 SP 1111 001D di6 MOVW An d16 SP 16 016 5 1111 000A 416 MOVW DWn abs8 DWn mem 1 6 abs8 1101 011D lt abs MOVW An abs8 An gt mem16 abs8 1101 010A lt abs MOVW DWn abs16 DWn gt mem16 abs16 1101 011D lt abs MOVW An abs16 Anmem16 abs16 1101 010A abs
29. XZ Read S x P20 P22 Port input data P2INO 2 FEN Read Schmitt input External interrupt Figure 4 4 2 Block Diagram P20 P22 nae 1659 E P2PLU1 Pull up resistor control D gt gt Write Read 5 Rese 5 P211M Special function input data o P21 Write A Read 1 AC zero cross detection circuiti P2IN1 Port input data U 0 Read X Schmitt input AC zero cross input External intrerrupt Figure 4 4 3 Block Diagram P21 Rese s P20UT7 Port output data 9 DQ Write d 7 7 P27 Reset signal input lt Schmitt input Pull up resistor is always added Figure 4 4 4 Block Diagram P27 16 Port2 Chapter 4 Ports 4 5 Port5 4 5 1 Description Port Setup Each bit of the port 5 control I O direction register P5DIR can be set individually to set pins as input or output The control flag of the port 5 direction control register P5DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 5 direction control register P5DIR to 0 and read the value of the port 5 input register P5IN To output data to pin set the control flag of the
30. register the timer 2 interrupt request flag is set at the next count clock then the value of the TM2BC becomes 00 and restart to count up When the TMnEN flag of the TMnMD register is changed at the same time to other bit binary counter may count up by the switching operation The initial value of the TM3CK2 0 in the TM3MD register is indefinite When timer 2 timer 3 is used independently set any mode except cascade connection E If fx is selected as the count clock source in timer 2 when the binary counter is read at operation uncertain value on counting up may be read To prevent this select the synchro nous fx as the count clock source In this case the timer 2 counter counts up in synchroniza tion with system clock therefore the correct value is always read But if the synchronous fx is selected as the count clock source CPU mode cannot return from STOP HALT mode 8 bit Timer Count V 13 Chapter 5 8 bit Timers 5 4 8 Event Count 5 4 1 Operation Event count operation has 2 types TMnIO input and synchronous TMnIO input can be selected as the count clock B8 bit Event Count Operation Event count means that the binary counter TMnBC counts the input signal from external to the TMnlO pin If the value of the binary counter reaches the setting value of the compare register TMnOC inter rupts can be generated at the next count clock Table 5 4 1 Event Count Input Clo
31. 2 a Am 76 4 sign extension d DWm 7 8 sign extension 4 D DWk 8 zero extension 21 Instruction Set Chapter 13 Appendices MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Machine Code 6 7 8 Dn2Dn Dn msbtemp Dn lsb CF Dn gt gt 1 Dn temp Dn msb Dn lsb gt CF Dn gt gt 1 Dn 0 Dn msb Dn Isbotemp Dn 1 Dn CFDn msb tempCF Bit manipulation instructions BSET BSET io8 bp mem8 IOTOP io8 amp bpdata PSW 0 e 0 e 5 5 0011 1000 i8 gt 1 meme8 IOTOP io8 bp BSET abs8 bp mem8 abs8 amp bpdata PSW 414 1011 abs 8 gt 1 mem8 abs8 bp BSET abs16 bp mem8 abs16 amp bpdata PSW 01 7 6 0011 1100 abs 16 gt 1 mem8 abs16 bp BCLR BCLR io8 bp mem8 IOTOP io8 amp bpdata PSW 0 0 e 5 5 0011 1000 16 i8 gt 0 mem8 IOTOP io8 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW ole 4 4 1011 1bp lt abs 8 gt 0 mem8 abs8 bp BCLR abs16 bp mem8 abs16 amp bpdata PSW 01 01676 0011 1100 1bp abs 16 gt 0 memg8 abs16 bp BTST BTST imm8 Dm Dm amp imma8 PSW 01 0 5 3 0010 0000 11Dm lt 8 BTST abs16 bp mem8 abs16 amp bpdata PSW 016 7 5 0011 1101 abs 16 gt Branch instructions Bcc BEQ label if ZF 1 PC 3 d4 label HOPC
32. Interrupt Enab xxxlR Interrupt Request Interrupt Block Diagram 3 1 3 Operation Wilnterrupt Processing Sequence Chapter3 Interrupts For interrupts other than reset the interrupt processing sequence consists of interrupt request interrupt acceptance and hardware processing The program counter PC and processor status word PSW and handy addressing data HA are saved onto the stack and execution branches to the address specified by the corresponding interrupt vector An interrupt handler ends by restoring the contents of any registers used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was inter rupted Interrupt service routine Main program DS Hardware processing Save up PC PSW etc Interrupt 12 machine cycles 11 machine cycles Restart Restore PSW PC up etc RTI Interrupt request xxxIR flag cleared at head Figure 3 1 2 Interrupt Processing Sequence maskable interrupts Non maskable interrupts have priority over maskable ones Overview 5 Chapter 3 Interrupts Sources and Vector Addresses Here is the list of interrupt vector address and interrupt group Table 3 1 2 Interrupt Vector Address and Interrupt Group Vector Vector Interrupt group Control Regist
33. MOVW DWn HA DWn mem 16 HA 1001 010D MOVW An HA 16 1001 011 MOVW imm8 DWm Sign imm8 2CDWm 0000 110d MOVW imm8 Am zero imm8 Am 0000 111a MOVW imm16 DWm 16 gt 20 Instruction Set B MIO Og aAlN alo N a wji wl alaja vj ajaja aloo o olco 1100 1114 1 d8 sign extension 2 44 zero extension 3 48 zero extension 4 5 8 sign extension 6 8 zero extension MN101C SERIES INSTRUCTION SET Mnemonic Operation Chapter 13 Appendices Machine Code 6 7 8 MOVW imm16 Am imm16 5Am 1101 111a H6 MOVW SP Am 0000 100 MOVW An SP An SP 0000 101A MOVW DWn DWm DWn DWm 1000 00Dd MOVW DWn Am DWn Am 0100 11Da MOVW An DWm An gt DWm 1100 11Ad MOVW An Am gt 0000 00Aa PUSH Dn SP 1 SP Dn mem amp SP 1111 10Dn PUSH An 5 2 gt 5 gt 16 5 0001 011 Dn mem8 SP gt Dn SP 1 SP 1110 10Dn POP An mem16 SP An SP 2 SP 0000 011A A
34. SCOORE At reset 00 000 SCOORE Overrun error detection 0 No error 1 Error SCOPEK Parity error detection 0 No error 1 Error SCOFEF Framing error detection 0 No error 1 Error Clock synchronous EUMD UART selection 0 Clock synchronous 1 UART SCOBSY Serial bus status 0 Other use 1 Serial transmission in progress Figure 10 2 7 Serial Interface 0 Control Register SCOCTR x 03F54 R W X 10 Control Registers Chapter 10 Serial Interface 0 10 3 Operation Serial Interface 0 can be used for both clock synchronous and half duplex UART 10 3 1 Clock Synchronous Serial Interface Selection of Clock Synchronous Serial Interface When the serial interface 0 is used as clock synchronous serial interface set the SCOCMD flag of the serial interface control register SCOCTR to 0 Activation Factor for Communication Table 10 3 1 shows activation factors for communication At master the transfer clock is generated by setting data to the transmission reception shift register SCOTRB or by receiving a start condition At slave input an external clock or input an external clock after a start condition is input Table 10 3 1 Synchronous Serial Interface Activation Factor ue Sequence Operation mode Activation factor c5mmunication Enable start condition Writing data to serial
35. Set the LCDEN flag of the LCD mode control register LCMD to 0 to stop the LCD operation Set LC1SEL flags of the LCD mode control register LCMD to 0 to switch into the static driver mode Set 2 as the LCD clock source by to 0 flags of the LCD mode control register LCMD Select SEGO 7 by the SEGSEL6 0 flag of the output control register LCCTR Set display data 2 by the segment output latch SEGO to 7 X 3FBD to e Chapter 11 11 4 1 LCD Display Examples Static Set the LCDEN flag of the LCD mode control register LCMD to 1 to start the LCD operation XI 16 LCD Function Operation Chapter 11 LCD Functions LCD Function Operation 17 Chapter 11 LCD Functions 11 4 3 LCD Display Examples 1 2 Duty 81 2 Duty 101 485 487 Segment Latch x 3FCO x3FBE x 3FBD x 3FBD bit7 bit3 open bit6 bit2 open bit5 bit1 bit4 bitO A electrode B electrode iit not lit LCD PANEL LCD ON COM S COM 5 N LCD OFF SEG SEG SEG SEG N LCD clock undefined Data EN o undefined Voo COM Vica SEG Vict Vice Vics Vico 1 2 Vicp COM SEG 0 1 2 Vico Vicb Lit Not lit Not lit Not lit Not lit S selective vo
36. XI 8 LCD Control Registers Chapter 11 LCD Functions 11 2 4 Segment Output Latch The segment output latch stores the LCD display data A 4 bit latch is assigned to every single segment and bit4 are read in synchronization with the timing of COMO bit1 and bit5 with COM1 bit2 and bit6 with COM2 and bit3 and bit7 with If the content is 1 the segment pin outputs the selective voltage If O non selective voltage is output Addresses are assigned within the range of to x 3FC9 Data read and write operations can be performed in the same way as for RAM access At reset the value of the segment output latch is undefined The correspondence between the segment output latch and the segment common pins is shown in Figure 11 2 3 OMS 52 COM2 1 one address 0 7 bit6 bits bit3 bit2 bit bitO SEG1 P81 lt SEGO P80 SEG3P83 SEG2 P82 SEG5 PB5 tt SEGA4 P84 x 3FCO SEG7P87 SEGO P86 x3FC1 SEG9P76 SEG8 P77 X 3FC2 SEG11 P74 1 SEG 10 P75 SEGI3P72 1014010 SEG12 P73 x 3FC4 gt SEG15 P70 1 1 SEG X3FC5 StGt7P66 i SEGI6 P67 x 3FC6 SEGIgP64 1 1 1 gt 5 5 7 gt 5 621 62 1 SEG20 P63 x3FC8 SEG23P60 22 61
37. mended Program Read High temperature storage 125 48h Mounting 1 1 EPROM Version XIII 3 Chapter 13 Appendices 13 1 3 Erasing Data in Windowed Package PX AP101C48 FBC FHC To erase data an internal EPROM with windowed packaging 0 gt 1 UV light at 253 7 nm is used to irradiate the chip through a permeable cover The recommended exposure is 10 W s cm This coverage can be achieved by using a commercial UV lamp positioned 2 to 3 cm above the package for 15 20 minutes when the illumination intensity of the package surface is 12000 uW cm Remove any filters attached to the lamp With a mirrored reflector plate to the lamp illumination intensity will increase 1 4 to 1 8 times and decrease the erasure time If the window becomes dirty with oil adhesive etc UV light permeability will get worse causing the erasure time to increase If this happens clean with alcohol or another solvent that will not harm the package The above recommended exposure has enough leeway with several times as much as it takes to erase all the bits It is based on the reliable data over all temperature and voltage The lump and the level of illumination should be regularly checked and well controlled Data in internal EPROM with windowed packaging is erased by applying a light that the wavelength is shorter than 400 nm Fluorescent lamp and sunlight are not able to erase data as much as UV light of 253 7 nm is bu
38. 0010 DnDm imm8 Dm Dm imm8 PSW 1100 00Dm imm8 abs8 mem8 abs8 imm8 PSW 0000 0100 imm8 abs12 mem8 abs12 imm8 PSW 0000 0101 imm8 abs16 mem8 abs16 imm8 PSW 1101 1000 PW DWn DWm DWm DWn PSW 1000 01Dd PW DWn Am Am DWn PSW 0101 11Da PW An Am Am An PSW 0000 01Aa PW imm16 DWm DWm imm16 PSW 1100 110d PW imm16 Am Am imm16 PSW 9 0 0 olo ojojoluuo oloo g vi wj wl wl uu 02 1101 110a Logical manipulation instructions AND AND Dn Dm Dm amp Dn Dm 01 0 2 0011 0111 DnDm AND imm8 Dm Dm amp imm8 5Dm 0 4 2 0001 11Dm lt 8 gt AND imm8 PSW PSW amp imm8 gt PSW 53 0010 1001 0010 lt 8 gt OR OR Dn Dm DmIDn gt Dm 0 9 3 2 0011 0110 DnDm imm8 Dm Dmlimm8 gt Dm 4 2 0001 10Dm lt 8 OR imm8 PSW PSWlimm8 2PSW 3 0010 1001 0011 lt 8 XOR XOR Dn Dm Dm Dn gt Dm 0le 0e 3 2 0011 1010 DnDm imm8 Dm Dm imm8 Dm 0 0 5 0011 1010DmDm lt 8 _ gt 1 D DWn d DWm 5 D DWm 79
39. 65 BNC label if NF 0 PC 5 d7 label H 3PC 5 3 4 0010 0010 0100 d7 1 5 BNC label if NF 0 PC 6 d11 label H 3PC 3 4 0010 0011 0100 lt 011 3 if NF 1 PC 62PC BNS labe if NF 1 PC 5 d7 label H 3PC 5 3 4 0010 0010 0101 d7 if NF 0 PC 5PC BNS labe if NF 1 PC 6 d11 label H PC 3 4 0010 0011 0101 lt d11 3 if NF 0 PC 6PC BVC labe if VF 0 PC 5 d7 label HPC 5 3 4 0010 0010 0110 lt d7 if VF 1 PC 53PC label if VF 0 PC 6 d11 label H gt PC 6 3 4 0010 0011 0110 lt d11 H 3 if VF 1 PC 69PC BVS label if VF 1 PC 5 d7 label HPC 5 3 4 0010 0010 0111 lt d7 if VF 0 PC 5PC BVS label if VF 1 PC 6 d1 6 3 4 0010 0011 0111 dti sH 8 if VF20 PC 62PC BRA label PC 3 d4 label H PC 3 1110 111H lt d4 gt 4 BRA label PC 4 d7 label H PC 4 1000 1001 d7 2 BRA label PC 5 d11 label H PC 5 1001 1001 lt 11 3 CBEQ imm8 Dm label if Dm imm8 PC 6 d7 label H PC amp 6 3 4 1100 10Dm 48 gt d7 2 8 6 CBEQ imm8 Dm label if Om imm8 PC 8 d1 1 5 e 8 45 0010 1100 10Dm lt 8 gt lt d11 H 3 if Dm4imm8 PC 82PC CBEQ imm8 abs8 label lif mem8 abs8 imm8 PC 9 d7 label HPC 9 6 7 0010 1101 1100 abs 8 4 8 gt d 2 if mem8 abs8 4imm8 PC 9 PC CBEQ imm8 abs8 label _ if mem8 abs8 imm8
40. Analog 2 input KEY2 KEY interrupt input 2 KEYS in PAPLUDS AN3 Analog 3 input KEYS KEY interrupt input 3 PA4 KEY4 in PAPLUD4 AN4 Analog 4 input KEY4 KEY interrupt input 4 AN5 KEY5 in s PAPLUDS AN5 Analog 5 input KEY5 KEY interrupt input 5 AN6 KEY6 in PAPLUDS6 AN6 Analog 6 input KEY6 KEY interrupt input 6 AN7 KEY7 in PAPLUD AN7 Analog 7 input KEY7 KEY interrupt input 7 COMO out COMO LCD common output 0 COM1 out COM LCD common output 1 2 out LCD common output 2 out LCD common output 3 1 10 Pin Description 1 3 3 Pin Functions Chapter 1 Table 1 3 3 Pin Function Summary 1 7 sName No 100 pin yo Other Function Function Description Vss VDD Power supply pin Supply 2 0 to 5 5 to and 0 to Vss OSC1 OSC2 Input Output Clock input pin Clock output pin Connect these oscillation pins to ceramic or crystal oscillators for high frequency clock operation If the clock is an external input connect it to OSC1 and leave OSC2 open The chip will not operate with an external clock when using either the STOP or SLOW modes Xl XO 12 13 Input Output Clock input pin Clock output pin Connect these oscillation pins to crystal oscillators for low frequency clock operation If the clock is an external input connect it
41. LCD Function Operation XI 25 Chapter 11 LCD Functions 11 4 7 LCD Display Examples 1 4Duty 1 4 Duty 101 485 487 Segment Latch x 3FC9 x 3FBE x 3FBE x 3FBD x 3FBD bit7 bit3 COM3 bit6 bit2 bit5 bit1 bit4 bitO A electrode B electrode notiit LCD PANEL LCD ON COM N LCD OFF SEG S SEG 5 SEG SEG LCD clock undefined Data 0 undefined Vict Vics COM Vict Vic2 Vica SEG Vi COM SEG 1 3 0 1 3 Vico Lit Not lit Not lit Not lit Not lit S selective voltage non selective voltage Vuco LCD driver voltage XI 26 LCD Function Operation LCD Functions Chapter 11 frame cycle 1 4 Duty Driving Waveform COM3 COM2 COMO SEG3 41 3 5 lt 1 3 2 e 2 1 3 B electrode COM1 SEG3 1 3 Figure 11 4 4 LCD Display Example 1 4 Duty XI 27 LCD Function Operation Chapter 11 LCD Functions 11 4 8 Setup Example 1 4 Duty Setup Example of the LCD Function Operation 1 4 Duty Segment signal SEGO to SEG3 and common signal COMO to at the
42. MAX SENS pin 1 Rising time tr 30 Fig 1 5 5 us 2 Falling time 30 ie tro i tio Input voltage level 1 M Pte Input Input voltage level 2 gt Output Figure 1 5 5 AC Zero cross Detector Electrical Characteristics 1 27 Chapter 1 Overview 1 5 5 A D Converter Characteristics 25 5 0 V Vss 0V 8 EPROM vers is Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 10 Bits 2 Non linearity error 1 5 0 V Vss 0V 3 F VREF 5 0 V VREF 0 V LSB 3 Differential non linearity Tan 1 00 us 3 error 1 4 Zero transition voltage 5 0 V Vss 0V 30 100 VREF 5 0 VREF 0 V mV 5 Full scale transition voltage TAD 1 00 us 4900 4970 6 fosc 8 MHz TAD 1 00 us 12 28 A D conversion time X 7 09 Kiz 183 12 427 28 TAD 15 2 us us 8 fosc 8 MHz TaD 1 00 us 2 0 18 0 Sampling time fx 32 768 kHz 9 Tap 15 2 us 30 52 274 68 10 VREF 9 2 0 Reference voltage 11 VREF 9 Vss 3 0 V 12 Analog input voltage VREF VREF Analog input leakage VADIN 2 0 V to 5 0 V 13 2e current unselected channel 14 Reference voltage Ladder resistor OFF 10 input leakage current VREF lt VREF lt VDD 15 Ladder resistance 20 50 80 8 TAD means A D conversion clock cycle The val
43. Oscillation characteristics The combination of oscillator and each version should be estimated to match when EPROM version is changed to Mask ROM version for mass production a EMC check should be done on each version when EPROM version is changed Noise characteristics to Mask ROM version for mass production There are no other functional differences Data for ROM option setting is used as Data for EPROM option setting is option data used as option data EPROM Version XIII 5 Chapter 13 Appendices 13 1 5 Writing to Microcomputer with Internal EPROM The device type that set by each ROM writer should be selected the mode for writing 256 k bit EPROM Set the writing voltage to 12 5 V iMounting the device in the programming adapter and the position of the No 1 pin No 1 pin of the device must be matched to this position Package Product name 64 LQFP OTP64LF14 101CP48 64 TQFP OTP64HT10 101CP48 No 1 Pin No 1 Pin Y side view top view MN101CP487 PX AP101C48 FBC Figure 13 1 1 Mounting a Device in Programming Adapter and the Position of No 1 Pin XIII 6 EPROM Version Chapter 13 Appendices Writer Setup The device types should be set up as listed below Table 13 1 2 Setup for Device Type Device type Remarks Hitachi 27C256 Mitsubishi 27C256 Hitachi 27C256 Mitsubishi 27C256 Hitachi 27 256 Do not run ID check and pin connection Mitsubishi 27C256 inspect
44. Pana Series The One toWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER MN101C MN101C485 487 LSI User s Manual Pub No 21448 028E Panasonic PanaX Series is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations 1 2 3 4 5 Request for your special attention and precautions in using the technical informaition and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specification Ask for the latest individual Product Standards or Specifications in advance fo
45. Ports 0 to 2 5 to 8 and A are controlled by the data output register PnNOUT the data input register PnIN the I O direction control register PnDIR the pull up resistor control register PnPLU and the pull up pull down resistor control resister PnPLUD and registers SYSMD P1OMD PAIMD P4IMD EXADV FLOAT1 FLOAT2 LCCTR that control special function pin This I O control is valid at selection of the special function as well Table 4 1 3 shows the registers to control ports 0 to 2 5 to 8 and A Table 4 1 2 Port Control Registers List 1 2 Register Address R W Function Page POOUT x 03F10 R W Port 0 output register IV 7 Bodo POIN x 03F20 Port 0 input register IV 7 PODIR x O3F30 R W Port 0 direction control register IV 7 POPLU x O3F40 R W Port 0 pull up resistor control register IV 7 P1OUT X 03F 11 R W Port 1 output register IV 11 P1IN x 03F21 Port1 input register IV 11 Port 1 P1DIR X 03F31 R W Port 1 direction control register IV 11 P1PLU x O3F41 R W Port 1 pull up resistor control register IV 11 1 x 03F39 R W Port 1 output mode register IV 12 2 X 03F 12 R W Port 2 output register IV 15 Port 2 P2IN X 03F22 Port 2 input register IV 15 P2PLU x O3F42 R W Port 2 pull up resistor control register IV 15 P5OUT X 03F15 R W Port 3 output register IV 18 P5IN x O3F25 Port input regist
46. SCOFEF Framing error Stop bit is not detected X 32 Operation Chapter 10 Serial Interface 0 mJudgement of Break Status Reception Reception at break status can be judged If all received data from start bit to stop bit is 0 the SCOBRKF flag of the SCOMD1 register is set and regard the break status The SCOBRKF flag is set at generation of the reception complete interrupt SCOIRQ Selection of Start Condition The SCOSTE flag of the SCOMDO register is originally to select start condition of the synchronous serial data communication When serial interface 0 is used as half duplex UART serial interface set the SCOSTE flag always to 0 to prevent the following errors Caution At UART communication set the SCOSTE flag of the SCOMD register to 0 Error At UART transmission when the SCOSTE flag is 1 start bit becomes H at the 2nd trans mission and after At synchronous serial data transmission as the SCOSTE flag 1 High level after transmission Normal operation at synchronous mode Start condition P00 SBOO TXD Shift register output POO H output control Source clock fs 2 fs 4 fs 16 Timer 3 output Transfer clock At UART transmission as the SCOSTE flag 1 Error operation at UART mode P00 SBO0 TXD X y Start bit Shift register output A POO H output cont
47. The set value should be 1000 1 999 x 03E7 Set the interrupt level by the TM4LV1 0 flag of the timer 4 interrupt control register TM4ICR If any interrupt request flag had already been set clear it Chapter 3 3 1 4 Interrupt Flag Setup Set the TM4IE flag of the TM4ICR register to 1 to enable the interrupt Set the TM4EN flag of the TM4MD register to 1 to start timer 4 TM4BC counts up from x 0000 When TM4BC reaches the set value of the TM4OC register the timer 4 interrupt request flag is set to 1 at the next count clock and the TM4BC becomes x 0000 and counts up again 16 bit Timer Count VI 11 Chapter 6 16 bit Timer When the TM4EN flag of the TM4MD register is changed at the same time to other bit binary counter may count up by the switching operation If the value of the and TM4OCL register are rewritten when the timer 4 is stopped the timer 4 binary counter becomes x 0000 But even if the TM4EN flag of the operating timer is cleared to 0 it doesn t stop until the count edge of the next clock Therefore during max 1 count clock after the TM4EN is cleared the binary counter cannot be initialized 12 16 bit Timer Count Chapter 6 16 bit Timer 6 4 16 bit Event Count 6 4 1 Operation Event count operation has 2 types TM4IO input and synchronous TM4IO input can be selected as the count clock W16 bit Event Count Operation
48. 0 3 Select the count clock source TM2MD 3 82 bp2 0 TM2CK2 0 001 4 Set the cycle the interrupt generation 2 x 3F72 9 5 Set the interrupt level TM2ICR x 3FE6 bp7 6 TM2LV1 0 10 6 Enable the interrupt TM2ICR x 3FE6 bp1 TM2IE 1 2 Select the normal timer operation Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the counting of timer 2 Set the TM2PWM flag of the TM2MD register to 0 to select the normal timer operation Select fs 4 to the clock source by the TM2CK2 0 flag of the TM2MD register Set the value of the interrupt generation cycle to the timer 2 compare register TM2OC The cycle is 250 so that the setting value is set to 249 9 At that time the timer 2 binary counter TM2BO is initialized to 00 Set the interrupt level by the TM2LV1 0 flag of the timer 2 interrupt control register TM2ICR If any interrupt request flag had already been set clear it 4 _ Chapter 3 3 1 4 Interrupt flag setting Set the TM2IE flag of the TM2ICR register to 1 to enable the interrupt V 12 8 bit Timer Count Chapter 5 8 bit Timers Setup Procedure Description 7 Start the timer operation 7 Set the TM2EN flag of the TM2MD register to TM2MD x 3F82 1 to start the timer 2 bp4 TM2EN 1 The TM2BC starts to count up from x00 When the TM2BC reaches the setting value of the 2
49. 15 Start the serial interface communication SCOTRB x 3F55 6 Set the SCOFM1 0 flag of the SCOMD2 register to 11 to select 8 bits data 2 stop bits at the frame mode 7 Set the SCOBRKE flag of the SCOMD2 register to 0 to select serial data transmission 8 Set the SCOSBOM flag of the SCOMD3 register to 1 to select N ch open drain for the TXD pin Set the POPLUO flag of the POPLU register to 0 not to add pull up resistor 9 Set the SCOIOM flag of the SCOMDS register to 1 to set the SBOO to transmission reception port Set the PODIRO flag of the PODIR register to 1 to set POO to output mode 10 11 Select the interrupt level by the SCOLV1 0 flag of the serial interface 0 interrupt control register SCOICR 12 Set the SCOIE flag of the SCOICR register to 1 to enable the interrupt request If any interrupt request flag had already been set clear it la Chapter 3 3 1 4 Interrupt Flag Setup 13 Set the baud rate timer by the TM3MD register register And set the TM3EN flag to 1 to operate timer 3 Chapter 5 5 8 Serial interface transfer clock output Set the SCOSBOS flag of the SCOMD3 register to 1 to set the serial interface communication 14 Set the transfer data to the SCOTRB register And the serial interface communication is started 15 Operation 43 Chapter 10 Serial Interface 0
50. 16 bit Timer Pulse Output Chapter 6 16 bit Timer counts up from 0000 If TM4BC reaches the set value of the 4 register and TM4BC is cleared to x 0000 the signal of the TM4IO output is inverted and TM4BC counts up from x 0000 again Set the compare register value as follows The timer pulse output cycle The compare register value 1 The count clock cycle x 2 16 bit Timer Pulse Output VI 19 Chapter 6 16 bit Timer 6 6 Added Pulse Type 16 bit PWM Output 6 6 1 Operation In the added pulse method 16 bit PWM output a 1 bit output is appended to the basic component of the 8 bit PWM output and the output is from TM4IO Precise 16 bit control is possible based on the number of PWM repetitions 256 times to which this bit is appended Added Pulse Type 16 bit PWM Output Timer 4 The lower 8 bits of the compare register TM4OCL set the duty H period of the basic PWM waveform and the upper 8 bits of the compare register set the added pulse position The cycle of the basic PWM waveform is the period of the full count overflow in the lower 8 bits of the binary counter TM4BCL Table 6 6 1 shows the PWM output pin Table 6 6 1 PWM Output Pin Timer 4 output pin P14 PWM output pin Added Pulse Type PWM Output Timer 4 PWM basic components Added pulse gt Added pulse Tn x 00 01 Tn2x02 03 Tn x
51. 6 160 X83 0 X43 0 X93 0 XS84 0 Xv3 0 X 4 0 Xe3 0 X13 0 X03 0 II 15 Memory Space Chapter 2 CPU Basics 2 3 Bus Interface 2 3 1 Bus Controller The MN101C series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads Therefore this series realizes faster operation There are four such buses ROM bus RAM bus peripheral expansion bus I O bus and external expansion bus They connect to the internal ROM internal RAM internal peripheral circuits and external interfaces respectively The bus control block controls the parallel operation of instruction read and data access the access speed adjustment for low speed external devices A functional block diagram of the bus controller is given below Instruction queue Program address Operand address Bus controller Interrupt control Address decode Memory control register Bus arbitor Memory mode setting Bus access wait control External interface Figure 2 3 1 External extension bus A D RAM bus Internal RAM Interrupt bus Peripheral extension bus Internal peripheral functions Functional Block Diagram of the Bus Controller In memory expa
52. Cautions on use of the internal EPROM Erasing Data in Windowed Package PX AP101C48 FBC FHC Differences between mask ROM version and EPROM version Writing to the Microcomputer with internal EPROM Cautions on handling a ROM writer Programming Adapter Connection Option bit XIII 2 EPROM Version Chapter 13 Appendices 13 1 2 Cautions on Use EPROM Version differs from the 101 487 485 Mask ROM Version in some of its electrical character istics The user should be aware of the following cautions 1 To prevent data from being erased by ultraviolet light after a program is written affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU 101 48 PX AP101C48 FHC 2 Because of device characteristics of the MN101CP48xxx a writing test cannot be performed on all bits Therefore the reliability of data writing may not be 100 ensured 3 When a program is being written be sure that power supply 6 V is connected before applying the Ver power supply 12 5 V Disconnect the Ver supply before disconnecting the Voo supply 4 should never exceed 13 5 V including overshoot 5 If a device is removed while a of 12 5 is applied device reliability may be damaged 6 At NCE Vi do not change Vpp from to 12 5 V or from 12 5 to 7 After a program is written screening at a high temperature storage before mounting is recom
53. F Read Rese P1DIRO direction control gt gt Write CK Read y ro S Reset z R P1OUTO J gt u Port output data c 5 1 U Write CK Read X 7 7 Rese P10TCO Output mode control t Write F Read Schmitt input Port input data 4 P1INO SX Read Timer input Remote control carrier output Figure 4 3 3 Block Diagram P10 PS Rese P1PLU2 4 Pull up resistor control B Write Read m P1DIR2 4 direction control o gt Write Read y A lt P12 P14 Rese 5 P1OUT2 4 M gt Port output data 0 U 5 Write Read 1 X 777 Rese P12 14TCO Output mode control Write Read Schmitt input P1IN2 4 pus Port input data N TN Read Timer input Timer output Figure 4 3 4 Block Diagram P12 to P14 Pot IV 13 Chapter 4 Ports 4 4 Port2 4 4 1 Description General Port Setup Port 2 is input port except P27 To read input data of pin read out the value of the port 2 input register P2IN P27 is reset pin When the software is reset write the bp7 of the port 2 output register P2OUT to The port 2 pull up resistor control register P2PLU can select if port 2 is added pull up resistor or not by each bit When the control flag of the port 2 pull up resistor control register P2PLU is set to 1 pull up res
54. IRQ1LV1 0 10 Enable the interrupt IRQ1ICR x 3FES bp1 1 1 Set the REDG1 flag of the external interrupt 1 control register IRQ1ICR to 1 to specify the active edge of the external interrupt to rising Select the noise filter by the NF1EN NFCKS1 0 flag of the noise filter control register NFCTR And select fs 2 for its sampling cycle Set the P211M flag of the pin control register 1 FLOAT1 to 1 to select the AC zero cross detector signal as the external interrupt 1 generation factor Set the interrupt level by the IRQ1LV 1 0 flag of the IRQ1ICR register If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt flag setup Set the IRQ1IE flag of the IRQ1ICR register to 1 to enable the interrupt When the input signal level from P21 SENS pin crosses 1 2 VDD the external interrupt 1 is gener ated Chapter 4 Ports Chapter 4 Ports 4 1 Overview 4 1 1 10 Port Diagram A total of 71 pins on this LSI including those shared with special function pins are allocated for the 9 ports of ports 0 to 3 ports 5 to 8 and port A Each I O port is assigned to its corresponding special function register area in memory I O ports are operated in byte or bit units in the same way as RAM gt P00 TXD SBO0 SEG23 A0 P60 gt Port0 P01 RXD SBIO SEG22 A1 P61 9 4 gt l P02 SBTO SEG21 A2 P62 gt gt P06
55. NCS NRE gt NRE NWE gt NWE Figure 2 3 7 SRAM Connection Example Bus Interface 21 Chapter 2 CPU Basics 2 4 Standby Function 2 4 1 Overview The MN101C48 series has two sets of system clock oscillator high speed oscillation low speed oscilla tion for two CPU operating modes NORMAL and SLOW each with two standby modes HALT and STOP Power consumption can be decreased with using those modes CPU operation mode STANDBY mode Interrupt NORMAL mode Program 5 NORMAL Reset OSC Oscillation XI Oscillation Interrupt HALT 0 3 E OSC Oscillation3 Oscillation 3 Program 4 Program 3 STOP mode IDLE OSC Oscillation XI Oscillation Program1 HALT mode Program 2 Interrupt Hat SLOW XI Halt OSC Halt Program 5 XI Oscillation Interrupt 3 SLOW mode E OSC Halt EXI Oscillation 5 Program 4 CPU halt Wait period for oscillation stabilization is inserted OSC High frequency oscillation clock Low frequency oscillation clock 32 Figure 2 4 1 Transition Between Operation Modes II 22 Standby Functions Chapter 2 CPU Basics BHALT Modes HALTO HALT1 The CPU stops operating But both of the oscilla
56. PC 10 d1 10 6 7 0010 1101 1101 abs 8 gt lt 8 gt lt d11 3 if mem8 abs8 4Zimm8 PC 102 PC CBEQ imm8 abs16 label il mem8 abst6 imm8 PC 11 d7 label eHPC e 11 7 8 0011 1101 1100 lt abs 16 gt lt gt 4 2 if mem8 abs16 4imm8 PC 113PC CBEQ imm8 abs16 label _ if mem8 abs16 imm8 PC 12 d11 label H PC 12 7 8 0011 1101 1101 lt abs 16 e lt 2 dii if mem8 abs16 4imm8 PC 12PC CBNE CBNE imm8 Dm label if Dm imm8 PC 6 d7 label H PC e 6 3 4 1101 10Dm lt 8 gt 47 H 2 if Dmzimm8 PC 62PC CBNE imm8 Dm label if Dm4imm8 PC 8 d11 label H PC 8 45 0010 1101 10Dm lt 8 gt lt d11 SH 3 if Dmzimm8 PC 82PC CBNE imm8 abs8 label lif mem8 abs8 Zimm8 PC 9 d7 label H3PC 9 6 7 0010 1101 1110 abs 8 8 gt 47 2 if mem8 abs8 imm8 PC 95PC CBNE imm8 abs8 label if mem amp abs Zimm8 10 011 e 10 6 7 0010 1101 1111 abs 8 gt lt 8 gt dil zb if mem8 abs8 imm8 PC 102PC CBNE imm8 abs16 label f mem8 abst6 simm8 PC 11 d7 label H 9PC 11 7 8 0011 1101 1110 lt abs 16 gt lt gt dz if mem8 abs16 imm8 PC 1 1 2PC CBNE imm8 abs16 label if mem8 abs16 4imm8 PC 12 d1 label H PC 12 7 8 0011 1101 1111 lt abs 16 gt lt gt didi oH 13 if mem8 abs16 imm8 PC 122 PC TBZ TBZ abs8 bp label if mem8 abs8 bp 0 PC 7 d7 label H PC 0 7 6 7 0011 0
57. Pin Configuration 100QFP LQFP Top view Figure 1 3 1 Pin Description I 8 Chapter 1 Overview 1 3 2 Pin Specification Table 1 3 1 Pin Specification 1 2 Pins Special Functions Functions Description SBOO TXD in out PODIRO POPLUO SBOO Serial Interface O transmission data output TXD UART transmission data output 01 SBIO RXD in out PODIR1 POPLU SBIO Serial Interface 0 reception data input RXD UART reception data input P02 SBTO in out PODIR2 POPLU2 Serial Interface 0 clock I O NDK BUZZER in out PODIR6 POPLU6 Data acknowledge signal BUZZER Buzzer output P10 in out P1DIRO P1PLUO RMOUT Remote control carrier output P12 TM2IO in out P1DIR2 P1PLU2 TM2IO Timer 2 in out P1DIR3 P1PLUS Timer 3 P14 TM4IO in out P1PLUA Timer 4 P20 IRQO in P2PLUO IRQO External interrupt 0 P21 IRQ1 SENS in P2PLU1 IRQ1 External interrupt 1 SENS Zero cross input P22 IRQ2 in P2PLU2 1 2 External interrupt 2 P27 NRST in M NRST Reset P50 NWE LEDO in out P5DIRO P5PLUO NWE Write enable signal LED Driving pin 0 51 NRE LED1 in out P5DIR1 P5PLU1 NRE Read enable signal LED Driving pin 1 P52 NCS LED2 in out P5DIR2 P5PLU2 Chip select signal LED Driving pin 2 P53 A16 LED3 in out P5DIR3 P5PLU3 16 Address output bp16 LED Dr
58. Register indirect d16 An Register relative indirect d4 PC branch instructions only d7 PC t branch instructions on 911 PC branch instructions d12 PC branch instructions on 416 PC branch instructions only Stack relative indirect d8 SP d16 SP Absolute abs8 abs12 abs16 i abs18 branch instructions only RAM short short An d16 17 0H PC d4 L 7 PPC 17 0H PC d11 L 17 0H PC d12 17 0H PC d16 L 15 0 15 0 SP d8 15 0 SP d16 7 0 11 0 15 0 IOTOP io8 1 1 Directly specifies the operand or mask value appended to the instruction code Specifies the address using an address register Specifies the address using an address register with 8 bit displacement Specifies the address using an address register with 16 bit displacement Specifies the address using the program counter with 4 bit displacement and H bit Specifies the address using the program counter with 7 bit displacement and H bit Specifies the address using the program counter with 11 bit displacement and H bit Specifies the address using the program counter with 12 bit displacement and H bit Specifies the address using the program counter with 16 bit displacement and H bit Specifies the address using the stack pointer with 4 bit displacement Specifies the address using the stack pointer with
59. SBOO pin data input pin SBIO pin or 2 chan nels type clock pin SBTO pin data I O pin SBOO pin can be selected as the communication SBIO pin can be used for only serial data input SBOO pin can be used for serial data input or output The SCOIOM flag of the SCOMDS register can select if the serial data is input from SBIO pin or SBOO pin When data input from SBOO pin is selected to set the 2 channels type the PODIRO flag of the PODIR register controls direction of SBOO pin to switch transmission reception At that time SBIO pin is free to be used as a general port At reception if SCOIOM of the SCOMDS register is set to 1 and serial data input from SBOO is selected SBIO pin is used as a general port Operation X 17 Chapter 10 Serial Interface 0 EBUSY Flag When the activation factor is generated shown in Table 10 3 1 and the serial interface communication is started the BUSY flag SCOBSY of the SCOCTR register is set to 1 That is cleared to 0 when the communication complete interrupt SCOIRQ is generated BOther Control Flag Setup Table 10 3 4 shows flags that are not used at clock synchronous communication So they need not to be set or monitored Table 10 3 4 Other Control Flag Register Flag Detail SCOBRKF Brake status reception monitor SCOMD1 SCOERE Error monitor SCONPE Parity is enabled SCOPM1 to 0 Added bit specification SCOMD2 SCOFM to 0 Frame m
60. TMORM Reserved RMBTMS Reserved v 10 Table Delete fs 64 6 4 ms 5 3 1 XII 11 1 VLCD LCD panel driver voltage Fig ure Ch ange a Static Voo Vico b 1 2 duty 1 2 bias Vico a Static Vico b 1 2 duty 1 2 bias Voo Vico 1 1 3 1 MN101C485 487 MN101C485 487 MN101C38A 38C MN101C38A 38C c 1 3 duty 1 3 bias 1 4 duty 1 3 bias d 1 3 duty 1 3 bias 1 4 duty 1 3 bias Vo 2 V Vico 3 V Voo Vico MN101C38A 38C MN101C38A 38C uh R ET S Vico Wis Vis r ZR z Vica 22 R vss 8 Vss Diferrences between Version2 51 and 2nd Edition 7th Printing 2 2 Details of Changes Page Line Definition Previous Edition Ver 2 51 New Edition Ver 2 7 XI 23 1 Change 1 2 Duty 1 3 Duty XI 27 1 Change 1 2 Duty 1 4 Duty XIII 7 4 Delete Please contact one of our sales offices 8 21 Delete Please contact one of our sales offices XIII 16 3 Change 5 0 SCOIOM Diferrences between 2nd Edition 5th Printing and Version2 51 Page Line Definition Details of Changes Previous Edition Ver 2 5 New Edition Ver 2 51 Cover Pub No Change 21448 025E 21448 0251E Colophon Change August 2001 2nd Edition 5th Printing October 2001 Ver2 51 Sales office Chan
61. Timer 4 Event count means that the binary counter TM4BC counts the input signal from external to the TM4IO pin If the value of the binary counter reaches the setting value of the compare register 4 inter rupts can be generated at the next count clock Table 6 4 1 Event Count Input Clock Source Timer 4 TMA4IO input P14 Synchronous TM4IO input Event input Count Timing of TM4IO Input Timer 4 When TMAIO input is selected TM4IO input signal is directly input to the count clock of the timer 4 The binary counter counts up at the falling edge of the TM4IO input signal TM4IO input TM4EN 7 3 flag register Binary counter Compare match signal Interrupt __ 34 MEN request flag Figure 6 4 1 Count Timing 4 Input Timer 4 If the binary counter is read at operation incorrect data at counting up may be read To prevent this use the event count by the synchronous TMA4IO input as the following page 16 bit Event Count VI 13 Chapter 6 16 bit Timer iCount Timing of Synchronous TMA4IO Input Timer 4 If the synchronous TM4IO input is selected the synchronizing circuit output signal is input to the count clock The synchronizing circuit output signal is changed at the falling edge of the system clock after the TMAIO input signal is changed The binary counter counts up at the falling edge of the synchronizing circuit
62. Timer 5 mode register VIL 6 TM5ICR x Timer 5 interrupt control register Ill 24 TM5MD x 03F88 Timer 5 mode register VIL 6 Timer base timer TBICR xOS3FE7 Time base interrupt control register 25 R W Readable Writable R 4 Readable only Control Registers Chapter 7 Time Base Timer 8 bit Free running Timer 7 2 2 Programmable Timer Registers Timer 5 is a 8 bit programmable counter Programmable counter consists of compare register TM5OC and binary counter TM5BC Binary counter is 8 bit up counter When the TM5CLRS of the timer 5 mode register TM5MD is 0 and the interrupt cycle data is written to the compare register TM5OC the timer 5 binary counter TM5BC is cleared to 00 Timer 5 Binary Counter TM5BC 7 6 5 4 3 2 1 0 TM5BC 5 7 TM5BC6 TM5BC5 5 4 TMSBC3 5 2 TMBBC1 TM5BCO 00000000 Figure 7 2 1 Timer 5 Binary Counter TM5BC 03 68 R 5 Compare Register TM5OC 7 6 5 4 3 2 1 0 TM5OC 50 7 50 6 50 5 TM50C4 50 3 TM50C2 5 1 50 0 atreset XX X XXXXX Figure 7 2 2 Timer 5 Compare Register 5 x 03F78 R W Control Registers VII 5 Chapter 7 Time Base Timer 8 bit Free running Timer 7 2 3 Timer Mode Registers This is a readable writable register that controls
63. Vss TOR PER MES 1 gt gt 1000 pF 1 as Rx500 1 That value is for reference Recommend Connection with A D Converter Operation 15 Chapter 13 Appendices Chapter 13 Appendices 13 1 EPROM Version 13 1 1 Overview EPROM version is microcomputer which was replaced the mask ROM of the MN101C48 series with electronically programmable EPROM There are MN101CP487BL HT and PX AP101C48 FBC FHC for MN101C48 series The MN101CP487BL and the MN101CP487HT are sealed in plastic Once data is written to the internal EPROM it cannot be erased The PX AP101C48 FBC FHC are sealed in a ceramic package with a window Written data can be erased by exposing the physical chip to intense ultraviolet radiation We offer the PX AP101C48 FBC FHC for a 64 pin flat package Setting the EPROM version to EPROM mode functions as a microcomputer are halted and the internal EPROM can be programmed For EPROM mode pin connection refer to figure 13 1 2 Programming Adapter Connection The specification for writing to the internal EPROM are the same as for a general purpose 256 k bit EPROM 12 5 tow 1 0 ms Therefore by using a dedicated programming adapter supplied by Panasonic which can convert the 64 pin of EPROM version to 28 pin having the same configuration as a normal EPROM a general purpose ROM writer can be used to perform read and write operations The EPROM Version is described on the following items
64. current flow Input Input protection resistance Forward current generates N VDD Figure 1 8 5 Power Supply and Input Pin Voltage The Relation between Power Supply and Reset Input Voltage After power supply is on reset pin voltage should be low for sufficient time ts before rising in order to be recognized as a reset signal Power voltage Voltage Reset pin low level 6 Chapter 2 2 5 1 Reset Operation 1 Figure 1 8 6 Power Supply and Reset Input Voltage Precautions I 37 Chapter 1 Overview 1 8 4 Power Supply Circuit Cautions for Setting Circuits with VDD The CMOS logic microcontroller is high speed and high density So the power circuit should be de signed taking into consideration of AC line noise ripple caused by LED driver Figure 1 8 6 shows an example for emitter follower type power supply circuit BAn Example for Emitter Follower Type Power Supply Circuit Set condensors for noise filter near microcontroller power pins Microcontroller Vss LED port For Noise filter Figure 1 8 6 An Example for Emitter Follower Type Power Supply Circuit 1 38 Precautions 1 8 5 Usage of Resonator Chapter 1 Ceramic resonator or crystal resonator can be used for oscillator clock of this LSI mRecommended resonator Basic configuration with ceramic resonator is shown by the fallowing figure and recommended resonator and its circuit constant are by the following table Ceramic resona
65. instruction queue becomes empty on the time that the next operation code to be executed is stored to instruction register at the last cycle Therefore only when instruction queue is empty and direct address da or immediate data imm are needed instruction queue keeps waiting for a cycle Instruction queue is controlled automatically by hardware so that there is no need to be controlled by software But when instruction execution time is estimated operation of instruction queue should be into consideration Instruction decoder generates control signal at each cycle of instruction execution by micro program control Instruction decoder uses pipeline process to decode instruction queue at one cycle before control signal is needed 2 1 5 Registers for Address Registers for address include program counter PC address registers 0 A1 and stack pointer SP iProgram Counter This register gives the address of the currently executing instruction It is 19 bits wide to provide access to a 256 KB address space in half byte 4 bit increments The LSB of the program counter is used to indicate half byte instruction The program counter after reset is stored from the value of vector table at the address of 4000 Program PC counter 6 Overview Chapter 2 CPU Basics E Address Registers 0 1 These registers are used as address pointers specifying data locations in memory They support the operations involved i
66. is set to 1 by an interrupt request and cleared to 0 by the interrupt accep tance This flag is managed by hardware but can be rewritten by software Interrupt enable flag IE is the flag that enables interrupts in the group There is no interrupt enable flag in non maskable interrupt NMI Once this interrupt request flag is set it is accepted without any condi tions Interrupt enable flag is set in maskable interrupt Interrupt enable flag IE of each maskable interrupt is valid when the maskable interrupt enable flag MIE flag of PSW is 1 Maskable interrupts have had vector numbers by hardware but their priority can be changed by setting interrupts level field There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority Maskable interrupts are accepted when its level is higher than the interrupt mask level IM1 0 of PSW Non maskable interrupts are always ac cepted regardless of the interrupt mask level II 2 Overview Chapter 3 Interrupts 3 1 1 Functions Table 3 1 1 Interrupt Functions Interrupt type Reset inte nupt Maskabk mntenupt Vectornum ber 0 1 2 to 20 addiess x04000 x04004 x04008 to x04050 Starting address Addiess specifed by vectoraddiess hte nupt Evel Level0 to 2 sofware hte nupt factor ExtemalRST pi Inout rors detection P I
67. oz If the SCOIOM flag of the SCOMD3 register is set to 1 the SBIO pin can be used as port When the SBOO pin is input mode reception is operated and when it is output mode trans mission is operated When the register except the SCOTRB is written or rewritten set the SCOSBOS SCOSBIS flag to 4 When the internal clock is used as clock source write dummy data to the SCOTRB register after setting the SCOSBIS flag and the SCOSBOS flag of the SCOMDS register to 1 Even if the reception is operated again write dummy data to the SCOTRB register X 28 Operation 10 3 3 Half duplex UART Serial Interface Chapter 10 Serial Interface 0 Serial interface 0 can be used for half duplex UART communication Table 10 3 11 shows UART serial interface functions Table 10 3 11 UART Serial Interface Functions Communication style UART Half duplex Interrupt SCOIRQ transmission reception TXD output input Used pins RXD input First transfer bit MSB LSB Parity bit selection 0 parity 1 parity Parity bit control odd parity even parity Frame selection 7 bits 1 stop 7 bits 2 stops 8 bits 1 stop 8 bits 2 stops Maximum transfer rate 625 kbps Operation X 29 Chapter 10 Serial Interface 0 Selection of Half duplex UART Serial Interface When the serial interface 0 is used as half duplex UART serial interfa
68. x 3FC9 SEG24 P53 at static at static at 1 2 duty at 1 2 duty at 1 3 duty S at 1 3 duty a ay gt 24 at 1 4 duty Figure 11 2 3 Correspondance between the Segment Output Latch and the Segment Common Pins When a duty ratio other than 1 4 is used the LCD display will be affected if a 1 is written to bits not used for the segment output latch Therefore write 0 to bits 7 and 3 when using a 1 3 duty ratio to bits 7 6 3 and 2 when using a 1 2 duty ratio and to bits 7 6 5 3 2 and 1 when the display mode is static LCD Control Registers XI 9 Chapter 11 LCD Functions 11 2 5 Operation The LCD driver is capable of static display and dynamic display 1 2 duty 1 2 bias 1 3 duty 1 3bias 1 4 duty 1 3 bias through the segment output pins SEGO to SEG24 and the common output pins COMO to LCD driver circuit operation The LCD driver circuit generates the timing siginals which are necessary for controling 1 2 duty 1 3 duty 1 4 duty and static at the timing control circuit based on the LCD clock divided by the prescaler and supplies them to the common driver and the multiplexer The common driver outputs the common signals which are necessary for the LCD display based on the voltage from the LCD power supply At reset or when the LCD is OFF Vpp is output When the LCD is OFF Vpp is output and the potential difference between the LCD electrodes becomes 0 The multipl
69. 0 Port 83 to 87 selection 0 SEG26 to SEG29 SEG30 to SEG33 SEG37 to SEG34 Port 74 to 77 selection 0 SEG41 to SEG38 Port 70 to 73 selection 0 SEG45 to SEG42 Port 64 to 67 selection 0 SEG49 to SEG46 Port 60 to 63 selection 0 SEG51 to SEG50 Port 53 to 54 selection N 26 31 38 42 XII 8 Reserved 0 LCDDTY1 LCDDTYO LCDCK3 LCDCK2 LCDCK1 LCDCKO LCD drivers enable Do not set IRQOICR Reserved IRQOLV1 RQOLVO Program interrupt request Watchdog interrupt request IRQOIE Set always 0 IRQOIR 0 0 IRQO interrupt level IRQO interrupt active edge 0 IRQO interrupt enable 0 IRQO interrupt request IRQ1ICR IRQ1LV1 RQ1LVO REDG1 0 IRQ1IE 0 IRQ1IR 0 IRQ1 interrupt TM2LV1 IRQ1 interrupt active edge IRQt interrupt enable IRQ1 interrupt request 0 2 interruput 2 interrupt enable 2 interrupt request SCOICR TBLV1 TBIE 0 TBIR 0 TB interrupt level SCOLV1 SCOLVO TB interrupt enable TB interrupt request 0 0 SCO interrupt level SCO interrupt enable SCO interrupt request IRQ2ICR ADLV1 ADLVO ADIE 0 ADIR 0 AD interrupt level IRQ2LV1 RQ2LVO AD interrupt enable AD interrupt request IRQ2IR 0 0 IRQ2 interrupt level IRQ2 interrupt active edge IRQ2 interrupt enable 0 IR
70. 0 flag of the TM3MD register Set the timer compare register to the value that baud rate comes to 300 bps t Chapter 10 Table 10 3 18 At that time the timer 3 binary counter TM3BC is initialized to 00 Set the flag of the TM3MD register to 1 to start timer 3 counts up from 00 Timer output is the clock of the serial interface 0 at transmission and reception For the compare register setup value and the serial interface operation setup t Serial Interface 0 Chapter 10 V 29 Serial Interface Transfer Clock Output Chapter 5 8 bit Timers 5 9 Cascade Connection 5 9 1 Operation Cascading timer 2 and 3 form a 16 bit timer B8 bit Timer Cascade Connection Operation Timer 2 Timer 3 Timer 2 and timer 3 are combined to be a 16 bit timer Cascading timer is operated at clock source of timer 2 which are lower 8 bits Table 5 9 1 Timer Functions at Cascade Connection Timer 2 Timer 3 16 Bit Interrupt source TM3IRQ Timer operation Event count TM210 input Timer pulse output output PWM output Synchronous output Serial interface transfer clock output output Remote control carrier 4 output fs fs 4 Clock source 2 input fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation fs System clock at NORMAL mode fs fosc 2 at
71. 0000 and counting up is restarted 16 16 bit Event Count Chapter 6 16 bit Timer 6 5 16 bit Timer Pulse Output 6 5 1 Operation TMAIO pin can output a pulse signal with any frequency WOperation of 16 bit Timer Pulse Output Timer 4 The timers can output 2 x cycle signal compared to the setting value in the compare register TM4OC Output pins are as follows Table 6 5 1 Timer Pulse Output Pin Timer 4 output P14 Pulse output pin iCount Timing of Timer Pulse Output Timer 4 TM4EN flag Compare WT register a Je counter Compare match signal Interrupt request flag TM4IO output Figure 6 5 1 Count Timing of Timer Pulse Output Timer 4 The TM4IO pin outputs 2 x cycle compared to the value in the compare register If the binary counter reaches the compare register and the binary counter is cleared to x 0000 TM4IO output timer output is inverted The inversion of the timer output is changed at the rising edge of the count clock This is happened to form the waveform inside to correct the output cycle In the initial state after releasing reset the timer pulse output is low output 16 bit Timer Pulse Output VI 17 Chapter 6 16 bit Timer 6 5 2 Setup Example Timer Pulse Output Setup Example Timer 4 TM4lO pin outputs 50 kHz pulse by using timer 4 For this select fosc as clock source and set 1 2 cycle 100 kHz for the timer 4
72. 04 repeated count 256 times Figure 6 6 1 Added Pulse Type PWM Output Set the P1DIR register and the P1PLU register when the P14 pin is used as a PWM output pin For PWM operation x FF TM4OCL produces the same result as x 00 constant low level output at the PWM4 pin not constant high Do not set x FF in TM4OCL VI 20 Added Pulse Type 16 bit PWM Output Setting the Added Pulse Position Chapter 6 16 bit Timer The upper 8 bits of timer 4 compare register set the position of the added pulse If the register is set to x 00 an additional bit is not appended to the basic PWM component If the register is set to x FF an additional bit is repeatedly appended to the 255 basic PWM compo nents during the cycle The relation between the value set in the register and the position of the added pulse is shown in the table below In the TMAOCH register the position of the added pulse the value of Tn depends which bit has 1 And the number of the setting value in is the number of bits to be added For example if x 03 is set in the TMAOCH register set 1 in bp1 bits are appended to pulse positions for x 01 Tn x 80 and x 02 Tnzx 40 x C0 shown the below table The setting value of Position of the added pulse the value of Tn wor 02 00000100 x04 00001000
73. 08 00010000 x10 00100000 x20 01000000 x40 10000000 x80 0 7 TM40CH 00000000 x00 none 00000001 x01 80 00000010 x 40 x C0 20 60 x 10 x 30 x 50 x 70 x 90 x B0 x D0 x F0 08 18 28 38 48 58 8 8 04 0 14 1 24 2 XFA XFC X02 Xx 06 XOA XOE x12 x16 XFA XFE 01 03 05 07 09 XFD XFF The setting value in the TM4OCH register 00 01 repeated count 256 times 1 Ld OUUU Figure 6 6 2 The Setting Value in The TM4OCH Register and The Position of The Added Pulse XFF lt Position of added pulse Added Pulse Type 16 bit PWM Output VI 21 Chapter 6 16 bit Timer 6 6 2 Setup Example Added Pulse Type 16 bit PWM Output Setup Example Timer 4 The output pin outputs the 1 4 duty 64 192 PWM output waveform at 78 125 kHz with timer 4 In the PWM output repetitions 256 times the added pulse is appended 7 times and the duty becomes 65 191 The high frequency oscillation fosc is set to be operated at 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM4MD x 3F84 bp6 TM4EN 20 2 Setthe special function pin to output mode P1OMD x 3F39 bp4 P14TCO
74. 1 repeat whn imm3 0 imm3 1 as macro instructions Other than the instruction of MN101C Series the assembler of this Series has the following instructions The assembler will interpret the macro instructions below as the assembler instructions macro instructions replaced instructions remarks INC Dn ADD 1 Dn DEC Dn ADD 1 Dn INC An ADDW 1 DEC An ADDW 1 An INC2 An ADDW 2 DEC2 An ADDW 2 An CLR Dn SUB Dn Dm ASL Dn ADD Dn Dm LSL Dn ADD Dn Dm ROL Dn ADDC Dn Dm NEG Dn NOT Dn ADD 1 Dn NOPL MOVW DWn DWm MOV MOV 0 SP Dn MOV MOV Dn 0 SP MOVW MOVW 0 SP DWn MOVW MOVW DWn 0 SP MOVW MOVW 0 5 MOVW MOVW 0 5 Ver3 2 2002 01 31 Instruction Set XIII 25 Chapter 13 Appendices 13 5 Instruction Map MN101C SERIES INSTRUCTION MAP 1stnibble 2nd nibble MOV 48 108 CMP 8 abs8 abs12 7 ADD 8 Dm D MOVW 8 DWm MOVW 8 JSR d12 label JSR d16 label MOV 8 abs8 abs12 PUSH An OR 8 Dm AND 8 Dm When the exension code is b oo10 When the extension code is b 0011 MOV abs12 Dm MOV abs8 Dm MOV An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am MOV 8 MOV d4 SP Dm MOV d8 An Dm 8 44 48 ADD 4 Dm SUB Dn Dn
75. 1 PRB ADP101C09 48 64PIN Probe Switches Adapter boards vary depending upon the models This adapter board must be used for only MN101C09 48 64PIN Use the adapter board with an EV board PRB EV101C15 Improper matching may cause any damage to the ICE The switches that the adapter board provides for configuring the probe are described below Adapter Board Layout 1 E i AE 3 1 Oscillator control SW1 4 Set this switch to its USR position to drive the in circuit emulator with the oscillator built into the target device If there is no target device set this switch to the ICE position to use the oscillator built into the probe 2 X1 control SW2 Set this switch to its USR position to drive the in circuit emulator with the X1 oscillator built into the target device If there is no target device set this switch to the ICE position to use the oscillator built into the probe 3 Power supply control SW3 Set this switch to its USR position to use the power supply from the target device If there is no target device set this switch to the ICE position to use the 5 volt power supply from the in circuit emulator 4 Function control DIP switches These switch settings vary with the individual target device as described below LCDSEL ON if using LCD OFF if using LED Watchdog Timer Frequency WDSEL2 WDSEL1 WDSEL1 WDSEL2 Watchdog timer Frequency Starting Oscillation after a reset NSSTRT ON L
76. 1 output register P1 OUT Each pin can be set individually if pull up resistor is added or not by the port 1 pull up resistor control register P1PLU Set the control flag of the port 1 pull up resistor control register P1PLU to 1 to add pull up resistor At reset the input mode is selected and pull up resistors are disabled high impedance output ilSpecial Function Pin Setup P12 to P14 are used as timer I O pin as well P10 is used as remote control carrier output pin as well The port 1 output mode register P1OMD can select P10 and P12 to P14 output mode by each bit When the port 1 output mode register P1OMD is 1 special function data is output and when it is O they are used as general port 10 Porti 4 3 2 P1OUT P1IN P1DIR P1PLU Registers 4 3 2 0 P10UT4 P10UT3 P1OUTO Chapter 4 Ports Atreset 000 0 Port 1 output register P1OUT x OSF11 R W 4 3 2 1 0 P1IN4 P1IN3 P11N2 Pino Port 1 input register P1IN x 03F21 R 4 3 2 1 0 P1DIR4 P1DIR3 P1DIR2 P1DIRO Port 1 direction control register P1DIR 03 31 R W 4 2 0 P1PLU4 1 LU3 2 PLUO P1OUT Output data 0 Low Vss lev
77. 16 Input PAO Analog input pins Analog input pins for an 8 channel 10 bit A D 1 17 PA1 converter AN2 18 PA2 When not used for analog input these pins can be used AN3 19 PA3 as normal input pins AN4 20 PA4 5 21 5 6 22 6 AN7 23 PA7 IRQO 34 Input P20 External interrupt External interrupt input pins IRQ1 35 P21 SENS input pins The valid edge for IRQO to 2 can be selected through IRQ2 36 P22 the IRQnICR register IRQ1 is an external interrupt pin that is able to deternine AC zero crossings When these are not used for interrupts these can be used as normal input pins SENS 35 Input P21 IRQ1 AC zero cross An input pin for an AC zero cross detection circuit The detection input pin AC zero cross detection circuit outputs a high level when the input is at an intermediate level Otherwise it outputs a low level voltage all the times SENS input signal is connected to the P21 input circuit and the IQR1 interrupt circuit When the AC zero cross detection circuit is not used this pin can be used as a normal P21 input The selection is set by the P21IM flag of the FLOAT1 register I 15 Pin Description Overview Chapter 1 Overview Table 1 3 8 Pin Function Summary 6 7 No Name 80 y o Function Description pin KEYO 16 Input PAO Key interrupt input pins Input pins for interrupt based on ORed result of pin KEY1 17 PA1 inputs KEY2 18 PA2 Key
78. 2 Registers noster pee rhet ide IV 39 4 9 3 Block Di gram 2 5 nosmet IU om tec eet ade IV 42 Synchronous Output Port 7 a eene nennen nennen IV 43 4 10 1 Block Diagram IV 43 4 10 2 CREBISUEES IV 44 4 10 3 Operations beenden edit IV 45 4 10 4 Setup IV 47 Chapter5 8 Timers 5 1 5 2 5 3 5 5 5 6 5 7 5 8 OVERVIEW ore aet one eo era ihe tee even V 2 5 1 1 Eu nctioDs 4 eem eS PE et Bis dem ect 2 5 1 2 Block Diagram pee bn V 3 Control Registers 2 eter eR Re nter o POR eR Aie qe V 5 5 2 1 R egistefs onere tote ete teet n dee V 5 5 2 2 Programmable Timer Registers essere V 6 5 2 3 Timer Mode Registers uice or e Reef ine evans V 7 8 bit Timer PED OI RO RR IR ete reas 10 5 3 1 Operation 10 5 3 2 Setup Example eae 12 8 bit Event Count 5 nne oae eor eruere 14 5 4 1 GIOCHI 14 5 4 2 Set p Example 5E V 16 8 bit Timer Pulse Outp ts sinisiin eene eene ener V 18 5 5 1 Operaatio niise os eie eerte eie esteri a eq V 18 5 5 2 Setup Example 2 B e nete eO UR RE 19 Sbit PWM Output sinc cc eee ird eere A V 21 5 6 1 Operations E tentes V 21 5
79. 2441 Hz 1953 Hz 977 Hz 488 Hz 10 1 2 duty 1221 Hz 977 Hz 488 Hz 244 Hz 11 static 2441 Hz 1953 Hz 977 Hz 488 Hz 00 1 4 duty 305 Hz 244 Hz 122 Hz 61Hz 0011 01 1 8 duty 407 Hz 326 Hz 163 Hz 81 Hz 1221 Hz 977 Hz 488 Hz 244 Hz OSC1 2 1 2 duty 610 Hz 488 Hz 244 Hz 122 Hz 11 static 1221 Hz 977 Hz 488 Hz 244 Hz 00 1 4 duty 153 Hz 122 Hz 61 Hz 31 Hz 0100 01 1 3 duty 203 Hz 163 Hz 81 Hz 41 Hz 5 1 215 610 Hz 488 Hz 244 Hz 122 2 10 1 2 duty 305 2 244 Hz 122 Hz 61 Hz 11 static 610 Hz 488 Hz 244 Hz 122 Hz 00 1 4 duty 76 Hz 61 Hz 31 Hz 15 Hz 0101 01 1 3 duty 102 Hz 81 Hz 41 Hz 20 Hz 8 305 He F244 Hz F122 Hz 61 Hz 40 1 2 duy 153 Hz 122 Hz 61 Hz 31 Hz 11 static 305 Hz 244 Hz 122 Hz 61 Hz 00 1 4 duty 38 Hz 31 Hz 15 Hz 8 Hz 0110 01 1 3 duty 51 Hz 41 Hz 20 Hz 10 Hz 153 Hz 122 Hz 61 Hz 31 Hz t0 1 2 duty 76 Hz 61 Hz 31Hz 15Hz 11 static 153 Hz 122Hz 61Hz 31Hz 00 1 4 duty 19 Hz 15Hz 8Hz 4Hz 0111 01 1 8 duty 25 Hz 20 Hz 10 Hz 5 Hz OSC1 2 76 Hz 61 Hz 31 Hz 15 Hz 10 1 2 duty 38 Hz 31 Hz 15 Hz 8 Hz 11 static 76 Hz 61 Hz 31 Hz 15 Hz 00 1 4 duty 128 Hz 01 1 3 du 171 Hz 1x00 512 He xv2 10 1 2 duty 256 Hz 11 static 512 Hz 00 1 4 duty 64 Hz 01 85H Xie 256 Hz 2 X127 10 1 2 duty 128 Hz 11 static 256 Hz 00 1 4 duty 32 Hz 01 1 3 du 43 Hz 1x10 y 128 Hz X12 10 1 2 duty 64 Hz 11 static 128 Hz 00 1 4 duty 1
80. 4 for the clock source by the 2 2 0 flag of the TM2MD register 8 bit PWM Output V 23 Chapter 5 8 bit Timers Setup Procedure Description 5 Set the period of PWM H output 5 Set the period of PWM output to the timer 2 x 3F72 40 2 compare register TM2OC The setting value is set to 256 4 64 40 because it should be the 1 4 duty of the full count 256 At that time the timer 2 binary counter TM2BO is initialized to 00 6 Start the timer operation 6 Setthe TM2EN flag of the TM2MD register to TM2MD 3 82 1 to operate timer 2 bp4 2 1 TM2BC counts up from x 00 PWM source waveform outputs H till TM2BC reaches the setting value of the TM2OC register and outputs L after that Then TM2BC continues counting up and PWM source waveform outputs H again once overflow happens and TM2BC restarts counting up from x 00 the timer 2 PWM output is selected by setting the TM3PWM flag of the TM3MD register to 1 the pin outputs the timer 2 PWM output too When port 1 is used as PWM output pin the settings of the P1DIR register and the P1PLU register are need to set to 1 V 24 8 bit PWM Output Chapter 5 8 bit Timers 5 7 8 bit Timer Synchronous Output 5 7 1 Operation When the binary counter of the timer reaches the set value of the compare register the latched data is output fr
81. 7th Printing and 2nd Edition 8th Printing Details of Changes Page Line Definition Previous Edition Ver 2 7 New Edition Ver 2 8 About Delete The MN101C48 series offers a variety of y This S Manual RAM and ROM combinations covering a wide range of applications It also offers a choice of masked ROM version or user programmable EPROM version ROM RAM MN101C485 512 16K MN101C487 512 16K MN101CP487 512 Unit byte 19 ae Change The absolute maximum ratings are the The absolute maximum ratings are the limit values beyond which the LSI may limit values beyond which the LSI may be damaged and proper operation is be damaged not assured 20 Figure Change Ta 40 esse EA 22 24 Figure Change 40 to 85 Ta 20 to 70 2 1 5 3 im Symbol T un um Symbol Conditions wax Unt Instruction 20 Set Change Latest Version Instruction Ch XIII 26 Map ange Latest Version Sales Offices Change Latest Version MN101C485 487 LSI User s Manual Record of Changes Diferrences between Version2 51 and 2nd Edition 7th Printing 1 2 Details of Changes
82. Description 3 Select the clock source SCOMD 1 x 3F51 bp4 3 SCOCK1 0 bp5 SCOCKM 4 Select the transfer clock SCOMD3 x 3F53 SCOBTS 5 Control the pin type SCOMDS x 3F53 bp4 3 bp5 SCOIOM POPLU x 3F40 bp2 0 POPLU2 0 6 Control the pin direction PODIR x 3F30 bp2 0 PODIR2 0 7 Control the pin function SCOMDS x 3F53 bp2 SCOSBOS bp1 SCOSBIS 8 Set the interrupt level SCOICR x 3FF8 bp7 6 SCOLV1 0 9 Enable the interrupt SCOICR x 3FF8 SCOIE SCOSBOM SCOSBTM 11 0 010 101 10 3 Set the SCOCK1 0 of the SCOMD1 register to 00 to select the clock source fs 2 Set the SCOCKM flag to 0 to select not to divide the clock source by 1 8 Set the SCOSBTS flag of the SCOMDS register to 1 to set the SBTO pin to serial interface clock I O pin The communication is used with the internal clock master communication Set the SCOSBOM SCOSBTM flag of the SCOMDS register to 11 to select the SBOO SBTO pin to N ch open drain Set the SCOIOM flag to 0 to set input serial data from the SBIO pin Set the POPLU2 0 flag of the POPLU register to 010 to select add pull up resistor only to the SBIO pin Set the PODIR2 0 flag of the port 0 pin direction control register PODIR to 101 to set POO and P02 to output mode and to set to input mode Set the SCOSBOS SCOSBIS flag of the SCOMD3 r
83. Dm mem8 d4 SP Dm 0110 1ADm 0110 01Dm MOV d8 SP Dm mem8 d84SP 5Dm 0110 01Dm mem8 d16 SP gt Dm 0110 00Dm MOV io8 D 8 IOTOP io8 Dm 0110 00Dm MOV abs8 Dm 8 abs8 5 Dm 0100 01Dm MOV abs12 Dm mem8 abs12 5Dm 0100 00Dm A MOV d16 SP Dm MOV abs16 Dm mem8 abs16 5 Dm 1100 00Dm MOV Dn Am Dnmem8 Am 0101 1aDn MOV Dn d8 Am Dn mem8 d8 Am 0111 1aDn MOV Dn d16 Am Dn mem8 d16 Am 0111 1aDn MOV Dn d4 SP Dn mem8 d4 SP 0111 01Dn 0111 01Dn MOV Dn d16 SP Dn mem8 d16 SP 0111 00Dn MOV Dn io8 Dn mem8 IOTOP i08 0111 00Dn Dn d8 SP Dn abs8 Dn mem8 abs8 0101 01Dn MOV Dn abs12 Dn mem8 d8 SP Dn mem8 abs12 0101 00Dn MOV Dn abs16 Dn mem8 abs16 1101 00Dn MOV 1 8 108 imm8 mem8 IOTOP io8 0000 0010 MOV imm8 abs8 imm8 gt mem8 abs8 0001 0100 MOV imm8 abs12 8 gt 8 5612 0001 0101 MOV 8 0616 imm8 mem8 abs16 1101 1001 MOV Dn HA Dn mem8 HA 1101 00Dn XIII MOVW An DWm mem16 An DWm 1110 00Ad MOVW 16 gt 1110 10Aa
84. EXT Dn DWm AND 8 PSW OR 8 PSW MOV Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC Dn Dm MOV abs16 Dm MOVW abs16 Am MOVW abs16 DWm CBEQ 8 Dm d12 MOVW An DWm MOV Dn abs16 MOVW An abs16 MOVW DWn abs16 CBNE 8 Dm d12 8 abs8 d7 d11 8 abs8 d7 d11 MOVW d16 SP Am MOVW d16 SP DWm MOVW d8 SP Am MOVW d8 SP DWm MOVW An Am ADDW 8 Am DIVU MOVW An d16 5P XIII 26 MOVW DWn d16 SP Instruction Map MOVW An d8 SP MOVW DWn d8 SP MOVW An Am MULU Extension code b 0011 2nd nibble 3rd nibble 0 1 2 TBZ abs8 bp d7 Chapter 13 Appendices 8 9 A B D TBZ abs8 bp d11 TBNZ abs8 bp d7 TBNZ abs8 bp d11 CMP Dn Dm ADD Dn Dm TBZ io8 bp d7 TBZ io8 bp d11 TBNZ io8 bp d7 TBNZ io8 bp d11 OR Dn Dm AND Dn Dm BSET io8 bp BCLR io8 bp JMP abs18 label JSR abs18 label Dn Dm 8 Dm ADDC Dn Dm BSET abs16 bp BCLR abs16 bp BTST abs16 bp om 8 86516 mov amp abet 8 abs16 d7 11 CBNE 8 6516 07 1 TBZ abs16 bp d7 TBZ abs16 bp d11 TBNZ abs16 bp d7 TBNZ abs16 bp d11 Ver2 1 2001 03 26 Instruction Map XIII 27 MN101C485 487 LSI User s Manual Record of Changes Diferrences between 2nd Edition
85. F 2 2 A D conversion data AN2 M x upper 8 bits Sample and 10 bits A D AN4 Id comparator AN X E A D conversion data 5 lower 2 bits AN6 VREF fs 2 fs 4 M gt 1 2 5 XX gt 1 6 U pa E 1 18 Figure 12 1 1 A D Converter Block Diagram Overview XII 3 Chapter 12 A D Converter 12 2 Control Registers A D converter consists of the control register ANCTRn and the data storage buffer ANBUFn 12 2 1 Registers Table 12 2 1 shows the registers used to control A D converter Table 12 2 1 A D Converter Control Registers Register Address RAW Function Page ANCTRO x 03F90 RAW A D converter control register O XII 5 ANCTR1 xOSF91 RAW A D converter control register 1 XII 6 ANBUFO x03F92 R A D buffer O XII 7 ANBUF1 X 03F93 R A D buffer 1 XII 7 ADICR RAN A D converter interrupt control register 27 PAIMD R W Port A input mode register 39 PAPLUD RAW Port A pull up pull down resistance control register 39 R W Readable Writable Readable only XII 4 Control Registers Chapter 12 A D Converter 12 2 2 Control Registers A D Converter Control Register 0 ANCTRO 7 6 5 4 3 2 1 0 At reset XX XXOXXX ANCTRO ANSH1 ANSHO ANCK1 ANCKO ANLADE ANCHS2 0
86. FLOAT1 4 R W control register 1 Ill 34 External interrupt 2 IRQ2ICR x O3FEB R W External interrupt 2 control register Il 19 IRQ4ICR xOSFED R W External interrupt 4 control register Ill 20 External interrupt 4 P4IMD xO3F3C R W 4 key interrupt control register Ill 35 R W Readable Writable External Interrupts 33 Chapter 3 Interrupts Noise Filter Control Register The noise filter control register NFCTR sets the noise remove function to IRQO and IRQ1 and also selects the sampling cycle of noise remove function 7 6 5 4 2 1 NFCTR NF1SCK1 NF1SCK0 NF1 NFOSCK1 NFOSCKO NFOEN atreset 000000 NFOEN IRQO noise filter setup 0 Noise filter OFF 1 Noise filter ON NFOCKS1 NFOCKSO IRQO noise filter sampling period 0 fs 2 0 8 1 fs 2 1 0 15 22 1 fg 2 NF1EN IRQ1 noise filter sampling setup 0 Noise filter OFF 1 Noise filter ON NF1CKS1 NF1CKS0 IRQ1 noise sampling period 0 fs 2 0 8 1 fs 2 1 0 fs 2 1 15 2 Figure 3 3 4 Noise Filter Control Register NFCTR R W 34 External Interrupts Chapter 3 Interrupts Pin Control Register 1 FLOAT 1 7 6 5 4 3 2 1 0 P211M PARDWN P7RDWN at reset FLOAT1 Port 7 pull up pull down resistor se
87. In Figure 11 3 4 C is a bias capacitor in the range of 0 01 uF to 0 1 uF which is used to reduce the impedance of the power supply TIT Figure 11 3 3 Supply to to VLc3 XI 12 LCD Voltage Control Circuit Chapter 11 LCD Functions LCD Voltage Control Circuit XI 13 Chapter 11 LCD Functions 11 4 LCD Function Operation Examples of the LCD panels connections displays and driving waveforms for static 1 2 duty 1 3 duty and 1 4 duty at each operation are shown below 11 4 1 LCD Display Examples Static 101 485 487 Static Segment Latch x3FC9 x3FBF x3FBF bit6 bit2 bit5 bit1 COM1 open bit4 bitO COMO A electrode B electrode not lit LCD PANEL LCD ON COM S LCD OFF SEG S SEG N undefined Data 0 undefined COM Vice 4 Vlci VoD es SEG Mice E Ee e COM SEG Oy pua Lit Not lit Not lit S selective voltage N non selective voltage LCD driver voltage In case of static always outputs selective voltage XI 14 LCD Function Operation Chapter 11 LCD Functions St
88. LCD segment output 12 SDO3 003 Synchronous output 3 P74 A12 5 11 in out P7DIR4 P7PLUD4 12 Address output bp12 SEG11 LCD segment output 11 SDO4 004 Synchronous output 4 P75 A13 SEG10 in out P7DIR5 P7PLUD5 A13 Address output 0913 SEG10 LCD segment output 10 SDO5 005 Synchronous output 5 P76 A14 9 in out P7DIRe P7PLUD6 A14 Address output bp14 SEG9 LCD segment output 9 SDO6 006 Synchronous output 6 P77 15 SEG8 in out P7DIR7 P7PLUD7 A15 Address output 0915 SEG8 LCD segment output 8 SDO7 SDO7 Synchronous output 7 P80 DO SEGO in out P8DIRO P8PLUO DO Data I O SEGO LCD segment output 0 P81 D1 SEG1 in out P8DIR1 P8PLU1 D1 Data I O 6 1 SEG1 LCD segment output 1 P82 D2 SEG2 in out P8DIR2 P8PLU2 D2 Data I O bp2 SEG2 LCD segment output 2 P83 D3 SEG3 in out P8DIR3 P8PLU3 D3 Data I O bp3 SEG3 LCD segment output 3 P84 D4 SEG4 in out P8DIR4 P8PLU4 D4 Data I O 6 4 SEG4 LCD segment output 4 P85 D5 SEG5 in out P8DIR5 P8PLUS5 D5 Data I O bp5 SEG5 LCD segment output 5 P86 D6 SEG6 in out P8DIR6 P8PLU6 D6 Data I O bp6 SEG6 LCD segment output 6 P87 D7 SEG7 in out P8DIR7 P8PLU7 D7 Data I O bp7 SEG7 LCD segment output 7 PAO KEYO in PAPLUDO Analog 0 input KEY interrupt input 0 PA1 AN1 KEY1 in PAPLUD1 AN1 Analog 1 input KEY1 KEY interrupt input 1 2 KEY2 in PAPLUD2 AN2
89. Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES NORTH AMERICA U S A Sales Office Panasonic Industrial Company PIC New Jersey Office Two Panasonic Way Secaucus New Jersey 07094 U S A Tel 1 201 348 5257 1 201 392 4652 Chicago Office 1707 N Randall Road Elgin Illinois 60123 7847 U S A Tel 1 847 468 5720 1 847 468 5725 Milpitas Office 1600 McCandless Drive Milpitas California 95035 U S A Tel 1 408 942 2912 1 408 946 9063 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee GA 30024 U S A Tel 1 770 338 6953 1 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Tel 1 619 503 2903 1 858 715 5545 e Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Mississauga Ontario LAW 2T3 CANADA Tel 1 905 238 2101 Fax 1 905 238 2414 LATIN AMERICA e Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F MEXICO Tel 52 5 488 1000 Fax 52 5 488 1073 Guadalajara Office SUCURSAL GUADALAJARA Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44920 MEXICO Tel 52 3 671 1205 OG Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Tel 55 12 33
90. Only timer 3 be used as a baud rate timer For baud rate setup q Chapter 5 5 8 Serial Interface Transfer Clock Output Serial interface 0 is operated by setting the SCOSBOS flag or the SCOSBIS flag of the SCOMDS register to 1 The SCOSBOS flag or the SCOSBIS flag should be set after all conditions are set After that at transmission the communication is started by writing data to the SCOTRB When a register except the SCOTRB is written rewritten set the SCOSBOS the SCOSBIS flag to 0 in advance When the TXD RXD pin are connected for communication with 1 channel the TXD pin inputs outputs serial data The port direction control register PODIR should be set for switching input output The RXD pin can be used as a general port When the serial interface port is enabled if the SCOCE1 0 flag of the SCOMDO register is switched the transfer bit count may be changed If it is used as half duplex UART serial interface setting the SCOCE1 0 flag fixed to 00 is recommended After transmission has completed the TXD pin is H level If the frame mode is set by the SCOFM flag of the SCOMD register the SCOLNG2 0 flag of the SCOMDO register is automatically set After the transfer has completed the transfer bit count in the SCOLNG2 0 flag of the SCOMDO register is automatically set At UART transmission set the SCOSBOS flag of t
91. Overview 1 5 3 DC Characteristics 40 to 85 Vss 0 V Rating Parameter Symbol Conditions MIN Unit Power supply current no load at output pin 6 1 01 fosc 20 0 MHz 5 25 60 mA 2 Power supply current 502 fosc 8 00 MHz 5 10 25 3 fx232 768 kHz 3 15 100 4 Supply current 1204 fosc 20 0 MHz 5 V 30 75 A 5 during HALTO mode Ibos fosc 8 00 MHz Vop 5 V 12 3 0 fx 32 768 kHz 6 506 4 8 Supply current Vop 3V Ta 25 during HALT1 mode fx 32 768 kHz 007 3 Ta 85 30 pA 8 Supply current 5 25 1 9 during STOP mode VoD 5V Ta 85 25 6 Measured under conditions of no load Pull up and pull down are unconnected The supply current during operation IDD1 and IDD2 are measured under the following conditions After all I O pins are set to input mode and the oscillation is set to NORMAL mode the MMOD pin is at Vss level the input pins are at VDD level and a 20 2 8 00 MHz square wave of VDD and Vss amplitudes is input to the OSC1 pin The supply current during operation IDD3 is measured under the following conditions After all I O pins are set to input mode and the oscillation is set to lt SLOW mode the MMOD pin is at Vss level the input pins are at VDD level and 32 768 kHz square wave of VDD and
92. P27 NRST pin And transferring to reset by program software reset can be executed If the internal LSI is reset and register is initiated the P2OUT7 flag becomes 1 and reset is released 4 4 4 2 Registers enough low level time at sudden unconnected And reset can be generated even if NRST pin a When NRST pin is connected to low power voltage detection circuit that gives pulse for is held low for less than OSC 4 clock cycles take notice of noise Reset II 29 Chapter 2 Basic CPU ilSequence at Reset 1 When reset comes to high level from low level the internal 14 bit counter It be used as watchdog timer too starts its operation by system clock The period from starting its count from its overflow is called oscillation stabilization wait time During reset internal register and special function register are initiated After oscillation stabilization wait time internal reset is released and program is started from the address written at address x 04000 at interrupt vector table VDD NRST OSC2XO Kt Oscillation stabilization Wait time internal RST Figure 2 5 2 Reset Released Sequence On 101 48 series the oscillation is stopped during the NRST pin p27 is low level II 30 Reset Chapter 2 Basic CPU 2 5 2 Oscillation Stabilization Wait Time Oscillation stabilization
93. P6DIR register A pull up resistor for each P63 44 A3 SEG20 bit can be selected individually by the P6PLU register P64 45 A4 SEG19 At reset when single chip mode is selected the input P65 46 A5 SEG18 mode is selected and pull up resistors for P60 to P67 P66 47 A6 SEG17 are disabled high impedance output P67 48 A7 SEG16 When configured as outputs these pins can drive segments P70 49 vO A8 000 SEG15 l port 7 8 bit CMOS tri state VO port P71 50 A9 SDO1 SEG14 Each bit can be set individually as either an input or P72 51 A10 SDO2 SEG13 output by the P7DIR register A pull up or pull down P73 52 A11 SDO3 SEG12 resistor for each bit can be selected individually by the P73 53 A12 SDO4 SEG11 P7PLUD register However pull up and pull down P75 54 A13 SDO5 SEG10 resistors cannot be mixed P76 55 A14 SDO6 SEG9 This port contains a synchronous output function for P77 56 A15 SDO7 SEG8 external 2 interrupt timer 1 interrupt timer 2 interrupt and timer 4 interrupt At reset when single chip mode is selected the input mode is selected and pull up resistors for P70 to P77 are disabled high impedance output When configured as outputs these pins can drive segments I 12 Pin Description Chapter 1 Table 1 3 5 Pin Function Summary 3 7 Name s m y o Function Description P80 74 VO DO SEG26 VO port 8 8 bit CMOS tri state VO port P81 73 D1 SEG27 Each individual bit can be switched to
94. SEG1 63 P81 D1 SEGO 64 P80 DO I 16 Pin Description Chapter 1 Table 1 3 9 Pin Function Summary 7 7 Overview No Name 80 y o Function Description pin MMOD 14 Input Memory mode switch This pin sets the memory expansion mode Set the input pin input low Do not change the setup after reset NWE 37 Output P50 Write enable pin Memory control signals for an expanded memory Active low space external to this LSI NRE 38 Output P51 Read enable pin NWE is a strobe signal that is output for writing to Active low external memory NCS 39 Output P52 Chip select pin NRE is a strobe signal that is output for reading from Active low external memory NDK 28 Input P06 BUZZER Data acknowledge pin NCS is a chip select signal that is output when external Active low memory is accessed AO 41 Output P60 SEG23 Address pin NDK is an acknowledge signal that indicates the A1 42 Output P61 SEG22 external memory access is complete A2 43 Output P62 SEG21 A3 44 Output P63 SEG20 A4 45 Output P64 SEG19 AO to A16 are address signals output to external A5 46 Output P65 SEG18 memory A6 47 Output P66 SEG17 DO to D7 are data signals that input data to and output A7 48 Output P67 SEG16 data from external memory A8 49 Output P70 SDOO SEG15 A9 50 Output P71 SDO1 SEG14 A10 51 Output P72 SDO2 SEG13 A11 52 Output P73 SDO3 SEG12 12 53 Output 74 004 SEG11 A13 54 O
95. SLOW mode fs fx 4 30 Cascade Connection Chapter 5 8 bit Timers At cascade connection the binary counter and the compare register are operated as a 16 bit regis ter At operation set the TMnEN flag of the upper and lower 8 bit timers to 1 to be operated Also the clock source is the one which is selected in the lower 8 bit timer Other setup and count timing is the same to the 8 bit timer at independently operation When timer 2 and timer 3 are used in cascade connection timer 3 interrupt request flag is used Disable the timer 2 interrupt Timer pulse output of timer 2 is L fixed output At the cascade connection if the binary counter should be cleared by rewriting the compare register the TMnEN flags of the lower and upper 8 bits timers mode registers should be set to 0 to stop the counting then rewrite the compare register Also set the 2 register by the 16 bit access instruction Cascade Connection 31 Chapter 5 8 bit Timers 5 9 2 Setup Example mCascade Connection Timer Setup Example Timer 2 Timer 3 Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 2 and timer 3 as a 16 bit timer is shown An interrupt is generated in every 2500 cycles 1 ms by selecting source clock to fs 4 fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedur
96. TBICR The time base interrupt control register TBICR controls interrupt level of time base interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter enable flag MIE of PSW is 0 When the interrupt level flag is set to level TBLV1 TBLVO 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 1 0 TBICR LV1 TBIE TBIR Atreset 00 00 TBIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated TBIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt level fla Lvi LVO P 9 CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 10 Time Base Interrupt Control Register TBICR x 03FE7 R W 26 Control Registers Chapter 3 Interrupts Serial interface 0 Interrupt Control Register SCOICR The serial interface 0 interrupt control register SCOICR controls interrupt level of serial interface 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 SCOLV1 SCOLVO 1 the interrupt of its vector is disabled r
97. VI 30 16 bit Timer Capture Chapter 7 Time Base Timer 8 bit Free running Timer Chapter 7 Time Base Timer 8 bit Free running Timer 7 1 Overview This LSI has a time base timer and a 8 bit free running timer timer 5 Time base timer is a 13 bit timer counter These timers stop the timer counting only at standby mode STOP mode 7 1 1 Functions Table 7 1 1 shows the clock sources and the interrupt generation cycles that timer 5 and time base timer can select Table 7 1 1 Clock Source and Generation Cycle Timer 5 8 Bit free running timer Timer operation Interrupt source TBIRQ fosc fs 4 Clock source Se fx fosc x 1 213 1 fx x 1 213 fosc x 1 27 fosc x 1 28 fosc x 1 29 fosc x 1 219 Interrupt generation fosc x 1 213 The interrupt generation cycle is decided by the any cycle 1 27 value written to fx x 1 28 72 fx x 1 29 72 fx x 1 219 fx x 1 2783 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 can be used as a clock source of time base timer is selected to fosc can be used as a clock source of time base timer is selected to fx Time base timer and timer 5 cannot stop timer counting VII 2 Overview Chapter 7 Time Base Timer 8
98. Vss amplitudes is input to the XI pin The supply current during HALTO mode 1004 and IDD5 are measured under the following conditions After all I O pins are set to input mode and the oscillation is set to lt HALTO mode the MMOD pin is at Vss level the input pins are at VDD level and a 20 MHz 8 00 MHz square wave of VDD and Vss amplitudes is input to the OSC1 pin The supply current during HALT1 mode IDD6 and IDD7 are measured under the following conditions After all pins set to input mode and the oscillation is set to HALT1 mode the MMOD pin is at Vss level the input pins are at VDD level and a 32 768 kHz square wave of VDD and Vss amplitudes is input to the XI pin The supply current during STOP mode 1008 and IDD9 are measured under the following conditions After the oscillation is set to STOP mode the MMOD pin is at Vss level the input pins are at VDD level and the OSC1 and XI pins are unconnected Electrical Characteristics I 23 Chapter 1 Overview is for EPROM vers 40 to 85 20 to 70 VDD 2 0 V T2 3 v to 5 5v VSS 0 Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 1 MMOD 10 Input high voltage 1 0 8 VDD VDD 11 Input high voltage 2 VDD 4 5 V to 5 5 0 7 VDD VDD 12 Input low voltage 1 VIL1 0 0 2 VDD 13 Input low voltage 2 ViL2 VDD 2 3 V to 5 5 V 0 0 3 VDD 14 Input le
99. W Synchronous output control register 37 Port 7 P7DIR xOS3F37 R W Port 7 direction control register IV 35 P7PLUD 47 R W 7 Pull up Pull down control register 35 P7OUT 17 R W Port 7 output register IV 35 R W Readable Writable IV 44 Synchronous Output Port 7 Chapter 4 Ports 4 10 3 Operation iSynchronous Output Setup The synchronous output control register SYSMD selects the synchronous output pin of the port 7 in each bit The synchronous output event is selected by the pin control register 2 FLOAT2 Table 4 11 2 Synchronous Output Event Page Synchronous output Port 7 V 31 port External interrupt 2 Ill 19 IRQ2 Output event Timer 2 V 25 Timer 4 VI 24 When the external interrupt 2 IRQ2 is selected the interrupt edge should be specified The interrupt edge can be specified by the external interrupt 2 control register IRQ21CR The synchronous output recognizes the generation of the specified edge as an event iSynchronous Output Operation When the synchronous output control register SYSMD is set to disable the synchronous output I O port the port 7 is functioned as a general port g Figure 4 10 1 Block Diagram After the output mode is selected by the port 7 direction control register P7DIR if the synchronous output is enabled by the synchronous output control register SYSMD the value of the sync
100. X 39 Chapter 10 Serial Interface 0 Pin Setup 1 2 channels at transmission Table 10 3 19 shows the pins setup at UART serial interface transmission The pins setup is common to the TXD pin RXD pin regardless of those pins are independent connected The RXD pin can be used as general port P01 Table 10 3 19 UART Serial Interface Pin Setup 1 2 channels at transmission Data output pin Data input pin Setup item TXD pin RXD pin Pin 1 TXD RXD pins connected or independe TXD RXD pins SCOMD3 SCOIOM Serial data output 1 input Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS Push pull Style N ch open drain SCOMD3 SCOSBOM Output mode VO PODIR PODIRO Added Not added Pul up POPLU POPLUO Setup 2 channels at reception Table 10 3 20 shows the pins setup at UART serial interface reception with 2 channels TXD pin RXD The TXD can be used as general port P00 Table 10 3 20 UART Serial Interface Pin Setup 2 channels at reception Data output pin Data input pin Setup item TXD pin RXD pin Pin Poo 1 TXD RXD pins independent TXD pin SCOMD3 SCOIOM port serial data input Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS Style input mode VO PODIR PODIR1 added not added Pull up POPLU POPLU1 X 40 Operation Chapter 10 Serial Interface 0
101. bit Instructions Number of instructions 37 Addressing modes 9 Instruction length Basic portion 1 byte min Extended portion 0 5 byte x n 0 lt lt 9 Basic Internal operating frequency max 10 MHz performance Instruction execution Min 1 cycle Inter register operation Min 2 cycles Load store Min 2 cycles Conditional branch 2 to 3 cycles Pipeline 3 stage instruction fetch decode execution Address space 256 KB max 64 KB for data 2 2 Memory space External bus Address 18 bit max Data 8 bit Minimum bus cycle 1 system clock cycle Interrupt Vector interrupt 3 interrupt levels Low power STOP mode dissipation mode HALT mode 2 Overview 2 1 1 ABUS BBUS Chapter 2 CPU Basics Block Diagram Data registers DO Processor status word T1 Clock Source oscillation Address registers D1 PSW T2 generator Stack pointer AO 02 SP 1 03 k Instruction execution controller nstruction decoder Program counter Incrementer Instruction Interrupt queue controller Y Program address Operand address 1 Interrupt bus Y Y Bus controller ry C ROM bus RAM bus Peripheral expansion 887 Y Y External interface Internal peripheral Intern
102. bit Free running Timer Block Diagram 7 1 2 Timer 5 Time Base Timer Block Diagram eseq Oulg L m gt a ub IM L OulSIA L lt A Jejunoo 19 8 16 8 Jeui 151 A A gt X 5101049 X n n W lt x A X 259 lt visi A SH TOL LHISIALL 0416111 MOSIALL cMOSINL IOSAL 4 oso OMOSWL Block Diagram Timer 5 Time Base Timer Figure 7 1 1 3 Overview Chapter 7 Time Base Timer 8 bit Free running Timer 7 2 Control Registers Timer 5 consists of binary counter TM5BC compare register TM5OC and is controlled by mode register TM5MD Time base timer is controlled by mode register TM5MD too 7 2 1 Control Registers Table 7 2 1 shows the registers that control timer 5 time base timer Table 7 2 1 Control Registers Register Address Function Page TM5BC x 03F68 Timer 5 binary counter VII 5 TM5OC x O3F78 Timer 5 compare register VII 5 Timer 5 TM5MD x 03F88
103. bit is enabled Stop Stop bit bit RXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 15 Reception Timing parity bit is disabled Operation Chapter 10 Serial Interface 0 mSequence Communication bit Y n 1 st reception 2 nd reception bit UART interrupt signal lt 2 nd reception is disabled On the above sequence communication this UART cannot regard start bit when the H period of the interrupt signal generated inside at reception complete and the falling edge of start bit input from the RXD pin are happened at the same time 1 machine cycle Therefore from the 2nd reception the operation cannot be properly executed To prevent this the reception interrupt signal and the falling edge of the start bit should not be happened at the same time There are 2 ways to solve it Method 1 by stop bit Set the stop bit at the transmission side to 2 bits and set the stop bit at the reception side to 1 bit For parity bit set the same to both sides of the reception and transmission Method 2 by parity bit Set the transmission parity bit to always 1 and set the reception parity bit to none For stop bit set the same to both sides of the reception and transmission At the reception parity bit is regarded as one of stop bit This error can be prevented if one of the above methods can be enabled Both methods do not depend on the combination of the oscillation fr
104. bpO TMBCKO 0 2 Select the interrupt generation cycle TM5MD x 3F88 bp6 4 TMBIR2 0 100 3 Set the interrupt level TBICR x 3FE7 bp7 6 TBLV1 0 01 4 Enable the interrupt 7 bp1 TBIE 1 Select fosc as a clock source by the TM5CKO flag of the timer 5 mode register TM5MD Select the selected clock x 1 213 as an interrupt generation cycle by the TM5IR2 0 flag of the TM5MD register Set the interrupt level by the TBLV1 0 flag of the time base interrupt control register TBICR If any interrupt request flag had already been set clear it 6 Chapter 3 3 1 4 Interrupt Flag Setup Set the TBIE flag of the TBICR register to 1 to enable the interrupt the above steps 1 2 can be set at once When the selected interrupt generation cycle has passed the interrupt request flag of the time base interrupt control register TBICR is set to 1 14 Time Base Timer Chapter 8 Watchdog Timer Chapter 8 Watchdog Timer 8 1 Overview This LSI has a watchdog timer This timer is used to detect software processing errors It is controlled by the watchdog timer control register WDCTR And once an overflow of watchdog timer is generated a watchdog interrupt WDIRQ is generated If the watchdog interrupt is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a syste
105. clock input Serial interface 0 clock output SCOMDS register SCOSBTS flag Figure 4 2 4 Block diagram P02 Reset PN POPLU6 Pull up resistor control DQ gt Write Read Reset PODIR6 direction control Jo gt Write Read P06 F Reset m POOUT6 j gt Port output data o U 122 Write Read X TIT POING Schmitt input Port input data Read Data acknowledge signal Buzzer output Expansion control DLYCTR register BUZOE flag memory expansion mode input mode is always selected Figure 4 2 5 Block diagram P06 In memory expansion mode 06 pin is used for pin even if the handshake mode is not used So P06 cannot be used for general input pin or buzzer output Port 0 IV 9 Chapter 4 Ports 4 3 Port1 4 3 1 Description Port Setup Each bit of the port 1 control I O direction register P1DIR can be set individually to set pins as input or output The control flag of the port 1 direction control register P1DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 1 direction control register P1DIR to 0 and read the value of the port 1 input register P1IN To output data to pin set the control flag of the port 1 direction control register P1DIR to 1 and write the value of the port
106. compare register at fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM4MD x 3F84 bp6 TM4EN 20 2 Setthe special function pin to output mode P1OMD x 3F39 bp4 P14TCO 1 P1DIR x 3F31 bp4 P41DIRA 21 3 Select the normal timer operation TMAMD x 3F84 bp5 0 4 Select the count clock source TM4MD 847 bp2 0 TM4CK2 0 000 5 Set the timer pulse output cycle TM40C x 3F75 x 3F74 x 00C7 6 Start the timer operation TMAMD x 3F84 1 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the P14TCO flag of the port 1 output mode register P1OMD to 1 to set P14 pin as the special function pin Set the P1DIR4 flag of the port 1 direction control register P1DIR to 1 to set output mode If it needs pull up resister should be added Chapter 4 I O Ports Set the TM4PWM flag of the timer 4 mode register TM4MD to 0 to select the normal timer operation Select fosc as a clock source by the TM4CK1 0 flag of the TM4MD register Set the 1 2 frequency of the timer pulse output cycle to the timer 4 compare register TM40C To be 100 kHz by a divided 20 MHz set as follows 200 1 199 7 Set the TM4EN flag of the TM4MD register to 1 to start timer 4 VI 18
107. connection Remote control carrier output fs fosc ane 6 4 5 4 S Clock source fx fx fs 16 056 213 2 input input 65 213 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 When timer 3 is used as a baud rate timer for serial interface function it is not used as a general timer Description of timer 5 is shown in Chapter 7 2 Overview Chapter 5 8 bit Timers Block Diagram 5 1 2 E Timers 2 and Block Diagram WMdeWL 9 97278 10482005 indui sd XN S indu OIL Andino OWL 2 4 0 E 918 4 Y 950 G EaR 1ue e gt snouoJuou S lt peau indino xoojo 1 eue S 24 ndjno Y HOgENL Y Andino TERT LO Ja UNOD 19 8 19junoo 19 8 OUIEIALL uon 2 yore SOEWL JOZNL Jejsibe1 NESW JejsiBo
108. controller Detects interrupt requests from peripheral functions and requests CPU shift to interrupt processing Bus controller Controls connection of CPU internal bus and CPU external bus Internal peripheral functions Includes peripheral functions timer serial interface A D converter etc Peripheral functions vary with model Figure 2 1 1 Block Diagram and Function Overview Chapter 2 CPU Basics 2 1 2 CPU Control Registers This LSI locates the peripheral circuit registers in memory space x 03F00 to with memory mapped I O CPU control registers are also located in this memory space Table 2 1 2 CPU Control Registers Registers Address RW Function Pages CPUM x O3F00 R W CPU mode control register ll 24 MEMCTR x 03F01 RAW Memory control register Il 17 Reserved x OSFEO For debugger NMICR xOSFE1 R W Non maskable interrupt control register Ill 16 2 xxxICR R W Maskable interrupt control register Ill 17 to 27 Reserved gt Reserved For reading interrupt vector data on interrupt process 1 of the register is only readable 4 Overview Chapter 2 CPU Basics 2 1 3 Instruction Execution Controller The instruction execution controller consists of four blocks memory instruction queue instruction regis ters and instruction decoder Instructions are fetched in 1 byte un
109. display duty by LCODTY1 0 LCMD x 3FCD flags of the LCD mode control register bp5 4 LCDDTY1 0 10 LCMD 3 Setup of the LCD clock 3 Setfosc 2 5 as the LCD clock source by LCMD x 3FCD to 0 flags of the LCD mode control bp3 0 LCDCK3 0 0100 register LCMD 4 Setup of the segment output segment port 4 Select SEGO 7 by SEGSEL6 0 flag of the pins output control register LCCTR LCCTR x bp6 0 SEGSEL6 0 x 60 5 Setup of the display data 5 Set 23 as the display data by the segment Segment output latch SEG1 0 output latch SEGO to 7 x 3FBD to x 3FC0 x 31 Chapter 11 11 4 3 LCD Display Segment output latch SEG3 2 Examples 1 2 Duty X SFBE x 22 Segment output latch SEG5 4 x 3FBF x 30 Segment output latch SEG7 6 X 3FC0 x 32 6 Start the LCD operation 6 Setthe LCDEN flag of the LCD mode control LCMD x 3FCD register LCMD to 1 to start the LCD bp7 LCDEN 1 operation XI 20 LCD Function Operation Chapter 11 LCD Functions LCD Function Operation XI 21 Chapter 11 LCD Functions 11 4 5 LCD Display Examples 1 3 Duty 81 3 Duty 101 485 487 Segment Latch 9 y3FBF x SFBF x 3FBE x3FBD x3FBD bit7 bit3 open bit6 bit2 bit5 bit1 bit4 bitO A electrode B electrode iit no
110. display mode of 1 4 duty 1 3 bias make the double digit 8 segment LCD panel display 23 la Display Examples 1 4 Duty It is used 4 MHz as the high oscillation clock fosc 122Hz as 2 for LCD clock and 31 Hz as frame frequency An example setup procedure with a description of each step is shown below Chapter 11 11 4 7 LCD Setup Procedure Description Stop the LCD operation LCMD x 3FCD bp7 LCDEN ll Setup of the LCD display duty LCMD x 3FCD bp5 4 LCDDTY1 0 00 Setup of the LCD clock LCMD x 3FCD bp3 0 LCDCK3 0 0100 Setup of the segment output segment port pins LCCTR x 3FCC bp6 0 SEGSEL6 0 x40 Setup of the display data Segment output latch SEG1 0 X SFBD x 5E Segment output latch SEG3 2 X 3FBE x 7C Start the LCD operation LCMD x 3FCD bp7 LCDEN ll Set the LCDEN flag of the LCD mode control register LCMD to 0 to stop the LCD operation Set 1 4 as the display duty by LCODTY1 0 flags of the LCD mode control register LCMD Set 2 as the LCD clock source by LCDCK3 0 flags of the LCD mode control register LCMD Select SEGO 3 by SEGSEL6 0 flags of the output control register LCCTR Set 23 as the display data by the segment output latch SEGO 3 x 3FBD to x 3FBE Chapter 11 11 4 7 LCD Display Examples 1 4 Duty Set the LCDEN flag of the LCD mode control register LCMD to
111. input pin for 2 bits can be selected individually by KEYS 19 PA3 the key interrupt control register KEY4 20 PA4 When not used for KEY input these pins can be used KEYS 21 PA5 as normal pins KEY6 22 PA6 KEY7 23 PA7 VLC1 7 LCD power supply These pins supply power to the LCDs VLC2 6 VDD is normally devided by resistors to supply this VLC3 5 voltage COMO 1 Output LCD common outputs These pins output common signal with the required COM1 2 timing to the LCD display Also they may be connected COM2 3 to the common pins on the LCD panel COM3 4 LEDO 46 Output P50 NWE LED large current LED driving pins LED1 47 P51 NRE output LED2 48 P52 NCS LED3 49 P53 A16 SEG24 SEG24 40 Output P53 A16 LED3 LCD segment output Connect to segment pins on the LCD panel These pins SEG23 41 P60 0 are allocated to PORT53 60 to 67 70 to 77 80 to 87 SEG22 42 P61 1 When segments are not used these pins can be used SEG21 43 P62 A2 as normal pins At reset all pins are set to the input SEG20 44 P63 A3 mode SEG19 45 P64 A4 SEG18 46 P65 A5 SEG17 47 P66 A6 SEG16 48 P67 A7 SEG15 49 P70 A8 SDOO SEG14 50 P71 A9 SDO1 SEG13 51 P72 A10 SDO2 SEG12 52 P73 A11 SDO3 SEG11 53 P74 A12 SDO4 SEG10 54 P75 A13 SDO5 SEG9 55 P76 A14 SDO6 SEG8 56 P77 A15 SDO7 SEG7 57 P87 D7 SEG6 58 P86 D6 SEG5 59 P85 D5 SEG4 60 P84 D4 SEG3 61 P83 D3 SEG2 62 P82 D2
112. mode 0 General port 1 A15 to A12 address output EXADVS ing nary Ganon id 0 General port 1 A16 address output Expansion address output control register EXADV R W Figure 4 5 2 Port 5 Registers 2 3 In memory expansion mode unused address pin can be used as general port Pot5 IV 19 Chapter 4 I O Ports 6 5 4 3 2 1 0 LCCTR 20 5 SEGSEL6 SEGSEL5 SEGSEL4 SEGSEL3 SEGSEL2 SEGSEL1 At reset 0000000 SEG24 SEGSELO Port P53 selection 0 Port P53 1 SEG24 SEG20 to 23 SEGSEL1 Port P60 to P63 selection 0 Port P60 to P63 1 SEG20 to 23 SEG16 to 19 SEGSEL2 Port P64 to P67 selection 0 Port P64 to P67 1 SEG16 to 19 SEG12 to 15 SEGSEL3 Port P70 to P73 selection 0 Port P70 to P73 1 SEG12 to 15 SEG8 to 11 SEGSEL4 port P74 to P77 selection 0 Port P74 to P77 1 SEG8 to 11 SEG4 to 7 SEGSELS Port P84 to P87 selection 0 Port P84 to P67 1 SEGA to 7 SEGO to 3 SEGSEL6 Port P80 to P83 selection 0 Port P80 to P83 SEGO to 3 Segment output control register LCCTR x O3FCC R W Figure 4 5 3 Port 5 Registers 3 3 4 5 3 Block Diagram Pull up resistor control direction control Port output data Port input data Write enable signal
113. of low speed oscillation clock before the transition from NORMAL to SLOW 2 cleared at IDLE High speed Setting value of Program for waiting time oscillation WAIT_CONST MOV WAIT CONST DO clock MHz decimal LOOP NOP 17 195 18 206 19 218 ADD 1 DO 20 229 BNE LOOP low speed oscillation clock 32 768 kHz When the execution time at NORMAL is above that duration also its possibility will be Set the program for switching to SLOW mode not to NORMAL mode from IDLE II 26 Standby Functions Chapter 2 CPU Basics 2 4 4 Transition to STANDBY Modes The program initiates transitions from a CPU operating mode to the corresponding STANDBY HALT STOP modes by specifying the new mode in the CPU mode control register CPUM Interrupts initiate the return to the former CPU operating mode Before initiating a transition to a STANDBY mode however the program must 1 Set the maskable interrupt enable MIE in the processor status word PSW to 0 to disable all maskable interrupts temporarily 2 Set the interrupt enable flags in the interrupt control registers xxxICR 1 or 0 to specify which interrupts do and do not initiate the return from the STANDBY mode Set MIE 1 to enable those maskable interrupts NORMAL SLOW mode Clear MIE flag in the PSW and all interrupt enable flags xxx IE All interrupts disabled in the mask
114. of the timer 4 is cleared during operation it does not stop until the next count clock Therefore during max 1 count clock after the TM4EN is cleared the binary counter cannot be initialized VI 10 16 bit Timer Count 6 3 2 Timer Operation Setup Example Timer 4 Setup Example Chapter 6 16 bit Timer Timer 4 generates an interrupt constantly for timer function Fosc fosc 20 MHz at operation is selected as a clock source to generate an interrupt every 1000 cycles 50 us An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter x 3F84 4 0 Select the normal timer operation x 3F84 bp5 TM4PWM 0 Select the count clock source TM4MD x 3F84 bp2 0 TM4CK2 0 000 Set the interrupt generation cycle TM40C x 3F75 x 3F74 x 03E7 Set the interrupt level TMAICR x 3FEF bp7 6 TM4LV1 0 10 Enable the interrupt TMAICR x 3FEF bp1 1 Start the timer operation x 3F84 bp6 4 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the TM4PWM flag of the TM4MD register to 0 to select the normal timer operation Select fosc as a clock source by the TM4CK2 0 flag of the TM4MD register Set the interrupt generation cycle to the timer 4 compare register 4 The cycle is 1000
115. port IV 30 Port7 FLOAT1 FLOAT2 SYSMD Chapter 4 Ports At reset Atreset 000 PzRpwN Port 7 pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor PARDWN pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor P21IM P21 input mode selection 0 Schmitt trigger input 1 ACZ input P7SYEVS1 P7SYEVSO Port 7 synchronous output event selection External interrupt 2 IRQ2 Timer 4 interrupt Timer 2 interrupt Timer 1 interrupt 7 6 5 4 3 2 1 0 P211M PARDWN P7RDWN Pin control register 1 FLOAT1 X 03F4B R W 7 6 5 4 3 2 1 0 P7SYEVS1 P7SYEVSO Pin control register 2 FLOAT2 0 4 R W 7 6 5 4 3 2 1 0 SYSMD7 SYSMD6 SYSMD5 S YSMD4 SYSMD3 SYSMD2 SYSMD SYSMDO Atreset 00000000 SYSMD Synchronous output control selection 0 Use as I O pin 1 Use as synchronous output pin Synchronous output control register SYSMD X 03F1F R W Figure 4 7 3 Port 7 Registers 3 4 Set the bp1 Oof the pin control register 2 FLOAT2 to the value except 11 Pot7 IV 31 Chapter 4 I O Ports 7 6 5 4 3 2 1 0 LCCTR SEGSEL6 SEGSEL5 SEGS
116. port 1 is used as pulse output the settings of the port 1 direction control register Set the compare register value as follows The timer pulse output cycle The compare register value 1 The count clock cycle x 2 The initial value of timer output and the initialization low level Initial value To initialize after reset release Set to low level Program example After timers 2 and 3 are set to Timer 2 Low level cascade connection the setting should be the original mov x04 TM3MD bclr TM3MD 2 After P13 output selection is set to the timer 2 PWM output TM2PWM mov x08 TM3MD flag 1 the setting should be back bclr TM3MD 3 to the timer 3 output Timer 3 indefinite 20 8 bit Timer Pulse Output Chapter 5 8 bit Timers 5 6 8 bit PWM Output The TMnIO pin outputs the PWM waveform which is determined by the match timing for the compare register and the overflow timing of the binary counter 5 6 1 Operation Operation of 8 bit PWM Output Timer 2 The PWM waveform with any duty cycle is generated by setting the duty cycle of PWM H period to the compare register TMnOC The cycle is the period from the full count to the overflow of the 8 bit timer Table 5 6 1 shows PWM output pins Table 5 6 1 Output Pins of PWM Output Timer 2 2 output pin P12 PWM output pin output pin P13
117. register PBOUT Each pin can be set individually if pull up resistor is added or not by the port 8 pull up resistor control register P8PLU Set the control flag of the port 8 pull up resistor control register PBPLU to 1 to add pull up resistor At reset the P80 to P87 input mode is selected and pull up resistors are disabled high impedance output Special Function Pin Setup P80 to P87 are used as LCD driving pins segment output as well The bp5 and 6 of the segment output control register LCCTR set if they used as segment output pins or general I O pins In memory expansion mode P80 to P87 are I O pins to the expansion memory In this mode register cannot control input or output Table 4 8 1 Expansion Pins P80 to P87 Pins In memory expansion mode P80 DO External memory data bp0 P81 D1 External memory data bp1 P82 D2 External memory data bp2 P83 D3 External memory data bp3 P84 D4 External memory data bp4 P85 D5 External memory data bp5 P86 06 External memory data bp6 P87 D7 External memory data bp7 IV 34 Port 8 Chapter 4 Ports Low Vss level High VoD level Pin is Low Vss level Pin is High VDD level mode selection Output mode Pu
118. register is stored to the received data buffer SCORXB automatically SCORXB can store data up to 1 byte SCORXB is rewritten in every communication complete so read data of SCORXB till the next receive complete And before the next data reception is started the same data to the SCORXB can be read even if the SCOTRB is reading When the SCOSBIS flag of the SCOMD3 register is set to serial interface input the SCOTRI flag of the SCOMD register is set to 1 at the same time SCOIRQ is generated SCOTRI is cleared to 0 when the next reception has completed Receive Bit Count and First Transfer Bit On reception when the transfer bit count is 1 bitto 7 bits the data reading method from the received data buffer SCORXB is different depending on the first transfer bit selection At MSB first data are read from the lower bits of SCORXB When there are 6 bits to be transferred as shown on figure 10 3 2 1 if data F to are stored to to bp5 of SCORXB Also data are read as the same way At LSB first data are read from the upper bits of SCORXB When there are 6 bits to be transferred as shown on figure 10 3 2 2 if data A to are stored to to bp5 of SCORXB But their order is changed the SWAP circuit and reading is started from the upper bits Operation X 15 Chapter 10 Serial Interface 0 SCORXB F E D Figure 10 3 2 1 Receive Bit Count and Transfer First Bit starting with
119. serial interface 0 that can be used for both communication types of clock synchro nous and UART Half duplex 10 1 1 Functions Table 10 1 1 shows functions of serial interface 0 Table 10 1 1 Serial Interface 0 Functions Communication style clock synchronous UART half duplex Interrupt SCOIRQ SCOIRQ Used pins SBOO SBIO SBTO TXD RXD 3 channels type Y 2 channels type Y SBOO SBTO Y 1 channel type 5 Y TXD 7 bits 1 stop Specification of transfer bit 1 to 8 bits 7 bits 2 stops count Frame selection 8 bits 1 stop 8 bits 2 stops Selection of parity bit Y 0 parity m 1 parity Parity bit control odd parity even parity s no selection Selection of start condition Start bit is always added Specification of the first N transfer bit Specification of input edge _ output edge Internal clock 1 8 dividing only Ve cid ug is available fs 2 fs 2 fs 4 fs 4 Clock source fs 16 6 16 Timer 3 output Timer 3 output External clock Maximum transfer rate 5 0 MHz 625 kbps fosc Machine clock High speed oscillation fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 When the transmission and reception are operated at the same time at master communication of the clock synchronous select no start condition 4 Set fs 2 as maximum frequency for external clock X 2 Overview Chapter 10 Serial Interface 0 10 1 2 Bloc
120. set the WDEN flag of the watchdog timer control register WDCTR to 0 to stop the watchdog timer before CPU mode is switched to STOP mode 6 Operation Chapter 8 Watchdog Timer 8 3 2 Setup Example The watchdog timer detects errors On the following example the watchdog timer period is set to 219 x system clock in ROM option An example setup procedure with a description of each step is shown below Binitial Setup Program Watchdog Timer Initial Setup Example Setup Procedure Description 1 Start the watchdog timer operation 1 Setthe WDEN flag of the WDCTR register to WDCTR x O3F02 start the watchdog timer operation WDEN 1 Routine Program Watchdog Timer Constant Clear Setup Example Setup Procedure Description 1 Set the constant watchdog timer clear 1 Clear the watchdog timer under the 1 4 cycle BCLR WDCTR WDEN of 219 x system clock WDEN 0 The watchdog timer clear should be inserted in BSET WDCTR WDEN the main routine with the same cycle and to WDEN 1 be the set cycle Operate the watchdog timer again after it is stopped Upper 2 bits of the counter are cleared The upper 2 bits of the watchdog timer are cleared when the WDEN flag of the watchdog timer control register WDCTR is set to 0 Therefore depending on the clear timing the watchdog timer may be reset at 1 4 x watchdog timer frequenc
121. should be odd 0 1 1 Control the total number 1 of parity bit and character bit should be even 1 none Do not add parity bit Break Status Transmission Control Setup The SCOBRKE flag of the SCOMD2 register generates the break status If SCOBRKE is set to 1 to select the break transmission all bits from start bits to stop bits transfer 0 Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be determined by the SCOORE SCOPEK and SCOFEF flag of the SCOCTR register Even one of those errors is detected the SCOERE flag of the SCOMD1 register is set to 1 The reception error flag is renewed at generation of the reception complete interrupt SCOIRQ The judgement of the received error flag should be operated until the next communication has finished The communication operation does not have any effect on those error flags Table 10 3 15 shows the list of reception error source Table 10 3 15 Reception Error Source of UART Serial Interface Flag Error Error source SCOORE Overrun error Next data is received before reading the receive buffer SCOPEK Parity error at fixed to 0 when parity bit is 1 at fixed to 1 when parity bit is 0 2 The total of 1 of parity bit and character bit odd parity ioven parity The total of 1 of parity bit and character bit even parity 5 098
122. synchronous output value storage register is not always same to the value of the port 7 output register P7OUT Therefore the pin output may be changed at the switching from the general output to the synchronous output VI 26 16 bit Timer Synchronous Output Chapter 6 16 bit Timer 6 8 16 bit Timer Capture 6 8 1 Operation The value of a binary counter is stored to register at the timing of the external interrupt input signal Capture Operation with External Interrupt Signal as a Trigger Timer 4 Capture trigger of input capture function is generated at the external interrupt signal that passed through the external interrupt interface block The capture trigger is selected by the timer 4 mode register TM4MD and the external interrupt control register IRQOICR IRQ1ICR IRQ2ICR Here are the capture trigger to be selected and the interrupt flag setup Table 6 8 1 Capture Trigger External interrupt n control Interrupt starting edge Capture trigger source register register IRQnICR of external interrupt n 9 IRQO rising edge 1 isi falling edge Hf falling edge IRQ1 rising edge IRQ1 rising edge IRQ2 falling edge 0 IRQ2 falling edge IRQ2 rising edge Pa IRQ2 rising edge 1 1 1 An interrupt request and a capture trigger are generated at switching the active edge of an external interrupt by program when the setup is as follows 1 at switching the active
123. the normal timer operation Select the clock source to 2 input by the TM2CK2 0 flag of the TM2MD register Set the timer 2 compare register 2 the interrupt generation cycle Counting is 5 so the setting value should be 4 At that time the timer 2 binary counter TM2BO is initialized to 00 Set the interrupt level by the TM2LV1 0 flag of the timer 2 interrupt control register TM2ICR If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt Flag Setup 16 8 bit Event Count Chapter 5 8 bit Timers Setup Procedure Description 7 Enable the interrupt 7 Setthe TM2IE flag of the TM2ICR register to TM2ICR x 3FE6 1 to enable the interrupt bp1 TM2IE 1 8 Start the event counting 8 Set the TM2EN flag of the TM2MD register to TM2MD x 3F82 start timer 2 bp4 2 1 Every time TM2BC detects the falling edge of 2 input TM2BC counts up from x00 When TM2BC reaches the setting value of theTM2OC register the timer 2 interrupt request flag is set at the next count clock then the value of TM2BC becomes x 00 and counting up is restarted 8 bit Event Count V 17 Chapter 5 8 bit Timers 5 5 8 bit Timer Pulse Output 5 5 1 Operation The pin can output a pulse signal with any cycle B Operation of Timer Pulse Output Timers 2 and 3 The timers can output 2 x cycle signal compared to the setting val
124. timer 5 and time base timer Timer 5 Mode Register TM5MD 5 6 7 6 5 4 3 2 1 0 TM5CLRS TM5IR2 TM5IR1 TMSIRO 5 5 2 5 5 0 At reset 0XXXXXX0 TM5CKSO Time base timer clock source 0 fosc 1 fx TM5CK3 TM5CK2 TM5CK1 Timer 5 clock source fosc x 0 0 1 15 4 0 0 1 1 Output of time base timer 1 0 Synchronous fx 1 Synchronous output of time base timer Time base timer 2 TMSIR1 TMSIRO interrupt cycle selection 0 base selection clock x 1 2 0 1 Time base selection clock x 1 2 1 0 base selection clock x 1 2 1 base selection clock 1 2 1 X X base selection clock 1 2 TMS5CLRS Timer 5 binary counter clear selection 0 Enable the initialization of TM5BC as 5 is written 1 Disable the initialization of TM5BC as 5 is written is disabled as TM5CLRS 0 TMBIRQ is enabled as TM5CLRS 1 Figure 7 2 3 Timer 5 Mode Register TM5MD 88 R W Control Registers Chapter 7 Time Base Timer 8 bit Free running Timer 7 3 8 bit Free running Timer 7 3 1 Operation 8 bit Free running Timer Timer 5 The generation cycle of timer interrupts is set by the clock so
125. to COM1 to bit4 to bitb 75 i 25 x 3 COMO to 2 0 to bit2 bit4 to bit6 100 25 x 4 to bitO to bit3 bit4 to bit7 Overview XI 3 Chapter 11 LCD Functions it Block Diagram 11 1 4 LCD Driver C 0036 193 1993 0 02 HOO 2 00 191A 201A SSA A jouoo 5 SJBAUP UOWUWOD 97 1 i i m 5 O F 1 0935 1935 tz93S AEE E 4 01 yoqe ndino 48244 71 XN ox ell 710097 040021 0527 0 esey jasay kn jesoy oso Figure 11 1 1 LCD Driver Circuit Block Diagram Overview 4 11 2 Control Registers Chapter 11 LCD Functions The LCD is controlled by LCD mode control register LCMD and segment output control register LCCTR The LCD display data is stored in the segment output latch 11 2 1 Registers Table 11 2 1 shows the registers used to control LCD Tabel 11 2 1 LCD Control Registers Register abbreviat
126. to XI and leave XO open The chip will not operate with an external clock when using the STOP mode If these pins are not used connect XI to Vss and leave XO open NRST 32 Input P27 Reset pin Active low This pin resets the chip when power is turned on is allocated as P27 and contains an internal pull up resistor Typ 35 kQ Setting this pin low initializes the internal state of the device Thereafter setting the input to high releases the reset The hardware waits for the system clock to stabilize then processes the reset interrupt Also if 0 is written to P27 and the reset is initiated by software a low level will be output The output has an N ch open drain configuration If a capacitor is to be inserted between NRST and Vss it is recommended that a discharge diode be placed between NRST and VDD 1 2 6 25 26 27 28 vO SBOO TXD 5 RXD SBTO NDK BUZZER VO port 0 4 bit CMOS tri state l O port Each bit can be set individually as either an input or output by the PODIR register A pull up resistor for each bit can be selected individually by the POPLU register At reset the input mode is selected and pull up resistors are disabled high impedance output P10 P12 P13 P14 30 31 32 vO RMOUT VO port 1 4 bit CMOS tri state l O port Each bit can be set individually as either an input or output by th
127. unstable Pch transistor and Nch transistor of input inverter are on and through current goes to the input circuit That increases current consumption and causes power supply noise Input pin Input 10 KQ to 100 kQ d 10 kO to 100 kQ Input Input Figure 1 8 2 Unused Pins only for input Through current Current Pch Input pin Input Nch 0 5 Input voltage at VDD 5 V Input inverter organization Input inverter characteristics Figure 1 8 3 Input Inverter Organization and Characteristics Precautions 1 35 Chapter 1 Overview mUnused pins for I O Unused pins should be set according to pins condition at reset If the output is high impedance Pch Nch transistor output off at reset to stabilize input set 10 to 100 resistor to be pull up or pull down If the output is on at reset set them open Output control Output control 10 kQ to 100 kQ Output OFF Output OFF Data Data 10 to 100 Output OFF Output OFF a 10 kQ to 100 kQ Data 10 to 100 Figure 1 8 4 Unused I O pins high impedance output at reset 1 36 Precautions Chapter 1 Overview 1 8 3 Power Supply The Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on If the input pin voltage is applied before power supply is on a latch up occurs and causes the destruction of micro controller by a large
128. wait time is the period from the stop of oscillation circuit to the stabilization for oscillation Oscillation stabilization wait time is automatically inserted at releasing from reset and at recovering from STOP mode At recovering from STOP mode the oscillation stabilization wait time con trol register DLYCTR is set to select the oscillation stabilization wait time At releasing from reset oscillation stabilization wait time is fixed The timer that counts oscillation stabilization wait time is also used as a watchdog timer at anytime except at releasing from reset and at recovering from STOP mode Watchdog timer is initiated at reset and at STOP mode and starts counting from the initialize value 0000 when system clock fs is as clock source After oscillation stabilization wait time it continues counting as a watchdog timer Chapter 8 Watchdog timer Block Diagram of Oscillation Stabilization Wait Time watchdog timer WDCTR WDEN reset input Y Mia ree 2 Y R 7 gt internal reset release 5 25 A fs 2 15 24 Y ROM option R i 124 overflow M e overflow gt O gt 1 4 gt WDIRQ DLYCTR 1 4 1 4 gt J DLYSO 1 DLYS1 BUZCKO 127 BUZCK1 1 2 BUZOE
129. when the input signal P21 SENS pin is at intermediate range At the other level IRQ1 pin is set to the low level AC zero cross can be detected by setting the P21IM flag of the pin control register FLOAT1 to 1 approx 10 ms at 50 Hz approx 8 3 ms at 60 Hz AC line waveform gt Ideal IRQ1 Actual j Point A Figure 3 3 8 AC Line Waveform and IRQ1 Generation Timing Actual IRQ1 interrupt request is generated several times at crossing the 1 2 of AC line wave form So the filtering operation by the program is necessary If you select the noise filter the judgement of this program can be easier But it can not be used for the recover when OSC is stopped at the back up mode External Interrupts 43 Zero cross Detector Setup Example External interrupt 1 AC zero cross detector generates the external interrupt 1 IRQ1 by using P21 SENS pin The sampling clock is set to 15 22 and the noise filter is used An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the interrupt edge IRQ1ICR bp5 REDG1 21 Select the noise filter and its sampling clock x 3F8A bp3 1 bp5 4 NF1CKS1 0 00 Select the AC zero cross detector signal FLOAT1 x 3F4B bp2 P211M 1 Set the interrupt level IRQ1ICR bp7 6
130. x x x x register upper 8 bits x 0 Note x Initial value is unstable XIII 16 TM5BC7 TM5BC6 TM5BC3 TM5BC2 TM5BC1 TM5BCO TM20C7 TM20C4 TM20C2 TM20C1 20 0 x data TM20C6 TM20C5 x x Special Function Registers List x Timer 2 x pare register x x Bit Symbol Initial Value Description Chapter 13 Appendices Bit 4 Bit3 TM30C3 2 1 TM3OCO x x x x TM30C7 6 TM40CL7 TM4OCL6 TM40CL Timer 3 compare register TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCLO Timer 4 compare register lower 8 ibts TM4OCH7 TM40CH6 TM40CH5 TM4OCH4 TM40CH3 TM40CH2 TM40CH1 TM4OCHO x x x x x x x x Timer 4 compare register upper 8 bit TM50C7 TM50C6 5 4 5 5 2 5 1 5 x x x x x x x Timer 5 compare register TM2PWM Timer 2 operation mode Timer 2 count control TM2CK2 TM2CK1 Clock source TM2CKO TM3PWM TM3CK2 TM3CK1 TM3CKO 0 0 x x x Timer 3 count control P13 output at TM2PWM operation Clock source TM4PWM T4ICTS1 T4ICTSO TM4CK2 TM4CK1 TM4CKO 0 0 0 x x x 0 Timer 4 count control TMSIR2 TMSCLRS TMS binary coun
131. x Systemclock 1 6384 ms 210 Systemclock 102 4 us Chapter 9 Buzzer Oscillation Stabilization Wait Time Oscillation stabilization wait time at fosc 20 MHz aaa a II 32 Reset Chapter 3 Interrupts Chapter 3 Interrupts 3 1 Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corresponding interrupt service routine from an interrupt vector table reset non maskable interrupts NMI 8 maskable peripheral interrupts and 4 external interrupts For interrupts other than reset the interrupt processing sequence consists of interrupt request interrupt acceptance and hardware processing After the interrupt is accepted the program counter PC and processor status word PSW and handy addressing data HA are saved onto the stack And an inter rupts handler ends by restoring using the POP instruction and other means the contents of any regis ters used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was interrupted Maximum 12 machine cycles before execution and maximum 11 machine cycles after execution Each interrupt has an interrupt control register which controls the interrupts Interrupt control register consists of the interrupt level field LV1 0 interrupt enable flag IE and interrupt request flag IR Interrupt request flag IR
132. 0 PAPLUD3 0 1111 Select the key input interrupt P4IMD bp7 IRQ4SEL 1 Select the key input pin PAIMD bp1 0 PAKYEN2 1 11 Specify the interrupt active edge IRQ4ICR x 3FED bp5 REDG4 0 Set the interrupt level IRQ4ICR x 3FED bp7 6 IRQ4LV1 0 10 Enable the interrupt IRQ4ICR x 3FED IRQ4E 1 Set the PADIR3 0 flag of the port A direction control register PADIR to 0000 to set PAO to PAS pins to input pins Set the PAPLUD 3 0 flag of the port A pull up down resistor control register PAPLUD to 1111 to add the pull up resistance to PAO to pins Set the IRQ4SEL flag of the port A key interrupt control register PAIMD to 1 to select the external interrupt A source to the port A key interrupt Set the PAKYEN 2 1 flag of the port A key interrupt control register PAIMD to 11 to set PAO to pins to key input pins Specify the falling edge to the interrupt active edge by setting 0 to the REDG4 flag of the external interrupt 4 control register IRQ4ICR Set the interrupt level by the IRQ4LV1 0 flag of the IRQ4ICR register If the interrupt request flag has been already set clear it Chapter 3 3 1 4 Interrupt flag setup Set the IRQ4IE flag of the IRQ4ICR register to 1 to enable the interrupt Note The above 3 and 4 and 5 and 6 can be set at the same time If there is at least one input signal from th
133. 0 1 4 88 kHz 0 1 2 05 kHz 8 39 MHz 4 19 MHz 1 0 4 10 kHz 2 MHz 1 MHz 1 1 1 95 kHz 4 Operation 9 3 2 Setup Example Chapter9 Buzzer Buzzer outputs 2 kHz square wave from P06 pin It is used 8 39 MHz as the high oscillation clock fosc An example setup procedure with a description of each step is shown below Setup Procedure Description Set the buzzer frequency DLYCTR x 3F03 bp6 5 BUZCK1 0 01 Set POOUT x 3F 10 POOUT6 0 PODIR x 3F30 PODIR6 1 Buzzer output ON DLYCTR x 3F03 bp7 BUZOE 1 Buzzer output OFF DLYCTR x 3F03 bp7 BUZOE 0 Set the BUZCK1 0 flag of the oscillation stabilization wait control register DLYCTR to 01 to select fs 2 to the buzzer frequency When the high oscillation clock fosc is 8 39 MHz the buzzer output frequency is 2 kHz Set the output data POOUTE of P06 pin to 0 and set the direction control PODIR6 of 06 pin to 1 to select output mode pin outputs low level Set the BUZOE flag of the oscillation stabilization wait control register DLYCTR to 1 to output the square wave of the buzzer output frequency set by P06 pin Set the BUZOE flag of the oscillation stabilization wait control register DLYCTR to 0 to clear and pin outputs low level IX 5 Operation Chapter 10 Serial Interface 0 Chapter 10 Serial Interface 0 10 1 Overview This LSI contains a
134. 000 abs 8 d7 2 8 8 1 7 TBZ abs8 bp label if mem8 abs8 bp 0 PC 8 d1 1 label H PC 0 8 6 7 0011 0000 16 abs 8 dii H 3 if mem8 abs8 bp 1 PC 82PC Instruction Set 1 44 2 47 sign extension 3 411 sign extension XIII 23 Chapter 13 Appendices MN101C SERIES INSTRUCTION SET TBZ Mnemonic BZ i08 bp label Operation ifmem8 OTOPsio8 bp 0 PC 7sd7 abelsH 3PC if mem8 IOTOP io8 bp 1 PC 7 PC 0011 0100 Obp io8 Machine Code BZ io8 bp label i mem8 OTOPsio8 op 0 PC 8sdt lebe mema IOTOP io8 bp 1 PC 8 PC 0011 0100 1bp lt io8 2 BZ abs16 bp label if mem8 abs16 bp 0 PC 9 d7 label H PC if mem8 abs16 bp 1 PC 9 PC 0011 1110 Obp lt abs gt d BZ abs16 bp label if mem8 abs16 bp 0 PC 10 d1 1 gt if mem8 abs16 bp 1 PC 10 PC 0011 1110 16 lt abs gt dii TBNZ abs8 bp label if mem8 abs8 bp 1 PC 7 d7 label H PC if mem8 abs8 bp 0 PC 72PC 0011 0001 Obp abs d7 BNZ abs8 bp label If mem abs8 bp 1 PC 8 d1 label HPC mem8 abs8 bp 0 PC 82PC 0011 0001 1bp abs did 12 BNZ io8 bp label ii mem8 io bp 1 PC 7 d7 label HPC if me
135. 1 But at the slave communication the SCOSBTS flag needs not to be set to 1 X 12 Operation Chapter 10 Serial Interface 0 Transfer Bit Count The transfer bit count is selected from 1 bit to 8 bits Set it by the SCOLNG2 to 0 flag of the SCOMDO register at reset 000 4 The SCOLNG2 to 0 flags change at the opposite edge of the transmission data output edge SCOMDO register is changed Except in an 8 bit transfer reset the transfer bit count at the After the transfer has completed the transfer bit count the SCOLNG2 to 0 flags of the time of the next transmission to 0 flags of the SCOMDO register are changed the transfer bit count in the SCOLNG2 to 0 a When the SCOSBOS flag or the SCOSBIS flag of the SCOMD3 register is 1 and the SCOCE1 2 flags of the SCOMDO register may be incremented iStart Condition The SCOSTE flag of the SCOMDO register sets if a start condition is enabled or not If a start condition is enabled and input bit counter is cleared to start the communication The start condition if the SCOCE1 flag of the SCOMDO register is set to 0 is regarded when a data line SBIO pin with 3 channels or SBOO pin with 2 channels is changed from H to L as a clock line SBTO pin is H Also the start condition if the SCOCE1 flag is set to 1 is regarded when a data line SBIO pin with 3 channels or SBOO pin with 2 channels is changed from to L as a
136. 1 P1DIR x 3F31 bp4 21 3 Select the count clock source TMAMD 3 84 bp2 0 TM4CK2 0 000 4 Setthe PWM operation TMAMD x 3F84 bp5 TM4PWM 1 5 Set the PWM output H period and the location of the added pulse TMAOC x 3F75 x 3F74 x 0740 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the P14TCO flag of the port 1 output mode register P1OMD to 1 to set the P14 pin as a special function pin Set the P1DIR4 flag of the port 1 direction control register P1DIR to 1 to set output mode If it needs pull up resister should be added Chapter4 Ports Select fosc as a clock source by the TM4CK2 0 flag of the TM4MD register Set the TM4PWM flag of the timer 4 mode register TM4MD to 1 to select the PWM operation Set the H period of the PWM output in the lower 8 bits of the timer 4 compare register TMAOCL To be 1 4 duty of the full count 256 of the lower 8 bits in the timer 4 binary counter TM4BCL the setting value should be 256 4 64 x 40 Also set the location of the added pulse in the upper 8 bits of the compare register If it is set to x 07 the added pulse is appended 7 times in 256 repetitions VI 22 Added Pulse Type 16 bit PWM Output Chapter 6 16 bit Timer Setup Procedure Description 6 Start the timer operation 6 Set the TM4EN flag of the TM4MD register to
137. 1 to start the LCD operation XI 28 LCD Function Operation Chapter 12 A D Conversion 12 Functions Chapter 12 A D Converter 12 1 Overview This LSI has an A D converter with 10 bits resolution That has a built in sample hold circuit and the analog input can be switched channel 0 to 7 ANO to AN7 As A D converter is stopped the power consumption can be reduced by a built in ladder resistance 12 1 1 Functions Table 12 1 1 shows the A D converter functions Table 12 1 1 A D Converter Functions A D input pins 8 pins Pins AN7 to ANO Interrupt ADIRQ Resolution 10 bits Conversion time min 9 6 us as TAD 800 ns Input range VREF to VREF Built in ladder resistance Power consumption ON OFF a Keep reference voltage between Vrer and Vrer above 2 V XII 2 Overview 12 1 2 Block Diagram ANCTR1 Chapter 12 A D Converter 0 ANBUF1 ANBUFO ANBUFIO o p ANBUF11 z ANBUF12 ANC TRO 0 ANBUF13 50 ND ANBUF14 ANCHS1 ANST conversion ANBUF15 ANCHS2 7 ANBUF16 ANBUFOG ANLADE ANBUF17 ANBUFO7 7 ANCKO N 1 ANSHO ANSH1 5 3 Y VREF 23 ANO gt AN1
138. 1PLU4 P1PLU3 P1PLU2 P1PLUO 0 P1PLU Port 1 pull up resistor OFF POPLU2 POPLU1 POPLUO P2PLU2 P2PLU1 P2PLUO 0 0 0 Port 2 pull up resistor ON OFF P5PLU3 P5PLU2 P5PLU1 P5PLUO Port 5 pull up resistor ON OFF P2PLU P5PLU P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLUO 0 0 0 0 0 0 0 P6PLU Port 6 pull up resistor ON OFF P7PLUD7 P7PLUD6 P7PLUD5 P7PLUD4 P7PLUD3 P7PLUD2 P7PLUD1 P7PLUDO P7PLUD Port 7 pull up pull down resistor ON OFF P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLUO 0 0 0 0 0 0 0 P8PLU Port 8 pull up resistor ON OFF PAPLUD7 PAPLUD6 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO PAPLUD PARDWN P7RDWN 0 0 WM 34 FLOAT1 31 40 P21 input mode selection Port A pull up pul down selection Port 7 pull up pul down selection P7SYEVS2 P7SYEVS1 0 0 FLOAT2 Port 7 synchronous output event selection SCOLNG2 SCOLNG1 SCOCEO SCOCE1 SCODIR SCOLNGO 0 0 x x 0 0 0 SCOSTE SCOMDO Note x Initial value is unstable data Reception data input edge Transmission data output edge First bit to be transferred Synchronous serial data transfer start condition Special Function Registers List Synchronous serial transfer bit count XIII 15 Chapter 13 Appendices Address Register SCOMD1 SCOMD2 Bit Symbol Initial Value Description SCOSK
139. 2 for LCD clock and 41 Hz as frame frequency An example setup procedure with a description of each step is shown below Chapter 11 11 4 5 LCD Setup Procedure Description 6 Stop the LCD operation LCMD x3FCD bp7 LCDEN ll Setup of the LCD display duty LCMD x 3FCD bp5 4 LCDDTY1 0 01 Setup of the LCD clock LCMD x 3FCD bp3 0 0 0100 Setup of the segment output segment port pins LCCTR x 3FCC bp6 0 SEGSEL6 0 x 60 Setup of the display data Segment output latch x 76 Segment output latch X SFBE x 40 Segment output latch x 3FBF x27 SEG1 0 SEG3 2 SEG5 4 Start the LCD operation LCMD x 3FCD bp7 LCDEN 1 Set the LCDEN flag of the LCD mode control register LCMD to 0 to stop the LCD operation Set 1 3 as the display duty by LCODTY1 0 flags of the LCD mode control register LCMD Set fosc 2 5 as the LCD clock source by to 0 flags of the LCD mode control register LCMD Select SEGO 7 by SEGSEL6 0 flag of the output control register LCCTR Set 23 as the display data by the segment output latch SEGO to 5 x 3FBD to x 3FBF Chapter 11 11 4 5 LCD Display Examples 1 3 Duty Set the LCDEN flag of the LCD mode control register LCMD to 1 to start the LCD operation XI 24 LCD Function Operation Chapter 11 LCD Functions
140. 3FEF bp7 6 TM4LV1 0 10 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the TM4PWM flag of the TM4MD register to 0 to select the normal timer operation Set the P1DIR4 flag of the port 1 direction control register P1DIR to 0 to set P14 pin to input mode If it needs pull up resistor should be added Chapter 4 Ports Select the TM4IO input as a clock source by the TM4CK2 0 flag of the TM4MD register Set the interrupt generation cycle to the timer 4 compare register 4 The set value should be 4 because the counting is 5 times Set the interrupt level by the TM4LV1 0 flag of the timer 4 interrupt control register TM4ICR If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt Flag Setup 16 bit Event Count VI 15 Chapter 6 16 bit Timer Setup Procedure Description 7 Enable the interrupt 7 Set the flag of the TM4ICR register to TMAICR x 3FEF 1 to enable interrupt bp1 TMAIE 1 8 Start the event count 8 Set the TM4EN flag of the TM4MD register to x 3F84 1 to start timer 4 bp6 TMAEN 1 Every time TM4BC detects the falling edge of input TM4BC counts up from x0000 When reaches the setting value of theTM4OC register the timer 4 interrupt request flag is set at the next count clock then the value of TM4BC becomes x
141. 47 07 BEQ 47 BNE 47 d7 47 BLT d7 BLE 97 BEQ d4 BNE d4 MOVW DWn MOVW An HA 911 911 911 911 911 911 911 BLE 911 MOV Dn Dm MOV 8 Dm BSET abs8 bp BCLR abs8 bp CMP 8 Dm MOVW abs8 Am MOVW abs8 DWm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW An abs8 MOVW DWn abs8 CBNE 8 Dm d7 CMPW 16 Am MOVW An DWm d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 Am MOVW Extension code b 0010 2nd nible 3rd nibble 0 1 MOVW An Am MOVW An d4 SP CMPW An Am MOVW DWn d4 SP PUSH Dn 8 9 B MOVW MOVW ADDW 8 SP ADDW 4 SPI BTST 8 Dm JSRV 04 UMP 0 JSR A0 JMP 1 JSR MOV PSW Dm REP 3 BGT d7 d7 BLS d7 BNC d7 BNS 47 d7 BVS 47 NOT Dn ROR Dn BGT d11 BHI d1 BLS 411 BNC d11 BNS 411 911 011 ASR Dn LSR Dn SUBW DWn DWm SUBW 16 DWm SUBW 16 Am SUBW DWn Am MOVW DWn Am ADDW DWn DWm ADDW 16 DWm ADDW 16 Am ADDW DWn Am CMPW DWn Am MOV d16 SP Dm MOV d8 SP Dm MOV d16 An Dm MOV Dn d16 SP MOV Dn d8 SP MOV Dn d16 Am MOVW DWn DWm NOPL n m CMPW DWn DWm ADDUW Dn Am
142. 5 9000 Fax 55 12 331 3789 EUROPE OG Europe Sales Office Panasonic Industrial Europe GmbH PIE U K Sales Office Willoughby Road Bracknell Berks RG12 8FP THE UNITED KINGDOM Tel 44 1344 85 3671 44 1344 85 3853 Germany Sales Office Hans Pinsel Strasse 2 85540 Haar GERMANY Tel 49 89 46159 119 49 89 46159 195 ASIA e Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 THE REPUBLIC OF SINGAPORE Tel 65 6390 3688 Fax 65 6390 3689 e Malaysia Sales Office Panasonic Industrial Company M Sdn Bhd Head Office Tingkat 16B Menara PKNS Petaling Jaya No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan MALAYSIA Tel 60 3 7951 6601 Fax 60 3 7954 5968 Fax 52 3 671 1256 Matsushita Electric Industrial Co Ltd 2002 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang MALAYSIA Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 Oe Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st FI Rachadaphisek Rd Huaykwang Bangkok 10320 THAILAND Tel 66 2 693 3428 Fax 66 2 693 3422 Philippines Sales Office PISP Panasonic Indsutrial Sales Philippines Division o
143. 6 2 Setup Example sic 23 8 bit Timer Synchronous Output 25 5 7 1 Operation e tee 25 5 7 2 Setup Example Roue dete ee ea 26 Serial Interface Transfer Clock 28 5 8 1 Operation ne pee 28 5 8 2 Setup V 29 Cascade Connection 30 5 9 1 Operation te pear te Ded V 30 5 9 2 SETUP Example 2e E PU RE UI E EEOSE 32 Remote Control Carrier Output V 34 3 10 Operation snuron Ie egere pede habe ees V 34 5 10 2 Setup Example m tee tt hee 35 Chapter 6 16 bit Timer 6 1 VI 2 6 1 1 22 nete e p E RUN oq Ue Rer VI 2 6 1 2 Block Diagram eie ne petite teretes VI 3 Control Registers estensione eie ee tenere VI 4 6 2 1 noie eR RU qe eee d ipe e VI 4 6 2 2 Programmable Timer Registers VI 5 6 2 3 Registers VI 7 contents vi 6 4 6 5 6 6 16 bit Timer COME ep coe VI 8 6 3 1 nbn eet tet psi VI 8 6 3 2 Setup Example aed sities tei VI 11 16 bit Event Count ia eere lod Te ER e p EH m VI 13 6 4 1 Operation re VI 13 6 4 2 Setup Example nuevo UR EEE E IMS 15 16 bit Timer Pulse
144. 6 Hz 1x11 01 1 3 duty ICE 21Hz X129 10 1 2 duty 32 Hz 11 static 64 Hz LCD Control Registers XI 7 Chapter 11 LCD Functions 11 2 3 Segment Output Control Register LCCTR The segment output control register LCCTR is readable writable register that controls the selection between port output P5 P6 P7 P8 and segment output SEGO to SEG24 At reset LCCTR is set to the input port values If SEGSELO to SEGSEL7 of LCCTR is set 1 appropriate pins are all invalid At this time the data of the appropriate port is read it returns 0 Segment Output Control Register LCCTR 7 6 5 4 3 2 1 0 LCCTR SEGSEL6SEGSEL5 SEGSEL4 SEGSEL3 SEGSEL2 SEGSEL1 SEGSELO at reset 00000000 SEGSELO SEG24 Port 53 select 0 Port 53 1 SEG24 SEG20 to 23 Port 60 to 63 SEGSEL1 elect 0 Port 60 to 63 1 SEG20 to 23 SEG16 to 19 Port 64 to 67 SEGSEL2 0 Port 64 to 67 1 SEG16 to 19 SEG12 to 15 Port 70 to 73 SEGSEL3 select 0 Port 70 to 73 1 SEG12 to 15 SEG8 to 11 Port 74 to 77 SEGSEL4 select 0 Port 74 to 77 1 SEG8 to 11 SEG4 to 7 Port 84 to 87 SEGSEL5 select 0 Port 84 to 87 1 SEG4 to 7 SEGO to 3 Port 80 to 83 SEGSEL6 select 0 Port 80 to 83 1 SEGO to Figure 11 2 2 LCD Output Control Register LCCTR x 3FCC R W
145. 7 input register P7IN To output data to pin set the control flag of the port 7 direction control register P7DIR to 1 and write the value of the port 7 output register P7OUT Each pin can be set individually if pull up pull down resistor is added or not by the port 7 pull up pull down resistor control register P7PLUD But pull up pull down cannot be mixed Set the control flag of the port 7 pull up pull down resistor control register P7PLUD to 1 to add pull up or pull down resistor The pin control register 1 FLOAT1 select if pull up resistor or pull down resistor is added The bpO of the pin control register 1 FLOAT1 is set to 1 for pull down resistor set to 0 for pull up resistor At reset the P70 to P77 input mode is selected and pull up resistors are disabled high impedance output Special Function Pin Setup The synchronous output control register SYSMD selects the synchronous output pin of the port 7 in each bit When the SYSMD is 1 it can be used for synchronous output and when it is 0 it can be used for general port The synchronous output event is selected by the pin control register 2 FLOAT2 When the bp1 bpO of the FLOAT2 are 00 the external interrupt 2 IRQ2 is selected and 01 for the timer 4 interrupt and 10 for the timer 2 interrupt Chapter 4 4 10 Synchronous output p IV 43 P70 to P77 are used as LCD driving pins segment output as well The bp3 and 4 of the segmen
146. 8 bit displacement Specifies the address using the stack pointer with 16 bit displacement Specifies the address using the operand value appended to the instruction code Optimum operand length can be used to specify the address Specifies an 8 bit offset from the address x 00000 Specifies an 8 bit offset from the top address x 03F00 of the special function register area Reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combined use with absolute addressing reduces code size 1 H half byte bit II 11 Overview Chapter 2 CPU Basics 2 2 Memory Space 2 2 1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable writable data In addition to these peripheral resources such as memory mapped special registers are allocated The MN101C series supports three memory modes single chip mode memory expansion mode processor mode in its memory model Setting of each mode is different In single chip mode the system consists of only internal memory In memory expansion mode and processor mode ROM RAM and external device for operation can be connected Settings for each modes are as follows Table 2 2 1 Memory Mode Setup EXMEM flag in EXADVS to 1 flag in Memory mode MMOD pin MEMCTR register EXADV register Single chip mode L 0 expansion L 1 0 1 mode MMOD pin should be fixed to L lev
147. 86 2 2757 1906 Kaohsiung Office 6th Floor Hsin Kong Bldg No 251 Chi Hsien 1st Road Kaohsiung 800 TAIWAN Tel 886 7 346 3815 886 7 236 8362 e Korea Sales Office Panasonic Industrial Korea Co Ltd PIKL Kukje Center Bldg 11th Fl 191 Hangangro 2ga Youngsan ku Seoul 140 702 KOREA Tel 82 2 795 9600 Fax 82 2 795 1542 050402 Printed in JAPAN
148. 8IN3 28 PODIR6 0 PODIR2 PODIR1 PODIRO xS3F30 Port 0 VO direction control P1DIR4 P1DIR3 P1DIR2 P1DIRO 0 0 0 0 X3F31 Port 1 VO direction control n Pon TS direction control P5DIR4 P5DIR2 P5DIR1 P5DIRO 5 Port 5 VO direction control P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIRO 0 0 0 0 0 0 0 0 x3F36 Port 6 VO direction control P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIRO X 3F37 Port 7 VO direction control P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIRO 0 0 0 0 0 0 0 0 x3F38 Port 8 VO direction control Note x Initial value is unstable No data XIII 14 Special Function Registers List Chapter 13 Appendices Bit Symbol Initial Value Description P14TCO P13TCO P12TCO P10TCO 0 VO port Special VO port Special function pin control function pin control PAIMD7 PAIMD6 5 4 PAIMD2 PAIMD1 PAIMDO 0 0 0 0 0 0 0 PAIMD VO port Special function pin contro IRQ4SEL P4KYEN4 P4KYEN3 P4KYEN2 P4KYEN1 0 0 0 0 0 P4IMD interrupt 6 PA7 key 4 key PA2 key PA1 key source selection interrupt selection interrupt selection interrupt selection interrupt selection POPLU6 0 0 0 0 POPLU Port 0 pull up resistor ON Port 0 pull up resistor ON OFF OFF P
149. 99 63 because 1 MHz is divided by 10 kHz At that time the timer 2 binary counter TM2BO is initialized to 00 Set the TM2EN flag of the TM2MD register to 1 to start timer 2 TM2BC counts up from 00 If any data is written to the port 7 output register P7OUT the data of port 7 is output from the synchronous output pin in every time an interrupt request is generated by the match of TM2BC and the set value of the 2 register When the port 7 synchronous output is disabled the value of the synchronous output value storage register is not always same to the value of the port 7 output register P7OUT Therefore the pin output may be changed at the switching from the general output to the synchronous output 8 bit Synchronous Output 27 Chapter 5 8 bit Timers 5 8 Serial Interface Transfer Clock Output 5 8 1 Operation Serial interface transfer clock can be created by using the timer output signal Serial Interface Transfer Clock Operation by 8 bit Timer Timer 3 Timer 3 output can be used as a transfer clock source for serial interface 0 and serial interface 1 Table 5 8 1 Timer for Serial Interface Transfer Clock Serial transfer clock Timer 3 Serial interface 0 Timing of Serial Interface Transfer Clock Timer IE d WEN age register counter Interrupt request flag Timer output Serial transf
150. A ee ie Des 2 8 1 1 Block Diagr m eaae om VIII 2 Control Regist ts 3 Operation E m eti ote Wa eene eo diee eie eed 4 8 3 1 Operation 4 8 3 2 Setup Example Pes 7 Chapter9 Buzzer 9 1 9 2 9 3 OVerVIe Ws co te eT etse Seah Bae IX 2 9 1 1 Block th ne e pte es IX 2 Control Register e bo oia e ei tree uas IX 3 Operation 2c et ost teda e ea e he ee e i teet ae ens IX 4 9 3 1 OPS atl mys sea 4 9 3 2 setup Example ep eI e TRE 5 Chapter 10 Serial Interface 0 10 3 au X 2 10 1 1 Functions 15 ien Rer epe tpe eret X 2 10 122 Block Diagram ensi ehe et etes X 3 Control Registers uon tee Rite Re eO e EO OU e eere tans X 4 10 2 R gisters use RU te USES X 4 10 2 2 Data Buffer Registers X 5 10 2 3 Mode Registers Control registers sese X 6 Operation sci eite eter ae et a o e eet test Rede X 11 10 31 Clock Synchronous Serial Interface X 11 10 3 2 Setup Example eee tete ded eene Ree X 26 10 3 3 Half duplex UART Serial Interface X 29 103 4 Setup eer tege X 42 Chapter 11 LCD Functions 11 1 11 2 11 3 11 4 QV ELVIS
151. BUZCKO DLYS1 DLYSO At reset 0xx 00 Oscillation stabilization wait period selection DLYS1 DLYSO 0 o 15 24 1 fs 210 o 1 5 28 1 1 Do not set Note After reset is released the oscillation stabilization wait period is fixed at 15 214 Buzzer output BUZCK1 BUZCKO frequency selection 0 fs 212 0 1 16 211 i 0 fs 21 1 fs 29 BUZOE P06 output selection 0 port data output 1 buzzer output Figure 9 2 1 Oscillation Stabilization Wait Timer Control Register DLYCTR 03 03 R W Control Register IX 3 Chapter 9 Buzzer 9 3 Operation 9 3 1 Operation mBuzzer Buzzer outputs the square wave having a frequency 1 2 to 1 2 2 of the system clock fs The BUZCK 1 0 flag of the oscillation stabilization wait control register DLYCTR set the frequency of buzzer output The BUZOE flag of the oscillation stabilization wait control register DLYCTR sets buzzer output ON OFF mBuzzer Output Frequency The frequency of buzzer output is decided by the frequency of the system clock fs and the bit 6 5 BUZCK1 BUZCKO of the oscillation stabilization wait control register DLYCTR Table 9 3 1 shows the buzzer output frequency Table 9 3 1 Buzzer Output Frequency fosc fs BUZCK1 BUZCKO Buzzer output frequency 0 0 2 44 kHz 20 MHz 10 MHz
152. Clock Timer Clock Type OSC1 Input XI Input External Clock Crystal Ceramic Frequency MHz kHz Unused 5 System operation clock OSC1 only OSC1 and XI 1 This check list is subjected to change Please request the most recent check list from the sales office when doing ROM release Option of this product is used a part of the built in ROM Please set data on the address of the option when doing ROM release Option I 31 Chapter 1 Overview 1 7 Package Dimension Package Code TQFP064 P 1010B 12 00 20 20 Units mm 10 00 0 10 10 00 010 12 00 0 20 TM SEATING PLANE Sealing material EPOXY resin Lead material FeNi Lead surface processing lt SnBi plate 0 50 0 10 Figure 1 7 1 64 TQFP The package dimension is subjected to change Before using this product please obtain product specifications from the sales office 1 32 Package Dimension Chapter 1 Overview Package Code LQFP064 P 1414 Units mm 16 00 030 14 00 20 10 16 00 0 20 1 00 140 0 10 SEATING PLANE 0 15 20 03 Sealing material EPOXY resin Lead material Alloy of Cu Lead surface processing Pd plate Figure 1 7 2 64 LQFP The package dimension is subjected to change Befo
153. Current interrupt mask level IM PSW Mie ZF Level judgement Accepted if IL lt IM 7 xxxICR xxxIR A Generated interrupt level IL Figure 3 1 4 Determination of Interrupt Acceptance accepted When the setting is xxxLV1 1 xxxLV0 1 the interrupt is disabled regardless of the value of XXXIE a The corresponding interrupt enable flag is not cleared to 0 even if the interrupt is LI Ill 8 Overview Chapter 3 0 and interrupts are disabled when MIE in the PSW is reset to 0 by a program Reset is detected MIE 1 and interrupts are enabled when MIE in the PSW is set 1 by a program The interrupt mask level IM IM1 IMO in the processor status word PSW changes when The program alters it directly A reset initializes it to 0 00b The hardware accepts and thus switches to the interrupt level IL for a maskable interrupt Interrupts Execution of the RTI instruction at the end of an interrupt service routine restores the processor status word PSW and thus the previous interrupt mask level 1 maskable interrupt enable MIE flag in the processor status word PSW is cleared to 0 when interrupt is accepted Non maskable interrupts have priority over maskable ones Overview 9 Chapter 3 Int
154. D x 3F1F bp7 0 SYSMD7 0 xFF Set the synchronous output data P7OUT x 3F17 bp7 0 PDOUT7 0 Event is generated Rising edge is generated at P22 Set the P7SYEVS1 0 flag of the FLOAT2 register to 00 to set the synchronous output event to the IRQ2 Set the REDG2 flag of the IRQ2ICR register to 1 to set the active edge of the IRQ2 at the rising edge Set the initial output data 55 to the P7OUT register Select output mode after the P7DIR7 0 flag of the P7DIR register is set to Port 7 outputs 55 Port 7 is set to synchronous output pin by setting the SYSMD7 0 flag of the SYSMD register to FF Set the synchronous output data AA to the P7OUT register Port 7 outputs AA at the rising edge of IRQ2 Synchronous Output Port 7 IV 47 Chapter 5 8 bit Timers Chapter 5 8 bit Timers 5 1 Overview This LSI contains 1 general purpose 8 bit timer Timers 2 and 1 8 bit timer Timers 3 that can be also used as baud rate timer Timers timers 2 and 3 can be used as 16 bit timers with cascade connection 5 1 1 Functions Table 5 1 1 shows functions of each timer Table 5 1 1 Timer Functions Timer 2 Timer 3 Timer 5 8 bit 8 bit 8 bit Interrupt source TM2IRQ TMSIRQ Timer operation y 4 Event count 4 4 Timer pulse output PWM output y Synchronous output Serial transfer clock output pean Cascade
155. EL4 SEGSEL3 secs eos SEGSELO Atreset 0000000 IV 32 Port7 NE SEG24 SEGSELO Port P53 selection 0 Port P53 1 SEG24 SEG20 to 23 SEGSEL1 Port P60 to P63 selection 0 Port P60 to P63 1 SEG20 to 23 SEG16 to 19 SEGSEL2 Port P64 to P67 selection 0 Port P64 to P67 1 SEG16 to 19 SEG12 to 15 SEGSEL3 Port P70 to P73 selection 0 Port P70 to P73 1 SEG12 to 15 8 to 11 SEGSEL4 Port P74 to P77 selection 0 Port P74 to P77 1 SEG8 to 11 SEG4 to 7 SEGSELS port P84 to P87 selection 0 Port P84 to P67 1 SEG4 to 7 SEGO to 3 SEGSEL6 Port P80 to P83 selection 0 Port P80 to P83 1 SEGO to 3 Segment output control register LCCTR R W Figure 4 7 4 Port 7 Registers 4 4 Chapter 4 Ports 4 7 3 Block Diagram Expansion control Address output Ps P7PLUDO 7 Pull up Pull down resistor control t D ER Write A Read Reset FLOAT1 Pull up Pull down resistor selection DQ gt Write AZ Read M Reset gt U direction control 4 S L 107DX P70 P77 1 o JU Port output data X 7 7
156. GSEL3 Port P70 to P73 selection 0 Port P70 to P73 SEG12 to 15 8 to 11 SEGSEL4 P74 to P77 selection 0 Port P74 to P77 8 to 11 SEG4 to 7 SEGSELS Port P84 to P87 selection 0 Port P84 to P67 1 SEGA to 7 SEGO to 3 SEGSEL6 Port P80 to P83 selection 0 Port P80 to P83 1 SEGO to 3 Segment output control register LCCTR R W Figure 4 8 2 Port 8 Registers 2 2 Chapter 4 Ports 4 8 3 Block Diagram Rese P8PLUO 7 Pull up resistor control 8 Uo gt gt Write Read m P8DIRO 7 0 direction control U Write NUL Read S P80 P87 Rese 777 Y w R Port output data 5 P8OUTO 7 0 M Write A Read U X 7 7 P8INO 7 i C 1 Port input data p Read Segment output control signal Data input Data output Expansion control Segment output control VDD VLC1 gt 21 2 Segment output VLC2 Pii VLC3 In memory expansion mode output mode is always selected When segment output is selected segment output contro automatically sets port I O direction control to input mode and segm
157. HO flag of the A D converter control register 0 ANCTRO to 01 Set the interrupt level by the ADLV1 0 flag of the A D conversion complete interrupt control register ADICR If any interrupt request flag had already been set clear it Chapter 3 3 1 4 Interrupt Flag Setting Enable the interrupt by setting the ADIE flag of the ADICR register to 1 Set the ANLADE flag of the A D converter control register 0 ANCTRO to 1 to senda current to the ladder resistance for the A D conversion 12 Operation Chapter 12 A D Converter Setup Procedure Description 8 Start the A D conversion 8 Set the ANST flag of the A D converter control x 3F91 register 1 ANCTR1 to 1 to start the A D bp7 ANST 1 conversion 9 Complete the A D conversion 9 When the A D conversion has finished the A D ANBUFO x 3F92 converter complete interrupt is generated ANBUF1 x 3F93 and the ANST flag of the A D converter control register 1 ANCTR1 is cleared to 0 The result of the conversion is stored to the A D converter buffer ANBUFO 1 Note The above 2 to 4 can be set at once Start the A D converter after the current flowing through the ladder resistors stabilizes The wait time should be decided by the calculated time from the ladder resistance max 80 kQ and the external bypass capacitor connected between Vrer and Operation XH 13 Chapte
158. Hz An example setup procedure with a description of each step is shown below Base period set by timer 0 36 7 kHz lt gt Base period set by timer 3 RMOUT output 1 3 duty Figure 5 10 3 Output Wave Form of RMOUT Output Pin Setup Procedure Description 1 Disable the remote control carrier output RMCTR x 3F89 bp3 0 2 Select the carrier output duty RMCTR x 3F89 bp1 RMDTYO 1 3 Stop the counter x 3F83 bp4 0 4 Set the remote control carrier output of the special function pin P1OUT x 3F11 bpO P1OUTO 0 P1OMD x 3F39 bpO P1OTCO 1 P1DIR x 3F31 bpO P4DIRO 21 5 Select the normal timer operation x 3F83 bp3 TM3PWM 0 1 Set the RMOEN flag of the remote control carrier output control register RMCTR to 0 to disable the remote control carrier output Set the flag of the RMCTR register to 1 to select 1 3 duty Set the TM3EN flag of the timer mode register TM3MD to 0 to stop the timer counting Set the P1OUTO flag of the port 1 output register P1OUT to 0 to set the output data of P10 pin to O Set the P1OTCO flag of the port 1 output mode register P1OMD to 1 to set P10 pin asa special function pin Set the P1DIRO flag of the port 1 direction control register P1DIR to 1 for output mode Set the TM3PWM flag of the TM3MD register to 0 to select no
159. IV 6 4 2 1 Description serep e aae ee Aa anil IV 6 4 2 2 N 7 4 2 3 Block Diagram etta bte ten ee IV 8 Port IV 10 4 3 1 Description RR HR Ub eee IV 10 4 3 2 Registers a et EO ae et EO URS IV 11 4 3 3 Block Di gram IV 13 IV 14 4 4 1 niente eph e e reap 14 4 4 2 Dioni P ecient Arte Abe IV 15 4 4 3 Block Diagram ene eet ret e pete IV 16 POTT S isis Rp HERD t DO e PIRE RR ROSA IV 17 4 5 1 ter emet IV 17 4 5 2 ene om E ee E ee IV 18 4 5 3 Block Di gram eene e IV 21 Port 23 4 6 1 Description ssi oe eile a ee ae a a te IV 23 4 6 2 R egISIeIS oot PI ERE IV 24 4 6 3 Block nebenbei eoo eed IV 26 Port T onc aula RI eie diee eiae Sha teta IV 27 4 7 1 eR eet IV 27 4 7 2 TO gasses IV 29 4 7 3 Block Di gram ege IV 33 doves ts IV 34 4 8 1 Description 34 4 8 2 I ete 35 4 8 3 Block Diagram nee apr IV 37 POIA A IV 38 4 9 1 D Sscrption aie eo eee ente ptit IV 38 4 9
160. Interface Block Diagram PAO KEYO PA1 KEY1 2 2 x X M PA4 KEY4 IRQ4 interrupt request 5 6 6 PA7 KEY7 4 X 0 ES eet LIRG4SEL Figure 3 3 3 External Interrupt 4 Interface Block Diagram 32 External Interrupts Chapter 3 Interrupts 3 3 3 Control Registers The external interrupt input signals which operated in each external interrupt 0 to 2 and 4 interface generate interrupt requests External interrupt 0 to 2 and 4 interface are controlled by the external interrupt control register IRQnICR And external interrupt interface 0 to 1 are controlled by the noise filter control register NFCTR and external interrupt interface 4 is controlled by the port 4 key interrupt control register P4IMD When the external interrupt 1 is used for AC zero cross detection it is controlled by the pin control register 1 FLOAT1 Table 3 3 2 shows the list of registers control external interrupt 0 to 2 and 4 Table 3 3 2 External Interrupt Control Register External Interrupt Register Address R W Function Page IRQOICR x O3FE2 R W External interrupt O control register lll 17 External interrupt 0 NFCTR X 03F8A R W Noise filter control register Ill 33 IRQ1ICR x OSFE3 R W External interrupt 1 control register 18 External interrupt 1 NFCTR R W Noise filter control register 35
161. LSI User s Manual Describes the device hardware MNIOIC Series Instruction Manual Describes the instruction set MNI01C Series Cross assembler User s Manual Describes the assembler syntax and notation MNI0IC Series C Compiler User s Manual Usage Guide Describes the installation the commands and options of the C Compiler MNIOIC Series C Compiler User s Manual Language Description Describes the syntax of the C Compiler MNIOIC Series C Compiler User s Manual Library Reference Describes the standard library of the C Compiler MNIOIC Series C Source Code Debugger User s Manual Describes the use of C source code debugger gt MNI0IC Series PanaX Series Installation Manual Describes the installation of C compiler cross assembler and C source code debugger and the procedure for bringing up the in circuit emulator Chapter 1 Overview Chapter 2 CPU Basics Chapter 3 Interrupts Chapter 4 Ports Chapter 5 8 bit Timers Chapter 6 16 bit Timer Chapter 7 Time Base Timer 8 bit Free running Timer Chapter 8 Watchdog Timer Chapter 9 Buzzer Chapter 10 Serial Interface 0 Chapter 11 LCD Functions Chapter 12 A D Conversion Functions N Chapter 13 Appendices 13 ii Contents Chapter 1 Overview 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 OVERVIEW Aus sei dere ance recs lea Des acest ae te 1 2 1 1 1 QUEL VIEW
162. M x SCOCK1 SCOCKO SCOBRKF 0 SCOERE 0 SCOTRI 0 1 8 dividing of transfer clock SCOFM1 Br source mE receive monitor SCOFMO SCOPM1 Error monitor SCOPMO Transmission Reception interrupt request flag SCONPE Brake status transmit control 0 Frame mode specification 0 x x Added bit specification x Parity enable SCOMD3 SCOCTR SCOIOM 0 SCOSBOM 0 SCOSBTM SCOSBOS 0 0 SCOSBIS 0 SCOSBTS 0 SCOBSY SBOO pin connection SCOCMD SBOO pin configuration SBTO pin configuration SBOO pin function SCOFEF SCOPEK SBIO input control SCOORE SBTO pin function 0 Serial bus status 0 Clock synchronous UART 0 0 Framing error detection Parity error detection 0 Overrun error detection SCOTRB SCORXB SCOTRB7 SCOTRB6 SCOTRB3 SCOTRB2 SCOTRB1 SCOTRBO SCORXB7 SCORXB6 ft register SCORXB2 SCORXB1 SCORXBO x x x x x TM2BC7 TM2BC6 TM2BC2 TM2BC1 TM2BCO TM3BC7 TM3BC6 TM3BC2 TM3BC1 TM3BCO 0 0 0 TM4BCL TM4BCH TM4BCL7 TM4BCL6 TM4BCL2 TM4BCL1 TM4BCLO TM4BCH7 TM4BCH6 TM4BCH2 TM4BCH1 TM4BCHO 0 0 0 0 0 TM4ICL TM4ICL7 TM4ICL6 TMAICL3 TM4ICL2 TM4ICL1 TM4ICLO TM4ICH7 TM4ICH6 register lower 8 bits TM4ICH3 TM4ICH2 TM4ICH1 TM4ICHO
163. M3BC TM3BC7 TM3BC6 TM3BC5 Tsece TM3BC2 TM3BC1 TM3BC0 Atreset 00000000 Figure 5 2 4 Timer 3 Binary Counter TM3BC 03 63 R 6 Control Registers Chapter 5 8 bit Timers 5 2 3 Timer Mode Registers Timer mode register is readable writable register that controls timers 2 and 3 E Timer 2 Mode Register TM2MD 7 6 5 4 3 2 1 0 TM2MD T TM2CK2 TM2CK1 TM2CKO Atreset 00XXX TM2CK2 TM2CK1 TM2CK0 Clock source 0 0 fs 1 fs 4 0 fx 0 1 1 TM2IO input 0 Synchronous fx 1 Synchronous TM2IOinput Timer 2 operation mode selection 0 Normal timer operation 1 PWM operation TM2EN Timer 2 count control 0 Disable the count 1 Enable the count Figure 5 2 5 Timer 2 Mode Register TM2MD x 03F82 R W Control Registers 7 Chapter 5 8 bit Timers E Timer Mode Register TM3MD TM3MD 8 3 2 1 0 TM3PWMITM3CK2 TM3CK1 TM3CKO At reset 00XXX TM3CK2 TM3CK1 Clock source fosc 15 4 15 16 input 2 cascade connection Synchronous input TM3PWM P13 output selection at TM2PWM operation Timer 3 output Timer 2 PWM out
164. M5MD to 0 At that time the initialization of the timer 5 binary counter TM5BC is enabled Clock source can be selected by the 5 1 flag of the TM5MD register Actually fs 4 is selected Set the interrupt generation cycle to the timer 5 compare register 5 At that timer is initialized to 00 Set the TM5CLRS flag of the TM5MD register to 1 to enable the interrupt request generation Set the interrupt level by the TM5LV1 0 flag of the timer 5 interrupt control register TM5ICR If any interrupt request flag had already been set clear it Chapter 3 3 1 4 Interrupt Flag Setup Set the flag of the TM5ICR register to 1 to enable the interrupt the above steps 1 2 can be set at once As is set TM5BC is initialized to 00 to count up When TM5BC matches 5 the timer 5 interrupt request flag is set at the next count clock and TM5BC is cleared to 00 to restart counting 10 8 bit Free running Timer Chapter 7 Time Base Timer 8 bit Free running Timer If the interrupt is enabled the timer 5 interrupt request flag should be cleared before timer 5 operation is started If the TM5CLRS flag of the TM5MD register is set to 0 TM5BC can be initialized in every rewriting of TM5OC register but in that state the timer 5 interrupt is disabled If the timer 5 interrupt should be enabled set the TM5CLRS flag to 1 a
165. MSB bit SCORXB A B D E F Data is read F E D Figure 10 3 2 2 Receive Bit Count and Transfer First Bit starting with LSB bit iinput Edge Output Edge Setup The SCOCE 1 to 0 flag of the SCOMDO register set an output edge of the transmission data an input edge of the reception data As the SCOCE1 flag 0 the transmission data is output at the falling edge and as 1 output at the rising edge As SCOCEO 0 the reception data is stored at the inversion edge to the output edge of transmission data and as 1 stored at the same edge Table 10 3 2 Input Edge and Output Edge of Transmission Reception Data SCOCEO SCOCE1 Reception data input edge Transmission data output edge 0 0 1 M 0 1 y 1 1 0 y y 1 1 4 1 16 Operation Chapter 10 Serial Interface 0 Setup The clock source can be selected from the internal clock or the external clock Here is the internal clock source that can be set by the SCOCK1 to 0 register of the SCOMD1 register Also the internal clock can be divided by 8 by setting the SCOCKM flag of the SCOMD 1 register to 1 Table 10 3 3 Synchronous Serial Interface Internal Clock Source Serial interface 0 fs 2 Clock source 15 4 internal clock fs 16 Timer 3 output Data Input Pin Setup 3 channels type clock pin SBTO pin data output pin
166. NDK BUZZER SEG20 A3 P63 gt SEG19 A4 P64 gt Port6 SEG18 A5 P65 6 SEG17A6 P66 SEG16 A7 P67 P10 RMOUT SEG15 SDO0 A8 P70 P12 TM2IO SEG14 SD01 A9 P71 Port1 SEG13SD02 A10 P72 gt 4 0 P14 TM4IO SEG12 SDOS A11 P73 SEG11 SDO4 A12 P74 gt gt Port7 SEG10 SD05 A13 P75 6 SEG9 SDO6 A14 P76 SEG8 SDO7 A15 P77 201 P21 IRQ1 SENS Port2 gt P22 IRQ2 SEGO D0 P80 P27 NRST SEG1 D1 P81 SEG2 D2 P82 gt SEG3 D3 P83 SEG4 D4 P84 gt Port8 SEG5 D5 P85 gt SEG6 D6 P86 SEG7 D7 P87 lt P50 NWE LEDO KEYO ANO PAO P51 NRE LED1 KEY1 AN1 PA1 Port5 P52 NCS LED2 KEY2 AN2 PA2 4 0 P53 A16 LED3 SEG24 KEYS ANS PA3 gt PortA KEY4 AN4 PA4 KEY5 AN5 PA5 KEY6 AN6 PA6 KEY7 AN7 PA7 Figure 4 1 1 Port Functions IV 2 Overview Chapter 4 Ports 4 1 2 Port Status at Reset Table 4 1 1 Port Status at Reset Single chip mode Port Name VO mode Pull up Pull down resistor VO port special functions Port 0 Input mode No pull up resistor VO port Port 1 Input mode No pull up resistor VO port Port 2 Input m
167. NORMAL eee II 25 2 4 4 Transition to STANDBY Modes esee II 27 Reset ERR n EUREN E E I IRE II 29 2 5 1 Reset Operation gei patere eie II 29 2 5 2 Oscillation Stabilization Wait Time sese II 31 Chapter3 Interrupts 3 1 3 3 2 3 1 1 eed 3 3 1 2 Block Did Sram ec eub eH DO qu noi de IP III 4 3 1 3 Operation donee bete 5 3 1 4 Interrupt Flag Setup III 14 Control Registers eoo e ete eet Gert ned E III 15 3 2 1 Registers List eripere 15 3 2 2 Interrupt Control Registers 16 External Interrupts III 28 3 3 1 OVELVIEW tee ren poit rp bees III 28 3 3 2 Block Dia eran co cc 4 en ete ee des III 29 3 3 3 Control Registers nennt ere deperit 32 3 3 4 Programmable Active Edge Interrupt III 36 3 3 5 Key Input Interrupt eee III 37 3 3 6 Noise FIET eee torikoa entrons eso epa pano d tee III 39 3 3 7 AC Zero cross Detector III 42 11 contents iv Chapter 4 contents 4 1 4 2 4 3 4 4 4 5 4 7 4 8 4 9 4 10 I O Ports OVERVIEW Dco e reti RU b bn ebd us IV 2 4 1 1 W O Port Diagram tr ee tee IV 2 4 1 2 I O Port Status at Reset IV 3 4 1 3 Control 4
168. P PC 7 bp15 8 mem8 SP 1 PC 7 H gt mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 7 bp17 16 mem8 SP 2 bp1 0 abs 18 label H PC 0011 1001 1 lt abs 18b 15 0 5 JSRV 4 SP 3 SP PC 3 bp7 0 mem8 SP PC 3 bp15 8 mem8 SP 1 3 8 5 2 7 0 8 2 6 2 3 6 17 16 8 2 6 1 0 mem6 x 004080 bl4 2 S PC bp7 0 8 004080 04 lt lt 2 1 0 15 8 mem8 x 004080 tbl4 lt lt 2 2 bp7 gt PC H mem8 x 004080 tbl4 lt lt 2 2 bp1 0 gt PC bpt7 16 1111 1110 lt t4 gt NOP XIII 24 NOP 2 gt Instruction Set 0000 0000 1 2 3 4 d7 sign extension d11 sign extension d12 sign extension d16 sign extension aa abs18 17 16 Chapter 13 Appendices MN101C SERIES INSTRUCTION SET Mnemonic Operation 5 6 7 RTS RTS mem8 SP gt PC bp7 0 2 7 0000 0001 mem8 SP 1 PC bp15 8 mem8 SP 2 bp7 PC H mem8 SP 2 bp1 0 PC bp17 16 SP 3 SP RTI RTI mem8 SP PSW 2 11 0000 0011 8 1 6 7 0 mem8 SP 2 PC bp15 8 8 3 6 7 mem8 SP 3 bp1 0 gt PC bp17 16 8 5 4 8 5 gt SP 6 SP Contorl instructions REP REP imm3 imm3 1 RPC 3 2 0010 0001 1rep 1
169. P NOP instructions three or less are NOP executed Program 5 MOV x 7 DO Set HALT1 mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Transition to STOP mode The system transfers from NORMAL mode to STOPO mode and from SLOW mode to STOP1 mode In both cases oscillation and the CPU are both halted There are two ways to leave a STOP mode a reset or an interrupt Program 6 MOV x 8 DO Set STOPO mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Program 7 MOV x B DO Set STOP1 mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Right after the instruction of the transition to HALT STOP mode NOP instruction should be inserted 3 times II 28 Standby Functions Chapter 2 Basic CPU 2 5 Reset 2 5 1 Reset Operation The CPU contents are reset and registers are initialized when the NRST pin P27 is pulled to low Binitiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low NRST pin should be held low for more than OSC 4 clock cycles 200 ns at a 20 MHz NRST pin 4 clock cycles 200 ns at a 20 MHz Figure 2 5 1 Minimum Reset Pulse Width 2 Setting the P2OUT7 flag of the P2OUT register to 0 outputs low level at
170. Pin Setup 1 channel at reception Table 10 3 21 shows the pin setup at UART serial interface reception with 1 channel TXD pin The RXD pin can be used as general port P01 Table 10 3 21 UART Serial Interface Pin Setup 1 channel at reception Data output pin Serial unused pin Setup item TXD pin RXD pin Pin P01 TXD RXD pins connected TXD RXD pin SCOMD3 SCOIOM Port Serial data input Function SCOMD3 SCOSBOS SCOMDS SCOSBIS Style Input mode E VO PODIR PODIRO added not added Pull up POPLU POPLUO Operation X 41 Chapter 10 Serial Interface 0 10 3 4 Setup Example Transmission Setup The setup example at UART transmission with serial interface 0 is shown Table 10 3 22 shows the conditions at transmission Table 10 3 22 UART Interface Transmission Setup Setup item set to TXD RXD pin connected with 1 channel Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source timer 3 output TXD pin type Nch open drain Pull up resistor of TXD pin not added Parity bit add check O add check Serial interface 0 interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the UART communication SCOCTR x 3F54 bp6 SCOCMD 1 Select the first bit to be transferred
171. Push pull Style Nch open drain Nch open drain Nch open drain SCOMD3 SCOSBOM SCOMD3 SCOSBTM id Output mode Input mode Output mode Input mode PODIR PODIRO PODIR PODIR1 PODIR PODIR2 Pul up Added Not added Added Not added Added Not added Added Not added POPLU POPLU2 BPins Setup 2 channels at transmission Table 10 3 8 shows the setup for synchronous serial interface pin with 2 channels SBOO pin SBTO pin at transmission SBIO pin can be used as a general port Table 10 3 8 Setup for Synchronous Serial Interface Pin 2 channels at transmission Data VO pin Serial unused pin Clock VO pin Setup item SBT1 pin SBOO pin pin Internal clock External clock master communication slave communication Pin P02 SBIO SBOO connected SBIO SBOO pin SCOMDS SCOIOM Serial data output 1 input Serial clock VO Port Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull Push pull Stype Nch open drain 2 Nch open drain Nch open drain SCOMD3 SCOSBOM SCOMD3 SCOSBTM Output mode Output mode Input mode PODIR PODIRO PODIR PODIR2 bel Added Not added Added Not added Added Not added ull up POPLU POPLUO POPLU POPLU2 X 24 Operation Chapter 10 Serial Interface 0 WPins Setup 2 channels at reception Table 10 3 9 shows the setup for synchronous serial interface pin with 2 channels SBOO
172. Q2 interrupt request Note x Initial XIII 18 IRQ4ICR IRQ4LV1 RQ4LVO REDG4 0 0 IRQ4IR 0 IRQ4 interrupt TM3LV1 IRQ4 interrupt active edge IRQ4 interrupt enabl IRQ4 interrupt request value is unstable 0 interrupt level No data Special Function Registers List TNG interrupt enable TMS interrupt request TM4ICR Bit Symbol Initial Value Description Chapter 13 Appendices TM4LV1 TM4LVO Bit 4 Bit 3 0 0 interrupt level TM4 interrupt enable TM4 interrupt request Note TMSICR Initial value is unstable TMSLV1 TMSLVO TMSIE 0 TMSIR 0 TMS interrupt level No data TM6 interrupt enable TM6 interrupt request Special Function Registers List XIII 19 Chapter 13 Appendices 13 4 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag CodelCycle Re Machine Code Notes VF NF CF ZF Size peat Ex 1 2 3 4 5 6 7 8 9 10 11 Data Move Instructions MOV Dn Dm Dn5Dm 1010 DnDm MOV imm8 Dm 8 gt 1010 DmDm lt 8 MOV Dn PSW Dn PSW 1001 01Dn MOV PSW Dm PSW gt Dm 0001 01Dm MOV An Di 8 gt 0100 1ADm MOV d8 An Dm mem8 d8 An gt Dm 0110 1ADm MOV d16 An Dm MOV d4 SP Dm mem8 d16 An
173. Read enable signal Chip select signal Expansion control Chapter 4 Ports E PSPLUO 2 gt 7 Write Read E ET PSDIRO 2 Write FA Read 57 50 52 Rese g 5 PSOUTO 2 M Write Read y X 7 7 A 0 2 N Read output mode is always selected Figure 4 5 4 Block Diagram P50 to P52 Pot5 IV 21 Chapter 4 Ports xs Rese Pull up resistor control ae P5PLU3 gt J Write CK Read Reset l M P5DIR3 0 direction control s a U a LE Write 7 Read 1 X S Rese 777 Y w Port output data Dd P5OUTS3 0 M J gt Pa Write CK Z Read 1 U X 777 P5IN3 Port input data N Read Segment output control signal Segment output control VDD Address output Expansion control VLC1 t Lp v Y Segment output VLC2 VLC3 When segment output is selected segment output control automatically sets port I O direction control to input mode and segment output control is set to without pull
174. SCOMDO x 3F50 bp4 SCODIR 0 Select the start condition SCOMDO x 3F50 bp3 SCOSTE 0 Select the clock source SCOMD1 x 3F51 bp4 3 SCOCK1 0 11 Select the parity bit SCOMD2 x 3F52 SCONPE 0 bp2 1 SCOPM1 0 00 Set the SCOCMD flag of the SCOCTR register to 1 to select the UART communication Select MSB as first transfer bit by the SCODIR flag of the SCOMDO register Set the SCOSTE flag of the SCOMDO register to disable start condition e 33 Selection of Start Condition Set the SCOCK1 0 flag to select timer 3 output as a clock source Set the SCONPE flag of the SCOMD2 register to select parity is enabled and set the SCOPM1 0 flag to select 0 added X 42 Operation Chapter 10 Serial Interface 0 Setup Procedure Description 6 Specify the flame mode SCOMD2 x 3F52 bp4 3 SCOFM1 0 11 7 Control the output data SCOMD2 x 3F52 bp5 SCOBRKE 0 8 Control the pin type SCOMDS x 3F53 bp4 SCOSBOM 1 POPLU x 3F40 POPLUO 0 9 Select the reception mode SCOMD3 x 3F53 bp5 SCOIOM 1 10 Control the pin direction PODIR x 3F30 PODIRO 1 11 Select the interrupt level SCOICR x 3FE8 bp7 6 SCOLV1 0 10 12 Enable the interrupt SCOICR x 3FE8 bp1 SCOIE 1 13 Set the baud rate timer 14 Set the serial interface communication SCOMD3 x 3F53 bp2 SCOSBOS 1
175. Through register settings external interrupts 0 to 4 can generate interrupt at the selected edge either rising or falling edge lilProgrammable Active Edge Interrupt Setup Example External interrupts 0 to 2 External interrupt 1 IRQ1 is generated at the rising edge of the input signal from P21 The table below provides a setup example for IRQ1 Setup Procedure Description 1 Specify the interrupt active edge 1 Set the REDG 1 flag of the external interrupt 1 IRQ1ICR control register IRQ1ICR to 1 to specify the bp5 REDG1 1 rising edge as the active edge for interrupts 2 Setthe interrupt level 2 Setthe interrupt priority level in the IRQ1LV1 0 IRQ1ICR flag of the IRQ1ICR register bp7 6 IRQ1LV1 0 10 If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt flag setup 3 Enable the interrupt 3 Set the flag of the IRQ1ICR register to IRQ1ICR 1 to enable the interrupt bp1 IRQMIE 1 External interrupt 1 is generated at the rising edge of the input signal from P21 1 The Interrupt request flag may be set to 1 at switching the interrupt edge so specify the interrupt active edge before the interrupt permission If the interrupt request flag is set to 1 at the switching of the interrupt edge an interrupt is a generated by setting the interrupt enable flag Therefore you had better clear the
176. XB3 SCORXB2 SCORXB1 SCORXBO at reset X X XX XX XX Figure 10 2 2 Serial Interface 0 Reception Data Buffer SCORXB 03 56 Control Registers X 5 Chapter 10 Serial Interface 0 10 2 3 Mode Registers Control Registers Serial Interface 0 Mode Register 0 SCOMDO SCOMDO X 6 7 6 5 4 3 2 1 0 scaceo SCOCE1 scopi SCOSTE at reset 00XX000 SCOLNG2 SCOLNG1 SCOLNGO Synchronous serial transfer bit count 8 bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits Joj joj2jo j o 1 bit SCOSTE Synchronous serial data transfer start condition selection 0 Disable start condition Enable start c ondition SCODIR First bit to be transferred 0 MSB first LSB first Reception data issi SCOCEO SCOCE1 input edge bare gata 0 0 Rising Falling 1 Falling Rising 1 0 Falling Falling 1 Rising Rising Figure 10 2 3 Serial Interface 0 Mode Register 0 SCOMDO x 03F50 R W Control Registers Serial Interface 0 Mode Register 1 SCOMD1 The SCOTRI SCOERE and SCOBRKF flags are only readable SCOMD1 7 6 5 4 3 2 1 0 SCOCKM SCOCK1 SCOCKO SCOBRKF SCOERE SCOTRI Chapter 10 Serial Interface 0 at r
177. able interrupt Enable interrupt External interrupt active REDGO edge flag 0 Falling edge 1 Rising edge IRQO IRQO Interrupt level flag LV1 LVO for external interrupt The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 2 External Interrupt 0 Control Register IRQOICR x OSFE2 R W 18 Control Registers Chapter 3 Interrupts Interrupt 1 Control Register IRQ1ICR The external interrupt 1 control register IRQ1ICR controls interrupt level of external interrupt 1 active edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is set to level 3 IRQ1LV1 IRQ1LVO0 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag 7 6 5 4 3 2 1 0 IRQ1 IRQ1 _ 9 REDG1 IRQ1IE IRQ1IR At reset 000 0 0 IRQ1IR External interrupt request flag 0 No interrupt request 1 Interrupt request generated IRQ1IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDG1 External interrupt active edge flag 0 Falling edge 1 Rising edge IRQ1 IRQ1 Interrupt level flag LV1 LVO for externa
178. able interrupt control register Enable interrupt which set the xxx IE of the return factor will trigger return and set MIE flag in the PSW HALT STOP Watchdog timer mode HALT stop counting STOP reset Processing inside parentheses is handled by hardware Set HALT STOP mode When returning from STOP mode wait for oscillation to stabilize Watchdog timer NORMAL SLOW HALT restarts counting mode STOP disabled Interrupt acceptance cycle lt _ lt Return factor interrupt occured Figure 2 4 3 Transition to from STANDBY Mode or higher than the mask level in PSW before transition to HALT or STOP mode it is impos a If the interrupt is enabled but interrupt priority level of the interrupt to be used is not equal to sible to return to CPU operation mode by maskable interrupt Standby Functions II 27 Chapter 2 CPU Basics i Transition to HALT modes The system transfers from NORMAL mode to HALTO mode and from SLOW mode to HALT1 mode The CPU stops operating but the oscillators remain operational There are two ways to leave a HALT mode a reset or an interrupt A reset produces a normal reset an interrupt an immediate return to the CPU state prior to the transition to the HALT mode The watchdog timer if enabled resumes counting Program 4 MOV x 4 DO Set HALTO mode MOV DO CPUM NOP After written in CPUM some NO
179. ace Transfer Rate and Timer Compare Register decimal Transfer Rate bps fosc Clock Source 300 1200 2400 4800 9600 19200 MHz timer 3 Set Value CakuatedVale Set Value Calcuated Value Set Value Calcuated Value Set Value Cakuated Value Set Value Caluated Value Set Value Calculated Value 4 00 tosc F 207 1202 103 2403 51 4807 25 9615 12 19230 fs 4 103 300 i 5 16 s 3 E 4 19 fosc 217 1201 108 2402 54 4762 15 9699 fs 4 108 300 5 z E 6 16 E 8 00 tosc 207 2404 103 4807 51 9615 25 19230 5 4 207 300 51 1201 E 2 7 5 16 gt z 8 38 tosc 5 217 2403 108 4805 54 9523 26 19398 5 4 217 300 54 1190 x z 3 E z 5 fs 16 B E S 12 00 tosc E 155 1808 77 9615 38 19230 15 4 77 1202 38 2403 3 5 16 77 300 5 i 5 E 16 00 fosc 207 4808 103 9615 51 19230 fs 4 103 1202 51 2404 p 3 E fs 16 103 300 2 j E 16 76 fosc 5 J 217 4805 108 9610 54 19045 fs 4 108 1201 54 2381 E E 5 16 108 300 2 E 20 00 E 129 9615 64 19231 5 4 129 1202 64 2404 32 4735 5 16 129 300 5 2 5 Operation
180. akage current ILK1 Vi 0 V to VDD 2 Input pin 2 P20 to P22 Schmitt trigger input 15 Input high voltage 0 8 VDD VDD 16 Input low voltage ViL3 0 0 2 VDD 17 Input leakage current Vi 0 V to 2 18 Input high current on 30 100 300 xm Pull up resistor ON Input pin 3 PAO to Schmitt trigger input 0 8 VDD VDD 19 Input high voltage VIH4 4 5 V to 5 5 V 0 54 VDD VDD V 20 Input low voltage ViLA 0 0 2 VDD 21 Input leakage current 4 Vi 0 V to 2 5 0 1 5 22 Input current 1 4 Pull up resistor ON 30 100 300 UA 23 Input current 2 VDOT SDN M Dew 30 100 300 VO pint P27 NRST Schmitt trigger input 24 Input high voltage VIH5 0 8 VDD VDD 25 Input low voltage Vis 0 0 15 VDD i 26 Input leakage current ILks VDD 10 27 Input current hs Pul 30 100 300 xi VO pin2 P0O0 to P06 P10 P12 to P14 Schmitt trigger input 28 Input high voltage VIH6 0 8 VDD VDD 29 Input low voltage ViL6 0 0 2 VDD 30 Input leakage current Vi 0 V to 2 31 Input current 2 mM 30 100 300 ES 32 Output high voltage VOH6 Vop 5 0 V 0 5 mA 4 5 33 Output low voltage VpD 5 0 1 5 0 5 Y I 24 Electrical Characteristics Chapter 1 Overview is for EPROM vers 40 to 85
181. al ROM Internal RAM 1 n functions External expansion bus Clock generator Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals to CPU blocks Program counter Generates addresses for the instructions to be inserted into the instruction queue Normally incremented by sequencer indication but may be set to branch destination address or ALU operation result when branch instructions or interrupts occur Instruction queue Stores up to 2 bytes of pre fetched instructions Instruction decoder Decodes the instruction queue sequentially generates the control signals needed for instruction execution and executes the instruction by controlling the blocks within the chip Instruction execution controller Controls CPU block operations in response to the result decoded by the instruction decoder and interrupt requests ALU Executes arithmetic operations logic operations shift operations and calculates operand addresses for register relative indirect addressing mode Internal ROM RAM Assigned to the execution program data and stack region Address register Stores the addresses specifying memory for data transfer Stores the base address for register relative indirect addressing mode Data register Holds data for operations Two 8 bit registers can be connected to form a 16 bit register Interrupt
182. ame cycle The LCD clock is supplied by the fosc or fx clock divided by the prescaler Bits 0 to 3 of the LCMD register sets the LCD clock and LCODTYO to 1 sets the LCD frame cycle Representative input frequencies corresponding to the LCD clock and the LCD frame cycle are shown below Table 11 3 4 Input Frequency and the LCD Clock Ecl Input Frequency Input Clock Duty 20 MHz 16 MHz 8 MHz 4 MHz 32 768 kHz LCDCKS to 0 LCDTY1 to 0 LCD Clock Frame LCDCbck Frame LCDClock Frame Frame LCDCbck Frame 00 1 4 duty 2441 Hz 1953 Hz 977 Hz 488 Hz 0000 01 1 8 duty 3255 Hz 2604 Hz 1302 Hz 651 Hz SCION 9766 Hz 7818 Hz 3906 Hz 1953 Hz M0 1 2 duty 4883 Hz 3906 Hz 1953 Hz 977 Hz 11 static 9766 Hz 7813 Hz 3906 Hz 1953 Hz 00 1 4 duty 1221 Hz 977 Hz 488 Hz 244 Hz 0001 01 1 3 duty 1628 Hz 1302 Hz 651 Hz 326 Hz a 4883 Hz 3906 Hz 1953 Hz 977 Hz 05 61 2 1 2 duty 2441 Hz 1953 Hz 977 Hz 488 Hz 11 static 4883 Hz 3906 Hz 1953 Hz 977 Hz 00 1 4 duty 610 Hz 488 Hz 244 Hz 122 Hz 0010 01 1 3 duty 814 Hz 651 Hz 326 Hz 163 Hz
183. ample Timer 4 Pulse width measurement is enabled by storing the value of the binary counter to the capture register at the interrupt generation edge of the external interrupt 0 input signal with timer 4 The interrupt generation edge is specified to be the rising edge An example setup procedure with a description of each step is shown below interrupt interrupt External interrupt IRQO input gt Pulse width to be measured Figure 6 8 2 Pulse Width Measurement of External Interrupt 0 Setup Procedure Description 1 Stop the counter 1 Set the TM4EN flag of the timer 4 mode TM4MD 3 84 register TM4MD to 0 to stop timer 4 bp6 TMAEN 0 counting 2 Select the count clock source 2 Select fosc as clock source by the TM4CK2 0 TM4MD x 3F 84 flag of the TM4MD register bp2 0 TM4CK2 0 000 3 Select the capture trigger generation 3 Select the external interrupt 0 IRQO input as interrupt source a generation source of capture trigger by the TM4MD x 3F84 T4ICTS1 0 flag of the TM4MD register bp4 3 T4ICTS1 0 01 4 Select the interrupt generation active 4 Set the REDGO flag of the external interrupt 0 edge control register IRQOICR to 1 to select the IRQOICR x 3FE2 rising edge as the interrupt generation active bp5 REDGO 1 edge 5 Select the normal timer operation 5 Set the TM4PWM of the timer 4 mode TM4MD x 3F84 register TM4MD to 0 to select the n
184. an input or output P82 72 D2 SEG28 bythe P8DIR register A pull up resistor for each bit can P83 71 D3 SEG29 be selected individually by the P8PLU register P84 70 D4 SEG30 At reset when single chip mode is selected the input P85 69 D5 SEG31 mode is selected and pull up resistors for P80 to P87 P86 68 D6 SEG32 are disabled high impedance output P87 67 D7 SEG33 When configured as outputs these pins can drive segments PAO 16 Input ANO Input port A 8 bit input port PA1 17 AN1 KEY1 A pull up or pull down resistor for each bit can be PA2 18 AN2 KEY2 selected individually by the PAPLUD resister However PA3 19 AN3 pull up and pull down resistors cannot be mixed PA4 20 AN4 KEY4 At reset the PAO to PA7 input mode is selected and PA5 21 AN5 KEY5 pull up resistors are disabled PA6 22 AN6 KEY6 PA7 23 AN7 KEY7 SBOO 25 Output P00 TXD Serial interface Transmission data input pins for serial interfaces 0 transmission data The output configuration either CMOS push pull or n output pins channel open drain can be selected Pull up resistors can be selected by the POPLU register Select output mode by the PODIR register and serial data output mode by serial mode register SCOMD3 These can be used as normal pins when the serial interface is not used SBIO 26 Input P01 RXD Serial interface Receive data input pins for serial interfaces 0 SBH 29 P04 received data Pull up resistors can be selected by the POPLU inp
185. apter 1 1 6 1 Rom option mWatchdog Timer Control Register WDCTR 7 6 5 4 3 2 1 0 WDCTR WDEN at reset 0 WDEN Watchdog timer 0 Watchdog timer is cleared disabled 1 Watchdog timer is enabled Figure 8 2 1 Watchdog Timer Control Register WDCTR x OSF02 R W Control Registers VIII 3 Chapter 8 Watchdog Timer 8 3 Operation 8 3 1 Operation The watchdog timer counts system clock fs as a clock source If the watchdog timer overflows the watchdog interrupt WDIRQ is generated as an non maskable interrupt NMI At reset the watchdog timer is stopped The watchdog timer control register WDCTR sets if the watchdog timer is enabled or disabled If the watchdog interrupt WDIRQ is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware Reset pin outputs low level mUsage of Watchdog Timer When the watchdog timer is used constant clear in program is necessary to prevent an overflow of the watchdog timer As a result of the software failure the software cannot execute in the intended se quence thus the watchdog timer overflows and error is detected After error is detected the watchdog timer interrupt WDIRQ is generated as non maskable interrupt NMI Programming of the watchdog timer is generally done in t
186. atic Driving Waveform Vpop Vici COMO ViCD Vica Vice Vpp Vici SEG4 data 0 Vica Vice Voo Vict SEG6 dat 0 Vica SEP A electrode COMO SEG4 B electrode COMO SEG6 lit Figure 11 4 1 LCD Display Example of Static LCD Function Operation XI 15 Chapter 11 LCD Functions 11 4 2 Setup Example Static Setup Example of the LCD Function Operation Static Segment signal SEGO to SEG7 and common signal COMO make the 8 segment LCD panel display OT a Chapter 11 11 4 1 LCD Display Examples Static It is used 4 MHz as the high oscillation clock fosc 122Hz as fosc 2 gt for LCD clock and 122 Hz as frame frequency An example setup procedure with a description of each step is shown below Setup Procedure Description 6 Stop the LCD operation LCMD x3FCD bp7 LCDEN ll Setup of the LCD display duty LCMD x 3FCD bp5 4 LCDDTY1 0 11 Setup of the LCD clock LCMD x 3FCD bp3 0 LCDCK3 0 0100 Setup of the segment output segment port pins LCCTR x bp6 0 SEGSEL6 0 x 60 Setup of the display data Segment output latch SEG1 0 X 3FBD x 00 Segment output latch SEG3 2 X SFBE x11 Segment output latch SEG5 4 x 3FBF x10 Segment output latch SEG7 6 x 3FCO 11 Start the LCD operation LCMD x 3FCD bp7 LCDEN ll 6
187. aveform of 5 Register bp1 Timer 5 8 8 bit Free running Timer Chapter 7 Time Base Timer 8 bit Free running Timer iCount Timing of Timer Operation Timer 5 Binary counter counts up with the selected clock source as a count clock Count clock TM5CLRS flag Compare register i B counter A D Compare match signal Interrupt 1 request i flag C E Figure 7 3 2 Count Timing of Timer Operation Timer 5 A When any data is written to the compare register as the TM5CLRS flag is 0 the binary counter is cleared to 00 B Even if any data is written to the compare register as the TM5CLRS flag is 1 the binary counter is not changed C When the binary counter reaches the value of the compare register as the TM5CLRS flag is 1 aninterrupt request flag is set at the next count clock D When an interrupt request flag is set the binary counter is cleared to x 00 and restarts the counting E Even if the binary counter reaches the value of the compare register as the TM5CLRS flag is 0 nointerrupt request flag is set When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1
188. binary counter capture register Each register has 2 sets of 8 bit register Operate by 16 bit access Compare register is a 16 bit register stores the value that compared to binary counter 4 Compare Register 4 7 6 5 4 3 2 1 0 TM4OCL TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 4 2 TM40CL1 TM40CLO At reset X X X X X X X X Figure 6 2 1 Timer 4 Compare Register Lower 8 bits TM4OCL x 03F74 R W 7 6 5 4 3 2 1 0 TM4OCH TM4OCH7 TM4OCH6 TM4OCH5 TM4OCH4 TM4OCH2 TM4OCH1 TMdOCH0 At reset X X X XX XXX Figure 6 2 2 Timer 4 Compare Register Upper 8 bits x 03F75 R W Binary counter is a 16 bit up counter If any data is written to a compare register during counting is stopped the binary counter is cleared to 0000 Timer 4 Binary Counter TM4BC 7 6 5 4 3 2 1 0 TMABCL 6 5 TM4BCL3 TM4BCL2 TM4BCL1 neca atreset 00000000 Figure 6 2 3 Timer 4 Binary Counter Lower 8 bits x 03F64 R 7 6 5 4 3 2 1 0 TM4BCH7 TM4BCH6 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2 at 00000000 Figure 6 2 4 Timer 4 Binary Counter Upper 8 bits TM4BCH x 03F65 Control Registers VI 5 Chapter 6 16 bit Timer Input capture regist
189. buffer 4 at master Disable start condition Writing data to serial buffer Transmission Enable start condition Clock reception Y at slave Disable start condition Clock reception Y Enable start condition Start condition reception 4 at master Disable start condition Writing data to serial buffer Reception Enable start condition Start condition reception at slave Disable start condition Clock reception Start condition is output by writing the transmission data to the transmission reception shift register SCOTRB when the SCOSBOS flag of the serial interface 0 mode register 3 SCOMD3 is set to 1 Then the transmission is started by the slave clock When synchronous serial interface is used for master clock reception it is necessary to write dummy data to the transmission reception shift register SCOTRB for starting master clock Automatic sequence reception with automatic data transfer can not be used because it is necessary to write dummy data to serial interface buffer and to read reception data per a frame reception Operation X 11 Chapter 10 Serial Interface 0 Cautions for master clock reception by the synchronous serial interface 0 On the product with serial interface 1 or serial interface 2 master clock reception by synchro nous serial interface 1 2 is started by setting the SCxSBTS of the serial interface mode register SCxMDx to 1 then setting the SCxSBIS to 1 and writ
190. ce set the SCOCMD flag of the serial interface 0 control register SCOCTR to 1 Activation Factor for Communication At transmission if any data is written to the transmission reception shift register SCOTRB a start bit Data is changed from H to L is generated to start transfer At reception if a start bit Data is changed from H to L is received communication is started At reception if the data length of L is longer than 0 5 bit that can be regarded as a start bit iTransmission Data transfer is automatically started by writing data to the transmission reception shift register SCOTRB after setting the SCOSBOS flag of the SCOMDO3 register to 1 During transmission reception and start bit input are disabled mReception When the SCOSBIS flag of the register is set to 1 and a start bit is received reception is started after the transfer bit counter is set as frame mode is specified During reception transmission is disabled Transfer Bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the SCOFM1 to 0 flag of the SCOMD2 register If the SCOCMD flag of the SCOCTR register is set to 1 and UART communica tion is selected the synchronous serial data transfer bit count selection flag SCOLNG2 to 0 of the SCOMDO register is automatically set Edge Output Edge Setup The SCOCE 1 0 flag of the SCOMDO register set an output edge of the transmissio
191. ck Timer 2 Timer 3 2 input input Event input P12 P13 Synchronous 2 input Synchronous TM3IO input iCount Timing of Input Timers 2 and 3 When TMnlO input is selected input signal is directly input to the count clock of the timer n The binary counter counts up at the falling edge of the TMnIO input signal Compare M register i ON AE UM counter Compare match signal Interrupt request flag Figure 5 4 1 Count Timing TMnIO Input Timers 2 and 3 When the TMnIO input is selected for count clock source and the value of the timer n binary counter is read during operation incorrect value at count up may be read To prevent this use the event count by synchronous TMnIO input as the following page 14 8 bit Event Count Chapter 5 8 bit Timers Count Timing of Synchronous TMnIO Input Timers 2 and 3 If the synchronous TMnIO input is selected the synchronizing circuit output signal is input to the timer count clock The synchronizing circuit output signal is changed at the falling edge of the system clock after the TMnIO input signal is changed TMnlO input N A a X X System clock fs Synchronizing circuit output Count clock Y 4 Y Y flag Compare register counter Compare match signal Interrupt request flag Figure 5 4 2 Count Timing of Synchronous TMnIO Input Timers 2
192. clock line SBTO pin is L When the reception and the transmission should be operated at the same time disable start condition for proper operation Enabling the start condition drives the SBOO pin high level for a fixed time interval 1 2 the clock source cycle after the transmission has completed If the start condition is disabled the SBOO will remain at the level of the last data bit cleared when the start condition is received In this case the receive bit count is fixed at 8 bits Gd If the start condition is enabled the SCOLNG2 to 0 flags of the SCOMDO register will be reception and the transmission should not be operated at the same time The clock may be a On the master communication of the clock synchronous if start condition is enabled the continued to output after the communication has completed First Transfer Bit The SCODIR flag of the SCOMDO register can set the first transfer bit MSB first or LSB first can be selected Transmission Data Set the transmission data to the transmission reception shift register SCOTRB Operation 13 Chapter 10 Serial Interface 0 When switching from transmission to reception set the SCOSBOS flag of the SCOMDO reg ister to 0 and then set the SCOSBIS flag to 1 Do not change both of these flags at the same time When switching from reception to transmission set the SCOSBIS flag of the SCOMDO regis ter to 0 and t
193. ctor base 00100 Wait cycles when Bus cycle at IOW1 to accessing special register area 20 MHz oscillation 00 No wait cycles 100 ns 01 1 wait cycle 150 ns 10 2 wait cycles 200 ns 11 3 wait cycles 250 ns Figure 2 3 2 Memory Control Register MEMCTR x 3F01 R W Bus Interface II 17 Chapter 2 CPU Basics The EXW1 EXWO wait settings affect accesses to external devices in the memory expansion mode After reset MEMCTR specifies the fixed wait cycle mode with three wait cycles dresses x 3F00 x 3FFF After reset MEMCTR specifies the fixed wait cycle mode with three wait cycles Wait setting of IOW is a function which CPU supports for special use for ex ample when special function register or I O is expanded to external For this LSI wait cycle setting is not always necessary Select no wait cycle for high performance system con struction 4 The IOW1 IOWO wait settings affect accesses to the special registers located at the ad mExpansion Address Control Register EXADV 7 6 5 4 3 2 1 0 EXADV EXADV3 EXADV2 EXADV1 At reset 000 P73 P70 11 address output EXADYA during memory expansion mode 0 General port 1 A11 to A8 address output ExADV2 P77 74 15 A12 address output during memory expansion mode 0 General port 1 A15 to 12 addre
194. d a current flow through the ladder resistance and A D converter goes into the waiting 2 to 5 are not in order 3 4 and 5 can be operated simultaneously Start the A D conversion Set the ANST flag of the A D converter control register 1 ANCTR1 to 1 to start A D converter A D conversion Each bit of the A D buffer 0 1 is generated after sampled in the sample and hold time set in 3 Each bit is generated in sequence from MSB to LSB Complete the A D conversion When A D conversion has finished the ANST flag is cleared to 0 and the result of the conversion is stored to the A D buffer ANBUFO 1 At the same time the A D complete interrupt request ADIRQ is generated Operation Chapter 12 A D Converter A D conversion clock ANST flag A D conversion start A D conversion complete Ts 7 lt gt Sampling Hold A D conversion bit 8 comparison bit 9 comparison bit 0 comparison bit 9 bit 8 bit 1 bit 0 Determine Determine Determine Determine This example is as sampling and hold time is TAD x 2 A D interrupt ADIRQ Figure 12 3 1 Operation of A D Conversion To read the value of the A D conversion A D conversion should be done several times to prevent noise error by confirming the match of level by program or by using the average value Operation XII 9 Chapter 12 A D Converter 12 3 1 Se
195. e Description 1 Stop the counter TM2MD x 3F82 bp4 TM2EN 0 TM3MD x 3F83 bp4 TMSEN 0 2 Select the normal operation of lower timer TM2MD x 3F82 bp3 0 3 Set the cascade connection x 3F83 bp2 0 2 0 100 4 Select the count clock source TM2MD x 3F 82 bp2 0 TM2CK2 0 001 5 Set the interrupt generation cycle TMnOC x 3F73 x 3F72 x 09C3 6 Disable the lower timer interrupt TM2ICR x 3FE4 bp1 2 0 Set the 2 flag of the timer 2 mode register TM2MD to 0 the TMSEN flag of the timer mode register TM3MD to 0 to stop timer 2 and timer 3 counting Set both of the TM2PWM flag of the TM2MD register to to select the normal operation of timer 2 Connect timer 2 and timer 3 in cascade connection by the 2 0 flag of the TM3MD register Set the clock source to fs 4 by the TM2CK2 0 flag of the TM2MD register Set the timer 3 compare register timer 2 compare register TM3OC TM2OC to the interrupt generation cycle x 09C3 2500 cycles 1 At that time timer 3 binary counter timer 2 binary counter TM3BC TM2BC are initialized to x 0000 Set the TM2IE flag of the timer 2 interrupt control register TM2ICR to 0 to disable the interrupt 32 Cascade Connection Chapter 5 8 bit Timers Setup Procedure Description 10 Set the lev
196. e Please refer to the at tached documents for how to use the diagnostic tool If a corresponding defect is determined through the diagnostic tool insert a nop instruction to avoid the corresponding condition to be fulfilled Example Addr Code 04100 AA mov A0 DO If a corresponding defect is determined 04100 89F7 bra 7 through the diagnostic tool insert a nop 04102 00 i mop instruction to avoid the corresponding 04103 2F dc F2 d 04104 DO dc 00 condition to be fulfilled Control Registers 17 Chapter 3 Interrupts External Interrupt 0 Control Register IRQOICR The external interrupt 0 control register IRQOICR controls interrupt level of the external interrupt 0 active edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is set to level 3 IRQOLV1 IRQOLVO 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag T 6 5 4 3 2 1 0 IRQO IRQO Mg IRQOICR LVI LVO REDGO IRQOIR At reset 000 0 0 External interrupt IRQOIR request flag 0 No interrupt request 1 Interrupt request generated External interrupt IRQOIE enable flag 0 Dis
197. e 6 1 1 16 bit Timer Functions Timer 4 16 bit timer Interrupt source TM4IRQ Timer operation Event count Timer pulse output PWM output Added Pulse Type Synchronous output Capture function 4 fosc Clock source h input fosc Machine clock High speed oscillation fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 VI 2 Overview 16 bit Timer Chapter 6 Block Diagram 6 1 2 4 E WM PN ZMOvINL OXOTINL 0 4 ANN LLL Y 1 uoneziu 10151691 eunjdeo 19 91 74 jouuouAs 7 ooul OILSY Y Ttouyouks eo 1 indino WMd Y Y indino sis 1 8 Hoar 8 ue lt a uonippe asing 110 9 NT 7 a yN jue e 1ndino snouosyouAS i yore l mi uoppe asd HOOPWL Timer 4 Block Diagram 49481691 16 91 1 4
198. e P1DIR register A pull up resistor for each bit can be selected individually by the P1PLU register At reset the input mode is selected and pull up resistors are disabled high impedance output I 11 Pin Description Overview Chapter 1 Overview Table 1 3 4 Pin Function Summary 2 7 Name T pin y o Other Function Function Description P20 34 Input IRQO Input port 2 3 bit input port P21 35 IRQ1 SENS A pull up resistor for each bit can be selected P22 36 IRQ2 individually by the P2PLU register At reset pull up resistors are disabled P27 29 Input NRST Input port 2 P27 has an n channel open drain configuration When 0 is written and the reset is initiated by software low level will be output P50 37 vO NWE LEDO VO port 5 4 bit CMOS tri state VO port P51 38 NRE LED1 Each bit can be set individually as either an input or P52 39 NCS LED2 output by the P5DIR register A pull up resistor for each P53 40 A16 LED3 SEG24 bit can be selected individually by the P5PLU register At reset when single chip mode is selected the input mode is selected and pull up resistors for P50 to P53 are disabled high impedance output When configured as outputs P50 to P53 can drive LED directly and also P53 can drive segments P60 41 VO SEG23 VO port 6 8 bit CMOS tri state VO port P61 42 1 SEG22 Each bit can be set individually as either an input or P62 43 A2 SEG21 output by the
199. e PAO to PA3 pins shows low level the external interrupt 4 is generated at the falling edge The setup of the key input should be done before the interrupt is enabled 39 External Interrupts Chapter 3 Interrupts 3 3 6 Noise Filter llNoise Filter External interrupts 0 to1 Noise filter reduces noise by sampling the input waveform from the external interrupt pins IRQO IRQ1 Its sampling cycle can be selected from 4 types 15 22 15 28 fs 2 15 215 llNoise Remove Selection External interrupts 0 to 1 Noise remove function can be used by setting the NFnEN flag of the noise filter control register NFCTR to 1 Table 3 3 3 Noise Remove Function NFnEN IRQO input P20 IRQ1 input P21 0 IRQO Noise filter OFF IRQ1 Noise filter OFF 1 IRQO Noise filter ON IRQ1 Noise filter ON 5 Cycle Setup External interrupts 0 and 1 The sampling cycle of noise remove function can be set by the NFnCKS 1 0 flag of the NFCTR register Table 3 3 4 Sampling Cycle Time of Noise Remove Function TNR Sampling High frequency oscillation cycle at fosc 20 MHz at fosc 8 MHz 0 fs 2 2 5 MHz 400 ns 1 MHz 1 us 1 5 28 39 06 kHz 25 60 us 15 62 kHz 64 us 0 15 29 19 53 kHz 51 20 us 7 81 kHz 128 us 1 fs 2 9 77 kHz 102 40 us 3 91 kHz 256 us 40 External Interrupts Chapter 3 Interrupts llNoise Remove Fu
200. e below in the internal EPROM specify the oscillator speed SLOW or NORMAL In the MN101C48X microcomputer EPROM versions MN101CP485 MN101CP487 etc bits 2 to 0 at address X 07FFF in the internal EPROM specify the oscillator speed SLOW or NORMAL B ROM Option Bits Figure 9 1 2 ROM Option Bits Figure 9 1 2 ROM Option Bits address X 07FFF Model EPROM Option Address MN101CP485 X 07FFF MN101CP487 X 07FFF After a reset connect oscillator pins to the high speed oscillation input too even if the slow mode is selected The WDMD bp5 should be always set to 1 If itis set to 0 that operation cannot be stopped after the watchdog timer is generated Differences between Old manual 1st Edition and Current manual 1st Edition 1st Printing Page Line Old manual 1st Edition Current manual 1st Edition 1st Printing 4 23 Serisl interface 2channels Serisl interface 1channel 1 13 fig 1 4 1 ROM ROM 8 16 Serial interface 0 Serial interface 1 Serial interface 0 Serial interface 0 only 101 485 487 LSI User s Manual June 2002 2nd Edition 8th Printing Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd
201. e of clock SBOO pin Figure 10 3 10 Transmission Reception Timing Reception falling edge Transmission rising edge SCOCEO 0 SCOCE1 1 X 22 Operation Pins Setup 3 channels at transmission Table 10 3 5 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO pin pin at transmission Chapter 10 Serial Interface 0 Table 10 3 5 Setup for Synchronous Serial Interface Pin 3 channels at transmission Data output pin Data input pin Clock VO pin SBTO pin Setup item SBOO pin SBIO pin Internal clock External clock master communication slave communication Pin P02 SBI0 SBOO independent SBIO SBOO pin 5 SCOMD3 SCOIOM Serial data output input Serial clock VO Port Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull Push pull Style Nch open drain E Nch open drain Nch open drain SCOOMD3 SCOSBOM SCOMD3 SCOSBTM ie Output mode Output mode Input mode PODIR PODIRO PODIR PODIR2 Bl Added Not added Added Not added Added Not added ull up POPLU POPLUO POPLU POPLU2 WPins Setup 3 channels at reception Table 10 3 6 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO pin pin at reception Table 10 3 6 Setup for Synchronous Serial Interface Pin 3 channels at reception
202. ection control register 11 x O3F89 R W Remote control carrier output control register V 9 carrier output R W Readable Writable Readable only Control Registers V 5 Chapter 5 8 bit Timers 5 2 2 Programmable Timer Registers Each of timers 2 and 3 has 8 bit programmable timer registers Programmable timer register consists of compare register and binary counter Compare register is 8 bit register which stores the value to be compared to binary counter Timer 2 Compare Register TM2OC 7 6 5 4 3 2 1 0 TM20C 20 7 TM20C6 TM20C5 TM20C2 20 1 20 0 Atreset XXXXXXKXX Figure 5 2 1 Timer 2 Compare Register 2 72 R W Compare Register 7 6 5 4 3 2 1 0 TM30C TM30C7 TM30C6 TM30C5 TM30C4 TM30C3 TM30C2 TM30C1 TM30C0 At reset X X XX XX XX Figure 5 2 2 Timer Compare Register x 03F73 R W Binary counter is 8 bit up counter If any data is written to compare register during counting is stopped binary counter is cleared to 00 Timer 2 Binary Counter TM2BC 7 6 5 4 3 2 1 0 TM2BC TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 2 Atreset 00000000 Figure 5 2 3 Timer 2 Binary Counter TM2BC x 03F62 Timer Binary Counter TM3BC 7 6 5 4 3 2 1 0 T
203. ed the interrupt is accepted regardless of the interrupt mask level of PSW The hardware then branches to the address stored at location x 04004 in the interrupt vector table The watchdog timer overflow interrupt request flag WDIR is set to 1 when the watchdog timer overflows The program interrupt request flag PIR is set to 1 when the undefined instruction is executed 7 6 5 4 3 2 1 0 NMICR PIR WDIR Reserved At reset 000 E Reserved Always set to 0 WDIR Watchdog interrupt request flag 0 No interrupt request 1 Interrupt request generated PIR Program interrupt request flag 0 No interrupt request 1 Interrupt request generated Figure 3 2 1 Non maskable Interrupt Control Register NMICR x 03FE1 R W On this LSI when undefined instruction is decoded the program interrupt request flag PIR is set to 1 and the non maskable interrupt is generated If the PIR flag setup is confirmed by the non maskable interrupt service routine the reset via the software is recommended When software reset the reset pin P27 outputs 0 Clear it to O a Once the WDIR becomes 1 by generating of non maskable interrupt only the program can 16 Control Registers Chapter 3 Interrupts Faulty interrupt which is not occured under normal conditions could be occered with certain combina
204. ed same 1 as that after reset Software must count that time a We recommend selecting the oscillation stabilization time after consulting with oscillator manufacturers Sample program for transition from SLOW to NORMAL mode is given below Program 2 MOV 01 DO Set IDLE mode MOV DO CPUM Program 3 MOV DO A loop to keep approx 6 7 ms with low frequency clock 32 kHz LOOP ADD 1 00 operation when changed to high frequency clock 20 MHz BNE LOOP SUB DO MOV DO CPUM Set NORMAL mode Standby Functions II 25 Chapter 2 CPU Basics Refer the following cautions to initiate the program on the transition to SLOW mode in case where the execution time at NORMAL mode is too short After the transition to NORMAL mode from SLOW mode if the mode is returned to SLOW again during 2 to 4 cycles of the low speed oscillation clock the short pulse can be generated in the system of the clock causing errors SLOW IDLE NORMAL SLOW CPU mode control register CPUM time 61 0 us to 122 0 us Xl 32 768 kHz If the mode will be switched to SLOW again the execution time of NORMAL mode should be not in this duration The following 1 or 2 should be executed on the program by the software When the execution time at NORMAL is above that duration 1 The following program should be inserted to make the waiting time for more than 4 cycles
205. edge from the falling to the rising when the interrupt pin is H level 2 at switching the active edge from the rising to the falling when the interrupt pin is L level Operate the interrupt flag with regard to the noise influence on the program t Chapter 3 3 3 4 Programmable Active Edge Interrupt 16 bit Timer Capture VI 27 Chapter 6 16 bit Timer Capture Count Timing at Falling Edges of External Interrupt Signal is selected as a Trigger Timer 4 TM4EN flag Compare N register a fale External interrupt m Capture trigger SEE MEE NM CE Figure 6 8 1 Capture Count Timing at an External Interrupt Signal is selected as a Trigger Timer 4 A capture trigger is generated at the falling edges of the external interrupt m input signal At the same timing the value of a binary counter is stored to the input capture register A capture trigger is generated only at the edge that is specified as a capture trigger source The other count timing is same to the count timing of the timer operation When the binary counter is used as a free counter that counts x 0000 to x FFFF set the compare register to x FFFF If a capture trigger is generated before the value of the input capture register is read the value of the input capture register can be rewritten 28 16 bit Timer Capture Chapter 6 16 bit Timer 6 8 2 Setup Example iCapture Function Setup Ex
206. egardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 Sco SCO CREE SCOICR LV1 LVO SCOIE SCOIR at reset 00 00 SCOIR Interrupt request flag 0 No interrupt request flag 1 Interrupt request generated SCOIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt UD 20 Interrupt level fla Lvi LVO 9 CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 11 Serial interface 0 Interrupt Control Register SCOICR x 03FE8 R W Control Registers III 27 Chapter 3 Interrupts A D Conversion Interrupt Control Register ADICR The A D conversion interrupt control register ADICR controls interrupt level of A D conversion interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 ADLV1 ADLVO0 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 1 0 AD AD ADICR LV1 LVO ADIE ADIR At reset 0 0 0 0 ADIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated ADIE Interrupt enable flag 0 Disable int
207. egister to 1 to set SBOO pin serial data output SBIO pin serial data input Set the interrupt level by the SCOLV1 0 flag of the serial interface 0 interrupt control register SCOICR Set the SCOIE flag of the SCOICR register to 1 to enable interrupts If the interrupt request flag SCOIR of the SCOICR register had already been set clear SCOIR before an interrupt is enabled e Chapter 3 3 1 4 Interrupt Flag Setup 27 Operation Chapter 10 Serial Interface 0 Setup Procedure Description 10 Start serial interface transmission 10 Set the transmission data to the serial interface 0 Transmission data gt SCOTRB x 3F55 transmission reception shift register SCOTRB Reception data input to SBIO pin Then an internal clock is generated to start transmission reception After the transmission has finished serial interface 0 interrupt SCOIRQ is generated Note In 2 each settings can be set at once When only reception with channels is operated set SCOSBOS of the SCOMD3 register to 0 and select a port The SBOO pin can be used as a general port When SBOO SBIO pin are connected for communication with 2 lines the SBOO pin inputs outputs serial data The port direction control register PODIR switches input output At re ception set SCOSBIS of the SCOMDS register to 1 always to select serial data input The SBIO pin can be used as a general port
208. el 1 High level At reset XXX X P1IN Input data 0 Pin is low Vss level 1 Pin is high VDD level Atreset 000 0 P1DIR mode selection 0 Input mode 1 Output mode Atreset 000 0 P1PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 1 pull up resistor control register P1PLU x 03F41 R W Figure 4 3 1 Port 1 Registers 1 2 Port 1 IV 11 Chapter 4 I O Ports 4 3 2 1 0 1 P14TCO P13TCO P12TCO P10TCO 12 Porti Atreset 000 0 P10TCO port timer 0 output selection 0 port 1 Timer 0 output P12TCO l O port timer 2 output selection 0 port 1 Timer 2 output P13TCO port timer output selection 0 port 1 Timer 3 output P14TCO port timer 4 output selection 0 port 1 Timer 4 output Port 1 output mode register P1OMD x 03F39 R W Figure 4 3 2 Port 1 Registers 2 2 Chapter 4 Ports 4 3 3 Block Diagram Ee Rese PiPLUO Pull up resistor control gt gt Write
209. el Do not change the setup of MMOD pin after reset II 12 Memory Space Chapter 2 CPU Basics 2 2 2 Single chip Mode In single chip mode the system consists of only internal memory This is the optimized memory mode and allows construction of systems with the highest performance The single chip mode uses only internal ROM and internal RAM The MN101C series devices offer up to 12 KB of RAM and up to 240 KB of ROM MN101C487 devices offer 512 bytes of RAM and 16 KB of ROM 256 bytes x 00000 Abs 8 addressing access area Internal RAM space 512 bytes x 00100 Data x 00200 A x 03F00 Special registers function area T A 04000 Interrupt vector table 256 bytes Y A A 128 bytes Y A 04080 Subroutine vector table 64 bytes 16 y Internal ROM space 040 0 Instruction code Table data X 07FFF MMOD pin L Figure 2 2 1 Single chip Mode Differs depending on the model 6 Table 2 2 2 Internal ROM Internal RAM Table 2 2 2 Internal Internal Internal RAM Internal ROM Model bytes MN101C485 X 00000 to X 001FF 101 487 8K X 04000 to X OBFFF 16K 00000 to XUDIFF X000 o XUTFFF x 07FFF can not be used for MN101C485 487 because of ROM option The value of internal RAM is uncertain when power is applied to it It needs to be initialized before it is u
210. el of the upper timer interrupt TMSICR x 3FEE bp7 6 TM3LV1 0 10 Enable the upper timer interrupt TMSICR x 3FEE 1 Start the upper timer operation TMSMD x 3F83 bp4 1 Start the lower timer operation TM2MD x 3F82 bp4 TM2EN 1 10 Set the interrupt level by the TM3LV1 0 flag of the timer 3 interrupt control register TMSICR If any interrupt request flag had already been set clear it Set the flag of the TMSICR register to 1 to enable the interrupt t Chapter 3 3 1 4 Interrupt Flag Setup Set the flag of the TM3MD register to 1 to start timer 3 Set the TM2EN flag of the TM2MD register to 1 to start timer 2 TM3BC TM2BC counts up from x 0000 as a 16 bit timer When TM3BC TM2BC reaches the set value of TM3OC 2 register the timer interrupt request flag is set to 1 at the next count clock and the value of TM3BC TM2BC becomes x 0000 and counting up is restarted ka Use a 16 bit access instruction to set the 2 register timer operation If the lower timer starts to operate before the upper timer does the first overflow signal of the lower timer may be invalid To prevent this start the upper timer operation before the lower Cascade Connection V 33 Chapter 5 8 bit Timers 5 10 Remote Control Carrier Output 5 10 1 Operation Carri
211. en below 1 If the return factor is a maskable interrupt set the MIE flag in the PSW to 1 and set the interrupt mask IM to a level permitting acceptance of the interrupt 2 Clear the interrupt request xxxIR in the maskable interrupt control register XxxICR set the interrupt enable flag for the return factor and set the IE flag in the PSW 3 Set CPUM to HALT or STOP mode Set the IRWE flag of the memory control register MEMCTR to clear interrupt request flag by software The system clock fs is fosc 2 at NORMAL mode and fx 4 at SLOW mode II 24 Standby Functions Chapter 2 CPU Basics 2 4 3 Transition between SLOW and NORMAL The MN101C48 series has two CPU operating modes NORMAL and SLOW Transition from SLOW to NORMAL requires passing through IDLE mode A sample program for transition from NORMAL to SLOW mode is given below Program 1 MOV x 3 DO MOV DO CPUM Set SLOW mode Transition from NORMAL to SLOW mode when the low frequency clock has fully stabilized can be done by writing to the CPU mode control register In this case transition through IDLE is not needed For transition from SLOW to NORMAL mode the program must maintain the IDLE mode until high frequency clock oscillation is fully stable In IDLE mode the CPU operates on the low frequency clock For transition from SLOW to NORMAL oscillation stabilization waiting time is requir
212. ent generation cycle x 3F75 x 3F74 2x 0063 7 Start the timer operation x 3F84 4 1 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the P7SYEVS2 1 flag of the pin control register 2 FLOAT2 to 01 to set the synchronous output event to the timer 4 interrupt Set the synchronous output control register SYSMD to x FF to set the synchronous output pin P77 to P70 Synchronous output pin Set the port 7 direction control register P7DIR to x FF to set port 7 to output pin If it needs pull up resistor should be added a 4 Ports Select fs 4 as a clock source by the TM4CK2 0 flag of the TM4MD register Set the TM4PWM flag of the TM4MD register to 0 to select the normal timer operation Set the synchronous output event generation cycle to the timer 4 compare register TM4OC To be 10 kHz by dividing 1 MHz set as follows 100 1 99 0063 Set the TM4EN flag of the TM4MD register to 1 to start timer 4 16 bit Timer Synchronous Output VI 25 Chapter 6 16 bit Timer TM4BC counts up from 0000 If any data is written to the port 7 output register P7OUT TM4BC reaches the set value of TM4OC register and the synchronous output pin outputs data of port 7 in every time an interrupt request is generated When the port 7 synchronous output is disabled the value of the
213. ent output control is set to without pull up resistors Figure 4 8 3 Block Diagram P80 to P87 Pot8 IV 37 Chapter 4 I O Ports 49 4 9 1 Description iGeneral Port Setup Port A is input port To read input data of pin read the value of the port A input register PAIN Each pin can be set individually if pull up pull down resistor is added or not by the port A pull up pull down resistor control register PAPLUD But pull up pull down cannot be mixed Set the control flag of the port A pull up pull down resistor control register PAPLUD to 1 to add pull up or pull down resis tor The pin control register 1 FLOAT1 select if pull up resistor or pull down resistor is added The bp1 of the FLOAT is set to 1 for pull down resistor and set to 0 for pull up resistor At reset the PAO to PA7 input mode is selected and pull up resistors are disabled ilSpecial Function Pin Setup PAO to are used as input pins for analog Each bit can be set individually as an input by the port A input mode register PAIMD When they are used as analog input pins set the port A input mode register PAIMD to 1 Then the value of the port A input register PAIN is 1 when input voltage is at intermediate level a By setting the control flag of the PAIMD register to 1 the through current is not occurred LI PAO to PA7 are used as input pins for KEY interrupt as well Key input pin should be pu
214. equency and the baud rate timer setup Operation X 37 Chapter 10 Serial Interface 0 Transfer Rate Baud rate timer timer 3 can set any transfer rate Table 10 3 17 shows the setup example of the transfer rate For detail of the baud rate timer setup Chapter 5 5 8 serial interface transfer clock output operation Table 10 3 17 Serial Interface Transfer Rate Setup Register Setup Register Page Serial 0 clock source timer 3 output SCOMD1 X 7 Timer 3 clock source TMS3MD V 8 Timer 3 compare register TM3OC V 6 Timer 3 compare register is set as follows overflow cycle set value of compare register 1 x timer clock cycle baud rate 1 overflow cycle x 2x8 8 means that clock source is divided by 8 Therefore set value of compare register timer clock frequency baud rate x 2 x 8 1 For example if baud rate should be 300 bps at timer 3 clock source fs 4 fosc 8 MHz fs fosc 2 set value should be as follows Set value of compare register 8 10 2 4 300 x 2 x 8 1 207 X CF Timer 3 clock source and the set values of timer 3 compare register at the standard transfer rate are shown on the following page At UART communication clock source is divided by 8 is selected regardless of the setup for the SCOCKM flag of the SCOMD 1 register X 38 Operation Chapter 10 Serial Interface 0 Table 10 3 18 UART Serial Interf
215. er M 3 clock Figure 5 8 1 Timing of Serial Interface Transfer Clock Timer 3 The timer pulse output is used as the clock source of the serial interface And its frequency is 1 2 of the set frequency in the timer compare register The count timing is same to the timing of timer operation For the baud rate calculation and the serial interface setup q Chapter 10 Serial Interface 0 V 28 Serial Interface Transfer Clock Output Chapter 5 8 bit Timers 5 8 2 Setup Example Serial Interface Transfer Clock Setup Example Timer 0 and Timer 3 How to create a transfer clock for half duplex UART serial interface 0 using with timer 3 is shown below The baud rate is selected to be 300 bps the source clock of timer 3 is selected to be fs 4 at fosc 8 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter x 3F83 bp4 TMSEN 0 Select the normal timer operation TM3MD x 3F83 bp3 TM3PWM 0 Select the count clock source TM3MD x 3F83 bp2 0 TM3CK2 0 001 Set the baud rate TM30C x 3F73 X CF Start the timer operation TM3MD x 3F83 bp4 1 1 Set the flag of the timer 3 mode register TM3MD to 0 to stop timer 3 counting Set the TM3PWM flag of the TM3MD register to 0 to select the normal timer operation Select the clock source to fs 4 by the 2
216. er Number Address Interrupt source address 0 04000 2 1 x04004 Non maskable interrupt NMI NMICR xOSFE1 2 X04008 External interrupt 0 IRQO IRQOICR 3 X0400C External interrupt 1 IRQ1 IRQ1ICR X 03FE3 4 04010 Reserved 5 X 03FE4 5 x04014 Reserved xO3FE5 6 X04018 Timer 2 interrupt TM2IRQ TM2ICR 6 7 x 0401C Time base period TBIRQ TBICR xO3FE7 8 X04020 Serial interface O interrupt SCOIRQ SCOICR X 03FE8 9 x04024 Reserved gt xO3FE9 10 x04028 converter interrupt ADIRQ ADICR 11 x0402C External interrupt 2 IRQ2 IRQ2ICR 12 X04030 Reserved 13 x 04034 External interrupt 4 IRQ4 IRQ4ICR xO3FED 14 x 04038 Timer 3 interrupt TM3IRQ TMSICR 15 X0403C Timer 4 interrupt TM4IRQ TM4ICR xO3FEF 16 x 04040 Timer 5 interrupt TMBICR 17 x 04044 Reserved xO3FF1 18 X04048 Reserved 5 19 x0404C Reserved gt 20 x 04050 Reserved For unused interrupts and reserved interrupts set the address the RTI instruction is de scribed on to the corresponded address 6 Overview Chapter 3 Interrupts Wilnterrupt Level and Priority This LSI allocated vector numbers and interrupt control registers except reset interrupt to each inter rupt The interrupt level except reset interrupt non maskab
217. er POOUT x 03F10 R W 7 6 5 4 3 2 1 0 POIN POIN6 POIN2 POINO At reset POIN Input data 0 Pin is low Vss level 1 Pin is high VDD level Port 0 input register POIN 20 7 6 5 4 3 2 1 0 PODIR Poirel z PODIR2 PODIR1 PODIRO Atreset 0 000 PODIR mode selection 0 Input mode 1 Output mode Port 0 direction control register PODIR x 03F30 R W 7 6 5 4 3 2 1 0 POPLU POPLUG POPLU2 POPLU1 At reset 0 000 POPLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 0 pull up resistor control register POPLU 40 R W Figure 4 2 1 Port 0 Registers Port 0 IV 7 Chapter 4 Ports 4 2 3 Block Diagram SCOMDS register 5 05 flag 5 ae heset R POPLUO Pull up resistor control gt Write i Read Reset PODIRO c direction control DQ 1 gt Write Read 3 X S Reset V g POOUTO T2 Port output data 9
218. er IV 18 Port5 P5DIR x 03F35 R W Port 3 direction control register V 18 P5PLU 03 45 R W Port 3 pull up resistor control register IV 18 LCCTR R W Segment output control register IV 20 25 32 36 PeOUT x O3F16 R W Port 6 output register N 24 P6IN x O3F26 Port 6 input register N 24 P6DIR x 03F36 R W Port 6 direction control register N 24 P6PLU 46 R W 6 pull up resistor control register N 24 LCCTR R W Segment output control register N 20 25 32 36 IV 4 Overview Chapter 4 I O Ports Table 4 1 3 Port Control Registers List 2 2 Register Address R W Function Page P7OUT x 03F17 R W Port 7 output register IV 29 P7IN x 03F27 Port7 input register IV 29 Port7 P7DIR x 03F37 R W Port 7 direction control register IV 29 P7PLUD x03F47 R W Port 7 pull up pull down resistor control register IV 29 LCCTR R W Segment output control register N 20 25 32 36 P8OUT 03 18 R W Port 8 output register IV 35 P8IN x O3F28 8 input register 35 Port8 P8DIR 03 8 R W Port 8 direction control register IV 35 P8PLU 48 R W Port 8 pull up resistor control register 35 LCCTR R W Segment output control register N 20 25 32 36 PAIN 2 input register 39 PAIMD X 03F3A R W Port A input mode register 39 PAPLUD X 03F4A R W Port A pu
219. er circuit with 25 segment pins and 4 common pins The LCD driver consists of a segment output latch a prescaler a timing control circuit segment drivers common drivers and a LCD voltage control circuit 11 1 1 Functions Functions of the LCD driver circuits are shown below Table 11 1 1 Functions of the LCD Static 1 2 Duty 1 3 Duty 1 4 Duty Segment Output Pins SEGO to SEG24 Common Output Pins COMO to COM3 Clock Source LCDCLK fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation LCDCLK LCD clock source which is selected in LCDCKO to LCDCK3 XI 2 Overview Chapter 11 LCD Functions 11 1 2 LCD Operation at Standby Mode At standby mode LCD driver operation may be restricted Table 11 1 2 shows the relation of the standby mode and the LCD operation Table 11 1 2 LCD Operation at Standby Mode LCD Clock wm a O LCD Operation is enabled A Keeping Display is enabled x LCD Operation is disabled Before getting into the CPU mode which the LCD operation is disabled switch the LCD off and switch the segment output to port 11 1 3 Maximum Number of Pixels Table 11 1 3 shows the maximum number of pixels that can be displayed Table 11 1 3 Maximum Number of Pixels that can be Displayed Maximum Number of Pixels 8 segment Segment x Common LCD Panel Segment Latch Bits Stati 25 25 x 1 COMO bit4 50 25 x 2 COMO
220. er is a register that holds the value loaded from a binary counter by capture trigger Capture trigger is generated by an input signal from an external interrupt pin Directly writing to the register by program is disable Timer 4 Input Capture Register TMAIC 7 6 5 4 3 2 1 0 TM4ICL TM4ICL7 TM4ICL6 TM4ICL5 TMAICL4 TM4ICL3 TM4ICL2 TM4ICLO At reset X XXX XXXX Figure 6 2 5 Timer 4 Input Capture Register Lower 8 bits TM4ICL 6 7 6 5 4 3 2 1 0 TM4ICH TM4ICH7 TM4ICHS TM4ICH4 TM4ICH3 TM4ICH2 TM4ICHO At reset X XX X XX XX Figure 6 2 6 Timer 4 Input Capture Register Upper 8 bits TM4ICH 03 67 VI 6 Control Registers Chapter 6 16 bit Timer 6 2 3 Timer Mode Registers This is a readable writable register that controls timer 4 Timer 4 Mode Register TM4MD 7 6 5 4 3 2 1 0 TM4MD TM4EN TMAICTS1 TM4ICTS0 TM4CK2 TM4CK1 TM4CKO atreset 0000 XXX TM4CK2 TM4CK1 TM4CKO Clock source 0 0 fosc fs 4 0 fs 16 1 TM4IO input 1 Synchronous TM4IO input TMAICTS1TM4ICTSO Capture trigger for timer 4 0 0 Disable input capture 1 IRQO 1 0 IRQ1 1 IRQ2 TM4PWM Timer 4 operation mode 0 16 bit timer normal
221. er pulse for remote control can be generated Operation of Remote Control Carrier Output Timer 3 Remote control carrier pulse is based on output signal of timer 3 Duty cycle is selected from 1 2 1 3 RMOUT P10 outputs remote control carrier output signal Base period set by timer Base timer output RMOUT 1 2 duty RMOUT 1 3 duty Figure 5 10 1 Duty Cycle of Remote Control Carrier Output Signal iCount Timing of Remote Control Carrier Output Timer 3 Base timer output Output ON RMOEN Output OFF 1 P1OMDO 0 RMOUT 1 3 duty A Figure 5 10 2 Count Timing of Remote Control Carrier Output Function Timer 3 A Even if the RMOEN flag is off when the carrier output is high the carrier waveform is held by the synchronizing circuit When the RMOEN flag is switched to on set the P10TCO flag of the P1OMD register to 1 When it is switched to off set it to 0 When the RMOEN flag is changed do not change the base cycle and its duty at the same time If they are changed at the same time the carrier wave form is not output properly V 34 Remote Control Carrier Output 5 10 2 Setup Example Chapter 5 8 bit Timers mRemote Control Carrier Output Setup Example Timer 3 Here is the setting example that the RMOUT pin outputs the 1 3 duty carrier pulse signal with H period of 36 7 kHz by using timer 3 The source clock of timer 3 is set to fosc at 8 M
222. erface 0 Block Diagram Figure 10 1 1 Chapter 10 Serial Interface 0 10 2 Control Registers 10 2 1 Registers Table 10 2 1 shows registers to control serial interface 0 Table 10 2 1 Serial Interface 0 Control Registers Register Address R W Function Page SCOMDO x O3F50 R W Serial interface 0 mode register 0 X 6 SCOMD 1 XO3F51 R W Serial interface 0 mode register 1 X 7 SCOMD2 x O3F52 R W Serial interface 0 mode register 2 X 8 0 SCOMD3 03 53 RAW Serial interface 0 mode register 3 X 9 SCOCTR X O3F54 R W Serial interface 0 control register X 10 SCOTRB x 03F55 R W Serial interface 0 transmission reception shift register 5 SCORXB x O3F56 Serial interface 0 reception data buffer X 5 R W Readable Writable Readable only X 4 Control Registers Chapter 10 Serial Interface 0 10 2 2 Data Buffer Registers Serial Interface 0 has a 8 bit shift register to shift the transmission and reception data and a 8 bit data buffer register for reception Serial Interface 0 Transmission Reception Shift Register SCOTRB 7 6 5 4 3 2 1 0 SCOTRB SCOTRB7 SCOTRB6 SCOTRBS SCOTRB4 SCOTRB3 SCOTRB2 SCOTRB1 SCOTRBO at reset XXX XX XXX Figure 10 2 1 Serial Interface 0 Transmission Reception Shift Register SCOTRB x 03F55 R W WSerial Interface 0 Received Data Buffer SCORXB 7 6 5 4 3 2 1 0 SCORXB sCoRXB7 SCORXB6 SCORXB5 SCORXB4 SCOR
223. errupt 1 Enable interrupt 4 TM4 interrupt level fi LVO Pipe weaned CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 8 Timer 4 Interrupt Control Register TM4ICR x O3FEF R W 24 Control Registers Chapter 3 Interrupts Timer 5 Interrupt Control Register TM5ICR The timer 5 interrupt control register TM5ICR controls interrupt level of timer 5 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 TM5LV1 TM5LV0 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 1 0 5 TM5 eS Lvi LVO At reset 0 0 0 0 TM5IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Interrupt enable flag 0 Disable interrupt 1 Enable interrupt 5 TMS interrupt level f Lvi ire cer ee tag The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 9 Timer 5 Interrupt Control Register 5 R W Control Registers 25 Chapter 3 Interrupts Time Base Interrupt Control Register
224. errupt 1 Enable interrupt AD AD Interrupt level fl Lvi vo ee The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 12 A D Conversion Interrupt Control Register ADICR R W 28 Control Registers Chapter 3 Interrupts 3 3 External Interrupts There are 4 external interrupts in this LSI The circuit external interrupt interface for the external interrupt input signal is built in between the external interrupt input pin and the interrupt controller block This external interrupt interface can manage to do with any kind of external interrupts 3 3 1 Overview Table 3 3 1 shows the list for functions which external interrupts 0 to 2 and 4 can be used Table 3 3 1 External Interrupt Functions External External External External interrupt 0 interrupt 1 interrupt 2 interrupt 4 IRQO IRQ1 IRQ2 IRQ4 External interrupt input pin P20 P21 P22 PAO PA7 Programmable active edge interrupt Y Y Y Key input interrupt Y PAO PA7 Noise filter built in zero cross detection Capture trigger for timer 4 Y Y Y Port 7 synchronous output _ 4 event External Interrupts 29 Chapter 3 Interrupts 3 3 2 Block Diagram Interrupt 0 Interface External Interrupt 1 Interface Block Diagram
225. errupt cycle change Set the IRWE flag of MEMCTR to enable the interrupt request flag to be rewritten This is necessary only when the interrupt request flag is changed by the software Rewrite the interrupt request flag xxxIR of the interrupt control register xxxICR Clear the IRWE flag so that interrupt request flag can not be rewritten by the software bp2 IRWE 0 6 Setthe interrupt level 6 Setthe interrupt level by the xxxLV1 0 flag of xxxICR the interrupt control register XxxICR bp7 6 xxxLV1 0 Set the IM1 0 flag of PSW when the interrupt PSW acceptance level of CPU should be changed bp5 4 IM1 0 7 Enable the interrupt 7 Setthe flag of the interrupt control xxxICR register xxxICR to enable the interrupt xxxlE 1 Set the MIE flag of PSW to enable maskable interrupts 14 Overview Chapter 3 Interrupts 3 2 Control Registers 3 2 1 Registers List Table 3 2 1 Interrupt Control Registers Register Address R W Functions Page NMICR 1 R W Non maskable interrupt control register Ill 16 IRQOICR xOSFE2 R W External interrupt 0 control register lll 17 IRQ1ICR R W External interrupt 1 control register Ill 18 IRQ2ICR XOS3FEB R W External interrupt 2 control register 19 IRQ4ICR XO3FED R W External interrupt 4 control register Ill 20 TM2ICR xOSFE6 R W Timer 2 interrupt cont
226. errupts Acceptance Operation When accepting an interrupt the MN101C48 series hardware saves the handy address register the return address from the program counter and the processor status word PSW to the stack and branches to the interrupt handler using the starting address in the vector table The following is the hardware processing sequence after interrupt acceptance 1 The stack pointer SP is updated SP 6 SP 2 The contents of the handy address register HA are saved to the stack Upper half of SP 5 Lower half of HA gt SP 4 x C 3 The contents of the program counter PC the return New SP gt PSW Lower address are saved to the stack after interrupt s PC bits 18 17 and 0 SP 3 aues 16 9 ds bits 16 9 amp reserved PC 18 17 Address PC bits 8 1 SP 1 4 The contents of the PSW are saved to the stack TE PSW gt SP Old SP Higher 5 interrupt level xxxLVn for the interrupt is before interrupt acceptance copied to the interrupt mask IMn in the PSW eo Interrupt level xxxLVn IMn 6 hardware branches to the address in the vector Figure 3 1 5 Stack Operation table during interrupt acceptance Winterrupt Return Operation An interrupt handler ends by restoring using the POP instruction and other means the contents of any registers used during processing and then execut
227. eset X00000 SCOTRI Transmission Reception interrupt request flag 0 Transmission interrupt request 1 Reception interrupt request SCOERE Error monitor 0 No error 1 Error SCOBRKF _ Break status receive monitor 0 Data Break 5 0 1 5 0 0 Clcok source 0 0 fs 2 1 fs 4 1 0 5 16 1 Timer 3 output SCOCKM 1 8 dividing of transfer clock selection 0 Do not divide by 8 1 Divide by 8 Clock source can be selected as an external clock by setting the SBTO pin to input mode At UART mode SCOCMD 1 the SCOCKM is fixed to 1 Figure 10 2 4 Serial Interface 0 Mode Register 1 SCOMD 1 x 03F51 R W Control Registers X 7 Chapter 10 Serial Interface 0 Serial Interface 0 Mode Register 2 SCOMD2 SCOMD2 X 8 5 4 3 2 1 0 ISCOBRKE SCOFM1 SCOFMO SCOPM1 SCOPMO SCONPE atreset 000 XXX SCONPE Parity enable 0 Enable parity bit 1 Disable parity bit A i ificati SCOPM1 SCOPMO dded bit speci ication Transmission Reception 0 0 Add 0 Check for 0 Add 1 Check for 1 0 Addodd parity Check for odd parity 1 Add even parity Check for even parity SCOFM1 SCOFMO Frame mode specification 0 0 7 data bits 1 stop bit 1 7 data bits 2 stop bits i 0 8 data bi
228. ew 1 1 Overview 1 1 1 Overview The MN101C series of 8 bit single chip microcontrollers incorporate multiple types of peripheral func tions This chip series is well suited for VCR MD TV CD LD printer telephone home automation pager air conditioner PPC remote control fax machine musical instrument and other applications The MN101C48 series brings to embedded microcomputer applications flexible optimized hardware configurations and a simple efficient instruction set The MN101C48C has an internal 16 KB of ROM and 512 bytes of RAM Peripheral functions include 4 external interrupts 8 internal interrupts including NMI 5 timer counters 1 set of serial interface A D converter watchdog timer synchronous output buzzer output and remote control output The configuration of this microcontroller is well suited for application such as a system controller in a VCR selection timer CD player MD or portable terminal With two oscillation systems max 20 MHz 32 kHz contained on the chip the system clock can be switched to high speed oscillation NORMAL mode or to low speed oscillation SLOW mode The system clock is generated by dividing the oscillation clock For example in case of NORMAL mode when the oscillation source fosc is 8 MHz minimum instruc tions execution time is for 250 ns and when fosc is 20 it is 100 ns 2 types of packages available 64 pin TQFP and 64 pin LQFP 1 1 2 Product Summary This ma
229. exer selects the segment output latched data in response to the signal from the timing control circuit and supplies it to the segment driver The segment driver converts the content of the segment output latch into the signals which is capable of driving the LCD based on the voltage supplied to LCD power supply then outputs the segment signal When the LCD is OFF Vss is output and the potential difference between the LCD electrodes becomes 0 V When the LCD is OFF VDD is output and the potential difference between the LCD elec trodes becomes 0 V At reset because the segments are also used as PORT pins they are set PORT input pins and become Hi z Therefore there could be some adverse effects such as blinks of the LCD display After reset set the segment output control register LCCTR again If the clock stops while LCD is displayed the LCD may be crushed by the pressure of DC voltage to LCD electrodes XI 10 LCD Control Registers 11 3 LCD Voltage Control Circuit Supply the voltage listed in Table 11 3 1 to the LCD power supply pins so that the LCD driver voltage will be supllied to the segment and common signals Examples of LCD power supply connections are shown in Figure 11 3 1 Table 11 3 1 LCD Power Supply Bias Method LCD Static 1 2 1 8 Power Supply 0 1 2 VLCD VLCD VLCD LCD panel driver voltage the maximum supply voltage to the LCD panel a Static
230. f Matsushita Electric Philippines Corporation 102 Laguna Boulevard Bo Don Jose Laguna Technopark Santa Rosa Laguna 4026 PHILIPPINES Tel 63 2 520 8615 Fax 63 2 520 8629 lndia Sales Office National Panasonic India Ltd NPI E Block 510 International Trade Tower Nehru Place New Delhi_110019 INDIA Tel 91 11 629 2870 91 11 629 2877 Sales Office P T MET amp Gobel M amp G JL Dewi Sartika Cawang 2 Jakarta 13630 INDONESIA Tel 62 21 801 5666 62 21 801 5675 China Sales Office Panasonic Industrial Shanghai Co Ltd PI SH Floor 6 Zhong Bao Mansion 166 East Road Lujian Zui PU Dong New District Shanghai 200120 CHINA Tel 86 21 5866 6114 86 21 5866 8000 Panasonic Industrial Tianjin Co Ltd Room No 1001 Tianjin International Building 75 Nanjin Road Tianjin 300050 CHINA Tel 86 22 2313 9771 86 22 2313 9770 Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ 7A 107 International Bussiness amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 CHINA Tel 86 755 359 8500 86 755 359 8516 Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11th Floor Great Eagle Center 23 Harbour Road Wanchai HONG KONG Tel 852 2529 7322 Fax 852 2865 3697 e Taiwan Sales Office Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6F 550 Sec 4 Chung Hsiao E RD Taipei 110 TAIWAN Tel 886 2 2757 1900 Fax 8
231. f VF NF 20 PC 4 PC BLT labe if VE NF 1 PC 5 d1 1 label H gt PC 5 2 3 1001 1110 dii 0 5 BLE label if VFNF ZF 1 PC 4 d7 labell H Pd 4 2 3 1000 1111 d7 2 if VF4NF ZF 0 PC 4 PC BLE label if VF NF ZF 1 PC 5 d1 label sH gt PG 5 2 3 1001 1111 lt 41 2 0 5 gt BGT label if VF NF ZF 0 PC 5 d7 label HPd 5 3 4 0010 0010 0001 d7 2 1 5 gt 1 d4sign extension 2 47 sign extension 3 11 sign extension XIII 22 Instruction Set MN101C SERIES INSTRUCTION SET Chapter 13 Appendices Size sion 1 2 3 4 5 6 7 8 9 10 11 Bec BGT label if VF NF ZF 0 PC 6 d1 label 6 3 4 0010 0011 0001 dii 3 if VFANF ZF 1 PC 6 9PC BHI label if CFIZF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0010 lt d7 2 if CFIZF 1 PC 53PC BHI label if CFIZF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0010 lt d11 if CFIZF 1 6 BLS label if CFIZF 1 PC 5 d7 label H gt PC 5 3 4 0010 0010 0011 d7 H 9 if CFIZF 0 PC 5PC BLS label if CFIZF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0011 lt d11 if CFIZF 0
232. f the SCOMDS register to 1 The SCOSBOS flag or the SCOSBIS flag should be set after all conditions are set After that at reception the communication is started by receiving start bit When a register except the SCOTRB is written rewritten set the SCOSBOS the SCOSBIS flag of the SCOMD3 register to 0 in advance When the TXD RXD pin are connected for communication with 1 channel the TXD pin inputs outputs serial data The port direction control register PODIR should be set for switching input output The RXD pin can be used as a general port When the serial interface port is enabled if the SCOCE1 0 flag of the SCOMDO register is switched the transfer bit count may be changed If it is used as half duplex UART serial interface setting the SCOCE1 0 flag fixed to 00 is recommended After reception has completed the TXD pin is H level If the frame mode is set by the SCOFM flag of the SCOMD2 register the SCOLNG2 0 flag of the SCOMDO register is automatically set After the transfer has completed the transfer bit count in the SCOLNG2 0 flag of the SCOMDO register is automatically set At UART reception set the SCOSBIS flag of the SCOMD3 register to 1 and set the SCOSBOS flag to 0 Setting both of flags to 1 is disabled Operation X 47 Chapter 11 LCD Function Chapter 11 LCD Functions 11 1 Overview This LSI contains an internal LCD driv
233. fter rewriting the TM5OC register On the timer 5 clock source selection either the time base timer output or the time base timer synchronous output is selected the clock setup of time base timer is necessary 8 bit Free running Timer 11 Chapter 7 Time Base Timer 8 bit Free running Timer 7 4 Time Base Timer 7 4 1 Operation Base Timer Time Base Timer The Interrupt is constantly generated Table 7 4 1 shows the interrupt generation cycle in combination with the clock source Table 7 4 1 Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle fosc x 1 28 12 8 us fosc 20 MHz fosc x 1 29 25 6 us fosc x 1 210 51 2 us fosc x 1 21 409 6 us fosc x 1 27 15 2 us fosc x 1 28 30 5 us fosc 8 39 MHz fosc x 1 2 61 0 us fosc x 1 279 122 0 us fosc x 1 21 976 4 us VII 12 Time Base Timer Chapter 7 Time Base Timer 8 bit Free running Timer WCount Timing of Timer Operation Time Base Timer The counter counts up with the selected clock source as a count clock 12 11 10 9 fosc fx 13 10 9 8 7 1 2 1 2 1 2 1 2 1 2 Figure 7 4 1 Count Timing of Timer Operation Time Base Timer When the selected interrupt cycle has passed the interrupt request flag of the time base interrupt control register TBICR is set to 1 An interrupt may be generated at switching of the clock source Enable interrupt after switch ing the clock
234. function of 16 bit timer is as follows Count clock TM4EN flag Compare register Binary counter Compare match signal Interrupt request flag Figure 6 3 1 Count Timing of Timer Operation Timer 4 A Set the value to the timer 4 compare register 4 B If the TM4EN flag is 1 the binary counter starts counting from x 0000 The counting is happened at the falling edge of the count clock But the binary counter doesn t count up at the first falling edge of the count clock C If the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock and the binary counter is cleared to x 0000 to restart counting up D Ifthe TM4EN flag is 0 the binary counter is stopped after 1 counting up 16 bit Timer Count VI 9 Chapter 6 16 bit Timer When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the interrupt is enabled the timer interrupt request flag should be cleared before timer operation is started If the set value of the compare register 4 is smaller than that of the binary counter TM4BC during the count operation the binary counter counts up to the overflow at first Even if the TM4EN flag
235. ge Latest version Diferrences between 1st Edition 2nd Printing and 2nd Edition 5th Printing Details of Changes Page Line Definition Previous Edition Ver 1 2 New Edition Ver 2 5 Cover Change 101 00 MN101C Warning Change If you have any inquiries or questions If you have any inquiries or questions about this about this book or our semiconductors book or our semiconductors please contact one please contact one of our sales offices of our sales offices listed at the back of this book listed at the back of this book or Matsushita Electronics Corporation s Sales Department About This Delete 1 Under development Manual All Chapters Change Spellings sentences All z Add LSI manual of MN101C series is added Chapters Setup examples of how to operate each functional block are also given Delete Description about MN101CP485 Table 1 2 1 1 1 Delete 1 Under development 1 6 13 Change LCD driver function 5 pins LCD driver function 4 pins 11 28 Add Transition to HALT modes _ Transition to STOP modes Title Change 101 00 SERIES INDTRUCTION SET MN101C SERIES INDTRUCTION SET Pages Instruction Add macro instructions Set the 6th Page Instruction Title Change 101 00 SERIES INDTRUCTION MAP MN101C SERIES INDTRUCTION Map the 1st Page Colophon Delete Matsushita Electronics Corporation
236. he SCOMD3 register to 1 and set the SCOSBIS flag to 0 Setting both of flags to 1 is disabled X 44 Operation Reception Setup The setup example at UART reception with serial interface 0 is shown Table 10 3 23 shows the conditions at reception Chapter 10 Serial Interface 0 Table 10 3 23 UART Interface Transmission Reception Setup Setup item set to TXD RXD pi n connected with 1 channel Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source timer 3 TXD pin type N ch open drain Pull up resistor of TXD pin added Parity bit add check O add check Serial 0 interface interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the UART communication SCOCTR x 3F54 bp6 SCOCMD 1 Select the first bit to be transferred SCOMDO x 3F50 bp4 SCODIR Select the start condition SCOMDO x 3F50 bp3 SCOSTE Select the clock source SCOMD1 x 3F51 bp4 3 SCOCK1 0 Select the parity bit SCOMD2 x 3F52 SCONPE bp2 1 SCOPM1 0 Specify the frame mode SCOMD2 x 3F52 bp4 3 SCOFM1 0 Select the reception mode SCOMDS x 3F53 bp5 SCOIOM 0 0 11 0 00 11 1 1 Set the SCOCMD flag of the SCOCTR register to 1 to select the UART communication Select MSB a
237. he last step of its programming How to Clear Watchdog Timer The upper 2 bits of the watchdog timer can be cleared by setting the WDEN flag of the watchdog timer control register WDCTR to The upper 2 bits of the watchdog timer are cleared when the WDEN flag of the watchdog timer control register WDCTR is set to 0 Therefore depending on the clear timing the watchdog timer may be reset at 1 4 x watchdog timer frequency If the WDEN flag is to be repeatedly cleared and set at regular intervals those operations should be performed within 1 4 of the watchdog timer frequency 4 Operation Chapter 8 Watchdog Timer mWatchdog Timer Period The watchdog timer period is decided by the system clock fs and ROM option t Chapter 1 1 6 1 Rom option If the watchdog timer is not cleared till the set period of watchdog timer that is regarded as an error and the watchdog interrupt WDIRQ of the non maskable interrupt NMI is generated Table 8 3 1 Watchdog Timer Period WDSEL2 WDSEL1 Watchdog timer period 0 0 218 x system clock 0 1 218 x system clock 1 X 220 x system clock System clock is decided by the CPU mode control register CPUM The watchdog timer period is generally decided from the execution time for main routine of program That should be set the longer period than the value of the execution time for main routine divided by natural number 1 2 And inser
238. he timer interrupt flag TMnIRQ is generated when binary counter and compare register are matched The latched data on port 7 is output from the port 7 in synchronization with the rising edge of the TMnIRQ About the setting of each timer operation q Chapter 5 8 bit timers Chapter 6 16 bit timers Timer count clock ENS PM n Timer compare i H d register i Binary counter N joo 4 N 1 X 00 4N NX FN Port 7 output X 7 X Y latched data Interrupt request flag Port 7 output X Y Z Figure 4 10 3 Synchronous Output Timing by Event Generation Timers 2 and 4 IV 46 Synchronous Output Port 7 4 10 4 Setup Example Chapter 4 I O Ports A setup example of the port 7 synchronous output by the external interrupt 2 IRQ2 is shown as follows As it is operated the initial output data of port 7 is 55 the synchronous output data is AA and the rising edge of the IRQ2 is selected at the synchronous event An example setup procedure with description of each step is shown below Setup Procedure Description Select the synchronous output event FLOAT2 x 3F4C bp1 0 B7SYEVS1 0 00 Specify the interrupt edge IRQ2ICR x 3FEB bp5 REDG2 1 Set the initial output data P7OUT x 3F17 bp7 0 P7OUT7 0 x 55 P7DIR x 3F37 bp7 0 P7DIR7 0 xFF Set the synchronous output pin SYSM
239. hen set the SCOSBOS flag to 1 Do not change both of these flags at the same time X 14 Operation Chapter 10 Serial Interface 0 iTranfer Bit Count and First Transfer Bit On transmission when the transfer bit is 1 bit to 7 bits the data storing method to the transmission reception shift register SCOTRB is different depending on the first transfer bit selection At MSB first use the upper bits of SCOTRB When there are 6 bits to be transferred as shown on figure 10 3 1 1 if data A to F are stored to bp2 to bp7 of SCOTRB the transmission is started from F to A At LSB first use the lower bits on the program When there are 6 bits to be transferred as shown on figure 10 3 1 2 if data A to F are stored to bpO to bp5 on the program the transmission is started from A to F because their order is changed in the SWAP circuit 7 6 5 4 3 2 1 0 SCOTRB F E D C B A Figure 10 3 1 1 Transfer Bit Count and First Transfer Bit starting with MSB 7 6 5 4 3 2 1 0 Setting on program F E D C B A SCOTRB A B C D E F Figure 10 3 1 2 Transfer Bit Count and First Transfer Bit starting with LSB Received Data Buffer The received data buffer SCORXB is the sub buffer that pushed the received data in the internal shift register After the communication complete interrupt SCOIRQ is generated data stored in the transmis sion reception shift
240. hronous output value stored register is output from pins If the synchronous output event that is set by the pin control register 2 FLOAT2 is never generated the synchronous output value stored register holds the same value when the synchronous output event is enabled Store the value that should be output from pin after the synchronous output event is generated to the port 7 output register PZOUT Once the synchronous output event that is set by the pin control register 2 FLOAT2 is generated the data of the synchronous output value stored register is switched to the data of the port 7 output register P7OUT and the output value from pin is changed When the port 7 synchronous output is disabled the value of the synchronous output value stored register is not always same to the value of the port 7 output register P7OUT This is because the pin output may be changed at switching from general output to synchro nous output Synchronous Output Port 7 IV 45 Chapter 4 I O Ports WPort 7 Synchronous Output External interrupt 2 IRQ2 The synchronous output timing when the synchronous output event is set at the falling edge of the external interrupt 2 is shown below The latched data on port 7 is output in synchronization with the falling edge of the IRQ2 latched data External interrupt IRQ2 Figure 4 10 2 Synchronous Output Timing by Event Generation IRQ2 7 Synchronous Output Timers 2 and 4 T
241. hronous Output Timer 4 TM4EN flag Compare a GS E AX register i i Port 7 output latched data Binary 00 oooofooo1 EN 0000 0001 0000 0001 4 N 1 counter match signal Interrupt request flag Port 7 output data Figure 6 7 1 Count Timing of Synchronous Output Timer 4 The port 7 latched data is output from the output pin in synchronization with the interrupt request generation by the match of binary counter and compare register Even if the port 7 is used as a synchronous output pin the setting of the P7DIR register is necessary VI 24 16 bit Timer Synchronous Output 6 7 2 Setup Example Synchronous Output Setup Example Timer 4 Chapter 6 16 bit Timer Setup example that latched data of port 7 is output constantly 100 us by using timer 4 from the synchro nous output pin is shown below The clock source of timer 4 is selected fs 4 at fosc 8 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM4MD x 3F84 bp6 TM4EN 20 2 Select the synchronous output event FLOAT2 4 bp1 0 P7SYEVS2 1 01 3 Setthe synchronous output pin SYSMD x 3F1F X FF P7DIR x 3F37 X FF 4 Select the count clock source TM4MD x 3F84 bp2 0 TM4CK2 0 001 b Select the normal timer operation TMAMD x 3F84 bp5 TM4PWM 0 6 Set the synchronous output ev
242. i bp F DQ z Write CK F Read Res PAINO 7 Reset PAIMDO 7 1 Write Read Figure 4 9 4 Block Diagram to PA7 Chapter 4 Ports 4 10 Synchronous Output Port 7 Port 7 has the synchronous output function that outputs the any set data to pins in synchronization with the generation of the specified event Synchronous event is selected from the external interrupt 2 P22 IRQ2 timer 2 interrupt or timer 4 interrupt signal 4 10 1 Block Diagram Port output data Timer 1 interrupt Timer 2 interrupt Timer 4 interrupt External interrupt 2 Pin control register FLOAT bp1 bpO 0 P7OUTO 7 1 U Output data DQ D Q X Write 7 output value store register Synchronous output event Synchronous output control Figure 4 10 1 Reset k SYSMD0 7 DQ e Write 4 Synchronous Output Control Block Diagram a Set the bp1 0of the pin control register 2 FLOAT2 to the value except 11 LI Synchronous Output Port 7 IV 43 Chapter 4 I O Ports 4 10 2 Registers Table 4 10 1 shows the synchronous output control registers of port 7 Table 4 10 1 Synchronous Output Control Registers Register Address R W Function Page FLOAT2 4 R W control register 2 37 SYSMD X 03F1F R
243. in Pull up resistors can be selected by the POPLU register Set this pin to the input mode by the PODIR register and to the serial input mode by the serial 0 mode register 3 SCOMD3 This can be used as normal pin when the serial interface is not used TM2IO 35 36 12 P13 Timer VO pins Event counter clock input pins timer output and PWM signal output pins for 8 bit timers 2 to 3 To use these pins as event clock inputs configure them as inputs by the P1DIR register When the pins are used as inputs pull up resistors can be specified by the P1PLU register For timer output PWM signal output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register When not used for timer these be used as normal pins RMOUT 30 vO P10 Remote control transmission signal output pin Output pin for remote control transmission signal with a carrier signal For remote control carrier output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register This can be used as a normal VO pin when remote control is not used BUZZER 31 Output P06 NDK Buzzer output Piezoelectric buzzer driver pin The driving frequency can be selected by the DLYCTR register Select output mode by the PODIR register and select PO6 buzzer outp
244. ine the optimum value after a sample product is evaluated by the oscillator manufacturer because the optimum value of the external capacitors C11 C12 C21 and C22 differ on the oscillator which is used Especially when the micro computer is used on low voltage you must implement enough matching evaluation with the oscillator Electrical Characteristics I 21 Chapter 1 Overview is for EPROM vers 40 to 85 Ta 20 to 70 Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX External clock input 1 OSC1 OSC2 is unconnected 20 frequency fosc 1 0 20 0 MHz 21 High level pulse width 22 5 gt 5 Fig 1 5 3 22 Low level pulse width twit 22 5 ns 23 Rising time turi 0 5 0 Fig 1 5 3 24 time twit 0 5 0 External clock input 2 XI XO is unconnected 27 Clock frequency fx 32 768 100 kHz 28 High level pulse width 45 5 Fig 1 5 4 us 28 Low level pulse width twi2 45 30 Rising time twr 0 20 Fig 1 5 4 ns 31 Falling time twi2 0 20 The clock duty rate should be 45 to 55 twh2 twl2 p twh1 Y twit lt gt lt gt gt 5 in gt lt ie tiz tose in gt Figure 1 5 3 OSC1 Timing Chart Figure 1 5 4 XI Timing Chart 1 22 Electrical Characteristics Chapter 1
245. ing dummy data to the transmission reception shift register SCxTRB But by the above setting this serial interface 0 cannot output the master clock so that the reception is not started Therefore the following setup by the software is necessary lt By software gt When synchronous serial interface 0 is used for master clock reception it is necessary to set the SCOSBTS flag of the serial interface 0 mode register SCOMD3 to 1 then set the SCOSBIS flag to 1 and set the SCOSBOS flag to 1 At last the master clock is output by the writing dummy data to the transmission reception shift register SCOTRB then the reception is started Program example for master clock reception by the synchronous serial interface 0 SCOSBTS lt 1 SCOSBIS SCOSBOS 1 1 SCOTRB lt x XX dummy data is written reception is started The SBOO pin cannot be used as general output port by setting the SCOSBOS flag to 1 But it can be used as general input port by setting the bpO of the port 0 direction control register PODIR to 0 Serial data communication of serial interface 0 can be available by setting the SCOSBIS flag or the SCOSBOS flag of the SCOMDS register to 1 The SCOSBIS flag or the SCOSBOS flag should be set to 1 after all conditions are set On the master communication of the clock synchronous set the SCOSBTS flag to 1 before the SCOSBOS flag or the SCOSBIS flag of the SCOMDS register is set to
246. ing the return from interrupt RTI instruction to return to the point at which execution was interrupted The following is the processing sequence after the RTI instruction 1 The contents of the PSW are restored from the stack SP 2 The contents of the program counter PC the return address are restored from the stack SP 1 to SP 3 3 The contents of the handy address register HA are restored from the stack SP 4 SP 5 4 The stack pointer is updated SP 6 SP 5 Execution branches to the address in the program counter The handy address register is an internal register used by the handy addressing function The hardware saves its contents to the stack to prevent the interrupt from interfering with operation of the function Registers such as data register or address register are not saved so that PUSH instruction should be used to save data register or address register onto the stack if necessary 1 The address bp6 to 2 when program counter saved to the stack are reserved Do not change by program 10 Overview Chapter 3 Interrupts iMaskable Interrupt Figure 3 1 6 shows the processing flow when a second interrupt with a lower priority level xxxLV1 xxxLVO 10 arrives during the processing of one with a higher priority level xxxLV1 xxxLV0 00 IMO 1 00 Main program Set MIE IM1 0 11 Interrupt 1 generated z Accepted becau
247. input register P7IN 03 27 7 6 5 4 3 2 1 0 P7DIR P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIRO Atreset 00000000 P7DIR mode selection 0 Input mode 1 Output mode Port 7 direction control register P7DIR 03 37 R W 7 6 5 4 3 2 1 0 P7PLUD P7PLUD7 supe P7PLUD4 P7PLUD3 P7PLUD2 P7PLUD1 P7PLUDO Atreset 00000000 Pull up or Pull down P7PLUD resistor selection 0 No pull up or pull down resistor 1 Pull up or Pull down resistor Port 7 pull up pull down resistor control register P7PLUD x 03F 47 R W Figure 4 7 1 7 Registers 1 4 Pot7 IV 29 Chapter 4 Ports 7 6 5 4 3 2 1 0 EXADV EXADV3 EXADV2 EXADV1 gt At reset 000 EXADV1 P73 P70 11 A8 address output during memory expansion mode General port A11 to A8 address output EXADV2 P77 P74 A15 A12 address output during memory expansion mode General port A15 to A12 address output EXADV3 P53 A16 address output during memory expansion mode General port A16 address output Expansion address output control register EXADV x OSFOE R W Figure 4 7 2 Port 7 Registers 2 4 In memory expansion mode unused address pin can be used as general
248. ins 64 pin TQFP 10 mm square 0 5 mm pitch code name TQFP64 P 1010B 64 pin LQFP 14 mm square 0 8 mm pitch code name LQFP64 P 1414 Hardware Functions I 7 Chapter 1 Overview Pin Description 1 3 Pin Configuration 1 3 1 lt 555555 4 V o OocoooOoocOO0uUlysr oogomomoooooo0zszzaz cc r SS s TRO SE ESS SSS rGidxoqcoooq coq cos O C CO cO 1O 10 10 QI QI QI OMRON S 544 00 5 8 91995 0 lt 6r 10 5 6 7 1995 14 lt 0 5 01 1995 lt LG OGQS LILV CELO3S 4d vyOGdS cIV EELO3S VZd lt S0QS 1V 0L93S S d 4 vG 90 5 6045 9 4 lt 1045 6 1 8995 lt 95 14 2995 8 ZS 9q0 9938 98d lt 8S GQ SDAS S8d 46 966 vd vDAS v8d lt 09 q eoas esad 19 cq eoas e8ad 4 Pi z9 11 1935 18 4 0 0 0995 08 lt v9 101 485 487 LCD 64PIN SSSSslU09soo0s xola 57a OOOO OO 5 S lt gt ELd OIEWL cLEd OIcIA L Old LNOWY Z d LSHN 90d H3ZZf18 MON 0 0195 0 0195 00d 008S QX L ZNd LNV Z3AM 9Vd 9NV 9HAM SVd SNV 9 3AM VVd VNV V3AM EVd ENV EAAM OV d cNV CHAM LVd ENV LA3M
249. interrupt request flag after the switching of the interrupt edge t Chapter 3 3 1 4 Interrupt flag setup The external interrupt pin is recommended to be pull up in advance External Interrupts 37 Chapter 3 Interrupts 3 3 5 Key Input Interrupt Input Interrupt External interrupt 4 This LSI can set port 4 pin PAO PA7 by 2 bits to key input pin Key input interrupt can generate an interrupt at the falling edge if at least 1 key input pin outputs low level Key input pin should be pull up in advance Set each bit of the port input control register PAIMD associated with the key input pins to 0 in advance When key input interrupt is used set the IRQ4SEL flag of the key interrupt control register P4IMD to 1 register IRQ4ICR to 0 falling edge a When port 4 key input interrupt is used set the REDGA flag of the external interrupt 4 control 38 External Interrupts Chapter 3 Interrupts Input Interrupt Setup Example External interrupt 4 After PAO to PAS of port A are set to key input pins and key is input low level the external interrupt 4 IRQ4 is generated An example setup procedure with a description of each step is shown below Setup Procedure Description Set the key input pin to input PAIMD bp3 0 PAIMD3 0 0000 Set the pull up resistance PAPLUD x 3F4A bp3
250. ion Equip name Vendor Pecker30 Aval Data Do not run ID check 2900 Data VO ChipLab Data VO The above table is based on the standard samples EPROM Version XIII 7 Chapter 13 Appendices 13 1 6 Cautions on Operation of ROM Writer Cautions on Handling the ROM writer 1 The Ver programming voltage for the EPROM versions is 12 5 V Programming with a 21 V ROM writer can lead to damage The ROM writer specifications must match those for standard 256 k bit EPROM Ver 12 5 tow 1 0 ms 2 Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter Faulty connections can damage the chip 3 After clearing all memory of the ROM writer load the program to the ROM writer 4 After confirming the device type write the loaded program in 3 to this LSI address from x 4000 to the final address of the internal ROM 5 There is the same address for ROM option setting even on EPROM version 6 Chapter 13 13 1 8 Option Bit The internal ROM space of this LSI is from x 4000 Chapter 2 2 2 Memory Space This writer has no internal ID codes of Silicon Signature and Intelligent Identifier of the 1 auto device selection command of ROM writer If the auto device selection command is to be executed for this writer the device is likely damaged Therefore never use this command mWhen the w
251. ion Address R W Register Name Page LCMD R W LCD mode control register 6 LCCTR xO3FCC R W Segment output control register 8 R W Readable Writable Segment output latch is located at addresses x 03FBD to x OSFC9 SEGO to SEG24 t Chapter 11 11 2 4 Segment Output Latch LCD Control Registers 5 Chapter 11 LCD Functions 11 2 2 LCD Mode Control Register LCMD The LCD mode control register LCMD is readable writable register that specifies LCD display ON OFF the display duty and the LCD clock Mode Control Register LCMD 7 6 5 4 3 2 1 0 LCMD LCDEN ReservedL CODTY1 LCODTYO LCDCK3 LCDCK2 LCDCK1 LCDCKO at reset 00000000 LCDCK3 LCDCK2 LCDCK1 Lcpcko 6D clock source selection 0 0 fosc 2 1 fosc 2 1 0 fosc 2 1 fosc 2 0 215 1 1 fosc 216 0 fosc 2 1 1 fosc 2 0 fx 28 0 1 X 1 fx 2 0 fx 28 1 fx 2 LCODTY1 LCODTY0 LCD display duty selection 0 0 1 4 duty 1 1 3 duty 1 0 1 2 duty 1 Static Reserved Always set to 0 LCDEN Enable disable LCD driver circuit 0 Stop turn off LCD 1 Start illuminate LCD Figure 11 2 1 LCD Mode Control Register LCMD x 3FCD R W 6 LCD Control Registers Chapter 11 LCD Functions Setup of the LCD fr
252. ister TM2ICR The timer 2 interrupt control register TM2ICR controls interrupt level of timer 2 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 TM2LV1 TM2LV0 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 TM2 TM2 _ _ _ TM2ICR LV1 LVO rate TM2IR At reset 00 0 0 TM2IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated 2 Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt level fla Lvi LVO P 9 The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 9 Timer 2 Interrupt Control Register TM2ICR x 03FE6 R W 22 Control Registers Chapter 3 Interrupts Timer Interrupt Control Register The timer 3 interrupt control register TM3ICR controls interrupt level of timer 3 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 TM3LV1 TM3LV0 1 the interrupt of its vector is disabled regardless of
253. istor is added P27 is always added pull up resistor At reset pull up resistors are disabled high impedance output for P20 to P22 ilSpecial Function Pin Setup P20 to P22 are used as external interrupt pins as well P21 is used as an input pin for external interrupt and AC zero cross To read data of AC zero cross set the bp2 of the pin control register FLOAT1 to 1 and read the value of the port 2 input register P2IN IV 14 Port2 Chapter 4 Ports 4 4 2 Registers 7 6 5 4 3 2 1 0 2 P20UT7 1 2 Output data 0 Low Vss level 1 High level Port 2 output register P2OUT x 03F12 R W 7 6 5 4 3 2 1 0 2 2 2 P2IN1 P2INO At reset XXX P2IN Input data 0 Pin is Low Vss level 1 Pin is High VDD level Port 2 input register P2IN x OSF22 7 6 5 4 3 2 1 0 P2PLU P2PLU2 P2PLU1 At reset 000 P2PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 2 pull up resistor control register P2PLU 03 42 R W Figure 4 4 1 Port 2 Registers Pot2 IV 15 Chapter 4 Ports 4 4 3 Block Diagram Nes Rese Pull up resistor control Dd P2PLUO 2 gt Write
254. itenupt Extemalpi input nhtemalperphenl function Generated operation D tect nputto CPU cow hputto CPU cor from nonm askabb mtenupt contolregister hout nte nupt request Evelset n ntenupt Bvelfag amp xxLVn of maskabb mtenuptcontol register amp xC to CPU cor Acceptance by the itenupt contolofthe register xxC A tio Al ts AW ts cceptoperaton ays accep ays accep aud PSW M cycbs 12 12 12 untilacceptance Vales ofthe ntenupt Evelfag Alfags The intenuptm ask Evel sett the itenupt fag nPSW 35 mask Evel n asking allintenupt E to 0 to 00 requests w ih the sam e orthe bwerprorty Overview 3 Chapter 3 Interrupts 3 1 2 II 4 Block Diagram Overview IRQLVL 2 0 IRQNM1 gt Interrupt CPU core Vector 1 1 IRQOICR Figure 3 1 1 WDOG Peripheral function yo xxxLV Interrupt Level Interrupt Enable xxxlR Interrupt Request Peripheral function yo XxxLV Interrupt Leve
255. its and temporarily stored in the 2 byte instruction queue Transfer is made in 1 byte or half byte units from the instruction queue to the instruction register to be decoded by the instruction decoder 7 0 eee Memory 1 p 5 0 1 byte or a half byte Instruction queue Instruction register i i Instruction decoder Instruction decoding CPU control signals Figure 2 1 2 Instruction Execution Controller Configuration Overview 5 Chapter 2 CPU Basics 2 1 4 Pipeline Process Pipeline process means that reading and decoding are executed at the same time on different instruc tions then instructions are executed without stopping Pipeline process makes instruction execution continual and speedy This process is executed with instruction queue and instruction decoder Instruction queue is buffer that fetches the second instruction in advance That is controlled to fetch the next instruction when instruction queue is empty at each cycle on execution At the last cycle of instruc tion execution the first word operation code of executed instruction is stored to instruction register At that time the next operand or operation code is fetched to instruction queue so that the next instruction can be executed immediately even if register direct da or immediate imm is needed at the first cycle of the next instruction execution But on some other instruction such as branch instruction
256. iving pin 3 SEG24 SEG24 LCD segment output 24 P60 AO SEG23 in out PeDIRO P6PLUO 0 Address output SEG23 LCD segment output 23 P61 Al SEG22 in out PeDIR1 PePLU1 1 Address output bp1 SEG22 LCD segment output 22 P62 A2 SEG21 in out PeDIR2 PePLU2 A2 Address output bp2 SEG21 LCD segment output 21 P63 SEG20 in out PeDIR3 P6PLU3 Address output bp3 SEG20 LCD segment output 20 P64 4 SEG19 in out P6DIR4 P6PLU4 4 Address output 6 4 SEG19 LCD segment output 19 P65 SEG18 in out P6DIR5 5 A5 Address output 0 5 SEG18 LCD segment output 18 P66 AG SEG17 in out P6DIR6 P6PLU6 6 Address output bp6 SEG17 LCD segment output 17 P67 A7 SEG16 in out PeDIR7 P6PLU7 7 Address output bp7 SEG16 LCD segment output 16 Pin Description 1 9 Chapter 1 Overview Table 1 3 2 Pin Specification 2 2 Pins Special Functions VO a ee Functions Description P70 A8 SEG15 in out P7DIRO P7PLUDO A8 Address output 0 8 SEG15 LCD segment output 15 SDOO SDOO Synchronous output 0 P71 A9 SEG14 in out P7DIR1 P7PLUD 1 A9 Address output bp9 SEG14 LCD segment output 14 001 SDO1 Synchronous output 1 P72 A10 SEG13 in out P7DIR2 P7PLUD2 10 Address output bp10 SEG13 LCD segment output 13 002 SDO2 Synchronous output 2 P73 11 SEG12 in out P7DIR3 P7PLUD3 A11 Address output bp11 SEG12
257. k CPU S oscillator oscillator MN101C ROM RAM T 16 KB 512 bytes E o 8 bit Timer 2 External Interrupt o m 2 a 8 bit Timer 3 5 Serial Interface 0 16 bit Timer 4 Time Base Timer 5 v A D converter Watch Dog Timer co PortA LCD mima I lt lt lt lt lt lt 22222989 gt gt gt lt lt lt lt lt lt lt lt gt gt gt gt gt gt gt gt Figure 1 4 1 Block Diagram 1 5 1 1 Chapter 1 Overview Electrical Characteristics This LSI user s manual describes the standard specification System clock fs is 1 2 of high speed oscillation at NOR MAL mode or 1 4 of low speed oscillation at SLOW mode Please ask our sales offices for its own product specifica tions Model Contents MN101C468 series Structure CMOS integrated circuit Application General purpose Function 8 bit single chip microcontroller Absolute Maximum Ratings 1 Power supply voltage Input clamp current SENS Input pin voltage Output pin voltage E 0 3 to 7 0 0 3 to VDD 0 3 0 3 to VDD 0 3 VO pin voltage 0 3 to VDD 0 3 Peak output current Average output current 1 All pins avg All pins total average output Operating ambient temperature Topr Other than port 5 loL2 avg IOL5 avg avg
258. k Diagram Serial Interface 0 Block Diagram L L AS809S L 0112008 82006 030005 132008 7 131005 315005 080005 5 29 1008 gt 1788006 33005 19 109 gt 343005 2 0DN100S o 1109 H1000S oawoos LaWwoos Y ndyo 13w11 x 91 5 Wa len W r 2 5 101 U09 Y 380 7 ry X el i 005 ilg lt lt 204 0185 A 1 AA pappe yoayo 04002 uoissiusueJ 0 02 4049899 L 1 ra uonipuoo 04002 10409291 yeaug Y Y Y A x 0 6 UOISSIUISUEJ oog axL 008S ue YUS b p A Pa 1055 g 2 eyng luojoajap 19 0015 5 g 05 33H800S 01026 114025 NOSSOOS OW400S 6 1285095 1909 as 5085005 OWd00S 5195095 01845026 8 4 015185026 20 0095 59 1055 X 3 Overview Serial Int
259. l interrupt The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 3 External Interrupt 1 Control Register IRQ1ICR x O3FES R W Control Registers III 19 Chapter 3 Interrupts External Interrupt 2 Control Register IRQ2ICR The external interrupt 2 control register IRQ2ICR controls interrupt level of external interrupt 2 active edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is set to level IRQ2LVO IRQ2LV1 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag 7 6 5 4 3 2 1 0 IRQ2 IRQ2 _ MT IRQ2ICR Wr RR REDG2 IRQ2IE RQ2IR At reset 000 0 0 IRQ2IR External interrupt request flag 0 No interrupt request Interrupt request generated IRQ2IE External interrupt enable flag 0 Disable interrupt Enable interrupt REDG2 External interrupt active edge flag 0 Falling edge 1 Rising edge IRQ2 IRG Lyo teut level flag for external interrupt The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 4 External I
260. le interrupt can be set by software per each interrupt group There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority For example if a vector 3 set to level 1 and a vector 4 set to level 2 request interrupts simultaneously vector 3 will be accepted Vector 1 Non maskable interrupt Priority Interrupt vector No 1 Vector 1 Level 0 Vectors 2 5 6 2 Vector 2 3 Vector 5 Interrupt level Level 1 Vector 3 4 Vector 6 setting range 5 Vector 3 Level 2 Vectors 4 8 6 Vector 4 7 Vector 8 Figure 3 1 3 Interrupt Priority Outline Overview 7 Chapter 3 Interrupts lDetermination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance 1 The interrupt request flag xxxIR the corresponding external interrupt control register IRQnICR or internal interrupt control register xxxICR is set to 1 2 Aninterrupt request is input to the CPU If the interrupt enable flag in the same register is 1 The interrupt level IL is set for each interrupt The interrupt level IL is input to the CPU The interrupt request is accepted If IL has higher priority than IM and MIE is 1 After the interrupt is accepted the hardware resets the interrupt request flag xxxIR in the interrupt control register xxxICR to 0 aana a A aS
261. lection P7RDWN 0 Pull up resistor Pull down resistor Port A pull up pull down PARDWN resistor selection 0 Pull up resistor 1 Pull down resistor 211 P21 input mode selection 0 Schmitt trigger input 1 ACZ input Figure 3 3 5 Pin Control Register 1 FLOAT1 x 03F4B R W External Interrupts III 35 Chapter 3 Interrupts Port 4 Key Interrupt Control Register P4IMD The port 4 key interrupt control register P4IMD selects if key interrupt is approved and if external interrupt IRQ4 is approved Also this register selects by 2 bits which pin on port 4 approved key interrupt 7 6 5 4 3 2 1 0 IRQ4SEL PAKYENAPAKYEN3 Atreset 0 0000 P41 P40 key interrupt selection 0 disable 1 enable PAKYEN2 P43 42 key interrupt selection 0 disable 1 enable P45 44 key interrupt selection 0 disable 1 enable PAKYEN4 P47 P46 key interrupt selection 0 disable 1 enable IRQ4SEL IRQ4 interrupt source selection 0 disable 1 Port 4 key interrupt Figure 3 3 6 Port 4 Key Interrupt Control Register P4IMD R W 36 External Interrupts Chapter 3 Interrupts 3 3 4 Programmable Active Edge Interrupt Programmable Active Edge Interrupts External interrupts 0 to 2
262. ll up pull down resistor control register 39 P4IMD x O3F3C R W Key interrupt control register IV 41 EXADV x O3FOE R W Expansion address output control register IV 19 30 SYSMD x O3F1F R W Synchronous output control register IV 31 nus FLOAT1 4 R W Pin control register 1 IV 31 40 FLOAT2 4 R W control register 2 IV 31 LCCTR R W Segment output control register IV 20 25 32 36 R W Readable Writable R Readable only Overview 5 Chapter 4 Ports 4 2 Porto 4 2 1 Description Port Setup Each bit of the port 0 control I O direction register PODIR can be set individually to set pins as input or output The control flag of the port 0 direction control register PODIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 0 direction control register PODIR to and read the value of the port 0 input register POIN To output data to pin set the control flag of the port 0 direction control register PODIR to 1 and write the value of the port 0 output register POOUT Each pin can be set individually if pull up resistor is added or not by the port 0 pull up resistor control register POPLU Set the control flag of the port 0 pull up resistor control register POPLU to 1 to add pull up resistor At reset the input mode is selected and pull up resistor
263. ll up pin in advance 1 When key input interrupt is used set the REDG4 flag of the external input 4 control register IRQ4ICR to 0 falling edge IV 38 PortA Chapter 4 Ports 4 9 2 Registers 7 6 5 4 3 2 1 0 PAIN PAIN7 PAING PAINS PAINS PAIN2 PAIN1 Atreset XXX XXXXX PAIN Input data 0 Pin is Low Vss level Pin is High level Port A input register PAIN x O3F2A 7 6 5 4 3 2 1 0 PAIMD PAIMD7 PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMDO Atreset 00000000 PAIMD port analog n input pin selection 0 port 1 Analog n input pin Port A input control register PAIMD R W 7 6 5 4 3 2 1 0 PAPLUD PAPLUD7 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO At 00000000 Pull up or Pull down PAPLUD resistor selection 0 No pull up or pull down resistor 1 Pull up or Pull down resistor Port A pull up pull down resistor control register PAPLUD R W Figure 4 9 1 A Registers 1 3 PotA IV 39 Chapter 4 I O Ports FLOAT1 211 PARDWN P7RDWN Atreset IV 40 Port A P7RDWN Port 7 pull up pull down resistor selection 0 Pull up re
264. ll up resistor selection 4 8 2 Registers 7 6 5 4 3 2 1 0 _ P80UT7 P8OUT6 P8OUT5 PSOUT4 PBOUT3 P8OUT2 PSOUT1 PBOUTO Atreset 00000000 P8OUT Output data 0 1 Port 8 output register PBOUT x 03F18 R W 7 6 5 4 3 2 1 0 P8IN P8IN7 P8IN6 5 P8IN4 2 P8INo Atreset P8IN Input data 0 1 Port 8 input register P8IN x O3F28 7 6 5 4 3 2 1 0 P8DIR 80 7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 PSDIR2 PSDIR1 P8DIRO Atreset 00000000 P8DIR 0 Input mode Port 8 direction control register P8DIR x 03F38 R W 7 6 5 4 3 2 1 0 P8PLU P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLUO At reset 00000000 P8PLU 0 No pull up resistor 1 Pull up resistor Port 8 pull up resistor control register P8PLU x 03F48 R W Figure 4 9 1 Port 8 Registers 1 2 Port 8 IV 35 Chapter 4 I O Ports 6 5 4 3 2 1 0 LCCTR x IV 36 8 SEGSEL6 SEGSEL5 SEGSEL4 SEGSEL3 SEGSEL2 SEGSEL1 At reset 0000000 SEG24 SEGSELO Port P53 selection 0 Port P53 1 SEG24 5 20 to 23 SEGSEL1 Port P60 to P63 selection 0 Port P60 to P63 1 SEG20 to 23 SEG16 to 19 SEGSEL2 Port P64 to P67 selection 0 Port P64 to P67 SEG16 to 19 SEG12 to 15 SE
265. lly masked Only interrupts with higher priority levels are accepted The net result is that interrupts are normally processed in decreasing order of priority It is however possible to alter this arrangement 1 To disable interrupt nesting Reset the MIE bit in the PSW to 0 Raise the priority level of the interrupt mask IM in the PSW 2 To enable interrupts with lower priority than the currently accepted interrupt Lower the priority level of the interrupt mask IM in the PSW Multiplex interrupts are only enabled for interrupts with levels higher than the PSW interrupt mask level IM It is possible to forcibly rewrite IM to accept an interrupt with a priority lower than the interrupt being processed but be careful of stack overflow Do not operate the maskable interrupt control register xxxICR when multiple interrupts are enabled If operation is necessary first clear the PSW MIE flag to disable interrupts an 12 Overview Chapter 3 Interrupts Figure 3 1 7 shows the processing flow for multiple interrupts interrupt 1 xxxLV1 xxxLV0z 10 and interrupt 2 xxxLV1 xxxLV0 00 Main program 1 1 0 11 Interrupt 1 generated zw Accepted because xxxLV1 0 IM xxxLV1 0 10 IM1 0 10 gt IInterrupt acceptance cycle q Interrupt service routine 1 Interrupt 2 generated 7 9 Accepted because xxxLV1 0 lt IM xxxLV1 0 00
266. ltage N non selective voltage driver voltage LCD Function Operation Chapter 11 LCD Functions 81 2 Duty Driving Waveform frame cycle COMO 2 Vicp E 1 seges Brea eise Vici Vice L1 Vies 1 1 1 1 1 1 1 1 1 1 1 SEGG 151 gt pases Vici Vice data 1 2 A electrode COM1 SEG6 eat 0 1 2 Vicp VicD 4 VLCD 1 2 Vicp B electrode COMO SEG6 0 1 2 CT wed 0 Figure 11 4 2 LCD Display Example of 1 2 Duty LCD Function Operation XI 19 Chapter 11 LCD Functions 11 4 4 Setup Example 1 2 Duty Setup Example of the LCD Function Operation 1 2 Duty Segment signal SEGO to SEG7 and common signal COMO to at the display mode of 1 2 duty 1 2 bias make the double digit 8 segment LCD panel display 23 e Chapter 11 11 4 3 LCD Display Examples 1 2 Duty It is used 4 MHz as the high oscillation clock fosc 122Hz as 2 for LCD clock and 61 Hz as frame frequency An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the LCD operation 1 Setthe LCDEN flag of the LCD mode control LCMD x 3FCD register LCMD to 0 to stop the LCD bp7 LCDEN 0 operation 2 Setup of the LCD display duty 2 Set 1 2 as the
267. m reset is initiated by the hardware Reset pin outputs low level 8 1 1 Block Diagram mWatchdog Timer Block Diagram internal reset release overflow WDIRQ WDCTR WDEN reset input gt LLL Y Y R 7 S 15 29 A MUX 15 219 15 2 Y ROM option R Y 1 2 overflow 0 Y UN gt 1 4 DLYCTR 1 4 1 4 gt J _DLyso 1 DLYS1 BUZCKO 1 2 BUZCK1 1 2 BUZOE 1 29 MUX 1 29 Figure 8 1 1 Block Diagram Watchdog Timer buzzer The watchdog timer is also used as a timer to count the oscillation stabilization wait time This is used as a watchdog timer except at recovering from STOP mode and at reset releasing The watchdog timer is initialized at reset or at STOP mode and counts system clock fs as a clock source from the initial value x 0000 The oscillation stabilization wait time is set by the oscillation stabilization control register DLYCTR After the oscillation stabilization wait counting is continued as a watchdog timer Chapter2 2 5 Reset 2 Overview Chapter 8 Watchdog Timer 8 2 Control Registers The watchdog timer is controlled by the watchdog timer control register WDCTR And the cycle of the watchdog timer period is set in ROM option Ch
268. m8 io bpz0 PC 72PC 0011 0101 Obp lt io8 47 4 io8 bp label if mem8 io bp 1 PC 8 d1 t 5 if mem8 io bp 0 PC 82PC 0011 0101 1bp lt io8 lt 41 52 BNZ abs16 bp label mem8 abs 16 bp 1 PC 9 d7 label H gt PG if mem8 abs16 bp 0 PC 9 PC 0011 1111 Obp lt abs gt d e TBNZ abs16 bplabel if mem8 abs16 bp 1 PC 10 d1 label HPC if mem8 abs16 bp 0 PC 1 02 PC 0011 1111 1bp abs gt dii JMP JMP An 0 17 16 15 0 0 0010 0001 00A0 JMP label abs18 label H2PC 0011 1001 lt abs 15 0 gt 15 JSR JSR An SP 3 SP PC 3 bp7 0 smem8 SP PC 3 bp15 8 mem8 SP 1 PC 3 H gt mem8 SP 2 bp7 0 8 5 2 6 2 PC 3 bp17 16 gt mem8 SP 2 bp1 0 0 PC bp17 16 An PC bp15 0 02PC H 0010 0001 00A1 JSR label SP 35SP PC 5 bp7 0 5mem8 SP PC 5 bp15 8 mem8 SP 1 5 8 2 6 7 0 8 2 6 2 5 5 17 16 8 2 6 1 0 5 912 5 0001 000H lt d12 3 JSR label SP 35SP PC 6 bp7 0 mema SP PC 6 bp15 8 mem8 SP 1 PC 6 H gt mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 6 bp17 16 gt mem8 SP 2 bp1 0 PC 6 d16 label H3PC 0001 001H lt d16 4 JSR label SP 3 SP PC 7 bp7 0 mem8 S
269. mte eee XII 3 Control Registers unten tenebre Nid Ree ee XII 4 12 25 ette bieten ite XII 4 12 2 2 Registets sees neptem OO RERO E Rs XII 5 12 2 3 AMD Buffer iie XII 7 cose nr tte e e e eet pete pet e teen XII 8 12 321 AMG Re ee a aes XII 10 12 3 2 Setup Examples nette eter rete XII 12 12 3 3 CautiOns iini e ERU Op E ERE ER eats decane XII 14 Chapter 13 Appendices contents 13 1 13 2 13 3 13 4 13 5 EPROM Versions citi REG REESE XIII 2 13 11 OVERVIEW ione eee eise ager ee ep XIII 2 13 322 Cautions on 1156 oni eoe RU ett hes XIII 3 13 1 3 Erasing Data in Windowed Package PX AP101C48 FBC FHC XIII 4 13 1 4 Differences between Mask ROM version and EPROM 1 XIII 5 13 1 5 Writing to Microcomputer with Internal EPROM XIII 6 13 1 6 Cautions on Operation ROM XIII 8 13 1 7 Programming Adapter Connection see XII 9 13 158 Option Bit iei hnen emet eater iater ees XIII 10 Probe Switches 101 09 48 64 XIII 11 Special Function Registers 116 XIII 13 Instr ction tee XIII 20 Instr ction i ett etae tete te et re dettes XIII 26 Chapter 1 Overview Chapter 1 Overvi
270. n address calculations i e addition subtraction and comparison Those pointers are 2 bytes data Transfers between these registers and memory are always in 16 bit units Either odd or even address can be transferred At reset the value of address register is undefined 15 0 lt Pointer SP This register gives the address of the byte at the top of the stack It is decremented during push opera tions and incremented during pop operations At reset the value of SP is undefined 15 0 2 1 6 Registers for Data Registers for data include four data registers DO D1 D2 D3 mData Registers 00 D1 D2 D3 Data registers DO to D3 are 8 bit general purpose registers that support all arithmetic logical and shift operations All registers can be used for data transfers with memory The four data registers may be paired to form the 16 bit data registers DWO D0 D1 and 02 03 At reset the value of Dn is undefined Data D1 DO Dwo registers D3 02 Dwi Overview 7 Chapter 2 CPU Basics 2 1 7 Processor Status Word Processor status word PSW is an 8 bit register that stores flags for operation results interrupt mask level and maskable interrupt enable PSW is automatically pushed onto the stack when an interrupt occurs and is automatically popped when return from the interrupt service routine 7 6 5 4 3 2 1 0 PSW Reserved MIE IM1 IMO VF NF CF ZF Atreset 0000 0000
271. n compare register is x FF V 22 8 bit PWM Output Chapter 5 8 bit Timers 5 6 2 Setup Example BPWM Output Setup Example Timer 2 The 1 4 duty cycle PWM output waveform is output from the 2 output pin at 2 kHz by using timer 2 at fosc 4 19 MHz Cycle period of PWM output waveform is decided by the overflow of the binary counter H period of the PWM output waveform is decided by the setting value of the compare register An example setup procedure with a description of each step is shown below TM2IO output 2 kHz Figure 5 6 4 Output Waveform of TMOIO Output Pin Setup Procedure Description 1 Stop the counter TM2MD x 3F82 bp4 TM2EN 20 2 Setthe special function pin to the output mode 1 x 3F39 bp2 12 1 P1DIR 1 bp2 P1DIR2 1 3 Select the PWM operation TM2MD x 3F82 bp3 2 1 4 Select the count clock source TM2MD x 3F82 bp2 0 TM2CK2 0 001 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the timer 2 counting Set the P12TCO flag of the port 1 output mode register P1OMD to 1 to set P12 pin to the special function pin Set the P1DIR2 flag of the port 1 direction control register P1DIR to 1 for the output mode If it needs pull up resistor should be added t Chapter 4 I O Ports Set the TM2PWM flag of the TM2MD register to 1 to select the PWM operation Select fs
272. n data an input edge of the received data At UART communication the transfer clock is not necessary but the SCOCE1 0 flag should be set to decide the timing of the data transmission reception in this serial interface At UART communication generally set the SCOCE1 0 flag to 00 the transmission data output edge to falling and the reception data input edge to rising Refer to Table 10 3 2 X 16 for Input Edge Output Edge Setup detail mData Input Pin Setup The communication mode can be selected from with 2 channels data output pin TXD pin data input or with 1 channel data I O pin TXD pin The pin can be used only for serial data input The TXD pin can be used for serial data input or output The SCOIOM flag of the SCOMD3 register can specify which pin RXD or TXD to input the serial data Data input from TXD pin is selected to be with 1 channel communication At switching transmission reception TXD pin s direction should be controlled by the PODIRO flag of the PODIR register At that time the RXD pin is not used so that it can be used as a general port X 30 Operation Chapter 10 Serial Interface 0 Mode and Parity Check Setup Figure 10 3 11 shows the data format at UART communication 1 data frame parity bit character bits Figure 10 3 11 UART Serial Interface Transmission Reception Data Format The transmission reception data consi
273. n drain First transfer bit MSB SBTO pin pull up resistor Not added SBOO pin pull up resistor Not added Input clock edge falling edge SBIO pin pull up resistor Added Serial 0 communication Output clock edge rising edge complete interrupt Enable Internal clock Clock master communication An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the clock synchronous serial 1 Set the SCOCMD flag of the serial interface 0 interface control register SCOCTR to 0 to select the SCOCTR x 3F54 clock synchronous serial interface SCOCMD 0 2 Setthe SCOMDO register 2 Setthe SCOLNG2 0 flag of the serial interface Select the transfer bit count 0 mode register 0 SCOMDO to 000 to set SCOMDO x 3F50 the transfer bit to 8 bits bp2 0 SCOLNG2 0 000 Select the start condition Set the SCOSTE flag of the SCOMDO register SCOMDO x 3F50 to 0 to disable start condition bp3 SCOSTE 0 Select the first bit to be transferred Set the SCODIR flag of the SCOMDO register to SCOMDO x 3F50 0 to set MSB as a transfer first bit bp4 SCODIR 0 Select the transfer edge Set the SCOCEO 1 flag of the SCOMDO SCOMDO x 3F50 register to 0 1 to set the transmission data bp6 SCOCEO 0 output edge rising and the received data bp5 SCOCE1 1 input edge falling X 26 Operation Chapter 10 Serial Interface 0 Setup Procedure
274. nction Operation External interrupts 0 to 1 After sampling the input signal to the external interrupt pins IRQO IRQ1 by the set sampling time if the same level comes continuously three times that level is sent to the inside of LSI If the same level does not come continuously three times the previous level is sent It means that only the signal with the width of more than Sampling time x 3 sampling clocks can pass through the noise filter and other much narrower signals are removed because those are regarded as noise IRQn pin input signal Waveform after filtering noise Figure 3 3 7 Noise Remove Function Operation Noise filter can not be used at STOP mode and HALT mode External Interrupts IH 41 Chapter 3 Interrupts Noise Filter Setup Example External interrupt 0 and 1 Noise remove function is added to the input signal from P20 pin to generate the external interrupt 0 IRQO at the rising edge The sampling clock is set to fs 2 and the operation state is fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description Specify the interrupt active edge IRQOICR x 3FE2 bp5 REDGO 1 Select the sampling clock NFCTR x 3F8A bp2 1 NFOCKS1 0 00 Set the noise filter operation NFCTR x 3F8A 1 Set the interrupt level IRQOICR x 3FE2 bp7 6 IRQOLV1 0 10 Enable the interrup
275. ndle a signed value Interrupt Mask Level IM1 and IMO Interrupt mask level IM1 and IMO controls the maskable interrupt acceptance in accordance with the interrupt factor interrupt priority for the interrupt control circuit in the CPU The 2 bit control flag defines levels 0 to Level 0 is the highest mask level The interrupt request will be accepted only when the level set in the interrupt level flag xxxLVn of the interrupt control register xxxICR is higher than the interrupt mask level When the interrupt is accepted the level is reset to IM1 IMO and interrupts whose mask levels are the same or lower are rejected during the accepted interrupt processing Table 2 1 3 Interrupt Mask Level and Interrupt Acceptance Interrupt mask level Priority Acceptable interrupt levels IM1 IMO Mask level 0 0 0 High Non maskable interrupt NMI only Mask level 1 0 1 NMI Level 0 Mask level 2 1 0 NMI Level 0 to 1 Mask level 3 1 1 Low NMI Level 0 to 2 imMaskable Interrupt Enable MIE Maskable interrupt enable flag MIE enables disables acceptance of maskable interrupts by the CPU s internal interrupt acceptance circuit 1 enables maskable interrupts 0 disables maskable inter rupts regardless of the interrupt mask level IM1 IMO setting PSW This flag is not changed by interrupts Overview 9 Chapter 2 CPU Basics 2 1 8 Addressing Modes The MN101C48 series su
276. need I 39 Chapter 2 CPU Basics contents 2 1 ONVGEVIGW iei cet EUER RR GERE 2 2 1 1 Block Diagram zie eir itte ree eode Wark guest tore 3 2 1 2 CPU Control Registers II 4 2 1 3 Instruction Execution Controller eene II 5 2 1 4 Pipeline Ptocess tne ed ehe ete ettet 6 2 1 5 Registers for 5 EE 6 2 1 6 Repistets fot Data oe ee ene tem ete 7 2 1 7 Processor Status Word eee 8 2 1 8 Addressing Modes noia eee a estes II 10 2 2 2 3 2 4 2 5 5 HR p rg HR RI E 12 2 2 1 Memory Modes em bt 12 2 2 2 Single chip Mode II 13 2 2 3 Memory Expansion Mode II 14 2 2 4 Special Function Registers eese eene 15 Bus Interac s ee II 16 2 3 1 Bus Controller is trei it i ie e ees II 16 2 3 2 Control Registers II 17 2 3 3 Fixed Wait Cycle Mode seen II 19 2 3 4 Handshake Mode nee Pede II 19 2 3 5 External Memory Connection Example sese II 21 St ndby Euncti n iino epe Pe eret II 22 2 4 1 OVERVIEW iie t ue E 22 2 4 2 CPU Mode Control Register essere II 24 2 4 3 Transition between SLOW and
277. ng mode after reset and the watchdog timer frequency EROM Option Bits 7 6 5 4 3 2 1 0 WDMD WDSEL2 WDSEL1 NSSTRT NSSTRT Operating mode after reset 0 SLOW mode 1 NORMAL mode WDSEL2WDSEL1 Watchdog timer frequency 0 fs 2 0 1 15 2 1 x fs 2 WDMD Set always to 1 Figure 1 6 1 ROM Option Bits ROM option address differs depending on the model Table 1 6 1 ROM Option Address Model ROM option address MN101C485 X 07FFF MN101C487 X 07FFF MN101CP487 X 07F FF 1 Even if SLOW mode is selected after reset connect oscillator pins to the high speed oscilla tion input 1 WDMD bp5 should be always set to 1 If it is set to 0 that operation cannot be stopped after the watchdog timer is started 1 30 Option 1 6 2 Option Check List Model Name MN101C 1 Operating mode after reset NORMAL mode SLOW mode 3 Supply voltage operating range Date SE No Chapter 1 Overview Customer Countersign 2 Watchdog timer period fs 2 fg 2 fs 2 CPU Operation Used Unused apply voltage Ose Operation Xl Operation At HALTO V At HALT1 V At STOP V to V 4 Type and freq uency of oscillation input System
278. nsion mode or processor mode the external expansion bus can access external device Memory control register can be used to select the access mode fixed wait cycle mode handshake mode Wait cycle setting to peripheral expansion bus connected to internal peripheral cir cuits is available II 16 Bus Interface Chapter 2 CPU Basics 2 3 2 Control Registers Bus interface is controlled by 2 registers the memory control register MEMCTR and the expansion address control register EXADV mMemory Control Register MEMCTR 7 6 5 4 3 2 1 0 MEMCTR IOW1 IOWO IVBA EXWH IRWE EXW1 EXWO Atreset 11001011 Fixed wait cycles Bus cycle at EAWT T00 20 MHz oscillation 00 No wait cycles 100 ns 01 1 wait cycle 150 ns 10 2 wait cycles 200 ns 11 3 wait cycles 250 ns IRWE Software write enable flag for interrupt request Software write disable 0 Even if data is written to each interrupt control register xxxICR the state of the interrupt request flag xxxIR will not change 1 Software write enable EXWH Fixed wait cycle mode or handshake mode 0 Handshake mode 1 Fixed wait cycle mode EXMEM Memory expansion mode 0 Do not expand external memory 1 Expand external memory IVBA Base address setting for interrupt vector table 0 Interrupt vector base x 04000 1 Interrupt ve
279. nterrupt 2 Control Register IRQ2ICR x 03FEB R W 20 Control Registers Chapter 3 Interrupts Interrupt 4 Control Register IRQ4ICR The external interrupt 4 control register IRQ4ICR controls interrupt level of external interrupt 4 active edge interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is set to level IRQ4LV1 IRQ4LV0 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag 7 6 5 4 3 2 1 0 IRQ4 IRQ4 _ D IRQ4ICR wi REDG4 IRO4IE IRO4IR At reset 000 0 0 IRQ4IR External interrupt request flag 0 No interrupt request 1 Interrupt request generated IRQ4IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDG4 External interrupt active edge flag 0 Falling edge 1 Rising edge IRQ4 IRQ4 LV1 LVO Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 5 External Interrupt 4 Control Register IRQ4ICR R W Control Registers III 21 Chapter 3 Interrupts Timer 2 Interrupt Control Reg
280. nual describes the following models of the MN101C48 series These products have same pe ripheral functions Table 1 1 1 Product Summary Model ROM Size RAM Size Classification 101 485 8 KB 512 bytes Mask ROM version MN101C487 16 KB 512 bytes Mask ROM version MN101CP487 16 KB 512 bytes EPROM version 1 2 Overview Chapter 1 Overview 1 2 Hardware Functions CPU Core MN101C Core LOAD STORE architecture 3 stage pipeline Half byte instruction set Handy addressing Memory addressing space is 256 KB Minimum instruction execution time High speed mode 0 10 4 20MHz 4 5 V to 5 5 0 25 4 8 MHz 2 7 V to 5 5 V 1 00us 2 MHz 2 0 V to 5 5 V Low speed mode 125 32 768 kHz 2 0 V to 5 5 1 EPROM vers is 2 3 V to 5 5 V Operation modes NORMAL mode High speed oscillation SLOW mode Low speed oscillation HALT mode STOP mode Memory modes Single chip mode Internal ROM 2 16 bytes 3 Internal RAM 2 512 bytes Memory expansion mode Internal ROM 2 16 Internal RAM 2 512 bytes External RAM 4 2 Differs depending upon the model E Chapter 1 1 1 2 Product Summary 3 1 byte of internal ROM is reserved for ROM option t Chapter 1 1 6 1 ROM Option Hardware Functions I 3 Chapter 1 Overview Interrupts 8 Internal interrupts lt Non maskable interrupt NMI gt Incorrect code execution interrupt and Watchdog timer interru
281. nversion Time ANSH1 ANSHO Sampling time A D conversion time Ts at TAD 800 5 at TAD 954 65 ns at TAD 1 91 us at TAD 15 26 us 0 TAD x 2 9 60 11 46 us 22 92 us 183 12 us 1 TAD x 6 12 80 us 15 27 us 30 56 244 16 us 0 TAD x 18 22 40 us 26 73 us 53 48 us 427 28 us 1 Reserved XII 10 Operation Chapter 12 A D Converter Built in Ladder Resistor Control The ANLADE flag of the ANCTRO register is set to 1 to send a current to the ladder resistance for A D conversion As A D converter is stopped the ANLADE flag of the ANCTRO register is set to 0 to save the power consumption Table 12 3 4 A D Ladder Resistor Control ANLADE A D ladder resistance control 0 A D ladder resistance OFF A D conversion stopped 1 A D ladder resistance ON A D conversion stopped A D Conversion Starting Setup A D conversion starting is set by the ANST flag of the register The ANST flag of the ANCTR1 register is set to 1 to start A D conversion Also the ANST flag of the ANCTR1 register is set to 1 during A D conversion then cleared to 0 as the A D conversion complete interrupt is generated Table 12 3 5 A D Conversion Starting ANST A D conversion status 0 A Dconversioncompletedor stopped 1 A D conversion started or in progress Operation XII 11 Chapter 12 A D Converter 12 3 2 Setup Example A D Conver
282. ode No pull up resistor VO port Port 5 Input mode No pull up resistor VO port Port 6 Input mode No pull up resistor VO port Port 7 Input mode No pull up pull down resistor VO port Port 8 Input mode No pull up resistor VO port Port A Input mode No pull up pull down resistor VO port Calculate the resistor of pull up and pull down based on the electrical characteristics of LSI User s Manual of each model as shown below Pull up resistor For example When pins maintain the low level guaranteed performance by the prescription of the electrical characteristics Notes It is not O V When VDD 5V VIN 1 5 V Input current Min 30 100 Max 300 LA means that the current runs from microcontroller Convert this to resistor value Typ 35 kQ However this value changes widely by temperature If it changes between 40 C and 85 it may be Min 11 7 kQ to Max 117 Pull down resistor For example When pins maintain the high level guaranteed performance by the prescription of the electrical characteristics Notes It is not VDD When 5 VIN23 5V Input current Min 30 uA 100 Max 300 LA Convert this to resistor value Typ 35 kQ However this value changes widely by temperature If it changes between 40 and 85 it may be Min 11 7 to Max 117 Overview IV 3 Chapter 4 I O Ports 4 1 3 Control Registers
283. ode specification SCOBRKE Brake status transmission control SCOORE Overrun error detection SCOCTR SCOPEK Parity error detection SCOFEF Frame error detection X 18 Operation Chapter 10 Serial Interface 0 Transmission Timing Tc 2 ts Tc ts Tc Clock SBTO pin Output data SBOO pin Start condition is enabled Output data SBOO pin Start condition is disabled Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ Write data SCOBSY is 1 on clock input at slave transmission to SCOTRB without start condition Figure 10 3 3 Transmission Timing falling edge 2 lt lt ts 54 Clock SBTO pin Output data SBOO pin Start condition is enabled Output data SBOO pin Start condition is disabled Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A A Write data SCOBSY is 1 on clock input at slave transmission to SCOTRB without start condition Figure 10 3 4 Transmission Timing rising edge Operation 19 Chapter 10 Serial Interface 0 Reception Timing Clock SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Input start condition Figure 10 3 5 Reception Timing rising edge start condition is enabled Clock SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Wri
284. of the serial interface 0 interrupt control register SCOICR Set the SCOIE flag of the SCOICR register to 1 to enable the interrupt request If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt Flag Setup Set the baud rate timer by the TM3MD register register And set the TM3EN flag to 1 to operate timer Set the SCOSBIS flag of the SCOMDS register to 1 to set the serial interface communication After start bit is received by inputting serial interface data from the TXD pin the received data is stored to the serial interface transmission reception shift register SCOTRB When the reception has completed the serial interface 0 interrupt SCOIRQ is generated then the received data is stored to the received buffer When the TXD RXD pin are connected for communication with 1 channel the TXD pin inputs outputs serial data The port direction control register PODIR should be set for switching input output At reception the SCOSBIS flag of the SCOMD3 register should be set to 1 and select serial interface data input The RXD pin can be used as a general port X 46 Operation Chapter 10 Serial Interface 0 Only timer 3 can be used as a baud rate timer For baud rate setup 4 Chapter 5 5 8 Serial Interface Transfer Clock Output Serial interface 0 is operated by setting the SCOSBOS flag or the SCOSBIS flag o
285. om port 7 at the next count clock BSynchronous Output Operation by 8 bit timer Timer 2 The port 7 latched data is output from the output pin at the interrupt request generation by the match of the binary counter and the compare register Only port 7 can perform synchronous output operation and individual pins can be set 8 bit timers that have synchronous output operation are timer 2 Table 5 7 1 Synchronous Output Port Timer 2 Timer 2 Synchronous output port Port 7 ilCount Timing of Synchronous Output Timer 2 TMnEN flag Compare T register 1 Port 7 output latch data EE DES d Le Co G0 co Cham CC CeCe counter Compare match signal Interrupt request flag Port 7 synchronous x 7 output data Figure 5 7 1 Count Timing of Synchronous Output Timer 2 The port 7 latched data is output from the output pin in synchronization with the interrupt request generation by the match of binary counter and compare register 8 bit Synchronous Output V 25 Chapter 5 8 bit Timers 5 7 2 Setup Example iSynchronous Output Setup Example Timer 2 Setup example that latched data of port 7 is output constantly 100 us by using timer 2 from the synchro nous output pin is shown below The clock source of timer 2 is selected fs 4 at fosc 8 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Start the c
286. operation 1 PWM operation TM4EN Timer 4 count control 0 Disable the count 1 Enable the count Figure 6 2 7 Timer 4 Mode Register TM4MD x 03F84 R W Control Registers VI 7 Chapter 6 16 bit Timer 6 3 16 bit Timer Count 6 3 1 Operation Timer operation can constantly generate interrupt 16 bit Timer Operation Timer 4 The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare register TM4OC in advance When the binary counter TM4BC reaches the set value of the compare register the timer 4 interrupt request flag is set to 1 at the next count clock the binary counter TM4BC is cleared to x 0000 and the counting up is restarted from x 0000 unit data even if it is a 16 bit MOVW instruction As a result the CPU will read the data a When the CPU reads the 16 bit binary counter TM4BC the read data is treated as 8 bits incorrectly if a carry from the lower 8 bits to the upper 8 bits occurs during counting VI 8 16 bit Timer Count Chapter 6 16 bit Timer Table 6 3 1 shows the clock source that can be selected Table 6 3 1 Clock Source at Timer Operation Timer 4 Clock source 1 count time fosc 50 ns fs 4 400 ns fs 16 1 6 us as fosc 20 MHZ fs fosc 2 10 MHz WCount Timing of Timer Operation Timer 4 The binary counter counts up with the selected clock source as the count clock The basic operation of the whole
287. ormal bp5 TM4PWM 0 timer operation 6 Set the compare register 6 Set the timer 4 compare register TM40C x 3F75 x 3F74 x FFFF TM4OCL to x FFFF At that time the timer 4 binary counter TM4BC is initialized to x 0000 16 bit Timer Capture VI 29 Chapter 6 16 bit Timer Setup Procedure Description 7 Set the interrupt level 7 Set the interrupt level by the IRQOLV1 0 flag of IRQOICR x 3FE2 the IRQOICR register bp7 6 IRQOLV1 0 10 If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt Flag Setup 8 Enable the interrupt 8 Enable the interrupt by setting the IRQOIE flag IRQOICR x 3FE2 of the IRQOICR register to 1 bp1 IRQOIE 21 9 Start the timer operation 9 Set the TM4EN flag of the TM4MD register to TMAMD x 3F84 1 to start timer 4 bp6 TMAEN 1 TM4BC counts up from x 0000 At the timing of the rising edge of the external interrupt 0 input signal the value of TM4BC is stored to the TMAIC register At the above 7 8 the IRQO interrupt is enabled but input capture is available even if an interrupt is disabled However if an interrupt is enabled the pulse width between rising edges of the external interrupt input signal can be measured by reading the value of TM4IC register by the interrupt service routine and by calculating the margin of the capture values the values of the 4 regis ter
288. ounter 1 Set the TM2EN flag of the timer 2 mode TM2MD x 3F82 register TM2MD to 0 to stop the timer 2 bp4 TM2EN 20 counting 2 Select the synchronous output 2 Setthe P7SYEVS1 0 flag of the pin control event register 2 FLOAT2 to 10 to set the FLOAT x 3F4C synchronous output event to timer 2 interrupt bp1 0 p7SYEVS1 0 10 3 Set the synchronous output pin 3 Set the synchronous output control register SYSMD x 3F1F x FF SYSMD to x FF to set the synchronous P7DIR x 3F37 X FF output pin P77 to P70 are synchronous output pin Set the port 7 direction control register P7DIR to x FF to set port 7 to output mode If it needs pull up resistor should be added Chapter 4 Ports 4 Select the normal timer operation 4 Set the TM2PWM flag of the TM2MD register TM2MD 3 82 to 0 to select the normal timer operation bp3 0 5 Select the count clock source 5 Select fs 4 for clock source TM2CK2 0 flag TM2MD x SF82 of the TM2MD register bp2 0 TM2CK2 0 001 V 26 8 bit Synchronous Output Chapter 5 8 bit Timers Setup Procedure Description 6 Set the synchronous output event generation cycle TM2CC x 3F72 x 63 7 Start the timer operation TM2MD x 3F82 bp4 2 1 6 Set the synchronous output generation cycle to the timer 2 compare register 2 The setting value is set to 100 1
289. output signal or the synchronizing circuit output signal that passed through the divide by circuit TM4IO input System clock fs Synchronizing circuit output count clock TM4EN flag Compare register Binary 0000 0001 0000 0001 counter Compare match signal Interrupt request flag Figure 6 4 2 Count Timing of Synchronous Input Timer 4 When the synchronous TMAIO input is selected as the count clock source the timer 4 counter counts up in synchronization with system clock therefore the correct value is always read But if the synchronous TM4IO is selected as the count clock source CPU mode cannot return from STOP HALT mode 14 16 bit Event Count 6 4 2 Setup Example Event Count Setup Example Timer 4 If the falling edge of the TM4IO input pin signal is detected 5 times using timer 4 an interrupt is gener ated Chapter 6 16 bit Timer An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter x 3F84 4 0 Select the normal timer operation x 3F84 bp5 TM4PWM 0 Set the special function pin to input mode P1DIR x 3F31 bp4 P1DIRA 0 Select the count clock source TM4MD x 3F84 bp2 0 TM4CK2 0 011 Set the interrupt generation cycle TM40C x 3F75 x 3F74 x 0004 Set the interrupt level TMAICR x
290. ow speed X1 operation OFF High speed OSC Probe Switches XII 11 Chapter13 Appendices 13 2 2 PRB EV101C15 Compatible devices This board corresponds to the following devices The product type is subject to change without prior notice The latest information should be confirmed on our web site MN101C08 MN101C16 MN101C39 MN101C09 MN101C24 MN101C42 MN101C10 MN101C27 MN101C45 MN101C11 MN101C28 MN101C48 MN101C14 MN101C30 MN101C51 MN101C15 MN101C38 How to connect Figure 1 Connecting a PRB EV101C15 to an Adapter board PRB ADP101C PRB EV101C15 Make sure that the points marked would be put together Caution1 MM Adapter board PRB ADP101C Caution 2 Caution When connect the boards make sure that they are connected without tilt If you put pressure on one side of the board that may cause any damage to the pins Caution2 Please visit our web site to check the adapter boards corresponding to your microcomputer we update the web site periodically 12 Probe Switches Chapter 13 Appendices 13 3 Special Function Registers List Bit Symbol Initial Value Description Address Register Reserved Reserved Reserved 0 STOP Set always 0 Set always 0 Set always 0 transition request HALT transition request MEMCTR Extemal memory expansion mode specified Interrupt vector Fixes wait mode Interr
291. pin SBTO pin at reception SBIO pin can be used as a general port Table 10 3 9 Setup for Synchronous Serial Interface Pin 2 channels at reception Data VO pin Serial unused pin Clock VO pin Setup item SBTO pin SBOO 5 0 pin Internal clock External clock master communication slave communication Pin 1 2 SBIO SBOO connected SBIO SBOO pin SCOMD3 SCOIOM Port Serial data input Serial clock Port Function SCOMD3 SCOMD3 SCOSBOS SCOSBIS SGOMDSISGOSBTS Push pull Push pull Style Nch open drain Nch open drain SCOMD3 SCOSBTM Input mode Output mode Input mode PODIR PODIRO PODIR PODIR2 ini Added Not added Added Not added Added Not added ull u d POPLU POPLUO POPLU POPLU2 Operation X 25 Chapter 10 Serial Interface 0 10 3 2 Setup Example Transmission Reception Setup Example The setup example for clock synchronous serial interface communication with serial interface 0 is shown Table 10 3 10 shows the conditions at transmission reception Table 10 3 10 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item set to Setup item set to Independent SBI0 SBOO with 3 channels Clock source fs 2 Transfer bit count 8 bits Clock source 1 8 dividing not divided by 8 Start condition none 5 0 SBOO pin style N ch ope
292. port 5 direction control register P5DIR to 1 and write the value of the port 5 output register Each pin can be set individually if pull up resistor is added or not by the port 5 pull up resistor control register PBPLU Set the control flag of the port 5 pull up resistor control register PBPLU to 1 to add pull up resistor At reset the P50 to P53 input mode is selected and pull up resistors are disabled high impedance output iSpecial Function Pin Setup P50 to P53 are used as LED driving pins as well P53 is used as LCD driving pin segment output as well The bpO of the segment output control register LCCTR set if they are used as segment output pins or general I O pins In memory expansion mode P50 to P52 are output pins for control signal to the expansion memory In this mode output mode is always selected In memory expansion mode P53 is output pin for address to the expansion memory But the bp7 of the address output control register EXADV set if they are used as address output pins or general I O pins Table 4 5 1 Expansion Pins P50 to P54 Pins In memory expansion mode P50 NWE P51 NRE P52 NCS P53 A16 External memory address bp16 memory expansion mode the of the EXADV register should be set to 1 for P53 output address Pot5 IV 17 Chapter 4 I O Ports 4 5 2 P5OUT P5IN P5DIR P5PLU IV 18 Registers 3 2 1 0
293. pports the nine addressing modes Each instruction uses a combination of the following addressing modes 1 Register direct 2 Immediate 3 Register indirect 4 Register relative indirect 5 Stack relative indirect 6 Absolute 7 RAM short 8 short 9 Handy These addressing modes are well suited for C language compilers All of the addressing modes can be used for data transfer instructions In modes that allow half byte addressing the relative value can be specified in half byte 4 bit increments so that instruction length can be shorter Handy addressing reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combining handy addressing with absolute addressing reduces code size For transfer data between memory 7 addressing modes register indirect register relative indirect stack relative indirect abso lute RAM short I O short handy can be used For operation instruction register direct and immediate can be used Refer to instruction s manual for the MN101C series This LSI is designed for 8 bit data access It is possible to transfer data in 16 bit increments with odd or even addresses II 10 Overview Chapter 2 CPU Basics Table 2 1 4 Addressing Modes Effective address Explanation Directly specifies the register Only internal registers can be specified 15 0 Addressing mode Dn DWn An SP PSW imm4 imm8 imm16 Register direct Immediate
294. pt lt Timer interrupts gt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Timer 5 interrupt Time base interrupt lt Serial interface interrupts gt Serial interface 0 interrupt Synchronous Half duplex UART lt A D interrupt gt A D converter interrupt lt Automatic transfer controller ATC interrupt gt Automatic transfer interrupt 4 External interrupts IRQO Edge selectable With Without noise filter IRQ1 Edge selectable With Without noise filter AC zero cross detector IRQ2 Edge selectable Synchronous output event IRQ4 Key interrupt function Timers 5 timers 4 can operate independently 8 bit timer for general use 1 set 8 bit timer for general use UART baud rate timer 1 set 8 bit free running timer 1 set Time base timer 1 set 16 bit timer for general use 1 set Timer 2 8 bit timer for general use Square wave output Timer pulse output PWM output Event count Synchronous output event Clock source fs fs 4 fx TM2IO pin input Timer 3 8 bit timer for general use or UART baud rate timer Square wave output Timer pulse output Event counter Serial interface transfer clock output 16 bit cascade connection function connect to timer 2 Remote control carrier output Clock source fosc fs 4 fs 16 pin input Hardware Functions Chapter 1 Overview Timer 4 16 bit timer for general use Square wave outpu
295. pts are the return factors from standby mode A wait period is inserted for oscillation stabiliza tion at reset and when returning from STOP mode but not when returning from HALT mode High low frequency oscillation mode is automatically returned to the same state as existed before entering standby mode oscillation fosc and low speed oscillation fx fosc should be set to 2 5 times or higher a To stabilize the synchronization at the moment of switching clock speed between high speed frequency than fx Standby Functions II 23 Chapter 2 CPU Basics 2 2 CPU Mode Control Register Transition from one mode to another mode is controlled by the CPU mode control register CPUM 7 6 5 4 3 2 1 0 CPUM RESERVED RESERVED RESERVED STOP HALT OSC1 OSCO At reset 2 0 0 0 0 0 0 0 Set always 0 d STOP HALT OSCt OSCO 255 CPU NORMAL 0 0 0 0 Oscillation Oscillation fosc 2 Operating IDLE 0 0 0 1 Oscillation Oscillation fx 4 Operating SLOW 0 0 1 1 Halt Oscillation fx 4 Operating HALTO 0 1 0 QOscillation Oscillation fosc 2 Halt HALT1 0 1 1 1 Halt Oscillation fx 4 Halt STOPO 1 0 0 0 Halt Halt Halt Halt STOP1 1 0 1 1 Halt Halt Halt Halt Figure 2 4 2 Operating Mode and Clock Oscillation CPUM 00 R W The procedure for transition from NORMAL to HALT or STOP mode is giv
296. put Timer 3 count control Disable the count Enable the count Figure 5 2 6 Timer 3 Mode Register TM3MD 03 83 R W Control Registers Chapter 5 8 bit Timers mRemote Control Carrier Output Control Register RMCTR 7 6 5 4 3 2 1 0 RMOEN Reserved RMDTY0 Reserved Atreset 00XX0 RMCTR Reserved Reserved Set always 0 Remote control carrier output duty RMDTYO 0 1 2 duty 1 1 3 duty Reserved Set always 0 RMOEN Enable remote control carrier output 0 Output low level 1 Output remote control carrier Reserved Set always 0 Figure 5 2 7 Remote Control Carrier Output Control Register RMCTR 89 R W Control Registers V 9 Chapter 5 8 bit Timers 5 3 8 bit Timer Count 5 3 1 Operation The timer operation can constantly generate interrupts B8 bit Timer Operation Timers 2 and 3 The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register TMnOC in advance If the binary counter TMnBC reaches the setting value of the compare register an interrupt is generated at the next count clock then binary counter is cleared and counting is restarted from 00 Table 5 3 1 shows clock source that can be selected Table 5 3 1 Clock Source Timers 2 and 3 at Timer Operation
297. r 12 A D Converter 12 3 3 Cautions Since conversion can be damaged by noise easily antinoise measures are necessary BAntinoise measures For A D input analog input add condenser near the Vss pins of micro controller Digital Analog VoD Vss Sa VREF Power supply to ia qp Digital Vss AN7 VREF Analog Vss Set near the Vss pin Figure 12 3 2 A D Converter Recommended Example 1 VDD VDD Vss Vss VREF Power supply to AN7 VREF Set near the Vss pin Figure 12 3 3 A D Converter Recommended Example 2 XII 14 Operation Chapter 12 A D Converter kept 1 input impedance of A D input pin should be under 500 and the external capacitor C more than 1000 pF under 1 pF 2 The A D conversion frequency should be set with consideration of R C time constant 3 Atthe A D conversion if the input level of micro controller is changed or the peripheral added circuit is switched to ON OFF the A D conversion may work wrongly because the analog input pins and power pins does not fix At the check of the setup confirm the wave form of analog input pins For high precision of A D conversion the following cautions on A D converter should be Equivalent circuit block that outputs analog signal microcontroller R s Em A 77 7
298. r more detailsd infomation required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book About This Manual Organization In this LSI manual the LSI functions are presented in the folowing order overview CPU basic functions interrupt functions port functions timer functions serial interface functions and other peripheral hardware functions Each section contains overview of function block diagram control register operation and setting example Manual Configuration Each section of this manual consists of a title summary main text key information precautions and warnings and references The layout and definition of each section are shown below Subtitle Chapter 2 Basic CPU Sub subtitle 8 The smallest block in this manual Main text 2 8 1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin P 27 is pulled to A Key information Initiating a Reset here are two methods to initiate a reset Drive the NRST pin low for at least four clock cycles NRST pin should be holded low for more than 4 clock cycles 200 nS at a 20 MHz NRST pin i 4 clock cycles 200 nS at a 20 MHz Figure 2 8 1 Minimum Reset Pulse Width 2 Setting the P2OUTT flag of
299. rce TM3MD 3 83 bp2 0 TM3CK2 0 000 5 Set the timer pulse output cycle x 3F73 x C7 6 Start the timer operation x 3F83 bp4 1 1 Set the flag of the timer 3 mode register TM3MD to 0 to stop timer 3 counting Set the P13TCO flag of the port 1 output mode register P1OMD to 1 to set P13 the special function pin Set the flag of the port 1 direction control register P1DIR to 1 to set output mode If it needs pull up resister should be added Chapter 4 Ports Set the TM3PWM flag of the TM3MD register to 0 to select the normal timer operation Select fosc for the clock source by the 2 0 flag of the TM3MD register Set the timer 3 compare register to the 1 2 of the timer pulse output cycle The setting value should be 200 1 199 7 because 100 kHz is divided by 20 MHz At that time the timer 3 binary counter is initialized to 00 Set the flag of the TM3MD register to 1 to start timer 3 8 bit Timer Pulse Output 19 Chapter 5 8 bit Timers counts up from x 00 If TM3BC reaches the setting value of the register then is cleared to x 00 output signal is inverted and TM3BC restarts to count up from 00 P1DIR and the port 1 pull up register P1PLU are need to set to 1 When
300. re using this product please obtain product specifications from the sales office Package Dimension 1 33 Chapter 1 Overview 1 8 Precautions 1 8 1 General Usage iConnection of VDD pin and VSS pin All VDD pins should be connected directly to the power supply and all Vss pins should be connected to ground in the external Please consider the LSI chip orientation before mounting it on to the printed circuit board Incorrect connection may lead a fusion and break a micro controller iCautions for Operation 1 Ifyou install the product close to high field emissions under the cathode ray tube etc shield the package surface to ensure normal performance 2 Each model has different operating condition Operation temperature should be well considered For example if temperature is over the operating condition its operation may be executed wrongly Operation voltage should be also well considered If the operation voltage is over the operation range it can be shortened the length of its life If the operation voltage is below the operating range it operation may be wrong I 34 Precautions Chapter 1 Overview 1 8 2 Unused Pins mUnused Pins for output and LCD output Set unused pins for output and LCD output open Output Figure 1 8 1 Unused Pins for output and LCD output mUnused Pins only for input Insert 10 kO to 100 kO resistor to unused pins only for input for pull up or pull down If the input is
301. rithmetic manupulation instructions EXT Dn DWm ADD Dn Dm sign Dn BDWm Dm Dn Dm w P jaj w w a w w w j w 1001 000d 0011 DnDm DD imm4 Dm Dm sign imm4 gt Dm 1000 00Dm DD imm8 Dm Dm imm8 gt Dm 0000 10Dm DDC Dn Dm Dm Dn CF gt Dm 1011 DnDm DDW DWn DWm DWm DWn gt DWm 0101 00Dd DDW DWn Am Am DWn gt Am 0101 10Da DDW imm4 Am Am sign imm4 gt Am 1110 110a DDW imm8 Am Am sign imm8 5Am 1110 110a DDW imm16 Am Am imm16 gt Am 0101 011 DDW imm4 SP SP sign mm4 SP 1111 1101 DDW imm8 SP SP sign imm8 SP 1111 1100 DDW imm16 SP SP imm16 SP 1111 1100 DDW imm16 DWm DWm imm16 5DWm 0101 010d DDUW Dn Am Am zero Dn gt Am 1000 1aDn A A A A A A A A A A A A A A DDSW Dn Am Am sign Dn gt Am 1001 1aDn SUB Dn Dm when DnzDm Dm Dn2Dm 1010 DnDm SUB Dn Dn Dn Dn2Dn 1000 01Dn SUB imm8 Dm Dm imm8 5Dm 1010 DmDm lt 8 SUBC Dn Dm Dm Dn CF5Dm 1011 DnDm SUBW DWn DWm DWm DWn DWm 0100 00Dd SUBW DWn Am Am DWn Am 0100 10Da SUBW imm16 DWm DWm imm16 DWm 0100 010d SUBW imm16 Am Am imm16 Am 0100 011a MULU Dn Dm Dm Dn 2DWk 1111 111D DIVU Dn DWm DWm Dn DWnm DWm h 1110 111d CMP Dn Dm Dm Dn PSW
302. riting is disabled When the writing is disabled check the following points 1 Check that the device is mounted correctly on the socket pin bending connection failure 2 Check that the erase check result is no problem 3 Check that the adapter type is identical to the device name 4 Check that the writing mode is set correctly 5 Check that the data is correctly transferred to the ROM writer 6 Recheck the check points 1 to 5 provided on the above paragraph of Cautions on Handling the ROM writer eee XIII 8 EPROM Version Chapter 13 Appendices 13 1 7 Programming Adapter Connection gt lt lt lt lt lt lt lt lt OO i0 SE MMN OOQ O O O O O O O O O O O O O O CQ st LO PF QN Oaoaadaadnkaanaananaadt G5808500905O LoT 90000 OQ 0 O0 0 0 D 0 CO CO LL LL LI UI UI co OPEN 1 SEG16 P67 A7 OPEN 2 SEG17 P66 A6 OPEN 3 SEG18 P65 5 4 SEG19 P64 A4 OPEN 5 SEG20 P63 A3 OPEN 6 SEG21 P62 A2 OPEN 7 SEG22 P61 Al VDD 8 MN101CP487 SEG23 P60 AO OPEN 9 SEG24 P53 Vss Vss 10 LCD Version P52 Vss Vss 11 OTP P51 Vss Vss 12 P50 Vss Vss 13 P22 Vss Vss P21 Vss OPEN P20 VPP NOE 16 e ei P14 TM4IO 33 V
303. ritten during the TMnEN flag is 1 the binary counter is not changed E If the TMnEN flag is 0 the binary counter is stopped after 1 count up When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register Compare register setting count till the interrupt request 1 If the compare register is set the smaller than the binary counter during the count operation the binary counter counts up to the overflow at first If the interrupt is enabled the timer interrupt request flag should be cleared before timer operation is started Even if the TMnEN flag of the timer is cleared during operation it does not stop until the next count clock Therefore during 1 count clock after the TMnEM is cleared the binary counter cannot be initialized 8 bit Timer Count 11 Chapter 5 8 bit Timers 5 3 2 Setup Example Timer Operation Setup Example Timers 2 and 3 Timer function can be set by using timer 2 that generates the constant interrupt By selecting fs 4 at fosc 20 MHz as a clock source interrupt is generated every 250 clock cycles 100 us An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM2MD x 3F82 bp4 TM2EN 20 TM2MD x SF82 bp3 STM2PWM
304. rmal timer operation 35 Remote Control Carrier Output Chapter 5 8 bit Timers Setup Procedure Description 6 Select the count clock source TM3MD x 3F83 bp2 0 2 0 000 7 Set the base cycle of remote control carrier x 3F73 x 6C 8 Start the timer operation TM3MD x 3F83 bp4 1 9 Enable the remote control carrier output RMCTR x 3F89 bp3 1 Select fosc to clock source by the TM3CK2 0 flag of the TM3MD register Set the base cycle of remote control carrier by writing x 6C to the timer 3 compare register The set value should be 8 MHz 73 4 kHz 1 108 x 6C 8 MHz is divided to be 73 4 kHz 2 times 36 7 kHz Set the flag of the TM3MD register to 1 to stop the timer 3 counting Set the RMOEN flag of the RMCTR register to 1 to enable the remote control carrier output TMSBC counts up from 00 Timer outputs the base cycle pulse set in Then the 1 3 duty remote control carrier pulse signal is output If the RMOEN flag of the RMCTR register is set to O the remote control carrier pulse signal output is stopped V 36 Remote Control Carrier Output Chapter 6 16 bit Timer Chapter 6 16 bit Timer 6 1 Overview This LSI contains a general purpose 16 bit timer Timer 4 6 1 1 Functions Table 6 1 1 shows the functions of timer 4 can use Tabl
305. rol UART clock Transfer clock Operation X 33 Chapter 10 Serial Interface 0 Other Control Flags The following flags need not to be set at communication Table 10 3 16 Other Control Flags Register Flag Detail SCOMDO SCOLNG2 to 0 Selection ot the transfer bit count automatically set SCOMD1 SCOCKM Selection of the 1 8 division automatically set SCOSBTS Selection of the SBT pin s function SCOMD3 SCOSBTM Selection of the SBT pin s style The following items are the same to clock synchronous serial interface Reference as follows BFirst Transfer Bit Setup Refer to X 13 Transfer Bit Count and First Transfer Bit Refer to X 15 mReceived Data Buffer Refer to X 15 Bit Count and First Transfer Bit Refer to X 15 EBUSY Flag Operation Refer to X 18 X 34 Operation Chapter 10 Serial Interface 0 Transmission Timing Stop Stop bit bit TXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 12 Transmission Timing parity bit is enabled Stop bit TXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 13 Transmission Timing parity bit is disabled Operation 35 Chapter 10 Serial Interface 0 Reception Timing X 36 Stop Stop bit bit RXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 14 Reception Timing parity
306. rol register Timer 2 interrupt Ill 21 TMSICR R W Timer interrupt control register Timer interrupt Ill 22 TM4ICR xOSFEF R W Timer 4 interrupt control register Timer 4 interrupt Ill 23 R W 5 interrupt control register Timer 5 interrupt Ill 24 TBICR X03FE7 RW Time base interrupt control register Time base period Ill 25 SCOICR X03FE8 R W Serial interface 0 interrupt control register Serial interface 0 interrupt Ill 26 ADICR R W A D converter interrupt control register A D converter interrupt 27 R W Readable Writable 1 Writing to the interrupt control register should be done after that maskable interrupts are set to be disabled by the MIE flag of the PSW register If the interrupt level flag xxxLVn is set to level 3 its vector is disabled regardless of interrupt enable flag and interrupt request flag Control Registers 15 Chapter 3 Interrupts 3 2 2 Interrupt Control Registers The interrupt control registers include the non maskable interrupt control register NMICR the external interrupt control register IRQnICR and the internal interrupt control register xxxICR MNon maskable Interrupt Control Register NMICR address x 03FE1 The non maskable interrupt control register NMICR stores the non maskable interrupt request When the non maskable interrupt request is generat
307. s are disabled high impedance output Special Function Pin Setup POO to 2 are used as I O pin for serial interface 0 as well POO is output pin of the serial interface 0 transmission data and UART transmission data When the SCOSBOS flag of the serial interface 0 mode register is 1 POO is serial data output 01 is the input pin of the serial interface 0 reception data and UART reception data When the SCOSBIS flag of the serial interface 0 mode register 3 SCOMD3 is 1 is serial data input pin PO2 is I O pin of the serial interface 0 clock When the SCOSBTS flag of serial interface 0 mode register SCOMD3 is 1 PO2 is serial interface clock output pin POO and 02 can be selected as either an push pull output or Nch open drain output by the SCOSBOM and the SCOSBTM of the serial interface 0 mode register SCOMD3 t Chapter 10 10 2 Control registers P06 is used as a buzzer output pin as well When the bp7 of the oscillation stabilization control register DLYCTR is 1 buzzer output is enabled In memory expansion mode data acknowledge mode input pin NDK is selected In those mode input mode is always selected IV 6 Pot0 Chapter 4 Ports 4 2 2 Registers 7 6 5 4 3 2 1 0 POOUT POOUT6 POOUT2 POOUTO Atreset 0 000 POOUT Output data 0 L Vss level 1 level Port 0 output regist
308. s first transfer bit by the SCODIR flag of the SCOMDO register Set the SCOSTE flag of the SCOMDO register to disable start condition 33 Selection of Start Condition Set the SCOCK1 0 flag of the SCOMD1 register to select timer 3 output as a clock source Set the SCONPE flag of the SCOMD2 register to select parity is enabled and set the SCOPM1 0 flag to select checked Set the SCOFM1 0 flag of the SCOMD2 register to 11 to select 8 bits data 2 stop bits at the frame mode Set the SCOIOM flag of the SCOMDS register to 1 to set the SBOO to transmission reception port X 45 Operation Chapter 10 Serial Interface 0 Setup Procedure Description 8 Control the pin direction PODIR x 3F30 PODIRO 0 9 Add pull up resistor to the TXD pin POPLU x 3F40 POPLUO 1 10 Select the interrupt level SCOICR 8 bp7 6 SCOLV1 0 10 11 Enable the interrupt SCOICR x 3FE8 bp1 SCOIE 21 12 Set the baud rate timer 13 Set the serial interface communication SCOMDS x 3F53 bp1 SCOSBIS 1 14 Start the serial interface reception Received data Input to TXD Set the PODIRO flag of the PODIR register to 0 to set the TXD pin to input mode Set the POPLUO flag of the POPLU register to add pull up resistor to the TXD pin Select the interrupt level by the SCOLV1 0 flag
309. se IL IM and MIE 1 xxxLV1 0 00 1 0 00 Interrupt acceptance cycle Interrupt service routine 1 1 Interrupt 2 generated xxxLV1 0 10 pee IM1 0 11 Interrupt acceptance cycle 1 0 10 Cinterrupt service routine 2 RTI 0 11 Interrupt generated 7 Not accepted because IM IL xxxLV1 0 11 Y Parentheses indicate hardware processing 1 If during the processing of the first interrupt an interrupt request with an interrupt level IL numerically lower than the interrupt mask IM arrives it is accepted as a nested interrupt If IL 2 IM however the interrupt is not accepted 2 second interrupt postponed because its interrupt level IL was numerically greater than the interrupt mask IM for the first interrupt service routine is accepted when the first interrupt handler returns Figure 3 1 6 Processing Sequence for Maskable Interrupts Overview 11 Chapter 3 Interrupts Multiplex Interrupt When 101 48 series device accepts an interrupt it automatically disables acceptance of subse quent interrupts with the same or lower priority level When the hardware accepts an interrupt it copies the interrupt level xxxLVn for the interrupt to the interrupt mask IM in the PSW As a result subse quent interrupts with the same or lower priority levels are automatica
310. sed Memory Space II 13 Chapter 2 CPU Basics 2 2 3 Memory Expansion Mode The MN101C series can connect external ROM RAM and external devices for operation in memory expansion mode This is the mode to expand to external memory while using internal ROM and RAM The memory expansion mode is set by assigning EXMEM flag bp4 of the memory control register on single chip mode The pins A8 to 16 of the address expansion control register EXADV control the address output to pins by setting the bit 7 to bit 5 of the EXADV Memory areas can be externally expanded as follows RAM x 02F00 x 03EFF 4 KB 00000 Abs8 addressing 4 256 bytes Internal 1 00100 Data 00200 16 External expansion 14 goer d d Spcial registers 256 bytes function area x 04000 Interrupt A 128 bytes vector table 04080 Subroutine 64 bytes vector table 16 KB E Te Internal ROM Instructions code Table data Y Y X07FFF MMOD pin L EXMEM flag 1 Figure 2 2 2 Memory Expansion Mode Differs depending on the model Table 2 2 2 Internal ROM Internal RAM The value of internal RAM is uncertain when power is applied to it It needs to be initialized before it is used II 14 Memory Space Chapter 2 CPU Basics 2 2 4 Special Function Registers The MN101C series loca
311. sistor 1 Pull down resistor PARDWN Port A pull up pull down resistor selection 0 Pull up resistor Pull down resistor P211M P21 input mode selection Schmitt trigger input ACZ input Pin control register 1 FLOAT1 X 03F4B R W Figure 4 9 2 Port A Registers 2 3 Chapter 4 I O Ports 7 6 5 4 3 2 1 0 5 At reset 0 0000 PAO 1 key interrupt selection 0 disable 1 enable PA2 key interrupt selection 0 disable 1 enable P4KYEN3 PA4 PAS key interrupt selection 0 disable 1 enable PAG PA7 key interrupt selection 0 disable 1 enable IRQ4SEL IRQ4 interrupt source selection 0 disable 1 PA key interrupt Key interrupt control register P4IMD R W Figure 4 9 3 Port A Registers 3 3 PotA IV 41 Chapter 4 Ports 4 9 3 Block Diagram Pull up Pull down resistor control Pull up Pull down resistor selection Port input data Input mode control Analog input Key interrupt input EYO 7 IV 42 PortA an PAPLUDO 7 B Write Read Reset gt R FLOAT
312. source Time base timer cannot stop the operation 13 bit counter of time base timer can be initialized only at reset This LSI has built in time base timer for digital clock For example if fx 32 768 kHz is selected as clock source interrupt request flag is set by 13 bit counter par 250 ms However the 13 bit counter can be initialized only at reset Therefore the first interrupt request flag is not always set after 250 ms Depending on counting condition the first interrupt request flag is generated after 0 ms minimum to 250 ms maximum So digital clock may gain 250 ms maximum How to keep a error to a minimum on setting for digital clock When fx 32 768 kHz is set as clock source and the time base timer is used as digital clock Select fosc as clock source Generate interrupt During interrupt service routine change clock source to fx and initialize a digital clock Time Base Timer 13 Chapter 7 Time Base Timer 8 bit Free running Timer 7 4 2 Setup Example Timer Operation Setup Time Base Timer Time base timer generates an interrupt constantly in the selected interrupt cycle The interrupt genera tion cycle is as fosc x 1 2 as 0 976 ms fosc 8 39 MHz for generation interrupts An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the clock source TM5MD x 3F88
313. ss Naro N a archaea 9 EN e lt i 2 SS 5 aa N ort lo CO N CN N CO 20 0 gt 0 0 2 0 0 000 2 20 0 gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt Package LQFP064 P 1414 TQFP064 P 1010B Pin pitch 0 8 mm 0 50 mm Figure 13 1 2 101 487 EPROM Programming Adapter Connection EPROM Version XIII 9 Chapter 13 Appendices 13 1 8 Option Bit MN101CP487 has EPROM option address to specify the operating mode after reset and the watchdog timer frequency Option Bits 7 6 5 4 3 2 1 0 WDMD WDSEL2 WDSEL1 NSSTRT NSSTRT Operating mode after reset 0 SLOW mode 1 NORMAL mode WDSEL2WDSEL1 Watchdog timer frequency 0 fs 2 0 1 fs 2 1 X fs 2 WDMD Must be set 1 Figure 13 1 3 EPROM Option Bits ROM option address differs depending on the model Model EPROM option address MN101CP487 X 07FFF 1 Even if SLOW mode is selected after reset connect oscillator pins as well as to the high speed oscillation input 1 WDMD bp5 should be always set to 1 If it is set to 0 that operation cannot be stopped after the watchdog timer is started XIII 10 EPROM Version Chapterl3 Appendices 13 2 Probe Switches 13 2
314. ss output P53 A16 address output during memory expansion mode 0 General port 1 A16 address output Figure 2 3 3 Expansion Address Control Register EXADV x OSFOE R W In memory expansion mode unused address pins can be used as general ports II 18 Bus Interface Chapter 2 CPU Basics 2 3 3 Fixed Wait Cycle Mode This mode accesses ROM RAM or other low speed devices connected to the external expansion bus by inserting the number of wait cycles specified in the external fixed wait counter EXW field of the memory control register MEMCTR Fixed wait cycle mode is used to automatically insert the number of wait cycles specified by the fixed wait counter EXWn in the MEMCTR After reset MEMCTR specifies the fixed wait cycle to three wait cycles To change to handshake mode or to use a different number modify the appropriate bits in MEMCTR 2 3 4 Handshake Mode Handshake mode uses the interlock control method in the data transfer sequence with a transfer enable signals NRE NWE and a data acknowledge signal Handshake mode adjusts the wait cycle for each external device that has a different access speed when the DK generation circuit is provided for each device CPU of this LSI keeps waiting until the reception of data acknowledge signal to ensure sufficient wait time so that external device can receive data with no error t MN101C LSI User s Man
315. sts of start bit character bit parity bit and stop bit Table 10 3 12 shows its kinds to be set Table 10 3 12 UART Serial Interface Transmission Reception Data Start bit 1 bit must be L Character bit 7 8 bits Parity bit fixed to 0 fixed to 1 even odd none Stop bit 1 2 bits noramally H The to 0 flag of the SCOMD2 register sets the frame mode Table 10 3 13 is shown the UART serial interface frame mode setting If the SCOCMD flag of the SCOCTR register is set to 1 and UART communication is selected the SCOLNG2 to 0 flag of the SCOMDO register is automatically set Table 10 3 13 UART Serial Interface Frame Mode SCOMD2 register Frame mode 5 SCOFMO 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits Stop bit 2 bits Operation 31 Chapter 10 Serial Interface 0 Parity bit is to detect wrong bits with transmission reception data Table 10 3 14 shows kinds of parity bit The SCONPE SCOPM1 to 0 flag of the SCOMD2 register set parity bit Table 10 3 14 Parity Bit of UART Serial Interface SCOMD2 register Parity bit Setup SCONPE SCOPM1 SCOPMO 0 0 0 fixed to 0 Set parity bit to 0 0 0 1 fixed to 1 Set parity bit to 1 Control the total number of 1 of parity bit and 0 1 0 character bit
316. t IRQOICR x 3FE2 bp1 IRQOIE 21 1 Set the REDG 0 flag of the external interrupt 0 control register IRQOICR to 1 to specify the interrupt active edge to the rising edge Select the sampling clock to fs 2 by the NFOCKS1 0 flag of the noise filter control register NFCTR Set the NFOEN flag of the NFCTR register to 1 to add the noise filter operation Set the interrupt level by the IRQOLV 1 0 flag of the IRQOICR register If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt flag setup Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt Note The above 2 and 3 are set at the same time The input signal from the P20 pin generates the external interrupt 0 at the rising edge of the signal after passing through the noise filter a The setup of the noise filter should be done before the interrupt is enabled LI The external interrupt pins are recommended to be pull up in advance 42 External Interrupts Chapter 3 Interrupts 3 3 7 AC Zero cross Detector This LSI has AC zero cross detector circuit The P21 SENS pin is the input pin of AC zero cross detector circuit AC zero cross detector circuit output the high level when the input level is at the middle and outputs the low level at other level Zero cross Detector External interrupt 1 AC zero cross detector sets the IRQ1 pin to the high level
317. t Timer pulse output PWM output Event count Synchronous output event Input capture function Clock source fosc fs 4 fs 16 TM4IO pin input Timer 5 8 bit free running timer Time base timer 8 bit free running timer Clock source fosc 15 4 fx fosc 27 213 Time base timer Interrupt generation cycle fosc 2 fosc 2 fosc 2 fosc 2 9 fosc 21 fx 2 28 29 fx 2 fx 2 8 at 32 768 kHz for low speed oscillation input can be set to measure one minute intervals Watchdog timer Watchdog timer frequency can be selected from 15 216 15 218 fs 2 as ROM option Remote control output Based on the timer 0 and timer 3 output a remote control carrier with duty cycle of 1 2 or 1 3 can be output Synchronous output Timer synchronous output Interrupt synchronous output Port 7 outputs the latched data on the event timing of the synchronous output signal of timer 2 or 4 or of the external interrupt 2 IRQ 2 Buzzer output Output frequency can be selected from 15 29 15 216 fs 2 15 212 A D converter 10 bits x 8 channels input Hardware Functions 1 5 Chapter 1 Overview Serial interface 1 type Serial interface 0 Half duplex UART Synchronous serial interface Synchronous serial interface Transfer clock source fs 2 fs 4 fs 16 UART baud rate timer timer 3 output External clock MSB LSB can be selected as the first bit to be transferred Any transfer size from 1
318. t current 1 PU EASTON ay 30 100 300 56 Input current 2 5222 d 30 100 300 57 high voltage VDD 5 0 0 5 mA 4 5 58 Output low voltage VOLt1 VDD 5 0 V loL 1 5 mA 0 5 Electrical Characteristics 1 25 Chapter 1 Overview is for EPROM vers 40 to 85 Ta 20 to 70 VDD 2 0 V 2 3 v to 5 5v VSS 0 Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin4 P21 when used as SENS 5 0 V for P21 SENS 59 Input high voltage 1 VDHH 4 5 VDD 60 Input high voltage 2 VDHL 1 5 VDD Fig 1 5 5 61 Input low voltage 1 VDLH Vss 3 5 62 Input low voltage 2 VDLL Vss 0 5 63 Input leakage current LKS VN 0 V to VDD 2 64 Input high current gt VDD VN lt 0 V 400 Display output pin 1 COMO to COM3 65 ZocoMit 5 405 3 6 Output impedance 66 Zocomz VDD 3V 03V 8 15 Display output pin 2 SEGO to SEG51 7 67 ZoseEG1 VDD 5V 0 5V 15 30 Output impedance 68 Zoseg2 VDD 5V t03V 30 60 7 SEGO to SEG24 also function as P53 P60 to P67 P70 to P77 P80 to P87 1 26 Electrical Characteristics Chapter 1 Overview 1 5 4 Characteristics 40 to 85 2 0 V 2 3 V to 5 5 Vss 0 V EPROM vers is Rating Parameter Symbol Conditions Unit MIN TYP
319. t lit LCD PANEL LCD ON COM S COM N LCD OFF SEG S SEG S SEG LCD clock undefined Data 1 0 undefined Vad Vict Vice Vica COM SEG Vict Vics Vic COM SEG 1 3 0 1 3 Vico sMiep 222 2 ee Lit Not lit Not lit Not lit Not lit S selective voltage N non selective voltage LCD driver voltage XI 22 LCD Function Operation Chapter 11 LCD Functions 1 3 Duty Driving Waveform i frame cycle Vict Vict Vice Vics Vict Vice Vics Vict 2 COM2 Vicb COMI COMO SEG5 data 4 VLCD 41 3 0 1 3 A electrode COM2 SEG5 Vicp 1 3 0 1 3 B electrode 1 5 5 not lit lit not lit Figure 11 4 3 LCD Display Example of 1 3 Duty LCD Function Operation XI 23 Chapter 11 LCD Functions 11 4 6 Setup Example 1 3 Duty Setup Example of the LCD Function Operation 1 3 Duty Segment signal SEGO to SEG5 and common signal COMO to COMO at the display mode of 1 3 duty 1 3 bias make the double digit 8 segment LCD panel display 23 t Display Examples 1 3 Duty It is used 4 MHz as the high oscillation clock fosc 122Hz as
320. t output control register LCCTR set if they are used as segment output pins or general I O pins Pot7 IV 27 Chapter 4 Ports In memory expansion mode P70 to P77 are output pins to the expansion memory But in memory expansion mode the bp5 bp6 of the address output control register EXADV set if they are used as address output pins or general I O pins Table 4 7 1 Expansion Pins P70 to P77 Pins In memory expansion mode P70 A8 External memory address bp8 P71 A9 External memory address bp9 P72 A10 External memory address bp10 P73 A11 External memory address bp11 P74 A12 External memory address bp12 P75 A13 External memory address bp13 P76 A14 External memory address bp14 P77 A15 External memory address bp15 memory expansion mode the bp5 6 of the EXADV register should be set to 1 for P70 to P77 output address IV 28 Port7 Chapter 4 Ports 4 7 2 Registers 7 6 5 4 3 2 1 0 P70UT5 P70UT4 P70UT3 P70UT2 P70UT1 700 0 Atreset 00000000 P7OUT P7OUT7 P7OUT6 P7OUT Output data 0 Low Vss level 1 High VDD level Port 7 output register P7OUT x 03F17 R W 7 6 5 4 3 2 1 0 ene ris P7IN4 P7INS P7IN2 P7IN1 At reset X XXX X XXX P7INO P7IN P7IN7 P7IN Input data Pin is Low Vss level Pin is High level Port 7
321. t the instruction of the watchdog timer clear to the main routine as that value makes the same cycle If the watchdog timer interrupt service routine does not respond to a watchdog timer interrupt for resetting the chip the hardware responds to the next one by pulling the RESET pin low to reset the chip Operation VIII 5 Chapter 8 Watchdog Timer mWatchdog Timer and CPU Mode The relation between this watchdog timer and CPU mode features are as follows 1 2 3 4 5 6 In NORMAL IDLE SLOW mode the system clock is counted The counting is continued regardless of switching at NORMAL IDLE SLOW mode In HALT mode the watchdog timer is not stopped In STOP mode the watchdog timer is cleared automatically by hardware In STOP mode the watchdog interrupt cannot be generated After releasing reset or recovering from STOP the counting is executed for the duration of the oscillation stabilization wait time Da YS DY WH On HALT mode the watchdog timer count won t stop If it should be stopped set the WDEN flag of the watchdog timer control register WDCTR to 0 to stop the watchdog timer opera tion before transition to HALT mode When CPU mode is switched to STOP mode during the watchdog timer operation the opera tion does not stop after it operates as a counter for oscillation stabilization waiting at recover the watchdog timer is not necessary to detect errors
322. t those light sources are also able to erase data more or less To expose those light sources for a long while can damage its system To prevent this cover the window with an opaque label If the wavelength is longer than 400 nm to 500 nm data can not be erased However because of typical semiconductor characteristics the circuit may malfunction if the chip is exposed to an extremely high illumination intensity The chip will operate normally if this exposure is stopped However for areas where it is continuous take necessary precautions against the light that the wavelength is longer than 400 nm XIII 4 EPROM Version Chapter 13 Appendices 13 1 4 Differences between Mask ROM Version and EPROM Version The differences between the 8 bit microcontroller MN101C487 485 Mask ROM version and MN101CP487 internal EPROM version are as follows Table 13 1 1 Differences between Mask ROM version and internal EPROM version MN101C48 series MN101CP487 Mask ROM version EPROM version 4 5 V to 5 5 V 0 1 us at 20 MHz 4 5 V to 5 5 V 0 1 us at 20 MHz Operating voltage 2 7 V to 5 5 V 0 25 us at 8 MHz 2 7 V to 5 5 V 0 25 us at 8 MHz 2 0 V to 5 5 V 1 00 us at 2 MHz 2 3 V to 5 5 V 1 00 us at 2 MHz Pin DC Characteristics Output current input current and input judge level are the same Option bits Settings for operating mode after reset ROM option EPROM option and watchdog timer frequency t Chapter 1 1 6 Option
323. te dummy data to SCOTRB at master or clock input at slave Figure 10 3 6 Reception Timing rising edge start condition 18 disabled X 20 Operation Chapter 10 Serial Interface 0 Clock SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Input start condition Figure 10 3 7 Reception Timing falling edge start condition is enabled Clock d SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Write dummy data to SCOTRB at master or clock input at slave Figure 10 3 8 Reception Timing falling edge start condition Is disabled Operation X 21 Chapter 10 Serial Interface 0 Transmission Reception Simultaneous Timing When transmission and reception are operated at the same time set the SCOCEO to 1 flag of the SCOMDO register to 00 or 01 Data is received at the opposite edge of the transmission clock so that the reception clock should be the opposite edge of the transmission clock from the other side SBTO pin Data is received at the rising edge of clock SBIO pin Data is output at the falling edge of clock Figure 10 3 9 Transmission Reception Timing Reception rising edge Transmission falling edge SCOCEO 0 SCOCE1 0 SBTO pin Data is received at the falling edge of clock SBIO pin Data is output at the rising edg
324. ter Setup Example by Registers A D conversion is started by setting registers The analog input pins are set to ANO the converter clock is set to fs 4 and the sampling hold time is set to TAD x 6 Then A D conversion complete interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the analog input pin PAIMD PAIMDO 1 PAPLUD 4 PAPLUDO 0 Select the analog input pin ANCTRO x 3F90 bp2 0 ANCHS2 0 000 Select the A D converter clock ANCTRO x 3F90 bp5 4 ANCK1 0 01 Set the sample and hold time ANCTRO x 3F90 bp7 6 ANSH1 0 01 Set the interrupt level ADICR bp7 6 ADLV1 0 00 Enable the interrupt ADICR x 3FEA bp1 ADIE 1 Set the A D ladder resistance ANCTRO x3F90 bp3 ANLADE 1 1 Set the analog input pin set in 2 to the special function pin by the port A input mode register PAIMD Also set no pull up pull down resistance by the port A pull up pull down resistance control register PAPLUD Set the ANO PAO to the analog input pin by setting the ANCHS2 0 flag of the A D converter control register 0 ANCTRO to 000 Set the fs 4 to the A D converter clock by setting the ANCK1 0 flag of the A D converter control register 0 ANCTRO to 01 Set the TAD x 6 to the sample and hold time by setting the ANSH1 ANS
325. ter clear Time base timer interrupt cycle Timer 4 operation mode Capture trigger for TM4 TMSIR1 TMSIRO 5 Timer 5 clock source Clock source 5 2 TM5CK1 Time base timer TM5CKO clock source Reserved RMOEN Reserved RMDTYO Reserved 0 0 x x 0 Enable remote control carrier output Set always 0 NF1CKS1 NF1CKSO 0 0 0 IRQ1 noise filter sampling period IRQ1 noise filter setup Remote control carrier output duty NFOCKS1 NFOCKSO 0 0 Set always 0 IRQO noise filter sampling period Set always 0 0 IRQO noise filter setup ANSHO ANCK1 ANCKO ANLADE ANCHS2 ANCHS1 ANCHSO x ANCTRO x x 0 x x x A D sample and hold time A D ladder resistance control A D conversion clock nalog input selection ANST 0 ANCTR1 A D conversion status ANBUFO ANBUFO A D buffer 0 lower 2 bits ANBUFO ANBUF17 16 ANBUF 15 ANBUF 14 ANBUF13 ANBUF 12 ANBUF 11 ANBUF10 x x ANBUF 1 x x x x x x Note x Initial value is unstable No data A D buffer 1 upper 8 bits Special Function Registers List XIII 17 Chapter 13 Appendices Address Bit Symbol Initial Value Description Register LCXXBUF Buffer for LCD display SEGSEL6 SEGSEL5 SEGSEL4 SEGSEL3 SEGSEL2 SEGSEL1 SEGSELO 0 Port 80 to 83 selection
326. tes the special function registers I O spaces at the addresses x 03F00 to in memory space The special function registers of this LSI are located as shown below Table 2 2 3 Register Map HOISIALL HOIEIAL 3909 YOILOU HOIOOHI HINN lozuoo 401 QW91 91991 2096191 4098191 4082191 3089191 ANGS LOT ANVLOT ANGELOT 1 3080101 3093097 308001 lozuoo Q v LANENV OANENV OHLONV YLOAN YLONWY GWEWL saw SOSWL HOOPWL TOOPWL DOENL OOZWL HOWL HOSTAL OGEWL OACWL euas 8Xu05S 1005 19095 QWODS 2011095 GNODS 0QINODS 203159 L1VOT4 4 Md8d 1494 fr1dSd fYldid ae Gand GWOld 9 yod Nivd NI8d NI9d Nild indino GWSAS LNO8d LNOZd LNOYd LNOSd LNO d LNOld LNOOd Jonuoo do HLOGM HLOWSN d 3 a 9 6 8 L 9 S 0 X44 0 X33 0 Xq4e0 X94 0 X843 0 60
327. the P2OUT register to 0 outputs low level at P27 And transfering to reset by program software reset can be executed If the internal LSI is reset and register is initiated the P2OUT7 flag becomes 1 and reset is released Important information from the main text E gt Chapter 4 4 4 2 Registers On this LSI the starting mode is NORMAL mode that high oscillation is the base clock enough low level time at sudeen unconnected And reset can be generated even if its pulse When the power voltage low circuit is connected to NRST pin circuit that gives pulse for is low level as the oscillation clock is under 4 clocks take notice of noise 44 Reset Summary Introduction to the section References References for the main text Precautions and warnings Precautions are listed in case of lost func tionality or damage Be sure to read Finding Desired Information This manual provides three methods for finding desired information quickly and easily 1 2 3 Consult the index at the front of the manual to locate the beginning of each section Consult the table of contents at the front of the manual to locate desired titles Chapter names are located at the top outer corner of each page and section titles are located at the bottom outer corner of each page mRelated Manuals Note that the following related documents are available MNIOIC Series
328. the expansion memory In this mode any register cannot control input or output Only at access to the expansion memory address is output and during other period at NCS H it is high impedance state input mode Table 4 6 1 Expansion Pins P60 to P67 Pins In memory expansion mode P60 AO External memory address bp0 P61 A1 External memory address bp1 P62 A2 External memory address bp2 P63 A3 External memory address bp3 P64 A4 External memory address bp4 P65 A5 External memory address bp5 P66 A6 External memory address bp6 P67 A7 External memory address bp7 Pot6 IV 23 Chapter 4 I O Ports 4 6 2 Registers 7 6 5 4 3 2 1 0 P6OUT P60UT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P60UT2 P60UT1 P60UTO At reset 00000000 P6OUT Output data 0 Low Vss level 1 High VDD level Port 6 output register P6OUT x 03F16 R W 7 6 5 4 3 2 1 0 P6IN P6IN7 P6ING P6IN5 PeIN4 P6IN3 P6IN2 P6IN1 P6INO At reset X X XXX XXX P6IN Input data 0 Pin is Low Vss level 1 Pin is High VDD level Port 6 intput register P6IN 03 26 7 6 5 4 3 2 1 0 P6DIR P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 PeDIR2 PeDIR1 PeDIRO At reset 00000000 P6DIR I O mode selection 0 Input mode 1 Output mode Port 6 direction control register P6DIR
329. the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 R i A po LVI LVO At reset 0 0 0 0 TMSIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Interrupt enable flag 0 Disable interrupt 1 Enable interrupt interrupt level f v The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 7 Timer Interrupt Control Register x 03FEE R W Control Registers 23 Chapter 3 Interrupts Timer 4 Interrupt Control Register TM4ICR The timer 4 interrupt control register TM4ICR controls interrupt level of timer 4 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 TM4LV1 TM4LV0 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 TM4 TM4 pig TM4ICR LV1 LVO TM4IE TMAIR At reset 0 0 0 0 TM4IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Interrupt enable flag 0 Disable int
330. tions of instruction codes This is reappeared with following combinations of instruction codes without exeption While a program is being executed if one of these instruction codes 2FD 3DA and which are identical to relevant unspecified instructions is generated right after the one of following 19 branch instructions is issued faulty interrupt which is not occured under normal conditions could be occured independently of issue of a branch instruction The relevant 19 branch instructions BEQ BNE BGE BCC BCS BLT BLE BGT BHI BLS BNC BNS BVC BVS BRA CBEQ CBNE TBZ TBNZ In ICE this faulty interrupt causes Illegal instruction break and halts the ICE operation In Mask ROM EEPROM and Flash ROM products this faulty interrupt results in a non maskable interrupt This causes is a design error in the hardware circuits which were originally designed to realize the sophistication of branch instructions This design error was detected in the circuits which process invalidation of the result ob tained from decoding of the program code before its execution Example When a branch instruction is placed right front of a ROM data and if the instruction right behind a branch instruction code 89 is 2FD corresponding faulty interrupt is occured Addr Code Nmonic 04100 AA mov A0 DO 04100 8907 bra 70 04102 dc F2 04103 dc OD ERN We released a software diagnostic tool as a temporary measur
331. to 8 bits can be selected Half duplex UART Baud rate timer Timer 3 Parity check overrun error framing error detection Transfer size 7 to 8 bits can be selected When using timer 3 the transfer rate for a 12 MHz oscillation are 19200 9600 4800 2400 1200 300 bps LED driver 4 pins LED driver LCD driver pins Segment output 25 pins max SEGO to 24 SEG 0 to 24 can be switched in 4 pin units to I O ports Segments 4 8 12 16 20 24 25 Note At reset SEG 0 to 24 are input ports Common output pins 4 pins Display mode selection Static 1 2 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias LCD driver clock The source clock is the main clock fosc 1 278 1 217 1 276 1 25 1 2 1 213 1 212 1 21 The source clock is the sub clock fx 1 23 1 28 1 27 1 26 LCD power supply Each of the VLC1 VLC2 and VLC3 pins supply power to the LCD 1 6 Hardware Functions Port Package Chapter 1 Overview ports 36 pins all have dual functions LED large current driver pins 4 pins push pull configuration Pins with dual function for external expansion mode 29 pins Input ports 11 pins all have dual functions dual function for External interrupt 3 pins One of which can also be used for zero cross input dual function for A D input 8 pins Special pins Analog reference voltage input pin 2 pins Operation mode input pin 1 pin Reset input pin 1 pin Power pin 2 pins Oscillation pin 4 p
332. tor C2 C1 7 7 TH Feedback resistance Rf 800 kQ TYP OSC1 MN101C48 series Figure 1 8 7 Basic configuration of Ceramic Resonator Connection Table 1 8 1 Recommended Ceramic Resonator and Its Circuit Constant D Recommended circuit constant Oscillation Ceramic resonator frequency product number Load capacity Dumping resistance C1 C2 Rd EFOB2005B5 Chip type 33 pF 5 pF built in 20 MHz EFOEX2005B4 Discrete type 33 pF 5 pF built in EFOB1605B5 type 33 pF 5 pF built in 16 MHz EFOEX1605E4 Discrete type 33 pF 5 pF built in EFOS8004B5 Chip type 33 pF 5 pF built in 2 8004 4 Discrete type 33 pF 5 pF built in dii EFOS4004B5 Chip type 33 pF 5 pF built in 2 EFOMCA004A Discrete type 33 pF 5 pF built in EFOS2004B5 Chip type 33 pF 5 pF built in 2 EFOMC2004A4 Discrete type 33 pF 5 pF built in Inquiry Matsushita Electronic Components Co Ltd URL http www maco panasonic co jp htm binl maco index html Precautions Overview I 39 Recommended value above is the consequence of the oscillation estimate by this LSI alone Insert dumping resistance if needed after the oscillation estimate on the application system substrate As for crystal resonator an oscillation estimate is not held by this LSI Apply the recommended value b
333. tors remain operational in HALTO and only the high frequency oscillator stops operating in HALT1 An interrupt returns the CPU to the previous CPU operating mode that is to NORMAL from HALTO or to SLOW from HALT1 ESTOP Modes STOPO STOP1 The CPU and both of the oscillators stop operating Aninterrupt restarts the oscillators and after allowing time for them to stabilize returns the CPU to the previous CPU operating mode that is to NORMAL from or to SLOW from STOP1 BSLOW Mode This mode executes the software using the low frequency clock Since the high frequency oscillator is turned off the device consumes less power while executing the software Mode This mode allows time for the high frequency oscillator to stabilize when the software is changing from SLOW to NORMAL mode To reduce power dissipation in STOP and HALT modes it is necessary to check the stability of both the output current from pins and port level of input pins For output pins the output level should match the external level or direction control should be changed to input mode For input pins the external level should be fixed The MN101C48 series has two system clock oscillation circuits OSC is for high frequency operation NORMAL mode and XI is for low frequency operation SLOW mode Transition between NORMAL and SLOW modes to standby mode is controlled by the CPU mode control register CPUM Reset and interru
334. ts 1 stop bit 8 data bits 2 stop bits SCOBRKE Break status transmit control 0 Data transmit Break transmit Figure 10 2 5 Serial Interface 0 Mode Register 2 SCOMD2 2 R W Control Registers Serial Interface 0 Mode Register SCOMD3 SCOMD3 7 6 5 4 3 2 1 0 Sra OM bosson 5 05 5005809 SCOSBIS Chapter 10 Serial Interface 0 atreset 000000 SCOSBTS SBTO pin function selection 0 Port Serial interface clock pin SBIO input control SCOSBIS reception enable flag 0 1 input 1 Serial data input SCOSBOS SBOO pin function selection transmission enable flag 0 Port 1 Serial data communication SCOSBTM SBTO pin configuration 0 Push pull output 1 N ch open drain output SCOSBOM SBOO pin configuration 0 Push pull output 1 N ch open drain output SCOIOM Reception port SBIO Reception port SBOO Transmission port SBIO General port SBOO Transmission Reception port Figure 10 2 6 Serial Interface 0 Mode Register x 03F53 R W Control Registers X 9 Chapter 10 Serial Interface 0 Serial Interface 0 Control Register SCOCTR The SCOORE SCOPEK SCOFEF and SCOBSY flags are only readable 7 6 3 2 1 SCOCTR SCOBSY SCOCMD SCOFEF SCOPEK
335. tup Pins of A D Converter Setup Input pins for A D converter is selected by the ANCH2 to 0 flag of the ANCTRO register Table 12 3 1 Input Pins of A D Converter Setup 2 1 ANCHSO A D 0 a 1 AN1 pin y 0 AN2 pin 1 0 4 1 AN5 pin i 0 AN6 pin 1 AN7 Clock of A D Converter Setup The A D converter clock is set by the ANCK1 to 0 flag of the ANCTRO register Set the A D converter clock TAD more than 800 ns and less than 15 26 us Table 12 3 2 shows the machine clock fosc fx fs and the A D converter clock TAD calculated as fs fosc 2 fx 4 Table 12 3 2 A D Conversion Clock and A D Conversion Cycle A D conversion cycle TAD ANCK1 ANCKO A D conversion clock at oscillation for high speed al at fosc 20 MHz Jat fosc 8 38 MHz at fx 32 768 kHz fs 2 200 00 ns 477 33 ns 244 14 us unusable unusable unusable 400 00ns 488 28 us a unusable 9583 8 unusable 5 8 800 00 1 91 us 27056 18 1 unusable fx x 2 15 26 us 15 26 us 15 26 us iSampling Time Ts of A D Converter Setup The sampling time of A D converter is set by the ANSH1 to 0 flag of the ANCTRO register The sampling time of A D converter depends on external circuit so set the right value by analog input impedance Table 12 3 3 Sampling Time of A D Conversion and A D Co
336. ual Architecture Instructions On handshake mode watchdog timer can be used to detect NDK not received error The reception of NDK is waited until the non maskable interrupt is generated by the overflow of watchdog timer Bus Interface II 19 Chapter 2 CPU Basics Access Timing with No Wait Cycles The NRE or NWE timing is determined based on OSC2 However since the delay from OSC2 to RE or WE varies depending upon the product use NRE or NWE as the reference when synchronizing with other devices Operation timing is same as the timing at NORMAL mode OSC high oscillation selec tion OSC2 NDK input E NCS i i i NRE NWE write Figure 2 3 4 ROM and RAM Access Timing with No Wait Cycles Access Timing with 1 Wait Cycle Access timing with 2 or 3 wait cycles follows the same pattern The latter part of the cycle is extended and the timing is the same nnnnnhrnnnnRnnn NDK input 3 NWE write read Figure 2 3 5 ROM and RAM Access Timing with 1 Wait Cycle II 20 Bus Interface Chapter 2 CPU Basics 2 3 5 External Memory Connection Example BSRAM Connection Example This example shows connection to SRAM The external expansion RAM area is x 02F00 to x 03EFF This LSI SRAM A16 to AO gt A16 to AO x 02F00 D7 to 00 4 D7 to DO External RAM area x OSEFF NCS gt
337. ue in the compare register TMnOC Output pins are as follows Table 5 5 1 Timer Pulse Output Pins Timer 2 Timer 3 2 output output Pulse output pin P12 P13 ilCount Timing of Timer Pulse Output Timers 2 and 3 TMnEN flag Compare register Binary oo ot 4N t1 00 X 4 NL JN J ot 00 counter Compare Match signal Interrupt request flag output Figure 5 5 1 Count Timing of Timer Pulse Output Timers 2 and 3 The TMnIO pin outputs 2 x cycle compared to the value in the compare register If the binary counter reaches the compare register and the binary counter is cleared to x 00 output is inverted 18 8 bit Timer Pulse Output Chapter 5 8 bit Timers 5 5 2 Setup Example Timer Pulse Output Setup Example Timers 2 and 3 TMSIO pin outputs 50 kHz pulse by using timer 3 For this select fosc as clock source and set a 1 2 cycle 100 kHz for the timer 3 compare register at fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter x 3F83 bp4 TMSEN 20 2 Setthe special function pin to the output mode x 3F39 bp3 1 P1DIR x 3F31 bp3 P1DIRS A 3 Select the normal timer operation x 3F83 bp3 TM3PWM 0 4 Select the count clock sou
338. ue of 2 3 4 and 5 are guaranteed on the condition that VDD VREF 5 VSS VREF 0 V 9 There should be more than 2 V between VREF and VREF 1 28 Electrical Characteristics Chapter 1 Overview 1 5 6 Bus Timing 0 wait states during Memory Expansion Read tcvc 100 ns min A16 00 at a tras 70 ns min 5 ns min Address hold Read address set up NCS M tavo Chip select delay Chip select delay 5 ns max 5 ns max NRE trew 70 ns min Read enable width 07 0 ra lt 80 15 Ons min Read data set up Read data hold Write mi gt tcyc 100 ns min A16 00 ra gt twas 25 ns min 5 ns min Address hold Write address set up NCS e EE tavo Chip select delay tavo Chip select delay 5 ns max 5 ns max NWE X 7 t wew 30 ns Write enable width D7 0 a lt twos 35 ns min 2 ns min Write data set up Write data hold To prevent the through current add the pull up pull down resistor or the level holding circuit to the expansion bus line address data to fix the level of the expansion bus line Espe cially for stand by mode Electrical Characteristics I 29 Chapter 1 Overview 1 6 Option 1 6 1 Option 101 48 series has ROM option address to specify the operati
339. uency to XI 3 tc2 tc3 tc4 where OSC1 is the CPU clock 5 where XI is the CPU clock 1 20 Electrical Characteristics Chapter 1 Overview is for EPROM vers 40 to 85 Ta 20 to 70 Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Crystal oscillator 1 Fig 1 5 1 12 Crystal frequency WDD depending on 2 0 20 0 MHz operating voltage 4 13 20 External capacitors pF 14 C12 20 15 Internal feedback resistor VDD 5 0 800 kQ Crystal oscillator 2 Fig 1 5 2 16 Crystal frequency fxtal2 VDD 2 0 V 2 3 V to 5 5 32 768 kHz 17 20 External capasitors pF 18 C22 20 19 Internal feedback resistor 20 VDD 5 0 V 4 5 0 1 XI 800 2 4 5 vo fxtal2 MN101C48 L1 e6 MN101C48 1 e OSC2 XO C12 C11 C22 2 7 21 22722 TL The instruction cycle is twice the clock cycle The instruction cycle is twice the clock cycle The feedback resistor is built in The feedback resistor is built in Figure 1 5 1 Crystal Oscillator 1 Figure 1 5 2 Crystal Oscillator 2 4 Refer to the values of Operating Conditions 1 to 4 on supply voltage during operation 3 Note that you should determ
340. up resistors In memory expansion mode set the bp7 of the EXADV register to be used as general I O pin or as address output pin Figure 4 5 5 Block Diagram P53 22 5 Chapter 4 Ports 4 6 4 6 1 Description ilGeneral port Setup Each bit of the port 6 control I O direction register can be set individually to set pins as input or output The control flag of the port 6 direction control register P6DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 6 direction control register PEDIR to and read the value of the port 6 input register P6IN To output data to pin set the control flag of the port 6 direction control register P6DIR to 1 and write the value of the port 6 output register P6OUT Each pin can be set individually if pull up resistor is added or not by the port 6 pull up resistor control register P6PLU Set the control flag of the port 6 pull up resistor control register PePLU to 1 to add pull up resistor At reset the P60 to P67 input mode is selected and pull up resistors are disabled high impedance output Special Function Pin Setup P60 to P67 are used as LCD driving pins Segment output as well The bp1 and 2 of the segment output control register LCCTR set if they are used as segment output pins or general I O pins In memory expansion mode P60 to P67 are output pins to
341. upt Wait cycle of address VO wait setup Hand shake mode request flag external memory BUZCK1 BUZCKO x x DLYCTR Enable buzzer Buzzer output Oscillation stabilization output frequency setup wait cycle setup EXADV2 EXADV1 0 0 0 A17 A16 address Ai5ipAt2addess 11 to 8 address N 19 30 output at memory output at memory expansion mode expansion mode expansion mode POOUT6 POOUT2 0 5 2 0 Port 0 output data Port 0 output data P1OUT4 P1OUTS P10UT2 P1OUTO 0 Port 1 output data e P2OUT7 1 Port2 output data P5OUT2 P6OUT7 6 0 6 6 5 P6OUT4 6 P6OUT2 0 0 0 0 0 0 Port 6 output data P7OUT7 P7OUT6 P7OUTS P7OUT4 P7OUTS P7OUT2 P7OUT1 P7OUTO Port 7 output data P8OUT6 5 P80UT3 P80UT2 P8OUT1 P8OUTO 0 0 0 0 0 Port 8 output data SYSMD7 SYSMD5 SYSMD4 SYSMD3 SYSMD1 SYSMDO 0 0 0 0 0 0 VO port Synchronous output contro Note x Initial value is unstable No data Special Function Registers List XIII 13 Chapter 13 Appendices Bit Symbol Initial Value Description Address Register 20 Port 0 input data 21 Port 1 input data P2INO xS3F22 25 Port 5 input data P6IN2 P6IN1 26 27 Port 7 input data P8IN4 P
342. urce selection and the setting value of the compare register 5 in advance If the binary counter TM5BC reaches the setting value of the compare register an interrupt is generated at the next count clock then binary counter is cleared and counting is restarted from x 00 Table 7 3 1 shows clock source that can be selected Table 7 3 1 Clock Source at Timer Operation Timer 5 Clock source One count time fosc 50 ns fs 4 400 ns fx 30 5 us fosc x 1 2 13 409 6 us fx x 1 2 13 250 ms fosc 20 MHz fx 32 768 kHz calculated as fs fosc 2 10 MHz 1 Timer 5 cannot stop its timer counting except at standby mode STOP mode 8 bit Free running Timer VII 7 Chapter 7 Time Base Timer 8 bit Free running Timer B8 bit Free running Timer as a 1 minute timer a 1 5 Table 7 3 2 shows the clock source selection and the TM5OC register setup when a 8 bit free running timer is used as a 1 minute timer a 1 second timer Table 7 3 2 1 minute timer 1 second timer Setup Timer 5 Clock Source Register 1 min fx x 1 213 xEF fx x 1 21 x1F fx x 1 218 x03 fx 2 32 768 kHz When the 1 minute timer 1 min is set on Table 7 3 2 the bp1 waveform frequency cycle of the TMBBC register is 1 Hz 1 s So that can be used for adjusting the seconds 5 Bee E 1Hz 1 8 Figure 7 3 1 W
343. ut by the DLYCTR register When not used for buzzer output this pin can be used as a normal VO pin 1 14 Pin Description Chapter 1 Table 1 3 7 Pin Function Summary 5 7 Name 80 pin y o UR NOR Function Description 33 VO P14 Timer VO pin Event counter clock input pin timer output and PWM signal output pin for 16 bit timer 4 To use this pin as event clock input configure this as input by the P1DIR register In the input mode pull up resistors can be selected by the P1PLU register For timer output PWM signal output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register When not used for timer this can be used as normal VO pin SDOO 49 Output P70 A8 SEG15 Synchronous output 8 bit synchronous output pins 001 50 P71 A9 SEG14 pins Synchronous output for each bit can be selected SDO2 51 P72 A10 SEG13 individually by the synchronous output control register SDO3 52 P73 A11 SEG12 SYSMD Set to the output mode by the P1DIR SDO4 53 P74 A12 SEG11 register SDO5 54 P75 A13 SEG10 When not used for synchronous output these pins can SDO6 55 P76 A14 SEG9 be used as a normal pins SDO7 56 P77 A15 SEG8 VREF 24 power supply for Reference power supply pins for the A D converter VREF 15 A D converter Normally the values of VREF VDD and VREF VSS are power supply for used A D converter ANO
344. ut pins register Select input mode by the PODIR register and serial input mode by the serial mode register SCOMD3 These can be used as normal pins when the serial interface is not used SBTO 27 VO P02 Serial interface Clock VO pins for serial interfaces 0 clock VO pins The output configuration either CMOS push pull or n channel open drain can be selected Push pull resistors can be selected by the POPLU register Select clock for each communication mode by the PODIR register and serial mode register SCOMDS These can be used as normal pins when the serial interface is not used I 13 Pin Description Overview Chapter 1 Overview Table 1 3 6 Pin Function Summary 4 7 Name No 80 pin yo Other Function Function Description 25 Output SBOO P00 UART transmission data output pin In the serial interface in UART mode this pin is configured as the transmission data output pin The output configuration either CMOS push pull or n channel open drain can be selected Pull up resistors can be selected by the POPLU resister Select output mode by the PODIR register and serial data output by serial 0 mode register SCOMD3 This can be used as normal pin when the serial interface is not used RXD 26 Input SBIO P01 UART received data input pin In the serial interface in UART mode this pis is configured as the received data input p
345. utput P75 SDO5 SEG10 A14 55 Output P76 SDO6 SEG9 A15 56 Output P77 SDO7 SEG8 A16 40 Output P53 SEG24 LED3 DO 64 VO P80 SEGO Data pin D1 63 VO P81 SEG1 D2 62 VO P82 SEG2 D3 61 VO P83 SEG3 D4 60 VO P84 SEG4 D5 59 VO P85 SEG5 D6 58 VO P86 SEG6 D7 57 VO P87 SEG7 I 17 Pin Description Chapter 1 Overview 1 4 1 4 1 TXD SBOO P00 RXD SBIO P01 SBTO0 P02 SBO1 P03 NDK BUZZER P06 RMOUT P10 21 12 TMSIO P13 TMA4IO P14 IRQO P20 SENS IRQ1 P21 IRQ2 P22 I 18 Block Diagram Block Diagram gt P60 A0 SEG23 4 P61 A1 SEG22 P62 A2 SEG21 P63 A3 SEG20 4 8 P64 A4 SEG19 lt gt P65 A5 SEG18 4 P66 A6 SEG17 lt lt P67 A7 SEG16 Block Diagram 4 P70 SDOO0 A8 SEG15 lt lt P71 SD01 A9 SEG14 lt gt P72 SD02 A10 SEG13 4 P73 SDO3 A11 SEG12 lt P74 SD04 A12 SEG11 4 P75 SDO5 A18 SEG10 gt 76 5 6 414 5 9 gt P77 SD07 A15 SEG8 lt lt P80 DO SEGO 4 P81 D1 SEG1 P82 D2 SEG2 lt P83 D3 SEG3 4 84 04 5 4 4 P85 D5 SEG5 4 P86 D6 SEG6 lt P87 D7 SEG7 d wv 8406 a ul io 77 LLI ui o O a EOS 222 lt 28 25 x x o gt gt 25 arcc Port 5 Sub clock System cloc
346. x 03F36 R W 7 6 5 4 3 2 1 0 P6PLU _ P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLUO At reset 00000000 24 P6PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 6 pull up resistor control register P6PLU x O3F46 R W Figure 4 6 1 Port 6 Registers 1 2 Chapter 4 Ports 7 6 5 4 3 2 1 0 LCCTR SEGSEL6 SEGSEL5 SEGSEL4 SEGSEL3 Atreset 0000000 NE SEG24 SEGSELO por P53 selection 0 Port P53 1 SEG24 SEG20 to 23 SEGSEL Port P60 to P63 selection 0 Port P60 to P63 1 SEG20 to 23 SEG16 to 19 SEGSEL2 Port P64 to P67 selection 0 Port P64 to P67 1 SEG16 to 19 SEG12 to 15 SEGSEL3 Port P70 to P73 selection 0 Port P70 to P73 SEG12 to 15 SEG8 to 11 SEGSEL4 Port P74 to P77 selection 0 Port P74 to P77 SEG8 to 11 SEGA to 7 SEGSELS por P84 to P87 selection 0 Port P84 to P67 SEGA to 7 SEGO to 3 SEGSEL6 Port P80 to P83 selection 0 Port P80 to P83 1 SEGO to 3 Segment output control register LCCTR R W Figure 4 6 2 Port 6 Registers 2 2 Pot6 IV 25 Chapter 4 Ports 4 6 3 Block Diagram
347. y If the WDEN flag is to be repeatedly cleared and set at regular intervals those operations should be performed within 1 4 of the watchdog timer frequency Operation VIII 7 Chapter 8 Watchdog Timer Binterrupt Service Routine Setup Setup Procedure Description 1 Set the watchdog interrupt service routine NMICR x 03FE1 TBNZ NMICR WDIR WDPRO 1 If the watchdog timer overflows the non maskable interrupt is generated Confirm that the WDIR flag of the non maskable interrupt control register NMICR is 1 on the interrupt service routine and manage the suitable execution Proper operation right before the WDOG interrupt is not guaranteed Therefore if the WDOG interrupt is generated initialize the system 8 Operation Chapter 9 Buzzer 9 Chapter 9 Buzzer 9 1 Overview This LSI has a buzzer It can output the square wave having a frequency 1 2 to 1 21 of the system clock fs POG BUZZER pin 9 1 1 Block Diagram iBuzzer Block Diagram 1 214 fs 2 2 Reset input CH E U gt BUZZER DLYCTR M _DLYSO_ 0 9 sie BUZCKO BUZCK1 BUZOE 7 Figure 9 1 1 Block Diagram Buzzer Ix 2 Overview Chapter9 Buzzer 9 2 Control Register Oscillation Stabilization Wait Time Control Register 7 6 5 4 3 2 1 0 DLYCTR BUZOE BUZCK1
348. y an resonator maker to circuit constant OSC2 and varies depending on stray capacitance of resonator or populated circuit Circuit constant of crystal resonator or ceramic resonator which are connected to OSC1 1 Consult an resonator maker to decide it without fail Chapter 2 CPU Basics Chapter 2 CPU Basics 2 1 Overview The MN101C CPU has a flexible optimized hardware configuration It is a high speed CPU with a simple and efficient instruction set Specific features are as follows 1 Minimized code sizes with instruction lengths based on 4 bit increments The series keeps code sizes down by adopting a minimum instruction length of one byte and variable instruction lengths based on 4 bit increments 2 Minimum instruction execution time is one system clock cycle 3 Minimized register set that simplifies the architecture and supports C language The instruction set has been determined depending on the size and capacity of hardware after an analysis of embedded application programing code and creation code by C language compiler Therefore the set is simple instruction using the minimal register set required for C language compiler MN101C LSI User s Manual Architecture Instructions Table 2 1 1 Basic Specifications Structure Load store architecture Six registers Data 8 bitx 4 Address 16 bit x 2 Other PC 19 bit PSW 8 bit SP 16

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