1 Product Description
Contents
1. 50 conductor flat cable Inputs 16 each input can generate an interrupt at programmable signal transition Input Isolation All channels completely independent from each other Input Voltage 24V DC Input Current 4 2mA typical 24V input voltage Input Switching Level 12V typical minimum 7 5 maximum 14V Input Signal Debouncing Electronic debouncing with programmable debounce time 8us to 261ms in 1 024ms steps common for all inputs Wait States IOSEL no wait states INTSEL no wait states IDSEL no wait states Power Requirements Tbd Temperature Range Operating 40 C to 85 C Storage 55 C to 125 C MTBF 394420h Humidity 5 95 non condensing TIP605 User Manual Issue 1 2 Figure 2 1 Technical Specification Page 6 of 12 3 ID Prom Contents TEWS amp TECHNOLOGIES Address Function Contents 0x01 ASCII T 0x49 0x03 ASCII P 0x50 0x05 ASCII A 0x41 0x07 ASCII C 0x43 0x09 Manufacturer ID 0xB3 0x0B Model Number Ox1A 0x0D Revision 0x10 OXOF Reserved 0x00 0x11 Driver ID Low Byte 0x00 0x13 Driver ID High Byte 0x00 0x15 Number of bytes used 0x0D 0x17 CRC 0x1F 0x19 Version 10 OXOA TIP605 User Manual Issue 1 2 Figure 3 1 ID PROM Contents Page 7 of 12 TEWS amp TECHNOLOGIES 4 IP Addressing 4 11 O Addressing The complete register set of the TIP2. 8 of 12 4 4 Interrupt Enable Register Rising Edge TEWS amp TECHNOLOGIES Bit Symbol Description Access Reset Value 15 0 Bit 0 enables the interrupt of input channel 1 for the rising edge bit 15 enables interrupt of input channel 16 All other bits are equivalent 1 enabled 0 disabled R W Figure 4 4 Interrupt Enable Register Rising Edge An interrupt request on interrupt request line INTREQO of the IP bus is only generated if the global interrupt enable bit of the Global Interrupt Control Register is set to 1 4 5 Interrupt Enable Register Falling Edge Bit Symbol Description Access Reset Value 15 0 Bit 0 enables the interrupt of input channel 1 for the falling edge bit 15 enables interrupt of input channel 16 All other bits are equivalent 1 enabled 0 disabled R W Figure 4 5 Interrupt Enable Register Falling Edge An interrupt request on interrupt request line INTREQO of the IP bus is only generated if the global interrupt enable bit of the Global Interrupt Control Register is set to 1 4 6 Interrupt Status Register Rising Edge Bit Symbol Description Access Reset Value 15 0 Bit 0 reflects the interrupt request state of input 1 for the rising edge bit 15 reflects interrupt request of input 16 All other bits are equivalent Read 1 interrupt request pending 0 no i
3. from the logic circuit Each input is independent of the other inputs and can be wired different Each input has two connections at the IP I O connector input x and input x All inputs are isolated by optocoupler and against each other The input channels can be activated only in one polarity and have an external diode to prevent damage of the optocoupler by wiring the input in a wrong direction 24V Lo Input x ma Input x 24V AN Input x ET Input x External voltage 0 to 24V HER L Input x Figure 5 1 Input Wiring Options TIP605 User Manual Issue 1 2 Page 11 of 12 TEWS amp TECHNOLOGIES 6 Pin Assignment I O Connector Pin Function 1 Input 1 2 Input 1 3 Input 2 4 Input 2 5 Input 3 6 Input 3 7 Input 4 8 Input 4 9 Input 5 10 Input 5 11 Input 6 12 Input 6 13 Input 7 14 Input 7 15 Input 8 16 Input 8 17 Input 9 18 Input 9 19 Input 10 20 Input 10 21 Input 11 22 Input 11 23 Input 12 24 Input 12 25 Input 13 26 Input 13 27 Input 14 28 Input 14 29 Input 15 30 Input 15 31 Input 16 32 Input 16 Figure 6 1 Input VO Connection TIP605 User Manual Issue 1 2 Page 12 of 12
4. 605 is accessible in the VO space of the IP Address rage ip io base address 0x00 to Ox0F Address Symbol Description Size Bit Access 0x00 DATAREG Input Data Register word R 0x03 INTCONT Global Interrupt Control Register byte R W 0x04 INTENALH Interrupt Enable Rising Edge word R W 0x06 INTENAHL Interrupt Enable Falling Edge word R W 0x08 INSTATLH Interrupt Status Rising Edge word R W Ox0A INTSTATHL Interrupt Status Falling Edge word R W 0x0D INTVEC Interrupt Vector Register byte R W OXOF DEBTIME Debounce Time Register byte R W Figure 4 1 Register Set All registers are set to 0 after reset 4 2 Input Data Register The Input Data Register is a read only register that reflects the actual states of inputs Bit Symbol Description Access Reset Value 15 0 16 bit input data R Figure 4 2 Input Data Register 4 3 Global Interrupt Control Register Bit Symbol Description Access Reset Value 7 Int Reg Global Interrupt Request flag R Read as 1 an interrupt request of at least one of the 16 input channels is pending 6 1 Not used and undefined during reads 0 Int Global Interrupt Enable Bit R W Enable 4 globally enables interrupts for all 16 inputs on interrupt request line INTREQO of the IP bus Figure 4 3 Global Interrupt Control Register TIP605 User Manual Issue 1 2 Page
5. NNn KERE Ak RA Nana nana ER RR KEER annan annnm ERG anna 10 4 9 Debounce Timer Register esse ske ER KERKE KEER ER RE AK KA AR REG ER KEER KERE AR RAAK ERGER KERE Ak nana KERR Ke ER ae 10 INSTALLATION sie ie Ge ee ed oe oe ae Ee Ge ae ee n ee ee Ge ER ae Re ee id 11 5 1 Ed ie EE N N EE EE EE N 11 PIN ASSIGNMENT VO CONNECTOR 2aa2aaaaaaaannnan aannnunnnnnnnnnnnnnunnnnnnnnnnnnnunnnn nana 12 TIP605 User Manual Issue 1 2 Page 3 of 12 FIGURE 1 1 FIGURE 2 1 FIGURE 3 1 FIGURE 4 1 FIGURE 4 2 FIGURE 4 3 FIGURE 4 4 FIGURE 4 5 FIGURE 4 6 FIGURE 4 7 FIGURE 4 8 FIGURE 4 9 FIGURE 5 1 FIGURE 6 1 TEWS amp TECHNOLOGIES Table of Figures BLOCK DIAGRAM ee ee ee ee Ge Ge Ge e GR RR GRA GRA RA v a Re ee ee ee Re ee ee k Ge ee ee 5 TECHNICAL SPECIFICATION aiaiaaiaaaaaaaaaaasaasaaanassnanansaannanaannnnnannnanansnannnannnnannansnnnnanannnnnnannannanani 6 I dsie kere Kid ES ER EE alu lal vaa sis saravt ARa 7 REGISTER Ed nana dsa eE i ae aia 8 INPUT DATA REGISTER 1172 00 amts lovandi RR See Ee sae Ee eg GE Gee Gee ee eu OR AEN eg Deb se 8 GLOBAL INTERRUPT CONTROL REGISTER ee ee ese ee ee ee ee se ee ge ee ee ee ee ee ee ee Ge ee ee ee ee Ge ee 8 INTERRUPT ENABLE REGISTER RISING EDGE ee ese ee se ee ee ee ee ee ee ee een ee ee ee ee ee ee ee ee ee ee ee ee 9 INTERRUPT ENABLE REGISTER FALLING EDGE esse ee se se ee ee ee ee ee ee ee ee ee ee ee ee see ee ee ee ee ee 9 INTERRUPT STATUS REGISTER
6. RISING EDGE ese ee se ee ee ee ee ee ee ee ee see ee ee ee ee ee ee ee ee ee ee ee 9 INTERRUPT STATUS REGISTER FALLING EDGE ese ee ee se ee se ee ee ee ee ee ese ee ee ee ee ee ee ee ee ee 10 INTERRUPT VECTOR REGISTER esse eg eke ees dee Ge ed casein Ee ee eg Ee ka t ede bee KERE ke de Bed ie 10 DEBOUNGE TIMER REGISTER 111170 cscs Ese Ee Gee ee de ee ne op Eed sed Ge ee Ge Ee ese dis EE de ee VER ke Ee h a 10 INPUT WIRING OP TIONS iis is EE RE DER Es Oe RE ee oe Re NESER Re Ge Ee AD BERE dee ee bene bek eb eed 11 INPUT VO CONNECTION EE RE RE EO EE 12 TIP605 User Manual Issue 1 2 Page 4 of 12 TEWS amp TECHNOLOGIES 1 Product Description The TIP605 is an IndustryPack compatible module with 16 digital inputs galvanically isolated by optocoupler The individual inputs are potential free in relation to each other A high performance input circuit ensures a defined switching point and polarization protection against confusing the pole All inputs have an electronic debounce circuit with a freely programmable debounce time All inputs can generate an interrupt The signal edge handling is programmable For the TIP605 the operating temperature range is 40 C to 85 C 16 Opto 16 Input couplers Circuits ID PROM Figure 1 1 Block Diagram TIP605 User Manual Issue 1 2 Page 5 of 12 TEWS amp TECHNOLOGIES Technical Specification Logic Interface Single Size IndustryPack Logic VO Interface
7. TEWS S The Embedded VO Company TECHNOLOGIES TIP605 16 Digital Inputs Optically Isolated Version 1 0 User Manual Issue 1 1 April 2003 D75605800 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany 1 E Liberty Street Sixth Floor Reno Nevada 89504 USA Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 Phone 1 775 686 6077 Fax 1 775 686 6024 e mail info tews com www tews com e mail usasales tews com www tews com TIP605 10 16 digital inputs optically isolated Issue 1 0 1 1 TIP605 User Manual Issue 1 2 General Revision TEWS S TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix 0x i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read S
8. et 1997 2003 by TEWS TECHNOLOGIES GmbH Date May 1997 April 2003 Page 2 of 12 DON TEWS amp TECHNOLOGIES Table of Contents PRODUCT DESCRIP TIOM ee ie ee IG ee N Ge ke ees 5 TECHNICAL SPECIFIGATION soes ses es sakedae ens Ges dd NAN eed dee ee Rd Wa NA kes Ne RGN WRANG Nee dd 6 IDPROMGONITENTS issues oi es sa n N de Ge N Ge N Ge ee ee 7 IP ADDRESSING esse sk os EE ee Nek ks N Ge ees We Ke NG Es Gee EG KEN ek eN N eN ad GR 8 4 1 VO Addressing se Re ek ee Ee Be ed Ge Oe EE ee Ge ee ee GE Ke ek de ee ae ee 8 4 2 Input Data Register ee RR EER RR EE REG AR KERE GR AR KERE Ge RR KEER Ge AR KERE Ge RR KERE Ge RR KERE Ge RR RE nnm KERE Ge KERE ee RR nna ae 8 4 3 Global Interrupt Control RegisteF sees ses ke ER KEER KERE AR KA AR KEER ER Re AR KA AR RR Nanna annan anna anna KERE ee RE anna 8 4 4 Interrupt Enable Register Rising Edge ee ee esse ee ese RR EER RR KEER Ge RR KERR RR KERE Ge RR EE Re GR RR RE Ee annan 9 4 5 Interrupt Enable Register Falling Edge 22222 se ee esse ee ER Re ER KERR e ER RR Ke RR KERE Ge RR KERE SR RR KERKE Ge ERK Ee 9 4 6 Interrupt Status Register Rising Edge a2ua22uaaaaaaaaaaaaaaannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnannnanana 9 4 7 Interrupt Status Register Falling Edge 2uaa2aaaanaaan nan sansnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnannn annan 10 4 8 Interrupt Vector Register a22 2222 aaa aaaansnannnnnnnnnnnnnnnnnnnnnnnnn
9. nterrupt request pending Write 1 clear pending interrupt request for a specific input R W Figure 4 6 Interrupt Status Register Rising Edge TIP605 User Manual Issue 1 2 Page 9 of 12 4 7 Interrupt Status Register Falling Edge TEWS amp TECHNOLOGIES Bit Symbol Description Access Reset Value 15 0 Bit 0 reflects the interrupt request state of input 1 for the falling R W edge bit 15 reflects interrupt request of input 16 All other bits are equivalent Read 1 interrupt request pending 0 no interrupt request pending Write 1 clear pending interrupt request for a specific input Figure 4 7 Interrupt Status Register Falling Edge 4 8 Interrupt Vector Register Bit Symbol Description Access Reset Value 7 0 8 bit interrupt vector is loaded by software R W Figure 4 8 Interrupt Vector Register 4 9 Debounce Timer Register Bit Symbol Description Access Reset Value 7 0 Value 0 sets the debounce time to a minimum of 8us default R W after reset The debounce time can be programmed in steps of 1 024ms in the range of 8us to 261ms The debounce time is common for all inputs debounce time ms 1 024 ms preload value Figure 4 9 Debounce Timer Register TIP605 User Manual Issue 1 2 Page 10 of 12 TEWS amp TECHNOLOGIES 5 Installation 5 1 Input Wiring Each input is optically isolated
Download Pdf Manuals
Related Search