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LPC11U2x - NXP Semiconductors

1. Footprint information for reflow soldering of LQFP48 package SOT313 2 Hx gt Gx gt gt P2 P1 Wal A PA EA IZ i TH HANNON ccu 24 ZZ 222 ene Ease IZ 2221 mm 4 pope ZZ 221 2 ZA A 222 Hy Gy EE ZEE By Ay 14 222 2224 a eke ZZ zc t 55 ZA ZZ 222 ZZ ZA 3 i 1 Y Y t t 4 H 4 NORA ROUGHER roe C Miva A A A A ud t d D2 8x d L D1 E Bx nl Ax gt Generic footprint pattern Refer to the package outline drawing for actual layout A solder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By D1 D2 Gx Gy Hx Hy 0 500 0 560 10 350 10 350 7 350 7 350 1 500 0 280 0 500 7 500 7 500 10 650 10 650 501313 2 Fig 41 Reflow soldering for the LQFP48 package LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 66 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of TFBGA48 package SOT1155 2 P OO OO OO ere OO OO OO OO solder land solder paste deposit 94 solder land plus solder paste oc
2. detail X DIMENSIONS mm are the original dimensions UNIT Ai A2 bp 0 25 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT313 2 136E05 MS 026 03 02 25 ISSUE DATE Fig 36 Package outline LQFP48 SOT313 2 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 61 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4mm DIMENSIONS mm are the original dimensions SOT314 2 detail X UNIT A max A2 bp c 1 6 Note 1 Plastic or me al protrusions of 0 25 mm maximum per side are not inclu
3. Table 8 Power consumption for individual analog and digital blocks Peripheral Typical supply current Notes mA n a 12 MHz 48 MHz IRC 0 27 System oscillator running PLL off independent of main clock frequency System oscillator 0 22 IRC running PLL off independent of main clock at 12 MHz frequency Watchdog 0 004 System oscillator running PLL off independent oscillator at of main clock frequency 500 kHz 2 BOD 0 051 Independent of main clock frequency Main PLL 0 21 ADC 0 08 0 29 CLKOUT 0 12 0 47 Main clock divided by 4 the CLKOUTDIV register CT16BO 0 02 0 06 CT16B1 0 02 0 06 CT32BO 0 02 0 07 CT32B1 0 02 0 06 GPIO 0 23 0 88 GPIO pins configured as outputs and set to LOW Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register IOCONFIG 0 03 0 10 12 0 04 0 13 ROM 0 04 0 15 SPIO 0 12 0 45 SPI1 0 12 0 45 UART 0 22 0 82 WWDT 0 02 0 06 Main clock selected as clock source for the WDT USB 1 2 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 40 of 74 NXP Semiconductors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller 9 4 Electrical pin characteristics
4. 20 10 bit ADG antes 20 5 20 General purpose external event 5 20 E6atUles arbenni nt REGI 20 System tick 21 Windowed WatchDog Timer WWDT 21 Feat res ls odi ERE 21 Clocking and power control 22 Integrated oscillators 22 Internal RC oscillator 23 System oscillator 24 Watchdog oscillator 24 System PLL and USB PLL 24 Clock 24 Wake up process 24 All information provided this document is subject to legal disclaimers 7 17 5 7 17 5 1 7 17 5 2 7 17 5 3 7 17 5 4 7 17 5 5 7 17 6 7 17 6 1 7 17 6 2 7 17 6 3 7 17 6 4 7 17 6 5 7 17 6 6 7 18 9 1 9 2 9 3 9 4 10 10 1 10 2 10 3 10 4 10 5 10 6 10 7 11 11 1 11 2 11 3 11 4 11 5 11 6 11 7 12 13 14 15 16 17 17 1 17 2 17 3 Power 24 Power profiles 25 Sleep mode 25 Deep sleep 25 Power down 25 Deep power down mode 26 System 26 a ahead E 26 Brownout detection 26
5. tCHCL Toy clk 002aaa907 Fig 21 External clock timing with an amplitude of at least Viigus 200 mV Internal oscillators Table 12 Dynamic characteristics IRC Tamb 40 to 85 2 7 V lt lt 3 6 1 Symbol Parameter Conditions Min Unit fosc RC internal RC oscillator 11 88 12 12 12 MHz frequency 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 12 15 002aaf403 f MHz VDD 3 6V 3 3V 3 0 V 12 05 27V 2 4 V 2 0 V 11 95 11 85 40 15 10 35 60 85 temperature C Conditions Frequency values are typical values 12 MHz 1 accuracy is guaranteed for 2 7 V lt Vpp 3 6 V and Tamb 40 C to 85 C Variations between parts may cause the IRC to fall outside the 12 MHz 1 96 accuracy specification for voltages below 2 7 V Fig 22 Internal RC oscillator frequency versus temperature Table 13 Dynamic characteristics Watchdog oscillator Symbol Parameter Conditions Min Typ Max Unit fosc int internal oscillator DIVSEL Ox1F FREQSEL Ox1 IS 7 8 kHz frequency the WDTOSCCTRL register DIVSEL 0x00 FREQSEL 1700 kHz in the WDTOSCCTRL
6. 2 3 6 002aae990 VoH T 85 C 25 3 2 40 C 2 8 2 4 2 0 10 20 30 40 50 60 mA Conditions Vpp 3 3 V on pin PIOO_7 Fig 15 High drive output Typical HIGH level output voltage versus HIGH level output current 2aaf01 60 002aaf019 loL T 85 C mA 25 40 40 20 0 0 0 2 0 4 0 6 VoL V Conditions Vpp 3 3 V on pins PIOO 4 and PIOO 5 Fig 16 I C bus pins high current sink Typical LOW level output current lo versus LOW level output voltage VoL All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 41 of 74 NXP Semiconductors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller 15 002 991 lot T 85 C mA 25 40 C 10 5 0 0 0 2 0 4 0 6 VoL V Conditions Vpp 3 3 V standard port pins and PIOO 7 Fig 17 Typical LOW level output current loj versus LOW level output voltage VoL 002aae992 3 6 24 mA Conditions Vpp 3 3 V standard port pins Fig 18 Typical HIGH level output voltage Voy versus HIGH level output source current lon All information provided in this document is subject to legal disclaimers
7. Table 19 Recommended values for in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors 15 MHz to 20 MHz 10 pF 1800 18 pF 18 pF 20 pF 1000 39 pF 39 pF 20 MHz to 25 MHz 10 pF 1600 18 pF 18 pF 20 pF 800 39 pF 39 pF 11 3 XTAL Printed Circuit Board PCB layout guidelines Follow these guidelines for PCB layout LPC11U2X Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors Cx2 and in case of third overtone crystal use have a common ground plane Connect the external components to the ground plain To keep parasitics and the noise coupled in via the PCB as small as possible keep loops as small as possible Choose smaller values of and if parasitics of the PCB layout increase All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 55 of 74 NXP Semiconductors LPC11U2x 11 4 LPC11U2X 32 bit ARM Cortex M0 microcontroller Standard I O pad configuration Figure 31 shows the possible pin modes for standard I O pins with analog input function Digital
8. LPC11U2x BUS 32 bit ARM microcontroller up to 32 kB flash up to 10 kB SRAM and 4 kB EEPROM USB device USART Rev 2 3 27 March 2014 Product data sheet 1 General description The LPC11U2x are an ARM based low cost 32 bit MCU family designed for 8 16 bit microcontroller applications offering performance low power simple instruction set and memory addressing together with reduced code size compared to existing 8 16 bit architectures The LPC11U2x operate at CPU frequencies of up to 50 MHz Equipped with a highly flexible and configurable Full Speed USB 2 0 device controller the LPC11U2x brings unparalleled design flexibility and seamless integration to today s demanding connectivity solutions The peripheral complement of the LPC 11U2x includes up to 32 kB of flash memory up to 10 kB of SRAM data memory 4 EEPROM one Fast mode Plus I C bus interface one RS 485 EIA 485 USART with support for synchronous mode and smart card interface two SSP interfaces four general purpose counter timers a 10 bit ADC Analog to Digital Converter and up to 54 general purpose I O pins For additional documentation related to the LPC11U2x parts see Section 15 References 2 Features and benefits W System ARM Cortex MO processor running at frequencies of up to 50 MHz ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC
9. 71 Data sheet 5 71 Definitions 2 2 eee 71 Disclaimers 71 continued gt gt NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 73 of 74 NXP Semiconductors LPC11U2x 17 4 18 19 Tradetmatks cr Re Contact information Contents 32 bit ARM Cortex M0 microcontroller Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information 2014 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 27 March 2014 Document identifier LPC11U2X
10. LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 68 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 14 Abbreviations Table 20 Abbreviations Acronym Description A D Analog to Digital ADC Analog to Digital Converter AHB Advanced High performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input Output JTAG Joint Test Action Group PLL Phase Locked Loop RC Resistor Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TAP Test Access Port USART Universal Synchronous Asynchronous Receiver Transmitter 15 References 1 LPC11U2x User manual UM10462 http Awww nxp com documents user_manual UM10462 pdf 2 LPC11U2x Errata sheet http www nxp com documents errata sheet ES LPC11U2X pdf LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 69 of 74 NXP Semiconductors LPC11U2x 16 Revision history 32 bit ARM Cortex M0 microcontroller Table 21 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11U2x v 2 3
11. All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 37 of 74 NXP Semiconductors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller 4 002aag751 IDD mA 3 48 MHz 2 Lo 36 2 eel 24 2 2 ee es 4 12 MHz 0 40 15 10 35 60 85 temperature C Conditions Vpp 3 3 V Sleep mode entered from flash internal pull up resistors disabled BOD disabled all peripherals disabled the SYSAHBCLKCTRL register all peripheral clocks disabled low current mode USB DP and USB DM pulled LOW externally 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 11 Typical supply current versus temperature in Sleep mode 002aag745 385 IDD pA 375 365 355 40 15 10 35 60 85 temperature C Conditions BOD disabled all oscillators and analog blocks turned off in the PDSLEEPCFG register USB DP and USB DM pulled LOW externally Fig 12 Typical supply current versus temperature in Deep sleep mode All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 38 of 74 NXP Semiconduc
12. 27 March 2014 36 of 74 NXP Semiconductors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller 002aag749 lop 48 MHz mA es 36 MHz 2 24 2 2 E 12 2 1 ee Vpp V Conditions Tamb 25 C Active mode entered executing code 1 1 from flash internal pull up resistors disabled BOD disabled all peripherals disabled in the SYSAHBCLKCTRL register all peripheral clocks disabled low current mode USB DP and USB DM pulled LOW externally 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 9 Typical supply current versus regulator supply voltage Vpp in active mode 002aag750 lop 48 MHz mA _ 36 MHz 2 DECRE EMEN c 24 MHz 2 Me MM 3 12 MHz 1 0 40 15 10 35 60 85 temperature C Conditions Vpp 3 3 Active mode entered executing code while 1 from flash internal pull up resistors disabled BOD disabled all peripherals disabled in the SYSAHBCLKCTRL register all peripheral clocks disabled low current mode USB_DP and USB_DM pulled LOW externally 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 10 Typical supply current versus temperature in Active mode
13. 9 5 45 5 V Vpp 2 1 8 V Vpp 20V 0 5 3 6 5 tolerant open drain pins 214 0 5 45 5 PIOO 4 and PIOO 5 ViA analog input voltage pin configured as analog input 2 0 5 4 6 V 3 Ipp supply current per supply pin 100 mA Iss ground current per ground pin 100 mA latch I O latch up current 0 5Vpp lt lt 1 5Vpp 100 mA Tj 125 C storage temperature non operating 6 65 150 C maximum junction 150 C temperature Ptot pack total power dissipation per based on package heat 1 5 transfer device power consumption Vesp electrostatic discharge human body model all pins 1 6500 V voltage 1 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted c The limiting values are stress ratings only Operating the part at these values is not recommended and proper operation is not guaranteed The conditions for functional operation are specified in Table 5 2 Maximum minimum voltage above the maximum operating voltage see Table 5 and bel
14. RS 339 gt USB 887330 Vss aaa 010178 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 52 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller For a bus powered device the VBUS signal does not need to be connected to the USB_VBUS pin see Figure 28 The USB_CONNECT function can additionally be connected as shown in Figure 27 to prevent the USB from timing out when there is a significant delay between power up and handling USB traffic Fig 28 USB interface on a bus powered device V REGULATOR LPC1xxx R1 1 5kQ VBUS T USB DP Rs 330 gt USB B USB DM Rs 330 Vss aaa 010179 LPC11U2X Remark When a bus powered circuit as shown in Figure 28 is used configure the PIOO_3 USB_VBUS pin for GPIO PIOO 3 in the IOCON block to ensure that the USB_CONNECT signal can still be controlled by software For details on the soft connect feature see the LPC 11U2x user manual Ref 1 Remark When self powered circuit is used without connecting VBUS configure the PIOO S USB VBUS pin for GPIO PIOO 3 and provide software that can detect the host presence through some other mecha
15. Rev 2 3 27 March 2014 35 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 9 1 static characteristics Table 7 BOD static characteristics Tamb 25 Symbol Parameter Conditions Min Typ Max Unit Vin threshold voltage interrupt level 1 assertion 2 22 de assertion 2 35 interrupt level 2 assertion 2 52 de assertion 2 66 interrupt level 3 assertion 2 80 de assertion 2 90 reset level 0 assertion 1 46 de assertion 1 63 reset level 1 assertion 2 06 de assertion 2 15 reset level 2 assertion 2 35 de assertion 2 43 reset level 3 assertion 2 63 de assertion 2 71 1 Interrupt levels are selected by writing the level value to the BOD control register BODCTRL see the LPC11Uxx user manual 9 2 Power consumption Power measurements in Active Sleep and Deep sleep modes were performed under the following conditions see the LPC 11Uxx user manual Configure all pins as GPIO with pull up resistor disabled in the IOCON block Configure GPIO pins as outputs using the GPIOnDIR registers Write 0 to all GPIOnDATA registers to drive the outputs LOW LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3
16. 20140327 Product data sheet LPC11U2X v 2 2 Part LPC11U22FBD48 301 added LPC11U2X v 2 2 20140311 Product data sheet LPC11U2X v 2 1 Modifications Updated Section 11 1 Suggested USB interface solutions for clarity Open drain 1 C bus and RESET pin descriptions updated for clarity See Table LPC11U2X v 2 1 20130917 Product data sheet LPC11U2X v 2 Modifications Number of CAP and MAT functions for timers updated in Figure 1 Table 3 Added 5 V tolerant pad to RESET PIOO 0 table note Table 7 Removed BOD interrupt level 0 Added Section 11 6 ADC effective input impedance Programmable glitch filter is enabled by default See Section 7 7 1 Table 5 Static characteristics added Pin capacitance section Updated Section 11 1 Suggested USB interface solutions Table 4 Limiting values Updated Vpp min and max Updated conditions Table 10 EEPROM characteristics Removed fak and ter the user does not have control over these parameters Changed the tprog from 1 1 ms to 2 9 ms the EEPROM IAP always does an erase and program thus the total program time is ter tprog Changed title of Figure 29 from USB interface on a self powered device to USB interface with soft connect e Section 10 7 USB interface added Parameter teopri and teopre renamed to tgopn LPC11U2X v 2 20120113 Product data sheet
17. Functional description 7 1 On chip flash programming memory The LPC11U2x contain 24 kB or 32 kB on chip flash program memory The flash can be programmed using In System Programming ISP or In Application Programming IAP via the on chip boot loader software 7 2 EEPROM The LPC11U2x contain 1 kB 2 kB or 4 kB of on chip byte erasable and byte programmable EEPROM data memory The EEPROM can be programmed using In Application Programming IAP via the on chip boot loader software LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 14 of 74 NXP Semiconductors LPC11U2x LPC11U2X 7 3 7 4 7 5 32 bit ARM Cortex M0 microcontroller SRAM The LPC11U2x contain a total of 8 or 10 on chip static RAM memory On chip ROM The on chip ROM contains the boot loader and the following Application Programming Interfaces APIs In System Programming ISP and In Application Programming IAP support for flash AP support for EEPROM USB API Power profiles for configuring power consumption and PLL settings 32 bit integer division routines Memory map The LPC11U2x incorporates several distinct memory regions shown in the following figures Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address r
18. LPC11U2X v 1 Modifications Use of USB with power profiles specified Section 7 17 5 1 Power consumption data added in Section 9 2 SSP dynamic characteristics added Table 16 RC dynamic characteristics added Table 12 Data sheet status changed to Product data sheet LPC11U2X v 1 20111129 Preliminary data sheet LPC11U2X All information provided in this document is subject to legal disclaimers Product data sheet Rev 2 3 27 March 2014 70 of 74 NXP B V 2014 All rights reserved NXP Semiconductors LPC11U2x 17 Legal information 32 bit ARM Cortex M0 microcontroller 17 1 Data sheet status Document status 1I2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest pr
19. NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 42 of 74 NXP Semiconductors 002aae988 Vi Conditions Vpp 3 3 V standard port pins Fig 19 Typical pull up current ly versus input voltage Vj 2 80 002 989 85 p 25 uA ee 60 40 20 0 0 1 2 3 4 5 Vi V Conditions Vpp 3 3 V standard port pins Fig 20 Typical pull down current 1 versus input voltage Vi LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 LPC11U2x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors LPC11U2x 10 Dynamic characteristics 32 bit ARM Cortex M0 microcontroller 10 1 Flash memory Table9 Flash characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 11 140000 100000 cycles tret retention time powered 10 years unpowered 20 years ter erase time sector or multiple 95 100 105 ms consecutive sectors torog programming time 12 0 95 1 1 05 ms 1 Number of program erase cycles 2 Programming times are given for writing 256 bytes from RAM to the flas
20. us Fast mode Plus 0 26 us data hold time 3 71 8 Standard mode 0 us Fast mode 0 us Fast mode Plus 0 us tsu DAT data set up time 9110 Standard mode 250 ns Fast mode 100 ns Fast mode Plus 50 ns 1 See the I C bus specification UM10204 for details 2 Parameters are valid over operating temperature range unless otherwise specified 3 device must internally provide a hold time of at least 300 ns for the SDA signal with respect to the Vj4 min of the SCL signal to bridge the undefined region of the falling edge of SCL 4 Cp total capacitance of one bus line in pF 5 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified t 6 Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 46 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 7 The maximum typ pat could be 3 45 us and 0 9 us for St
21. Non Maskable Interrupt NMI input selectable from several input sources System tick timer B Memory Up to 32 kB on chip flash program memory Up to 4 kB on chip EEPROM data memory byte erasable and byte programmable Up to 10 kB SRAM data memory 16 kB boot ROM In System Programming ISP and In Application Programming IAP for flash and EEPROM via on chip bootloader software ROM based USB drivers Flash updates via USB supported ROM based 32 bit integer division routines Debug options NXP Semiconductors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller Standard JTAG Joint Test Action Group test interface for BSDL Boundary Scan Description Language Serial Wire Debug Digital peripherals Up to 54 General Purpose I O GPIO pins with configurable pull up pull down resistors repeater mode and open drain mode Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins High current source output driver 20 mA on one pin High current sink driver 20 mA on true open drain pins Four general purpose counter timers with a total of up to 5 capture inputs and 13 match outputs Programmable Windowed WatchDog Timer WWDT with a dedicated internal low power WatchDog Oscillator WDO Ana
22. boosted to a higher frequency up to the maximum CPU operating frequency by the system PLL Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU the watchdog timer or the CLKOUT pin The watchdog oscillator nominal frequency is programmable between 7 8 kHz and 1 7 MHz The frequency spread over processing and temperature is 40 see also Table 13 System PLL and USB PLL The LPC11U2x contain a system PLL and a dedicated PLL for generating the 48 MHz USB clock The system and USB PLLs are identical The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz To support this frequency range an additional divider keeps the CCO within its frequency range while the PLL is providing the desired output frequency The output divider can be set to divide by 2 4 8 or 16 to produce the output clock The PLL output frequency must be lower than 100 MHz Since the minimum output divider value is 2 it is insured that the PLL output has a 50 96 duty cycle The PLL is turned off and bypassed following a chip reset Software can enable the PLL later The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settlin
23. 0 PIOO 9 MOSIO 18 F7 28 37 EPU PIOO 9 General purpose digital input output CT16B0_MAT1 y o MOSIO Master Out Slave In for SSPO O CT16BO 1 Match output 1 for 16 bit timer 0 SWCLK PIOO 10 SCK0 19 E7 29 38 SWCLK Serial wire clock and test clock TCK for CT16BO_MAT2 JTAG interface PIOO 10 General purpose digital input output pin SCKO Serial clock for SSPO CT16B0_MAT2 Match output 2 for 16 bit timer 0 TDI PIOO_11 ADO 21 08 32 42 li PU TDI Test Data for JTAG interface CT32B0_MAT3 VO PIOO 11 General purpose digital input output pin ADO converter input 0 CT32BO Match output for 32 bit timer 0 TMS PIOO 12 AD1 22 C7 33 44 6 PU TMS Test Mode Select for JTAG interface CT32B1 CAPO ET PIO 12 General purpose digital input output pin AD1 A D converter input 1 CT32B1 Capture input 0 for 32 bit timer 1 TDO PIOO 13 AD2 23 C8 34 45 TDO Test Data Out for JTAG interface CT32B1 MATO E PIOO 13 General purpose digital input output pin AD2 A D converter input 2 CT32B1_MATO Match output 0 for 32 bit timer 1 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 10 of 74 NXP Semicond
24. 1 7 14 7 14 1 7 15 7 16 7 16 1 7 17 7 17 1 7 17 1 1 7 17 1 2 7 17 1 3 7 17 2 7 17 3 7 17 4 LPC11U2X General 1 Features and benefits 1 5 3 Ordering 3 Ordering 5 3 Block diagram 4 Pinning 5 PINNING cioe ec ET Bd a 5 Pin description 9 Functional description 14 On chip flash programming memory 14 EEPROM iesu sure xar 14 SRAM EET 15 On chip ROM 15 Memory 15 Nested Vectored Interrupt Controller NVIC 16 5 16 Interrupt 5 17 IOCON block 17 EeatUres cius oh odes x eek ae 17 General Purpose Input Output GPIO 17 5 18 USB interface 18 Full speed USB device controller 18 FeatUresS iius pe 18 USART i 18 5 19 SSP serial I O 19 5 19 I C bus serial I O controller 19 5
25. 4 V 2 pins configured 20 mA current as Fast mode Plus pins 2 0 V lt Vpp lt 3 6 V 1 8 V lt 2 0 V 16 lu input leakage current V Vpp 15 2 4 uA Vi 5V 10 22 uA Oscillator pins Vi xtal crystal input voltage 0 5 1 8 1 95 V Vowtal crystal output voltage 0 5 1 8 1 95 USB pins loz OFF state output fl 10 uA current VBus bus supply voltage 2 5 25 V Vpi differential input D D 2 0 2 sensitivity voltage Vom differential common includes Vp range 2 10 8 2 5 V mode voltage range Vi rsse single ended receiver 2 0 8 2 0 switching threshold voltage VoL LOW level output for low full speed 2 0 18 voltage of 1 5 to 3 6 V Vou HIGH level output driven for low full speed 2 2 8 3 5 V voltage of 15 to GND Cirans transceiver capacitance pin to GND 2 20 pF Zpnv driver output with 33 Q series resistor steady state 118121 36 E 44 1 Q impedance for driver drive which is not high speed capable LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 32 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 5 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Condition
26. 5 32 Vpp PIO1 13 TRST PIOO 14 TDO PIOO 13 TMS PIOO 12 PIO1 11 TDI PIOO 11 PIO1 29 PIOO_22 PIO1_8 SWCLK PIOO 10 PIO0 9 8 PIO1 21 PIO1 2 Vpp LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 8 of 74 NXP Semiconductors LPC11U2x 6 2 Pin description Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO port number The default function after reset is listed first All port pins have internal pull up resistors enabled after reset except for the true open drain pins PIOO_4 and Table 3 PIOO_5 32 bit ARM Cortex M0 microcontroller Every port pin has a corresponding IOCON register for programming the digital or analog function the pull up pull down configuration the repeater and the open drain modes The USART counter timer and SSP functions are available on more than one port pin Pin description Symbol Reset state Description RESET PIOO 0 N Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 RESET External reset input with 20 ns glitch filter A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 This pin also serves as the debug sele
27. 5 4 LPC11U2X 32 bit ARM Cortex M0 microcontroller consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider which provides even better power control Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile The power configuration routine configures the LPC11U2x for one of the following power modes Default mode corresponding to power configuration after reset CPU performance mode corresponding to optimized processing capability Efficiency mode corresponding to optimized balance of current consumption and CPU performance Low current mode corresponding to lowest power consumption In addition the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock Remark When using the USB configure the LPC11U2x in Default mode Sleep mode When Sleep mode is entered the clock to the core is stopped Resumption from the Sleep mode does not need any special sequence but re enabling the clock to the ARM core In Sleep mode execution of instructions is suspended until either a reset or interrupt occurs Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the proces
28. Code security Code Read Protection CRP 26 APB 27 eae Lem Ped ete 27 External interrupt inputs 27 Emulation and debugging 28 Limiting values 29 Static characteristics 30 BOD static characteristics 36 Power consumption 36 Peripheral power consumption 39 Electrical pin characteristics 41 Dynamic characteristics 44 Flash memory 44 External 44 Internal oscillators 45 WO SOUS eos aR pe 46 Hen inc ele 46 SSP 48 USB interface 51 Application information 52 Suggested USB interface solutions 52 Inputs ee eee bags 53 XTAL Printed Circuit Board PCB layout guideliries zi mu IER ew aS 55 Standard I O pad configuration 56 Reset pad 57 ADC effective input 57 ADC usage 58 Package 59 Soldering 64 Abbreviations 69 69 Revision history 70 Legal information
29. VoL LOW level output 2 0 V lt Vpp x 3 6 V lop 4 mA 0 4 V voltage 1 8 V lt Vpp lt 2 0 V lo mA 0 4 V lou HIGH level output Vou Vpp 0 4 V 20 mA current 25V lt Vpop lt 3 6 V 1 8 V lt Vpp lt 2 5 V 12 mA lo LOW level output VoL 0 4 V 4 mA current 20V Vppx3 6V 1 8 lt 2 0 V 3 mA lois LOW level short circuit Voi Vpp 14 50 mA output current lod pull down current Vi 5V 10 50 150 uA lou pull up current Vi20V 15 50 85 2 0 V lt Vppx 3 6 V 1 8 lt 2 0 10 50 85 Vpp Vi lt 5 0 0 0 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 31 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 5 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit I C bus pins PIOO 4 and PIOO 5 Vin HIGH level input 0 7Vpp V voltage LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 05Vpp V lo LOW level output VoL 0 4 V 2 pins configured 3 5 mA current as standard mode pins 2 0V x Vppx 3 6 V 1 8 V lt 2 0 V 3 lot LOW level output VoL 0
30. a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 71 of 74 NXP Semiconductors LPC11U2x Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive
31. pin providing a digital function can be programmed to generate an interrupt on a level a rising or falling edge or both The GPIO block consists of three parts 1 The GPIO ports 2 The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts 3 Two GPIO group interrupt blocks to control two combined interrupts from all GPIO pins All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 17 of 74 NXP Semiconductors LPC11U2x 7 8 1 7 9 7 9 1 7 9 1 1 7 10 LPC11U2X 32 bit ARM Cortex M0 microcontroller Features GPIO pins can be configured as input or output by software All GPIO pins default to inputs with interrupt disabled at reset Pin registers allow pins to be sensed and set individually Up to eight GPIO pins can be selected from all GPIO pins to create an edge or level sensitive GPIO interrupt request Any pin or pins in each port can trigger a port interrupt USB interface The Universal Serial Bus USB is a 4 wire bus that supports communication between a host and one or more up to 127 peripherals The host controller allocates the USB bandwidth to attached devices through a token based protocol The bus supports hot plugging and dynamic configuration of the devices The host controller initiates all transactions The LPC11U2x USB interface consists of a
32. register 1 Typical ratings are not guaranteed The values listed are at nominal supply voltages All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 45 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 2 The typical frequency spread over processing and temperature Tamb 40 C to 85 C is 40 3 See the LPC11Uxx user manual 10 4 I O pins Table 14 Dynamic characteristics I O pins Tamb 40 to 85 3 0 V lt x 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3 0 5 0 ns tr fall time pin configured as output 2 5 5 0 ns 1 Applies to standard port pins and RESET pin 10 5 I C bus Table 15 Dynamic characteristic I C bus pins Tamb 40 to 85 Symbol Parameter Conditions Min Max Unit fscL SCL clock Standard mode 0 100 kHz frequency Fast mode 0 400 kHz Fast mode Plus 0 1 MHz tr fall time 131141516 of both SDA SCL 300 ns signals Standard mode Fast mode 20 0 1 x Cp 300 ns Fast mode Plus 120 ns LOW period of the Standard mode 4 7 us SCL clock Fast mode 1 3 us Fast mode Plus 0 5 us tHIGH HIGH period of the Standard mode 4 0 us SCL clock Fast mode 0 6
33. the NVIC but can have several interrupt flags Individual interrupt flags can also represent more than one interrupt Source IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Connect peripherals to the appropriate pins before activating the peripheral and before enabling any related interrupt Activity of any enabled peripheral function that is not mapped to a related pin is treated as undefined Features Programmable pull up pull down or repeater mode All GPIO pins except PIOO 4 and PIOO 5 are pulled up to 3 3 V Vpp 3 3 V if their pull up resistor is enabled Programmable pseudo open drain mode e Programmable 10 ns glitch filter on pins PIOO 22 PIOO 23 and PIOO 11 to PIOO 16 The glitch filter is turned on by default Programmable hysteresis Programmable input inverter General Purpose Input Output GPIO The GPIO registers control device pin functions that are not connected to a specific peripheral function Pins can be dynamically configured as inputs or outputs Multiple outputs can be set or cleared in one write operation LPC11U2x use accelerated GPIO functions e GPIO registers are a dedicated AHB peripheral so that the fastest possible I O timing can be achieved Entire port value can be written in one instruction Any GPIO
34. x Cia Rmux Rew and 1 fs x Cio and can be calculated using Equation 1 with fs sampling frequency Cia ADC analog input capacitance Rmux analog mux resistance Rew switch resistance Cio pin capacitance E Ta Rast Ry J 1 ia io LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 57 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Under nominal operating condition Vpp 3 3 V and with the maximum sampling frequency fs 400 kHz the parameters assume the following values Cia 1 pF max Rmux 2 max Rew 1 3 max Cio 7 1 pF max The effective input impedance with these parameters is Rin 308 kQ 11 7 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6 The ADC input trace must be short and as close as possible to the LPC11U2x chip Shield The ADC input traces from fast switching digital signals and noisy power supply lines The ADC and the digital core share the same power supply Therefore filter the power supply line adequately To improve the ADC performance in a noisy environment put the device in Sleep mode during the ADC conversion LPC11U2X All information provided in this document is subject
35. 0 pF Rou 1 5 D Vpp 3 0 lt lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 to 90 8 5 13 8 ns tr fall time 10 to 90 96 7 7 13 7 ns tFRFM differential rise and fall time ty t 109 matching Vcns output signal crossover voltage 1 3 2 0 V tFEOPT source SEO interval of EOP see Figure 26 160 175 ns tFpEoP source jitter for differential transition see Figure 26 2 5 ns to SEO transition tJR1 receiver jitter to next transition 18 5 18 5 ns tJR2 receiver jitter for paired transitions 10 to 90 96 9 9 ns 1 EOP width at receiver must accept as 82 ns EOP see Figure 26 1 Characterized but not implemented as production test Guaranteed by design TPERIOD crossover point extended crossover point ae differential data lines source EOP width tFEOPT differential data to SEO EOP skew ias n TPERIOD trpEoP _ T receiver EOP width aaa 009330 Fig 26 Differential data to EOP transition skew and EOP width LPC11U2X All information provided in this document is subject to legal disclaimers Rev 2 3 27 March 2014 NXP B V 2014 All rights reserved 51 of 74 Product data sheet NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 11 Application i
36. 30 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 5 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lo LOW level output VoL 0 4 V 4 mA current 2 0 V lt lt 3 6 V 1 8 V lt 2 0 V 3 mA lous HIGH level short circuit 0 V 4 45 mA output current lots LOW level short circuit 14 50 mA output current log pull down current Vi 5V 10 50 150 uA lou pull up current Vi 0V 15 50 85 2 0 V lt lt 3 6 V 1 8 V lt Vpp 2 0 V 10 50 85 Vpp V lt 5V 0 0 0 pA High drive output pin PIOO 7 lit LOW level input current 0 on chip pull up resistor 0 5 10 nA disabled HIGH level input Vi Vpp on chip pull down resistor 0 5 10 nA current disabled loz OFF state output Vo 0 V Vo Vpp on chip 0 5 10 nA current pull up down resistors disabled Vi input voltage pin configured to provide a digital 1102 o 5 0 V function 13 Vo output voltage output active 0 Vpp V Vin HIGH level input 0 7Vpp V voltage Vit LOW level input voltage 0 3Vpp Vhys hysteresis voltage 0 4 Vou HIGH level output 2 5 V lt Vpp 3 6 V 20 mA Vpp 0 4 V voltage 1 8 V lt Vpp lt 2 5 V lou 12 mA 0 4 V
37. 32 bit timer 0 SCLK Serial clock input output for USART synchronous mode PIOO 18 RXD 31 B3 46 61 81 PIOO 18 General purpose digital input output pin CTS2B0 MATO RXD Receiver input for USART Used UART ISP mode 2 0_ Match output 0 for 32 bit timer 0 PIOO 19 TXD 32 B2 47 62 8 PU O PIOO 19 General purpose digital input output pin CT32B0 MAT1 O TXD Transmitter output for USART Used in UART ISP mode O CT32BO 1 Match output 1 for 32 bit timer 0 PIOO_20 CT16B1_CAPO 7 F2 9 11 I O PIOO 20 General purpose digital input output pin CT16B1 CAPO Capture input 0 for 16 bit timer 1 PIOO 21 CT16B1 MATO 12 G4 17 22 I O PIOO 21 General purpose digital input output pin z O CT16B1_MATO Match output 0 for 16 bit timer 1 MOSI1 Master Out Slave for SSP1 PIOO 22 AD6 20 E8 30 40 l PU VO PIOO 22 General purpose digital input output pin CT16B1_MAT1 MISO1 AD6 A D converter input 6 16 1_ 1 Match output 1 for 16 bit timer 1 MISO1 Master In Slave Out for SSP1 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 11 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroll
38. 7 17 6 3 LPC11U2X 32 bit ARM Cortex M0 microcontroller Power down mode reduces power consumption compared to Deep sleep mode at the expense of longer wake up times Deep power down mode In Deep power down mode power is shut off to the entire chip except for the WAKEUP pin The LPC11U2x can wake up from Deep power down mode via the WAKEUP pin The LPC11U2x can be prevented from entering Deep power down mode by setting a lock bit in the PMU block Locking out Deep power down mode enables the application to keep the watchdog timer or the BOD running at all times When entering Deep power down mode an external pull up resistor is required on the WAKEUP pin to hold it HIGH Pull the RESET pin HIGH to prevent it from floating while in Deep power down mode System control Reset Reset has four sources on the LPC11U2x the RESET pin the Watchdog reset power on reset POR and the BrownOut Detection BOD circuit The RESET pin is a Schmitt trigger input pin Assertion of chip reset by any source once the operating voltage attains a usable level starts the IRC and initializes the flash controller A LOW going pulse as short as 50 ns resets the part When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values In Deep power down mode a
39. ARM Cortex M0 microcontroller HVQFN33 plastic thermal enhanced very thin quad flat package no leads 32 terminals body 5 x 5 x 0 85 mm terminal 1 index area A A1 detail X C 1 hy wc 17 EE cr e A cj A E i 2 1 2 e a 24 terminal 1 index area 32 25 Dh 0 d A 1 1 1 Dimensions mm the original dimensions scale Uni A b c DD p EU E e e L w y y max 0 05 0 30 51 375 51 375 0 5 mm nom 0 85 0 2 05 35 35 0 1 0 05 0 05 0 1 min 0 00 0 18 49 345 49 345 0 3 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included hvgfn33f po i References Outline bak Furopean Issue date version IEC JEDEC JEITA projection MO 220 11 10 17 Fig 35 Package outline HVQFN33 5 x 5 x 0 85 mm LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 60 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2
40. CKO CT32BO CAP1 PIOO 22 AD6 CT16B1 MAT1 MISO1 SWCLK PIOO 10 SCKO0 CT16BO MAT2 PIOO 9 MOSIO CT16BO MAT1 PIOO 8 MISOO CT16B0 MATO PIO1 21 DCD MISO1 PIO1 31 002aag622 PIO1 24 CT32BO MATO 21 USB DP 20 PIOO 6 USB CONNECT SCKO 22 PIOO 4 SCL 15 PIOO 5 SDA 16 PIOO 21 CT16B1 MATO MOSIM 17 USB DM 19 PIO1 28 CT32BO CAPO SCLK 24 PIOO 7 CTS 23 PIO1 23 CT16B1 MAT1 SSEL1 18 PIOO 3 USB VBUS 14 PIO1 20 DSR SCK4 13 Fig 4 Pin configuration LQFP48 LPC11U2X All information provided in this document is subject to legal disclaimers Rev 2 3 27 March 2014 NXP B V 2014 All rights reserved 7 of 74 Product data sheet NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller PIO1 0 PIO1 25 PIO1 19 RESET PIOO 0 PIOO 1 PIO1 7 Vss XTALIN XTALOUT VDD PIOO 20 PIO1 10 PIO0 2 PIO1 26 PIO1 27 PIO1 4 Fig 5 64 PIO1 6 63 PIO1 16 52 SWDIO PIOO 15 62 PIOO_19 61 18 60 17 59 PIO1_12 58 Vpp 57 PlO1 15 56 23 55 PlO1 9 54 Vss 53 PIOO_16 LPC11U24FBD64 401 51 PIO1 22 50 PIO1 3 49 PIO1 14 002aag624 PIO1 20 18 PIOT 1 17 See Table 3 for the full pin name Pin configuration LQFP64 PIOO 4 20 PIOO 5 21 PIOO 21 22 PIO1 18 28 PIOO 3 19 PIO1 17 23 PIO1 23 24 USB DM 25 USB DP 26 PIO1 24 27 PIOO 6 29 PIOO 7 30 PIO1 28 31 PIO1
41. Debug functions are integrated into the ARM Cortex MO Serial wire debug functions are supported in addition to a standard JTAG boundary scan The ARM Cortex MO is configured to support up to four breakpoints and two watch points The RESET pin selects between the JTAG boundary scan RESET LOW and the ARM SWD debug RESET HIGH The ARM SWD debug port is disabled while the LPC11U2x is in reset To perform boundary scan testing follow these steps Erase any user code residing in flash Power up the part with the RESET pin pulled HIGH externally Wait for at least 250 us Pull the RESET pin LOW externally Perform boundary scan operations oar WD Once the boundary scan operations are completed assert the TRST pin to enable the SWD debug mode and release the RESET pin pull HIGH Remark The JTAG interface cannot be used for debug purposes LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 28 of 74 LPC11U2x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors 8 Limiting values Table 4 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 1 Symbol Parameter Conditions Min Max Unit Vpp supply voltage core and 11 0 5 14 6 V external rail Vi input voltage 5 V tolerant digital I O pins SII2
42. FBD48 301 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U24FHI33 301 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 5 x 5 x 0 85 mm LPC11U24FBD48 301 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U24FET48 301 TFBGA48 plastic thin fine pitch ball grid array package 48 balls body 4 5 x 4 5 x SOT1155 2 0 7 mm LPC11U24FHN33 401 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm LPC11U24FBD48 401 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U24FBD64 401 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 4 1 Ordering options Table 2 Part ordering options Part Number Flash EEPROM Main USB USB I2C bus SSP ADC GPIO Package kB kB SRAM SRAM FM channels kB kB LPC11U22FBD48 301 16 1 6 2 1 1 2 8 40 LQFP48 LPC11U23FBD48 301 24 1 6 2 1 1 2 8 40 LQFP48 LPC11U24FHI33 301 32 2 6 2 1 1 2 8 26 HVQFN33 5 x 5 LPC11U24FBD48 301 32 2 6 2 1 1 2 8 40 LQFP48 LPC11U24FET48 301 32 2 6 2 1 1 2 8 40 TFBGA48 LPC11U24FHN33 401 32 4 8 2 1 1 2 8 26 HVQFN33 7 x 7 LPC11U24FBD48 401 32 4 8 2 1 1 2 8 40 LQFP48 LPC11U24FBD64 401 32 4 8 2 1 1 2 8 54 LQFP64 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Produc
43. PIO1 8 General purpose digital input output pin PIO1_9 55 3 EPU VO PIO1 9 General purpose digital input output pin PIO1 10 0 12 81 PU VO PIO1 10 General purpose digital input output pin PIO1 11 43 VO PIO1 11 General purpose digital input output pin PIO1 12 59 PIO1 12 General purpose digital input output PIO1 13 DTR B8 36 47 B PU VO PIO1 13 General purpose digital input output pin CT16B0 MATO TXD O DTR Data Terminal Ready output for USART CT16BO MATO Match output 0 for 16 bit timer 0 TXD Transmitter output for USART PIO1 14 DSR A8 37 49 8 PU O PIO1 14 General purpose digital input output pin CT16BO_MAT1 RXD DSR Data Set Ready input for USART CT16B0_MAT1 Match output 1 for 16 bit timer 0 RXD Receiver input for USART PIO1 15 DCD 28 A4 43 57 PU O PIO1 15 General purpose digital input output pin CT16B0 MAT2 SCK1 DCD Data Carrier Detect input for USART CT16B0_MAT2 Match output 2 for 16 bit timer 0 SCK1 Serial clock for SSP1 PIO1 16 RI 2 48 63 81 I O PIO1 16 General purpose digital input output pin CT16B0 RI Ring Indicator input for USART CT16BO Capture input 0 for 16 bit timer 0 LPC11U2X All information provided in this document is subject to legal disclaimers Product d
44. Package outline TFBGA48 SOT1155 2 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 63 of 74 NXP Semiconductors LPC11U2x 13 Soldering 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of HVQFN33 package see detail X rm rtg nii ja L l D SLx Bx Ax solder land solder paste occupied area Dimensions in mm z 0 60 1 0 30 detail 0 5 5 95 5 95 425 425 085 0 27 Issue date 11 11 20 Fig 39 Reflow soldering for the HVQFN33 5x5 package 002aag766 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 64 of 74 LPC11U2x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package 8 20 OA OID lt x 1o N N PID 0 30 CU a 08 S 391 M 9086 1 3 1 VO Vd A
45. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased 2 CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands 3 Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP This mode effectively disables ISP override using PIOO 1 pin as well If necessary the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART CAUTION If level three Code Read Protection CRP3 is selected no future factory testing can be performed on the device In addition to the three CRP levels sampling of pin PIOO 1 for valid user code can be disabled For details see the LPC11Uxx user manual 7 17 6 4 APB interface The APB peripherals are located on one APB bus 7 17 6 5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex MO to the flash memory the main static RAM and the ROM 7 17 6 6 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 27 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 7 18 Emulation and debugging
46. andard mode and Fast mode but must be less than the maximum of typ pAr or tvp Ack by a transition time see UM10204 This maximum must only be met if the device does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock 8 tHD DAT is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 9 tSU DAT is the data set up time that is measured with respect to the rising edge of SCL applies to data in transmission and the acknowledge 10 A Fast mode I C bus device be used in a Standard mode I C bus system but the requirement tsy par 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tsu pAr 1000 250 1250 ns according to the Standard mode I C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time tsU DAT 0 SDA tHD DAT SCL 5 1 f ENDS IE 1 SCL 002aaf425 Fig 23 I C bus pins clock timing LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 47 of 74 NXP Semiconductor
47. applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 18 Contact information 32 bit ARM Cortex M0 microcontroller whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 17 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP Semiconductors For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 72 of 74 NXP Semiconductors LPC11U2x 19 Contents 32 bit ARM Cortex M0 microcontroller OuRBWD 7 6 1 7 6 2 7 7 7 7 1 7 8 7 8 1 7 9 7 9 1 7 9 1 1 7 10 7 10 1 7 11 7 11 1 7 12 7 12 1 7 13 7 13
48. ata sheet Rev 2 3 27 March 2014 NXP B V 2014 All rights reserved 12 of 74 NXP Semiconductors LPC11U2x Table 3 Pin description 32 bit ARM Cortex M0 microcontroller Symbol e Nem Reset Type Description e state z SS EEEE PIO1_17 CT16BO_CAP1 23 i PU O PIO1 17 General purpose digital input output pin RXD CT16B0_CAP1 Capture input 1 for 16 bit timer 0 RXD Receiver input for USART PIO1 18 CT16B1 CAP1 28 PIO1 18 General purpose digital input output pin TXD 16 1_ 1 Capture input 1 for 16 bit timer 1 TXD Transmitter output for USART PIO1 19 DTR SSEL1 1 B12 S3 B IPU PIO1 19 General purpose digital input output pin DTR Data Terminal Ready output for USART SSEL1 Slave select for SSP1 PIO1 20 DSR SCK1 13 18 PU PIO1 20 General purpose digital input output pin DSR Data Set Ready input for USART SCK1 Serial clock for SSP1 PIO1_21 DCD MISO1 G8 26 35 BI PU VO PIO1 21 General purpose digital input output pin DCD Data Carrier Detect input for USART MISO1 Master In Slave Out for SSP1 PIO1_22 RI MOSI1 A7 38 51 81 PU O PIO1 22 General purpose digital input output p
49. ation hereof LPC11U2X All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers shoul
50. be connected externally in case of fundamental mode oscillation L Cj and Rg represent the fundamental frequency Capacitance Cp in Figure 30 represents the parallel package capacitance and must not be larger than 7 pF Parameters Fosc Rs and Cp are supplied by the crystal manufacturer LPC1xxx T XTALIN XTALOUT 4 LO Cp XTAL 4 e Rs CX2 002aaf424 Fig 30 Oscillator modes and models oscillation mode of operation and external crystal model used for evaluation All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 54 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 18 Recommended values for in oscillation mode crystal and external components parameters low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cx 1 MHz to 5 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF 3000 39 pF 39 pF 30 pF 3000 57 pF 57 pF 5 MHz to 10 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF 2000 39 pF 39 pF 30 pF lt 1000 57 pF 57 pF 10 MHz to 15 MHz 10 pF 1600 18 pF 18 pF 20 pF 600 39 pF 39 pF 15 MHz to 20 MHz 10 pF 800 18 pF 18 pF
51. bject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 18 of 74 NXP Semiconductors LPC11U2x 7 10 1 7 11 7 11 1 7 12 LPC11U2X 32 bit ARM Cortex M0 microcontroller The USART uses a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz Features Maximum USART data bit rate of 3 125 Mbit s 16 byte receive and transmit FIFOs Register locations conform to 16C550 industry standard e Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Fractional divider for baud rate control auto baud capabilities and FIFO control mechanism that enables software flow control implementation Support for RS 485 9 bit mode Support for modem control Support for synchronous mode Includes smart card interface SSP serial I O controller The SSP controllers operate on a SSP 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer The SSP supports full duplex transfers with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carr
52. ct input LOW level selects the JTAG boundary scan HIGH level selects the ARM SWD debug mode In deep power down mode this pin must be pulled HIGH externally The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power down mode is not used PIOO 0 General purpose digital input output pin PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE PU PIOO 1 General purpose digital input output pin A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration CLKOUT Clockout pin CT32B0_MAT2 Match output 2 for 32 bit timer 0 USB FTOGGLE USB 1 ms Start of Frame signal PIOO 2 SSELO 1680 10 PIOO 2 General purpose digital input output pin SSELO Slave select for SSPO CT16BO Capture input 0 for 16 bit timer 0 3 USB VBUS 14 PIOO 3 General purpose digital input output pin A LOW level on this pin during reset starts the ISP command handler A HIGH level during reset starts the USB device enumeration USB_VBUS Monitors the presence of USB bus power PIOO 4 SCL 15 I IA PIOO 4 General purpose digital input output pin open drain SCL I C bus clock input output open drain High current sink only if 12C Fast mode Plu
53. cupied area solder resist DIMENSIONS in mm P SL SP SR Hx 0 50 0 225 0 275 0 325 4 75 Fig 42 Reflow soldering for the TFBGA48 package OD 010101919 see detail X detail X sot1155 2 fr LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 67 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314 2 a Hx Gx P2 gt mW 1 A IE IE ZI MZ A L ARR i 1 i E L 22 LZ E EE ZZA 2221 1 ZZ 2221 1 122 ZA Hy Gy ZZ ZZA By Ay Lu Za 222 I escas 2 224 d ZZ 222 Mas TL 75 Es 7777 22 KZA EE 1 CAAA A A A A A 2 2 VA 1 101 Fog i CEE E d _ L D2 8x _ bag a Bx gt lt gt Generic footprint pattern Refer to the package outline drawing for actual layout A solder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By D1 D2 Gx Gy Hx Hy 0 500 0 560 13 300 13 300 10 300 10 300 1 500 0 280 0 400 10 500 10 500 13 550 13 550 E Fig 43 Reflow soldering for the LQFP64 package
54. d provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in
55. ded OUTLINE VERSION REFERENCES EUROPEAN IEC JEDEC JEITA PROJECTION ISSUE DATE SOT314 2 136E10 MS 026 Edge 90 01 19 03 02 25 Fig 37 Package outline LQFP64 SOT314 2 LPC11U2X All information provided in this document is subject to legal disclaimers Product data sheet Rev 2 3 27 March 2014 NXP B V 2014 All rights reserved 62 of 74 LPC11U2x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors TFBGA48 plastic thin fine pitch ball grid array package 48 balls body 4 5 x 4 5 x 0 7 mm SOT1155 2 gt gt B A E ball A1 index area A2 E A 1 detail X 9 i i e G F E 6 2 D 12e ball A1 1 2 3 4 5 6 7 8 solder mask open area index area not for solder ball 0 5mm L 1 L Dimensions scale Unit A A2 b D E e 1 e2 v w y y1 max 1 10 0 30 0 80 0 35 46 4 6 mm nom 0 95 0 25 0 70 030 45 45 05 35 3 5 0 15 0 05 0 08 0 1 min 0 85 0 20 0 65 0 25 44 44 sot1155 2_po i Ref Outline ee Furopean Issue date version IEC JEDEC JEITA projection 43 06 47 SOT1155 2 e Fig 38
56. eep power down mode An external pull up resistor is required on this pin for the Deep power down mode See Figure 32 for the reset pad configuration 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 31 I2C bus pin compliant with the I2C bus specification for I2C standard mode 12C Fast mode and 12C Fast mode Plus The pin requires an external pull up to provide output functionality When power is switched off this pin is floating and does not disturb the I2C lines Open drain configuration applies to all functions on this pin 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 31 includes high current output driver 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 31 includes digital input glitch filter Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only This pad is not 5 V tolerant When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce susceptibility to noise Leave XTALOUT floating
57. emapping The AHB Advanced High performance Bus peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals The APB Advanced Peripheral Bus peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kB of space This addressing scheme allows simplifying the address decoding for each peripheral All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 15 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller LPC11U2x 49B i OxFFFF FFFF us reserved Uu 010 0000 rivate peripheral bus reserved APB peripherals 0x5000 4000 0x4008 0000 25 31 d 0x5000 0000 0x4006 4000 m GPIO GROUP INT 0000 S GPIO GROUPO INT 0x4008 4000 mm 0x4005 C000 0x4005 8000 A 20 21 reserved APB peripherals PE 0x4004 C000 1GB x4000 0000 19 GPIO interrupts 3 N 0x4004 C000 system control 0x4004 8000 IQCON 0x4004 4000 SSPO 0x4004 0000 15 flash EEPROM controller EROR 0x2000 4000 0568 0x2000 0000 0x2000 4800 0 4003 C000 PMU 0x4003 8000 reserved 10 13 reserved Ox1FFF 4000 16 kB boot ROM 0x4002 8000 Ox1FFF 0000 reserved 0x4002 4000 reserved 0x4002 0000 ADC 0x4001 C000 32 bit counter timer 1 0x4001 8000 ys reser
58. er Table 3 Pin description Symbol a IS Reset Description Z Seale state m is EEEE PIO0_23 AD7 27 A5 42 56 1 PU IO PIOO 23 General purpose digital input output pin AD7 converter input 7 PIO1 0 CT32B1 MATO l 1 PU JO PIO1_0 General purpose digital input output pin CT32B1 MATO Match output 0 for 32 bit timer 1 PIO1 1 CT32B1 MAT1 l 17 11 VO PIO1 1 General purpose digital input output pin CT32B1_MAT1 Match output 1 for 32 bit timer 1 PIO1 2 CT32B1 MAT2 34 11 EPU VO PIO1 2 General purpose digital input output pin CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIO1_3 CT32B1_MAT3 l 50 8 PIO1 3 General purpose digital input output pin O CT32B1 Match output for 32 bit timer 1 PIO1 4 CT32B1 CAPO 16 181 VO PIO1 4 General purpose digital input output CT32B1 Capture input 0 for 32 bit timer 1 PIO1 5 CT32B1 CAP1 H8 32 PIO1 5 General purpose digital input output pin CT32B1_CAP1 Capture input 1 for 32 bit timer 1 PIO1 6 0 64 PIO1 6 General purpose digital input output PIO1 7 l e B YO PIO1_7 General purpose digital input output pin PIO1_8 l 39 VO
59. er is designed to count cycles of the system derived clock It can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt Features A 32 bit 16 bit timer counter with a programmable 32 bit 16 bit prescaler Counter or timer operation One capture channel per timer that can take a snapshot of the timer value when an input signal transitions A capture event can also generate an interrupt All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 20 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Four match registers per timer that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match The timer and prescaler can be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an
60. ercent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 8 6 The absolute error is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 8 7 Tamb 25 C maximum sampling frequency fs 400 kSamples s and analog input capacitance Cia 1 pF 8 Input resistance depends on the sampling frequency fs Rj 1 fs x Cia LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 34 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 1023 offset error Eo gain error Eg 1022 1021 1020 1019 1018 code out 1 LSB ideal offset error Eo Example of an actual transfer curve 1018 Via LSBideal 1022 1023 1019 1020 1021 1024 Vpp Vss 1024 1 LSB 002aa 426 1 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity 5 Center of a step of the actual transfer curve Fig 8 ADC characteristics LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet
61. formation provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 33 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 6 ADC static characteristics Tamb 40 C to 85 C unless otherwise specified ADC frequency 4 5 MHz Vpp 2 5 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit ViA analog input voltage 0 Vpp V Cia analog input capacitance 1 pF Ep differential linearity error t1 LSB Ei adi integral non linearity 1 5 LSB Eo offset error 3 5 LSB Eg gain error 0 6 Er absolute error 6 4 LSB Rysi voltage source interface 40 resistance Ri input resistance 718 25 MQ 1 The ADC is monotonic there are no missing codes 2 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 8 3 The integral non linearity E is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 8 4 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 8 5 The gain error Eg is the relative difference in p
62. full speed device controller with on chip PHY PHYsical layer for device functions Remark Configure the LPC11U2x in default power mode with the power profiles before using the USB see Section 7 17 5 1 Do not use the USB with the part in performance efficiency or low power mode Full speed USB device controller The device controller enables 12 Mbit s data exchange with a USB Host controller It consists of a register interface serial interface engine and endpoint buffer memory The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer The status of a completed USB transfer or error condition is indicated via status registers If enabled an interrupt is generated Features Dedicated USB PLL available Fully compliant with USB 2 0 specification full speed e Supports 10 physical 5 logical endpoints including one control endpoint Single and double buffering supported Each non control endpoint supports bulk interrupt or isochronous endpoint types Supports wake up from Deep sleep mode and Power down mode on USB activity and remote wake up Supports SoftConnect USART The LPC11U2x contains one USART The USART includes full modem control support for synchronous mode and a smart card interface The RS 485 9 bit mode allows both software address detection and automatic address detection using 9 bit mode All information provided in this document is su
63. g time is 100 ps Clock output The LPC11U2x feature a clock output function that routes the IRC oscillator the system oscillator the watchdog oscillator or the main clock to an output pin Wake up process The LPC11U2x begin operation by using the 12 MHz IRC oscillator as the clock source at power up and when awakened from Deep power down mode This mechanism allows chip operation to resume quickly If the application uses the main oscillator or the PLL software must enable these components and wait for them to stabilize Only then can the system use the PLL and main oscillator as a clock source Power control The LPC11U2x support various power control features There are four special modes of processor power reduction Sleep mode Deep sleep mode Power down mode and Deep power down mode The CPU clock rate can also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This power control mechanism allows a trade off of power versus processing speed based on application requirements In addition a register is provided for shutting down the clocks to individual on chip peripherals This register allows fine tuning of power All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 24 of 74 NXP Semiconductors LPC11U2x 7 17 5 1 7 17 5 2 7 17 5 3 7 17
64. h Data must be written to the flash in blocks of 256 bytes Table 10 EEPROM characteristics Tamp 40 to 85 Vpp 2 7 to 3 6 Based on JEDEC NVM qualification Failure rate lt 10 ppm for parts as specified below Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 100000 1000000 cycles tret retention time powered 100 200 years unpowered 150 300 years tprog programming 64 bytes 2 9 ms time 10 2 External clock Table 11 Dynamic characteristic external clock Tamb 40 C to 85 C Vpp over specified ranges Symbol Parameter Conditions Min Typ l Unit fosc oscillator frequency 1 25 MHz Teye clock cycle time 40 1000 ns tcHcx clock HIGH time Toyo x 0 4 ns teLcx clock LOW time x 0 4 ns clock rise time 5 ns tcHcL clock fall time 5 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 44 of 74 NXP Semiconductors LPC11U2x LPC11U2X 10 3 32 bit ARM Cortex M0 microcontroller
65. ies meaningful data Features Maximum SSP speed of 25 Mbit s master or 4 17 Mbit s slave in SSP mode Compatible with Motorola SPI Serial Peripheral Interface 4 wire Texas Instruments SSI Serial Synchronous Interface and National Semiconductor Microwire buses e Synchronous serial communication Master or slave operation 8 frame FIFOs for both transmit and receive 4 bit to 16 bit frame I C bus serial I O controller The LPC11U2x contain one I C bus controller The I C bus is bidirectional for inter IC control using only two wires a Serial CLock line SCL and a Serial DAta line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I C bus is a multi master bus and more than one bus master connected to the interface can be controlled the bus All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 19 of 74 NXP Semiconductors LPC11U2x 7 12 1 7 13 7 13 1 7 14 7 14 1 LPC11U2X 32 bit ARM Cortex M0 microcontroller Features The l C interface is an 2 c
66. iles residing in boot ROM provide optimized performance and minimized power consumption for any given application through one simple function call Four reduced power modes Sleep Deep sleep Power down and Deep power down Processor wake up from Deep sleep and Power down modes via reset selectable GPIO pins watchdog interrupt or USB port activity All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 2 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Processor wake up from Deep power down mode using one special function pin Power On Reset POR Brownout detect with four separate thresholds for interrupt and forced reset 3 Applications Unique device serial number for identification Single 3 3 V power supply 1 8 V to 3 6 V Temperature range 40 C to 85 C Available as LQFP64 LQFP48 TFBGA48 and HVQFN33 packages Consumer peripherals Medical Handheld scanners USB audio devices W Industrial control 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC11U22FBD48 301 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U23
67. in RI Ring Indicator input for USART MOSI1 Master Out Slave for SSP1 PIO1 23 CT16B1 MAT1 H4 18 24 I O PIO1 23 General purpose digital input output pin SSEL1 O 16 1 MAT1 Match output 1 for 16 bit timer 1 SSEL1 Slave select for SSP1 PIO1 24 CT32BO0 MATO Ge 21 27 VO PIO1 24 General purpose digital input output pin CT32BO MATO Match output 0 for 32 bit timer 0 PIO1 25 CT32BO MAT1 1 1 2 VO PIO1 25 General purpose digital input output pin O CT32BO 1 Match output 1 for 32 bit timer 0 PIO1 26 CT32BO MAT2 G2 11 14 VO PIO1 26 General purpose digital input output pin RXD O 32 0 MAT2 Match output 2 for 32 bit timer 0 RXD Receiver input for USART PIO1 27 CT32BO MAT3 G1 12 15 VO PIO1 27 General purpose digital input output pin TXD CT32BO MAT3 Match output 3 for 32 bit timer 0 TXD Transmitter output for USART PIO1 28 CT32BO CAPO H7 24 31 VO PIO1 28 General purpose digital input output pin SCLK CT32B0 Capture input 0 for 32 bit timer 0 SCLK Serial clock input output for USART synchronous mode PIO1 29 SCKO D7 31 41 PU JO 29 General purpose digital input output pin CT32B0_CAP1 SCKO Serial clock for SSPO CT32B0_CAP1 Capture input 1 for 32 bit timer 0 LPC11U2X All i
68. input pulse and capturing the timer value on the trailing edge 7 15 System tick timer The ARM Cortex MO includes a system tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception at a fixed time interval typically 10 ms 7 16 Windowed WatchDog Timer WWDT The purpose of the WWDT is to prevent an unresponsive system state If software fails to update the watchdog within a programmable time window the watchdog resets the microcontroller 7 16 1 Features LPC11U2X Internally resets chip if not periodically reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time period both programmable Optional warning interrupt can be generated at a programmable time before watchdog time out Software enables the WWDT but a hardware reset or a watchdog reset interrupt is required to disable the WWDT Incorrect feed sequence causes reset or interrupt if enabled Flag to indicate watchdog reset Programmable 24 bit timer with internal prescaler Selectable time period from Tcy WDCLk x 256 x 4 to Tcy wDCLk x 224 x 4 in multiples of Tcy WDCLK x 4 The Watchdog Clock WDCLK source be selected from the IRC or the dedicated watchdog oscillator WDO The clock source selection provides a wide range of potential timing choices of watchdog operation under different power conditions All information provided in this documen
69. k 12 MHz BIAIS 2 mA 6 7 8 system clock 50 MHz 1516 7 mA 71 8 9 Sleep mode BIAIS 1 mA Vpp 3 3 V Tamb 25 C 16117118 system clock 12 MHz Deep sleep mode Vpp 3 3 V 360 uA Tamb 25 C Power down mode Vpp 3 3 V 2 uA Tamb 25 C Deep power down mode 10 220 nA Vpp 3 3 V Tamb 25 C Standard port pins RESET liL LOW level input current Vj 0 V on chip pull up resistor 0 5 10 nA disabled HIGH level input Vi Vpp on chip pull down resistor 0 5 10 nA current disabled loz OFF state output Vo 0 V Vo on chip 0 5 10 nA current pull up down resistors disabled Vi input voltage pin configured to provide a digital 1102 0 5 0 V function 13 Vo output voltage output active 0 Vpp V Vin HIGH level input 0 7Vpp V voltage ViL LOW level input voltage 0 3Vpp V Vnys hysteresis voltage 0 4 V Vou HIGH level output 2 0 V lt Vpp 3 6 V lou 4 mA Vpp 0 4 V voltage 1 8 V lt 2 0 V lop 3 mA 3 V VoL LOW level output 2 0 V lt Vpp x 3 6 V lop 4 mA 0 4 V voltage 1 8 V lt Vpp lt 2 0 V lg 0 4 V lou HIGH level output Vou Vpp 0 4 V 4 mA current 2 0 V lt lt 3 6 V 1 8 V lt 2 0 V 3 mA LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014
70. ld _ I eno 507 e o Solder resist covered via 0 30 PH ft 0 60 SR cover 0 60 CU OwDtot 5 10 OA 0 45 DM 4 25 m evia SAAS AAA CAS BASSAS JJ 9 JJ i 0 70 SP 9491919191916 lt GapD SKS 55059 000009090909 ESS RRR EEE 2 40 gt 2 70 SP evia SDhtot A 4 85 CU DHS 5 80 CU LbD SPD 1 00 SP 4 7 95 CU LaD dS 02 10995 SS e 98 SHA E V0 0 6 0 3MO VO 028 910 A side fully covered number of vias 20 solder land plus solder paste 7 solder land Remark solder resist s y WN solder paste deposit N 001aa0134 Stencil thickness 0 125 mm Dimensions in mm occupied area Fig 40 Reflow soldering for the HVQFN33 7x7 package NXP B V 2014 All rights reserved All information provided in this document is subject to legal disclaimers LPC11U2X Rev 2 3 27 March 2014 65 of 74 Product data sheet NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller
71. ll rights reserved Product data sheet Rev 2 3 27 March 2014 5 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller ball A1 LPC11U24FET48 301 index area OOOOOO OO0O000 OO OO OO w OO OO OO c H OOOOO0O00 002 623 Transparent top view Fig 3 Pin configuration TFBGA48 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 6 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller PIO1 25 CT32B0 MAT1 PIO1 19 DTR SSEL1 RESET PIOO 0 PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE Vss XTALIN XTALOUT Vpp PIOO 20 CT16B1 PIOO 2 SSELO CT16BO PIO1 26 CT32B0 MAT2 RXD PIO1 27 CT32B0 MAT3 TXD 48 PIO1 16 RI CT16BO CAPO 47 PIOO 19 TXD CT32BO MAT1 46 PIOO 18 RXD CT32BO0 MATO 45 PIOO 17 RTS CT32B0 CAPO SCLK 43 PIO1 15 DCD CT16BO MAT2 SCK1 40 PIOO 16 AD5 CT32B1 MAT3 WAKEUP 42 PIOO 23 AD7 44 Vpp 41 Vss LPC11U22FBD48 301 LPC11U23FBD48 301 LPC11U24FBD48 301 LPC11U24FBD48 401 39 SWDIO PIOO 15 AD4 CT32B1 MAT2 38 PIO1 22 RI MOSI1 37 PIO1 14 DSR CT16BO MAT1 RXD PIO1 13 DTR CT16B0 MATO TXD TRST PIOO_14 AD3 CT32B1_MAT1 TDO PIOO_13 AD2 CT32B1_MATO TMS PIOO_12 AD1 CT32B1_CAPO TDI PIOO 11 ADO CT32B0 MAT3 PIO1 29 S
72. log peripherals 10 bit ADC with input multiplexing among eight pins Serial interfaces USB 2 0 full speed device controller USART Universal Synchronous Asynchronous Receiver Transmitter with fractional baud rate generation internal FIFO a full modem control handshake interface and support for RS 485 9 bit mode and synchronous mode USART supports an asynchronous smart card interface ISO 7816 3 Two SSP Synchronous Serial Port controllers with FIFO and multi protocol capabilities I C bus interface supporting the full IC bus specification and Fast mode Plus with a data rate of up to 1 Mbit s with multiple address recognition and monitor mode Clock generation Crystal Oscillator with an operating range of 1 MHz to 25 MHz system oscillator 12 MHz high frequency Internal RC oscillator IRC that can optionally be used as a system clock Internal low power low frequency WatchDog Oscillator WDO with programmable frequency output PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources A second dedicated PLL is provided for USB Clock output function with divider that can reflect the crystal oscillator the main clock the IRC or the watchdog oscillator Power control Integrated PMU Power Management Unit to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes Power prof
73. n external pull up resistor is required on the RESET pin Brownout detection The LPC11U2x includes four levels for monitoring the voltage on the Vpp pin If this voltage falls below one of the four selected levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt Alternatively software can monitor the signal by reading a dedicated status register Four additional threshold levels can be selected to cause a forced reset of the chip Code security Code Read Protection CRP CRP provides different levels of security in the system so that access to the on chip flash and use of the Serial Wire Debugger SWD and In System Programming ISP can be restricted Programming a specific pattern into a dedicated flash location invokes CRP IAP commands are not affected by the CRP In addition ISP entry via the PIOO 1 pin can be disabled without enabling CRP For details see the LPC11Uxx user manual There are three levels of Code Read Protection All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 26 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 1 CRP1 disables access to the chip via the SWD and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands
74. n this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 4 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 6 Pinning information 6 1 Pinning 5 N m k O o lt gt 6 S FEE t ES lt lt lt lt lt 9 229 2 25 ooo o m m ta a NAN re N REE E S Ow OJO oi E EIE 8583 E cic L L N 5 8 pub AT 9 terminal 1 n gt index area E GT Go Gs Gs Gs TRST PIOO 14 AD3 CT32B1 MAT1 TDO PIOO 13 AD2 CT32B1 TMS PIOO 12 AD1 CT32B1 CAPO TDI PIOO 11 ADO CT32BO PIOO 22 ADG CT16B1 MAT1 MISO1 SWCLK PIOO 10 5 0 1680 MAT2 0 9 MOSIO CT16BO MAT1 0 8 MISOO CT16BO MATO PIO1 19 DTR SSEL1 RESET PIOO 0 PIOO 4 CLKOUT CT32B0 MAT2 USB FTOGGLE XTALIN XTALOUT LPC11U24 VDD PIOO 20 CT16B1 CAPO PIOO 2 SSELO CT16BO CAPO 15 mD 12 15 m 238524 idle 002 621 gt 6 gt a QDR 5 ao gt zu o Q g a H 5 9 n Transparent top view Fig 2 Pin configuration HVQFN33 LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 A
75. nformation 11 1 Suggested USB interface solutions The USB device can be connected to the USB as self powered device see Figure 27 or bus powered device see Figure 28 On the LPC11U2x the PIOO 3 USB VBUS pin is 5 V tolerant only when Vpp is applied and at operating voltage level Therefore if the USB VBUS function is connected to the USB connector and the device is self powered the USB VBUS pin must be protected for situations when Vpp 0 V If Vpp is always at operating level while VBUS 5 V the USB VBUS pin can be connected directly to the VBUS pin on the USB connector For systems where Vpp can be 0 V and VBUS is directly applied to the VBUS pin precautions must be taken to reduce the voltage to below 3 6 V which is the maximum allowable voltage on the USB VBUS pin in this case One method is to use a voltage divider to connect the USB VBUS pin to the VBUS on the USB connector The voltage divider ratio should be such that the USB VBUS pin will be greater than 0 7Vpp to indicate a logic HIGH while below the 3 6 V allowable maximum voltage For the following operating conditions VBUS max 5 25 V Vpp 3 6 V the voltage divider should provide a reduction of 3 6 V 5 25 V or 0 686 V Fig 27 USB interface on a self powered device where USB VBUS 5 V USB CONNECT Soft connect switch R1 1 5 LPC1xxx R2 R3 USB_VBUS USB B connector UsB
76. nformation provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 13 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 3 Pin description Symbol a Reset Type Description 9 state gt O I e l c c e PIO1_ 31 25 l BI i PU lO PIO1_31 General purpose digital input output pin USB_DM 13 G5 19 25 D USB_DM USB bidirectional D line USB_DP 14 H5 20 26 Ul USB DP USB bidirectional D line XTALIN 4 01 6 8 B Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V XTALOUT 5 7 9 Bj Output from the oscillator amplifier Vpp 6 B4 8 10 Supply voltage to the internal regulator the external 29 E2 44 33 rail and the ADC Also used as the ADC reference 48 voltage 58 Vss 33 B5 5 7 Ground D2 41 54 1 2 4 5 6 7 8 Pin state at reset for default function Input Output PU internal pull up enabled inactive no pull up down enabled F floating If the pins are not used tie floating pins to ground or power to minimize power consumption 5 V tolerant pad RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from D
77. nism before enabling USB CONNECT and the soft connect feature Enabling the soft connect without host presence will lead to USB compliance failure XTAL input The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is driven by a clock in slave mode it is recommended that the input be coupled through a capacitor with Cj 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Cg In slave mode a minimum of 200 mV RMS is needed All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 53 of 74 NXP Semiconductors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller LPC1xxx 100pF T Fig 29 Slave mode operation of the on chip oscillator 002aae788 In slave mode couple the input clock signal with a capacitor of 100 pF Figure 29 with an amplitude between 200 mV RMS and 1000 mV RMS This signal corresponds to a square wave signal with a signal swing of between 280 mV and 1 4 V The XTALOUT pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 30 and in Table 18 and Table 19 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cy need to
78. oduct status information is available on the Internet at URL http www nxp com 17 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 17 3 Disclaimers Limited warran
79. ompliant interface with open drain pins The I2C bus interface supports Fast mode Plus with bit rates up to 1 Mbit s Easy to configure as master slave or master slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The I C bus can be used for test and diagnostic purposes The I C bus controller supports multiple address recognition and a bus monitor mode 10 bit ADC The LPC11U2x contains one ADC It is a single 10 bit successive approximation ADC with eight channels Features 10 bit successive approximation ADC e Input multiplexing among 8 pins Power down mode Measurement range 0 V to Vpp 10 bit conversion time gt 2 44 us up to 400 kSamples s Burst conversion mode for single or multiple inputs Optional conversion on transition of input pin or timer match signal Individual result registers for each ADC channel to reduce interrupt overhead General purpose external event counter timers The LPC11U2x includes two 32 bit counter timers and two 16 bit counter timers The counter tim
80. on provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 48 of 74 NXP Semiconductors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller SCK CPOL 0 SCK CPOL 1 MOSI MISO MOSI MISO Toy clk DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID Fig 24 SSP master timing in SPI mode DATA VALID 1 0 002 829 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 49 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Toy clk SCK CPOL 0 SCK CPOL 1 tos MOSI DATA VALID ta tha 1 MISO DATA VALID DATA VALID tos MOSI DATA VALID twa lt tha 0 MISO DATA VALID DATA VALID 002aae830 Fig 25 SSP slave timing in SPI mode LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 50 of 74 LPC11U2x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors 10 7 USB interface Table 17 Dynamic characteristics USB pins full speed C 5
81. output driver Digital input Pull up enabled disabled Digital input Pull down enabled disabled Digital input Repeater mode enabled disabled Analog input pin configured as digital output driver output enable output m VDD weak pull up pull up enable k repeater mode wee pin configured R enable pull down as digital input pull down enable data input lt 4 L select analog input pin configured as analog input 4 analog input Bg Fig 31 Standard I O pad configuration 002aaf304 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 56 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 11 5 Reset pad configuration 20 ns RC reset FILTER Vss 002 274 Fig 32 Reset pad configuration 11 6 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source See Figure 33 ADC Block Source ADC COMPARATOR 002aah615 Fig 33 ADC input channel The effective input impedance Rin seen by the external voltage source Vgxr is the parallel impedance of 1 fa
82. ow ground that can be applied for a short time lt 10 ms to a device without leading to irrecoverable failure Failure includes the loss of reliability and shorter lifetime of the device 3 See Table 6 for maximum operating voltage 4 Vpop present or not present Compliant with the I2C bus standard 5 5 V can be applied to this pin when Vpp is powered down 5 Including voltage on outputs in 3 state mode 6 The maximum non operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime Please refer to the JEDEC spec J STD 033B 1 for further details 7 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 series resistor LPC11U2X All information provided in this document is subject to legal disclaimers Rev 2 3 27 March 2014 NXP B V 2014 All rights reserved 29 of 74 Product data sheet NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 9 Static characteristics Table 5 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vpp supply voltage core 121 1 8 3 3 3 6 and external rail Ipp supply current Active mode Vpp 3 3 V Tamb 25 C code while 1 executed from flash system cloc
83. s LPC11U2x 32 bit ARM Cortex M0 microcontroller 10 6 SSP interface Table 16 Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI master in SPI mode Toy clk clock cycle time full duplex mode Hl 50 ns when only transmitting 40 ns tps data set up time in SPI mode 2 15 ns 2 4 V lt Vpp x 3 6 V 20VxVpp 24V 21 20 ns 18V lt Vpp lt 20V 21 24 ns tpu data hold time in SPI mode 2 0 ns tv data output valid time in SPI mode B 10 ns tha data output hold time in SPI mode E ns SPI slave in SPI mode ToyPcu POLK cycle time 20 ns tps data set up time in SPI mode BIA 0 ns data hold time in SPI mode BIA 4 ns twa data output valid time SPI mode BIA 3 x Toy PcLk 11 ns tha data output hold time SPI mode BIA 2 x 5 ns 1 SSPCLKDIV 1 SCR x CPSDVSR fmain The clock cycle time derived from the SPI bit rate Tey cik is a function of the main clock frequency fmain the SPI peripheral clock divider SSPCLKDIV the SPI SCR parameter specified in the SSPOCRO register and the SPI CPSDVSR parameter specified in the SPI clock prescale register 2 Tamb 40 C to 85 C 3 12 x Tey PcLk 4 Tamb 25 C for normal voltage supply range Vpp 3 3 V LPC11U2X All informati
84. s Min Typ Max Unit Pin capacitance Cio input output pins configured for analog function 7 1 pF capacitance I2C bus pins 4 and PIOO_5 2 5 pF pins configured as GPIO 2 8 pF 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 For USB operation 3 0 V lt Vpp lt 3 6 V Guaranteed by design 3 IRC enabled system oscillator disabled system PLL disabled 4 Ibp measurements were performed with all pins configured as GPIO outputs driven LOW and pull up resistors disabled 5 BOD disabled 6 All peripherals disabled in the AHBCLKCTRL register Peripheral clocks to USART SSP0 1 disabled in the SYSCON block 7 USB DP and USB DM pulled LOW externally 8 Low current mode PWR LOW CURRENT selected when running the set power routine in the power profiles 9 IRC disabled system oscillator enabled system PLL enabled 10 WAKEUP pin pulled HIGH externally An external pull up resistor is required on the RESET pin for the Deep power down mode 11 Including voltage on outputs in 3 state mode 12 Vpp supply voltage must be present 14 Allowed as long as the current limit does not exceed the maximum current allowed by the device 15 To Vss 16 Includes external resistors of 33 O 1 96 on USB DP and USB DM 13 3 state outputs go into 3 state mode in Deep power down mode LPC11U2X All in
85. s is selected in the I O configuration register LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 9 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 3 Pin description Symbol es Reset Type Description Z 9 state gt O ke l c c e PIOO_5 SDA 11 H3 16 21 HIA O PIOO 5 General purpose digital input output pin open drain VO SDA I C bus data input output open drain High current sink only if IC Fast mode Plus is selected in the I O configuration register PIOO_6 USB_CONNECT 15 22 29 PU I O PIOO 6 General purpose digital input output pin SCKO USB_CONNECT Signal used to switch an external 1 5 kQ resistor under software control Used with the SoftConnect USB feature y o SCKO Serial clock for SSPO PIOO 7 CTS 16 G7 23 30 B EPU lO PIOO 7 General purpose digital input output pin high current output driver CTS Clear To Send input for USART PIOO 8 MISOO0 17 F8 27 36 EPU VO PIOO 8 General purpose digital input output pin CT16B0 MATO y o MISOO Master In Slave Out for SSPO O CT16BO MATO Match output 0 for 16 bit timer
86. sor itself by memory systems and related controllers and by internal buses Deep sleep mode In Deep sleep mode the LPC11U2x is in Sleep mode and all peripheral clocks and all clock sources are off except for the IRC The IRC output is disabled unless the IRC is selected as input to the watchdog timer In addition all analog blocks are shut down and the flash is in stand by mode In Deep sleep mode the application can keep the watchdog oscillator and the BOD circuit running for self timed wake up and BOD protection The LPC11U2x can wake up from Deep sleep mode via reset selected GPIO pins a watchdog timer interrupt or an interrupt generating USB port activity Deep sleep mode saves power and allows for short wake up times Power down mode In Power down mode the LPC11U2x is in Sleep mode and all peripheral clocks and all clock sources are off except for watchdog oscillator if selected In addition all analog blocks and the flash are shut down In Power down mode the application can keep the BOD circuit running for BOD protection The LPC11U2x can wake up from Power down mode via reset selected GPIO pins a watchdog timer interrupt or an interrupt generating USB port activity All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 25 of 74 NXP Semiconductors LPC11U2x 7 17 5 5 7 17 6 7 17 6 1 7 17 6 2
87. t data sheet Rev 2 3 27 March 2014 3 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 5 Block diagram XTALIN XTALOUT RESET LPC11U2x TEST DEBUG INTERFACE CLOCK GENERATION POWER CONTROL CLKOUT SYSTEM FUNCTIONS ARM CORTEX MO System bus slave slave 17 slave O master ae USB_DP HIGH SPEED use vevice USB_DM GPIO ports 0 1 ARBEITE BUS slave CONTROLLER USB_VBUS C USB FTOGGLE slave U USB_CONNECT AHB TO APB RXD BRIDGE Ee EU EN USART EO p SMARTCARD INTERFACE K 10 bit ADC SCLK 2C SCL SDA CT16BO MAT 2 0 C l C BUS 16 bit COUNTER TIMERO CT16BO_CAP 1 0 2 SSPO SCKO SSELO CT16B1 MATT 1 0 x 16 bit COUNTER TIMER 1 MISOU MOSIQ CT16B1_CAP 1 0 2 CT32B0_MAT 3 0 SSP4 SCK1 SSEL1 32 bit COUNTER TIMER 0 MISO1 MOSI1 CT32B0_CAP 1 0 2 SpA MAI 32 bit COUNTER TIMER 1 C Les DI CT32B1 CAP 1 0 2 SYSTEM CONTROL WINDOWED WATCHDOG TIMER PMU GPIO pins GPIO INTERRUPTS GPIO pins GPIO GROUPO INTERRUPTS lt GPIO pins GPIO GROUP1 INTERRUPTS NX 002aag333 1 Not available on HVQFN33 packages 2 CT32B1 CAP available on TFBGA48 LQFP64 packages only 1680 CAP1 and CT16B1 CAP1 available on LQFP64 packages only CT32BO CAP1 available on LQFP48 TFBGA48 LQFP64 packages only Fig 1 Block diagram LPC11U2X All information provided i
88. t is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 21 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller 7 17 Clocking and power control 7 17 1 Integrated oscillators The LPC11U2x include three independent oscillators the system oscillator the Internal RC oscillator IRC and the watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular application Following reset the LPC11U2x operates from the internal RC oscillator until software switches to a different clock source The IRC allows the system to operate without any external crystal and the bootloader code to operate at a known frequency See Figure 7 for an overview of the LPC11U2x clock generation LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 22 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller peripheral clocks SYSAHBCLKCTRLn AHB clock enable IRC oscillator main clock SSPO PERIPHERAL CLOCK DIVIDER SSPO watchdog oscillator USART PERIPHERAL CLOCK DIVIDER UART MAINCLKSEL main clock select SYSTEM PLL CPU system control PMU SYSTEM CLOCK System clock n DIVIDER Da memories SSP1 PERIPHERAL CLOCK DIVIDER SSP1 IRC oscilla
89. to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 58 of 74 NXP Semiconductors LPC11U2x 12 Package outline 32 bit ARM Cortex M0 microcontroller HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals body 7 x 7 x 0 85 mm Fig 34 Package outline HVQFN33 7 x 7 x 0 85 mm LPC11U2X All information provided in this document is subject to legal disclaimers D terminal 1 index area E A A1 Y i detail X Y gt L Y L 1 In 4 e t Eh e2 Y d Y terminal 1 index area 0 2 5 2mm 1 Lol i 1 Dimensions scale Unit ADU A b c 00 Dp E e e L w y y max 1 00 0 05 0 35 7 1 4 85 7 1 4 85 0 75 mm nom 0 85 0 02 0 28 0 2 7 0 4 70 7 0 4 70 0 65 4 55 4 55 0 60 0 1 0 05 0 08 0 1 min 0 80 0 00 0 23 6 9 4 55 6 9 4 55 0 45 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included hvqfn33_po References Outline European Issue date version IEC JEDEC JEITA projection gt co SES 09 03 23 NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 59 of 74 NXP Semiconductors LPC11U2x 32 bit
90. tor system oscillator SYSPLLCLKSEL system PLL clock select system oscillator USB PLL USB 48 MHz CLOCK USB USBPLLCLKSEL USB clock select USBUEN USB clock update enable IRC oscillator System oscillator CLKOUT PIN CLOCK CLKOUT pin watchdog oscillator DIVIDER P CLKOUTUEN CLKOUT update enable IRC oscillator WDT watchdog oscillator WDCLKSEL WDT clock select 002aaf892 Fig 7 LPC11U2x clocking generation block diagram 7 17 1 1 Internal RC oscillator The IRC can be used as the clock source for the WDT and or as the clock that drives the system PLL and then the CPU The nominal IRC frequency is 12 MHz Upon power up any chip reset or wake up from Deep power down mode the LPC11U2x use the IRC as the clock source Software can later switch to one of the other available clock sources LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 23 of 74 NXP Semiconductors LPC11U2x 7 17 1 2 7 17 1 3 7 17 2 7 17 3 7 17 4 7 17 5 LPC11U2X 32 bit ARM Cortex M0 microcontroller System oscillator The system oscillator can be used as the clock source for the CPU with or without using the PLL On the LPC11U2x use the system oscillator to provide the clock source to USB The system oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be
91. tors LPC11U2x LPC11U2X 32 bit ARM Cortex M0 microcontroller 002aag746 20 Ipp Vpp 3 6 V 3 3 V pA Vpp 2 0 V Vpp 1 8 15 40 15 10 35 60 85 temperature C Conditions BOD disabled all oscillators and analog blocks turned off in the PDSLEEPCFG register USB_DP and USB_DM pulled LOW externally Fig 13 Typical supply current versus temperature in Power down mode 002aag747 0 8 g 40 15 10 35 60 85 temperature C Fig 14 Typical supply current versus temperature in Deep power down mode 9 3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG for analog blocks registers All other blocks are disabled in both registers and no code is executed Measured on a typical sample at Tamp 25 C Unless noted otherwise the system oscillator and PLL are running in both measurements The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 39 of 74 NXP Semiconductors LPC11U2x 32 bit ARM Cortex M0 microcontroller
92. ty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the public
93. uctors LPC11U2x 32 bit ARM Cortex M0 microcontroller Table 3 Pin description Symbol a IS Reset Type Description Z 9 state gt O X l c c amp TRST PIOO_14 AD3 24 7 35 46 18 EPU Test Reset for JTAG interface 2 1 PIOO 14 General purpose digital input output pin AD3 A D converter input 3 CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO PIOO 15 AD4 25 39 52 18 VO SWDIO Serial wire debug input output 2 1_ 2 PIOO 15 General purpose digital input output pin AD4 A D converter input 4 CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIOO 16 AD5 26 A6 40 53 18 PU VO PIOO 16 General purpose digital input output pin CT32B1_MAT3 WAKEUP In Deep power down mode this pin functions as the WAKEUP pin with 20 ns glitch filter Pull this pin HIGH externally to enter Deep power down mode Pull this pin LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part AD5 converter input 5 CT32B1_MAT3 Match output 3 for 32 bit timer 1 PIOO 17 RTS 30 A3 45 60 8 VO PIOO 17 General purpose digital input output pin CT32B0_CAPO SCLK RTS Request To Send output for USART CT32B0_CAP0 Capture input 0 for
94. ved 0x1000 2000 8 SRAM LPC11U2x 401 SRAM LPC11U2x 301 reserved 0x1000 1800 32 bit counter timer 0 0x4001 4000 0x1000 0000 16 bit counter timer 1 _ 0x4001 0000 16 bit counter timer 0 0x4000 C000 USART SMART CARD 0x4000 8000 0x0000 8000 WWDT 0x4000 4000 0x0000 6000 32 kB on chip flash LPC11U24 I C bus 0x4000 0000 oj m IN o 0x0000 4000 0x0000 00CO 16 kB on chip flash LPC11U22 active interrupt vectors 0x0000 0000 0x0000 0000 002aag594 Fig 6 LPC11U2x memory 7 6 Nested Vectored Interrupt Controller NVIC The Nested Vectored Interrupt Controller NVIC is part of the Cortex MO The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 6 1 Features Controls system exceptions and peripheral interrupts n the LPC11U2x the NVIC supports 24 vectored interrupts LPC11U2X All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved Product data sheet Rev 2 3 27 March 2014 16 of 74 NXP Semiconductors LPC11U2x 7 6 2 T LPC11U2X 7 7 7 1 7 8 32 bit ARM Cortex M0 microcontroller Four programmable interrupt priority levels with hardware priority level masking Software interrupt generation Interrupt sources Each peripheral device has one interrupt line connected to

LPC11U2x - NXP Semiconductors

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