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1. 11371 00 9602 Figure 1 3 MVME130x Switches LEDs Headers Connectors 1 9 Preparing the PowerBase With the jumper installed between pins 3 and 4 factory configuration the debugger uses the current user setup operation parameters in EEPROM When the jumper is removed making the bit a 1 the debugger uses the default setup operation parameters in ROM instead Refer to the ENV command description in Chapter 6 for the ROM defaults The five higher order bits SRH3 to SRH7 are required to get GCSR locations for up to 18 boards when used in a Wide Area Network WAN The MVME130x is shipped from the factory with J2 set to all 0s jumpers on all pins each PowerBase board in the system must have a unique address in order for the system to function correctly These addresses are given in Table 1 2 There is a method to issue commands to the PPCBug on the PowerBase board via the VMEbus This method utilizes the Global Control and Status Registers GCSR in the VMEchip2 Eight 16 bit registers are included in the GCSR set These registers are accessible in the VMEbus short I O space responding to address modifier codes 29 or 2D The specific address of the GCSR on the VMEbus is programmed in the VMEchip2 LCSR by the debugger and is determined by the conditions described below At start up PPCBug when executing on PowerBase reads the state of the upper five jumpers on the softw
2. Connector Location Table VMEbus connector T Pi Cl VMEbus connector PMC Slot 1 for I O P2 C 2 Debug serial port RJ45 JA C 3 RISCwatch header J3 C 4 CPU debug connector J4 C 5 PROM mezzanine connector J8 J9 C 6 PMC connector Slot 1 for 32 bit PCI J11 J12 C 7 Slot 2 for 32 bit PCI J21 J22 C 8 Slot 1 for P2 I O J14 C 9 Pin Assignments The following tables furnish pin assignments only For detailed descriptions of the various interconnect signals consult the support information documentation for the MVME130x contact your Motorola sales office and or the support information section of the MVME762 transition module and SIM705 documentation VMEbus Connector P1 Two 96 pin connectors P1 and P2 supply the interface between the base board and the VMEbus P1 provides power and VME signals for 24 bit addressing and 16 bit data Its pin assignments are set by the VMEbus specification They are listed in the following table C 1 Pin Assignments ON Oo FWOND Table C 1 VMEbus Connector Pin Assignments P1 VDO VBBSY VD8 VD1 VBCLR VD9 VD2 VACFAIL VD10 VD3 VBGINO VD11 VD4 VBGOUTO VD12 VD5 VBGIN1 VD13 VD6 VBGOUT1 VD14 VD7 VBGIN2 VD15 GND VBGOUT2 GND VSYSCLK GND VBGIN3 VBGOUT3 VSYSFAIL VBERR VDS1 VBRO VSYSRESET VDSO VBR1 VLWO
3. STARTUP pr Power up reset initialization INITIALIZATION P initialize devices on the PowerBase board system POST p gt Power On Self Test diagnostics BOOTING P Firmware configured boot mechanism if so configured Default is no boot MONITOR P Interactive command driven on line PowerPC debugger when terminal connected Figure 5 1 PowerPC Debugger Architecture Restarting the PowerBase Debug Monitor The debug monitor interactive command level is available if a terminal is connected to the DEBUG port At the monitor a number of different commands may be entered to interact with the hardware Specifically the commands are routed through various drivers in the firmware This way the actual register settings and commands used by the hardware are transparent to a firmware user The firmware user only needs to be familiar with the basic PPCBug commands Restarting the PowerBase Break You can initialize the PowerBase to a known state in three different ways a Break a Reset a Abort Each has certain characteristics which make it more appropriate than the others in given situations A break is generated by pressing and releasing the BREAK key on the current console keyboard Break does not generate an interrupt The only time break is recognized is when characters are sent or received by the console port Break performs the following a Removes any
4. Control and Status Registers 0 0 0 128MB Not Present 1 1 1 Not Present Not Present 1 1 0 8MB 8MB 1 0 1 32MB 32MB 1 0 0 128MB 128MB Note Theonly valid combinations for PowerBase are 010 binary and 110 binary ASYM Asymmetric Refresh Mode When cleared this bit indicates that the DRAM devices installed for Bank 0 and Bank 1 Bank 2 and Bank 3 have more row address bits than column address bits This bit is used to determine how to program the MPC105 chip appropriately For 1M x16 DRAM the asymmetric refresh mode is also referred to as the 4K refresh mode For these devices there would be 12 row address bits and 8 column address bits General Purpose I O Port The general purpose I O port is used to provide various functions This port is mapped into the ISA I O space The assignments for the port pins are as shown in Table 4 10 Table 4 10 General Purpose I O Port Pins Assignment Port Pin Signal Name Direction Signal Name PAO BRDFAILO Output Board Fail when set will cause FAIL LED to be lit PAI TBENDIS_ Output TBEN Disable If cleared TBENDIS_ will drive proces sor s TBEN pin low to disable its internal timebase PA2 N A Output N A PA3 N A Output N A PA4 FNR Input FNR 2 0 means PROMmez is installed PA5 PARITY_ Input PARITY_ 0 means parity DRAM is present 4 22 Programming the PowerBase Table 4 10 General Purpose I O Po
5. PowerBase Architecture utilizing P2 I O it is necessary for customers to design their own connectivity transition scheme Note Motorola offers a transition board the MVME762 for use with the PowerBase However this board was designed to support only one configuration of a PowerBase PMC combination the PowerCom MVME130x with the MPMC282 01x MC68360 PMC installed For more details on this transition board refer to the MVME762 and PowerCom documentation listed in Appendix A Figure 1 1 shows the PowerBase board and the positions of the PMCs and PROM mezzanine The block diagram in Figure 1 2 illustrates the architecture of the MVME130x base board Add on PROM Module LEDs Debug Port Add on PCI Mezzanine Card PMC2 o PMC2 Front Panel yo PMC1 Front Panel or P2 yo Add on PCI Mezzanine Card P2 PMC1 PowerBase Board 11372 Figure 1 1 PowerBase with Optional PROM and PMC Mezzanines 1 2 Preparing and Installing the PowerBase m Optional MPC603 PROM Flash PowerPC 1 MB ioe ee MPC603 Bus DRAM MPC105 8 or 16MB Parity Option PCI Bus VME2PCI PCI ISA Bridge ASIC PMC Slot 1 PMC Slot 2 ISA Bus PC16550 VMEchip2 UART ASIC VMEbus Reha TR poe tat eee ee ida niox ed te Ne ee Neth ee gee Le ee ee ee ME Te ee Boe Vg fee Do Meee weav
6. Document Title and Source FuoHcanon Number PowerPC 603 RISC Microprocessor Technical Summary MPC603 D Motorola Literature and Printing Distribution Services P O Box 20924 Phoenix Arizona 85036 0924 Telephone 602 994 6561 FAX 602 994 6430 PowerPC 603 RISC Microprocessor User s Manual MPC603UM AD Motorola Literature and Printing Distribution Services P O Box 20924 Phoenix Arizona 85036 0924 Telephone 602 994 6561 FAX 602 994 6430 OR IBM Microelectronics MPR603UMU 01 Mail Stop A25 862 1 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC Telephone 1 800 769 3772 FAX 1 800 POWERfax FAX 1 800 769 3732 Manufacturers Documents Table A 2 Manufacturers Documents Continued Publication Document Title and Source Number MPC105 PCI Bridge Memory Controller User s Manual MPC105UM AD Motorola Literature and Printing Distribution Services P O Box 20924 Phoenix Arizona 85036 0924 Telephone 602 994 6561 FAX 602 994 6430 PowerPC Microprocessor Family The Programming Environments MPCFPE AD Motorola Literature and Printing Distribution Services P O Box 20924 Phoenix Arizona 85036 0924 Telephone 602 994 6561 FAX 602 994 6430 OR IBM Microelectronics MPRPPCFPE 01 Mail Stop A25 862 1 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC Telephone 1 800 769 3772 FAX
7. FA12 FA14 GND FA16 FA18 GND FOE RCS1 L BMDO GND BMD2 BMD4 GND BMD6 BMD8 GND BMD10 BMD12 GND BMD14 BMD16 GND BMD18 BMD20 Oo RP 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Connector Pin Assignments PCI Mezzanine Card Connectors J11 and J12 Two 64 pin connectors J11 and J12 supply the interface between the PowerBase board and an optional PCI mezzanine card PMC The pin assignments for PMC Slot 1 are listed in the following table Table C 7 PMC1 Connector Pin Assignments J11 and J12 TCK 12V GND INTA_ INTB_ INTC_ PMCPRSNT1_ f 5V INTD_ Not Used GND Not Used CLK GND GND PMCGNT1_ PMCREQ1_ 5V 5V AD31 AD28 AD27 AD25 GND GND C BE3_ AD22 AD21 AD19 5V 5V AD17 FRAME GND GND IRDY_ DEVSEL_ 5V GND LOCK_ SDONE_ SBO_ PAR GND 5V AD15 12V TRST_ TMS TDO TDI GND GND Not Used Not Used Not Used Pull up 3 3V RST_ Pull down 3 3V Pull down Not Used GND AD30 AD29 GND AD26 AD24 3 3V IDSEL1 AD23 3 3V AD20 AD18 GND AD16 C BE2_ GND Not Used TDRY_ 3 3V GND STOP PERR GND 3 3V SERR_
8. The remote GO command causes the following sequence a Remote processor places the PowerBase execution address in general purpose registers 0 and 1 GPCSRO and GPCSR1 a Remote processor sets bit 8 SIGO of the VMEchip2 LM SIG register 4 PowerBase installs breakpoints and begins execution The result is identical to the MPCR method with status code B described in a previous section Using PPCBug The GCSR registers are accessed in the VMEbus short I O space Each general purpose register is two bytes wide occurring at an even address The general purpose register number 0 is at an offset of 8 local bus or 4 VMEbus from the start of the GCSR registers The local bus base address for the GCSR is variable The VMEbus base address for the GCSR depends on the group select value and the module select value programmed in the Local Control and Status Registers LCSR of the PowerPC board The execution address is formed by reading the GCSR general purpose registers in the following manner GPCSRO used as the upper 16 bits of the address GPCSR1 used as the lower 16 bits of the address The address appears as GPCSRO GPCSR1 Data and Address Sizes Data and address sizes are defined as follows A byte is eight bits numbered 0 through 7 with bit 0 being the least significant A half word is 16 bits numbered 0 through 15 with bit 0 being the least significant A word is 32 bits numbered 0 through
9. a Calculated BUS clock speed does not match the associative CNFG parameter a Selftest error failure MPU Clock Speed Calculation The MPU clock speed is calculated and checked against a user definable parameter housed in EEPROM refer to the CNFG command in Chapter 6 of this manual and to the PPCBug Firmware Package User s Manual If the check fails a warning message displays The calculated clock speed is also checked against known clock speeds and tolerances Memory Requirements The debugger requires a total of 512KB of read write memory The debugger allocates this memory starting from the top of memory For example on a system which contains 64MB 04000000 of read write memory i e DRAM the debugger s memory page is located at 03F80000 to 03FFFFFF MPU Hardware and Firmware Initialization The debugger performs the MPU hardware and firmware initialization process This process occurs each time the PowerBase is reset or powered up The steps below are a high level outline not all of the detailed steps are listed 1 Sets MPU MSR to known value 2 Invalidates the MPU s data instruction caches 3 Clears all segment registers of the MPU 5 8 o AN Oo GO A 12 13 14 15 16 17 18 19 20 2 22 MPU Hardware and Firmware Initialization Clears all block address translation registers of the MPU Initializes the MPU bus to PCI bus bridge device Initializes the PC
10. as shown in the diagram below Bit 0 SRHO Bit 1 SRH1 Bit 2 SRH2 Bit 3 SRH3 Bit 4 SRH4 Bit 5 SRH5 Bit 6 SRH6 Bit 7 SRH7 1 15 J2 PPCBug INSTALLED 2 Reserved for future use Setup parameter source InZEEPROM Out ROM Reserved for future use Board selection in WAN Board selection in WAN Board selection in WAN Board selection in WAN 16 Board selection in WAN The PowerPC firmware PPCBug reserves all bits SRHO to SRH7 1 8 Preparing and Installing the PowerBase VME BUS P1 P2 6 l AT A32 Ai ase B1 B32 B1 B32 C1 ae c32 Gi T C32 PMC SLOT 2 PMC SLOT 1 PMC SLOT 1 I O tr e J22 J12 J14 2 z Z g PMC SLOT 2 PMC SLOT 1 9 be z J21 J11 I J8 2 s z N o ul a E z o a a J5 SYSTEM 35 CONTROLLER i HEADER 1 PROM FLASH PROM FLASH SOCKET SOCKET a S XU1 XU2 o W z O J4 o i a J8 SOFTWARE Pu READEABLE 9 HEADER RISC WATCH ABORT RESET FAL PMC2 DEBUG SWITCH swiTcH TES CEO PORT 4 2 A st se feo Ms 8 AO esgos s OQ I I I I TI TI c E E O U IL x 2 S PES 3 E o 3 w Fd z nN zz amp a 9 o Ec BIS ko i fi E 2 s VO O dOsns 5 lt 3 o amp
11. 00100 System Reset Used for the abort switch soft reset feature 00700 Program Used for instruction breakpoints 00CO0 System Call Used for the System Call Handler 02000 Run Mode Used for instruction tracing These vectors may be taken over under a user s application However prior to returning control to the debugger these vectors must be restored for proper operation of the affected features Advanced Debugger Topics MPU Registers Certain MPU registers must be preserved for their specific uses MPU Register SPR275 MPU register SPR275 is reserved for use by the debugger If SPR275 is to be used by the user program it must be restored prior to utilizing debugger resources system calls and or returning control to the debugger MPU Registers SPR272 SPR274 These MPU registers are utilized by debugger as scratch registers Context Switching Context switching is the switching from the debugger state to the user target state or vice versa This switching occurs upon the invocation of either the GD GN GO GT T or TT commands or the return from user state to the debugger state User State to Debugger State When the context switch transitions from the user state to the debugger state the following MPUisters are captured RO R31 General Purpose Registers FRO FR31 Floating Point Unit Data Registers SRO SR15 Segment Registers SPRn Special Purpose Registers n is 1 8 9 18 19 22 25 26 27 268 269 275
12. 1 800 POWERfax FAX 1 800 769 3732 PC16550 UART PC16550DV National Semiconductor Corporation Customer Support Center or nearest Sales Office 2900 Semiconductor Drive P O Box 58090 Santa Clara California 95052 8090 Telephone 1 800 272 9959 82378 System I O SIO PCI to ISA Bridge Controller 290473 003 Intel Corporation Literature Sales P O Box 7641 Mt Prospect Illinois 60056 7641 Telephone 1 800 548 4725 A Ordering Related Documentation Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table A 3 Related Specifications Publication Document Title and Source Number VME64 Specification ANSI VITA 1 1994 VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale Arizona 85260 3415 Telephone 602 951 8866 FAX 602 951 0720 NOTE An earlier version of this specification is available as Versatile Backplane Bus VMEbus ANSI IEEE Institute of Electrical and Electronics Engineers Inc Standard 1014 1987 Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 OR Microprocessor system bus for 1 to 4 byte data TEC 821 BUS Bur
13. 23 EMS GND PMCIO45 23 PMCIO46F See Note C 3 Pin Assignments Table C 2 VMEbus Connector Pin Assignments P2 Continued 24 PMCIO48 VD25 PMCIO47 24 25 PMCIO50 VD26 PMCIO49 25 26 PMCIO52 VD27 PMCIO51 26 27 PMCIO54 VD28 PMCIO53 27 28 PMCIO56 VD29 aaee 28 PMCIO55F See Note 29 PMCIO58 VD30 PMCIO57 29 30 PMCIO60 VD31 PMCIO59 30 31 PMCIO62 GND PMCIO61 31 32 PMCIO64 45V PMCIO63 32 Note Fused lines are used with the MVME762 transition board factory configuration C 4 Connector Pin Assignments Debug Serial Port J1 Table C 3 Debug Serial Port Pin Assignments J1 DCD EXT RTS EXT GND TD EXT RD EXT GND CTS EXT DTR EXT On Oa 5 o Nvv RISCwatch Header J3 Table C 4 RISCwatch Header Pin Assignments J3 MPC603 Pin Header Pin 240 Pin QFP MPC603 I O Resistor TDO TDI 4 7K pull up TRST 220 ohm pull down 3 3V 1K series TCK 4 7K pull up O CO N 0 oc A O N TMS 4 7K pull up SRESET 4 7K pull up HRESET 10K pull up KEY CHECKSTOP 4 7K pull up GND C 5 Pin Assignments Note The QACK signal on the MPC603 has a 1K ohm pull down resistor to allow the MPC603 processor to enter the state required for reading and writing SCAN string data CPU Connector J4 One 190 pin SMT connector with center row of power and grou
14. C BE1_ GND AD14 AD13 C 11 C Pin Assignments Table C 7 PMC1 Connector Pin Assignments J11 and J12 Continued 47 49 51 53 55 57 59 61 63 AD12 AD11 ADO 45V GND C BEO ADO6 ADO05 ADO04 GND 45V AD03 ADO2 ADO1 ADOO 45V GND REQ64_ 48 50 52 54 56 58 60 62 64 47 49 51 53 55 57 59 61 63 GND AD10 AD08 3 3V ADO7 Not Used 3 3V Not Used Not Used GND Not Used Not Used GND Not Used ACK64_ 3 3V GND Not Used C 12 Connector Pin Assignments PCI Mezzanine Card Connectors J21 and J22 Two 64 pin connectors J21 and J22 supply the interface between the PowerBase board and an optional PCI mezzanine card PMC The pin assignments for PMC Slot 2 are listed in the following table Table C 8 PMC2 Connector Pin Assignments J21 and J22 TCK 12V GND INTA_ INTB_ INTC_ PMCPRSNT2 f 5V INTD_ Not Used GND Not Used CLK GND GND PMCGNT2_ PMCREQ2_ 5V 5V AD31 AD28 AD27 AD25 GND GND C BES AD22 AD21 AD19 5V 5V AD17 FRAME GND GND IRDY_ DEVSEL_ 5V GND LOCK_ SDONE_ SBO_ PAR GND 5V AD15 AD12 AD11 12V TRST_ TMS TDO TDI GND GND Not Used Not Used Not Used Pull up 3 3V RST_ Pull down 3 3V Pull down Not Used GND AD30 AD29 GND AD26 AD24 3 3V IDSEL2 AD23 3 3V A
15. PCI ISA I O Space Notes 1 The IBC PCI ISA bridge performs subtractive decoding in this range and forward the PCI memory cycle to the ISA if DEVSEL is not detected 2 The VME2PCI ASIC can be programmed to claim some of this address range to forward the PCI memory cycle to the VMEchip2 4 7 Memory Maps VMEbus Memory Map The VMEbus is programmable The mapping of local resources as viewed by VMEbus masters varies among applications The VMEchip2 ASIC includes a user programmable map decoder for the VMEbus to local bus interface The map decoder enables you to program the starting and ending address and the modifiers to which the MVME130x responds The VMEchip2 also includes a user programmable map decoder for the GCSRs global control status registers accessible from both the VMEbus and the local bus The GCSR map decoder allows you to program the starting address of the GCSRs in the VMEbus short I O space The VME2PCI ASIC supplies the interface between the PCI local bus and the VMEchip2 ASIC Table 4 5 shows the mapping of onboard resources from the point of view of the VME2PCI and Table 4 6 shows the mapping of onboard resources from the point of view of the VMEchip2 4 8 Table 4 5 VME2PCI View of the Memory Map Programming the PowerBase PCI poses Configuration Register Name Read Write E ndn Address
16. Symmetric MultiProcessing A computer architecture in which tasks are distributed among two or more local processors Surface Mount Technology A method of mounting devices such as integrated circuits resistors capacitors and others on a printed circuit board characterized by not requiring mounting holes Rather the devices are soldered to pads on the printed circuit board Surface mount devices are typically smaller than the equivalent through hole devices The term used to describe any single program or group of programs languages operating procedures and documentation of a computer system A computing system is normally spoken of as having two major components hardware and software Software is the real interface between the user and the computer Static Random Access Memory Source Synchronous BLock Transfer A set of detailed technical guidelines used as a means of establishing uniformity in an area of hardware or software development Super Video Graphics Array IBM An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 800 x 600 pixels One way broadcast of digital information The digital information is injected in the broadcast TV signal VBI or full field The transmission medium could be satellite microwave cable etc The display medium is a regular TV receiver GL 11 J o0ooro 2 o0o00r o Glossary thick Ethernet 10Base5 An Ethern
17. and a functional description of the PowerBase general purpose VMEbus board based on the PowerPC 603 microprocessor PowerBase is a powerful low cost embedded VME controller as well as an intelligent Peripheral Component Interconnect PCI Mezzanine Card PMC carrier board One of the primary applications for the PowerBase board is as a Wide Area Network WAN Controller module for the telecommunications market worldwide PowerBase Architecture PowerBase consists of the base board which may be an MVME1301 MVME1302 MVME1305 or MVME1306 These modules include support circuitry such as parity DRAM PROM Flash memory and bridges to the Industry Standard Architecture ISA bus and the VMEbus PowerBase s PMC carrier architecture allows flexible configuration options and easy upgrades It is designed to support one optional add on PROM mezzanine module plus two PMCs in a single VMEmodule slot Optional PROM mezzanine board contains sockets for 4MB of One Time Programmable OTP PROM organized as 64 bits wide Optional PMC products include capabilities such as Asynchronous Transfer Mode ATM Fiber Distributed Data Interface FDDI Fast Ethernet Fast Wide Small Computer System Interface SCSI 2 and high speed serial connectivity The PowerBase board supports front panel and P2 I O on PMC slot 1 and front panel I O only on PMC slot 2 Additionally the 64 pins of I O from PMC slot 1 are routed directly to P2 When 1 1
18. 127 WT 129 GLOBAL 131 SHARED 133 AACK 135 ARTY 137 DRTY 139 TA 141 TEA 143 145 147 DBB 149 TCLK OUT ABB 151 L2PRSNT 153 CPUGNT 155 CPUREQ INT 157 L2DIRTYI_ MCPI_ 159 L2DIRTYO_ SMI 161 L2DOE CKSTPI_ 163 LOWE_ CKSTPO_ 165 L2HIT HALTED 167 L2TALE TLBISYNC 169 L2TALOE TBEN 171 L2TOE SUSPEND 173 L2TWE DRVMODO 175 L2TV DRVMOD1 177 L2INT NAPRUN 179 SRESET QREQ 181 HRESET QACK 183 GND TDO 185 CPUCLK1 TDI 187 CPUCLK2 TCK 189 CPUCLKS TMS TRST_ 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 Connector Pin Assignments C 9 Pin Assignments PROM Mezzanine Connectors J8 and J9 Two 64 pin surface mount connectors J8 and J9 supply the interface between the add on PROM mezzanine and the PowerBase The pin assignments are listed in the following two Table C 6 PROM Mezzanine Connectors Pin Assignments J8 and J9 tables FA0 FA2 GND FA4 FA6 GND FA8 FA10 GND
19. 18 GENERAL PURPOSE CONTROL AND STATUS REGISTER 4 E 1C GENERAL PURPOSE CONTROL AND STATUS REGISTER 5 Note Refer to the PowerBase Embedded Controller Programmer s Reference Guide for the bit and register functions of the last six registers above when PPC1Bug uses the registers VME2PCI ASIC Programming Model The VME2PCI ASIC provides the necessary interface between the PCI Local Bus and the VMEchip2 The Control and Status Registers of the VME2PCI ASIC consist of The VMEchip2 CSR window the Pseudo IACK Registers and the PCI Configuration Registers All these registers can be mapped anywhere in the PCI Memory Space and or PCI I O Space The mapping is done by programming the appropriate base address registers of the VME2PCI Configuration Registers In addition the PCI Configuration Registers are also accessible from the PCI Configuration Space Figures 4 1 and 4 2 illustrate how the VME2PCI Control and Status Registers can be mapped 4 14 PCI LOCAL BUS PCI MEMORY SPACE MEM BASE 0 VME2PCI CSRs Programming the PowerBase MEM BASE EFFF MEM BASE F000 MEM BASE F7FF MEM BASE F800 FFF40000 aa M VMEchip2 CSR WINDOW FFF4EFFF gt IACK REGISTERS IACK CYCLES MEM BASE FFFF CONFIGURATION REGISTERS VMEchip2 VMEchip2 CSR INTERRUPT HANDLER 11192 00 9411 Figure 4 1 VME2PCI s CSR Mapping in PCI Memory Space PCI LOCAL BUS PCI I O SPACE IO BAS
20. 282 287 528 543 976 981 1008 1010 IP Instruction Pointer copy of SPR26 MSR Machine State Register copy of SPR27 CR Condition Register FPSCR Floating Point Status Control Register Floating Point Support Debugger State to User State When the context switch transitions from the debugger state to the user state the following MPU registers are restored RO R31 General Purpose Registers FRO FR31 Floating Point Unit Data Registers SPRn Special Purpose Registers n is 1 8 9 275 1010 IP Instruction Pointer copied to SPR26 MSR Machine State Register copied to SPR2 CR Condition Register FPSCR Floating Point Status Control Register Note that on a restoration context switch registers whose perspectives feature MMU characteristics and operating modes of the MPU are not restored The debugger honors the user s MMU configuration If the user s program wishes to utilize the programmatic interface i e system calls of the debugger it must maintain the address translation of 1 to 1 and the I O resources utilized by the debugger must be data cache inhibited Floating Point Support The MD and MM commands allow display and modification of floating point data in memory Use either the MD command or the MM command to assemble or disassemble floating point instructions Valid data types that can be used when modifying a floating point data register or a floating point memory location Integer Data Types B
21. 31 with bit 0 being the least significant Byte Ordering The MPU on the PowerBase is programmed to big endian byte ordering Any attempt to use small endian byte ordering immediately renders the PPCBug debugger unusable Performing Diagnostic Tests Performing Diagnostic Tests The PPCBug hardware diagnostics are intended for testing and troubleshooting the PowerBase board In order to use the diagnostics you must switch to the diagnostic directory You may switch between directories by using the SD Switch Directories command You may view a list of the commands in the directory that you are currently in by using the HE Help command If you are in the debugger directory the debugger prompt PPC1 Bug gt displays and all of the debugger commands are available Diagnostics commands cannot be entered at the PPCl Bug prompt If you are in the diagnostic directory the diagnostic prompt PPC1 Diag gt displays and all of the debugger and diagnostic commands are available The diagnostic test groups are listed in the following table Using the HE command you can list the diagnostic routines available in each test group Refer to the PPC1Bug Diagnostics Manual for complete descriptions of the diagnostic routines and instructions on how to invoke them Table 5 1 Diagnostic Test Groups Test Group Description 182378 182378 PCI ISA Bridge Tests PC16550 PC16550 UART Tests RAM Local RAM Tests PCIBUS PCI Bus
22. 5 Using PPCBug You may also wish to obtain the PPC1Bug Diagnostics Manual listed in the table entitled Motorola Computer Group Documents in Appendix A Ordering Related Documentation What you need to do Refer to On page Unpack the hardware Unpacking the Hardware 1 7 Configure the hardware by Configuring the Hardware 1 7 setting jumpers on the board Preparing the PowerBase 1 8 Install optional PMC s if any Installing Optional PMCs 1 17 PMC Slots 2 4 For additional information on PMCs refer to the documentation furnished with the PMCs Connect a console terminal Installing the Hardware 1 13 Debug Port 2 3 Installation Considerations 1 18 Connect any other optional Connector Pin Assignments C 1 devices or equipment you will For more information on optional be using devices and equipment refer to the documentation provided with that equipment Power up the system Installing the Hardware 1413 Status Indicators DS1 DS4 2 2 If any problems occur refer to the section 5 17 Overview of Start Up Procedures Table 1 1 Start Up Overview Continued What you need to do Refer to On page Change any environmental ENV Set Environment 6 2 parameters as you wish You may also wish to obtain the PPCBug Firmware Package User s Manual listed in the table Motorola Computer Group Documents in Appendix A Ordering Related Documentation Install the optional PROM Installing an
23. 80802000 00802000 PCI Vendor ID R 1057 80802002 00802002 PCI Device ID R 4800 80802004 00802004 PCI Command R W 0000 80802006 00802006 PCI Status R W 0000 80802008 00802008 PCI Revision ID R 01 80802009 00802009 PCI Class Code R 068000 8080200C 0080200C PCI Cache Line Size R W 00 8080200D 0080200D PCI Latency Timer R W 00 8080200E 0080200E PCI Header Type R 00 80802010 00802010 PCII O Base Address R W 00000001 80802014 00802014 PCI Memory Base Address R W 00000000 8080203C 0080203C PCIInterrupt Line R W 00 8080203D 0080200D PCI Interrupt Pin R 01 8080203E 0080200E PCI Minimum Grant R 00 8080203F 0080200F PCI Maximum Latency R 00 80802040 00802040 Slave Starting Address 1 R W 0000 80802042 00802042 Slave Ending Address 1 R W 0000 80802044 00802044 Slave Address Offset 1 R W 0000 80802046 00802046 Slave Address Enable 1 R W 00 80802048 00802048 Slave Starting Address 2 R W 0000 8080204A 0080204A Slave Ending Address 2 R W 0000 8080204C 0080204C Slave Address Offset 2 R W 0000 8080204E 0080204E Slave Address Enable 2 R W 00 80802050 00802050 Interrupt Status and Control R W 0000 4 9 Memory Maps Table 4 6 VMEchip2 Memory Map Sheet 1 of 3 VMEchip2 LCSR Base Address BASE 0000 OFFSET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SLAVE ENDING ADDRESS 1 4 SLAVE ENDING ADDRESS 2 8 SLAVE ADDRESS TRANSLATION ADDRESS 1 C SLAVE ADDRESS TR
24. Functional Description bridge memory controller the 82378ZB ISA bridge controller the VME2PCI chip and the two PMC slots The MPC980 provides the 16MHz clock that is used for the VMEbus SYSCLK when the PowerBase board is configured as the VMEbus system controller The MPC980 also provides the 14 31818MHz clock for the counter timers inside the 82378ZB ISA bridge controller IBC 2 A 1 8432MHz oscillator which is used by the baud rate generator inside the PC16550 UART chip VMEbus Interface The VMEbus interface is provided by the VMEchip2 ASIC Since the VMEchip2 local bus interface is the MC68040 bus the VME2PCI ASIC is also required The VMEchip2 ASIC in tandem with the VME2PCI ASIC constitutes the VMEbus interface The VMEchip2 interfaces an MC68040 style local bus to the VMEbus The VME2PCI interfaces the PCI bus to an MC68040 style local bus When the VMEchip2 and the VME2PCI chips are used together they form a PCI bus to VMEbus interface The VMEchip2 VME2PCI combination provides a The local bus to VMEbus interface a The VMEbus to local bus interface a The DMA controller functions of the local VMEbus The VMEchip2 includes Global Control and Status Registers GCSRs for interprocessor communications It can provide the VMEbus system controller functions as well For detailed programming information refer to the VMEchip2 and VME2PCI discussions in the PowerBase Embedded Controller Programmer s Reference G
25. IBC Refer to the 82378ZB data sheet for programming information on this timer PowerBase Components VMEchip2 Timers EEPROM There are two programmable 32 bit timers in the VMEchip2 Refer to the PowerBase Embedded Controller Programmer s Reference Guide for programming information on the VMEchip2 There is one 28C64 EEPROM device that provides 8KB of non volatile storage for configuration information and environment variables Refer to Chapter 6 for more about the configurable environment parameters PROM Mezzanine Card Slot The PowerBase provides for an add on PROM mezzanine board The PROM mezzanine interface to the PowerBase is via two 64 pin connectors These connectors are the same type as those used for PMC boards The PROM mezzanine provides eight 32 pin PLCC sockets that support one bank of 512Kx8 devices for a total of 4MB of PROM memory The memory is organized as 64 bits wide and is controlled by the MPC105 When installed the PROM mezzanine will disable the onboard PROM Flash memory because the MPC105 cannot support both memory interfaces simultaneously The supported package is for one time programmable OTP PLCC devices The appropriate PROM device type is AM27C040 150JC or equivalent Since the devices are socketed it is assumed that they must be programmed externally before installation on the board Note The PROM mezzanine can optionally be configured to use PLCC Flash devices by changing several zero o
26. In RGB systems the color of a pixel is defined by some Red intensity some Green intensity and some Blue intensity Phase Locked Loop PCI Mezzanine Card Performance Optimized With Enhanced RISC architecture IBM The trademark used to describe the Performance Optimized With Enhanced RISC microprocessor architecture for Personal Computers developed by the IBM Corporation PowerPC is superscalar which means it can handle more than one instruction per clock cycle Instructions can be sent simultaneously to three types of independent execution units branch units fixed point units and floating point units where they can execute concurrently but finish out of order PowerPC is used by Motorola Inc under license from IBM GL 8 Glossary PowerPC 601 PowerPC 6037 PowerPC 603e PowerPC 6047 The first implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 256 entry buffer and a 32KB unified instruction and data cache It provides a 64 bit data bus and a separate 32 bit address bus PowerPC 601 is used by Motorola Inc under license from IBM The second implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 64 entry buffer and an 8KB instruction and data cache It provides a selectable 32 bit or 64 bit data bus and a separate 32 bit address bus PowerPC 603 is used by Motorola Inc under licen
27. In general a debugger command is made up of the following parts a The command name e g MD or md Note that either uppercase or lowercase is allowed At least one intervening space before the first argument a Any required arguments as specified by command Entering Debugging Commands a One or more options Precede an option or a string of options with a semi colon If no option is entered the command s default option conditions are used Conventions The following conventions are used in the descriptions of the commands arguments and options that follow boldface strings italic strings Command Arguments A boldface string is a literal such as a command name program name or option and is to be typed just as it appears An italic string is an argument A vertical bar separating two or more items indicates that a choice is to be made only one of the items separated by this symbol should be selected Square brackets enclose an item that is optional The item may appear zero or one time Braces enclose an optional symbol that may occur zero or more times The following arguments are common to many of the commands Additional arguments are defined in the descriptions of commands found in the PPCBug Firmware Package User s Manual You will also see the arguments for each command when you type HE to display the help menu EXP Expression see EXP on page 5 20 ADDR Address see ADDR on
28. PMC Slot Tests Using PPCBug Notes 1 You may enter command names in either uppercase or lowercase 2 Some diagnostics depend on restart defaults that are set up only in a particular restart mode Refer to the documentation on a particular diagnostic for the correct mode 5 Entering Debugging Commands PPCBug is command driven and performs its various operations in response to commands that you enter at the keyboard When the debugger prompt rPci Bug appears on the screen then the debugger is ready to accept commands What you enter is stored in an internal buffer Execution begins only after you press the Return key allowing you to correct entry errors if necessary using the control characters described in the PPCBug General Information chapter After the debugger executes the command the prompt reappears However if the command causes execution of user target code for example GO then control may or may not return to the debugger depending on what the user program does For example if a breakpoint has been specified then control returns to the debugger when the breakpoint is encountered during execution of the user program Alternately the user program could return to the debugger by means of the System Call Handler routine RETURN described in the PPCBug Firmware Package User s Manual For more about this refer to the GD GO and GT command descriptions in the PPCBug Firmware Package User s Manual
29. Software Readable Header 4 0802 8000 0802 8004 0002 Board Configuration Register 4 0804 8000 0804 8004 0004 DRAM Size Register 4 0846 8000 0846 8004 2006 General Purpose I O Register 4 Notes 1 All ISA I O locations not specified in this table are reserved 2 These locations are internally decoded by the IBC PCI ISA bridge 3 These locations are internally decoded by the UART Memory Maps 4 These locations are either not specified by the PRP specification or not PRP compliant They may overlap some other functions specified by the PRP specification 5 The board comes up in contiguous mode Contiguous and discontiguous modes are programmed by the MPC105 PCI bridge memory controller The PPCBug debugger and several operating systems AN execute in contiguous mode If this is changed to Caution discontiguous mode PPCBug will cease functioning correctly 4 6 PCI Local Bus Memory Map Programming the PowerBase Table 4 4 shows the PCI Memory Map of the PowerBase from the point of view of the PCI Local Bus Table 4 4 PCI View of the PCI Memory Map PCI Address Processor Bus Address Nm Size Definition Notes Start End Start End 00000000 O0FFFFFF 16MB Not forwarded to MPU bus PCI ISA Memory Space 1 2 01000000 7FFFFFFF 2GB Not forwarded to MPU bus PCI Memory Space 2 16MB 80000000 FFFFFFFF 2GB 00000000 7FFFFFFF Onboard DRAM via MPC105 00000000 FFFFFFFF 4GB Not forwarded to MPU bus
30. TX 78758 3493 Document Specification Ordering Telephone 1 800 PowerPC Telephone 1 800 769 3772 Telephone 708 296 9332 PCI Local Bus Specification MPR PPC RPU 02 A 5 A Ordering Related Documentation A 6 PowerBase Specifications Specifications lists the general specifications for the PowerBase boards The subsequent sections detail cooling requirements and FCC compliance A complete functional description of the PowerBase boards appears in Chapter 3 Specifications for the optional PMCs can be found in the documentation for those modules Table B 1 PowerBase Specifications Power requirements with no PMCs installed See Note Characteristics Specifications MPU MPC603 66MHz SPECint92 estimated baseline peak 37 9 47 9 SPECint92 estimated baseline peak 43 9 48 0 Memory DRAM 8MB or 16MB with optional byte parity EEPROM 8KB PROM Flash or 1MB or 4MB via optional mezzanine OTP ROM via optional mezzanine Timers via VMEchip2 One watchdog timer Two 32 bit tick timers 5Vdc 45 4 0A typical 5 8A maximum 12Vdc 0mA 12Vdc 0mA typical Operating temperature Storage temperature 0 C to 55 C entry air with forced air cooling refer to Cooling Requirements section 40 C to 85 C Relative humidity Vibration operating 5 to 90 non condensing 2 Gs RMS 20Hz 2000Hz random B 1 Specifications Table B 1 PowerBas
31. Table 4 12 shows the PCI arbitration assignments for all PCI masters on the PowerBase Figure 4 3 shows the arbitration configuration diagram of the IBC Additional details on PCI arbitration can be found in the PowerBase Embedded Controller Programmer s Reference Guide Table 4 11 PCI Arbitration Assignments PCIBUS CPUREQ IBCREQ REQO REQ1 REQ2 REQ3 REQUEST PCI CPU IBC PMCI VME PMC2 MASTER MPC105 Internal Slot 1 VME2PCI Slot 2 4 24 Programming the PowerBase IBCREQ INTERNAL TO IBC REQO BANK 0 FIXED CONTROL BANK 0 A ROTATE CONTROL BANK 0 REQ1 00 0 REQ2 BANK 3 jl coi BANK2 i 1 m 10 FIXED CONTROL BANK 3 A ic ROTATE CONTROL BANK 3 CPUREQ 0 SEG BANK 1 1 FIXED CONTROL BANK 1 ROTATE CONTROL BANK 1 FIXED CONTROL BANK 2 A FIXED CONTROL BANK 2 B ROTATED CONTROL BANK 2 11187 00 9411 Figure 4 3 IBC Arbiter Configuration Diagram Interrupt Handling The MVME130x supports both maskable and non maskable interrupts Figure 4 4 illustrates the interrupt architecture 4 25 Programming Considerations INT we INT MPC603 0 IBC o e O ui z z Q O H NM gt B e MPC105 gt MCP SERR amp PERR gt PCI INTERRUPTS gt ISA INTERRUPTS 11412 Figure 4 4 MVME
32. a watchdog time out or by a control bit in the LCSR in the VMEchip2 SYSRESET remains asserted for at least 200 ms as required by the VMEbus specification Similarly the VMEchip2 provides an input signal and a control bit to initiate a local reset operation By setting a control bit software can maintain a board in a reset state disabling a faulty board from participating in normal system operation The local reset driver is enabled even when the VMEchip 2 is not the system controller A local reset may be generated by the RESET switch a power up reset a watchdog time out a VMEbus SYSRESET or a control bit in the GCSR Status Indicators DS1 DS4 There are four LED light emitting diode status indicators located on the MVME130x front panel CPU FAIL PMC1 and PMC2 CPU DS1 This green LED indicates CPU activity lights when the DBB Data Bus Busy signal line on the processor bus is active FAIL DS4 This yellow LED indicates board failure lights when the BRDFAIL signal line is active PMC1 DS3 This green LED indicates PCI activity lights when the PCI bus grant to PMC1 signal line on the PCI bus is active This indicates that a PMC if installed is active PMC2 DS2 This green LED indicates PCI activity lights when the PCI bus grant to PMC2 signal line on the PCI bus is active This indicates that a PMC if installed is active 2 2 Using the Front Panel DEBUG Port The RJ45 port labeled DE
33. as listed in table Motorola Computer Group Documents in Appendix A Ordering Related Documents Some options however are not software programmable Such options are controlled through manual installation or removal of header jumpers or interface modules on the base board or the associated modules Serial ports on the optional PMC boards are manually configurable For a discussion of the configurable items on the PMCS refer to the user s manual for the particular PMC 1 7 Preparing the PowerBase Preparing the PowerBase Figure 1 3 illustrates the placement of the switches jumper headers connectors and LED indicators on the MVME130x Manually configurable items on the base board include a General purpose software readable header J2 a VMEbus system controller selection J5 The MVME130x has been factory tested and is shipped with the configurations described in the following sections The MVME130x factory installed debug monitor PPCBug operates with those factory settings Setting the General Purpose Software Readable Header J2 Header J2 provides eight readable jumpers These jumpers can be read as a register at ISA I O address 801 hexadecimal Bit 0 is associated with header pins 1 and 2 bit 7 is associated with pins 15 and 16 The bit values are read as a 0 when the jumper is installed and as a 1 when the jumper is removed The MVME130x is shipped from the factory with J2 set to all 0s jumpers on all pins
34. board made of nonconducting material such as plastic or fiberglass on which chips and other electronic components are mounted Also referred to as a circuit board or card bits per inch bits per second The pathway used to communicate between the CPU memory and various input output devices including floppy drives and hard disk drives Available in various widths 8 16 and 32 bit with accompanying increases in speed A high speed memory that resides logically between a central processing unit CPU and the main memory This temporary memory holds the data and or instructions that the CPU is most likely to use over and over again and avoids frequent accesses to the slower hard drive or floppy disk drive Column Address Strobe The clock signal used in dynamic RAMs to control the input of column addresses Compact Disc A hard round flat portable storage unit that stores information digitally Compact Disk Read Only Memory Cubic Feet per Minute GL 2 Glossary CISC Complex Instruction Set Computer A computer whose processor is designed to sequentially run variable length instructions many of which require several clock cycles that perform complex tasks and thereby simplity programming CODEC COder DECoder Color Difference CD The signals of R Y and B Y without the luminance Y signal The Green signals G Y can be extracted by these two signals Composite Video Signal CVS CVBS Signal that
35. breakpoints in the user code 4 Keeps the breakpoint table intact a Takes a snapshot of the machine state if the function was entered using SYSCALL a Allows access to the snapshot for diagnostic purposes 5 5 Using PPCBug Reset Abort Many times it may be desirable to terminate a debugger command prior to its completion for example the display of a large block of memory Break allows you to terminate the command immediately A system reset is initiated by pressing and releasing the PowerBase board s RESET switch Cold and warm reset modes are available By default PPCBug is in cold mode refer to the RESET command description in the PPCBug Firmware Package User s Manual During cold reset a total system initialization takes place as if the PowerBase had just been powered up a All static variables are restored to their default states a The breakpoint table and offset registers are cleared The target registers are invalidated Input and output character queues are cleared a Onboard devices are reset a The first two serial ports are reconfigured to their default state During warm reset the PPCBug variables and tables are preserved as well as the target state registers and breakpoints Note that revision 1 1 of the PPCBug does not support the warm reset feature Reset must be used if the processor ever halts or if the PPCBug environment is ever lost vector table is destroyed stack corrup
36. cleared VMEbus Present If set there is no VMEbus interface If cleared VMEbus interface is supported 4 20 GFXP_ LANP_ SCSIP_ DRAM Size Register Programming the PowerBase Always set Graphics Present If set there is no onboard graphics interface If cleared there is an onboard graphics capability MVME1300 series has no graphics Always set Ethernet Present If set there is no Ethernet transceiver interface If cleared there is onboard Ethernet support MVME1300 series has no onboard Ethernet support Always set SCSI Present If set there is no onboard SCSI interface If cleared onboard SCSI is supported MVME1300 series has no onboard SCSI interface The DRAM Size Register is an 8 bit register providing the DRAM size information Banks 0 and 1 if present are on the PowerBase s board REG DRAM Size Register 0804h BIT SD6 SD5 SD4 SD3 SD2 SD1 SDO FIELD B2 B3 B2 B3 B2 B3 B2 B3 BO B1 BO B1 BO B1 BO B1 SIZ2 SIZ1 SIZO ASYM SIZ2 SIZ1 SIZO OPER R R R R R R R RESE 1 1 1 N A N A N A N A T SIZ2 SIZ0 DRAM Size These bits provide the DRAM size information for the two banks of DRAM supported by the PowerBase The encoding for these size bits is as follows BO B1 B2 B3 DRAM Size SIZ2 SIZ1 Bank 0 Bank 2 Bank 1 Bank 3 Not Present Not Present 0 1 0 8MB Not Present 0 0 1 32MB Not Present 4 21
37. for encoding or decoding Used by some USA TV and IC manufacturers for color decoding GL 5 J oooro 2 0o00r o Glossary ISA bus ISASIO ISDN LAN LED LFM little endian MBLT MCA bus MCG MFM MIDI MPC MPC105 MPC601 MPC603 MPC603e Industry Standard Architecture bus The de facto standard system bus for IBM compatible computers until the introduction of VESA and PCI Used in the reference platform specification IBM ISA Super Input Output device Integrated Services Digital Network A standard for digitally transmitting video audio and electronic data over public phone networks Local Area Network Light Emitting Diode Linear Feet per Minute A byte ordering method in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte Multiplexed BLock Transfer Micro Channel Architecture Motorola Computer Group Modified Frequency Modulation Musical Instrument Digital Interface The standard format for recording storing and playing digital music Multimedia Personal Computer The PowerPC to PCI bus bridge chip developed by Motorola for the Ultra 603 Ultra 604 system board It provides the necessary interface between the MPC603 MPC604 processor and the Boot ROM secondary cache the DRAM system memory array and the PCI bus Motorola s c
38. in effect when this publication went to print Note that where a prompt refers to NVRAM the PowerBase uses EEPROM Note also that some parameters are not applicable to PowerBase e g those for SCSI and the automatic booting routines Bug or System environment B S B B Do not run the self test diagnostics during system start up Display the PPC1 Bug prompt if the start up fails or if you exit from the start up sequence Default Run the self test diagnostics during system start up Display the PPC1 Diag prompt if the start up fails or if you exit from the start up sequence Field Service Menu Enable Y N N Y N Display system menu in place of a debugger prompt if the start up fails or if you exit from the start up sequence Display a debugger prompt if the start up fails or if you exit from the start up sequence Default Remote Start Method Switch G M B N B The method for executing a cross loaded program when the PowerBase is cross loaded from another VME based CPU G Use the Global Control and Status Register GCSR method to pass and start execution of cross loaded program VMEchip2 Use the Multiprocessor Control Register MPCR method in shared RAM to pass and start execution of cross loaded program Use both the GCSR and the MPCR methods to pass and start execution of cross loaded program Do not use any remote start method 6 3 Advanced Debugger Topics Probe System for
39. page 5 22 COUNT Count the syntax is the same as for EXP see EXP on page 5 20 Using PPCBug EXP RANGE TEXT PORT Use either a space or a comma to separate arguments You may A range of memory addresses specified with a pair of arguments either ADDR ADDR or ADDR COUNT An ASCII string of up to 255 characters delimited at each end by the single quote mark Port Number see PORT on page 5 23 select the default value for an argument by inserting a pair of commas in place of the argument The EXP expression argument can be one or more numeric values separated by the arithmetic operators amp lt lt gt gt Numeric values may be expressed in either hexadecimal decimal octal or binary by immediately preceding them with the proper plus minus multiply by divide by logical AND shift left shift right base identifier Data Type Base Identifier Examples Integer Hexadecimal FFFFFFFF Integer Decimal amp amp 1974 amp 10 amp 4 Integer Octal 456 Integer Binary 1000110 Entering Debugging Commands If no base identifier is specified then the numeric value is assumed to be hexadecimal A numeric value may also be expressed as a string literal of up to four characters The string literal must begin and end with the single quote mark The numeric value is interpreted as the concatenation of the ASCII values of the characte
40. reset Default NVRAM Bootlist GEV fw boot path Boot Abort Delay 5 The time in seconds that the start up sequence waits before starting NVRAM Bootlist boot During the delay a user may exit to the debugger or diagnostics prompt by pressing the BREAK key The value may be from 0 255 Auto Boot Enable Y N N Y Enable Auto Boot N Disable Auto Boot Default Auto Boot at power up only Y N N Y Run Auto Boot at power up reset only N Run Auto Boot at any reset 6 5 Advanced Debugger Topics Auto Boot Scan Enable Y N Y Y Auto Boot boots from the devices in the Auto Boot scan Device Type List Default N Auto Boot boots from the CLUN and DLUN Auto Boot Scan Device Type List FDISK CDROM TAPE HDISK The order in which Auto Boot selects available boot devices if Auto BootScan Enable is set to Y The entries must be uppercase and be separated by back slashes V Auto Boot Controller LUN 00 The boot controller Logical Unit Number Auto Boot Device LUN 00 The boot device Logical Unit Number Auto Boot Partition Number 00 The disk partition that the boot is run from as specified in the PowerPC Reference Platform specification The valid partitions are 1 2 3 or 4 If the parameter is set to 0 the firmware searches the partitions in order until it finds the first bootable partition Auto Boot Abort Delay 7 The time in seconds that the start up sequence waits b
41. significant address bits logical 0 is nonsignificant Master Control 4 00 The access characteristics for the address space defined with this master address decoder Local Bus Slave Attribute Register Advanced Debugger Topics Short I O VMEbus A16 Enable Y N Y Y Enable the Short I O Address Decoder Default N Disable the Master Address Decoder Short I O VMEbus A16 Control 01 The access characteristics for the address space defined with the Short I O address decoder Local Bus to VMEbus I O Control Register F Page VMEbus A24 Enable Y N Y Y Enable the F Page Address Decoder Default N Disable the F Page Address Decoder F Page VMEbus A24 Control 02 The access characteristics for the address space defined with the F Page address decoder Local Bus to VMEbus I O Control Register EC2 Vector Base 1 06 The base interrupt vector VMEchip2 Base Vector 0 for the component specified EC2 Vector Base 2 07 The base interrupt vector VMEchip2 Base Vector 1 for the component specified EC2 GCSR Group Base Address D8 The group address FFFFxx00 in Short I O for this board EC2 GCSR Board Base Address 00 The base address FFFFD8x0 in Short I O for this board Entering and Debugging Programs VMEbus Global Time Out Code 02 The VMEbus time out VGTO when the VMEchip2 is systems control
42. with a flammability rating of 94V 0 The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc 1995 and may be used only under a license such as those contained in Motorola s software licenses The software described herein and the documentation appearing herein are furnished under a license agreement and may be used and or disclosed only in accordance with the terms of the agreement The software and documentation are copyrighted materials Making unauthorized copies is prohibited by law No part of the software or documentation may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means without the prior written permission of Motorola Inc Motorola and the Motorola symbol are registered trademarks of Motorola Inc PowerPC 6037 is a trademark of International Business Machines Corporation PowerPC is a trademark of International Business Machines Corporation and is used by Motorola with permission All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyright Motorola 1996 All Rights Reserved Printed in the United States of America May 1996 Preparing and Installing the PowerBase Introduction This manual provides general information hardware preparation and installation instructions operating instructions
43. 001EFB Version 4 00001EFC 00001F07 Serial number 12 00001F08 00001F17 Board ID 16 00001F18 00001F27 PWA 16 00001F28 00001F2B Reserved 0 4 00001F2C 00001F31 Ethernet address 6 00001F32 00001F33 Reserved 1 2 2 3 3 00001F34 00001F35 Local SCSI ID 00001F36 00001F38 MPU Speed in MHz 00001F39 00001F3B Bus Speed in MHz 00001F3C 00001FF6 Reserved 187 00001FF7 Checksum 1 Programming the PowerBase Control and Status Registers The PowerBase has the following Control and Status Registers CSRs a CPU Configuration Register a Software Readable Header Register 4 Board Configuration Register a DRAM Size Register a General Purpose I O Port Programming information for these registers is provided in the PowerBase Embedded Controller Programmer s Reference Guide CPU Configuration Register The CPU Configuration Register provides configuration information about the processor CPU Configuration Register 0800 CPUTYPE R L2P1 L2P0 L2 Cache present These bits are defined as follows L2P1 L2P0 L2 Cache Size 0 0 512KB 0 1 256KB 1 0 1MB 1 1 L2 Cache Not Present For the PowerBase this field is hardwired to 11b 4 17 Control and Status Registers CKM1 CKM0 Clocking configuration These bits reflect the clocking configuration of the PowerBase The encoding for these bits is as CPUTYPE foll
44. 1 Figure 4 7 Little Endian Mode 4 33 Programming Considerations 4 34 Using PPCBug PPCBug Overview The PPCBug firmware is the layer of software just above the hardware The firmware provides the proper initialization for the devices on the PowerBase board upon power up or reset This chapter describes the basics of PPCBug and its architecture describes the monitor interactive command portion of the firmware in detail and gives information on actually using the PPCBug debugger and the special commands A complete list of PPCBug commands appears at the end of the chapter Chapter 6 contains information about the CNFG and ENV commands system calls and other advanced user topics PPCBug Basics The PowerPC debug firmware PPCBug is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers Facilities are available for loading and executing user programs under complete operator control for system evaluation PPCBug provides a high degree of functionality user friendliness portability and ease of maintenance It achieves good portability and comprehensibility because it was written entirely in the C programming language except where necessary to use assembler functions PPCBug includes commands for a Display and modification of memory 4 Breakpoint and tracing capabilities 5 1 Using PPCBug A powerful assembler and disassembler useful for patchi
45. 130x 7 Reinstall the MVME130x board in the chassis according to the instructions given in the Installing the PowerBase section of this chapter Installing Optional PMCs Proceed as follows to install optional PCI mezzanine cards PMCs on your PowerBase board 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure Note If your MVME130x has not yet been installed in a chassis go to step 4 2 Perform an operating system shutdown a Turn the AC or DC power off and remove the AC cord or DC power lines from the system Inserting or removing modules with power applied may result in damage to module components gt Caution Dangerous voltages capable of causing death are present in this equipment Use extreme caution when Warning handling testing and adjusting gt Installation Considerations J Caution b Remove chassis or system cover s as necessary for access to the VMEmodules 3 Remove the screws securing the MVME130x to the chassis and remove the MVME130x from its card slot 4 Lay the MVME130x on a level surface with the P1 and P2 connectors closest to you and position the PMC above it in the center for PMC2 or left hand side for PMC1 Refer to Figure 1 1 Avoid touching areas of integrated circuitry static discharge can damage these circuits 5 Ins
46. 130x Interrupt Architecture 4 26 Programming the PowerBase Machine Check Interrupt MCP The IBC can be programmed to assert NMI when it detects either SERR low on the PCI Local Bus or IOCHK low on the ISA bus However IOCHK is not used on the MVME130x The MPC105 will assert MCP to the processor upon detecting a high level on NMI from the IBC Note that MPC105 also monitors SERR and PERR It can be programmed to asserted MCP when it detects a low level on either SERR or PERR The MPC105 can also be programmed to assert MCP under many other conditions Refer to the PowerBase Embedded Controller Programmer s Reference Guide for additional information on the MCPs interrupt signal Maskable Interrupts The IBC supports 15 interrupt requests These 15 interrupts are ISA type interrupts that are functionally equivalent to two 82C59 interrupt controllers Except for IROO IRQ1 IRQ2 IRQ8 and IRQ13 each of the interrupt lines can be configured for either edge sensitive or level sensitive mode by programming the appropriate ELCR registers in the IBC There IBC also supports four PCI interrupts INT3 INT0O The IBC has four PIRQ Route Control Registers to allow each PCI interrupt line to be routed to any of eleven ISA interrupt lines IRQO IRQ1 TRQ2 IRQ8 and IRQ13 are reserved for ISA system interrupts Since PCI interrupts are defined as level sensitive software must program the selected IRQ s for level s
47. 4 IRQ3 IRQ2 IRQI EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN IRQ RQ RQ IRQ RQ IRQ IRQ IRQ IRQ IRQ RQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 SET SET SET SET SET SET SET SET IRQ RQ RQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 CLR CLR CLR CLR CLR CLR CLR CLR IRQ RQ RQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 P ERROR IRQIE TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SIG 1 SIG 0 LM 1 LMO IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SW3 Sw2 swt swo IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IRQ 4 VMEB IRQ 3 VME IRQ 2 VME IRQ 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL GPIOO GPIOI GPI RG REV DIS DIS So DIS EN DIS EN EROM SRAM MST gas BSYT INT BGN 1361 9403 This sheet begins on facing page 4 13 Memory Maps Table 4 6 VMEchip2 Memory Map Sheet 3 of 3 VMEchip2 GCSR Base Address BASE 0100 Offsets VME lLocal 15 14 13 12 11 10 9 8 716 5 4 ale2l1lo bus Bus 0 0 CHIP REVISION CHIP ID 2 4 LM3 LM2 LM1 LMO SIG3 SIG2 SIG1 SIGO RST ISF BF SCON SYSFL X X X 4 8 GENERAL PURPOSE CONTROL AND STATUS REGISTER 0 6 C GENERAL PURPOSE CONTROL AND STATUS REGISTER 1 8 10 GENERAL PURPOSE CONTROL AND STATUS REGISTER 2 A 14 GENERAL PURPOSE CONTROL AND STATUS REGISTER 3 C
48. A EN WP S U P D EN D16 WP S U SIZE SPEED SPEED EN EN EN 15 14 13 12 11 10 9 8 4 6 5 4 3 2 1 0 ARB MAST MAST MST MST MASTER DMA DMA DMA DMA DM DMA ROBN DHB DWB FAIR RWD VMEBUS HALT EN TBL FAIR RELM VMEBUS DMA DMA LB DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA TBL SNP MODE INC INC WRT D16 D64 BLK AM AM AM AM AM AM INT VME LB BLK 5 4 3 2 1 0 LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER MPU MPU MPU MPU MPU DMA DMA DMA DMA DMA DMA DMA DMA TABLE CLR LBE LPE LOB LTO LBE LPE LOB LTO TBL VME DONE INTERRUPT COUNT STAT ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR 1360 9403 This sheet begins on facing page 4 11 Memory Maps Table 4 6 VMEchip2 Memory Map Sheet 2 of 3 VMEchip2 LCSR Base Address BASE 0000 OFFSET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BGTO DMA DMA GLOBAL 4C EN TIME OFF TIME ON TIMER 99 TICK TIMER 1 2 TICK TIMER 1 58 TICK TIMER 2 5C TICK TIMER 2 SCON SYS BRD PURS CLR BRD RST SYS WD WD WD TO WD WD WD 60 FAIL FAIL STAT PURS FAIL SW RST CLR CLR TO BF SRST RST STAT STAT OUT EN TO CNT STAT EN LRST EN EN 64 PRE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AC AB SYS MWP PE IRQ1E TIC2 TIC1 VME DMA SIG3 SIG2 SIG1 SIG
49. ANSLATION ADDRESS 2 ADDER SNP WP SUP USR A32 A24 ah BLK PRGM DATA2 10 2 2 2 2 2 2 2 2 2 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 MASTER ENDING ADDRESS 1 18 MASTER ENDING ADDRESS 2 1C MASTER ENDING ADDRESS 3 20 MASTER ENDING ADDRESS 4 24 MASTER ADDRESS TRANSLATION ADDRESS 4 MAST MAST MAST MAST 28 D16 WP MASTER AM 4 D16 WP MASTER AM 3 EN EN EN EN GCSR MAST MAST MAST MAST 2C GCSR GROUP SELECT BOARD SELECT ER Eu e 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WAIT ROM DMA TB SRAM 30 RMW ZERO SNP MODE SPEED 34 38 DMA CONTROLLER 3C DMA CONTROLLER 40 DMA CONTROLLER 44 DMA CONTROLLER TICK TICK CLR IRQ VMEBUS 48 2A IRQ 1 IRQ STAT INTERRUPT VMEBUS INTERRUPT VECTOR EN LEVEL This sheet continues on facing page 4 10 Programming the PowerBase 15 14 13 12 11 10 9 8 f 6 5 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER SNP WP SUP USR A32 A24 BIK BLK PRGM DATA1 D64 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST MAST D16 WP MASTER AM 2 D16 WP MASTER AM 1 EN EN EN EN 102 102 102 102 101 101 101 101 ROM ROM BANK B ROM BANK
50. BUG on the front panel of the PowerBase supplies the PowerBase serial communications interface implemented via a UART PC16550 controller chip from National Semiconductor It is asynchronous only This serial port is configured for EIA 232 D DTE as shown in Figure 2 1 The DEBUG port may be used for connecting a terminal to the PowerBase to serve as the firmware console for PowerBase s factory installed debugger PPCBug The port is configured as follows 4 8 bits per character 1 stop bit per character a Parity disabled no parity a Baud rate 9600 baud default baud rate at power up SOUT gt o 4 RTS 5o 2 DTR 7o 8 SIN lt 5 CTS lt 7 DCD lt 1 3 6 PC16550 ES V Debug Figure 2 1 Debug Port Configuration 2 3 PMC Slots After power up the baud rate of the DEBUG port can be reconfigured by using the debugger s Port Format PF command Refer to Chapters 5 and 6 for information about PPCBug PMC Slots Two openings located on the front panel provideI O expansion by allowing access to one or two single wide or one double wide PCT Mezzanine Card PMC connected to the PMC connectors on the PowerBase For pin assignments for the PMC connectors refer to Appendix C Do not attempt to install any PMC boards without performing an operating system shutdown and Warning following the procedures given in Chapter 1 For further information on PMCs r
51. D20 AD18 GND AD16 C BE2_ GND Not Used TDRY_ 3 3V GND STOP PERR GND 3 3V SERR_ C BE1_ GND AD14 AD13 GND AD10 C Pin Assignments Table C 8 PMC2 Connector Pin Assignments J21 and J22 Continued 49 51 53 55 57 59 61 63 ADO 45V GND C BEO ADO6 AD05 AD04 GND 5V AD03 AD02 ADO1 ADOO 45V GND REQ64 50 52 54 56 58 60 62 64 49 51 53 55 57 59 61 63 AD08 3 3V ADO7 Not Used 3 3V Not Used Not Used GND Not Used Not Used GND Not Used ACK64_ 3 3V GND Not Used C 14 Connector Pin Assignments PCI Mezzanine Card I O Connector J14 The mapping of the PMC Slot 1 I O connector J14 to the VMEbus P2 connector is as follows Table C 9 PMC1 Connector Pin Assignments for I O J14 and VMEbus P2 Gi 2 A1 C2 C3 C4 C5 C6 C7 C8 C9 C 15 Glossary Abbreviations Acronyms and Terms to Know This glossary defines some of the abbreviations acronyms and key terms used in this document 10Base5 10Base2 10BaseT ACIA AIX architecture ASCII ASIC AUI BBRAM bi endian big endian See thick Ethernet See thin Ethernet See twisted pair Ethernet Asynchronous Communications Interface Adapter Advanced Interactive eXecutiv
52. D800 is used for all others 31 From EEPROM XXX 1 1 Notes 1 The first three jumper positions for bits SRHO through 2 may have unrelated functions This is represented above as xxx An I jumper installed on the pins a no jumper on the pins 2 Default setting Preparing the PowerBase Setting the VMEbus System Controller Selection Header J5 The MVME130x is factory configured in automatic system controller mode i e a jumper is installed across pins 1 and 2 of header J5 This means that the MVME130x determines if it is system controller at system power up or reset by its position on the bus if it is in slot 1 on the VME system it configures itself as the system controller Install the jumper across pins 2 and 3 if you intend to operate the MVME130x as system controller in all cases Remove the jumper from J5 if the MVME130x is not to operate as system controller under any circumstances J5 J5 J5 1 1 1 Jl I 2 3 3 3 Automatic System Controller System Controller Enabled System Controller Disabled factory configuration Preparing and Installing the PowerBase Installing the Hardware The following paragraphs discuss the installation of the PowerBase into a VME chassis and installing the optional PMC boards and PROM mezzanine board onto the PowerBase Taking ESD Precautions Use ESD Wrist Strap M
53. Diagnostics Manual PPCIDIAA UM MVME762 Transition Module User s Manual VME762A UM SIM705 Serial Interface Module Installation Guide SIM705A TH Notes 1 Although not shown in the above list each Motorola Computer Group manual publication number is suffixed with characters that represent the revision level of the document such as xx2 the second revision of a manual a supplement bears the same number as the manual but has a suffix such as xx2A1 the first supplement to the second revision of the manual 2 Motorola documents marked with a in the above list can be purchased as a set under part number LK PWRCOM when it becomes available The content of this set may be revised as needed and without any notice to the customer A Ordering Related Documentation Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice To further assist your development effort Motorola has collected some of the non Motorola documents in this list from the suppliers This bundle can be ordered as part number 68 PCIKIT The contents of this set is revised as needed and without any notice to the customer Table A 2 Manufacturers Documents
54. E 0 VME2PCI CSRs IO BASE EFFF IO BASE F000 VMEchip2 CSR WINDOW IO BASE F7FF IO BASE F800 Pa IACK REGISTERS CONFIGURATION IO BASE FFFF REGISTERS FFF40000 FFF4EFFF IACK CYCLES VMEchip2 VMEchip2 CSR INTERRUPT HANDLER 11193 00 9411 Figure 4 2 VME2PCI s CSR Mapping in PCI I O Space 4 15 Memory Maps EEPROM Memory Map The EEPROM is divided into five areas as shown in Table 4 7 The first four areas are defined by software while the fifth area is reserved for future use The first area is reserved for user data The second area is open The third area is used by the PowerBase board debugger PPCBug The fourth area detailed in Table 4 8 is the configuration area The EEPROM chip is not a direct address mapped device The EEPROM address strobe registers in conjunction with the EEPROM data port register must be used to gain access i e read write of data Table 4 7 EEPROM Memory Map Offset start end Description Size Bytes 00000000 00000FFF EEPROM per the PRP specification 4096 00001000 000010FF Open 1784 000016F8 00001EF7 Debugger area 2048 00001EF8 00001FF7 Configuration area see Table 4 8 256 00001FF8 00001FFF Reserved for future use 8 Table 4 8 EEPROM Configuration Area Memory Map Offset start end Description Size Bytes 00001EF8 00
55. Ebus system controller functions VMEbus interface to local bus A24 A32 D8 D16 D32 BLT D8 D16 D32 D64 Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 VMEbus interrupter VMEbus interrupt handler Global CSR for interprocessor communications DMA for fast local memory VMEbus transfers A16 A24 A32 D16 D32 D64 a Interfaces to two P1386 1 PCI Mezzanine Cards PMCs Accepts two single width PMCs or one double width PMC Front panel and or VMEbus P2 I O on PMC slot 1 3 2 Functional Description Front panel I O on PMC slot 2 4 One asynchronous serial port debug port via an RJA5 front panel connector a 8 bit Software Readable Header a 8KB of EEPROM 2 RESET switch a ABORT switch Status LEDs for FAIL CPU PMC1 and PMC2 Refer to Appendix B for product specifications PowerBase Components Figure 3 1 is a block diagram of the MVME130x s overall architecture RISCWatch Header A 16 pin male 2x8 header is provided for connecting to the RISCWatch MPC603 processor interface MPC603 interconnect information is provided in Appendix C PCI Bridge Memory Controller MPC105 A Motorola MPC105 device provides the necessary interface between the MPC603 processor the Flash memory the PROM the DRAM and the PCI Local Bus The MPC105 supports various PowerPC processor external bus frequencies up to 66 66MHz and PCI frequencies up to 33 33MHz Table 3 1 summar
56. FFFFFFFFFFFF Local SCSI Identifier No System Serial Number o 7 2 ii System Identifier c 729929 999 9 2 9 99 9 9 9 9 2 99 2 The parameters that are quoted are left justified character ASCII strings padded with space characters and the quotes are displayed to indicate the size of the string Parameters that are not quoted are considered data strings and data strings are right justified The data strings are padded with zeroes if the length is not met The Board Information Block is factory configured before shipment There is no need to modify block parameters unless the EEPROM is corrupted Refer to the PowerBase Embedded Controller Programmer s Reference Guide for the actual location and other information about the Board Information Block Refer to the PPCBug Firmware Package User s Manual for a description of CNFG and examples ENV Set Environment Use the ENV command to view and or configure interactively all PPCBug operational parameters that are kept in EEPROM Refer to the PPCBug Firmware Package User s Manual for a description of the use of ENV Additional information on control and status registers that affect these parameters is contained in the PowerBase Embedded Controller Programmer s Reference Guide Modifying Parameters in EEPROM Configuring the PPCBug Parameters Listed and described below are the parameters that you can configure using ENV The default values shown were those
57. I bus to ISA bus bridge device Calculates the external bus clock speed of the MPU Delays for 750 milliseconds Determines the CPU base board type 10 11 Sizes the local read write memory i e DRAM Initializes the read write memory controller Sets base address of memory to 00000000 Retrieves the speed of read write memory from EEPROM Initializes the read write memory controller with the speed of read write memory Retrieves the speed of read only memory i e Flash from EEPROM Initializes the read only memory controller with the speed of read only memory Enables the MPU s instruction cache Copies the MPU s exception vector table from FFF00000 to 00000000 Verifies MPU type Verifies the external bus clock speed of the MPU Determines the debugger s console host ports and initializes the PC16550A Displays the debugger s copyright message Displays any hardware initialization errors that may have occurred 5 9 Using PPCBug 23 24 25 26 27 28 29 30 31 32 33 34 Checksums the debugger object and displays a warning message if the checksum failed to verify Displays the amount of local read write memory found Verifies the configuration data that is resident in EEPROM and displays a warning message if the verification failed Calculates and displays the MPU clock speed verifies that the MPU clock speed matches the configuration data and di
58. J o0ooro Glossary GL 14
59. Macro Listing NOMAL Disable Macro Listing MAR Load Macros MAW Save Macros MD MDS Memory Display MENU System Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot See Note NBH Network Boot Operating System Halt See Note NBO Network Boot Operating System See Note NIOC Network I O Control See Note NIOP Network I O Physical See Note NIOT Network I O Teach Configuration See Note NPING Network Ping See Note Table 5 2 Debugger Commands Continued PPCBug Debug Command Set Command Command Mnemonic Title OF Offset Registers Display Modify PA Printer Attach NOPA Printer Detach PBOOT Bootstrap Operating System See Note PF Port Format NOPF Port Detach PFLASH Program Flash Memory PS Put RTC into Power Save Mode See Note RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Remote RESET Cold Warm Reset RL Read Loop RM Register Modify RS Register Set SD Switch Directories SET Set Time and Date See Note SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display Search T Trace TA Terminal Attach TIME Display Time and Date See Note TM Transparent Mode TT Trace to Temporary Breakpoint VE Verify S Records Against Memory VER Revision Version Display WL Write Loop Note Commands for Global Environment I O networking PB
60. NO Seconds xx The default is set to the slowest speed found on the available banks in the DRAM memory used on the board which varies depending on the speed of the DRAM memory ROM First Access Length 0 31 x The number of clock cycles used in accessing the ROM This is programmed into the MPC105 ROMFAL field Memory Control Configuration Register 8 bits 23 27 Refer to Chapter 3 for appropriate values The default ROMFAL value varies according to the bus clock speed for the system The allowable range is from 0 to 1F ROM Next Access Length 0 15 x The waitstates in access time for nibble or burst mode accesses to bursting ROMs This is programmed into the MPC105 ROMNAL field Memory Control Configuration Register 8 bits 28 31 Refer to Chapter 3 for appropriate values The default ROMNAL value varies according to the bus clock speed for the system The allowable range is from 0 to F 6 9 Advanced Debugger Topics DRAM Parity Enable On Detection Always Never O A N O O Enable DRAM parity on detection of a parity error A Enable DRAM parity always N Enable DRAM parity never L2Cache Parity Enable On Detection Always Never O A N 0 O Enable L2 Cache parity on detection of a parity error A Enable L2 Cache parity always N Enable L2 Cache parity never PCI Interrupts Route Control Registers PIRQ0 1 2 3 XXXXXXXX This parameter initializes the PIRQx PCI Interru
61. O LM1 LMO 68 FAIL IRQ FAIL BERR IRQ IRQ IRQ IRQ IACK IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN 6C IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 70 CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR 74 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 78 AC FAIL ABORT SYS FAIL MST WP ERROR IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IACK DMA SIG3 SIG 2 7C IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 80 SW7 SW6 SW5 SW4 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 4 SPARE VME IRQ 7 VME IRQ 6 VME IRQ 5 8 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL T VECTOR BASE VECTOR BASE ina Pu d ABORT GPIOEN REGISTER 0 REGISTER 1 EN LEVEL LEVEL LEVEL 8C This sheet continues on facing page 4 12 Programming the PowerBase RS ERES RC ECRIRE RECURSUS VME LOCAL WD ACCESS BUS TIME OUT PRESCALER TIMER TIMER SELECT CLOCK ADJUST COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW VES ee SEN OVERFLOW Ge EN EN COUNTER 2 5 2 COUNTER 1 i i SCALER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sw swe sws sw4 SW3 swe SW SWO SPARE VME VME VME VME VME VME VME IRQ RQ RQ RQ IRQ IRQ IRQ IRA IRQ7 IRQ6 IRQS IRQ
62. OOT and RTC are not applicable to PowerBase Using PPCBug Advanced Debugger Topics Modifying Parameters in EEPROM You can use the factory installed debug monitor PPCBug to modify certain parameters contained in the PowerBase board s EEPROM a The Board Information Block in EEPROM contains various elements concerning operating parameters of the hardware Use the PPCBug command CNFG to change those parameters a Use the PPCBug command ENV to change configurable PPCBug parameters in EEPROM The CNFG and ENV commands are both described in the PPCBug Firmware Package User s Manual Refer to that manual for general information about their use and capabilities The following paragraphs present additional information about CNFG and ENV that is specific to the PPCBug debugger along with the parameters that can be configured with the ENV command CNFG Configure Board Information Block Use this command to display and configure the Board Information Block which is resident within the EEPROM The Board Information Block contains various elements detailing specific operational parameters of the PowerBase board The board structure for the PowerBase board is as shown in the following typical example 6 1 Advanced Debugger Topics Board PWA Serial Number 1234567 x Board Identifier POWERBASE 5 Artwork PWA Identifier 01 w3135F06A Ld PU Clock Speed 067 Bus Clock Speed 067 Ethernet Address
63. Optional PROM 1 15 mezzanine if desired NOTE Mezzanine power must be off Program the MVME130x Configuring the Hardware 17 module as needed for your Programming the PowerBase 4 1 applications You may also wish to obtain the PowerBase Embedded Controller Programmer s Reference Guide listed in the table Motorola Computer Group Documents in Appendix A Ordering Related Documentation 1 6 Preparing and Installing the PowerBase Unpacking the Hardware Ak Caution Note Ifthe shipping carton is damaged upon receipt request that the carrier s agent be present during the unpacking and inspection of the equipment Unpack the equipment from the shipping carton Refer to the packing list and verify that all items are present Save the packing material for storing and reshipping of equipment Avoid touching areas of integrated circuitry static discharge can damage these circuits Configuring the Hardware To produce the desired configuration and ensure proper operation of the PowerBase board you may need to carry out certain modifications before and after installing the module The MVME130x provides software control over most options by setting bits in control registers after installing the MVME130x in a system you can modify its configuration The MVME130x control registers are described in Chapter 4 with additional information in the PowerBase Embedded Controller Programmer s Reference Guide
64. PowerBase Embedded Controller Installation and Use VMEPBA IH1 Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes No part of this material may be reproduced or copied in any tangible medium or stored in a retrieval system or transmitted in any form or by any means radio electronic mechanical photocopying recording or facsimile or otherwise without the prior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph c 1 ii of th
65. RD VWRITE VBR2 VAMS5 GND VBR3 VA23 VDTACK VAMO VA22 GND VAM1 VA21 VAS VAM2 VA20 GND VAM3 VA19 VIACK VIACKIN GND VSERCLK VA18 VIACKOUT VSERDAT VAM4 GND VA7 VIRQ7 VA6 VIRQ6 VA5 VIRQ5 VA4 VIRQ4 VIRQ3 VIRQ2 VIRQ1 5VSTDBY 5V o oaAanoun Mw Connector Pin Assignments VMEbus Connector P2 Rows A and C of the P2 connector provide power and interface signals to the transition module when one is used Row B of P2 provides power to the PowerBase and the upper eight VMEbus lines as specified by the VMEbus specification Table C 2 VMEbus Connector Pin Assignments P2 1 PMCIO2 45V PMCIO1 1 2 PMCIO4 GND PMCIO3 2 3 PMCIO6 RETRY_ PMCIO5 3 4 PMCIO8 VA24 PMCIO7 4 5 PMCIO10 VA25 PMCIO9 5 6 PMCIO12 VA26 PMCIO 1 1 6 7 PMCIO14 VA27 PMCIO13 7 8 PMCIO16 VA28 PMCIO15 8 PMCIO17 SP MEIS ea PMCIO17F See Note 2 10 PMCIO20 VA30 PMCIO19 10 11 PMCIO22 VA31 PMCIO21 11 12 PMCIO24 GND PMCIO23 12 13 PMCIO26 5V PMCIO25 13 14 PMCIO28 VD16 PMCIO27 14 15 PMCIO30 VD17 PMCIO29 15 16 PMCIO32 VD18 PMCIO31 16 17 PMCIO34 VD19 PMCIO33 17 18 PMCIO36 VD20 PMCIO35 18 19 PMCIO38 VD21 eee 19 PMCIO37F See Note 20 PMCIO40 VD22 PMCIO39 20 21 PMCIO42 VD23 PMCIO41 21 22 PMCIO44 VD24 PMCIO43 22
66. Supported I O Controllers Y N Y Y Access the appropriate system buses e g VMEbus local MPU bus to determine the presence of supported controllers Default N Do not access the VMEbus to determine the presence of supported controllers Auto Initialize of NVRAM Header Enable Y N Y Y Enable auto initialization of NVRAM header Default N Disable auto initialization of NVRAM header Network PReP Boot Mode Enable Y N N Y Enable network PReP boot mode N Disable network PReP boot mode Default Negate VMEbus SYSFAIL Always Y N N Y Negate VMEbus SYSFAIL during board initialization N Negate VMEbus SYSFAIL after successful completion or entrance into PPCBug Default Local SCSI Bus Reset on Debugger Setup Y N N Y Reset the Local SCSI bus on debugger set up N Do not reset the Local SCSI bus on debugger set up Default Local SCSI Bus Negotiations Type A S N A A Asynchronous SCSI bus negotiation S Synchronous SCSI bus negotiation N None 6 4 Modifying Parameters in EEPROM Local SCSI Data Bus Width W N N WwW Wide SCSI 16 bit bus N Narrow SCSI 8 bit bus Default NVRAM Bootlist GEV fw boot path Boot Enable Y N N Y Enable NVRAM Bootlist boot N Disable NVRAM Bootlist boot Default NVRAM Bootlist GEV fw boot path Boot at power up only Y N N Y Run NVRAM Bootlist boot at power up reset only N Run NVRAM Bootlist boot at any
67. TC SBC SCSI SCSI 2 Fast Wide serial port SIM A computer in which the processor s instruction set is limited to constant length instructions that can usually be executed in a single clock cycle Radio Frequency Interference The three separate color signals Red Green and Blue Used with color displays an interface that uses these three color signals as opposed to an interface used with a monochrome display that requires only a single signal Both digital and analog RGB interfaces exist See Reduced Instruction Set Computer RISC Read Only Memory Real Time Clock Single Board Computer Small Computer Systems Interface An industry standard high speed interface primarily used for secondary storage The SCSI 1 implementation provides up to 5 Mbps data transfer An improvement over plain SCSI and includes command queuing Fast SCSI provides 10 Mbps data transfer on an 8 bit bus Wide SCSI provides up to 40 Mbps data transfer on a 16 or 32 bit bus A connector that can exchange data with an I O device one bit at a time It may operate synchronously or asynchronously and may include start bits stop bits and or parity Serial Interface Module GL 10 Glossary SIMM SIO SMP SMT software SRAM SSBLT standard s SVGA Teletext Single Inline Memory Module A small circuit board with RAM chips normally surface mounted that is designed to fit into a standard slot Super I O controller
68. ace is used for Direct Mapped PCI Configuration Space accesses See the PCI Configuration Space Mapping section for more details This memory space is mapped as either onboard PROM Flash space or PROM mezzanine space Onboard PROM Flash memory is disabled when the PROM mezzanine is installed 4 3 Memory Maps 5 The EEPROM is mapped in this area See the ISA PCI I O Space Mapping section for more details 6 A read of any byte within this 16 byte field BFFFFFFO through BFFFFFFF causes a PCI IACK cycle The data read is the IACK vector Direct Mapped PCI Configuration Space Table 4 2 shows the mapping of the direct mapped PCI configuration space on the PowerBase Table 4 2 PCI Configuration Space Map P PCI Configuration rocessor Address IDSEL Space Address Definition Start End Start End 80800000 808007FF 00800000 008007FF Reserved All 80800800 808008FF 100800800 008008FF IBC Configuration Registers 80800900 80801FFF 00800900 00801FFF Reserved A13 80802000 808020FF 00802000 008020FF VME2PCI Configuration Registers 80802100 8080FFFF 00802100 0080FFFF Reserved A16 80810000 808100FF 00810000 008100FF PMC Slot 1 Configuration Registers 80810100 8081FFFF 00810100 0081FFFF Reserved A17 80820000 808200FF 00820000 008200FF PMC Slot 2 Configuration Registers 80820100 80FFFFFF 00820100 OOFFFFFF Reserved Notes 1 Accesses to Rese
69. ach bus domain has its own view of the memory map The following sections describe the PowerBase memory organization from the following three points of view a The mapping of all resources as viewed by the processor MPU bus memory map 4 The mapping of onboard resources as viewed by PCI local bus masters PCI bus memory map 4 The mapping of onboard resources as viewed by VMEbus masters VMEbus memory map Additional more detailed memory maps can be found in the PowerBase Embedded Controller Programmer s Reference Guide 4 1 Memory Maps MPU Bus Memory Map The MPU bus memory map is split into different address spaces by the Transfer Type TT signals The local resources respond to the normal access and interrupt acknowledge codes Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables The normal address range is defined by the TT signals on the MPU bus For the MVME130x transfer types 0 1 and 2 define the normal address range Table 4 1 defines the entire map 00000000 to FFFFFFFF Many areas of the map are user programmable and suggested uses are shown in the table The cache inhibit function is programmable in the PowerPC 603 microprocessor MMU The onboard I O space must be marked cache inhibit and serialized in its page table Table 4 2 focuses on the map for the local I O devices accessible through the directly mapped PCI Configuratio
70. age User s Manual then a lt CR gt lt LF gt sequence is issued along with another prompt CTRL H backspace Moved the cursor back one position The character at the new cursor position is erased If the hardcopy option is selected a character is typed along with the deleted character DEL delete or rubout key Performs the same function as CTRL H CTRL D redisplay Redisplay the entire command line as entered so far is on the following line CTRL A repeat Repeat the previous line This happens only at the command line The last line entered is redisplayed but not executed The cursor is positioned at the end of the line You may enter the line as is or you can add more characters to it You can edit the line by backspacing and typing over old characters The XON and XOFF characters in effect for the terminal port may be entered to control the output from any PPCBug command if the XON XOFF protocol is enabled default The characters listed are initialized by PPCBug but you may change them with the PF command CTRL S wait Halt console output XON CTRL Q resume Resume console output XOFF PPCBug Debug Command Set PPCBug Debug Command Set The PPCBug debugging commands are summarized in the following table Arguments and options for the commands will be displayed when you use the HE help command All command details are explained in the PPCBug Firmware Package User s Manual Table 5 2 Debugge
71. and the general purpose I O port The 82378ZB device hereafter referred to as the IBC provides the following features a PCI bus arbitration for MPC105 VME2PCI ASIC and the two PMC slots Functional Description a ISA bus arbitration a ISA interrupt mapping for four PCI interrupts a Functionality of two 82C59 interrupt controllers to support 14 ISA interrupts a Edge level control for ISA interrupts a One 16 bit timer a Three interval counters timers 82C54 functionality AD11 is routed to the IDSEL pin on the IBC device therefore the base address of the configuration space for the IBC is at 00800800 in the PCI configuration area PC16550 UART Timers The PowerBase board uses a PC16550 Universal Asynchronous Receiver Transmitter UART to provide the asynchronous debug port TTL level signals for the port are routed through appropriate EIA 232 D drivers and receivers to an RJ45 connector on the front panel The external signals are ESD protected Timers and counters on the PowerBase board are provided by the IBC and the VMEchip2 Interval Timers 16 Bit Timers The IBC has three built in counters that are equivalent to those found in an 82C54 programmable interval timer These counters are grouped into one timer unit Timer 1 in the IBC These counters use the OSC clock input as their clock source The PowerBase drives the OSC pin with a 14 31818MHz clock source There is one 16 bit timer provided by the
72. ansition board with which it Functional Description communicates On the PowerBase board the four pins that are used to provide power to the MVME762 transition module have polyswitches in series for overcurrent protection factory configuration A build option for use with other transition boards can provide direct connections with no polyswitches Note Ifthe pins are used for high speed signals you should evaluate the signal integrity If power fault protection is desired for transition boards other than the MVME762 it must be provided by the corresponding PMC module since it directly provides power to the transition module For the purposes of calculating how many power pins are required for a transition board the following trace widths are present on PowerBase for the PMC1 I O pins Header Pin Trace Width 10 50 mil 17 75 mil 28 50 mil 37 20 mil J14 46 20 mil 55 60 mil 64 50 mil All others 10 mil PowerBase Components Programming the PowerBase Introduction This chapter provides basic information useful in programming your PowerBase This includes a description of memory maps control and status registers PCI arbitration interrupt handling sources of reset and big little endian issues For complete programming information refer to the PowerBase Embedded Controller Programmer s Reference Guide Memory Maps There are multiple buses on the PowerBase and e
73. are readable header J2 These jumpers determine a board select number Each board select number has been assigned a specific group and board address in VMEbus short I O space as shown in Table 1 2 The specific assigned address is written into the LCSR and EEPROM unless all five jumpers have been removed board select number 31 If all five jumpers are removed then the values previously stored in EEPROM for group and board addresses are programmed in the LCSR Values may be stored in the EEPROM by setting the board select number with jumpers on J2 or with the debugger ENV command In this way any jumper setting a board select number other than 31 will over ride and set the GCSR address yet any VMEbus short I O address may be set using the ENV command and the board select set to 31 Preparing and Installing the PowerBase Table 1 2 GCSR Addresses Seed Foren om Notes Number Setting 0 FFFFD800 XXXIIIII 1 2 1 FFFFD810 XXX IIII 1 2 FFFFD820 XXXI III 1 3 FFFFD830 XXX 11I 1 4 FFFFD840 XXXII II 1 5 FFFFD850 XXX I 1I 1 6 FFFFD860 XXXI II 1 7 FFFFD870 XXX 11I 1 8 FFFFD880 XXXIII I 1 9 FFFFD890 XXX II I 1 10 FFFFD8A0 XXXI I I 1 11 FFFFD8BO XXX 1 I 1 12 FFFFD8CO XXXII I 1 13 FFFFD8DO XXX I I 1 14 FFFFD8E0 XXXI I 1 Note FFFFD8FO is not used 15 FFFFD900 XXX 1I 1 16 FFFFD910 XXXIIII 1 17 FFFFD920 XXX III 1 18 FFFFD930 XXXI II 1 Note SFFFF
74. ase The front panel is pictured in Figure 1 3 in Chapter 1 Switches There are two switches ABORT and RESET and four LED light emitting diode status indicators CPU FAIL PMC1 PMC2 located on the MVME130x front panel ABORT S1 When activated by software the ABORT switch can generate an interrupt signal from the base board to the processor at a user programmable level The interrupt is normally used to abort program execution and return control to the PPCBug debugger firmware located in the PowerBase Flash or PROM memory The interrupt signal reaches the processor module via ISA bus interrupt line IRQ8 The signal status is also available from the general purpose I O port refer to Chapter 4 This also allows software after an IRO8 interrupt to poll the ABORT switch and verify that it has been pressed The interrupter connected to the ABORT switch is an edge sensitive circuit filtered to remove switch bounce RESET S2 The RESET switch resets all onboard devices and causes HRESET to be asserted in the MPC603 it also drives a SYSRESET signal if the PowerBase is the system controller The VMEchip2 includes both a global and a local reset driver When the VMEchip2 operates as the VMEbus system controller the reset 2 1 Status Indicators DS1 DS4 driver provides a global system reset by asserting the VMEbus signal SYSRESET A SYSRESET signal may be generated by the RESET switch a power up reset
75. carries video picture information for color brightness and synchronizing signals for both horizontal and vertical scans Sometimes referred to as Baseband Video cpi characters per inch cpl characters per line CPU Central Processing Unit The master computer unit in a system DCE Data Circuit terminating Equipment DLL Dynamic Link Library A set of functions that are linked to the referencing program at the time it is loaded into memory DMA Direct Memory Access A method by which a device may read or write to memory directly without processor intervention DMA is typically used by block I O devices DOS Disk Operating System dpi dots per inch DRAM Dynamic Random Access Memory A memory technology that is characterized by extremely high density low power and low cost It must be more or less continuously refreshed to avoid loss of data DTE Data Terminal Equipment ECC Error Correction Code ECP Extended Capability Port GL 3 J oooro 2 o0o00r o Glossary EEPROM EISA bus EPP EPROM ESCC ESD Ethernet FDC FDDI FIFO firmware frame Electrically Erasable Programmable Read Only Memory A memory storage device that can be written repeatedly with no special erasure fixture EEPROMs do not lose their contents when they are powered down Extended Industry Standard Architecture bus IBM An architectural system using a 32 bit bus that allows data to be transferred between per
76. characteristics for the address space defined with this master address decoder Local Bus Slave Attribute Register Default 00 Master Enable 3 Y N N Y Enable the Master Address Decoder 3 N Disable the Master Address Decoder 3 Default Master Starting Address 3 00000000 The base address of the VMEbus resource that is accessible from the local bus Master Ending Address 3 00000000 The ending address of the VMEbus resource that is accessible from the local bus Modifying Parameters in EEPROM Master Control 43 00 The access characteristics for the address space defined with this master address decoder Local Bus Slave Attribute Register Master Enable 4 Y N N Y Enable the Master Address Decoder 4 N Disable the Master Address Decoder 4 Default Master Starting Address 4 00000000 The base address of the VMEbus resource that is accessible from the local bus Master Ending Address 4 00000000 The ending address of the VMEbus resource that is accessible from the local bus Master Address Translation Address 4 00000000 The base address of VMEbus resource that is associated with the starting and ending address selection from the previous questions This allows the VMEbus address and the local address to be different Master Address Translation Select 4 00000000 This register defines which bits of the address are significant A logical 1 indicates
77. creased airflow It is important to note that there are several factors in addition to the rated CFM of the air mover which determine the actual volume and speed of air flowing over a module FCC Compliance The PowerBase was tested in an FCC compliant chassis and meets the requirements for Class A equipment FCC compliance was achieved under the following conditions B 3 Regulatory Compliance a Shielded cables on all external I O ports a Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel 4 Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground a Front panel screws properly tightened For minimum RF emissions it is essential that the conditions above be implemented Failure to do so could compromise the FCC compliance of the equipment containing the module Regulatory Compliance The PowerBase is a board level product and meant to be used in standard VME applications As such it is the responsibiility of the OEM to meet the regulatory guidelines as determined by its application All external I O connectors are shielded to aid in meeting EMI emiassions standards PowerBase is tested in an MCG chassis for EMI evaluation B 4 Connector Pin Assignments Introduction This appendix summarizes the pin assignments for the following groups of interconnect signals for the PowerBase board
78. d for board selection in WAN 9 and 10 Bit 4 SRH4 Used for board selection in WAN 11 and 12 Bit 5 SRH5 Used for board selection in WAN 13and14 Bit 6 SRH6 Used for board selection in WAN 15and16 Bit 7 SRH7 Used for board selection in WAN 4 19 Control and Status Registers Board Configuration Register The Board Configuration Register is an 8 bit register providing the configuration information about the PowerBase Board Configuration Register 0802 hex BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SDO FIELD N A SCCP PMC2P PMCIP VMEP GFXP_ LANP_ SCSIP_ OPER R R R R R R R R RESE 1 1 N A N A 0 1 1 1 T Not Used Always set Formerly known as Transition Module Present The PowerBase boards have no way of knowing if a transition module is present SCCP _ Always set Z85230 ESCC Present If set there is no on board sync serial support ESCC not present If cleared there is on board support for sync serial interface via Z85230 ESCC Note that this pertains to an ESCC mounted on the base board not on a PMC PMCIP PMC1 Present If set there is no PCI Mezzanine Card installed in PMC Slot 1 If cleared PMC slot 1 contains a PMC PMC2P _ PMC2 Present If set there is no PCI Mezzanine Card installed in PMC Slot 2 If cleared PMC slot 2 contains a PMC Note A double width PMC may use either PMC1P_ or PMC2P as its presence detect bit VMEP_ Always
79. d or DC power lines from the system Installing the Hardware aS Caution A Warning aS Caution Inserting or removing modules with power applied may result in damage to module components Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting b Remove chassis or system cover s as necessary for access to the VMEmodules 3 Remove the filler panel from the card slot where you are going to install the PowerBase board Ifyou intend to use the MVME130x as system controller it must occupy the leftmost card slot slot 1 The system controller must be in slot 1 to correctly initiate the bus grant daisy chain and to ensure proper operation of the IACK daisy chain driver Ifyou do not intend to use the MVME130x as system controller it can occupy any unused card slot Avoid touching areas of integrated circuitry static discharge can damage these circuits 4 Slide the MVME130x into the selected card slot Be sure the module is seated properly in the P1 and P2 connectors on the backplane Do not damage or bend connector pins 5 Secure the MVME130x in the chassis with the screws provided making good contact with the transverse mounting rails to minimize RF emissions Note Some VME backplanes e g those used in Motorola Modular Chassis systems have an auto jumpering feature for automatic propagation of the IACK and BG
80. ddress Decoder 2 VME2PCI Slave Starting Address 2 20000000 The starting address of the second PCI Memory Space for the VME2PCT s slave interface PCI memory accesses within the range of the starting and ending addresses are passed on to the VMEchip2 as adjusted by the slave address offset Only the upper 16 bits of this address are significant VME2PCI Slave Ending Address 2 2FFFFFFF The ending address of the second PCI Memory Space for the VME2PCT s slave interface Only the upper 16 bits of this address are significant VME2PCI Slave Address Offset 2 D0000000 The offset used to translate the most significant 16 bits of the address to be presented to the VMEchip2 from the PCI bus The address presented is equal to the sum of PCI address bits 31 16 and the offset bits 31 16 Bits 15 00 will be zero Configuring the Slave Address Decoders The following parameters set up the two slave address decoders in the VMEchip2 The decoders are used to allow another VMEbus master to access a local resource of the PowerBase Refer to the VMEchip2 ASICs information in Chapter 4 and the PowerBase Embedded Controller Programmer s Reference Guide for information on these parameters Advanced Debugger Topics Slave Enable 1 Y N N Y Enable the Slave Address Decoder 1 N Disable the Slave Address Decoder 1 Default Slave Starting Address 1 00000000 The base add
81. e IBM version of UNIX The main overall design in which each individual hardware component of the computer system is interrelated The most common uses of this term are 8 bit 16 bit or 32 bit architectural design systems American Standard Code for Information Interchange a 7 bit code used to encode alphanumeric information In the IBM compatible world this is expanded to 8 bits to encode a total of 256 alphanumeric and control characters Application Specific Integrated Circuit Attachment Unit Interface Battery Backed up Random Access Memory Having big endian and little endian byte ordering capability A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the bytes are ordered left to right 0 1 2 3 with 0 being the most significant byte GL 1 2 o0o00r o Glossary BIOS BitBLT BLT board bpi bps bus cache CAS CD CD ROM CFM Basic Input Output System The built in program that controls the basic functions of communications between the processor and the I O devices peripherals Also referred to as ROM BIOS Bit Boundary BLock Transfer A type of graphics drawing routine that moves a rectangle of data from one area of display memory to another The data need not have any particular alignment BLock Transfer The term more commonly used to refer to a PCB printed circuit board Basically a flat
82. e Rights in Technical Data and Computer Software clause at DFARS 252 227 7013 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Preface The PowerBase Embedded Controller Installation and Use manual provides information you will need to install and use your PowerBase module one of the MVME130x family of PCI Mezzanine Card PMC carrier boards MVMEI301 8MB DRAM no parity MVME1302 8MB DRAM parity MVME1305 16MB DRAM no parity MVME1306 16MB DRAM parity The manual includes hardware preparation and installation instructions information about using the front panel a functional description information about programming the board using the PPCBug debugging firmware and advanced debugger topics Additional manuals you may wish to obtain are listed in Appendix A Ordering Related Documentation Other appendices provide the PowerBase specifications connector pin assignments and a glossary of terms This manual is intended for anyone who wants to design OEM systems supply additional capability to an existing compatible system or work in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed The PowerBase boards may be populated with a number of plug together components including PMCs PROM mezzanine transition board and Serial Interface Modules SIMs Combinations of PowerBase boards and specific components are collectively referred to as PowerCom The i
83. e Specifications Continued Characteristics Specifications Altitude operating 5000 meters 16 405 feet Physical dimensions Height Double high VME board 9 2 in 233 mm base board only Front panel width 0 8 in 19 8 mm Depth 6 3 in 160 mm PCI Mezzanine Card Address Data A32 D32 PMC PMC slots Bus Clock Up to 33MHz Signaling 5V Power 7 5 watts maximum per slot see Note Module types Basic single wide front panel or P21 O 74 0 mm x 149 0 mm Basic double wide front panel or P2 I O 149 0 mm x 149 0 mm PMCI O Slot 1 Front panel and or VMEbus P21 O Slot 2 Front panel I O Peripheral Computer PCI bridge MPC105 Interface PCI PClbus 32 bit 33MHz VMEbus DTB master A32 D32 D08 D64 BLK ANSI VITA 1 1994 DTB slave A24 A32 D08 D64 BLK UAT YMO Arbiter Round Robin or Priority E IEEE S1 Interrupt handler IRQ 1 7 Interrupt controller Any one of seven System controller Via jumper or auto detect Location monitor Four LMA32 Note The power requirement listed for the MVME130x does not include the power requirements for the PMC slots The PMC specification allows for 7 5 watts per PMC slot The 15 watts total can be drawn from any combination of the four voltage sources provided by the PowerBase 3 3V 5V 12V and 12V B 2 PowerBase Specifications Cooling Requirements The Motorola PowerBase Embedded Controller
84. e sen See I Front Panel RJ45 VMEbus i or VMEbus P2 Pron Eang Debug Port P1 and P2 i I O l i External I O Figure 1 2 PowerBase Board Block Diagram 1 3 Equipment Required PowerBase interfaces to the VMEbus via the P1 and P2 connectors It also draws 5V 12V and 12V power from the VMEbus backplane through these two connectors The 3 3V power used for the processor and PCI bridge chip and possibly for the PMC mezzanine is derived onboard from the 5V power Support for two IEEE P1386 1 PCI mezzanine cards is provided via five 64 pin SMT connectors Front panel openings are provided on the PowerBase board for the two PMC slots In addition there are 64 pins of I O from PMC slot 1 that are routed to P2 The two PMC slots may contain two single width PMCs or one double width PMC Equipment Required The following equipment is required to utilize a PowerBase board a MVME130x base board PowerBase a VMEsystem enclosure The following equipment is optional a PROM mezzanine module 1 4 Preparing and Installing the PowerBase Overview of Start Up Procedures The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read this entire chapter and read all Caution and Warning notes before beginning Table 1 1 Start Up Overview Performing Diagnostic Tests in Chapter
85. eau Central de la Commission Electrotechnique Internationale 3 rue de Varemb Geneva Switzerland IEEE Common Mezzanine Card Specification CMC P1386 Draft 2 0 Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 Related Specifications Table A 3 Related Specifications Continued Document Title and Source IEEE PCI Mezzanine Card Specification PMC Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 Bidirectional Parallel Port Interface Specification Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 Publication Number P1386 1 Draft 2 0 IEEE Standard 1284 Peripheral Component Interconnect PCI Local Bus Specification Revision 2 0 PCI Special Interest Group P O Box 14070 Portland Oregon 97214 4070 Marketing Help Line Telephone 503 696 6111 Document Specification Ordering Telephone 1 800 433 5177or 503 797 4207 FAX 503 234 6762 PowerPC Reference Platform PRP Specification Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Power Personal Systems Architecture 11400 Burnet Rd Austin
86. ed they are programmed externally before they are installed on the board The onboard monitor debugger PPCBug resides in the Flash devices PPCBug provides a A boot loader and extensive on board diagnostics a A single line assembler disassembler a A remote boot capability Each bank of PROM Flash is 8 bits wide and is controlled by the MPC105 The MPC105 performs byte alignment for write accesses and also packs bytes for 16 bit 32 bit and 64 bit read accesses to the PROM Flash area The PROM Flash must be accessed in the MPC105 non burst mode For PROM Flash speed of 150ns software should program ROMFAL first access length and ROMNAL last access length in the MPC105 device with the following values 3 5 PowerBase Components J Caution Table 3 2 Minimum ROMFAL and ROMNAL Values at 150ns Processor External Minimum Minimum Bus Speed ROMFAL ROMNAL 66 66MHz 10 0 Note The onboard PROM Flash memory is disabled when the PROM mezzanine is installed because the MPC105 cannot support both memory interfaces simultaneously A status bit is available from the general purpose I O port to allow the firmware to know whether it is operating from on board PROM Flash or from the PROM mezzanine Since Flash and PROM devices have different pinouts the MVME130x must be hard wired with zero ohm resistors for Flash or PROM memory configuration The factory configuration is for Flash PowerBase s
87. efer to the user s manual for the particular PMC PMC1 PMC Slot 1 The opening labeled PMC1 on the front panel provides I O access to a PMC when it is connected to the 64 pin SMT connectors J11 and J12 on the PowerBase board When a PMC is connected to the 64 pin SMT connectors J11 J12 and J14 on the PowerBase board 64 pins of I O from PMC slot 1 are routed to P2 the 96 pin VMEbus connector on the back of the PowerBase board Both P2 and the front panel are then accessible for I O PMC2 PMC Slot 2 The opening labeled PMC2 on the PowerBase front panel provides I O access to a PMC when it is connected to 64 pin SMT connectors J21 and J22 on the PowerBase board Double Wide PMCs A double wide 8 port PMC connected to J11 J12 J21 and J22 would allow front panel I O access through both PMC1 and PMC2 and optionally the P2 connector if J14 is also used 2 4 Functional Description Introduction This chapter describes the PowerBase embedded controller on a block diagram level The General Description provides an overview of the MVME130x followed by a detailed description of several blocks of circuitry Figure 3 1 shows a block diagram of the overall board architecture Detailed descriptions of other MVME130x blocks including programmable registers in the ASICs and peripheral chips can be found in the PowerBase Embedded Controller Programmer s Reference Guide Refer to it for a functional description of the MVME130
88. efore starting Auto Boot During the delay a user may exit to the debugger or diagnostics prompt by pressing the BREAK key The value may be from 0 255 Auto Boot Default String NULL for an empty string A string filename which is passed on to the code being booted The maximum length of this string is 16 characters 6 6 Modifying Parameters in EEPROM ROM Boot Enable Y N N Y Enable ROM Boot N Disable ROM Boot Default ROM Boot at power up only Y N Y Y Run ROM Boot at power up only Default N Run ROM Boot at any reset ROM Boot Enable search of VMEbus Y N N Y Search the VMEbus address space for a ROM Boot module in addition to the normal areas of memory N VMEbus address space will not be accessed by ROM Boot ROM Boot Abort Delay 5 The time in seconds that the start up sequence waits before starting ROM Boot During the delay a user may exit to the debugger or diagnostics prompt by pressing the BREAK key The value may be from 0 255 ROM Boot Direct Starting Address FFF00000 The first location tested when PPCBug searches for a ROM Boot module ROM Boot Direct Ending Address FFFFFFEC The last location tested when PPCBug searches for a ROM Boot module 6 7 Advanced Debugger Topics Network Auto Boot Enable Y N N Y Enable Network Auto Boot N Disable Network Auto Boot Default Network Auto Boot at power up only Y N Y Y Run Network Auto Boot at p
89. ensitive mode Note that more than one PCI interrupt can be routed to the same ISA IRQ line Figure 4 5 shows the IBC interrupt structure Additional details on interrupt assignments can be found in the PowerBase Embedded Controller Programmer s Reference Guide 4 27 Programming Considerations PIRQO PIRQ1 PIRQ2 PIRQ3 PIRQ ROUTE CONTROL REGISTER PIRQ ROUTE CONTROL REGISTER PIRQ ROUTE CONTROL REGISTER PIRQ ROUTE CONTROL REGISTER TIMER1 COUNTERO INTR CONTROLLER 1 INT1 IRQx pun oe IRQ1 IRQ3 IRQ4 IRQx IRQ5 j IRQ6 H v IRQ7 M IRQx IRQ8 IRQ9 IRQx IRQ10 IRQ11 n IRQ12 IRQ13 IRQ14 IRQ15 CONTROLLER 2 INT2 Figure 4 5 IBC Interrupt Handler Block Diagram 11189 00 9411 4 28 Programming the PowerBase Handling VMEchip2 Interrupts VME chip2 interrupts consist of interrupts from the VMEbus IRQ lines and from the VMEchip2 internal resources i e DMA and Timers You can program the VMEchip2 interrupt control registers as though the system were MC68040 based i e with interrupt priority levels from 1 through 7 When an interrupt is pending the VME chip2 asserts three encoded interrupt request lines IPL2 IPLO to the VME2PCI device An interrupt is then issued by the VME2PCI device to the processor through the IBC After learning from
90. ert the PMC s front panel bezel through the selected PMC slot in the PowerBase s front panel and gently seat the PMC onto the PowerBase ensuring that the keying pin and connectors are properly aligned Refer to Figure 1 3 6 Turn the PowerBase over and using the four provided screws fasten the PMC to the MVME130x from the underside 7 Reinstall the MVME130x board in the chassis according to the instructions given in the Installing the PowerBase section of this chapter Installation Considerations The PowerBase board draws power from the VMEbus backplane connectors P1 and P2 P2 is also used for the upper 16 bits of data in 32 bit transfers and for the upper 8 address lines in extended addressing mode The MVME130x may not function properly without its main board connected to VMEbus backplane connectors P1 and P2 Whether the PowerBase operates as a VMEbus master or as a VMEbus slave it is configured for 32 bits of address and 32 bits of data A32 D32 However it handles A16 or A24 devices in the Preparing and Installing the PowerBase address ranges indicated in Chapter 4 D8 and or D16 devices in the system must be handled by the PowerPC processor software Refer to the memory maps in Chapter 4 The MVME130x contains shared onboard DRAM whose base address is software selectable Both the onboard processor and off board VMEbus devices see this local DRAM at base physical address 00000000 as programmed by the PPCBu
91. ess A binary address issued by a CPU that indirectly refers to the location of information in primary memory such as main memory When data is copied from disk to main memory the physical address is changed to the virtual address GL 12 Glossary VL bus VMEchip2 VME2PCI volatile memory VRAM Windows NT XGA Y Signal See VESA Local bus VL bus MCG second generation VMEbus interface ASIC Motorola MCG ASIC that interfaces between the PCI bus and the VME chip2 device A memory in which the data content is lost when the power supply is disconnected Video Dynamic Random Access Memory Memory chips with two ports one used for random accesses and the other capable of serial accesses Once the serial port has been initialized with a transfer cycle it can operate independently of the random port This frees the random port for CPU accesses The result of adding the serial port is a significantly reduced amount of interference from screen refresh VRAMs cost more per bit than DRAMs The trademark representing Windows New Technology a computer operating system developed by the Microsoft Corporation EXtended Graphics Array An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Luminance Parameter that determines the brightness but not the color of each spot pixel on a CRT screen in color or B W systems GL 13
92. ess and the local address to be different Slave Address Translation Select 2 00000000 A mask that defines which bits of the address are significant A 1 indicates a significant bit A 0 indicates a nonsignificant bit Slave Control 2 0000 The access restriction for the address space defined with this slave address decoder VMEbus Slave Write Post and Snoop Control Register and VMEbus Slave Address Modifier Select Register Master Enable 1 Y N Y Y Enable the Master Address Decoder 1 N Disable the Master Address Decoder 1 Master Starting Address 1 00000000 The base address of the VMEbus resource that is accessible from the local bus Default is the end of calculated local memory Master Ending Address 1 1FFFFFFF The ending address of the VMEbus resource that is accessible from the local bus Master Control 1 OD The access characteristics for the address space defined with this master address decoder Local Bus Slave Attribute Register Default 0D Advanced Debugger Topics Master Enable 2 Y N N Y Enable the Master Address Decoder 2 N Disable the Master Address Decoder 2 Default Master Starting Address 2 00000000 The base address of the VMEbus resource that is accessible from the local bus Master Ending Address 2 00000000 The ending address of the VMEbus resource that is accessible from the local bus Master Control 2 00 The access
93. esses are limited to 1MB 5 digits regardless of the range of the closest offset register The PORT argument is the logical number of the port to be used to input or output Valid port numbers which may be used for these commands are as follows 0 or 00 Terminal port 0 console port is used for interactive user input and output the default This port number usually refers to the serial port labelled either COMI or SERI on the system board However this port number may also be used for the graphics adapter device 1 or 01 Terminal port 10 host port is the default for downloading uploading concurrent mode and transparent modes This port is labeled either COM2 or SER2 on the system board Command Options Many commands have one or more options defined in the command descriptions found in the PPCBug Firmware Package User s Manual You will also see the options for each command when you type HE to display the help menu Precede an option or a string of options with a semi colon If no option is entered the command s default option conditions are used Using PPCBug Terminal Input and Output Control Characters You may use the following control codes for limited editing while entering commands at the ppci Bug gt prompt CTRL X cancel line Move the cursor to the beginning of the line If the terminal port is configured with the hardcopy or TTY option refer to the PF command in the PPCBug Firmware Pack
94. et implementation in which the physical medium is a double shielded 50 ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters also referred to as thicknet thin Ethernet 10Base2 An Ethernet implementation in which the physical medium is a single shielded 50 ohm RG58A U coaxial cable capable of carrying data at 10 Mbps for a length of 185 meters also referred to as AUI or thinnet twisted pair Ethernet 10BaseT An Ethernet implementation in which the physical medium is an unshielded pair of entwined wires capable of carrying data at 10 Mbps for a maximum distance of 185 meters UART Universal Asynchronous Receiver Transmitter UV UltraViolet UVGA Ultra Video Graphics Array An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Vertical Blanking Interval VBI The time it takes the beam to fly back to the top of the screen in order to retrace the opposite field odd or even VBI is on the order of 20 TV lines Teletext information is transmitted over 4 of these lines lines 14 17 VESA bus Video Electronics Standards Association or VL bus An internal interconnect standard for transferring video information to a computer display system VGA Video Graphics Array IBM The third and most common monitor standard used today It provides up to 256 simultaneous colors and a screen resolution of 640 x 480 pixels virtual addr
95. g endian software e g AIX The PowerPC processor and the VMEbus are inherently big endian while the PCI bus is inherently little endian The following figures illustrate how the MVME130x handles the endian issue in big endian and little endian modes Processor Memory Domain The MPC608 processor can operate in both big endian and little endian mode However it always treats the external processor memory bus as big endian by performing address rearrangement and reordering when running in little endian mode Role of the MPC105 Because the PCI bus is little endian the MPC105 performs byte swapping in both directions from PCI to memory and from the processor to PCI to maintain address invariance while programmed to operate in big endian mode with the processor and the memory subsystem 4 30 PCI Domain Programming the PowerBase Inlittle endian mode the MPC105 reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from PCI In this case no byte swapping is done The PCI bus is inherently little endian and all devices connected directly to PCI will operate in little endian mode regardless of the mode of operation in the processor s domain Role of the VME2PCI Because PCI is little endian and the VMEbus is big endian the VME2PCI performs byte swapping in both directions from PCI to VMEbus and from VMEbus to PCI to maintain address invariance regardless of the m
96. g firmware This may be changed via software to any other base address Refer to the PowerBase Programmer s Reference Guide for more information If the MVME130x tries to access off board resources in a nonexistent location and is not system controller and if the system does not have a global bus time out the MVME130x waits forever for the VMEbus cycle to complete This will cause the system to lock up There is only one situation in which the system might lack this global bus time out when the MVME130x is not the system controller and there is no global bus time out elsewhere in the system Multiple PowerBase boards may be installed in a single VME chassis Each must have a unique GCSR address selected by setting jumpers on its J2 header as described in Preparing the PowerBase In general hardware multiprocessor features are supported Other MPUs on the VMEbus can interrupt disable communicate with and determine the operational status of the processor s One register of the GCSR global control status register set includes four bits that function as location monitors to allow one MVME130x processor to broadcast a signal to any other MVME130x processors All eight registers are accessible from any local processor as well as from the VMEbus Installation Considerations Using the Front Panel Introduction This chapter provides information about the switches status indicators and I O ports on the front panel of the PowerB
97. gned integer representing the value read from the software readable jumper header J2 Refer to the section Preparing the PowerBase in Chapter 1 Using PPCBug Executing Remote Commands through the GCSR Execution of commands issued from a remote processor through the VMEchip2 Global Control and Status Registers GCSR is performed as follows After performing the above initialization PPCBug begins monitoring the GCSR and debugger input port At this point the host or some other remote processor may control execution of PPCBug via the GCSR or you may enter a debugger command on a terminal attached to the debug port The host may invoke the commands listed below by writing to GCSR register s and then setting the SIG1 bit of the GCSR LM SIG control register To execute a command through the GCSR on PowerBase 1 Write the command code in GCSRO 2 If the command requires write information needed to GCSR1 through GCSR5 3 Set SIG1 bit in LM SIG register 4 Allow sufficient time for the command to complete Reading GCSRO will show only the busy bit set bit 07 once the command has been accepted and will be cleared when the command has completed unless the Selftest command was issued and has failed Note that during the VME test portion of selftest an attempt to read the GCSR will be unsuccessful 5 Read GCSR to retrieve any information returned by the command Commands Available Through the GCSR Registers For detail
98. hm resistors on the PROM mezzanine board The Flash devices in such a configuration will not be reprogrammable in circuit however They must be reprogrammed with an external programmer The appropriate Flash device type is AM29F040 150JC or equivalent Functional Description The PROM must be accessed in the MPC105 non burst mode For PROM speed of 150ns software should program ROMFAL and ROMNAL in the MPC105 device with the following values Table 3 6 Minimum ROMFAL and ROMNAL Values at 150ns Processor External Minimum Minimum Bus Speed ROMFAL ROMNAL 66 66MHz 10 0 A status bit is available from the general purpose I O port to allow the firmware to know whether it is operating from on board PROM Flash or from the PROM mezzanine PCI Mezzanine Card PMC Slots PMC1 The PowerBase board supports two PMC slots Five 64 pin connectors are located on the PowerBase board to interface to two 32 bit IEEE P1386 1 PMCs to add any desirable function The PMC slots have the characteristics listed below For detailed programming information refer to the programmer s reference guide and to the user documentation for the PMC modules you intend to use PMC slot 1 supports Mezzanine type PCI Mezzanine Card PMC Mezzanine size Single width and standard depth 75mm x 150mm with front panel PMC connectors J11 J12 and J14 32 Bit PCI with front panel or P2 I O Signalling voltage Vio 5 0V AD16 i
99. ipherals in 32 bit chunks instead of the 16 bit or 8 bit units that most systems use With the transfer of larger bits of information the machine is able to perform much faster than the standard ISA bus system Enhanced Parallel Port Erasable Programmable Read Only Memory A memory storage device that can be written once per erasure cycle and read many times Enhanced Serial Communication Controller Electro Static Discharge Damage A local area network standard that uses radio frequency signals carried by coaxial cables Floppy Disk Controller Fiber Distributed Data Interface A network based on the use of optical fiber cable to transmit data in non return to zero invert on 1s NRZI format at speeds up to 100 Mbps First In First Out A memory that can temporarily hold data so that the sending device can send data faster than the receiving device can accept it The sending and receiving devices typically operate asynchronously The program or specific software instructions that have been more or less permanently burned into an electronic component such as a ROM read only memory or an EPROM erasable programmable read only memory One complete television picture frame consists of 525 horizontal lines with the NTSC system One frame consists of two Fields GL 4 Glossary graphics controller HAL hardware HCT VO IBC IDE IEEE interlaced IQ Signals On EGA and VGA a section of circuitry tha
100. is provided via the System Call Handler This gives a convenient way of doing character input output and many other useful operations so that you do not have to write these routines into the target code Refer to the PPCBug Firmware Package User s Manual for details on the routines available and how to invoke them from within a user program The System Call Handler is accessible through the sc system call instruction with exception vector 00C00 System Call Exception Preserving the Operating Environment This section explains how to avoid contaminating the operating environment of the debugger PPCBug uses certain portions of the system board onboard resources and also off board system memory to contain temporary variables exception vectors etc If you disturb resources upon which PPCBug depends then the debugger may not function reliably or may not function at all If your application enables translation through the Memory Management Unit MMU and utilizes resources of the debugger e g system calls your application must create the necessary translation tables for the debugger to have access to its various resources The debugger honors the enabling of the MMU it does not alter or disable translation Memory Requirements The debugger requires a total of 512K bytes of read write memory The debugger will allocate this memory from the top of memory For example on a system which contains 64 megabytes 04000000 of read wr
101. is specified designed and tested to operate reliably with an incoming air temperature range from 0 to 55 C 32 to 131 F with forced air cooling of the entire assembly base board and modules at a velocity typically achievable by using a 100 CFM axial fan Temperature qualification is performed in a standard Motorola VMEsystem chassis Twenty five watt load boards are inserted in two card slots one on each side adjacent to the board under test to simulate a high power density system configuration An assembly of three axial fans rated at 100 CFM per fan is placed directly under the VME card cage The incoming air temperature is measured between the fan assembly and the card cage where the incoming airstream first encounters the module under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded While the exact amount of airflow required for cooling depends on the ambient air temperature and the type number and location of boards and other heat sources adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module Less airflow is required to cool the module in environments having lower maximum ambients Under more favorable thermal conditions it may be possible to operate the module reliably at higher than 55 C with in
102. ite memory i e DRAM the debugger s memory page will be located at 03F80000 to 03FFFFFF Preserving the Operating Environment This memory space is used by the debugger for program stack I O buffers variables and register files If a user program is loaded e g booted S Records into memory and if this program is utilizing the debugger s programmatic interface i e system calls the program must not modify this allocated memory Whenever the host hardware is reset the following is done a Target IP instruction pointer is initialized to 00004000 i e just above the memory space of the exception vector table a Target pseudo stack pointer is initialized to the starting location of the debugger s read write memory space a Target IP will be set to the appropriate address if a program load operation Note that user programs should handle the stack area properly in that it should not write starting at the initialized location Some compilers and assemblers may write to the stack prior to decrementing the stack This read write memory space that is allocated for the debugger by the debugger may increase in future releases of the debugger To properly compensate for the increased read write memory requirements user programs may utilize the target IP as indicator for the top plus 1 of usable memory Exception Vectors Used by PPCBug The following exception vectors are reserved for use by the debugger
103. izes the clock frequencies supported by the PowerBase 3 3 PowerBase Components RISCwatch CPU Connector MPU Bus MPC603 gt MPU Clock Generator i MPC105 Bridge DRAM 8MB Optional Address and Control DRAM Parity Optional PCI Local Bus 82378ZB ISA Bridge VME2PCI Bridge PMC Slot 2 PMC Slot 1 t VME VMEchip2 Decode Function Buffers M E an EEPROM PC16550 d 1 1 8Kx8 UART Front Panel P2 Connector P1 Connector 11414 00 Figure 3 1 MVME130x Block Diagram 3 4 Functional Description Table 3 1 MPC603 Clock Frequencies Supported by PowerBase MPC603 Internal Processor Speed 66 66MHz MPC105 MPC105 iue MPC603 Internal External MPC105 PCI Bus ema Clock PLL Clock Clock Clock PLL Frequency Bus Speed Frequency Frequency 66 66MHz 1x 66 66MHz 33 33MHz 2x 33 33MHz Flash Devices and Boot ROM The PowerBase has two onboard 32 pin PLCC sockets which support two banks of 512Kx8 PROM or Flash devices that together provide a total of IMB of PROM Flash capacity This memory space is provided for the Boot ROM function The factory configuration is with Flash devices installed Since the devices are socket
104. ler Default 02 256 us VMEbus Access Time Out Code 02 The local bus to VMEbus access time out VATO Default 02 32 ms Entering and Debugging Programs There are various ways to enter a user program into system memory for execution One way is to create the program using the MM Memory Modify command with the DI assembler disassembler option entering the program one source line at a time After each source line is entered it is assembled and the object code is loaded to memory Refer to the PPCBug Firmware Package User s Manual for complete details of the PPCBug Assembler Disassembler Another way is to download an object file from a host system The program must be in S record format refer to the PPCBug Firmware Package User s Manual and may have been assembled or compiled on the host system Alternately the program may have been previously created using the MM command as outlined above and stored to the host using the DU Dump command A communication link must exist between the host system and system board port 1 Refer to Chapter 1 for hardware configuration information The file is downloaded from the host to system board memory by the LO Load command Once the object code has been loaded into memory you can set breakpoints if desired and run the code or trace through it Advanced Debugger Topics Calling System Routines from User Programs Access to various PPCBug routines
105. mory Space for the VME2PCT s slave interface Only the upper 16 bits of this address are significant VME2PCI Slave Address Offset 1 00000000 The offset used to translate the most significant 16 bits of the address to be presented to the VMEchip2 from the PCI bus The address presented is equal to the sum of PCI address bits 31 16 and the offset bits 31 16 Bits 15 00 will be zero Advanced Debugger Topics 20S6 00 9Sc LL 3434 000000 34424244 00000014 343344 000000 344433 00000010 34444434 34424444 34444444 zd 33444443 3ovds 3ovds AHOW3IN AHOW3MW c q 9iv O I LHOHS 00004444 00004444 000044312 00004443 at E AOVdS AYOWAWN eit 3N IS m lt q dddddzdd ee ee fee 00004242 dd AOVdS AYOWAN 9Iq eev 000000143 3ovds 00000014 00000012 00000013 AYOWAN F4 34444404 39vd d 33444404 34444402 344344403 3Oovds AHOW3IN 9IQ vcV 00000004 00000004 00000002 00000003 at 3433333 44444441 ddddddil Fe Fe eb Be 3ovds 3OovdS 3Oovds 3OovdS AHOW3IN AHON3IN AHOW3MW AHOW3IN lod ceacev L H31SVIN HE JAVITS 00000010 00000010 00000010 00000019 a ti sn diuo q3INA eau93IWNA IOde3WA 00000009 YOSS300 d Figure 6 1 PPCBug Default Processor to VMEbus Mapping 6 12 Modifying Parameters in EEPROM VME2PCI Slave Enable 2 Y N Y Y Enable VME2PCI Slave Address Decoder 2 N Disable VME2PCI Slave A
106. mplied integer bit always 1 Scientific Notation The scientific notation format provides a convenient way to enter and display a floating point decimal number Internally the number is assembled into a packed decimal number and then converted into a number of the specified data type Entering data in this format requires the following fields a An optional sign bit or a One decimal digit followed by a decimal point a Up to 17 decimal digits at least one must be entered a An optional Exponent field that consists of An optional underscore The Exponent field identifier letter E An optional Exponent sign From 1 to 3 decimal digits For more information about the floating point unit refer to the PowerPC 603 RISC Microprocessor User s Manual Advanced Debugger Topics Ordering Related Documentation Motorola Computer Group Documents The publications listed below are on related products and some may be referenced in this document If not shipped with this product manuals may be purchased by contacting your local Motorola sales office Table A 1 Motorola Computer Group Documents Document Title t PowerBase Embedded Controller Installation and Use VMEPBA IH PowerBase Embedded Controller Programmer s Reference Guide VMEPBA PG PowerCom Installation and Use Manual VMEPCOMA IH PPCBug Firmware Package User s Manual Parts 1 and 2 2 PPCBUGA1 UM PPCBUGA2 UM PPC1Bug
107. n Space 4 2 Programming the PowerBase Table 4 1 Processor View of the Memory Map Processor Address ECL Addrest Seed Size Generated Definition Notes Start End Start End 00000000 7FFFFFFF 2GB DRAM Not Forwarded to PCI 80000000 807FFFFF 8MB 00000000 OO7FFFFF ISA PCI I O Space 1 2 5 80800000 80FFFFFF 8MB 00800000 OOFFFFFF Direct Map PCI Configuration 3 Space 81000000 BF7FFFFF 1000MB 01000000 3F7FFFFF PCI I O Space BFS8FFFFF BFFFFFEF 8MB Reserved 16B BFFFFFFO BFFFFFFF 16B 3FFFFFFO 3FFFFFFF PCI IACK Special Cycles 6 C0000000 COFFFFFF 16MB 00000000 OOFFFFFF PCI ISA Memory Space C1000000 FEFFFFFF 1GB 01000000 3EFFFFFF PCI Memory Space 32MB Two possible mappings follow depending on whether the PROM mezzanine is installed Refer to Note 4 FF000000 FFEFFFFF 15MB Reserved 4 FFF00000 FFF7FFFF 512KB Onboard PROM Flash Bank 0 4 FFF80000 FFFFFFFF 512KB Onboard PROM Flash Bank 1 4 FF000000 FFBFFFFF 12MB Reserved 4 FFC00000 FFFFFFFF 4MB PROM Mezzanine Bank 0 4 Notes 1 PCI configuration accesses to CF8 Configuration Address and CFC Configuration Data are supported by the MPC105 PCI bridge memory controller as specified in the PCI Specification Revision 2 0 Both Contiguous and Discontiguous mappings are supported by the PowerBase MVME1300 series See the ISA PCI I O Space Mapping section for more details This sp
108. nd pins is used to provide access to the Processor Bus and some MPC105 signals The pin assignments for this connector J4 are as follows Table C 5 CPU Connector Pin Assignments J4 1 PAO PA1 2 3 PA2 PA3 4 5 PA4 PA5 6 7 PA6 PA7 8 9 PA8 PA9 10 11 PA10 PA11 12 13 PA12 PA13 14 15 PA14 PA15 16 17 PA16 PA17 18 19 PA18 PA19 20 21 PA20 PA21 22 23 PA22 PA23 24 25 PA24 PA25 26 27 PA26 PA27 28 29 PA28 PA29 30 31 PA30 PA31 32 33 PAPARO PAPAR1 34 35 PAPAR2 PAPAR3 36 37 APE RSRV_ 38 Connector Pin Assignments Table C 5 CPU Connector Pin Assignments J4 Continued 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 PDPARO PDPAR1 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 112 113 DPE DBDIS _ 114 Pin Assignments Table C 5 CPU Connector Pin Assignments J4 Continued 115 117 119 121 123 125 CL
109. nformation in this manual applies principally to the MVME130x PowerBase boards The PMCs PROM mezzanine transition modules and SIMs are described briefly here but are documented in detail in separate publications Document Terminology Throughout this manual a convention is used which precedes data and address parameters by a character identifying the numeric format as follows Dollar m Specifies a hexadecimal character Ox Zero x Percent Specifies a binary number amp Ampersand Specifies a decimal number For example 12 is the decimal number twelve and 12 hexadecimal is the equivalent of decimal number eighteen Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows Byte 8 bits numbe
110. ng programs A self test at power up feature which verifies the integrity of the system PPCBug consists of three parts a A command driven user interactive software debugger described in the PPCBug Firmware Package User s Manual It is hereafter referred to as the debugger or PPCBug a A command driven diagnostics package for the PowerBase hardware hereafter referred to as the diagnostics The diagnostics package is described in the PPC1Bug Diagnostics Manual a A user interface or debug diagnostics monitor that accepts commands from the system console terminal When using PPCBug you operate out of either the debugger directory or the diagnostic directory a If you are in the debugger directory the debugger prompt PPC1 Bug gt is displayed and you have all of the debugger commands at your disposal a If you are in the diagnostic directory the diagnostic prompt PPCl Diag is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands Because PPCBug is command driven it performs its various operations in response to user commands entered at the keyboard When you enter a command PPCBug executes the command and the prompt reappears However if you enter a command that causes execution of user target code e g GO then control may or may not return to PPCBug depending on the outcome of the user program 5 2 PPCBug Implementation PPCBug Im
111. nother qualifier is provided In the alternate register number Rn form the debugger uses the address contained in MPU Register Rn where n is 0 through 31 i e 0 1 31 In commands with the address range specified as ADDR ADDR and with size option H or W chosen data at the second ending address is acted on only if the second address is a proper boundary for a half word or word respectively Otherwise the range is truncated so that the last byte acted upon is at an address that is a proper boundary Offset Registers Eight pseudo registers Z0 Z7 called offset registers are used to simplify the debugging of relocatable and position independent modules The listing files in these types of programs usually start at an address normally 0 that is not the one at which they are loaded so it is harder to correlate addresses in the listing with addresses in the loaded program The offset registers solve this problem by taking into account this difference and forcing the display of PORT Entering Debugging Commands addresses in a relative address offset format Offset registers have adjustable ranges and may even have overlapping ranges The range for each offset register is set by two addresses base and top Specifying the base and top addresses for an offset register sets its range In the event that an address falls in two or more offset registers ranges the one that yields the least offset is chosen Note Relative addr
112. ode of operation in the processor s domain VMEbus Domain The VMEbus is inherently big endian All devices connected directly to the VMEbus are expected to operate in big endian mode regardless of the mode of operation in the processor s domain In big endian mode byte swapping is performed first by the VME2PCI and then by the MPC105 The result has the desirable effect of being transparent to the big endian software In little endian mode however software must take the byte swapping effect of the VME2PCI and the address reverse rearranging effect of the MPC105 into account 4 31 Programming Considerations BIG ENDIAN PROGRAM oa DRAM A M BIG ENDIAN A N WAY BYTE SWAP LITTLE ENDIAN PCI m T gt VME2PCI Y LITTLE ENDIAN A N WAY BYTE SWAP BIG ENDIAN VMEchip2 VMEbus a 11190 00 9411 Figure 4 6 Big Endian Mode 4 32 Programming the PowerBase LITTLE ENDIAN PROGRAM LITTLE ENDIAN A EA MODIFICATION XOR BIG ENDIAN fce D MPC105 y DRAM M S EA MODIFICATION BIG ENDIAN A A LITTLE ENDIAN PCI m T gt VME2PCI Y LITTLE ENDIAN A N WAY BYTE SWAP i BIG ENDIAN VMEchip2 VMEbus a 11191 00 941
113. of both memory banks Thus only a total of eight parity devices are required A status bit available from the general purpose I O port allows the firmware to know whether parity is present or not This bit is controlled by a pulldown resistor 3 7 PowerBase Components DRAM Specifi cations The PowerBase uses 1Mx16 devices in 400 mil 50 pin TSOP packaging The following table lists the DRAM specifications Table 3 4 DRAM Specifications DRAM Specifications Options Quantity Size and Configuration Package Speed 8MB Main 4 1M x 16 400 mil TSOP 60ns 16MB Main 8 1M x 16 400 mil TSOP 60ns DRAM Timing Configurations Onboard DRAM devices on the PowerBase are controlled by the MPC105 Refer to the MPC105 specification for additional performance information The following table shows the programming values including latency for the MPC105 timing configurations required for 60ns DRAM at the processor memory bus frequency Table 3 5 Programming Values for DRAM Timing Configurations Processor Read Write Timing Configurations DRAM External Bus Lat Frequency RP1 RCD2 CAS3 CP4 CAS5 RAS6P arency 66 66MHz 3 2 4 1 3 4 8 4 4 4 Clocks There are two oscillators on the PowerBase board 1 A 14 31818MHz oscillator which feeds an MPC980 clock driver chip The MPC980 provides the 66 6MHz and 33 3MHz clocks for the MPC603 processor the MPC105 3 8
114. omponent designation for the PowerPC 601 microprocessor Motorola s component designation for the PowerPC 603 microprocessor Motorola s component designation for the PowerPC 603e microprocessor GL 6 Glossary MPC604 MPU MTBF multisession non interlaced nonvolatile memory NTSC NVRAM OEM OMPAC OS OTP palette Motorola s component designation for the PowerPC 604 microprocessor MicroProcessing Unit Mean Time Between Failures A statistical term relating to reliability as expressed in power on hours poh It was originally developed for the military and can be calculated several different ways yielding substantially different results The specification is based on a large number of samplings in one place running continuously and the rate at which failure occurs MTBF is not representative of how long a device or any individual component is likely to last nor is it a warranty but rather an indicator of the relative reliability of a family of products The ability to record additional information such as digitized photographs on a CD ROM after a prior recording session has ended A video system in which every pixel is refreshed during every vertical scan A non interlaced system is normally more expensive than an interlaced system of the same resolution and is usually said to have a more pleasing appearance A memory in which the data content is maintained whether the power supply is connec
115. onal PROM mezzanine on your PowerBase board Installing the Hardware JN Caution A Warning AN Caution 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure Note If your MVME130x has not yet been installed in a chassis go to step 4 2 Perform an operating system shutdown a Turn the AC or DC power off and remove the AC cord or DC power lines from the system Inserting or removing modules with power applied may result in damage to module components Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting b Remove chassis or system cover s as necessary for access to the VMEmodules 3 Remove the screws securing the MVME130x to the chassis and remove the MVME130x from its card slot 4 Lay the MVME130x on a level surface with the P1 and P2 connectors on your right and position the PROM mezzanine above it in the upper right hand corner Refer to Figure 1 1 Avoid touching areas of integrated circuitry static discharge can damage these circuits Preparing and Installing the PowerBase 5 Gently seat the PROM mezzanine onto the PowerBase module ensuring that the connectors are properly aligned Refer to Figure 1 3 6 Using the provided screws fasten the PROM mezzanine to the MVME
116. otorola strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system Electronic components such as disk drives computer boards and memory modules can be extremely sensitive to Electro Static Discharge ESD After removing the component from the system or its protective wrapper place the component flat on a grounded static free surface and in the case of a board component side up Do not slide the component over any surface If an ESD station is not available you can avoid damage resulting from ESD by wearing an antistatic wrist strap available at electronics stores that is attached to an unpainted metal part of the system chassis Installing the PowerBase Before installing the PowerBase into your VME chassis ensure that the jumpers on PowerBase s J2 and J5 headers are configured as previously described If you intend to mount the optional PCI mezzanine cards PMCs or PROM mezzanine on your PowerBase refer to the sections Installing Optional PMCs and Installing the Optional PROM Mezzanine before you begin this procedure Proceed as follows to install the PowerBase in the VME chassis 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown a Turn the AC or DC power off and remove the AC cor
117. ower up reset only Default N Run Network Auto Boot at any reset Network Auto Boot Controller LUN 00 The boot controller Logical Unit Number Network Auto Boot Device LUN 00 The boot device Logical Unit Number Network Auto Boot Abort Delay 5 The time in seconds that the Network Auto Boot sequence waits before starting the boot During the delay a user may exit to the debugger or diagnostics prompt by pressing the BREAK key The value is from 0 255 Network Auto Boot Configuration Parameters Offset NVRAM 00001000 The address where the network interface configuration parameters are saved retained in EEPROM These parameters are the necessary parameters to perform an unattended network boot A typical offset might be 1000 but this is application specific Note The default value of 00001000 locates the NIOT parameters just above the PRP partition of the EEPROM 6 8 Modifying Parameters in EEPROM Memory Size Enable Y N Y Y Memory will be sized for Self Test diagnostics Default N Memory will not be sized for Self Test diagnostics Memory Size Starting Address 00000000 The Starting Address for memory sizing Memory Size Ending Address 40000000 The Ending Address for memory sizing This is the calculated size of local memory If the memory start is changed from 0 this parameter would also need to be adjusted The default may be different for each board DRAM Speed in NA
118. ows CKM1 CKMO PCI Bus Clock 0 0 1 1 0 1 0 1 33MHz 20MHz 25MHz 33 33MHz CPU External Bus Clock 33MHz 40MHz 50MHz 66 66MHz For the PowerBase this field is hardwired to 11b CPU type These four bits reflect the CPU type information For the PowerBase this field is hardwired to 11b 4 18 Programming the PowerBase Software Readable Header Register The Software Readable Header J2 on the PowerBase controls a read only register located at ISA I O address x801 A jumper installed for a particular bit results in a logic 0 and no jumper results in a logic 1 With the jumper installed between pins 3 and 4 factory configuration the debugger uses the current user setup operation parameters in EEPROM When the jumper is removed making the bit a 1 the debugger uses the default setup operation parameters in ROM instead Refer to the ENV command description in Chapter 6 for the ROM defaults The five higher order bits SRH3 to SRH7 are required to get GCSR locations for up to 18 boards when used in a Wide Area Network WAN Refer also to Chapter 1 Setting the General Purpose Software Header J2 Table 4 9 Software Readable Header Jumpers J2 Pins SRH Bit Definition 1 and 2 Bit 0 SRHO Reserved for future use 3 and 4 Bit 1 SRH1 Used for setup operation parameters selection 5 and 6 Bit 2 SRH2 Reserved for future use 7 and 8 Bit 3 SRH3 Use
119. plementation ZN Caution Physically PPCBug is contained in two Flash devices on the PowerBase that together provide 1MB of storage If the optional PROM mezzanine board is mounted on the PowerBase the firmware on the PowerBase board is no longer accessible PPCBug is written largely in the C programming language providing benefits of portability and maintainability Where necessary assembler has been used in the form of separately compiled program modules containing only assembler code No mixed language modules are used The executable code is checksummed at every power on or reset firmware entry The result is checked with a pre calculated checksum contained in the last 16 bit word of the Flash image Comparison with Other MCG Debuggers PPCBug is similar to previous Motorola Computer Group MCG firmware debugging packages such as MVME147Bug MVME167Bug and MVME187Bug with differences due to microprocessor architectures These differences are primarily reflected in the a Instruction mnemonics a Register displays a Addressing modes of the assembler disassembler a Argument passing to the system calls 5 3 Using PPCBug Power Up Reset Sequence Figure 5 1 illustrates the basic flow the firmware follows at a power up reset sequence On the PowerBase the default power up condition is to the setup parameters contained in EEPROM Using the ENV command Chapter 6 you can change this if desired
120. pts route control registers The parameter is a 32 bit value divided into four parts to yield the four PIRQx PIRQ0 1 2 3 route control registers which are each a byte wide The default value xxxxxxxx is dependent upon the system type Runs an ENV D command to get the default value specific to the host system Modifying Parameters in EEPROM Configuring the VMEbus Interface The following parameters set up the VMEbus interface for PowerBase modules Refer to the VME2PCI and VMEchip2 ASICs information in Chapter 4 and to the PowerBase Embedded Controller Programmer s Reference Guide for information on these parameters Figure 6 1 illustrates the processor to VMEbus mapping VME2PCI Master Master Enable Y N Y Y Enable all VMEbus interface master and slave decoders Default N Disable all VMEbus interface master and slave decoders VME2PCI Slave Enable 1 Y N Y Y Y Enable the VME2PCI Slave Address Decoder 1 N Disable VME2PCI Slave Address Decoder 1 VME2PCI Slave Starting Address 1 01000000 The starting address of the first PCI Memory Space for the VME2PCT s slave interface PCI memory accesses within the range of the starting and ending addresses are passed on to the VMEchip2 as adjusted by the slave address offset Only the upper 16 bits of this address are significant VME2PCI Slave Ending Address 1 1FFFFFFF The ending address of the first PCI Me
121. r Commands Command Command Mnemonic Title AS One Line Assembler BC Block of Memory Compare BF Block of Memory Fill BI Block of Memory Initialize BM Block of Memory Move BR Breakpoint Insert NOBR Breakpoint Delete BS Block of Memory Search BV Block of Memory Verify CM Concurrent Mode NOCM No Concurrent Mode CNFG Configure Board Information Block CS Checksum DC Data Conversion DMA Block of Memory Move DS One Line Disassembler DU Dump S Records ECHO Echo String ENV Set Environment GD Go Direct Ignore Breakpoints GEVBOOT Global Environment Variable Boot See Note GEVDEL Global Environment Variable Delete See Note GEVDUMP Global Environment Variable s Dump See Note GEVEDIT Global Environment Variable Edit See Note GEVINIT Global Environment Variable Initialization See Note Using PPCBug Table 5 2 Debugger Commands Continued Command Command Mnemonic Title GEVSHOW Global Environment Variable s Display See Note GN Go to Next Instruction GO Go Execute User Program GT Go to Temporary Breakpoint HE Help IOC I O Control for Disk See Note IOI I O Inquiry See Note IOP I O Physical Direct Disk Access See Note IOT I O Teach for Configuring Disk Controller See Note LO Load S Records from Host MA Macro Define Display NOMA Macro Delete MAE Macro Edit MAL Enable
122. red 0 through 7 with bit 0 being the least significant Half word 16 bits numbered 0 through 15 with bit 0 being the least significant Word 32 bits numbered 0 through 31 with bit 0 being the least significant Double word 64 bits numbered 0 through 63 with bit 0 being the least significant Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the equipment Motorola Inc assumes no liability for the customer s failure to comply with these requirements The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground The equipment is supplied with a three conductor ac power cable The power cable must be plugged into an approved three contact electrical outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards Do Not Operate in an Explosive Atmo
123. ress of the local resource that is accessible by the VMEbus Default is the base of local memory Slave Ending Address 1 3FFFFFFF The ending address of the local resource that is accessible by the VMEbus Default is the end of calculated memory Slave Address Translation Address 1 80000000 The base address of local resource that is associated with the slave starting and ending addresses This allows the VMEbus address and the local address to be different Slave Address Translation Select 1 00000000 A mask that defines which bits of the address are significant A 1 indicates a significant bit A 0 indicates a nonsignificant bit Slave Control 1 O3FF The access restriction for the address space defined with this slave address decoder VMEbus Slave Write Post and Snoop Control Register and VMEbus Slave Address Modifier Select Register Default 03FF Slave Enable 2 Y N N Y Enable the Slave Address Decoder 2 N Do not enable the Slave Address Decoder 2 Slave Starting Address 2 00000000 The base address of the local resource that is accessible by the VMEbus Modifying Parameters in EEPROM Slave Ending Address 2 00000000 The ending address of the local resource that is accessible by the VMEbus Slave Address Translation Address 2 00000000 The base address of local resource that is associated with the slave starting and ending addresses This allows the VMEbus addr
124. rs This value is right justified as any other numeric value would be String Literal eee A 41 ABC 414243 TEST 54455354 Evaluation of an expression is always from left to right unless parentheses are used to group part of the expression There is no operator precedence Subexpressions within parentheses are evaluated first Nested parenthetical subexpressions are evaluated from the inside out Valid Expression Examples Expression P Notes FF0011 FF0011 45 99 DE amp 45 amp 99 90 35 67 10 5C 10011110 1001 A7 88 lt lt 4 880 shift left AA amp FO AO logical AND The total value of the expression must be between 0 and FFFFFFFF Using PPCBug ADDR The syntax for the ADDR argument is similar to the syntax accepted by the PowerPC one line assembler All control addressing modes are allowed An address offset register mode is also provided ADDR Formats The ADDR format is HexadecimalNumber S s AU u Rr Enter ADDR as a hexadecimal number e g 20000 for address 00020000 The address or starting address of a range can be qualified by a suffix either S or s for supervisor address space or U or u for user address space The default when the suffix is not specified is supervisor Once a qualifier has been entered it remains valid for all addresses entered for that command sequence until either the PPCBug is reentered or a
125. rt Pins Assignment Continued PortPin Signal Name Direction Signal Name PA6 FUSE Input FUSE 1 means at least one of the polyswitches on the PowerBase MVME1300 series board is opened PA7 ABORT_ Input Status of the ABORT_ signal Programming Considerations Good programming practice dictates that only one MPU at a time have control of the MVME130x control registers Of particular note are 4 Registers that modify the address map 4 Registers that require two cycles to access a VMEbus interrupt request registers PCI Arbitration There are five potential PCI bus masters on the MVME130x embedded controller a MPC105 PCI MPU bus bridge and memory controller a IBC PCI ISA bus bridge controller a VME2PCI ASIC PCI VMEchip2 interface ASIC a Two PMC PCI mezzanine card slots The IBC supplies the PCI arbitration support for these five devices The IBC supports flexible arbitration modes of fixed priority rotating priority and mixed priority The IBC registers that control the arbitration mode are the PCI Arbiter Priority Control PAPC Register and the PCI Arbiter Priority Control Extension ARBPRIX Register The PAPC register and the ARBPRIX register default to 04 hex and 00 hex 4 23 Programming Considerations respectively This default configuration puts the CPU MPC105 at the highest priority level Refer to the 582378ZB Reference Manual for programming information
126. rved space may select multiple devices and produce unpredictable results 2 When a double width PMC is installed it may use either A16 or A17 for its IDSEL During configuration the firmware will need to probe the PCI bus to find the location of this PMC s configuration space ISA PCI I O Space Programming the PowerBase Table 4 3 focuses on the mapping of the ISA PCI I O space from the processor view of the memory map Table 4 3 ISA PCI I O Space Memory Map ISA I O Processor Address Function Notes Address Contiguous Discontiguous 0020 8000 0020 8000 1000 IBC Interrupt 1 Control amp Mask 2 0021 8000 0021 8000 1001 0040 8000 0040 8000 2000 IBC Timer Counter 1 Registers 2 0043 8000 0043 8000 2003 0060 8000 0060 8000 3000 IBC Reset Ubus IRO12 2 0061 8000 0061 8000 3001 IBC NMI Status and Control 2 0074 8000 0074 8000 3014 EEPROM Address Strobe 0 0075 8000 0075 8000 3015 EEPROM Address Strobe 1 0077 8000 0077 8000 3017 EEPROM Data Port 0092 8000 0092 8000 4012 IBC Port 92 Register 2 00A0 8000 00A0 8000 5000 IBC Interrupt 2 Control amp Mask 2 00A1 8000 00A1 8000 5001 O3F8 8000 03F8 8001 F018 PC16550 UART Serial Port 1 DEBUG 3 O3FF 8000 O3FF 8001 FO1F 04D0 8000 04D0 8002 6010 IBC INT1 Edge Level Control 2 04D1 8000 04D1 8002 6011 IBC INT2 Edge Level Control 2 0800 8000 0800 8004 0000 CPU Configuration Register 4 0801 8000 0801 8004 0001
127. s refer to the PowerBase Embedded Controller Programmer s Reference Guide Code Command Name and Description 0x0001 Invoke Selftest Execute Selftest Multiprocessor Support Remote Start This command sets a Busy Failed Selftest bit and starts selftest When the selftests are complete it clears the bit that started the test If the selftests pass the Busy Failed Selftest bit is cleared If not the address of an error message buffer is written to two GCSR registers GCSR1 and GCSR2 0x0002 Setup VMEbus Slave Decoder 1 This command sets Slave Decoder 1 starting ending translation and select addresses as well as write post and snoop control using values found in the GCSR registers 0x0004 Read a PowerBase local resource This command reads data from an address found in two GCSR registers and copies it into two other GCSR registers 0x0008 Write a PowerBase local resource This command copies data from two GCSR registers and writes it into the address found in two other GCSR registers 0x0010 Request Board Information or query for residual data This command returns the address of the board residual data It will locate the start of free memory and initialize a residual data structure Using the GO Command through GCSR A remote processor can initiate program execution in a local MVME 130x PowerBase board s dual port RAM by issuing a remote GO command using the Global Control and Status Registers GCSR
128. s initialize RAM including the memory locations used for multi processor support MPCR and MPAR The MPCR contains 00 at power up indicating that initialization is not yet complete As the initialization proceeds the execution path comes to the routine that displays the prompt Before sending the prompt this routine places an R in the MPCR to indicate that initialization is complete Then the prompt is sent If no terminal is connected to the port the MPCR is still polled to see whether an external processor requires control to be passed to the dual port RAM If a terminal does respond the MPCR is polled for the same purpose while the serial port is being polled for user input A G placed in the MPCR by a remote processor indicates that the Go Direct type of transfer is requested as with the GD command A B in the MPCR indicates that breakpoints are to be armed before control is transferred as with the GO command In either sequence an E is placed in the MPCR to indicate that execution is underway just before control is passed to RAM Any remote processor could examine the MPCR contents If the code being executed in dual port RAM is to re enter PPCBug a system call using function 0063 SYSCALL RETURN returns control to PPCBug with a new display prompt Note that every time PPCBug returns to the prompt an R is moved into the MPCR to indicate that control can be transferred once again to a specified RAM location Mul
129. s routed to the IDSEL pin on PMC slot 1 therefore the base address of the configuration space of this PMC slot is at 00810000 in the PCI configuration area PowerBase Components PMC2 PMC slot 2 supports Mezzanine type PCI Mezzanine Card PMC Mezzanine size Single width and standard depth 75mm x 150mm with front panel PMC connectors J21 and J22 82 Bit PCI with front panel I O only Signalling voltage Vig 5 0V AD17 is routed to the IDSEL pin on PMC slot 2 therefore the base address of the configuration space of this PMC slot is at 00820000 in the PCI configuration area Double Width PMC The PMC connectors are located such that a double width PMC may be installed in place of the two single width PMCs In this case the PowerBase supports the following Mezzanine type PCI Mezzanine Card PMC Mezzanine size Double width and standard depth 150mm x 150mm with front panel PMC connectors J11 J12 J21 J22 and J14 32 bit PCI with front panel or P2 I O Signalling voltage Vig 5 0V For the double width PMC it may pick up AD16 from the PMC slot 1 connector or AD17 from the PMC slot 2 connector therefore the base address of the configuration space of this PMC may be at 00810000 or 00820000 in the PCI Configuration area Transition Board Power The PowerBase board supplies 12V 12V 5V and 3 3V to the PMCs Because PMC1 is wired directly to the 64 I O pins of P2 it must provide power to any tr
130. safety features are maintained Dangerous Procedure Warnings Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing WARNING and adjusting This equipment generates uses and can radiate electro magnetic energy It may cause or be susceptible to electro magnetic interference EMI if not WARNING installed and used in a cabinet with adequate EMI protection European Notice Board products with the CE marking comply with the EMC Directive C 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 CISPR 22 Radio Frequency Interference EN50082 1 IEC801 2 IEC801 3 IEEC801 4 Electromagnetic Immunity The product also fulfills EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC This board product was tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC safety performance All Motorola PWBs printed wiring boards are manufactured by UL recognized manufacturers
131. se from IBM A variant of the second implementation of the PowerPC family of microprocessors This CPU incorporates a faster clock 100MHz and 256KB L2 cache PowerPC 603e is used by Motorola Inc under license from IBM The third implementation of the PowerPC family of microprocessors currently under development PowerPC 604 is used by Motorola Inc under license from IBM PowerPC Reference Platform PRP A specification published by the IBM Power Personal Systems Division which defines the devices interfaces and data formats that make up a PRP compliant system using a PowerPC processor PowerStack RISC PC System Board PRP PRP compliant PRP Spec PROM PS 2 QFP A PowerPC based computer board platform developed by the Motorola Computer Group It supports Microsoft s Windows NT and IBM s AIX operating systems See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP Programmable Read Only Memory Personal System 2 IBM Quad Flat Package GL 9 J o0ooro 2 o0o00r o Glossary RAM RAS Random Access Memory The temporary memory that a computer uses to hold the instructions and data currently being worked with All data in RAM is lost when the computer is turned off Row Address Strobe A clock signal used in dynamic RAMs to control the input of the row addresses Reduced Instruction Set Computer RISC RFI RGB RISC ROM R
132. signals Step 6 does not apply to such backplane designs Preparing and Installing the PowerBase 6 On the chassis backplane remove the INTERRUPT ACKNOWLEDGE IACK and BUS GRANT BG jumpers from the header for the card slot occupied by the MVME130x If you intend to use PPCBug interactively connect the terminal that is to be used as the PPCBug system console to the DEBUG port on the front panel of the PowerBase Set up the terminal as follows Eightbits per character Onestop bit per character Parity disabled no parity Baud rate 9600 baud default baud rate of the port at power up In normal operation the host CPU controls PowerBase operation via the VMEbus GCSR registers refer to MultiProcessor Support in Chapter 5 In normal operation connection of a debug console terminal is required only if you intend to use PPCBug interactively Replace the chassis or system cover s cable peripherals to the panel connectors as appropriate reconnect the system to the AC or DC power source and turn the equipment power on The MVME130x s CPU LED indicates activity as a set of confidence tests is run and the debugger prompt PPc1 Bug gt appears Installing the Optional PROM Mezzanine AN Caution When you install the PROM Mezzanine on your PowerBase the Flash devices will be inaccessible and you will not be able to use the PPCBug functions in Flash Proceed as follows to install the opti
133. sors The location of MPCR is calculated as local RAM size minus 1C000 The MPCR contents are organized as follows N A N A N A MPCR The status codes stored in the MPCR are of two types d Status returned from the monitor a Status set by the bus master The status codes that may be returned from the monitor are NUL 00 Wait the initialization is not yet complete E 45 Code pointed to by the MPAR address is executing P 50 Program Flash Memory The MPAR is set to the address of the Flash memory program control packet R 52 Ready the firmware monitor is watching for a change You can only program Flash memory by the MPCR method See the PFLASH system call for a description of the Flash memory program control packet structure The status codes that may be set by the bus master are G 47 Initiate code at the MPAR address in a manner similar to the GD command B 42 Initiate code at the MPAR address with breakpoints enabled in a manner similar to the GO command Using PPCBug The Multiprocessor Address Register MPAR contains the second of two words used to control communication between processors The MPAR contents specify the address at which execution for the remote processor is to begin if the MPCR contains a G or B The location of MPAR is calculated as MPCR plus 4 The MPAR is organized as follows MP AR At power up the PPCBug self test routine
134. sphere Do not operate the equipment in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment constitutes a definite safety hazard Keep Away From Live Circuits Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust Alone Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present Use Caution When Exposing or Handling the CRT Breakage of the Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion avoid rough handling or jarring of the equipment Handling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that
135. splays a warning message if the verification fails Displays the BUS clock speed verifies that the BUS clock speed matches the configuration data and displays a warning message if the verification fails Probes PCI bus for supported network devices Probes PCI bus for supported mass storage devices Initializes the memory IO addresses for the supported PCI bus devices Executes Self Test if so configured Default is no Self Test Fxtinguishes the board fail LED if Self Test passed and outputs any warning messages Executes boot program if so configured Default is no boot Executes the debugger monitor i e issues the PPc1 Bug gt prompt Multiprocessor Support Remote Start The PowerPC board dual port RAM feature makes the shared RAM available to remote processors as well as to the local processor This can be done by either of the following two methods Either method can be enabled disabled by the ENV command as its Remote Start Switch method Note that PPCBug runs in single processor operation only Multiprocessor Support Remote Start Refer to Chapter 6 for information on setting the ENV command parameters Multiprocessor Control Register MPCR Method A remote processor can initiate program execution in the local PowerPC board dual port RAM by issuing a remote GO command using the Multiprocessor Control Register MPCR MPCR contains one of two words used to control communication between proces
136. t can provide hardware assistance for graphics drawing algorithms by performing logical functions on data written to display memory Hardware Abstraction Layer The lower level hardware interface module of the Windows NT operating system It contains platform specific functionality The term used to describe any of the physical embodiments of a computer system with emphasis on the electronic circuits the computer and electromechanical devices peripherals that make up the system A computing system is normally spoken of as having two major components hardware and software Hardware Conformance Test A test used to ensure that both hardware and software conform to the Windows NT interface Input Output PCI ISA Bridge Controller Intelligent Device Expansion Institute of Electrical and Electronics Engineers A graphics system in which the even scanlines are refreshed in one vertical cycle field and the odd scanlines are refreshed in another vertical cycle Its advantage is that the video bandwidth is roughly half that required for a non interlaced system of the same resolution This results in less costly hardware and may also make it possible to display a resolution that would otherwise be impossible on given hardware The disadvantage of an interlaced system is flicker especially when displaying objects that are only a few scanlines high Similar to the color difference signals R Y B Y but using different vector axis
137. ted etc Abort is invoked by pressing and releasing the PowerBase board s ABORT switch 5 6 Board Failure Whenever abort is invoked when executing a user program running target code a snapshot of the processor state is captured and stored in the target registers When working in the debugger abort captures and stores only the following 4 Instruction pointer 4 Status register a Format and vector information For this reason abort is most appropriate when terminating a user program that is being debugged Abort should be used to regain control if the program gets caught in a loop etc The target IP and register contents help to pinpoint the malfunction Pressing and releasing the abort switch causes the following a An interrupt is sent to the microprocessor a The target registers reflecting the machine state at the time the abort switch was pressed are displayed on the screen LE Any breakpoints installed in the user code are removed 4 Breakpoint table remains intact a Control is returned to the debugger Board Failure The following conditions result in a board failure a Board initialization error failure a Debugger object checksum error a Environment data EEPROM ENV parameters failure i e checksum a Configuration data EEPROM CNFG parameters failure i e checksum 5 7 Using PPCBug a Calculated MPU clock speed does not match the associative CNFG parameter
138. ted or not National Television Standards Committee USA Non Volatile Random Access Memory Original Equipment Manufacturer Over Molded Pad Array Carrier Operating System The software that manages the computer resources accesses files and dispatches programs One Time Programmable The range of colors available on the screen not necessarily simultaneously For VGA this is either 16 or 256 simultaneous colors out of 262 144 GL 7 J o0ooro 2 o0o00r o Glossary parallel port PCI local bus PCMCIA bus PDS physical address PIB pixel PLL PMC POWER PowerPCTM A connector that can exchange data with an I O device eight bits at a time This port is more commonly used for the connection of a printer to a system Peripheral Component Interconnect local bus Intel A high performance 32 bit internal interconnect bus used for data transfer to peripheral controller components such as those for audio video and graphics Personal Computer Memory Card International Association bus A standard external interconnect bus which allows peripherals adhering to the standard to be plugged in and used without further system modification Processor Direct Slot A binary address that refers to the actual location of information stored in secondary storage PCI to ISA Bridge An acronym for picture element also called a pel A pixel is the smallest addressable graphic on a display screen
139. the IBC that the source of the interrupt is the VME2PCI the software determines the interrupt level to acknowledge the VMEchip2 by examining the ILVL status bits of the Interrupt Control and Status Register in the VME2PCI ASIC Finally to get the interrupt vector from the VMEchip2 the interrupt handling routine must read the appropriate Pseudo IACK Registers Handling ABORT Interrupts The MVME130x can be programmed to generate an interrupt to the processor via ISA Interrupt IRQ8 when the ABORT switch is activated refer also to the ABORT Switch section at the beginning of this chapter The ABORT signal is also routed to the general purpose I O port Refer to the 82378ZB Data Sheet for programming information DMA Channels The IBC supports seven DMA channels The PowerBase does not use the DMA channels in the IBC 4 29 Programming Considerations Sources of Reset The MVME130x embedded controller has six equally powerful potential sources of reset 1 Power on reset 2 RESET switch 3 ALT RST function controlled by the Port 92 register in the IBC resets the VMEbus when the MVME130x is system controller 4 Reset sources from the VMEchip2 the VMEbus SYSRESET Watchdog Reset and Software Reset functions 5 When the MVME130x is operating as the VMEbus System Controller an HRESET signal will also cause a VMEbus SYSRESET Endian Issues The PowerBase supports both little endian e g Windows NT and bi
140. tiprocessor Support Remote Start Global Control and Status Register GCSR Methods Initialization These methods support PPCBug for the PowerBase MVME130x when used as a WAN communications controller and known as PowerCom To configure a system with multiple PowerBase boards in a VME chassis PowerBase memory must not by default automatically appear on the VMEbus at start up or overlap might occur hence the need for a command to control this through the GCSR 1 At start up PPCBug initializes the PowerBase board hardware registers to configure the board environment according to a defined set of parameters The specific parameters used may be default parameters or user selected parameters which were previously stored in non volatile memory 2 PPCBug initializes a residual data structure with certain important board specific product data The residual data structure adheres to the PRP Specification 3 At start up PPCBug determines an assigned location in VMEbus short I O space A16 which the PowerBase GCSR registers occupy The GCSR address is determined by the upper five software readable jumpers on header J2 also referred to as the board select number GCSR supports mapping from jumper settings Short I O addresses are contained in a table and looked up by comparing the board select number in the table to the jumpers present on the software readable jumper header J2 This function expects the first argument to be an unsi
141. uide 3 9 PowerBase Components VMEchip2 ASIC The VMEchip2 ASIC is a 324 pin LGA device Addresses from the VMEbus must be translated by the VMEchip2 to the upper 2GB area since that is where the onboard DRAM is mapped in the PCI memory space Refer to the PowerBase Embedded Controller Programmer s Reference Guide for programming information on the VMEchip2 VME2PCI ASIC The VME2PCI ASIC is a 225 pin OMPAC device that interfaces between the PCI Local Bus and the MC68040 bus the local bus of the VMEchip2 The VME2PCI performs address translation from PCI memory space so that the MPC603 processor can get to the VMEchip2 internal registers the VMEbus F page the VMEbus Short I O area and to perform pseudo IACK cycles to fetch interrupt vectors from the VMEchip2 and the VMEbus The VME2PCI ASIC also performs byte swapping between PCI and the VMEchip2 since PCI is little endian and VMEbus is big endian Little endian software may have to manipulate multi byte data when communicating to the VMEbus AD13 is routed to the IDSEL pin on the VME2PCI chip therefore the base address of the VME2PCI Configuration Space is at 00802000 in the PCI Configuration area Refer to the PowerBase Embedded Controller Programmer s Reference Guide for additional information ISA Bridge Controller IBC The PowerBase board uses the Intel 82378ZB to interface to the ISA bus for the debug port the EEPROM the Control and Status Registers CSRs
142. upports these PROM Flash device types Flash default AM29F040 150JC or equivalent PROM AM27C040 150JC or equivalent As supplied the two PLCC sockets hold Flash devices that contain bootstrap firmware If these devices are removed or corrupted your system will not boot Replacement PROM Flash devices must have board initialization and boot capability 3 6 PROM Flash Latency The following table shows the PROM Flash read latency at the processor memory bus frequency Functional Description Table 3 3 PROM Flash Read Latency P 8 Bit Access 64 Bit Access opi ROMFAL ROMNAL Times Times External Bus r Fr ie Value Value in number in number of cd of clocks clocks 66 66MHz 10 0 14 98 DRAM The MPC105 supports one or two banks of DRAM The PowerBase base board contains one bank four devices of IMx16 DRAM devices providing 8MB of DRAM or as a build option two banks eight devices of IMx16 DRAM devices providing 16MB of DRAM The DRAM is organized as 64 bits wide Parity Protection Optional parity protection is provided by eight 4Mx1 TSOP devices mounted on the back side of the board The board may be configured with 8MB or 16MB of non parity memory with only front side mounted chips but for parity memory the back side must also be populated Since the parity devices are 4M deep and the two main memory banks are only 1M deep one 4Mx1 device provides parity for a given byte
143. x in greater depth General Description The PowerBase is a general purpose high performance embedded controller VMEmodule based on the 66MHz PowerPC 603 microprocessor As shown in the PowerBase Features section PowerBase offers many standard features desirable in a computer system including a debug port Boot ROM PROM Flash memory DRAM and interface for two PCI Mezzanine Cards PMCs contained in a one slot VME package Its flexible mezzanine architecture allows relatively easy upgrades of the I O and or memory There are four standard buses on PowerBase PowerPC 603 Processor Bus PCI Local Bus ISA Bus VMEbus 3 1 PowerBase Features As shown in Figure 3 1 an MPC105 PCI Bridge Memory Controller provides the interface from the Processor Bus to PCI An 82378ZB device performs the bridge function between PCI and ISA Two ASIC devices VME2PCI and VMEchip2 provide the interface between the PCI Local Bus and the VMEbus The PCI local bus is a key feature In addition to the on board local bus peripherals the PCI bus supports an industry standard mezzanine interface IEEE P1386 1 PMC PCI Mezzanine Card PowerBase Features The base board contains the following a 66 66MHz MPC603 PowerPC processor a 8 or 16MB of DRAM with or without parity build options a 1MB of onboard PROM Flash memory for Boot ROM a Option for 4MB of PROM on a mezzanine board a VMEbus interface implemented with VMEchip2 ASIC VM
144. yte 12 Half Word 1234 Word 12345678 Advanced Debugger Topics Floating Point Data Types Single Precision Real 1 FF 7FFFFF Double Precision Real 1 7FF FFFFFFFFFFFFF Scientific Notation 3 12345678901234501 E4123 decimal When entering data in single or double precision format observe the following rules a The sign field is the first field and is a binary field a The exponent field is the second field and is a hexadecimal field a The mantissa field is the last field and is a hexadecimal field a Thesign field the exponent field and at least the first digit of the mantissa field must be present any unspecified digits in the mantissa field are set to zero a Each field must be separated from adjacent fields by an underscore a Allthe digit positions in the sign and exponent fields must be present Single Precision Real The single precision real format would appear in memory as 1 bit sign field 1 binary digit 8 bit biased exponent field 2 hex digits Bias 7F 23 bit fraction field 6 hex digits A single precision number takes 4 bytes in memory Floating Point Support Double Precision Real The double precision real format would appear in memory as 1 bit sign field 1 binary digit 11 bit biased exponent field 8 hex digits Bias 3FF 52 bit fraction field 13 hex digits A double precision number takes 8 bytes in memory Note The single and double precision formats have an i

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