ADC-EMC User Manual AD001174 Version 1.3
Contents
1. Figure 2 XMC Switching Figure 2 shows the interface between primary XMC connectors of the two PMC XMC sites There are two groups of x4 SERDES signals between the two sites using switched routing Each SERDES lane x1 consists of a TX and RX pair The first group of x4 connects via a multiplexer to a x4 PCle port of the 8525 switch to allow host communication to XMC resources Alternatively the XMCs may be connected via the multiplexer to each other for sideband communication The second group of x4 connects via a multiplexer to a Samtec QSE DP connector to allow linking of multiple ADC EMC boards Alternatively the XMCs may be connected via the multiplexer to each other for sideband communication The cable used to connect 2 carrier cards via the QSE DP connectors is a Samtec EQDP 014 06 00 TTR TBL 2 Board Clocking PCle P PEX i pP la Ea P 3525 C PEX c c PEXx c PCle 1 8114 8114 Switch e x e x PCle PCle y ICS 1 9DB 5 106 e DR J 100MHz 2 Tri state 5 X8 PCle Primary Figure 3 Clock Distribution The clock distribution network on the ADC EMC uses a 1 6 buffer to replicate the 100MHz reference clock from the edge connector to all PCI Express devices Each clock driven to an XMC connector is automatically disa2. 30 31 AD 49 Ground 32 31 VO VO 32 33 Ground AD 48 34 33 VO VO 34 33 AD 47 AD 46 36 35 VO VO 36 37 AD 45 Ground 38 37 VO VO 38 39 V O AD 44 40 39 VO VO 40 41 AD 43 AD 42 42 41 VO VO 42 43 AD 41 Ground 44 43 VO VO 44 45 Ground AD 40 46 45 VO VO 46 47 AD 39 AD 38 48 47 VO VO 48 49 AD 37 Ground 50 49 VO VO 50 51 Ground AD 36 52 51 VO VO 52 53 AD 35 AD 34 54 53 VO VO 54 55 AD 33 Ground 56 55 VO VO 56 57 V O AD 32 58 58 VO VO 58 59 NC NC 60 59 VO VO 60 61 NC Ground 62 61 VO VO 62 63 Ground NC 64 63 VO VO 64 Notes V VO 3 3V For signal definitions see IEEE Std 1386 2001 ADC EMC User Manual Revision History Date Rev Comment Nov 2007 1 0 Initial release Jun 2008 1 1 Added JP4 Information Aug 2008 1 2 Section 3 3 Recommendation to install JP4 unless different power supplies are used in the system Section 3 10 Updated J5 Header table to clarify connections to Pn4 and pairing of differential signals Jun 2009 1 3 Fixed LED Definitions 3 12
3. 5GHz Board Architecture Description The ADC EMC is based on the PEX8525 PCIe switch and PEX8114 PCIe PCIX bridges Each PMC site is connected to an independent PCI PCI X bus as shown in Figure 1 Each of the two PMC sites supports Pn4 IO with quick switch isolation to permit various IO combinations A set of switches on the board enables each of the quick switch blocks The IO Bus is 64 bits wide and connects to all 64 signals from the Pn4 connector of each PMC site Further all of the IO Bus can be routed to the J5 header through a quick switch block that provides a level of protection to the IO bus signals by limiting the external signal levels 1 J J r gt 1 1 1 4 5 I x4 P PEX gk Clg PMC1 ala J M 8525 e 7 ia PCle 5 80 pin hdr 64 WO mux X8 serdes Switch ess AS q 2 PCle PCle I x4 4 2 1 x8 5 I X8 PCle Primary Figure 1 ADC EMC Board Block Diagram 1 1 ADC EMC User Manual 1 3 hdr hdr x4 x4 PCle PEX er puc 8525 PCle Switch PCle PCle 4 x8 y X8 PCle Primary X4 serdes gt puc X4 serdes fe a8 DAS a
4. backplane and J4 Power connector It is connected to the power controller device and can be removed to enable the OR ing feature between the disk power connector and PCIe edge connector This feature will protect the ADC EMC from feeding power from one power supply back to the other 3 4 J1 JTAG Connector NC 14 Ogi 13 GND NC 12 O O 11 GND TDI 10 o O 9 GND TDO 8 DOO 7 no TCK 6 O Of 5 GND TMS 4 OD 3 GND VREF 2 OO cn 3 6 ADC EMC User Manual For use with Xilinx Parallel IV or Platform Cable USB IDC ribbon cables For more information see DS300 or DS097 available at www xilinx com 3 5 J2 J3 Samtec QSE DP Connector Note J2 Connects to XMC1 J15 signals J3 connects to XMC2 J25 signals LINK DESCRIPTION PIN PIN DESCRIPTION LINK XMC_ DP4 1 2 XMC_ DP14 en XMC_DP4 3 4 XMC_ DP14 RAA XMC_ DP5 3 6 XMC_ DP15 IXB XMC_ DPS 7 8 XMC_ DP15 REB XMC_ DP6 9 10 XMC_ DP16 TC XMC_ DP6 11 12 XMC_ DP16 BAG XMC_ DP7 13 14 XMC_ DP17 us XMC_ DP7 15 16 XMC_ DP17 m Unused 17 18 Unused Unused 19 20 Unused Unused 21 22 Unused Unused 23 24 Unused Unused 25 26 Unused Unused 27 28 Unused 3 6 J4 Disk Power Connector 3 7 J16 J17 JTAG Headers 3 8 J18 RC Header Pin Function VCC JTAG I O Voltage input from PMC GND Unused TCK NC TDO TDI KEY Not Instal
5. ADC EMC User Manual AD001174 CAT DATA Version 1 3 158 POI gt gt y EXPRESS ADC EMC User Manual Copyright 2007 Alpha Data Parallel Systems Ltd All rights reserved This publication is protected by Copyright Law with all rights reserved No part of this publication may be reproduced in any shape or form without prior written consent from Alpha Data Parallel Systems Limited Alpha Data Parallel Systems Ltd 4 West Silvermills Lane Edinburgh EH3 5BD Scotland UK Phone 44 0 131 558 2600 Fax 44 0 131 558 2700 Email support alpha data com ADC EMC User Manual Reserved rights This manual is designed to provide outline information only Alpha Data has a continual policy of improving its products hence it reserves the right to change product specification without prior warning Alpha Data cannot accept any liability for loss or damages arising from the use of this manual or the use of products detailed within it Trademark acknowledgements PCI PCI X PCI EXPRESS and PCIe are registered trademarks of PCI SIG Warranty and Support All Alpha Data products enjoy parts and labour warranty for 12 months after purchase The warranty is based on the customer returning the defective goods to Alpha Data for repair or replacement which will be at the discretion of the company The warranty does not cover damages caused by negligence misuse and normal wear and tear No liability is
6. C Primary Connector u een innen 3 10 3 12 P11 P21 P12 P22 PMC Connectors eaeessessesnssnsenssnssssnsennsenseeseensennnnnnnnnnnnnnnnnnnnnnnnnnn 3 10 3 13 P13 P23 P14 P24 PME Connectors c 6 28 avivascac cesta coanccaaseaastcacceatiassastscsavcdsetaanas 3 11 Revision Hist ty tide annee initie sen Dunn 3 12 ADC EMC User Manual 1 Introduction 1 1 1 2 About the Hardware The ADC EMC is a full length PCI Express card designed to carry two PCI Mezzanine Cards PMC or Switched Mezzanine Cards XMC It can be used in x1 x2 x4 and x8 PCle signalling environments installed in x8 or x16 PCle slots There are two PMC slots on the card which support 32 or 64 bit operation on independent PCI PCI X busses The secondary bus VIO is configured for 3 3V operation and a key pin prevents 5V signalling devices from being installed The board has many configurations for XMC support The high speed serial lanes of two XMC cards can be connected for inter XMC communication can route to the PCI express bridge for host communication and can route to a Samtec QS DP connector for intra carrier card communication The ADC EMC carrier card also supports features of Alpha Data FPGA boards in a PCI environment with the provision of Pn4 routing between the two PMC sites and selectively to a 64 way header The secondary bus interfaces are rated at up to 133MHz operation in PCI X mode The primary PCIe interfaces are rated for Gen at 2
7. ECT LANES 2 3 CONNECT LANES TO BRIDGE CONNECT LANES J15 J25 SW1 5 XMC MUX SELECT LANES 4 5 CONNECT LANES TO HEADER CONNECT LANES J15 J25 SW1 6 XMC MUX SELECT LANES 6 7 CONNECT LANES TO HEADER CONNECT LANES J15 J25 SW1 7 XMC1 ROOT COMPLEX ENABLE DISABLE SWI 8 XMC2 ROOT COMPLEX ENABLE DISABLE SW2 1 JTAG CARRIER DEBUG BYPASS CARRIER 8525 amp 8114 INCLUDE IN JTAG CHAIN SW2 2 JTAG PMC1 DEBUG BYPASS PMC JTAG HEADER INCLUDE IN JTAG CHAIN SW2 3 JTAG PMC2 DEBUG BYPASS PMC2 JTAG HEADER INCLUDE IN JTAG CHAIN SW2 4 80 PIN HEADER J5 ENABLE CONNECT BUSSED Jn4 SIGNALS HEADER UNCONNECTED SW2 5 PMC1 J14 BUS CONNECT CONNECT LOWER 32 BITS UNCONNECTED SW2 6 PMC1 J14 BUS CONNECT CONNECT UPPER 32 BITS UNCONNECTED SW2 7 PMC2 J24 BUS CONNECT CONNECT LOWER 32 BITS UNCONNECTED SW2 8 PMC2 J24 BUS CONNECT CONNECT UPPER 32 BITS UNCONNECTED Note Switch controls the corresponding lanes of both XMC sites Note Root signal is used in PCI express mode to enable a processor XMC root features bus enumeration It also the carrier card to propagate the XMC Reset MRSTOn to both XMC sites MRSTIn 3 2 JP1 enables JP1 is connected to the PortEN signal of the CPLD It is used at the factory to configure the device and should and should only be installed in manufacturing as changes to this device could cause system failure 3 3 JP4 JP4 should be left installed unless the system uses separate power supplies for the PCle
8. Figure 4 JTAG Routing 1 3 ADC EMC User Manual 2 Installation 2 1 2 2 2 3 In order to ensure that the board operates correctly first time please read these instructions completely before attempting installation It will also help you to read the whole manual first so that you know how you want the board to be set up The installation instructions for your PC should be followed at all times Into a PC The ADC EMC can be installed in any x8 or x16 PCIe host connector Adding PMC XMC cards Fit any PMC modules that are required If only one PMC module is to be fitted either site can be used PMC site 1 is positioned so that an I O connector on the module aligns with the aperture in the ADC EMC s edge panel The PMC modules should be supplied with mounting kits which normally include spacers nuts bolts and washers Figure 1 shows the typical assembly of a PMC to the ADC EMC It is recommended that washers be used on both sides of the ADC EMC to avoid damage to the PCB Figure 5 Assembly of a PMC to the ADC EMC Software Support The ADC EMC uses transparent bridge devices that are compatible with most operating systems that adhere to the PCI Bios specification No software is required to enable operation of the ADC EMC Configuration of the 8525 switch is by a dedicated pre programmed SPI EEPROM on the ADC EMC Configuration of each of the 8114 bridges is also by individual dedicated pre programmed SPI EEPROMs Th
9. I Express 3 12 P11 P21 P12 P22 PMC Connectors A B C D E F 01 DP00 DP00 3 3V DP01 DPOI1 VPWR 02 GND GND NC GND GND MRSTI 03 DP02 DP02 3 3V DP03 DP03 VPWR 04 GND GND NC GND GND MRSTO 05 DP04 DP04 3 3V DP05 DP05 VPWR 06 GND GND NC GND GND 12V 07 DP06 DP06 3 3V DP07 DP07 VPWR 08 GND GND NC GND GND 12V 09 NC NC NC NC NC VPWR 10 GND GND NC GND GND GAO 11 DP10 DP10 NC DP11 DP11 VPWR 12 GND GND GAI GND GND MPRESENT 13 DP12 DP12 NC DP13 DP13 VPWR 14 GND GND GA2 GND GND MSDA 15 DP14 DP14 NC DP15 DP15 VPWR 16 GND GND MVMRO GND GND MSCL 17 DP16 DP16 NC DP17 DP17 NC 18 GND GND NC GND GND NC 19 REFCLK REFCLK NC PCIE_WAKE PCIE_ROOT NC Notes VPWR 5 0V Pn1 Jn1 32 Bit PCI Pn2 Jn2 32 Bit PCI Pin Signal Signal Signal Signal Pin 1 TCK 12V 12V TRST 2 3 Ground INTA TMS TDO 4 5 INTB INTCH 6 TDI Ground 6 7 BUSMODE1 5V 8 Ground NC 8 9 INTD NC NC NC 10 11 Ground NC BUSMODE2 3 3V 12 13 CLK Ground RST BUSMODE3 14 15 Ground GNT 3 3V BUSMODE4 16 17 REQ 5V PME Ground 18 19 Vd O ADI31 ADI30 AD 29 20 21 AD 28 AD 27 Ground AD 26 22 23 AD 25 Ground AD 24 3 3V 24 25 Ground C BE 3 IDSEL AD 23 26 27 AD 22 AD 21 3 3V AD 20 28 29 AD 19 5V AD 18 Ground 30 31
10. accepted by the company for any damage caused by the use of its hardware or software All goods from Alpha Data carry a 6 months free support service This service is available by letter phone fax and email Technical support contracts for longer periods are available on request Support contracts for software components also normally cover the cost of upgrades ADC EMC User Manual Table of Contents f Introducido 1 1 1 1 About the Hard Wat ui na A a 1 1 1 2 Board Architecture Description ss 1 1 1 3 B atd Clocking sran nets Retenir tir ie een dean nera 1 2 1 4 JTAG Deb sging sun ap nn 1 3 2 Installation een een ns ste ae lade 2 4 2 1 A Re Eo A oe 2 4 2 2 Adding PMC XME cards sachen E a Ai 2 4 2 3 Software SUpport a a eaa ibn Bun nn nn nt seine 2 4 2 4 Power Considerations ini ibi 2 5 3 Hardware Information occccccccccnccnnnnnnnnonnnnnnnnnnnnconcnnnnnncnnnnnonnnnnonnnnnonnn ono nan ennrnncnnnnnnnnnnnnnanoninonons 3 6 3 1 SWITCHES acre avieedsvectagea sees 3 6 3 2 RN 3 6 3 3 N A EEE E E NR 3 6 3 4 J1 JTAG Connector eeeeeeseeseeeseessessesnnnnnnnnnnnnnnnnnnnnnnnnnnennnesenennnnnnnnnnnnnnnnnennnnennnenneennnnn 3 6 3 5 J2 J3 Samtec QSE DP Connector sus 3 7 3 6 J4 Disk Power Connect aan ih 3 7 3 7 116 4 117 ITAG Headers csi a bos 3 7 3 8 MLS LE Headers nia gan en an ne di dis ee 3 7 3 9 Board LEDS lt a as 3 7 3 10 JS Header Configuration euer ragen 3 8 3 11 P157P25 XM
11. bled if the plug in card is not present 1 2 ADC EMC User Manual 1 4 JTAG Debugging The ADC EMC features a versatile JTAG debugging chain that has selectable routing to the carrier card devices and either of the PMC JTAG headers The main JTAG connector J1 connects to a Xilinx Parallel IV or Xilinx Platform Cable USB using the IDC ribbon cable provided with these devices There are 2 JTAG headers J16 and J17 which allow connections to the PMC XMC cards JTAG chains by using flying leads which are available from Xilinx The I O voltage of the JTAG header signals is controlled by the VCC signal from the PMC and is supported from 2 5V to 5 0V There are 3 switches on the ADC EMC that control the routing of the JTAG chain When the corresponding switch is closed the devices will automatically be inserted into the JTAG chain in the following order SW2 1 will include the PEX8525 and both PEX8114 devices in the chain SW2 2 will include the PMC1 header in the chain and SW2 3 will include the PMC2 header in the chain When the corresponding switch is open the JTAG signals will be set in an idle state and the JTAG chain routed around them The PMC JTAG headers have an auto detect feature that will remove them from the JTAG chain if the header is not connected Note Routing is also included for JTAG connections to each PMC via the PMC connectors and can be enabled with a firmware change from the factory
12. e 8525 switch can also be controlled via a dedicated PC connection available via a header for debug purposes ADC EMC User Manual 2 4 Power Considerations The ADC EMC is designed to support standard PMC or PMC XMC format boards These cards are usually specified to consume a maximum of 7 5W each and these together with the background power consumed by the ADC EMC amount to around 22W within the budget of a typical PCI Express slot x16 x8 The ADC EMC can operate using the power provided by the PCI Express edge connector if the PMC XMC cards will require less than 19W total Where additional power is required a disk drive type connector is provided to allow a controlled connection to the system power supply to source and additional 24W 12V at up to 2 0A A protection mechanism will prevent the board from exceeding the current limit of the PCIe connector by more than 50 A red LED will illuminate and the 12V power will be removed automatically if this condition is reached This indicates the auxiliary disk power connector must also be used This protection mechanism is set at a higher limit than the recommended maximum so care should be taken to ensure the board has adequate power supplied The ADC EMC seamlessly controls the two sources of 12V power and will not allow current to flow from one source back to the other when jumper JP4 is removed The PMC XMC cards are supplied with 12V 12V 5V and 3 3V power rails Figure 6
13. ed to Pn4 1 and Pn4 3 The pairing on this connector is consistent with the heritage ADC PMC board and the routing from Pn4 is updated for the new pairing system on the ADM XRC 4FX and later PMC boards J5 2 80 1 79 gnd 1 2 gnd gnd 3 4 gnd gnd 5 6 gnd gnd 7 8 gnd gnd 9 10 gnd Pn4 1 11 12 Pn4 3 Pn4 2 13 14 Pn4 4 Pn4 5 15 16 Pn4 7 Pn4 6 17 18 Pn4 8 Pn4 9 19 20 Pn4 11 Pn4 10 21 22 Pn4 12 Pn4 13 23 24 Pn4 15 Pn4 14 25 26 Pn4 16 Pn4 17 27 28 Pn4 19 Pn4 18 29 30 Pn4 20 Pn4 21 31 32 Pn4 23 Pn4 22 33 34 Pn4 24 Pn4 25 35 36 Pn4 27 Pn4 26 37 38 Pn4 28 Pn4 29 39 40 Pn4 31 Pn4 30 41 42 Pn4 32 Pn4 33 43 44 Pn4 35 Pn4 34 45 46 Pn4 36 Pn4 37 47 48 Pn4 39 Pn4 38 49 50 Pn4 40 Pn4 41 51 52 Pn4 43 Pn4 42 53 54 Pn4 44 Pn4 45 55 56 Pn4 47 Pn4 46 57 58 Pn4 48 Pn4 49 59 60 Pn4 51 Pn4 50 61 62 Pn4 52 Pn4 53 63 64 Pn4 55 Pn4 54 65 66 Pn4 56 Pn4 57 67 68 Pn4 59 Pn4 58 69 70 Pn4 60 Pn4 61 71 72 Pn4 63 Pn4 62 73 74 Pn4 64 gnd 75 76 gnd gnd H 78 gnd gnd 79 80 gnd 3 8 ADC EMC User Manual 3 9 ADC EMC User Manual 3 11 P15 P25 XMC Primary Connector JTAG Connections pulled high to inactive state and TDI is connected to TDO For signal definitions see VITA42 0 VITA42 2 Serial Rapid IO or VITA42 3 PC
14. led O CO NI OD Mn BY N TMS Pin Function SDA GND GPO General Purpose Output of PEX8525 VCC 3 3V Fused Un BY WR RD SCL The 1 10 inch header can be used to access the internal registers of the PEX8525 at I2C bus address 0x58 The I2C bus is also routed to the XMC connectors J15 and J16 with I2C channel select addresses of 0x00 and 0x01 respectively The ADC EMC board has the necessary pull ups for I2C communication 3 9 Board LEDs Reference Color Function D1 Green PCle PCI Bridge PMC2 Port Good D2 Green PCIe PCI Bridge PMC1 Port Good D3 Green PCle Host Port Good 3 7 ADC EMC User Manual D4 Green 3V3 Power OK Indicator D5 Green XMC2 PCIe Port Good D6 Green XMC1 PCIe Port Good D7 Green 12V Power OK Indicator D8 Red PCIe 12V Supply Limit Exceeded 3 10 J5 Header Configuration The IO header JS is suitable for mating with IDC connectors and is a RN P50E 080 P1 SRI TG or equivalent The signaling level is dependant on the PMC drivers and the header inputs but is limited to 3 3V in either direction by level shifting circuitry on the ADC EMC carrier card The IO header is optimised for LVDS pairing to ADM XRC 4FX and later mezzanine card connections All odd number J5 header signals are P with even numbers being N For example J5 11 and J5 12 are a P N pair connect
15. shows the maximum power limit on each supply rail to the combined load of both PMC XMC cards The system must not exceed any of these limits in the given configuration The total power provided to the PMC XMC cards must not exceed 19W or 43W if the disk power connector is supplied Using External Power PMC Power Limits Connector PCIe Power Only Total available for both PMC Sites 43W 19W 12V Rail available power 43W 19W 12V Rail available power 18W 18W 5V Rail available power 28W 19W 3 3V Rail available power 25W 19W Figure 6 Power Supply Limits Disk power H 12V gt 12V _ Pwr or Be 12Ve 5 Mux L_45y _N _ pmc2 12V gt psu _ 1 0V gt pex 3V3 15V 3 MER seq 3 3v bridges X8 PCle Primary Figure 7 Power Supply Diagram 2 5 ADC EMC User Manual 3 Hardware Information 3 1 Switches There are 16 switches on the board that are used for configuration settings SWITCH FUNCTION CLOSED ON OPEN OFF SWI 1 XMC1 NVM WRITE PROHIBIT ALLOW NON VOLITILE MEM WRITES PROHIBIT SW1 2 XMC2 NVM WRITE PROHIBIT ALLOW NON VOLITILE MEM WRITES PROHIBIT SW1 3 XMC MUX SELECT LANES 0 1 CONNECT LANES TO BRIDGE CONNECT LANES J15 J25 SWI 4 XMC MUX SEL
16. vwo AD 17 AD 16 C BE 2 32 33 FRAME Ground Ground IDSELB 34 35 Ground IRDY TRDY 3 3V 36 37 DEVSEL 5V Ground STOP 38 39 PCIXCAP LOCK PERR Ground 40 41 NC NC 3 3V SERR 42 43 PAR Ground C BE 1 Ground 44 45 vo AD 15 AD 14 AD 13 46 47 AD 12 ADI11 M66EN AD 10 48 49 AD 09 5V AD 08 3 3V 50 51 Ground C BEIO AD 07 REQB 52 53 AD 06 AD 05 3 3V GNTB 54 55 AD 04 Ground NC Ground 56 57 WO AD 03 NC NC 58 59 AD 02 AD 01 Ground NC 60 61 AD 00 5V ACK64 3 3V 62 63 Ground REQ64 64 Ground MONARCH 64 Notes V VO 3 3V For signal definitions see IEEE Std 1386 2001 3 10 ADC EMC User Manual 3 13 P13 P23 P14 P24 PMC Connectors Pn3 Jn3 64 Bit PCI Pn4 Jn4 User Defined O Pin Signal Signal Pin Pin Signal Signal Pin 1 NC Ground 2 1 VO VO 2 3 Ground C BE 7 4 3 VO VO 4 5 C BE 6 C BE 5 6 5 VO VO 6 T C BE 4 Ground 8 7 VO VO 8 9 VO PAR64 10 9 VO VO 10 11 AD 63 AD 62 12 11 VO VO 12 13 AD 61 Ground 14 13 VO VO 14 15 Ground AD 60 16 15 VO VO 16 17 AD 59 AD 58 18 17 VO VO 18 19 AD 57 Ground 20 19 VO VO 20 21 V O AD 56 22 21 VO VO 22 23 AD 55 AD 54 24 23 VO VO 24 25 AD 53 Ground 26 23 VO VO 26 27 Ground AD 52 28 27 VO VO 28 29 AD 51 ADI50 30 29 VO VO
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