AN-835 (Rev. A)
Contents
1. WENZEL XTAL ROHDE amp SCHWARZ DIFFERENTIAL ENCODE ARS AGILENT OR Q INPUT SINGLE ENDED ADC FIFO BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR e PC USB 1OPTIONAL TO IMPROVE PERFORMANCE NOTES 1 AINLEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog Figure 14 Two Tone Test Setup Rev A Page 13 of 28 05941 013 NOISE POWER RATIO NPR dB NPR is a dynamic test that is used to assess the performance of converters with a fully loaded Gaussian noise source The noise level is adjusted such that the converter is loaded just below the point of clipping with a Nyquist limited noise source Then a narrow band of noise is removed with a deep notch filter The noise within the notch is measured using FFT techniques NPR dB to determine the ratio of noise density in the notch to the noise density without the notch The results are expressed in decibels NPR is optimized just prior to clipping as shown in Figure 15 When clipping begins NPR falls off rapidly as the input signal is increased If the input signal i2. Jon 295 73 082 mae E NN woso 302 co 3 1 gt 30 5 Ba Fleguercy MHz 05941 008 Figure 8 AD9445 with Analog IF of 130 MHz 1 0 dBFS using Wenzel Clock SNR 75 2 dBFS Data Date 11 30 2005 Time 10 10 27 Temp 25 C Jog Dever 0 De p Encode 125 ware loss 5005 MH sam fenn zas ul SINAD 33 95 ant anas Fund 1 073 dps 3747 abe lan 2058 te Jon ar a awas lusor nas fmo sawe na erae Re 05941 009 Figure 9 AD9445 with Analog IF of 130 MHz 1 0 dBFS using a CMOS Clock SNR 71 2 dBFS When clock sources are not available with the desired jitter performance it is possible to divide a higher frequency clock into lower rates This has the effect of reducing the jitter at the rate of 10 log x where x is the division ratio The limitation of this however is the jitter of the gates themselves The AN 501 Application Note provides an indication of the clock jitter associated with various logic families see www analog com Rev A Page 7 of 28 When custom clocking is desired a PLL is often required A PLL allows the ADC to be synchronized to an external clock reference using a VCO or VCXO However it is difficult to clock more than one device using a simple PLL but adding delays between the devices can facili
3. 10 Harmonic Image dBc ee 10 Two Tone 12 EIZEE2 ABO ns RE Eee 12 E2 EE dBe eee rete ete eie eee ient ied 12 Second Order Input Intercept Point IIP2 dBm 12 2F1 F2 and 2F2 Fl dBe u a see 12 Third Order Input Intercept Point IIP3 dBm 12 Worst Other Spur WoSpur 12 Two Tone SFDR ABC R 12 Noise Power Ratio NPR dB 14 Full Power Bandwidth MHZ esee 15 References Dither Testing Joe aha ua aus 16 Analog Input eue venae 17 Analog Input Impedance see 17 Voltage Standing Wave Ratio 17 Analog Input Full Scale Range V p p 18 Common Mode Input Range V se 19 Common Mode Rejection Ratio CMRR dB Aperture Delay AD ps a 20 Aperture Jitter or Aperture Uncertainty ps RMS 21 Crosstalke dB 3 iacit o E C ERREUR 21 Condition One eR RR EM 21 Condition eed teet ire 21 Input Referred Noise LSB RMS sss 21 Out of Range Recovery Time CLK Cycles 21 Digital Time Domain eere 21 Minimum Conversion Rate MSPS 21 Maximum Conve
4. SCHWARZ ANALOG MICROWAVE WENZEL XTAL ROHDE amp SCHWARZ DIFFERENTIAL AGILENT R ENCODE SINGLE ENDED O INPUT SUPPLY STANDARDIZED 6V TO 9V O O input OR LAB SUPPLIES AD92xx AD94xx OR AD66xx COMMON MODE REJECTION RATIO CMRR dB The CMRR is defined as the amount of rejection on the differential analog inputs when a common signal is applied Typically it is expressed in decibels and can be calculated as follows Api FFERENTIAL CMRR 20 log COMMON MODE Simply tie the two analog inputs together provide a common mode bias on the analog inputs if needed and inject an input signal near full scale of the converter To calculate CMRR simple record the fundamental spur level dB on the FFT display to collect the Acommon number To collect the ApIrFFERENTIAL number simply record the analog input level applied at the inputs of the converter in dB This measurement is then repeated over several frequencies or over the band of interest 1dB PAD C TTE OR K amp L MICROWAVE LPF1 ANALOG INPUT ADC FIFO BOARD SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V MONITOR 1008 Tine T1937 Yap 29 1OPTIONAL TO IMPROVE PERFORMANCE NOTES OR LAB SUPPLIES PC USB 1 AINLEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED
5. ADC applications Additionally they are available in a variety of voltages and can source up to 1 A For more information on designing power supplies for high speed ADCs see the CN0135 Circuit Note and the CN0137 Circuit Note at www analog com VINO IN 05941 011 Figure 11 ADP3338 ADP3339Typical Application ADP1706ARDZ 1 8 R7 U700 PWR IN3 DUT AVDD1 05941 031 Figure 12 ADP1706 ADP1707 ADP1708Typical Application DATA ACQUISITION Data acquisition and processing is accomplished with high speed caching memory Data is collected at full ADC speed or can be decimated depending on the testing method used Bench testing uses the HSC ADC EVALC evaluation platform no decimation required in conjunction with the VisualAnalog software see the HSC ADC EVALC Evaluation Platform section for more details Typically 16k 32k or 64k FFTs are performed but bench FFTs can be as large as 4M samples When the analog input source is not synchronized with the clock noncoherent sampling a Hanning or Blackman Harris windowing function is typically used For more information see On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform fredric j harris Proceedings on the IEEE Vol 66 No 1 January 1978 Rev A Page 8 of 28 AC TEST DEFINITIONS AC or dynamic tests are typically made with the analog signal at the rated frequency with a signal power of 0 1 dB 0 5 dB or 1 dB below full scale d
6. Noise 2x JB x lt 105NR 20 where V p p is the ADC full scale input range SNR is the full scale SNR performance when driven by a small input signal 12 1 006 LSB rms 1 0 0 8 0 6 0 4 NUMBER OF HITS Millions 0 2 05941 026 N 3 N 2 N 1 N N 1 N 2 N 3 CODE Figure 26 Input Referred Noise Histogram OUT OF RANGE RECOVERY TIME CLK CYCLES It is the time required for the ADC to recover to the rated accuracy after an input transient moves from 10 above positive full scale to 10 above negative full scale or from 10 below negative full scale to 10 below positive full scale DIGITAL TIME DOMAIN Minimum Conversion Rate MSPS The minimum conversion rate is the clock rate at which the SNR of the lowest specified analog signal frequency drops by no more than 3 dB below the guaranteed limit Maximum Conversion Rate MSPS The maximum conversion rate is the clock rate at which parametric testing is performed Higher operating rates are possible but they are not guaranteed Rev A Page 21 of 28 Pipeline Delay CLK Cycles For the general evaluation board setup see Figure 27 Use one channel of an oscilloscope to capture the analog input Use another channel to capture the MSB data bit out Setup the trigger for this channel to capture on the rising edge Use the vertical cursors to measure the amount of delay Pipeline delay is defined as the delta time between the zero crossing of the analog input risin
7. O O input AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR GPIB P USB NOTES 1 AIN LEVELS SHOULD BE ADJUSTED FOR 1dB AT 10MHz 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog 6 BOONTON PROBES SHOULD USE UNTERMINATED ADAPTERS Figure 22 Analog Input Full Scale Range Test Setup 05941 021 Rev A Page 18 of 28 COMMON MODE INPUT RANGE V Common mode input range is the dc offset range that is either applied or supplied to both of the ADC s analog input pins for which the converter will operate within its normal signal range Typically unbuffered converters have to be supplied with a dc common mode bias to operate properly This bias is usually AVDD 2 and can be set with an external voltage divider or the VCM CML pin provided by the converter Buffered converters have an internal buffer and typically provide the common mode AVDD 2 0 7 V directly on the analog input pins without any other hardware necessary to provide this bias Every converter has an optimum range in which it can operate and provide excellent performance It maybe a limited or a wide range to be certain consult the converter s data sheet OUTPUT WENZEL XTAL 1dB PAD TTE OR K amp L ROHDE
8. SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog 6 RESISTIVE DIVIDER MAY NOT BE NECESSARY FOR SOME ADCs 05941 022 Figure 23 CMRR Test Setup Rev A Page 19 of 28 APERTURE DELAY AD ps AD is a measure of the difference in the delay between the analog path and the encode path It is measured by observing the time from the 50 point of the rising edge of the sample clock to the time at which the input signal is actually sampled Aperture delay can be measured by using the following test configuration 1 Connect the analog input to an analog filtered source 2 Using a program like VisualAnalog adjust the input until the single tone FFT results in a full scale signal 0 dBFS 3 Disconnect the analog input and use a shorting bar to short the analog input to ground 4 Use a continuous average time domain plot to measure the offset of the part Remove the shorting bar from the analog input and reconnect the analog input as shown in Figure 24 Record the new offset value and use it to solve the following equation lt j Code syerace Offset 2 2m x Frequency tap sin where Codeaverace is the new offset value obtained after removing the shorting bar from the analog input and reconnecting the analog input see Step 5 Offset is the offset of the part measured using a continuous average time doma
9. clock logic threshold or 50 point for a differential clock input and the time when all bits are within valid logic levels Encode Pulse Width or Encode Duty Cycle Encode pulse width high is the minimum amount of time that the encode signal can be in a logic high state and achieve the specified performance Encode pulse width low is the minimum amount of time that the encode signal can be in logic low state and achieve the specified performance In a traditional ADC when the encode signal is in a logic high state the circuit is in a TEKTRONIX TDS 854C 500MHz OSCILLOSCOPE CH1 CH2 CH3 O WENZEL XTAL ROHDE amp SCHWARZ DIFFERENTIAL ORO Q AGILENT SINGLE ENDED SUPPLY STANDARDIZED 6V TO 9V O INPUT OR LAB SUPPLIES MONITOR sample mode If held in a high state for an insufficient time the sample process fails to complete If held in a low state for an insufficient time the circuit fails to accurately acquire the signal to be sampled Optimal operation is achieved when the acquire and sample times are suitably balanced In many converters the encode duty cycle is provided instead of pulse width measurements This is usually stated for the maximum rated encode and expressed as a range of the percentage of time that the encode line may be in the high state For this test rated performance is defined as the range over which SNRFS performance is within 3 dB of nominal performance WENZE
10. indicated In practice external devices including latching and memory elements make it difficult to measure anything beyond about 2 x 10 6 or 2 x 10 7 Rev A Page 24 of 28 DC TEST DEFINITIONS GAIN ERROR FS It is the difference between the measured full scale and ideal full scale This is usually expressed as a percentage of full scale GAIN MATCHING FS It is the ratio of the maximum full scale to the minimum full scale of a multichannel ADC It is expressed as a percentage of full scale using the following equation FSRvax FSRa FSR 100 2 Gain Matching where FSRuax is the most positive gain error of the ADC is the most negative gain error OFFSET ERROR FS It is the difference between the measured and ideal voltage at the analog input that produces the midscale code at the output This is usually expressed as a percentage of full scale OFFSET MATCHING mV It is the difference in offsets expressed in millivolts between the channels of a multichannel converter It is computed with the following equation Offset Matching VOFFSETmax VOFFSETum where VOFFSETuwax is the most positive offset error VOFFSETum is the most negative offset error Offset matching is usually expressed in millivolts with the full scale input range stated in the product data sheet TEMPERATURE DRIFT ppm The temperature drifts for offset error and gain error specify the
11. which is the desired signal referenced to the carrier or in dBFS which is the desired signal referenced to the full scale of the converter Either unit can be converted to the other by adding or subtracting the level of the carrier from full scale For more information about FFT testing see The FFT Fundamentals and Concepts Tektronix Inc 070 1754 00 Production Group 45 first printing December 1975 SINGLE TONE FFT Signal to Noise Ratio SNR dB The SNR is the ratio of the rms signal amplitude to the rms value of the sum of all spectral components except the first six harmonics and As the input level is decreased SNR typically decreases decibel for decibel in a linear fashion Signal to Noise Ratio Referenced to Full Scale SNRFS dBFS The SNRES is the ratio of the rms full scale to the rms value of the sum of all spectral components except the first six harmonics and dc SNRFS is expressed in decibels referenced to full scale dBFS The difference between SNR and SNRES is the difference between the fundamental amplitude and full scale Signal to Noise and Distortion SINAD dB The SINAD is the ratio of the rms signal amplitude to the rms value of the sum of all spectral components including harmonics but excluding dc The difference between SNR and SINAD is the energy contained in the first six harmonics User Defined Signal to Noise Ratio UDSNR dB UDSNR is a term that refers to the ability to se
12. 8 Time PC USB 1OPTIONAL TO IMPROVE PERFORMANCE NOTES 1 AIN LEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog Figure 13 Single Tone Test Setup Rev A Page 11 of 28 05941 012 TWO TONE FFT When multiple tones are passed through a converter with nonlinearities intermodulation distortion products IMD result Two tone testing in an ADC is a means of specifying these nonlinearities Because many of the distortion products may be relatively high in the analog spectrum it is possible that the frequencies have aliased This should be kept in mind when identifying distortion products F1 F2 dBc This term represents the second order distortion product that appears at the frequency and is the sum of the two input fre quencies The measure of this term is the ratio of its rms value to the rms value of one of the two input tones expressed in dBc F2 F1 dBc This term represents the second order distortion product that appears at the frequency and is the difference of the two input frequencies The measure of this term is the ratio of its rms value to the rms value of one of the two input tones expressed in dBc Second Order Input Intercept Po
13. ANALOG AN 835 DEVICES APPLICATION NOTE One Technology Way P O 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com Understanding High Speed ADC Testing and Evaluation by Alex Arrants Brad Brannon and Rob Reeder SCOPE DYNAMIC TEST HARDWARE SETUP This document describes both the characterization and production SNR SINAD worst spur and IMD are tested using a hardware test methods used by the High Speed Converter Group of Analog setup similar to that shown in Figure 1 In production tests the Devices Inc to evaluate high speed analog to digital converters test hardware is highly integrated but the hardware principles ADCs While this application note should be considered a are the same The basic setup for dynamic testing includes a reference it is not a substitute for a product data sheet signal generator band pass filter test fixture low noise power supplies encode source often integrated on the evaluation board data acquisition module and data analysis software Analog Devices provides application hardware and software to aid in bench evaluation WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY SIGNAL SYNTHESIZER Sag 4LO INPUT Le ANALOG INPUT We ts S 4 mF SIGNAL SYNTHESIZER AGILENT ae A s iy E POWER SUPPLY z RUNNING ADC ANALYZER q OPTIONAL c
14. Analog Devices Green Wayne Rob Reeder and Robert Shillito Analog to Digital Converter Clock Optimization A Test Engineering Perspective Analog Dialogue 42 02 February 2008 Hand Jim Mark Looney and Rob Reeder Pushing the State of the Art with Multichannel A D Converters Analog Dialogue 39 05 May 2005 Kessler Walt and Rob Reeder NPR Specification Aids Wireless System Analysis Microwaves amp RF December 2005 Newman Eric and Rob Reeder A Resonant Approach to Interfacing Amplifiers to Switched Capacitor ADCs Microwave Product Digest September 2005 2006 2010 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners AN05941 0 6 10 A ANALOG DEVICES Newman Eric and Rob Reeder 2006 AN 827 Application Note A Resonant Approach to Interfacing Amplifiers to Switched Capacitor ADCs Analog Devices January Reeder Rob Testing an A Ds power supply rejection ratio EE Times July 1 2003 Reeder Rob 2005 2009 AN 742 Application Note Frequency Domain Response of Switched Capacitor ADCs Analog Devices September Reeder Rob Transformer Coupled Front End for Wideband A D Converters Analog Dialogue Volume 39 April 2009 Reeder Rob Compare aperture delay between ADCs Test amp Measurement World May 1 2002 Rob Reeder Wideband A D Converter Front End Design Considerations Ana
15. B Band pass filters are used when analog frequencies are fixed and will not be changed Band pass filters also eliminate much of the wideband noise generated by signal sources and typically provide the best performance for ADC testing Filters such as Q70T series have a bandwidth defined as a percentage of the center frequency The more narrow the bandwidth the less noise that passes through the filter however the analog frequency is more restricted and there is a greater insertion loss When a center frequency is chosen the bandwidth can be determined Ideally a bandwidth of 5 to 6 should be selected keeping in mind that good noise performance is being traded for analog frequency flexibility As with low pass filters the band pass filter has a transition band that defines the shape between the 3 dB frequency above and below the center frequency and the frequency of the guaranteed stop band performance In the case of TTE s Q70T the stop band rejection is 60 dB z lt 2 H 40 60 80 100 120 FREQUENCY MHz 8 Figure 5 Typical Performance of TTE s J97 0 10 IL 100MHz 20 z o hk 30 2 E PNEU 50 60 85 90 95 100 105 110 115 08941 006 FREQUENCY MHz Fi
16. BFS If different amplitudes are used they will be defined in the data sheet test conditions For these tests the encode rate is usually set at or near the maximum rated value The data sheet should be consulted to determine the remainder of the test conditions including power supply and temperature conditions FFT TESTING Both coherent and noncoherent FFT testing can be used depending on the actual test conditions When coherent testing is used the analog frequency is chosen such that the captured data samples exercise as many converter codes as possible in the record length This is accomplished by using a prime relationship between the analog frequency and the encode rate For example if coherent sampling is used and a 10 MHz analog input is desired with a specified sample rate of 65 MSPS the calculated coherent analog input frequency is 10 0015258789063 MHz or exactly 2521 cycles This can be calculated using the following equation J vestrep _ FREQUENCY Sample _ Rate FFT _ Samples Cycles The number of cycles should be rounded to the nearest integer When possible the nearest prime number should be selected to ensure that the maximum number of quantization levels of the converter is exercised When the number of cycles has been selected the previous equation can be solved using the desired analog input frequency FFT testing typically results in measurements expressed in decibels Units can be expressed in dBc
17. Crosstalk is measured in three ways under two conditions Condition One If a signal is driven near full scale crosstalk can be measured by one of the following methods e Drive any two channels using a different midbaseband frequency for each that are at least 2 MHz apart at 0 5 dBFS Record the same fundamental frequency on any open channel nondriven Repeat for all channel combinations e Driveany 1 channel using a single midbaseband frequency at 0 5 dBFS Record the same fundamental frequency on any open channel nondriven Repeat for all channel combinations Condition Two If a signal is driven 3 dB over full scale known as the overdriven condition crosstalk can be measured as follows e Useeither method described in the Condition One section however with a midbaseband frequency amplitude set to 3 dB above full scale results are expressed in decibels as a ratio of the energy of the undesired signal on the quite channel to the energy on the driven channel INPUT REFERRED NOISE LSB RMS It is a measure of the wideband noise generated by the ADC as shown in Figure 26 A histogram of the output codes is created while the input is grounded Input referred noise is calculated using the standard deviation of the histograms and it is presented in terms of LSB rms This measurement can also be correlated using SNRFS measurements and converting decibels to volts using the following equation Vp p
18. Currently ADIsimADC is supported by MATLAB C National Instruments LabVIEW SignalExpress Agilent s ADS and Applied Wave Research s Visual System Stimulatior Others will be available in the future The tool can be downloaded from the website along with a complete collection of current models Links are provided to third party tools that support ADIsimADC For more information on ADIsimADC behavioral modeling visit www analog com ADIsimADC For more detailed information on ADIsimADOC see the AN 737 Application Note at www analog com Figure 4 VisualAnalog Typical Canvas Showing an FFT and Time Domain Rev A Page 5 of 28 lc dt te eli re e HESS Perte FFT are rata en ee GSS 3 mal u gt z wo wo mo n we 12000 100 Performance Plots 05941 004 ANALOG SIGNAL SOURCE Usually dynamic testing employs a Rohde amp Schwarz SMA SMHU SMG SMGU an Agilent 8644 signal generator a Wenzel crystal oscillators or a Valpey Fisher crystal oscillator These sources have proven to provide exceptional performance low phase noise flat frequency response and reasonable harmonic performance for frequencies of a few kilohertz to those of a few gigahertz Harmonic performance of these generators is typically not as good as the intrinsic linearity of a given ADC mandating the need for additio
19. L XTAL ROHDE amp SCHWARZ AGILENT ANALOG 5 OUTPUT ANALOG ADC FIFO BOARD AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES SW Due 1130 NOTES 1 AIN SHOULD BE SET TO A LOW FREQUENCY FULL SCALE SIGNAL 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE REVS ON EVALUATION BOARD AND PARTS AS NOTED 6 ALL OSCILLOSCOPE PROBES SHOULD BE SOLDERED DOWN AND GROUNDED 7 TEKTRONIX PROBES M N P6243 OR BETTER SHOULD BE USED lt 1pF WITH 1GHz BW 05941 025 Figure 28 Propagation Delay Test Setup Rev A Page 23 of 28 CONVERSION ERROR RATE CER The conversion error rate CER is a measurement of the frequency of errors generated by the ADC An error is defined as output codes that fall outside the bounds of converter noise in excess of that allowed by normally distributed noise Converter noise is defined as the noise normally generated by quantization thermal effects and clock jitter and is generally considered Gaussian However converter noise and errors are actually binomially distributed and can be estimated from a normal distribution using the half integer corrections for the continuity formula lt lt A sample is considered to be an error if the frequency of occurre
20. LE ENDED STANDARDIZED 6V TO 9V OR LAB SUPPLIES NOTES 1 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 2 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 3 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 4 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog 5 CALIBRATE NETWORK ANALYZER 3 5mm CALIBRATION KIT PART NO 85033C OR EQUIVALENT The amount of power reflected back from the device can be computed from the input impedance based on the following equation Zw Zo Zn 20 where p is the amount of power reflected back from the device Zin is the complex input impedance of the ADC Zois the desired impedance of the network From the reflection coefficient the VSWR can be calculated by using the following equation 1 VSWR 1 p ENCODE ANALOG INPUT AD92xx AD94xx OR AD66xx EVALUATION BOARD 05941 020 Figure 21 Analog Input Impedance and VSWR Test Setup Rev A Page 17 of 28 ANALOG INPUT FULL SCALE RANGE V Analog input full scale range is the range of peak to peak voltage either single ended or differential that can be applied to the analog input s of the converter to generate a valid full scale response ROHDE amp SCHWARZ AGILENT ANALOG ANALOG BOONTON 7 ee WENZEL XTAL ROHDE amp SCHWARZ DIFFERENTIAL dc ENCODE A AGILENT SINGLE ENDS INPUT ADC FIFO BOARD TANDARDIZED 6V TO 9V STANDARDIZED 6V TO 9
21. de Signal Sources 7 Changes to Figure 10 Power Supplies Section Figure 11 and Data Acquisition Section kir r E 8 Added Figure 12 Renumbered Sequentially 8 Changes to User Defined Signal to Noise Ratio UDSNR dB Section and Noise Figure NF dB Section 9 Changes to Noise Floor dBFS Section and Effective Number of Bits ENOB Bits Section 10 Changes to Figure 13 Changes to Figure 14 Changes to Figure 17 ii 14 Changes to Figure 19 15 Changes to Dither Testing and Figure 20 sss 16 Changes to Figure 21 a ttr ern 17 Changesito Figure 22 ieee Anges 18 Changes to Common Mode Input Range V Section Common Mode Rejection Ratio CMRR dB Section and Figure 23 19 Changes to Aperture Delay AD ps Section and Figure 24 20 Changes to Input Referred Noise LSB RMS Section 21 Added Figur 261222 reme entro greet haee 21 Changes to Pipeline Delay CLK Cycles Section 22 Added Figure 27 eter eet i a uta 22 Changes to Figure 28 4 23 Changes to Conversion Error Rate CES Section and prio 24 Added Figure 29i ete aep ies 24 Changes to References Section sse 28 4 06 Revision 0 In
22. e amount of a signal on the power supply that is coupled to the digital output of the ADC It can be measured by changing the power supply and then measuring the change in offset of the converter by ADC in volts minus the input value measured by the oscilloscope expressed in decibels WENZEL XTAL ROHDE amp SCHWARZ ENCODE ANALOG AGILENT O O INPUT ADC FIFO BOARD SINGLE ENDED TEKTRONIX SOOM S NII gt ih n UPPLY 500MHz OSCILLOSCOPE O INPUT AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT SIGNAL GENERATOR ANALOG 5 HP33120A OUTPUT STANDARDIZED 6V TO 9V 100 1000 OR LAB SUPPLIES 3300 NONPOLARIZED LAB SUPPLIES O 1mH 10mH 100mH MONITOR SW Ba e YN Te TEC taw AT PC USB NOTES 1 ALL BYPASS CAPACITORS AND FERRITE BEADS SHOULD BE REMOVED FROM THE EVALUATION BOARD 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 THE VALUE OF R IS RELATED TO THE SOURCE IMPEDANCE OF THE END POWER SUPPLIES 4 THE SIGNAL MEASURED BY THE OSCILLOSCOPE IS COMPARED TO THE FFT OUTPUT TO DETERMINE THE PSRR 5 TEKTRONIX PROBES M N P6243 OR BETTER SHOULD BE USED 1pF WITH 1GHz BW Figure 33 PSRR Test Setup 05941 030 Rev A Page 27 of 28 REFERENCES Additional information on data converter characterization can be found in The Data Conversion Handbook by Walt Kester Newness ISBN 0 7506 7841 0 Additional reference books including the Hi
23. ewa OR VISUAL ANALOG USER SOFTWARE CLOCK OUTPUTS SPECTRUM INPUT ANALYZER OSCILLOSCOPE at STE ao GAIN CONTROL o 1 1 T 2 INPUT SIGNAL Sx j SYNTHESIZER 1 x 05941 001 Figure 1 Typical Characterization Test Setup Rev A Page 1 of 28 TABLE OF CONTENTS SCOPE MR M M 1 Dynamic Test Hardware Setup sse 1 Revision HIStOLY P M 3 HSC ADC EVALC Evaluation Platform 4 Back rounid sasari A 5 ADIsimADC Analog Signal Source Analog Signal Filter tret Encode Signal Sources seen 7 Power Supplies cia ettari rab ipia 8 DatazACquisitiorts se PUE RIEN 8 AC T stDefinitionsz oir e Rn ee T 9 FET Testihgiucusaeuesenucsaaienenien eet dE nda 9 Single Tone FET eit tiii ORDER ee HUE 9 Signal to Noise Ratio SNR dB sss 9 Signal to Noise Ratio Referenced to Full Scale SNRES BES E OR IU RE 9 Signal to Noise and Distortion SINAD dB 9 User Defined Signal to Noise Ratio UDSNR dB 9 Noise Figure NE dB qayqa asa 9 Noise Floor dBFS 10 Effective Number of Bits ENOB Bits 10 Spurious Free Dynamic Range SFDR dBc 10 Harmonic Distortion dBc or dBFS 10 Total Harmonic Distortion THD dBc
24. g edge and the 50 MSB data bit rising edge Take the delta time found and divide it by 1 sample frequency to determine the pipeline delay It is the delay through the converter as a function of the encode cycles To maximize throughput many high speed converters leverage pipeline processing As a result the corresponding data is not output until several clock cycles after the signal is sampled This delay is the pipeline delay and can be expressed as whole or fractional clock cycles depending on the data converter suman T CH1 CH2 AGILENT O RONDE amp SCHWARZ DIFFERENTIAL ANALOG AGILENT OR O INPUT SINGLE ENDED ADC FIFO BOARD STANDARDIZED 6V TO 9V OR LAB SUPPLIES AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR Due 12730 2208 Time FTW Tome 25 NOTES AIN SHOULD BE SET TO A LOW FREQUENCY FULL SCALE SIGNAL ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED USE THE APPROPRIATE REVS ON EVALUATION BOARD AND PARTS AS NOTED ALL OSCILLOSCOPE PROBES SHOULD BE SOLDERED DOWN AND GROUNDED TEKTRONIX PROBES M N P6243 OR BETTER SHOULD BE USED 1pF WITH 1GHz BW NOmRONLI 05941 032 Figure 27 Pipeline Delay Test Setup Rev A Page 22 of 28 Propagation Delay ns Propagation delay is the delay between the
25. gh Speed Design Techniques the Practical Analog Design Techniques the Linear Design Seminar and the System Applications Guide can be found at www analog com In addition to the many reference books various applications notes articles and reprints are available from your Analog Devices sales representative or you can visit our website at www analog com for additional information ADDITIONAL REFERENCES Brannon Brad 1995 AN 410 Application Note Overcoming Converter Nonlinearities with Dither Analog Devices December Brannon Brad 2004 AN 756 Application Note Sampled Systems and the Effect of Clock Phase Noise and Jitter Analog Devices December Brannon Brad and Allen Barlow 2006 AN 501 Application Note Aperture Uncertainty and ADC System Performance Analog Devices March Brannon Brad and Tom MacLeod 2009 AN 737 Application Note How ADIsimADC Models an ADC Analog Devices April Caserta Jim and Rob Reeder Ask The Application Engineer 36 Wideband A D Converter Front End Design Considerations II Amplifier or Transformer Drive for the Analog Dialogue Volume 41 February 2007 Cobb Michael and Rob Reeder June 2009 Webcast Designing with Switching Regulators in High Speed A D Converter Applications Analog Devices and Avnet Electronics Marketing Downing Salina and Rob Reeder April 2006 Webcast Designing Transformer Coupled Front Ends for High Performance A D Converters
26. gure 6 Typical Band Pass Performance of TTE s Q70T As noted previously band pass filters may only have a stop band rejection of 60 dB meaning that signals that fall into the stop band will be rejected by 60 dB If for example a signal source has a harmonic that is 25 dB below the fundamental the effective level of the harmonic is 85 dBc after a Q70T filter For many high performance ADCs this is not sufficient When performance of 100 dBc or better is required it is common to cascade band pass filter with a low pass filter When selecting a low pass filter to follow a band pass filter the low pass frequency should be selected such that stop band performance of the low pass filter optimally filters any harmonics that pass through the band pass filter With a J97 low pass filter stop band rejection is reached at 1 2 times the 3 dB frequency If the second harmonic of the band pass filter is set equal to 1 4 times the low pass 3 dB frequency it ensures that all harmonics passing through the band pass filter are filtered and that the additional insertion loss of the low pass filter does not significantly reduce the level of the desired pass band In this case the low pass frequency should equal 1 4 times the band pass frequency and theoretically the cascaded rejection should be about 140 dB Although this is difficult to achieve in practice due to coupling and radiation effects this technique is a useful one and can achieve well bey
27. he rms signal amplitude to the rms value of the specified harmonic component reported in dBc or dBFS Because ADCs are nonlinear devices the output is rich in spectral components The worst spurious energy may not be directly related to the first two harmonics 2HD and 3HD and is measured by the worst other spurious WoSpur WoSpur is the ratio of the rms signal amplitude to the rms value of the worst spurious component excluding the first six harmonically related components it is reported in dBc Total Harmonic Distortion THD dBc THD is the ratio of the rms signal energy to the rms value of the sum of the first six harmonics Harmonic Image dBc The harmonic image measurement result is valid only when analyzing interleaved ADCs This specification does not apply to most ADCs Harmonic image is the ratio of the rms signal amplitude to the rms value of the nonharmonic component generated from the clocking phase difference of two ADCs reported in dBc Rev A Page 10 of 28 RONDE amp SCHWARZ 1dB PAD TTE OR KaL 19B PAD TTE OR K amp L ANALOG AGILENT OUTPUT V CJ MICROWAVE MICROWAVE O WENZEL XTAL ANALOG DIFFERENTIAL ROHDE amp SCHWARZ ENCODE INPUT AGILENT OR 2 0 INPUT ADC FIFO BOARD STANDARDIZED 6V TO 9V SUPPLY SINGLE ENDED OR LAB SUPPLIES INPUT AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR Dae 1251300
28. in plot see Step 4 2 2 is the midscale of an ADC WENZEL XTAL ROHDE amp SCHWARZ ANALOG AGILENT OUTPUT Q TEE SHORTING ADAPTER 89 WENZEL XTAL ANALOG INPUT ADC FIFO BOARD ROHDE amp SCHWARZ en AGILENT O SINGLE ENDED AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR S fei Gas Dae 1135 Tie OF TV Temp 1X EH YY PC en USB NOTES 1 AIN LEVELS SHOULD BE ADJUSTED FOR OdBFS OUTPUT FOR THE INPUT FREQUENCY OF MIDBAND 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog 05941 023 Figure 24 Aperture Delay Test Setup Rev A Page 20 of 28 APERTURE JITTER OR APERTURE UNCERTAINTY ps RMS It is the sample to sample variation in aperture delay that can be manifested as frequency dependent noise on the ADC input Details on measuring aperture jitter can be found in the AN 501 Application Note and details on converting aperture jitter to phase noise can be found in the AN 756 Application Note at www analog com ERROR VOLTAGE ENCODE i dt 05941 024 Figure 25 Aperture Uncertainty CROSSTALK dB It is defined as the measure of any feedthrough coupling onto the quiet channel of a multichannel ADC
29. int IIP2 dBm The IIP2 is the measure of the full scale input signal power of the converter minus the IMD second order products It is reported in dBm 2F1 F2 2F2 dBc These terms represent the third order distortion products of the converter The measure of each term is the ratio of its rms value to the rms value of one of the two input tones expressed dBc The peak spurious component is considered an IMD product Third Order Input Intercept Point IIP3 dBm The IIP3 is the measure of the full scale input signal power of the converter minus half the IMD third order products It is reported in dBm Worst Other Spur WoSpur dBc WoSpur is the worst resulting spurious not related to the second or third order distortion products resulting from mixing two analog input signals The measure of this term is the ratio of its rms value to the rms value of one of the two input tones expressed in dBc Two Tone SFDR dBc The SFDR is the ratio of the rms value of the signal to the rms value of the peak spurious spectral component for the analog input that produces the worst result In most cases SFDR isa harmonic of the input signal applied to the ADC Rev A Page 12 of 28 1dB TO WENZEL XTAL 10dB PAD ROHDE amp SCHWARZ ANALOG TTE OR K amp L AGILENT OUTPUT O MICROWAVE CO COMBINER 1dB TO WENZEL XTAL 10dB PAD ROHDE amp SCHWARZ ANALOG TTE OR K amp L AGILENT OUTPUT MICROWAVE CO
30. itial Version Rev A Page 3 of 28 HSC ADC EVALC EVALUATION PLATFORM The high speed ADC FIFO evaluation kit HSC_ADC_EVALC includes a FPGA based buffer memory board to capture blocks of digital data from Analog Devices high speed ADC evaluation boards VisualAnalog and SPIController software For more information on the HSC ADC EVALC evaluation platform visit www analog com FIFO ON BOARD POWER VOLTAGE SINGLE OR MULTICHANNEL ue CONFIGURATION MODE HIGH SPEED ADC EVALUATION BOARD eum qu J2 HSC ADC EVALC FILTERED DATA CONVERTER I O CONNECTORS CLOCK INPUT The FPGA based buffer memory board be connected to PC through a standard USB cable and used with the Visual Analog and SPIController software to quickly evaluate the performance of the high speed ADCs Users can change settings in the SPI registers unique to the individual ADC product view an FFT for a specific analog input and sample rate and analyze SNR SINAD SFDR and harmonic information as well as time domain information such as gain and offset The HSC ADC EVALC supports CMOS LVDS and CML outputs Some boards may require an interposer or slightly different FIFO alternative If additional or different hardware is necessary it will be specified in the product data sheet For more detailed information on the HSC ADC EVALC the SPIController and how the Visual Analog software works visit www analog c
31. log Dialogue 40 07 July 2006 Reeder Rob 2007 AN 935 Application Note Designing an ADC Transformer Coupled Front End Analog Devices September Reeder Rob 2009 CN 0135 Circuit Note Powering the AD9272 Octal Ultrasound ADC LNA VGA AAF with the ADP5020 Switching Regulator PMU for Increased Efficiency Analog Devices October Reeder Rob Considering the ADC input interface EE Times Europe December 1 2009 Reeder Rob Improve the Design of Your Passive Wideband ADC Front End Network Electronic Design March 26 2010 Rob Reeder Are Your Filter s Filtering EDN Design News February 1 2009 Rob Reeder Keeping Common Modes Common EDN Design News April 1 2009 Rob Reeder What s the Converter Frequency Kenneth Design News July 17 2009 Rob Reeder Bring on the Converter Noise Part 1 Design News October 1 2009 Rob Reeder RAQ Bring on the Converter Noise Part 2 Design News November 23 2009 Rob Reeder RAQ Taming A D Converter Power Supplies Design News March 1 2010 www analog com Rev A Page 28 of 28
32. maximum change from the initial 25 value to the value at Tmn or Tmax This is usually expressed in ppm VOLTAGE OUTPUT HIGH VOLTAGE OUTPUT LOW Vou Vo V Voltage output high Vou is the voltage representing the high logic level Voltage output low Vor is the voltage representing the low logic level DC or static tests are typically made with dc or very low frequency test signals The purpose of these tests is to determine the base line values of many of the core converter specifications Test conditions vary by product therefore the product s data sheet should be consulted to determine actual test conditions LINEARITY There are two types of converter linearity differential nonlinearity DNL and integral nonlinearity INL The basic measure of an ADC is the range of voltages for which each code is active The integration of these voltages determines the overall transfer function of the converter Together these two basic measurements determine the characteristic static performance of the ADC These tests are frequently performed using histogram techniques A histogram is collected by driving the analog input of the ADC with a signal of known statistical qualities For example a dc ramp has the quality of a uniform probability density function This means that when driving an ADC input each ADC code has an equal probability of occurring over a large observation window Other waveforms such as sine waves have known func
33. nal filtering between the signal generator and the analog input to the ADC ANALOG SIGNAL FILTER Both fixed frequency and tunable frequency band pass filters are used for device testing The fixed frequency filters are typically smaller than tunable filters and often provide slightly better performance Tunable filters allow testing across a wide range of frequencies using one filter Several filter manufacturers including K amp L Microwave TTE and Allen Avionics Inc provide excellent filters for ADC testing There are two types of filters that are often used for ADC testing low pass filters and band pass filters These can be used individually or combined to yield the level of performance required for an application Low pass filters are a good choice when a wide range of analog frequencies must be applied to the ADC However they allow noise to pass from the signal generator to the ADC This noise may reduce the level of performance measured for the ADC A typical low pass filter is the J97 available from Usually low pass filters have a transition band that defines where the pass band ends and the stop band begins Along with this specification a guaranteed stop band rejection is specified In the case of the J97 the transition band is defined to be between 1 0 times and 1 2 times the 3 dB frequency and the guaranteed stop band rejection is 80 dB Energy beyond 1 2 times the 3 dB frequency is reduced by a minimum of 80 d
34. nce exceeds that predicted by this distribution 450k 400k NUMBER OF OCCURRENCES N Sra et Te EXPECTED 05941 033 Figure 29 Binomial Distribution 1 Million Samples Noise magnitude is normalized to Sigma o and can be determined by measuring the full scale SNR and then solving the following equation using this value 2N O a o gt 2x 42 x105NR 20 When sigma has been determined based on the expected SNR or from the data sheet a method can be employed to capture data such that the expected ADC code is subtracted from the actual code resulting in a distribution histogram With a statistically large data set it can be expected that for normal ADC noise the resultant distribution will be similar to that shown in Figure 29 For a large distribution excess samples in any of these ranges are an indication of bit errors as shown in Table 1 Table 1 Sigma vs Normal Probability of Occurrence Normal Probability Natural Occurrences Outside of Occurrence in 1 Million Samples 3 58 2x 10 2000 4 22 2x10 200 4 76 2x 10 20 5 25 2x10 2 5 70 2x107 0 2 6 11 2x 10 0 02 6 50 2x10 0 002 6 85 2 10710 0 0002 Note that with a sample rate of 100 MSPS one error outside the 6 85 sigma is normal in a 50 second window and does not constitute a conversion error Only when the rate exceeds 2 x 10 10 isa conversion error
35. ntization level and can result from a variety of causes Most products are designed or screened for no missing codes WENZEL XTAL ROHDE amp SCHWARZ ANALOG AGILENT OUTPUT 1dB PAD 1dB PAD TTE OR K amp L MICROWAVE BPF TTE OR K amp L MICROWAVE LPF WENZEL XTAL ROHDE amp SCHWARz DIFFERENTIAL ORO AGILENT SINGLE ENDED ANALOG ENCODE INPUT INPUT ADC FIFO BOARD STANDARDIZED 6V TO 9V O SUPPLY OR LAB SUPPLIES INPUT AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR OB Bae 1OPTIONAL TO IMPROVE PERFORMANCE NOTES 1 AIN LEVELS SHOULD BE ADJUSTED FOR 0 01dBFS AND ABOUT 2 2MHz 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 CUSTOMER SOFTWARE DOES NOT SUPPORT INL AND DNL TESTING 6 USE APPROPRIATE REVS ON EVALUATION BOARD AND PARTS AS NOTED 05941 029 Figure 32 DNL and INL Test Setup Rev A Page 26 of 28 POWER SUPPLY REJECTION RATIO PSRR dB expressed as a percentage of full scale More typically PSRR is measured by injecting an ac signal of known amplitude on the power supply pins and then measuring the observed spectrum of an FFT PSRR is the difference between the values measured PSRR is a measurement of th
36. ode sources is Valpey Fisher which offers several options including differential PECLs and voltage controlled crystal oscillators VCXOs For less demanding applications standard CMOS clock modules can be used and are available from various manufacturers For end applications that require the clock to be synchronized with an external reference a VCXO in a PLL loop can be employed as found in products like the AD9516 05941 007 Figure 7 Typical Low Cost CMOS Clock Oscillator It is very important that an appropriate clock oscillator be used in each ADC design Selection of the proper clock is aided by Analog Devices AN 501 Application Note AN 756 Application Note and Analog to Digital Converter Clock Optimization A Test Engineering Perspective and can be found at www analog com These application notes explain how to measure aperture jitter and how to specify a clock that meets the required phase noise or jitter specification Failure to properly specify a clock source will degrade SNR performance as shown in Figure 8 and Figure 9 As a reference a typical Wenzel clock oscillator has about 0 07 ps of aperture jitter whereas the CMOS clock oscillators have about 0 3 ps or more of aperture jitter S FETA Data Date 11 30 2005 Time 10 09 30 Temp 25 T 5 005 Mhe SNA 2413 SNAFS 7 2 UDSNR 31 3 si h sa snan 7383 Fund 1 979 atts et aae en a 17
37. om FIFO PORTB PORTD FIF CONTROL 9 USB 3 CONTROLLER gt SRE RISI asses SSRS PORTC PORTE S STANDARD USB 2 0 ONBOARD VOLTAGE REGULATORS JTAG CONNECTOR 05941 002 Figure 2 Typical HSC ADC EVALC Evaluation Platform Rev A Page 4 of 28 BACKGROUND GENERAL PURPOSE I O USB SPI CONTROL XILINX VIRTEX 4 FPGA 2 2 57 DEBUG PINS EXTERNAL SYNC AMM BEJ GR gt Mes 7718786 CYPRESS USB CONTROLLER USB CONNECTOR 10 R67 rx T oN oN c19 BE fifi OFF OFF ON DATA BUS mann Cot L 3 S 1 DATA BUS 2 N PLATFORM M2 MI MO BER R459 R4erm ARAF on Sonos bi Er n CONFIG 55 USB Hg I5 C FPGA JTAG CONNECTOR I FPGA LOAD 2 5VMGT SELECT aa 5 ON BOARD POWER SUPPLY 100MHz OSCILLATOR FPGA I O VOLTAGE MODE FPGA CONFIG PROM 5VDC POWER INPUT 05941 003 Figure 3 HSC ADC EVALC FPGA Based Data Capture Board ADIsimADC ADIsimADC is Analog Devices ADC behavioral modeling tool ADIsimADC accurately models many of the time and frequency domain errors common to ADCs This tool can be invaluable in terms of both simple converter selection and complete system simulation Although the tool is fully integrated into the VisualAnalog software to aid in simple converter selection it is also supported by several third party CAD vendors
38. ond 100 dBc harmonic rejection Rev A Page 6 of 28 It is also worth noting that 0 5 dB to 3 dB attenuator can be placed between the band pass and low pass series combination This helps to provide a better match between the two filters which are nominally specified at 50 When specifying filters request those made with large cores to prevent saturation Filters are typically designed for an input power of about 15 dBm In many cases however ADC drive requirements are much larger than this causing core saturation and distortion Specifying larger cores reduces the spurious distortion caused by core saturation Finally it is worth mentioning that filter connectors can also be specified Although adapters are easily found to convert between connector types using them introduces mismatches that can subtly affect converter performance While this may not be a problem with 8 bit and 10 bit converters it is quite noticeable with 12 14 and 16 bit converters ENCODE SIGNAL SOURCES For high performance converters stock signal generators usually are insufficient as encode sources because of both close in and wideband phase noise Fixed frequency oscillators are typically used for encode sources High performance crystal oscillators manufactured by Wenzel and Techtrol Cyclonetics Inc TCI can be used Wenzel s Sprinter and Ultra Low Noise series can offer optimum phase noise performance Another source of high quality enc
39. r of the fundamental frequency as determined by the FFT analysis is reduced by 3 dB A particular value of SFDR or SNR performance is not implied by this test FUNDAMENTAL LEVEL dB 0 1 2 3 4 5 6 7 8 3dB CUTOFF 315MHz 05941 017 50 100 150 200 250 300 350 400 450 500 FREQUENCY MHz Figure 18 Typical Full Power Bandwidth Response ROHDE amp SCHWARZ ADAPTER ANALOG BOONTON AGILENT ANALOG OUTPUT O Em INPUT VOLTMETER WENZEL XTAL ROHDE amp SCHWARZ DIFFERENTIAL ENCODE AGILENT OR 2 0 INPUT ADC FIFO BOARD STANDARDIZED 6V TO 9V SUPPLY SINGLE ENDED OR LAB SUPPLIES O INPUT AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES NOTES 1 AIN LEVELS SHOULD BE ADJUSTED FOR 1dB AT A 10MHz REFERENCE FREQUENCY 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog 6 BOONTON PROBES SHOULD USE UNTERMINATED ADAPTERS 05941 018 Figure 19 Full Power Bandwidth Test Setup Rev A Page 15 of 28 DITHER TESTING Applying extra noise to an ADC analog input causes dithering of the transfer function reducing the spurious caused by static nonlinearities While dither does little to reduce distortion cau
40. rsion Rate MSPS 21 Pipeline Delay CLK Cycles sse 22 Propagation Delay ns sse 23 Encode Pulse Width or Encode Duty Cycle 23 Conversion Error Rate CER eere 24 DG Test Definitions c ep ERU pier pices ts 25 Gain Error FS ccssssssssssssssessesssssssessceseesesesssssessesesseesesseseees 25 Gain Matching 96FS eerte 25 Offset Error 96 ES iuc cie citrate ei te e e E 25 Offset Matching MV u N u hasa 25 Temperature Drift ppm a 25 Voltage Output High Voltage Output Low V 25 Ibis M 25 Differential Nonlinearity Error DNL LSB 26 Missing Code zie ERE M 26 Integral Nonlinearity Error INL LSB 26 Power Supply Rejection Ratio PSRR dB Additional References a 28 Rev A Page 2 of 28 REVISION HISTORY 6 10 Rev 0 to Rev A Added Alex Arrants to 1 Changes to Dynamic Test Hardware Setup Section and Pig te usasqa ayayaw FERREUS 1 Changes to HSC ADC EVALC Evaluation Platform Section and Figure 2oy E VA VEER RES 4 Changes to Figure 3 ADIsimADC Section and Figure 4 5 Changes to Analog Signal Source Section Analog Signal Filter Section Figure 5 and Figure 6 sse 6 Changes to Enco
41. s reduced NPR falls off approximately 1 dB for each decibel reduction in noise power 86 0 81 16 BIT NPR 60 83dB NOTCH 18 0MHz 20 NOTCH WIDTH 3 0MHz TA 14 BIT a 40 66 5 61 A 60 12 BIT E 56 a gt 80 51 46 10 BIT ai E 36 5 120 5 30 25 20 15 10 0 0 5 10 15 20 25 30 20 log Vo N rms dBFS FREQUENCY MHz Figure 15 Typical NPR Curves Figure 16 Typical NPR Response for a 12 Bit Converter NOISE COM NC7108 NOISE GENERATOR nno 18MHz NOISE COM NOTCH FILTER TTE OR K amp L MICROWAVE ANTI ALIAS FILTER WENZEL XTAL ANALOG ROHDE amp SCHWARz DIFFERENTIAL ENCODE AGILENT OR 2 0 INPUT PEST SINGLE ENDED ADC FIFO BOARD STANDARDIZED 6V TO 9V OR LAB SUPPLIES AD92xx AD94xx OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR NOTES 1 SET NOISE COM TO 5dBm OR DECREMENT INCREMENT FOR APPROPRIATE NOISE INPUT LEVEL 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED 5 USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog 6 USE AN ADC FIFO BOARD WITH AT LEAST 64k 05941 016 Figure 17 NPR Test Setup Rev A Page 14 of 28 FULL POWER BANDWIDTH MHz Analog input bandwidth is the analog input frequency at which the spectral powe
42. sed by slew rate limitations it is very efficient at reducing localized errors that hinder ADC performance There are two types of dither out of band and wideband As shown in the setup in Figure 20 out of band dither is band limited noise placed out of band where it does not spectrally disrupt converter performance This technique is commonly used in communication systems where digital filters are used to select desired signals and filter out all others Wideband dither is often used in high performance test equipment In this configuration NOISE COM DNG7500 TTE OR K amp L NOISE GENERATOR MICROWAVE 1 5 2 1dB WENZEL XTAL ROHDE amp SCHWARZ TTE OR K amp L PAD AGILENT MICROWAVE WENZEL XTAL ROHDE amp SCHWARZ AGILENT DIFFERENTIAL R ENCODE SINGLE ENDED INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES O INPUT AD92xx AD94xx OR AD66xx EVALUATION BOARD wideband analog noise is added to the input and the digital equivalent is subtracted from the output The net effect of either technique is that spurious performance of the converter is greatly enhanced For more details see the AN 410 Application Note at www analog com It is common for spurious performance to improve by 15 dB or more when dither is used depending on the application Many data sheets include dithered performance plots for comparison In addition using the VisualAnalog software with the ADIsimADC allows dither to be added to the
43. simulation further demonstrating how dither will improve performance ANALOG INPUT ADC FIFO BOARD SUPPLY INPUT STANDARDIZED 6V TO 9V MONITOR SOAM Due 03163005 Tie ETE Tae 15 NOTES OR LAB SUPPLIES PC USB 1 AIN LEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED 2 ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE 3 UNLESS ONBOARD REGULATORS ARE USED SUPPLIES SHOULD BE AT NOMINAL 4 5 6 7 TEMPERATURE SHOULD BE AT AMBIENT UNLESS OTHERWISE NOTED USE THE APPROPRIATE CONFIGURATION FILE FOR VisualAnalog ADJUST DC BINS TO EXCLUDE DITHER USE AN ADC FIFO BOARD WITH AT LEAST 64k ADJUST NOISE COM DITHER LEVEL FOR MAXIMUM SFDR PERFORMANCE Figure 20 Dither Test Setup Rev A Page 16 of 28 05941 019 ANALOG INPUT Analog Input Impedance It is the ratio of the complex input voltage divided by the complex input current for the analog input Analog input impedance is typically measured with a network analyzer and displayed on a Smith chart In some instances the complex input can be broken down into resistive capacitive or inductive terms and reported as such Voltage Standing Wave Ratio VSWR VSWR is a measure of the amount of power that is reflected back from the input of the ADC This is a measure of the efficiency of the transfer of energy to the input port of the ADC ENAS5071B NETWORK ANALYZER WENZEL XTAL ROHDE amp SCHWARZ suas AGIEENT SING
44. sion 1 0 User Manual at www analog com Noise floor is equivalent to FFT Bins Noise Floor SNRFS 10 log 3 This is an indication of the average noise in each FFT bin If the size of the FFT is doubled this number decreases by 3 dB Noise floor does not provide an absolute measurement but instead gives a relative indication of where the noise is for a given setup Effective Number of Bits ENOB Bits ENOB provides a measure of the performance of the ADC that is expressed in bits ENOB is most accurately measured using a sine wave curve fit method The most common method for computing ENOB is to use the following equation based on the SINAD at the full scale of the converter SINAD 1 76 6 02 ENOB Spurious Free Dynamic Range SFDR dBc The SFDR is the ratio of the rms value of the signal to the rms value of the peak spurious spectral component for the analog input that produces the worst result In most cases SFDR is a harmonic of the input signal applied to the ADC Harmonic Distortion dBc or dBFS A harmonic is a spectral component that is an integer multiple of the driven analog input frequency For example the frequency of the second harmonic is twice the analog input Most ADCs have specifications for one or more harmonics Typically the second and third harmonics are singled out because they have the worst performance of all the harmonics Harmonic distortion no matter the order is the ratio of t
45. t the integration limits of the noise over a user definable span of frequencies See the AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual at www analog com for details on FFT analysis It is the ratio of the rms signal amplitude to the rms sum of all spectral components except the first six harmonics and dc within the specified band set by the user UDSNR is reported in decibels Noise Figure NF dB The NF is the ratio of the noise power at the output of a device to the noise power at the input to the device where the input noise temperature is equal to the reference temperature 298 K The noise figure is expressed in decibels The NF of an ADC can be computed for a single configuration Assuming that the input range termination and sample rate are fixed the noise figure for an ADC can be calculated using the following equation 2 m 10xlog 778 21 _ SNRFS Noise Figure 0 001 Encode F ncode ae EA where V rms rms full scale input voltage Zin ADC input impedance or input network and ADC input impedance SNRFS full scale ADC SNR Encode Frequency ADC clock rate k Boltzman s constant 1 38 x 10 T temperature in Kelvin 298 K B bandwidth of interest Hz Rev A Page 9 of 28 Noise Floor dBFS Noise floor is a term used in VisualAnalog software see the AN 905 Application Note VisualAnalog Converter Evaluation Tool Ver
46. tate such clocking Devices such as the AD9516 are ideal for clock cleanup and distribution as shown in Figure 10 The additive jitter of the AD9516 is about 0 22 ps and the device is optimized for driving ADCs DACs and various logic devices i AND MONITOR SWITCHOVER gt pie ver ours O OUT2 ovo LvPECL to ours Q OUT4 7 ours ane sas 9 OUT6 OUT7 Have Hoe russo P Gis gt ours SERIAL CONTROL PORT lt _ AND DIGITAL LOGIC AD9516 0 05941 010 Figure 10 AD9516 Low Jitter Clock Source POWER SUPPLIES Power supplies for ADCs are very important Therefore it is important to provide clean quiet power supplies because most ADCs can modulate excessive noise on these input bias pins To fully understand how an ADC performs with a certain amount of noise on these pins the power supply rejection ratios of all the supplies should be measured and understood over the frequency band of interest While switching regulators are fine for many applications some examples include the ADP5020 ADP2108 and the ADP2114 However linear regulators often provide a quieter higher performance solution Devices such as the ADP3338 ADP3339 see Figure 11 and ADP1706 ADP1707 ADP1708 see Figure 12 series provide very low noise and well regulated sources and they are suitable for most
47. tions as well Although such waveforms are not uniform they can be accurately described mathematically see The Data Conversion Handbook Walt Kester Newness 2005 Page 315 Typical histogram tests are performed by taking as large a number of samples as is reasonable For high resolution converters this may be 4 million samples or more Rev A Page 25 of 28 Differential Nonlinearity Error DNL LSB Integral Nonlinearity Error INL LSB DNL is the variation of any code from an ideal 1 LSB step INL is the deviation of the transfer function from a reference This is measured by examining each of the histogram bins line measured in fractions of 1 LSB using a best straight line and comparing the actual probability of occurrence to the determined by a least mean squared curve fit This is measured ideal probability This results in a direct measure of DNL by integrating the histogram to form a transfer function and for each code then performing the linear regression on this function The difference between the actual transfer function and this best fit ONLA Cate 02 04 2008 Tine 16 09 17 Tep 25 C oie line j the INL tva Cabe 02 04 2008 Tins 16 69 17 Tempe 25 Jo 05941 027 ii Figure 30 Typical 10 Bit DNL eid 05941 028 Missing Code Figure 31 Typical 10 Bit INL code is said to be missing if the DNL for that code is 1 LSB A missing code is defined as a missing qua
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